2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <linux/module.h>
30 #include <linux/pm_runtime.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_fourcc.h>
34 #include <drm/drm_plane_helper.h>
36 #include "display/intel_atomic.h"
37 #include "display/intel_fbc.h"
38 #include "display/intel_sprite.h"
42 #include "intel_drv.h"
44 #include "intel_sideband.h"
45 #include "../../../platform/x86/intel_ips.h"
50 * RC6 is a special power stage which allows the GPU to enter an very
51 * low-voltage mode when idle, using down to 0V while at this stage. This
52 * stage is entered automatically when the GPU is idle when RC6 support is
53 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
55 * There are different RC6 modes available in Intel GPU, which differentiate
56 * among each other with the latency required to enter and leave RC6 and
57 * voltage consumed by the GPU in different states.
59 * The combination of the following flags define which states GPU is allowed
60 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
61 * RC6pp is deepest RC6. Their support by hardware varies according to the
62 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
63 * which brings the most power savings; deeper states save more power, but
64 * require higher latency to switch to and wake up.
67 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
69 if (HAS_LLC(dev_priv)) {
71 * WaCompressedResourceDisplayNewHashMode:skl,kbl
72 * Display WA #0390: skl,kbl
74 * Must match Sampler, Pixel Back End, and Media. See
75 * WaCompressedResourceSamplerPbeMediaNewHashMode.
77 I915_WRITE(CHICKEN_PAR1_1,
78 I915_READ(CHICKEN_PAR1_1) |
79 SKL_DE_COMPRESSED_HASH_MODE);
82 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
83 I915_WRITE(CHICKEN_PAR1_1,
84 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
86 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
87 I915_WRITE(GEN8_CHICKEN_DCPR_1,
88 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
90 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
91 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
92 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
94 DISP_FBC_MEMORY_WAKE);
96 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
97 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
98 ILK_DPFC_DISABLE_DUMMY0);
100 if (IS_SKYLAKE(dev_priv)) {
101 /* WaDisableDopClockGating */
102 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
103 & ~GEN7_DOP_CLOCK_GATE_ENABLE);
107 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
109 gen9_init_clock_gating(dev_priv);
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
117 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
119 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
120 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
123 * Wa: Backlight PWM may stop in the asserted state, causing backlight
126 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
127 PWM1_GATING_DIS | PWM2_GATING_DIS);
130 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
132 gen9_init_clock_gating(dev_priv);
135 * WaDisablePWMClockGating:glk
136 * Backlight PWM may stop in the asserted state, causing backlight
139 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
140 PWM1_GATING_DIS | PWM2_GATING_DIS);
142 /* WaDDIIOTimeout:glk */
143 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
144 u32 val = I915_READ(CHICKEN_MISC_2);
145 val &= ~(GLK_CL0_PWR_DOWN |
148 I915_WRITE(CHICKEN_MISC_2, val);
153 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
157 tmp = I915_READ(CLKCFG);
159 switch (tmp & CLKCFG_FSB_MASK) {
161 dev_priv->fsb_freq = 533; /* 133*4 */
164 dev_priv->fsb_freq = 800; /* 200*4 */
167 dev_priv->fsb_freq = 667; /* 167*4 */
170 dev_priv->fsb_freq = 400; /* 100*4 */
174 switch (tmp & CLKCFG_MEM_MASK) {
176 dev_priv->mem_freq = 533;
179 dev_priv->mem_freq = 667;
182 dev_priv->mem_freq = 800;
186 /* detect pineview DDR3 setting */
187 tmp = I915_READ(CSHRDDR3CTL);
188 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
191 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
195 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
196 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
198 switch (ddrpll & 0xff) {
200 dev_priv->mem_freq = 800;
203 dev_priv->mem_freq = 1066;
206 dev_priv->mem_freq = 1333;
209 dev_priv->mem_freq = 1600;
212 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
214 dev_priv->mem_freq = 0;
218 dev_priv->ips.r_t = dev_priv->mem_freq;
220 switch (csipll & 0x3ff) {
222 dev_priv->fsb_freq = 3200;
225 dev_priv->fsb_freq = 3733;
228 dev_priv->fsb_freq = 4266;
231 dev_priv->fsb_freq = 4800;
234 dev_priv->fsb_freq = 5333;
237 dev_priv->fsb_freq = 5866;
240 dev_priv->fsb_freq = 6400;
243 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
245 dev_priv->fsb_freq = 0;
249 if (dev_priv->fsb_freq == 3200) {
250 dev_priv->ips.c_m = 0;
251 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
252 dev_priv->ips.c_m = 1;
254 dev_priv->ips.c_m = 2;
258 static const struct cxsr_latency cxsr_latency_table[] = {
259 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
260 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
261 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
262 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
263 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
265 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
266 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
267 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
268 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
269 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
271 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
272 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
273 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
274 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
275 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
277 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
278 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
279 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
280 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
281 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
283 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
284 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
285 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
286 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
287 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
289 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
290 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
291 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
292 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
293 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
296 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
301 const struct cxsr_latency *latency;
304 if (fsb == 0 || mem == 0)
307 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
308 latency = &cxsr_latency_table[i];
309 if (is_desktop == latency->is_desktop &&
310 is_ddr3 == latency->is_ddr3 &&
311 fsb == latency->fsb_freq && mem == latency->mem_freq)
315 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
320 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
324 vlv_punit_get(dev_priv);
326 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
328 val &= ~FORCE_DDR_HIGH_FREQ;
330 val |= FORCE_DDR_HIGH_FREQ;
331 val &= ~FORCE_DDR_LOW_FREQ;
332 val |= FORCE_DDR_FREQ_REQ_ACK;
333 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
335 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
336 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
337 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
339 vlv_punit_put(dev_priv);
342 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
346 vlv_punit_get(dev_priv);
348 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
350 val |= DSP_MAXFIFO_PM5_ENABLE;
352 val &= ~DSP_MAXFIFO_PM5_ENABLE;
353 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
355 vlv_punit_put(dev_priv);
358 #define FW_WM(value, plane) \
359 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
361 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
366 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
367 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
368 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
369 POSTING_READ(FW_BLC_SELF_VLV);
370 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
371 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
372 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
373 POSTING_READ(FW_BLC_SELF);
374 } else if (IS_PINEVIEW(dev_priv)) {
375 val = I915_READ(DSPFW3);
376 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
378 val |= PINEVIEW_SELF_REFRESH_EN;
380 val &= ~PINEVIEW_SELF_REFRESH_EN;
381 I915_WRITE(DSPFW3, val);
382 POSTING_READ(DSPFW3);
383 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
384 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
385 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
386 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
387 I915_WRITE(FW_BLC_SELF, val);
388 POSTING_READ(FW_BLC_SELF);
389 } else if (IS_I915GM(dev_priv)) {
391 * FIXME can't find a bit like this for 915G, and
392 * and yet it does have the related watermark in
393 * FW_BLC_SELF. What's going on?
395 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
396 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
397 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
398 I915_WRITE(INSTPM, val);
399 POSTING_READ(INSTPM);
404 trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
406 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
407 enableddisabled(enable),
408 enableddisabled(was_enabled));
414 * intel_set_memory_cxsr - Configure CxSR state
415 * @dev_priv: i915 device
416 * @enable: Allow vs. disallow CxSR
418 * Allow or disallow the system to enter a special CxSR
419 * (C-state self refresh) state. What typically happens in CxSR mode
420 * is that several display FIFOs may get combined into a single larger
421 * FIFO for a particular plane (so called max FIFO mode) to allow the
422 * system to defer memory fetches longer, and the memory will enter
425 * Note that enabling CxSR does not guarantee that the system enter
426 * this special mode, nor does it guarantee that the system stays
427 * in that mode once entered. So this just allows/disallows the system
428 * to autonomously utilize the CxSR mode. Other factors such as core
429 * C-states will affect when/if the system actually enters/exits the
432 * Note that on VLV/CHV this actually only controls the max FIFO mode,
433 * and the system is free to enter/exit memory self refresh at any time
434 * even when the use of CxSR has been disallowed.
436 * While the system is actually in the CxSR/max FIFO mode, some plane
437 * control registers will not get latched on vblank. Thus in order to
438 * guarantee the system will respond to changes in the plane registers
439 * we must always disallow CxSR prior to making changes to those registers.
440 * Unfortunately the system will re-evaluate the CxSR conditions at
441 * frame start which happens after vblank start (which is when the plane
442 * registers would get latched), so we can't proceed with the plane update
443 * during the same frame where we disallowed CxSR.
445 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
446 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
447 * the hardware w.r.t. HPLL SR when writing to plane registers.
448 * Disallowing just CxSR is sufficient.
450 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
454 mutex_lock(&dev_priv->wm.wm_mutex);
455 ret = _intel_set_memory_cxsr(dev_priv, enable);
456 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
457 dev_priv->wm.vlv.cxsr = enable;
458 else if (IS_G4X(dev_priv))
459 dev_priv->wm.g4x.cxsr = enable;
460 mutex_unlock(&dev_priv->wm.wm_mutex);
466 * Latency for FIFO fetches is dependent on several factors:
467 * - memory configuration (speed, channels)
469 * - current MCH state
470 * It can be fairly high in some situations, so here we assume a fairly
471 * pessimal value. It's a tradeoff between extra memory fetches (if we
472 * set this value too high, the FIFO will fetch frequently to stay full)
473 * and power consumption (set it too low to save power and we might see
474 * FIFO underruns and display "flicker").
476 * A value of 5us seems to be a good balance; safe for very low end
477 * platforms but not overly aggressive on lower latency configs.
479 static const int pessimal_latency_ns = 5000;
481 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
482 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
484 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
486 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
488 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
489 enum pipe pipe = crtc->pipe;
490 int sprite0_start, sprite1_start;
493 u32 dsparb, dsparb2, dsparb3;
495 dsparb = I915_READ(DSPARB);
496 dsparb2 = I915_READ(DSPARB2);
497 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
498 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
501 dsparb = I915_READ(DSPARB);
502 dsparb2 = I915_READ(DSPARB2);
503 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
504 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
507 dsparb2 = I915_READ(DSPARB2);
508 dsparb3 = I915_READ(DSPARB3);
509 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
510 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
517 fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
518 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
519 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
520 fifo_state->plane[PLANE_CURSOR] = 63;
523 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
524 enum i9xx_plane_id i9xx_plane)
526 u32 dsparb = I915_READ(DSPARB);
529 size = dsparb & 0x7f;
530 if (i9xx_plane == PLANE_B)
531 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
533 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
534 dsparb, plane_name(i9xx_plane), size);
539 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
540 enum i9xx_plane_id i9xx_plane)
542 u32 dsparb = I915_READ(DSPARB);
545 size = dsparb & 0x1ff;
546 if (i9xx_plane == PLANE_B)
547 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
548 size >>= 1; /* Convert to cachelines */
550 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
551 dsparb, plane_name(i9xx_plane), size);
556 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
557 enum i9xx_plane_id i9xx_plane)
559 u32 dsparb = I915_READ(DSPARB);
562 size = dsparb & 0x7f;
563 size >>= 2; /* Convert to cachelines */
565 DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n",
566 dsparb, plane_name(i9xx_plane), size);
571 /* Pineview has different values for various configs */
572 static const struct intel_watermark_params pineview_display_wm = {
573 .fifo_size = PINEVIEW_DISPLAY_FIFO,
574 .max_wm = PINEVIEW_MAX_WM,
575 .default_wm = PINEVIEW_DFT_WM,
576 .guard_size = PINEVIEW_GUARD_WM,
577 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
579 static const struct intel_watermark_params pineview_display_hplloff_wm = {
580 .fifo_size = PINEVIEW_DISPLAY_FIFO,
581 .max_wm = PINEVIEW_MAX_WM,
582 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
583 .guard_size = PINEVIEW_GUARD_WM,
584 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
586 static const struct intel_watermark_params pineview_cursor_wm = {
587 .fifo_size = PINEVIEW_CURSOR_FIFO,
588 .max_wm = PINEVIEW_CURSOR_MAX_WM,
589 .default_wm = PINEVIEW_CURSOR_DFT_WM,
590 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
591 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
593 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
594 .fifo_size = PINEVIEW_CURSOR_FIFO,
595 .max_wm = PINEVIEW_CURSOR_MAX_WM,
596 .default_wm = PINEVIEW_CURSOR_DFT_WM,
597 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
598 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
600 static const struct intel_watermark_params i965_cursor_wm_info = {
601 .fifo_size = I965_CURSOR_FIFO,
602 .max_wm = I965_CURSOR_MAX_WM,
603 .default_wm = I965_CURSOR_DFT_WM,
605 .cacheline_size = I915_FIFO_LINE_SIZE,
607 static const struct intel_watermark_params i945_wm_info = {
608 .fifo_size = I945_FIFO_SIZE,
609 .max_wm = I915_MAX_WM,
612 .cacheline_size = I915_FIFO_LINE_SIZE,
614 static const struct intel_watermark_params i915_wm_info = {
615 .fifo_size = I915_FIFO_SIZE,
616 .max_wm = I915_MAX_WM,
619 .cacheline_size = I915_FIFO_LINE_SIZE,
621 static const struct intel_watermark_params i830_a_wm_info = {
622 .fifo_size = I855GM_FIFO_SIZE,
623 .max_wm = I915_MAX_WM,
626 .cacheline_size = I830_FIFO_LINE_SIZE,
628 static const struct intel_watermark_params i830_bc_wm_info = {
629 .fifo_size = I855GM_FIFO_SIZE,
630 .max_wm = I915_MAX_WM/2,
633 .cacheline_size = I830_FIFO_LINE_SIZE,
635 static const struct intel_watermark_params i845_wm_info = {
636 .fifo_size = I830_FIFO_SIZE,
637 .max_wm = I915_MAX_WM,
640 .cacheline_size = I830_FIFO_LINE_SIZE,
644 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
645 * @pixel_rate: Pipe pixel rate in kHz
646 * @cpp: Plane bytes per pixel
647 * @latency: Memory wakeup latency in 0.1us units
649 * Compute the watermark using the method 1 or "small buffer"
650 * formula. The caller may additonally add extra cachelines
651 * to account for TLB misses and clock crossings.
653 * This method is concerned with the short term drain rate
654 * of the FIFO, ie. it does not account for blanking periods
655 * which would effectively reduce the average drain rate across
656 * a longer period. The name "small" refers to the fact the
657 * FIFO is relatively small compared to the amount of data
660 * The FIFO level vs. time graph might look something like:
664 * __---__---__ (- plane active, _ blanking)
667 * or perhaps like this:
670 * __----__----__ (- plane active, _ blanking)
674 * The watermark in bytes
676 static unsigned int intel_wm_method1(unsigned int pixel_rate,
678 unsigned int latency)
682 ret = mul_u32_u32(pixel_rate, cpp * latency);
683 ret = DIV_ROUND_UP_ULL(ret, 10000);
689 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
690 * @pixel_rate: Pipe pixel rate in kHz
691 * @htotal: Pipe horizontal total
692 * @width: Plane width in pixels
693 * @cpp: Plane bytes per pixel
694 * @latency: Memory wakeup latency in 0.1us units
696 * Compute the watermark using the method 2 or "large buffer"
697 * formula. The caller may additonally add extra cachelines
698 * to account for TLB misses and clock crossings.
700 * This method is concerned with the long term drain rate
701 * of the FIFO, ie. it does account for blanking periods
702 * which effectively reduce the average drain rate across
703 * a longer period. The name "large" refers to the fact the
704 * FIFO is relatively large compared to the amount of data
707 * The FIFO level vs. time graph might look something like:
712 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
716 * The watermark in bytes
718 static unsigned int intel_wm_method2(unsigned int pixel_rate,
722 unsigned int latency)
727 * FIXME remove once all users are computing
728 * watermarks in the correct place.
730 if (WARN_ON_ONCE(htotal == 0))
733 ret = (latency * pixel_rate) / (htotal * 10000);
734 ret = (ret + 1) * width * cpp;
740 * intel_calculate_wm - calculate watermark level
741 * @pixel_rate: pixel clock
742 * @wm: chip FIFO params
743 * @fifo_size: size of the FIFO buffer
744 * @cpp: bytes per pixel
745 * @latency_ns: memory latency for the platform
747 * Calculate the watermark level (the level at which the display plane will
748 * start fetching from memory again). Each chip has a different display
749 * FIFO size and allocation, so the caller needs to figure that out and pass
750 * in the correct intel_watermark_params structure.
752 * As the pixel clock runs, the FIFO will be drained at a rate that depends
753 * on the pixel size. When it reaches the watermark level, it'll start
754 * fetching FIFO line sized based chunks from memory until the FIFO fills
755 * past the watermark point. If the FIFO drains completely, a FIFO underrun
756 * will occur, and a display engine hang could result.
758 static unsigned int intel_calculate_wm(int pixel_rate,
759 const struct intel_watermark_params *wm,
760 int fifo_size, int cpp,
761 unsigned int latency_ns)
763 int entries, wm_size;
766 * Note: we need to make sure we don't overflow for various clock &
768 * clocks go from a few thousand to several hundred thousand.
769 * latency is usually a few thousand
771 entries = intel_wm_method1(pixel_rate, cpp,
773 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
775 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
777 wm_size = fifo_size - entries;
778 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
780 /* Don't promote wm_size to unsigned... */
781 if (wm_size > wm->max_wm)
782 wm_size = wm->max_wm;
784 wm_size = wm->default_wm;
787 * Bspec seems to indicate that the value shouldn't be lower than
788 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
789 * Lets go for 8 which is the burst size since certain platforms
790 * already use a hardcoded 8 (which is what the spec says should be
799 static bool is_disabling(int old, int new, int threshold)
801 return old >= threshold && new < threshold;
804 static bool is_enabling(int old, int new, int threshold)
806 return old < threshold && new >= threshold;
809 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
811 return dev_priv->wm.max_level + 1;
814 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
815 const struct intel_plane_state *plane_state)
817 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
819 /* FIXME check the 'enable' instead */
820 if (!crtc_state->base.active)
824 * Treat cursor with fb as always visible since cursor updates
825 * can happen faster than the vrefresh rate, and the current
826 * watermark code doesn't handle that correctly. Cursor updates
827 * which set/clear the fb or change the cursor size are going
828 * to get throttled by intel_legacy_cursor_update() to work
829 * around this problem with the watermark code.
831 if (plane->id == PLANE_CURSOR)
832 return plane_state->base.fb != NULL;
834 return plane_state->base.visible;
837 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
839 struct intel_crtc *crtc, *enabled = NULL;
841 for_each_intel_crtc(&dev_priv->drm, crtc) {
842 if (intel_crtc_active(crtc)) {
852 static void pineview_update_wm(struct intel_crtc *unused_crtc)
854 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
855 struct intel_crtc *crtc;
856 const struct cxsr_latency *latency;
860 latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
865 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
866 intel_set_memory_cxsr(dev_priv, false);
870 crtc = single_enabled_crtc(dev_priv);
872 const struct drm_display_mode *adjusted_mode =
873 &crtc->config->base.adjusted_mode;
874 const struct drm_framebuffer *fb =
875 crtc->base.primary->state->fb;
876 int cpp = fb->format->cpp[0];
877 int clock = adjusted_mode->crtc_clock;
880 wm = intel_calculate_wm(clock, &pineview_display_wm,
881 pineview_display_wm.fifo_size,
882 cpp, latency->display_sr);
883 reg = I915_READ(DSPFW1);
884 reg &= ~DSPFW_SR_MASK;
885 reg |= FW_WM(wm, SR);
886 I915_WRITE(DSPFW1, reg);
887 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
890 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
891 pineview_display_wm.fifo_size,
892 4, latency->cursor_sr);
893 reg = I915_READ(DSPFW3);
894 reg &= ~DSPFW_CURSOR_SR_MASK;
895 reg |= FW_WM(wm, CURSOR_SR);
896 I915_WRITE(DSPFW3, reg);
898 /* Display HPLL off SR */
899 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
900 pineview_display_hplloff_wm.fifo_size,
901 cpp, latency->display_hpll_disable);
902 reg = I915_READ(DSPFW3);
903 reg &= ~DSPFW_HPLL_SR_MASK;
904 reg |= FW_WM(wm, HPLL_SR);
905 I915_WRITE(DSPFW3, reg);
907 /* cursor HPLL off SR */
908 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
909 pineview_display_hplloff_wm.fifo_size,
910 4, latency->cursor_hpll_disable);
911 reg = I915_READ(DSPFW3);
912 reg &= ~DSPFW_HPLL_CURSOR_MASK;
913 reg |= FW_WM(wm, HPLL_CURSOR);
914 I915_WRITE(DSPFW3, reg);
915 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
917 intel_set_memory_cxsr(dev_priv, true);
919 intel_set_memory_cxsr(dev_priv, false);
924 * Documentation says:
925 * "If the line size is small, the TLB fetches can get in the way of the
926 * data fetches, causing some lag in the pixel data return which is not
927 * accounted for in the above formulas. The following adjustment only
928 * needs to be applied if eight whole lines fit in the buffer at once.
929 * The WM is adjusted upwards by the difference between the FIFO size
930 * and the size of 8 whole lines. This adjustment is always performed
931 * in the actual pixel depth regardless of whether FBC is enabled or not."
933 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
935 int tlb_miss = fifo_size * 64 - width * cpp * 8;
937 return max(0, tlb_miss);
940 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
941 const struct g4x_wm_values *wm)
945 for_each_pipe(dev_priv, pipe)
946 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
949 FW_WM(wm->sr.plane, SR) |
950 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
951 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
952 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
954 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
955 FW_WM(wm->sr.fbc, FBC_SR) |
956 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
957 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
958 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
959 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
961 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
962 FW_WM(wm->sr.cursor, CURSOR_SR) |
963 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
964 FW_WM(wm->hpll.plane, HPLL_SR));
966 POSTING_READ(DSPFW1);
969 #define FW_WM_VLV(value, plane) \
970 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
972 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
973 const struct vlv_wm_values *wm)
977 for_each_pipe(dev_priv, pipe) {
978 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
980 I915_WRITE(VLV_DDL(pipe),
981 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
982 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
983 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
984 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
988 * Zero the (unused) WM1 watermarks, and also clear all the
989 * high order bits so that there are no out of bounds values
990 * present in the registers during the reprogramming.
992 I915_WRITE(DSPHOWM, 0);
993 I915_WRITE(DSPHOWM1, 0);
994 I915_WRITE(DSPFW4, 0);
995 I915_WRITE(DSPFW5, 0);
996 I915_WRITE(DSPFW6, 0);
999 FW_WM(wm->sr.plane, SR) |
1000 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1001 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1002 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1004 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1005 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1006 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1008 FW_WM(wm->sr.cursor, CURSOR_SR));
1010 if (IS_CHERRYVIEW(dev_priv)) {
1011 I915_WRITE(DSPFW7_CHV,
1012 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1013 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1014 I915_WRITE(DSPFW8_CHV,
1015 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1016 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1017 I915_WRITE(DSPFW9_CHV,
1018 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1019 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1021 FW_WM(wm->sr.plane >> 9, SR_HI) |
1022 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1023 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1024 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1025 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1026 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1027 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1028 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1029 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1030 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1033 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1034 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1036 FW_WM(wm->sr.plane >> 9, SR_HI) |
1037 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1038 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1039 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1040 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1041 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1042 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1045 POSTING_READ(DSPFW1);
1050 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1052 /* all latencies in usec */
1053 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1054 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1055 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1057 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1060 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1063 * DSPCNTR[13] supposedly controls whether the
1064 * primary plane can use the FIFO space otherwise
1065 * reserved for the sprite plane. It's not 100% clear
1066 * what the actual FIFO size is, but it looks like we
1067 * can happily set both primary and sprite watermarks
1068 * up to 127 cachelines. So that would seem to mean
1069 * that either DSPCNTR[13] doesn't do anything, or that
1070 * the total FIFO is >= 256 cachelines in size. Either
1071 * way, we don't seem to have to worry about this
1072 * repartitioning as the maximum watermark value the
1073 * register can hold for each plane is lower than the
1074 * minimum FIFO size.
1080 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1082 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1084 MISSING_CASE(plane_id);
1089 static int g4x_fbc_fifo_size(int level)
1092 case G4X_WM_LEVEL_SR:
1094 case G4X_WM_LEVEL_HPLL:
1097 MISSING_CASE(level);
1102 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1103 const struct intel_plane_state *plane_state,
1106 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1107 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1108 const struct drm_display_mode *adjusted_mode =
1109 &crtc_state->base.adjusted_mode;
1110 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1111 unsigned int clock, htotal, cpp, width, wm;
1116 if (!intel_wm_plane_visible(crtc_state, plane_state))
1119 cpp = plane_state->base.fb->format->cpp[0];
1122 * Not 100% sure which way ELK should go here as the
1123 * spec only says CL/CTG should assume 32bpp and BW
1124 * doesn't need to. But as these things followed the
1125 * mobile vs. desktop lines on gen3 as well, let's
1126 * assume ELK doesn't need this.
1128 * The spec also fails to list such a restriction for
1129 * the HPLL watermark, which seems a little strange.
1130 * Let's use 32bpp for the HPLL watermark as well.
1132 if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1133 level != G4X_WM_LEVEL_NORMAL)
1136 clock = adjusted_mode->crtc_clock;
1137 htotal = adjusted_mode->crtc_htotal;
1139 if (plane->id == PLANE_CURSOR)
1140 width = plane_state->base.crtc_w;
1142 width = drm_rect_width(&plane_state->base.dst);
1144 if (plane->id == PLANE_CURSOR) {
1145 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1146 } else if (plane->id == PLANE_PRIMARY &&
1147 level == G4X_WM_LEVEL_NORMAL) {
1148 wm = intel_wm_method1(clock, cpp, latency);
1150 unsigned int small, large;
1152 small = intel_wm_method1(clock, cpp, latency);
1153 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1155 wm = min(small, large);
1158 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1161 wm = DIV_ROUND_UP(wm, 64) + 2;
1163 return min_t(unsigned int, wm, USHRT_MAX);
1166 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1167 int level, enum plane_id plane_id, u16 value)
1169 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1172 for (; level < intel_wm_num_levels(dev_priv); level++) {
1173 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1175 dirty |= raw->plane[plane_id] != value;
1176 raw->plane[plane_id] = value;
1182 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1183 int level, u16 value)
1185 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1188 /* NORMAL level doesn't have an FBC watermark */
1189 level = max(level, G4X_WM_LEVEL_SR);
1191 for (; level < intel_wm_num_levels(dev_priv); level++) {
1192 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1194 dirty |= raw->fbc != value;
1201 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1202 const struct intel_plane_state *plane_state,
1205 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1206 const struct intel_plane_state *plane_state)
1208 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1209 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1210 enum plane_id plane_id = plane->id;
1214 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1215 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1216 if (plane_id == PLANE_PRIMARY)
1217 dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1221 for (level = 0; level < num_levels; level++) {
1222 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1225 wm = g4x_compute_wm(crtc_state, plane_state, level);
1226 max_wm = g4x_plane_fifo_size(plane_id, level);
1231 dirty |= raw->plane[plane_id] != wm;
1232 raw->plane[plane_id] = wm;
1234 if (plane_id != PLANE_PRIMARY ||
1235 level == G4X_WM_LEVEL_NORMAL)
1238 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1239 raw->plane[plane_id]);
1240 max_wm = g4x_fbc_fifo_size(level);
1243 * FBC wm is not mandatory as we
1244 * can always just disable its use.
1249 dirty |= raw->fbc != wm;
1253 /* mark watermarks as invalid */
1254 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1256 if (plane_id == PLANE_PRIMARY)
1257 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1261 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1263 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1264 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1265 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1267 if (plane_id == PLANE_PRIMARY)
1268 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1269 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1270 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1276 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1277 enum plane_id plane_id, int level)
1279 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1281 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1284 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1287 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1289 if (level > dev_priv->wm.max_level)
1292 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1293 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1294 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1297 /* mark all levels starting from 'level' as invalid */
1298 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1299 struct g4x_wm_state *wm_state, int level)
1301 if (level <= G4X_WM_LEVEL_NORMAL) {
1302 enum plane_id plane_id;
1304 for_each_plane_id_on_crtc(crtc, plane_id)
1305 wm_state->wm.plane[plane_id] = USHRT_MAX;
1308 if (level <= G4X_WM_LEVEL_SR) {
1309 wm_state->cxsr = false;
1310 wm_state->sr.cursor = USHRT_MAX;
1311 wm_state->sr.plane = USHRT_MAX;
1312 wm_state->sr.fbc = USHRT_MAX;
1315 if (level <= G4X_WM_LEVEL_HPLL) {
1316 wm_state->hpll_en = false;
1317 wm_state->hpll.cursor = USHRT_MAX;
1318 wm_state->hpll.plane = USHRT_MAX;
1319 wm_state->hpll.fbc = USHRT_MAX;
1323 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1326 struct intel_atomic_state *state =
1327 to_intel_atomic_state(crtc_state->base.state);
1328 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1329 int num_active_planes = hweight32(crtc_state->active_planes &
1330 ~BIT(PLANE_CURSOR));
1331 const struct g4x_pipe_wm *raw;
1332 const struct intel_plane_state *old_plane_state;
1333 const struct intel_plane_state *new_plane_state;
1334 struct intel_plane *plane;
1335 enum plane_id plane_id;
1337 unsigned int dirty = 0;
1339 for_each_oldnew_intel_plane_in_state(state, plane,
1341 new_plane_state, i) {
1342 if (new_plane_state->base.crtc != &crtc->base &&
1343 old_plane_state->base.crtc != &crtc->base)
1346 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1347 dirty |= BIT(plane->id);
1353 level = G4X_WM_LEVEL_NORMAL;
1354 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1357 raw = &crtc_state->wm.g4x.raw[level];
1358 for_each_plane_id_on_crtc(crtc, plane_id)
1359 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1361 level = G4X_WM_LEVEL_SR;
1363 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1366 raw = &crtc_state->wm.g4x.raw[level];
1367 wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1368 wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1369 wm_state->sr.fbc = raw->fbc;
1371 wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1373 level = G4X_WM_LEVEL_HPLL;
1375 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1378 raw = &crtc_state->wm.g4x.raw[level];
1379 wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1380 wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1381 wm_state->hpll.fbc = raw->fbc;
1383 wm_state->hpll_en = wm_state->cxsr;
1388 if (level == G4X_WM_LEVEL_NORMAL)
1391 /* invalidate the higher levels */
1392 g4x_invalidate_wms(crtc, wm_state, level);
1395 * Determine if the FBC watermark(s) can be used. IF
1396 * this isn't the case we prefer to disable the FBC
1397 ( watermark(s) rather than disable the SR/HPLL
1398 * level(s) entirely.
1400 wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1402 if (level >= G4X_WM_LEVEL_SR &&
1403 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1404 wm_state->fbc_en = false;
1405 else if (level >= G4X_WM_LEVEL_HPLL &&
1406 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1407 wm_state->fbc_en = false;
1412 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
1414 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1415 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1416 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1417 struct intel_atomic_state *intel_state =
1418 to_intel_atomic_state(new_crtc_state->base.state);
1419 const struct intel_crtc_state *old_crtc_state =
1420 intel_atomic_get_old_crtc_state(intel_state, crtc);
1421 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1422 enum plane_id plane_id;
1424 if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
1425 *intermediate = *optimal;
1427 intermediate->cxsr = false;
1428 intermediate->hpll_en = false;
1432 intermediate->cxsr = optimal->cxsr && active->cxsr &&
1433 !new_crtc_state->disable_cxsr;
1434 intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1435 !new_crtc_state->disable_cxsr;
1436 intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1438 for_each_plane_id_on_crtc(crtc, plane_id) {
1439 intermediate->wm.plane[plane_id] =
1440 max(optimal->wm.plane[plane_id],
1441 active->wm.plane[plane_id]);
1443 WARN_ON(intermediate->wm.plane[plane_id] >
1444 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1447 intermediate->sr.plane = max(optimal->sr.plane,
1449 intermediate->sr.cursor = max(optimal->sr.cursor,
1451 intermediate->sr.fbc = max(optimal->sr.fbc,
1454 intermediate->hpll.plane = max(optimal->hpll.plane,
1455 active->hpll.plane);
1456 intermediate->hpll.cursor = max(optimal->hpll.cursor,
1457 active->hpll.cursor);
1458 intermediate->hpll.fbc = max(optimal->hpll.fbc,
1461 WARN_ON((intermediate->sr.plane >
1462 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1463 intermediate->sr.cursor >
1464 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1465 intermediate->cxsr);
1466 WARN_ON((intermediate->sr.plane >
1467 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1468 intermediate->sr.cursor >
1469 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1470 intermediate->hpll_en);
1472 WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1473 intermediate->fbc_en && intermediate->cxsr);
1474 WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1475 intermediate->fbc_en && intermediate->hpll_en);
1479 * If our intermediate WM are identical to the final WM, then we can
1480 * omit the post-vblank programming; only update if it's different.
1482 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1483 new_crtc_state->wm.need_postvbl_update = true;
1488 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1489 struct g4x_wm_values *wm)
1491 struct intel_crtc *crtc;
1492 int num_active_crtcs = 0;
1498 for_each_intel_crtc(&dev_priv->drm, crtc) {
1499 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1504 if (!wm_state->cxsr)
1506 if (!wm_state->hpll_en)
1507 wm->hpll_en = false;
1508 if (!wm_state->fbc_en)
1514 if (num_active_crtcs != 1) {
1516 wm->hpll_en = false;
1520 for_each_intel_crtc(&dev_priv->drm, crtc) {
1521 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1522 enum pipe pipe = crtc->pipe;
1524 wm->pipe[pipe] = wm_state->wm;
1525 if (crtc->active && wm->cxsr)
1526 wm->sr = wm_state->sr;
1527 if (crtc->active && wm->hpll_en)
1528 wm->hpll = wm_state->hpll;
1532 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1534 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1535 struct g4x_wm_values new_wm = {};
1537 g4x_merge_wm(dev_priv, &new_wm);
1539 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1542 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1543 _intel_set_memory_cxsr(dev_priv, false);
1545 g4x_write_wm_values(dev_priv, &new_wm);
1547 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1548 _intel_set_memory_cxsr(dev_priv, true);
1553 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1554 struct intel_crtc_state *crtc_state)
1556 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1557 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1559 mutex_lock(&dev_priv->wm.wm_mutex);
1560 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1561 g4x_program_watermarks(dev_priv);
1562 mutex_unlock(&dev_priv->wm.wm_mutex);
1565 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1566 struct intel_crtc_state *crtc_state)
1568 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1569 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1571 if (!crtc_state->wm.need_postvbl_update)
1574 mutex_lock(&dev_priv->wm.wm_mutex);
1575 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1576 g4x_program_watermarks(dev_priv);
1577 mutex_unlock(&dev_priv->wm.wm_mutex);
1580 /* latency must be in 0.1us units. */
1581 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1582 unsigned int htotal,
1585 unsigned int latency)
1589 ret = intel_wm_method2(pixel_rate, htotal,
1590 width, cpp, latency);
1591 ret = DIV_ROUND_UP(ret, 64);
1596 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1598 /* all latencies in usec */
1599 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1601 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1603 if (IS_CHERRYVIEW(dev_priv)) {
1604 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1605 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1607 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1611 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1612 const struct intel_plane_state *plane_state,
1615 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1616 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1617 const struct drm_display_mode *adjusted_mode =
1618 &crtc_state->base.adjusted_mode;
1619 unsigned int clock, htotal, cpp, width, wm;
1621 if (dev_priv->wm.pri_latency[level] == 0)
1624 if (!intel_wm_plane_visible(crtc_state, plane_state))
1627 cpp = plane_state->base.fb->format->cpp[0];
1628 clock = adjusted_mode->crtc_clock;
1629 htotal = adjusted_mode->crtc_htotal;
1630 width = crtc_state->pipe_src_w;
1632 if (plane->id == PLANE_CURSOR) {
1634 * FIXME the formula gives values that are
1635 * too big for the cursor FIFO, and hence we
1636 * would never be able to use cursors. For
1637 * now just hardcode the watermark.
1641 wm = vlv_wm_method2(clock, htotal, width, cpp,
1642 dev_priv->wm.pri_latency[level] * 10);
1645 return min_t(unsigned int, wm, USHRT_MAX);
1648 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1650 return (active_planes & (BIT(PLANE_SPRITE0) |
1651 BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1654 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1656 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1657 const struct g4x_pipe_wm *raw =
1658 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1659 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1660 unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1661 int num_active_planes = hweight32(active_planes);
1662 const int fifo_size = 511;
1663 int fifo_extra, fifo_left = fifo_size;
1664 int sprite0_fifo_extra = 0;
1665 unsigned int total_rate;
1666 enum plane_id plane_id;
1669 * When enabling sprite0 after sprite1 has already been enabled
1670 * we tend to get an underrun unless sprite0 already has some
1671 * FIFO space allcoated. Hence we always allocate at least one
1672 * cacheline for sprite0 whenever sprite1 is enabled.
1674 * All other plane enable sequences appear immune to this problem.
1676 if (vlv_need_sprite0_fifo_workaround(active_planes))
1677 sprite0_fifo_extra = 1;
1679 total_rate = raw->plane[PLANE_PRIMARY] +
1680 raw->plane[PLANE_SPRITE0] +
1681 raw->plane[PLANE_SPRITE1] +
1684 if (total_rate > fifo_size)
1687 if (total_rate == 0)
1690 for_each_plane_id_on_crtc(crtc, plane_id) {
1693 if ((active_planes & BIT(plane_id)) == 0) {
1694 fifo_state->plane[plane_id] = 0;
1698 rate = raw->plane[plane_id];
1699 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1700 fifo_left -= fifo_state->plane[plane_id];
1703 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1704 fifo_left -= sprite0_fifo_extra;
1706 fifo_state->plane[PLANE_CURSOR] = 63;
1708 fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1710 /* spread the remainder evenly */
1711 for_each_plane_id_on_crtc(crtc, plane_id) {
1717 if ((active_planes & BIT(plane_id)) == 0)
1720 plane_extra = min(fifo_extra, fifo_left);
1721 fifo_state->plane[plane_id] += plane_extra;
1722 fifo_left -= plane_extra;
1725 WARN_ON(active_planes != 0 && fifo_left != 0);
1727 /* give it all to the first plane if none are active */
1728 if (active_planes == 0) {
1729 WARN_ON(fifo_left != fifo_size);
1730 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1736 /* mark all levels starting from 'level' as invalid */
1737 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1738 struct vlv_wm_state *wm_state, int level)
1740 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1742 for (; level < intel_wm_num_levels(dev_priv); level++) {
1743 enum plane_id plane_id;
1745 for_each_plane_id_on_crtc(crtc, plane_id)
1746 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1748 wm_state->sr[level].cursor = USHRT_MAX;
1749 wm_state->sr[level].plane = USHRT_MAX;
1753 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1758 return fifo_size - wm;
1762 * Starting from 'level' set all higher
1763 * levels to 'value' in the "raw" watermarks.
1765 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1766 int level, enum plane_id plane_id, u16 value)
1768 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1769 int num_levels = intel_wm_num_levels(dev_priv);
1772 for (; level < num_levels; level++) {
1773 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1775 dirty |= raw->plane[plane_id] != value;
1776 raw->plane[plane_id] = value;
1782 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1783 const struct intel_plane_state *plane_state)
1785 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1786 enum plane_id plane_id = plane->id;
1787 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1791 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1792 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1796 for (level = 0; level < num_levels; level++) {
1797 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1798 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1799 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1804 dirty |= raw->plane[plane_id] != wm;
1805 raw->plane[plane_id] = wm;
1808 /* mark all higher levels as invalid */
1809 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1813 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1815 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1816 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1817 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1822 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1823 enum plane_id plane_id, int level)
1825 const struct g4x_pipe_wm *raw =
1826 &crtc_state->wm.vlv.raw[level];
1827 const struct vlv_fifo_state *fifo_state =
1828 &crtc_state->wm.vlv.fifo_state;
1830 return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1833 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1835 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1836 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1837 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1838 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1841 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1845 struct intel_atomic_state *state =
1846 to_intel_atomic_state(crtc_state->base.state);
1847 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1848 const struct vlv_fifo_state *fifo_state =
1849 &crtc_state->wm.vlv.fifo_state;
1850 int num_active_planes = hweight32(crtc_state->active_planes &
1851 ~BIT(PLANE_CURSOR));
1852 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1853 const struct intel_plane_state *old_plane_state;
1854 const struct intel_plane_state *new_plane_state;
1855 struct intel_plane *plane;
1856 enum plane_id plane_id;
1858 unsigned int dirty = 0;
1860 for_each_oldnew_intel_plane_in_state(state, plane,
1862 new_plane_state, i) {
1863 if (new_plane_state->base.crtc != &crtc->base &&
1864 old_plane_state->base.crtc != &crtc->base)
1867 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1868 dirty |= BIT(plane->id);
1872 * DSPARB registers may have been reset due to the
1873 * power well being turned off. Make sure we restore
1874 * them to a consistent state even if no primary/sprite
1875 * planes are initially active.
1878 crtc_state->fifo_changed = true;
1883 /* cursor changes don't warrant a FIFO recompute */
1884 if (dirty & ~BIT(PLANE_CURSOR)) {
1885 const struct intel_crtc_state *old_crtc_state =
1886 intel_atomic_get_old_crtc_state(state, crtc);
1887 const struct vlv_fifo_state *old_fifo_state =
1888 &old_crtc_state->wm.vlv.fifo_state;
1890 ret = vlv_compute_fifo(crtc_state);
1894 if (needs_modeset ||
1895 memcmp(old_fifo_state, fifo_state,
1896 sizeof(*fifo_state)) != 0)
1897 crtc_state->fifo_changed = true;
1900 /* initially allow all levels */
1901 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1903 * Note that enabling cxsr with no primary/sprite planes
1904 * enabled can wedge the pipe. Hence we only allow cxsr
1905 * with exactly one enabled primary/sprite plane.
1907 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1909 for (level = 0; level < wm_state->num_levels; level++) {
1910 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1911 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1913 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1916 for_each_plane_id_on_crtc(crtc, plane_id) {
1917 wm_state->wm[level].plane[plane_id] =
1918 vlv_invert_wm_value(raw->plane[plane_id],
1919 fifo_state->plane[plane_id]);
1922 wm_state->sr[level].plane =
1923 vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1924 raw->plane[PLANE_SPRITE0],
1925 raw->plane[PLANE_SPRITE1]),
1928 wm_state->sr[level].cursor =
1929 vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1936 /* limit to only levels we can actually handle */
1937 wm_state->num_levels = level;
1939 /* invalidate the higher levels */
1940 vlv_invalidate_wms(crtc, wm_state, level);
1945 #define VLV_FIFO(plane, value) \
1946 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1948 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1949 struct intel_crtc_state *crtc_state)
1951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1952 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1953 struct intel_uncore *uncore = &dev_priv->uncore;
1954 const struct vlv_fifo_state *fifo_state =
1955 &crtc_state->wm.vlv.fifo_state;
1956 int sprite0_start, sprite1_start, fifo_size;
1958 if (!crtc_state->fifo_changed)
1961 sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1962 sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1963 fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1965 WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1966 WARN_ON(fifo_size != 511);
1968 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1971 * uncore.lock serves a double purpose here. It allows us to
1972 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1973 * it protects the DSPARB registers from getting clobbered by
1974 * parallel updates from multiple pipes.
1976 * intel_pipe_update_start() has already disabled interrupts
1977 * for us, so a plain spin_lock() is sufficient here.
1979 spin_lock(&uncore->lock);
1981 switch (crtc->pipe) {
1982 u32 dsparb, dsparb2, dsparb3;
1984 dsparb = intel_uncore_read_fw(uncore, DSPARB);
1985 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
1987 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1988 VLV_FIFO(SPRITEB, 0xff));
1989 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1990 VLV_FIFO(SPRITEB, sprite1_start));
1992 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1993 VLV_FIFO(SPRITEB_HI, 0x1));
1994 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1995 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1997 intel_uncore_write_fw(uncore, DSPARB, dsparb);
1998 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2001 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2002 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2004 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2005 VLV_FIFO(SPRITED, 0xff));
2006 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2007 VLV_FIFO(SPRITED, sprite1_start));
2009 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2010 VLV_FIFO(SPRITED_HI, 0xff));
2011 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2012 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2014 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2015 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2018 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2019 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2021 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2022 VLV_FIFO(SPRITEF, 0xff));
2023 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2024 VLV_FIFO(SPRITEF, sprite1_start));
2026 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2027 VLV_FIFO(SPRITEF_HI, 0xff));
2028 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2029 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2031 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2032 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2038 intel_uncore_posting_read_fw(uncore, DSPARB);
2040 spin_unlock(&uncore->lock);
2045 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
2047 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
2048 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2049 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2050 struct intel_atomic_state *intel_state =
2051 to_intel_atomic_state(new_crtc_state->base.state);
2052 const struct intel_crtc_state *old_crtc_state =
2053 intel_atomic_get_old_crtc_state(intel_state, crtc);
2054 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2057 if (!new_crtc_state->base.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->base)) {
2058 *intermediate = *optimal;
2060 intermediate->cxsr = false;
2064 intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2065 intermediate->cxsr = optimal->cxsr && active->cxsr &&
2066 !new_crtc_state->disable_cxsr;
2068 for (level = 0; level < intermediate->num_levels; level++) {
2069 enum plane_id plane_id;
2071 for_each_plane_id_on_crtc(crtc, plane_id) {
2072 intermediate->wm[level].plane[plane_id] =
2073 min(optimal->wm[level].plane[plane_id],
2074 active->wm[level].plane[plane_id]);
2077 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2078 active->sr[level].plane);
2079 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2080 active->sr[level].cursor);
2083 vlv_invalidate_wms(crtc, intermediate, level);
2087 * If our intermediate WM are identical to the final WM, then we can
2088 * omit the post-vblank programming; only update if it's different.
2090 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2091 new_crtc_state->wm.need_postvbl_update = true;
2096 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2097 struct vlv_wm_values *wm)
2099 struct intel_crtc *crtc;
2100 int num_active_crtcs = 0;
2102 wm->level = dev_priv->wm.max_level;
2105 for_each_intel_crtc(&dev_priv->drm, crtc) {
2106 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2111 if (!wm_state->cxsr)
2115 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2118 if (num_active_crtcs != 1)
2121 if (num_active_crtcs > 1)
2122 wm->level = VLV_WM_LEVEL_PM2;
2124 for_each_intel_crtc(&dev_priv->drm, crtc) {
2125 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2126 enum pipe pipe = crtc->pipe;
2128 wm->pipe[pipe] = wm_state->wm[wm->level];
2129 if (crtc->active && wm->cxsr)
2130 wm->sr = wm_state->sr[wm->level];
2132 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2133 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2134 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2135 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2139 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2141 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2142 struct vlv_wm_values new_wm = {};
2144 vlv_merge_wm(dev_priv, &new_wm);
2146 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2149 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2150 chv_set_memory_dvfs(dev_priv, false);
2152 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2153 chv_set_memory_pm5(dev_priv, false);
2155 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2156 _intel_set_memory_cxsr(dev_priv, false);
2158 vlv_write_wm_values(dev_priv, &new_wm);
2160 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2161 _intel_set_memory_cxsr(dev_priv, true);
2163 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2164 chv_set_memory_pm5(dev_priv, true);
2166 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2167 chv_set_memory_dvfs(dev_priv, true);
2172 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2173 struct intel_crtc_state *crtc_state)
2175 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2178 mutex_lock(&dev_priv->wm.wm_mutex);
2179 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2180 vlv_program_watermarks(dev_priv);
2181 mutex_unlock(&dev_priv->wm.wm_mutex);
2184 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2185 struct intel_crtc_state *crtc_state)
2187 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2188 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2190 if (!crtc_state->wm.need_postvbl_update)
2193 mutex_lock(&dev_priv->wm.wm_mutex);
2194 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2195 vlv_program_watermarks(dev_priv);
2196 mutex_unlock(&dev_priv->wm.wm_mutex);
2199 static void i965_update_wm(struct intel_crtc *unused_crtc)
2201 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2202 struct intel_crtc *crtc;
2207 /* Calc sr entries for one plane configs */
2208 crtc = single_enabled_crtc(dev_priv);
2210 /* self-refresh has much higher latency */
2211 static const int sr_latency_ns = 12000;
2212 const struct drm_display_mode *adjusted_mode =
2213 &crtc->config->base.adjusted_mode;
2214 const struct drm_framebuffer *fb =
2215 crtc->base.primary->state->fb;
2216 int clock = adjusted_mode->crtc_clock;
2217 int htotal = adjusted_mode->crtc_htotal;
2218 int hdisplay = crtc->config->pipe_src_w;
2219 int cpp = fb->format->cpp[0];
2222 entries = intel_wm_method2(clock, htotal,
2223 hdisplay, cpp, sr_latency_ns / 100);
2224 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2225 srwm = I965_FIFO_SIZE - entries;
2229 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2232 entries = intel_wm_method2(clock, htotal,
2233 crtc->base.cursor->state->crtc_w, 4,
2234 sr_latency_ns / 100);
2235 entries = DIV_ROUND_UP(entries,
2236 i965_cursor_wm_info.cacheline_size) +
2237 i965_cursor_wm_info.guard_size;
2239 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2240 if (cursor_sr > i965_cursor_wm_info.max_wm)
2241 cursor_sr = i965_cursor_wm_info.max_wm;
2243 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2244 "cursor %d\n", srwm, cursor_sr);
2246 cxsr_enabled = true;
2248 cxsr_enabled = false;
2249 /* Turn off self refresh if both pipes are enabled */
2250 intel_set_memory_cxsr(dev_priv, false);
2253 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2256 /* 965 has limitations... */
2257 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2261 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2262 FW_WM(8, PLANEC_OLD));
2263 /* update cursor SR watermark */
2264 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2267 intel_set_memory_cxsr(dev_priv, true);
2272 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2274 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2275 const struct intel_watermark_params *wm_info;
2280 int planea_wm, planeb_wm;
2281 struct intel_crtc *crtc, *enabled = NULL;
2283 if (IS_I945GM(dev_priv))
2284 wm_info = &i945_wm_info;
2285 else if (!IS_GEN(dev_priv, 2))
2286 wm_info = &i915_wm_info;
2288 wm_info = &i830_a_wm_info;
2290 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2291 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2292 if (intel_crtc_active(crtc)) {
2293 const struct drm_display_mode *adjusted_mode =
2294 &crtc->config->base.adjusted_mode;
2295 const struct drm_framebuffer *fb =
2296 crtc->base.primary->state->fb;
2299 if (IS_GEN(dev_priv, 2))
2302 cpp = fb->format->cpp[0];
2304 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2305 wm_info, fifo_size, cpp,
2306 pessimal_latency_ns);
2309 planea_wm = fifo_size - wm_info->guard_size;
2310 if (planea_wm > (long)wm_info->max_wm)
2311 planea_wm = wm_info->max_wm;
2314 if (IS_GEN(dev_priv, 2))
2315 wm_info = &i830_bc_wm_info;
2317 fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2318 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2319 if (intel_crtc_active(crtc)) {
2320 const struct drm_display_mode *adjusted_mode =
2321 &crtc->config->base.adjusted_mode;
2322 const struct drm_framebuffer *fb =
2323 crtc->base.primary->state->fb;
2326 if (IS_GEN(dev_priv, 2))
2329 cpp = fb->format->cpp[0];
2331 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2332 wm_info, fifo_size, cpp,
2333 pessimal_latency_ns);
2334 if (enabled == NULL)
2339 planeb_wm = fifo_size - wm_info->guard_size;
2340 if (planeb_wm > (long)wm_info->max_wm)
2341 planeb_wm = wm_info->max_wm;
2344 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2346 if (IS_I915GM(dev_priv) && enabled) {
2347 struct drm_i915_gem_object *obj;
2349 obj = intel_fb_obj(enabled->base.primary->state->fb);
2351 /* self-refresh seems busted with untiled */
2352 if (!i915_gem_object_is_tiled(obj))
2357 * Overlay gets an aggressive default since video jitter is bad.
2361 /* Play safe and disable self-refresh before adjusting watermarks. */
2362 intel_set_memory_cxsr(dev_priv, false);
2364 /* Calc sr entries for one plane configs */
2365 if (HAS_FW_BLC(dev_priv) && enabled) {
2366 /* self-refresh has much higher latency */
2367 static const int sr_latency_ns = 6000;
2368 const struct drm_display_mode *adjusted_mode =
2369 &enabled->config->base.adjusted_mode;
2370 const struct drm_framebuffer *fb =
2371 enabled->base.primary->state->fb;
2372 int clock = adjusted_mode->crtc_clock;
2373 int htotal = adjusted_mode->crtc_htotal;
2374 int hdisplay = enabled->config->pipe_src_w;
2378 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2381 cpp = fb->format->cpp[0];
2383 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2384 sr_latency_ns / 100);
2385 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2386 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2387 srwm = wm_info->fifo_size - entries;
2391 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2392 I915_WRITE(FW_BLC_SELF,
2393 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2395 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2398 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2399 planea_wm, planeb_wm, cwm, srwm);
2401 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2402 fwater_hi = (cwm & 0x1f);
2404 /* Set request length to 8 cachelines per fetch */
2405 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2406 fwater_hi = fwater_hi | (1 << 8);
2408 I915_WRITE(FW_BLC, fwater_lo);
2409 I915_WRITE(FW_BLC2, fwater_hi);
2412 intel_set_memory_cxsr(dev_priv, true);
2415 static void i845_update_wm(struct intel_crtc *unused_crtc)
2417 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2418 struct intel_crtc *crtc;
2419 const struct drm_display_mode *adjusted_mode;
2423 crtc = single_enabled_crtc(dev_priv);
2427 adjusted_mode = &crtc->config->base.adjusted_mode;
2428 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2430 dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2431 4, pessimal_latency_ns);
2432 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2433 fwater_lo |= (3<<8) | planea_wm;
2435 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2437 I915_WRITE(FW_BLC, fwater_lo);
2440 /* latency must be in 0.1us units. */
2441 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2443 unsigned int latency)
2447 ret = intel_wm_method1(pixel_rate, cpp, latency);
2448 ret = DIV_ROUND_UP(ret, 64) + 2;
2453 /* latency must be in 0.1us units. */
2454 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2455 unsigned int htotal,
2458 unsigned int latency)
2462 ret = intel_wm_method2(pixel_rate, htotal,
2463 width, cpp, latency);
2464 ret = DIV_ROUND_UP(ret, 64) + 2;
2469 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2472 * Neither of these should be possible since this function shouldn't be
2473 * called if the CRTC is off or the plane is invisible. But let's be
2474 * extra paranoid to avoid a potential divide-by-zero if we screw up
2475 * elsewhere in the driver.
2479 if (WARN_ON(!horiz_pixels))
2482 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2485 struct ilk_wm_maximums {
2493 * For both WM_PIPE and WM_LP.
2494 * mem_value must be in 0.1us units.
2496 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2497 const struct intel_plane_state *plane_state,
2498 u32 mem_value, bool is_lp)
2500 u32 method1, method2;
2506 if (!intel_wm_plane_visible(crtc_state, plane_state))
2509 cpp = plane_state->base.fb->format->cpp[0];
2511 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2516 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2517 crtc_state->base.adjusted_mode.crtc_htotal,
2518 drm_rect_width(&plane_state->base.dst),
2521 return min(method1, method2);
2525 * For both WM_PIPE and WM_LP.
2526 * mem_value must be in 0.1us units.
2528 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2529 const struct intel_plane_state *plane_state,
2532 u32 method1, method2;
2538 if (!intel_wm_plane_visible(crtc_state, plane_state))
2541 cpp = plane_state->base.fb->format->cpp[0];
2543 method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2544 method2 = ilk_wm_method2(crtc_state->pixel_rate,
2545 crtc_state->base.adjusted_mode.crtc_htotal,
2546 drm_rect_width(&plane_state->base.dst),
2548 return min(method1, method2);
2552 * For both WM_PIPE and WM_LP.
2553 * mem_value must be in 0.1us units.
2555 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2556 const struct intel_plane_state *plane_state,
2564 if (!intel_wm_plane_visible(crtc_state, plane_state))
2567 cpp = plane_state->base.fb->format->cpp[0];
2569 return ilk_wm_method2(crtc_state->pixel_rate,
2570 crtc_state->base.adjusted_mode.crtc_htotal,
2571 plane_state->base.crtc_w, cpp, mem_value);
2574 /* Only for WM_LP. */
2575 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2576 const struct intel_plane_state *plane_state,
2581 if (!intel_wm_plane_visible(crtc_state, plane_state))
2584 cpp = plane_state->base.fb->format->cpp[0];
2586 return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
2590 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2592 if (INTEL_GEN(dev_priv) >= 8)
2594 else if (INTEL_GEN(dev_priv) >= 7)
2601 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2602 int level, bool is_sprite)
2604 if (INTEL_GEN(dev_priv) >= 8)
2605 /* BDW primary/sprite plane watermarks */
2606 return level == 0 ? 255 : 2047;
2607 else if (INTEL_GEN(dev_priv) >= 7)
2608 /* IVB/HSW primary/sprite plane watermarks */
2609 return level == 0 ? 127 : 1023;
2610 else if (!is_sprite)
2611 /* ILK/SNB primary plane watermarks */
2612 return level == 0 ? 127 : 511;
2614 /* ILK/SNB sprite plane watermarks */
2615 return level == 0 ? 63 : 255;
2619 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2621 if (INTEL_GEN(dev_priv) >= 7)
2622 return level == 0 ? 63 : 255;
2624 return level == 0 ? 31 : 63;
2627 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2629 if (INTEL_GEN(dev_priv) >= 8)
2635 /* Calculate the maximum primary/sprite plane watermark */
2636 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2638 const struct intel_wm_config *config,
2639 enum intel_ddb_partitioning ddb_partitioning,
2642 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2644 /* if sprites aren't enabled, sprites get nothing */
2645 if (is_sprite && !config->sprites_enabled)
2648 /* HSW allows LP1+ watermarks even with multiple pipes */
2649 if (level == 0 || config->num_pipes_active > 1) {
2650 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2653 * For some reason the non self refresh
2654 * FIFO size is only half of the self
2655 * refresh FIFO size on ILK/SNB.
2657 if (INTEL_GEN(dev_priv) <= 6)
2661 if (config->sprites_enabled) {
2662 /* level 0 is always calculated with 1:1 split */
2663 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2672 /* clamp to max that the registers can hold */
2673 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2676 /* Calculate the maximum cursor plane watermark */
2677 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2679 const struct intel_wm_config *config)
2681 /* HSW LP1+ watermarks w/ multiple pipes */
2682 if (level > 0 && config->num_pipes_active > 1)
2685 /* otherwise just report max that registers can hold */
2686 return ilk_cursor_wm_reg_max(dev_priv, level);
2689 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2691 const struct intel_wm_config *config,
2692 enum intel_ddb_partitioning ddb_partitioning,
2693 struct ilk_wm_maximums *max)
2695 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2696 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2697 max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2698 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2701 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2703 struct ilk_wm_maximums *max)
2705 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2706 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2707 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2708 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2711 static bool ilk_validate_wm_level(int level,
2712 const struct ilk_wm_maximums *max,
2713 struct intel_wm_level *result)
2717 /* already determined to be invalid? */
2718 if (!result->enable)
2721 result->enable = result->pri_val <= max->pri &&
2722 result->spr_val <= max->spr &&
2723 result->cur_val <= max->cur;
2725 ret = result->enable;
2728 * HACK until we can pre-compute everything,
2729 * and thus fail gracefully if LP0 watermarks
2732 if (level == 0 && !result->enable) {
2733 if (result->pri_val > max->pri)
2734 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2735 level, result->pri_val, max->pri);
2736 if (result->spr_val > max->spr)
2737 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2738 level, result->spr_val, max->spr);
2739 if (result->cur_val > max->cur)
2740 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2741 level, result->cur_val, max->cur);
2743 result->pri_val = min_t(u32, result->pri_val, max->pri);
2744 result->spr_val = min_t(u32, result->spr_val, max->spr);
2745 result->cur_val = min_t(u32, result->cur_val, max->cur);
2746 result->enable = true;
2752 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2753 const struct intel_crtc *intel_crtc,
2755 struct intel_crtc_state *crtc_state,
2756 const struct intel_plane_state *pristate,
2757 const struct intel_plane_state *sprstate,
2758 const struct intel_plane_state *curstate,
2759 struct intel_wm_level *result)
2761 u16 pri_latency = dev_priv->wm.pri_latency[level];
2762 u16 spr_latency = dev_priv->wm.spr_latency[level];
2763 u16 cur_latency = dev_priv->wm.cur_latency[level];
2765 /* WM1+ latency values stored in 0.5us units */
2773 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2774 pri_latency, level);
2775 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2779 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2782 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2784 result->enable = true;
2788 hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
2790 const struct intel_atomic_state *intel_state =
2791 to_intel_atomic_state(crtc_state->base.state);
2792 const struct drm_display_mode *adjusted_mode =
2793 &crtc_state->base.adjusted_mode;
2794 u32 linetime, ips_linetime;
2796 if (!crtc_state->base.active)
2798 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2800 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2803 /* The WM are computed with base on how long it takes to fill a single
2804 * row at the given clock rate, multiplied by 8.
2806 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2807 adjusted_mode->crtc_clock);
2808 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2809 intel_state->cdclk.logical.cdclk);
2811 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2812 PIPE_WM_LINETIME_TIME(linetime);
2815 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2818 struct intel_uncore *uncore = &dev_priv->uncore;
2820 if (INTEL_GEN(dev_priv) >= 9) {
2823 int level, max_level = ilk_wm_max_level(dev_priv);
2825 /* read the first set of memory latencies[0:3] */
2826 val = 0; /* data0 to be programmed to 0 for first set */
2827 ret = sandybridge_pcode_read(dev_priv,
2828 GEN9_PCODE_READ_MEM_LATENCY,
2832 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2836 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2837 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2838 GEN9_MEM_LATENCY_LEVEL_MASK;
2839 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2840 GEN9_MEM_LATENCY_LEVEL_MASK;
2841 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2842 GEN9_MEM_LATENCY_LEVEL_MASK;
2844 /* read the second set of memory latencies[4:7] */
2845 val = 1; /* data0 to be programmed to 1 for second set */
2846 ret = sandybridge_pcode_read(dev_priv,
2847 GEN9_PCODE_READ_MEM_LATENCY,
2850 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2854 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2855 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2856 GEN9_MEM_LATENCY_LEVEL_MASK;
2857 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2858 GEN9_MEM_LATENCY_LEVEL_MASK;
2859 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2860 GEN9_MEM_LATENCY_LEVEL_MASK;
2863 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2864 * need to be disabled. We make sure to sanitize the values out
2865 * of the punit to satisfy this requirement.
2867 for (level = 1; level <= max_level; level++) {
2868 if (wm[level] == 0) {
2869 for (i = level + 1; i <= max_level; i++)
2876 * WaWmMemoryReadLatency:skl+,glk
2878 * punit doesn't take into account the read latency so we need
2879 * to add 2us to the various latency levels we retrieve from the
2880 * punit when level 0 response data us 0us.
2884 for (level = 1; level <= max_level; level++) {
2892 * WA Level-0 adjustment for 16GB DIMMs: SKL+
2893 * If we could not get dimm info enable this WA to prevent from
2894 * any underrun. If not able to get Dimm info assume 16GB dimm
2895 * to avoid any underrun.
2897 if (dev_priv->dram_info.is_16gb_dimm)
2900 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2901 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2903 wm[0] = (sskpd >> 56) & 0xFF;
2905 wm[0] = sskpd & 0xF;
2906 wm[1] = (sskpd >> 4) & 0xFF;
2907 wm[2] = (sskpd >> 12) & 0xFF;
2908 wm[3] = (sskpd >> 20) & 0x1FF;
2909 wm[4] = (sskpd >> 32) & 0x1FF;
2910 } else if (INTEL_GEN(dev_priv) >= 6) {
2911 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2913 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2914 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2915 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2916 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2917 } else if (INTEL_GEN(dev_priv) >= 5) {
2918 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2920 /* ILK primary LP0 latency is 700 ns */
2922 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2923 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2925 MISSING_CASE(INTEL_DEVID(dev_priv));
2929 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2932 /* ILK sprite LP0 latency is 1300 ns */
2933 if (IS_GEN(dev_priv, 5))
2937 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2940 /* ILK cursor LP0 latency is 1300 ns */
2941 if (IS_GEN(dev_priv, 5))
2945 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2947 /* how many WM levels are we expecting */
2948 if (INTEL_GEN(dev_priv) >= 9)
2950 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2952 else if (INTEL_GEN(dev_priv) >= 6)
2958 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2962 int level, max_level = ilk_wm_max_level(dev_priv);
2964 for (level = 0; level <= max_level; level++) {
2965 unsigned int latency = wm[level];
2968 DRM_DEBUG_KMS("%s WM%d latency not provided\n",
2974 * - latencies are in us on gen9.
2975 * - before then, WM1+ latency values are in 0.5us units
2977 if (INTEL_GEN(dev_priv) >= 9)
2982 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2983 name, level, wm[level],
2984 latency / 10, latency % 10);
2988 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2991 int level, max_level = ilk_wm_max_level(dev_priv);
2996 wm[0] = max(wm[0], min);
2997 for (level = 1; level <= max_level; level++)
2998 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3003 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3008 * The BIOS provided WM memory latency values are often
3009 * inadequate for high resolution displays. Adjust them.
3011 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3012 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3013 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3018 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
3019 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3020 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3021 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3024 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3027 * On some SNB machines (Thinkpad X220 Tablet at least)
3028 * LP3 usage can cause vblank interrupts to be lost.
3029 * The DEIIR bit will go high but it looks like the CPU
3030 * never gets interrupted.
3032 * It's not clear whether other interrupt source could
3033 * be affected or if this is somehow limited to vblank
3034 * interrupts only. To play it safe we disable LP3
3035 * watermarks entirely.
3037 if (dev_priv->wm.pri_latency[3] == 0 &&
3038 dev_priv->wm.spr_latency[3] == 0 &&
3039 dev_priv->wm.cur_latency[3] == 0)
3042 dev_priv->wm.pri_latency[3] = 0;
3043 dev_priv->wm.spr_latency[3] = 0;
3044 dev_priv->wm.cur_latency[3] = 0;
3046 DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n");
3047 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3048 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3049 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3052 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3054 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3056 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3057 sizeof(dev_priv->wm.pri_latency));
3058 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3059 sizeof(dev_priv->wm.pri_latency));
3061 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3062 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3064 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3065 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3066 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3068 if (IS_GEN(dev_priv, 6)) {
3069 snb_wm_latency_quirk(dev_priv);
3070 snb_wm_lp3_irq_quirk(dev_priv);
3074 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3076 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3077 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3080 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3081 struct intel_pipe_wm *pipe_wm)
3083 /* LP0 watermark maximums depend on this pipe alone */
3084 const struct intel_wm_config config = {
3085 .num_pipes_active = 1,
3086 .sprites_enabled = pipe_wm->sprites_enabled,
3087 .sprites_scaled = pipe_wm->sprites_scaled,
3089 struct ilk_wm_maximums max;
3091 /* LP0 watermarks always use 1/2 DDB partitioning */
3092 ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3094 /* At least LP0 must be valid */
3095 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3096 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3103 /* Compute new watermarks for the pipe */
3104 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
3106 struct drm_atomic_state *state = crtc_state->base.state;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3108 struct intel_pipe_wm *pipe_wm;
3109 struct drm_device *dev = state->dev;
3110 const struct drm_i915_private *dev_priv = to_i915(dev);
3111 struct drm_plane *plane;
3112 const struct drm_plane_state *plane_state;
3113 const struct intel_plane_state *pristate = NULL;
3114 const struct intel_plane_state *sprstate = NULL;
3115 const struct intel_plane_state *curstate = NULL;
3116 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3117 struct ilk_wm_maximums max;
3119 pipe_wm = &crtc_state->wm.ilk.optimal;
3121 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
3122 const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
3124 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3126 else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
3128 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
3132 pipe_wm->pipe_enabled = crtc_state->base.active;
3134 pipe_wm->sprites_enabled = sprstate->base.visible;
3135 pipe_wm->sprites_scaled = sprstate->base.visible &&
3136 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3137 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3140 usable_level = max_level;
3142 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3143 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3146 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3147 if (pipe_wm->sprites_scaled)
3150 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3151 ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
3152 pristate, sprstate, curstate, &pipe_wm->wm[0]);
3154 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3155 pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
3157 if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3160 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3162 for (level = 1; level <= usable_level; level++) {
3163 struct intel_wm_level *wm = &pipe_wm->wm[level];
3165 ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
3166 pristate, sprstate, curstate, wm);
3169 * Disable any watermark level that exceeds the
3170 * register maximums since such watermarks are
3173 if (!ilk_validate_wm_level(level, &max, wm)) {
3174 memset(wm, 0, sizeof(*wm));
3183 * Build a set of 'intermediate' watermark values that satisfy both the old
3184 * state and the new state. These can be programmed to the hardware
3187 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
3189 struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc);
3190 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3191 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3192 struct intel_atomic_state *intel_state =
3193 to_intel_atomic_state(newstate->base.state);
3194 const struct intel_crtc_state *oldstate =
3195 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3196 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3197 int level, max_level = ilk_wm_max_level(dev_priv);
3200 * Start with the final, target watermarks, then combine with the
3201 * currently active watermarks to get values that are safe both before
3202 * and after the vblank.
3204 *a = newstate->wm.ilk.optimal;
3205 if (!newstate->base.active || drm_atomic_crtc_needs_modeset(&newstate->base) ||
3206 intel_state->skip_intermediate_wm)
3209 a->pipe_enabled |= b->pipe_enabled;
3210 a->sprites_enabled |= b->sprites_enabled;
3211 a->sprites_scaled |= b->sprites_scaled;
3213 for (level = 0; level <= max_level; level++) {
3214 struct intel_wm_level *a_wm = &a->wm[level];
3215 const struct intel_wm_level *b_wm = &b->wm[level];
3217 a_wm->enable &= b_wm->enable;
3218 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3219 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3220 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3221 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3225 * We need to make sure that these merged watermark values are
3226 * actually a valid configuration themselves. If they're not,
3227 * there's no safe way to transition from the old state to
3228 * the new state, so we need to fail the atomic transaction.
3230 if (!ilk_validate_pipe_wm(dev_priv, a))
3234 * If our intermediate WM are identical to the final WM, then we can
3235 * omit the post-vblank programming; only update if it's different.
3237 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3238 newstate->wm.need_postvbl_update = true;
3244 * Merge the watermarks from all active pipes for a specific level.
3246 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3248 struct intel_wm_level *ret_wm)
3250 const struct intel_crtc *intel_crtc;
3252 ret_wm->enable = true;
3254 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3255 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3256 const struct intel_wm_level *wm = &active->wm[level];
3258 if (!active->pipe_enabled)
3262 * The watermark values may have been used in the past,
3263 * so we must maintain them in the registers for some
3264 * time even if the level is now disabled.
3267 ret_wm->enable = false;
3269 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3270 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3271 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3272 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3277 * Merge all low power watermarks for all active pipes.
3279 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3280 const struct intel_wm_config *config,
3281 const struct ilk_wm_maximums *max,
3282 struct intel_pipe_wm *merged)
3284 int level, max_level = ilk_wm_max_level(dev_priv);
3285 int last_enabled_level = max_level;
3287 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3288 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3289 config->num_pipes_active > 1)
3290 last_enabled_level = 0;
3292 /* ILK: FBC WM must be disabled always */
3293 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3295 /* merge each WM1+ level */
3296 for (level = 1; level <= max_level; level++) {
3297 struct intel_wm_level *wm = &merged->wm[level];
3299 ilk_merge_wm_level(dev_priv, level, wm);
3301 if (level > last_enabled_level)
3303 else if (!ilk_validate_wm_level(level, max, wm))
3304 /* make sure all following levels get disabled */
3305 last_enabled_level = level - 1;
3308 * The spec says it is preferred to disable
3309 * FBC WMs instead of disabling a WM level.
3311 if (wm->fbc_val > max->fbc) {
3313 merged->fbc_wm_enabled = false;
3318 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3320 * FIXME this is racy. FBC might get enabled later.
3321 * What we should check here is whether FBC can be
3322 * enabled sometime later.
3324 if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
3325 intel_fbc_is_active(dev_priv)) {
3326 for (level = 2; level <= max_level; level++) {
3327 struct intel_wm_level *wm = &merged->wm[level];
3334 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3336 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3337 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3340 /* The value we need to program into the WM_LPx latency field */
3341 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3344 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3347 return dev_priv->wm.pri_latency[level];
3350 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3351 const struct intel_pipe_wm *merged,
3352 enum intel_ddb_partitioning partitioning,
3353 struct ilk_wm_values *results)
3355 struct intel_crtc *intel_crtc;
3358 results->enable_fbc_wm = merged->fbc_wm_enabled;
3359 results->partitioning = partitioning;
3361 /* LP1+ register values */
3362 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3363 const struct intel_wm_level *r;
3365 level = ilk_wm_lp_to_level(wm_lp, merged);
3367 r = &merged->wm[level];
3370 * Maintain the watermark values even if the level is
3371 * disabled. Doing otherwise could cause underruns.
3373 results->wm_lp[wm_lp - 1] =
3374 (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3375 (r->pri_val << WM1_LP_SR_SHIFT) |
3379 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3381 if (INTEL_GEN(dev_priv) >= 8)
3382 results->wm_lp[wm_lp - 1] |=
3383 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3385 results->wm_lp[wm_lp - 1] |=
3386 r->fbc_val << WM1_LP_FBC_SHIFT;
3389 * Always set WM1S_LP_EN when spr_val != 0, even if the
3390 * level is disabled. Doing otherwise could cause underruns.
3392 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3393 WARN_ON(wm_lp != 1);
3394 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3396 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3399 /* LP0 register values */
3400 for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3401 enum pipe pipe = intel_crtc->pipe;
3402 const struct intel_wm_level *r =
3403 &intel_crtc->wm.active.ilk.wm[0];
3405 if (WARN_ON(!r->enable))
3408 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3410 results->wm_pipe[pipe] =
3411 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3412 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3417 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3418 * case both are at the same level. Prefer r1 in case they're the same. */
3419 static struct intel_pipe_wm *
3420 ilk_find_best_result(struct drm_i915_private *dev_priv,
3421 struct intel_pipe_wm *r1,
3422 struct intel_pipe_wm *r2)
3424 int level, max_level = ilk_wm_max_level(dev_priv);
3425 int level1 = 0, level2 = 0;
3427 for (level = 1; level <= max_level; level++) {
3428 if (r1->wm[level].enable)
3430 if (r2->wm[level].enable)
3434 if (level1 == level2) {
3435 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3439 } else if (level1 > level2) {
3446 /* dirty bits used to track which watermarks need changes */
3447 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3448 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3449 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3450 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3451 #define WM_DIRTY_FBC (1 << 24)
3452 #define WM_DIRTY_DDB (1 << 25)
3454 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3455 const struct ilk_wm_values *old,
3456 const struct ilk_wm_values *new)
3458 unsigned int dirty = 0;
3462 for_each_pipe(dev_priv, pipe) {
3463 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3464 dirty |= WM_DIRTY_LINETIME(pipe);
3465 /* Must disable LP1+ watermarks too */
3466 dirty |= WM_DIRTY_LP_ALL;
3469 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3470 dirty |= WM_DIRTY_PIPE(pipe);
3471 /* Must disable LP1+ watermarks too */
3472 dirty |= WM_DIRTY_LP_ALL;
3476 if (old->enable_fbc_wm != new->enable_fbc_wm) {
3477 dirty |= WM_DIRTY_FBC;
3478 /* Must disable LP1+ watermarks too */
3479 dirty |= WM_DIRTY_LP_ALL;
3482 if (old->partitioning != new->partitioning) {
3483 dirty |= WM_DIRTY_DDB;
3484 /* Must disable LP1+ watermarks too */
3485 dirty |= WM_DIRTY_LP_ALL;
3488 /* LP1+ watermarks already deemed dirty, no need to continue */
3489 if (dirty & WM_DIRTY_LP_ALL)
3492 /* Find the lowest numbered LP1+ watermark in need of an update... */
3493 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3494 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3495 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3499 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3500 for (; wm_lp <= 3; wm_lp++)
3501 dirty |= WM_DIRTY_LP(wm_lp);
3506 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3509 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3510 bool changed = false;
3512 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3513 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3514 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3517 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3518 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3519 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3522 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3523 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3524 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3529 * Don't touch WM1S_LP_EN here.
3530 * Doing so could cause underruns.
3537 * The spec says we shouldn't write when we don't need, because every write
3538 * causes WMs to be re-evaluated, expending some power.
3540 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3541 struct ilk_wm_values *results)
3543 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3547 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3551 _ilk_disable_lp_wm(dev_priv, dirty);
3553 if (dirty & WM_DIRTY_PIPE(PIPE_A))
3554 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3555 if (dirty & WM_DIRTY_PIPE(PIPE_B))
3556 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3557 if (dirty & WM_DIRTY_PIPE(PIPE_C))
3558 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3560 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3561 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3562 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3563 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3564 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3565 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3567 if (dirty & WM_DIRTY_DDB) {
3568 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3569 val = I915_READ(WM_MISC);
3570 if (results->partitioning == INTEL_DDB_PART_1_2)
3571 val &= ~WM_MISC_DATA_PARTITION_5_6;
3573 val |= WM_MISC_DATA_PARTITION_5_6;
3574 I915_WRITE(WM_MISC, val);
3576 val = I915_READ(DISP_ARB_CTL2);
3577 if (results->partitioning == INTEL_DDB_PART_1_2)
3578 val &= ~DISP_DATA_PARTITION_5_6;
3580 val |= DISP_DATA_PARTITION_5_6;
3581 I915_WRITE(DISP_ARB_CTL2, val);
3585 if (dirty & WM_DIRTY_FBC) {
3586 val = I915_READ(DISP_ARB_CTL);
3587 if (results->enable_fbc_wm)
3588 val &= ~DISP_FBC_WM_DIS;
3590 val |= DISP_FBC_WM_DIS;
3591 I915_WRITE(DISP_ARB_CTL, val);
3594 if (dirty & WM_DIRTY_LP(1) &&
3595 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3596 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3598 if (INTEL_GEN(dev_priv) >= 7) {
3599 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3600 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3601 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3602 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3605 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3606 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3607 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3608 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3609 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3610 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3612 dev_priv->wm.hw = *results;
3615 bool ilk_disable_lp_wm(struct drm_device *dev)
3617 struct drm_i915_private *dev_priv = to_i915(dev);
3619 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3622 static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
3626 /* Slice 1 will always be enabled */
3629 /* Gen prior to GEN11 have only one DBuf slice */
3630 if (INTEL_GEN(dev_priv) < 11)
3631 return enabled_slices;
3634 * FIXME: for now we'll only ever use 1 slice; pretend that we have
3635 * only that 1 slice enabled until we have a proper way for on-demand
3636 * toggling of the second slice.
3638 if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
3641 return enabled_slices;
3645 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3646 * so assume we'll always need it in order to avoid underruns.
3648 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3650 return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
3654 intel_has_sagv(struct drm_i915_private *dev_priv)
3656 return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
3657 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3661 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3662 * depending on power and performance requirements. The display engine access
3663 * to system memory is blocked during the adjustment time. Because of the
3664 * blocking time, having this enabled can cause full system hangs and/or pipe
3665 * underruns if we don't meet all of the following requirements:
3667 * - <= 1 pipe enabled
3668 * - All planes can enable watermarks for latencies >= SAGV engine block time
3669 * - We're not using an interlaced display configuration
3672 intel_enable_sagv(struct drm_i915_private *dev_priv)
3676 if (!intel_has_sagv(dev_priv))
3679 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3682 DRM_DEBUG_KMS("Enabling SAGV\n");
3683 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3686 /* We don't need to wait for SAGV when enabling */
3689 * Some skl systems, pre-release machines in particular,
3690 * don't actually have SAGV.
3692 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3693 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3694 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3696 } else if (ret < 0) {
3697 DRM_ERROR("Failed to enable SAGV\n");
3701 dev_priv->sagv_status = I915_SAGV_ENABLED;
3706 intel_disable_sagv(struct drm_i915_private *dev_priv)
3710 if (!intel_has_sagv(dev_priv))
3713 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3716 DRM_DEBUG_KMS("Disabling SAGV\n");
3717 /* bspec says to keep retrying for at least 1 ms */
3718 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3720 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3723 * Some skl systems, pre-release machines in particular,
3724 * don't actually have SAGV.
3726 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3727 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3728 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3730 } else if (ret < 0) {
3731 DRM_ERROR("Failed to disable SAGV (%d)\n", ret);
3735 dev_priv->sagv_status = I915_SAGV_DISABLED;
3739 bool intel_can_enable_sagv(struct intel_atomic_state *state)
3741 struct drm_device *dev = state->base.dev;
3742 struct drm_i915_private *dev_priv = to_i915(dev);
3743 struct intel_crtc *crtc;
3744 struct intel_plane *plane;
3745 struct intel_crtc_state *crtc_state;
3748 int sagv_block_time_us;
3750 if (!intel_has_sagv(dev_priv))
3753 if (IS_GEN(dev_priv, 9))
3754 sagv_block_time_us = 30;
3755 else if (IS_GEN(dev_priv, 10))
3756 sagv_block_time_us = 20;
3758 sagv_block_time_us = 10;
3761 * If there are no active CRTCs, no additional checks need be performed
3763 if (hweight32(state->active_crtcs) == 0)
3767 * SKL+ workaround: bspec recommends we disable SAGV when we have
3768 * more then one pipe enabled
3770 if (hweight32(state->active_crtcs) > 1)
3773 /* Since we're now guaranteed to only have one active CRTC... */
3774 pipe = ffs(state->active_crtcs) - 1;
3775 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3776 crtc_state = to_intel_crtc_state(crtc->base.state);
3778 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3781 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3782 struct skl_plane_wm *wm =
3783 &crtc_state->wm.skl.optimal.planes[plane->id];
3785 /* Skip this plane if it's not enabled */
3786 if (!wm->wm[0].plane_en)
3789 /* Find the highest enabled wm level for this plane */
3790 for (level = ilk_wm_max_level(dev_priv);
3791 !wm->wm[level].plane_en; --level)
3794 latency = dev_priv->wm.skl_latency[level];
3796 if (skl_needs_memory_bw_wa(dev_priv) &&
3797 plane->base.state->fb->modifier ==
3798 I915_FORMAT_MOD_X_TILED)
3802 * If any of the planes on this pipe don't enable wm levels that
3803 * incur memory latencies higher than sagv_block_time_us we
3804 * can't enable SAGV.
3806 if (latency < sagv_block_time_us)
3813 static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
3814 const struct intel_crtc_state *crtc_state,
3815 const u64 total_data_rate,
3816 const int num_active,
3817 struct skl_ddb_allocation *ddb)
3819 const struct drm_display_mode *adjusted_mode;
3821 u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3823 WARN_ON(ddb_size == 0);
3825 if (INTEL_GEN(dev_priv) < 11)
3826 return ddb_size - 4; /* 4 blocks for bypass path allocation */
3828 adjusted_mode = &crtc_state->base.adjusted_mode;
3829 total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
3832 * 12GB/s is maximum BW supported by single DBuf slice.
3834 * FIXME dbuf slice code is broken:
3835 * - must wait for planes to stop using the slice before powering it off
3836 * - plane straddling both slices is illegal in multi-pipe scenarios
3837 * - should validate we stay within the hw bandwidth limits
3839 if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
3840 ddb->enabled_slices = 2;
3842 ddb->enabled_slices = 1;
3850 skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
3851 const struct intel_crtc_state *crtc_state,
3852 const u64 total_data_rate,
3853 struct skl_ddb_allocation *ddb,
3854 struct skl_ddb_entry *alloc, /* out */
3855 int *num_active /* out */)
3857 struct drm_atomic_state *state = crtc_state->base.state;
3858 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3859 struct drm_crtc *for_crtc = crtc_state->base.crtc;
3860 const struct intel_crtc *crtc;
3861 u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
3862 enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
3866 if (WARN_ON(!state) || !crtc_state->base.active) {
3869 *num_active = hweight32(dev_priv->active_crtcs);
3873 if (intel_state->active_pipe_changes)
3874 *num_active = hweight32(intel_state->active_crtcs);
3876 *num_active = hweight32(dev_priv->active_crtcs);
3878 ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
3882 * If the state doesn't change the active CRTC's or there is no
3883 * modeset request, then there's no need to recalculate;
3884 * the existing pipe allocation limits should remain unchanged.
3885 * Note that we're safe from racing commits since any racing commit
3886 * that changes the active CRTC list or do modeset would need to
3887 * grab _all_ crtc locks, including the one we currently hold.
3889 if (!intel_state->active_pipe_changes && !intel_state->modeset) {
3891 * alloc may be cleared by clear_intel_crtc_state,
3892 * copy from old state to be sure
3894 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3899 * Watermark/ddb requirement highly depends upon width of the
3900 * framebuffer, So instead of allocating DDB equally among pipes
3901 * distribute DDB based on resolution/width of the display.
3903 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
3904 const struct drm_display_mode *adjusted_mode =
3905 &crtc_state->base.adjusted_mode;
3906 enum pipe pipe = crtc->pipe;
3907 int hdisplay, vdisplay;
3909 if (!crtc_state->base.enable)
3912 drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
3913 total_width += hdisplay;
3915 if (pipe < for_pipe)
3916 width_before_pipe += hdisplay;
3917 else if (pipe == for_pipe)
3918 pipe_width = hdisplay;
3921 alloc->start = ddb_size * width_before_pipe / total_width;
3922 alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
3925 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
3926 int width, const struct drm_format_info *format,
3927 u64 modifier, unsigned int rotation,
3928 u32 plane_pixel_rate, struct skl_wm_params *wp,
3930 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
3932 const struct skl_wm_params *wp,
3933 const struct skl_wm_level *result_prev,
3934 struct skl_wm_level *result /* out */);
3937 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
3940 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
3941 int level, max_level = ilk_wm_max_level(dev_priv);
3942 struct skl_wm_level wm = {};
3943 int ret, min_ddb_alloc = 0;
3944 struct skl_wm_params wp;
3946 ret = skl_compute_wm_params(crtc_state, 256,
3947 drm_format_info(DRM_FORMAT_ARGB8888),
3948 DRM_FORMAT_MOD_LINEAR,
3950 crtc_state->pixel_rate, &wp, 0);
3953 for (level = 0; level <= max_level; level++) {
3954 skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
3955 if (wm.min_ddb_alloc == U16_MAX)
3958 min_ddb_alloc = wm.min_ddb_alloc;
3961 return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
3964 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
3965 struct skl_ddb_entry *entry, u32 reg)
3968 entry->start = reg & DDB_ENTRY_MASK;
3969 entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
3976 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
3977 const enum pipe pipe,
3978 const enum plane_id plane_id,
3979 struct skl_ddb_entry *ddb_y,
3980 struct skl_ddb_entry *ddb_uv)
3985 /* Cursor doesn't support NV12/planar, so no extra calculation needed */
3986 if (plane_id == PLANE_CURSOR) {
3987 val = I915_READ(CUR_BUF_CFG(pipe));
3988 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
3992 val = I915_READ(PLANE_CTL(pipe, plane_id));
3994 /* No DDB allocated for disabled planes */
3995 if (val & PLANE_CTL_ENABLE)
3996 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
3997 val & PLANE_CTL_ORDER_RGBX,
3998 val & PLANE_CTL_ALPHA_MASK);
4000 if (INTEL_GEN(dev_priv) >= 11) {
4001 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4002 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4004 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4005 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4007 if (is_planar_yuv_format(fourcc))
4010 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4011 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4015 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4016 struct skl_ddb_entry *ddb_y,
4017 struct skl_ddb_entry *ddb_uv)
4019 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4020 enum intel_display_power_domain power_domain;
4021 enum pipe pipe = crtc->pipe;
4022 intel_wakeref_t wakeref;
4023 enum plane_id plane_id;
4025 power_domain = POWER_DOMAIN_PIPE(pipe);
4026 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4030 for_each_plane_id_on_crtc(crtc, plane_id)
4031 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4036 intel_display_power_put(dev_priv, power_domain, wakeref);
4039 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
4040 struct skl_ddb_allocation *ddb /* out */)
4042 ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
4046 * Determines the downscale amount of a plane for the purposes of watermark calculations.
4047 * The bspec defines downscale amount as:
4050 * Horizontal down scale amount = maximum[1, Horizontal source size /
4051 * Horizontal destination size]
4052 * Vertical down scale amount = maximum[1, Vertical source size /
4053 * Vertical destination size]
4054 * Total down scale amount = Horizontal down scale amount *
4055 * Vertical down scale amount
4058 * Return value is provided in 16.16 fixed point form to retain fractional part.
4059 * Caller should take care of dividing & rounding off the value.
4061 static uint_fixed_16_16_t
4062 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4063 const struct intel_plane_state *plane_state)
4065 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4066 u32 src_w, src_h, dst_w, dst_h;
4067 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4068 uint_fixed_16_16_t downscale_h, downscale_w;
4070 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
4071 return u32_to_fixed16(0);
4073 /* n.b., src is 16.16 fixed point, dst is whole integer */
4074 if (plane->id == PLANE_CURSOR) {
4076 * Cursors only support 0/180 degree rotation,
4077 * hence no need to account for rotation here.
4079 src_w = plane_state->base.src_w >> 16;
4080 src_h = plane_state->base.src_h >> 16;
4081 dst_w = plane_state->base.crtc_w;
4082 dst_h = plane_state->base.crtc_h;
4085 * Src coordinates are already rotated by 270 degrees for
4086 * the 90/270 degree plane rotation cases (to match the
4087 * GTT mapping), hence no need to account for rotation here.
4089 src_w = drm_rect_width(&plane_state->base.src) >> 16;
4090 src_h = drm_rect_height(&plane_state->base.src) >> 16;
4091 dst_w = drm_rect_width(&plane_state->base.dst);
4092 dst_h = drm_rect_height(&plane_state->base.dst);
4095 fp_w_ratio = div_fixed16(src_w, dst_w);
4096 fp_h_ratio = div_fixed16(src_h, dst_h);
4097 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4098 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4100 return mul_fixed16(downscale_w, downscale_h);
4103 static uint_fixed_16_16_t
4104 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
4106 uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
4108 if (!crtc_state->base.enable)
4109 return pipe_downscale;
4111 if (crtc_state->pch_pfit.enabled) {
4112 u32 src_w, src_h, dst_w, dst_h;
4113 u32 pfit_size = crtc_state->pch_pfit.size;
4114 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4115 uint_fixed_16_16_t downscale_h, downscale_w;
4117 src_w = crtc_state->pipe_src_w;
4118 src_h = crtc_state->pipe_src_h;
4119 dst_w = pfit_size >> 16;
4120 dst_h = pfit_size & 0xffff;
4122 if (!dst_w || !dst_h)
4123 return pipe_downscale;
4125 fp_w_ratio = div_fixed16(src_w, dst_w);
4126 fp_h_ratio = div_fixed16(src_h, dst_h);
4127 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4128 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4130 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
4133 return pipe_downscale;
4136 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
4137 struct intel_crtc_state *crtc_state)
4139 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4140 struct drm_atomic_state *state = crtc_state->base.state;
4141 struct drm_plane *plane;
4142 const struct drm_plane_state *drm_plane_state;
4143 int crtc_clock, dotclk;
4144 u32 pipe_max_pixel_rate;
4145 uint_fixed_16_16_t pipe_downscale;
4146 uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
4148 if (!crtc_state->base.enable)
4151 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4152 uint_fixed_16_16_t plane_downscale;
4153 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
4155 const struct intel_plane_state *plane_state =
4156 to_intel_plane_state(drm_plane_state);
4158 if (!intel_wm_plane_visible(crtc_state, plane_state))
4161 if (WARN_ON(!plane_state->base.fb))
4164 plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
4165 bpp = plane_state->base.fb->format->cpp[0] * 8;
4167 plane_downscale = mul_fixed16(plane_downscale,
4170 max_downscale = max_fixed16(plane_downscale, max_downscale);
4172 pipe_downscale = skl_pipe_downscale_amount(crtc_state);
4174 pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
4176 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
4177 dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
4179 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
4182 pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
4184 if (pipe_max_pixel_rate < crtc_clock) {
4185 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
4193 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4194 const struct intel_plane_state *plane_state,
4197 struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
4199 u32 width = 0, height = 0;
4200 struct drm_framebuffer *fb;
4202 uint_fixed_16_16_t down_scale_amount;
4205 if (!plane_state->base.visible)
4208 fb = plane_state->base.fb;
4209 format = fb->format->format;
4211 if (intel_plane->id == PLANE_CURSOR)
4213 if (plane == 1 && !is_planar_yuv_format(format))
4217 * Src coordinates are already rotated by 270 degrees for
4218 * the 90/270 degree plane rotation cases (to match the
4219 * GTT mapping), hence no need to account for rotation here.
4221 width = drm_rect_width(&plane_state->base.src) >> 16;
4222 height = drm_rect_height(&plane_state->base.src) >> 16;
4224 /* UV plane does 1/2 pixel sub-sampling */
4225 if (plane == 1 && is_planar_yuv_format(format)) {
4230 data_rate = width * height;
4232 down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4234 rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4236 rate *= fb->format->cpp[plane];
4241 skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4242 u64 *plane_data_rate,
4243 u64 *uv_plane_data_rate)
4245 struct drm_atomic_state *state = crtc_state->base.state;
4246 struct drm_plane *plane;
4247 const struct drm_plane_state *drm_plane_state;
4248 u64 total_data_rate = 0;
4250 if (WARN_ON(!state))
4253 /* Calculate and cache data rate for each plane */
4254 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4255 enum plane_id plane_id = to_intel_plane(plane)->id;
4256 const struct intel_plane_state *plane_state =
4257 to_intel_plane_state(drm_plane_state);
4261 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4262 plane_data_rate[plane_id] = rate;
4263 total_data_rate += rate;
4266 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4267 uv_plane_data_rate[plane_id] = rate;
4268 total_data_rate += rate;
4271 return total_data_rate;
4275 icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4276 u64 *plane_data_rate)
4278 struct drm_plane *plane;
4279 const struct drm_plane_state *drm_plane_state;
4280 u64 total_data_rate = 0;
4282 if (WARN_ON(!crtc_state->base.state))
4285 /* Calculate and cache data rate for each plane */
4286 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
4287 const struct intel_plane_state *plane_state =
4288 to_intel_plane_state(drm_plane_state);
4289 enum plane_id plane_id = to_intel_plane(plane)->id;
4292 if (!plane_state->linked_plane) {
4293 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4294 plane_data_rate[plane_id] = rate;
4295 total_data_rate += rate;
4297 enum plane_id y_plane_id;
4300 * The slave plane might not iterate in
4301 * drm_atomic_crtc_state_for_each_plane_state(),
4302 * and needs the master plane state which may be
4303 * NULL if we try get_new_plane_state(), so we
4304 * always calculate from the master.
4306 if (plane_state->slave)
4309 /* Y plane rate is calculated on the slave */
4310 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4311 y_plane_id = plane_state->linked_plane->id;
4312 plane_data_rate[y_plane_id] = rate;
4313 total_data_rate += rate;
4315 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4316 plane_data_rate[plane_id] = rate;
4317 total_data_rate += rate;
4321 return total_data_rate;
4325 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
4326 struct skl_ddb_allocation *ddb /* out */)
4328 struct drm_atomic_state *state = crtc_state->base.state;
4329 struct drm_crtc *crtc = crtc_state->base.crtc;
4330 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4332 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
4333 u16 alloc_size, start = 0;
4334 u16 total[I915_MAX_PLANES] = {};
4335 u16 uv_total[I915_MAX_PLANES] = {};
4336 u64 total_data_rate;
4337 enum plane_id plane_id;
4339 u64 plane_data_rate[I915_MAX_PLANES] = {};
4340 u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
4344 /* Clear the partitioning for disabled planes. */
4345 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4346 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4348 if (WARN_ON(!state))
4351 if (!crtc_state->base.active) {
4352 alloc->start = alloc->end = 0;
4356 if (INTEL_GEN(dev_priv) >= 11)
4358 icl_get_total_relative_data_rate(crtc_state,
4362 skl_get_total_relative_data_rate(crtc_state,
4364 uv_plane_data_rate);
4367 skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
4368 ddb, alloc, &num_active);
4369 alloc_size = skl_ddb_entry_size(alloc);
4370 if (alloc_size == 0)
4373 /* Allocate fixed number of blocks for cursor. */
4374 total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
4375 alloc_size -= total[PLANE_CURSOR];
4376 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
4377 alloc->end - total[PLANE_CURSOR];
4378 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
4380 if (total_data_rate == 0)
4384 * Find the highest watermark level for which we can satisfy the block
4385 * requirement of active planes.
4387 for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
4389 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4390 const struct skl_plane_wm *wm =
4391 &crtc_state->wm.skl.optimal.planes[plane_id];
4393 if (plane_id == PLANE_CURSOR) {
4394 if (WARN_ON(wm->wm[level].min_ddb_alloc >
4395 total[PLANE_CURSOR])) {
4402 blocks += wm->wm[level].min_ddb_alloc;
4403 blocks += wm->uv_wm[level].min_ddb_alloc;
4406 if (blocks <= alloc_size) {
4407 alloc_size -= blocks;
4413 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4414 DRM_DEBUG_KMS("minimum required %d/%d\n", blocks,
4420 * Grant each plane the blocks it requires at the highest achievable
4421 * watermark level, plus an extra share of the leftover blocks
4422 * proportional to its relative data rate.
4424 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4425 const struct skl_plane_wm *wm =
4426 &crtc_state->wm.skl.optimal.planes[plane_id];
4430 if (plane_id == PLANE_CURSOR)
4434 * We've accounted for all active planes; remaining planes are
4437 if (total_data_rate == 0)
4440 rate = plane_data_rate[plane_id];
4441 extra = min_t(u16, alloc_size,
4442 DIV64_U64_ROUND_UP(alloc_size * rate,
4444 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4445 alloc_size -= extra;
4446 total_data_rate -= rate;
4448 if (total_data_rate == 0)
4451 rate = uv_plane_data_rate[plane_id];
4452 extra = min_t(u16, alloc_size,
4453 DIV64_U64_ROUND_UP(alloc_size * rate,
4455 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4456 alloc_size -= extra;
4457 total_data_rate -= rate;
4459 WARN_ON(alloc_size != 0 || total_data_rate != 0);
4461 /* Set the actual DDB start/end points for each plane */
4462 start = alloc->start;
4463 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4464 struct skl_ddb_entry *plane_alloc =
4465 &crtc_state->wm.skl.plane_ddb_y[plane_id];
4466 struct skl_ddb_entry *uv_plane_alloc =
4467 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
4469 if (plane_id == PLANE_CURSOR)
4472 /* Gen11+ uses a separate plane for UV watermarks */
4473 WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
4475 /* Leave disabled planes at (0,0) */
4476 if (total[plane_id]) {
4477 plane_alloc->start = start;
4478 start += total[plane_id];
4479 plane_alloc->end = start;
4482 if (uv_total[plane_id]) {
4483 uv_plane_alloc->start = start;
4484 start += uv_total[plane_id];
4485 uv_plane_alloc->end = start;
4490 * When we calculated watermark values we didn't know how high
4491 * of a level we'd actually be able to hit, so we just marked
4492 * all levels as "enabled." Go back now and disable the ones
4493 * that aren't actually possible.
4495 for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
4496 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4497 struct skl_plane_wm *wm =
4498 &crtc_state->wm.skl.optimal.planes[plane_id];
4501 * We only disable the watermarks for each plane if
4502 * they exceed the ddb allocation of said plane. This
4503 * is done so that we don't end up touching cursor
4504 * watermarks needlessly when some other plane reduces
4505 * our max possible watermark level.
4507 * Bspec has this to say about the PLANE_WM enable bit:
4508 * "All the watermarks at this level for all enabled
4509 * planes must be enabled before the level will be used."
4510 * So this is actually safe to do.
4512 if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
4513 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
4514 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
4517 * Wa_1408961008:icl, ehl
4518 * Underruns with WM1+ disabled
4520 if (IS_GEN(dev_priv, 11) &&
4521 level == 1 && wm->wm[0].plane_en) {
4522 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
4523 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
4524 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
4530 * Go back and disable the transition watermark if it turns out we
4531 * don't have enough DDB blocks for it.
4533 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4534 struct skl_plane_wm *wm =
4535 &crtc_state->wm.skl.optimal.planes[plane_id];
4537 if (wm->trans_wm.plane_res_b >= total[plane_id])
4538 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
4545 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4546 * for the read latency) and cpp should always be <= 8, so that
4547 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4548 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4550 static uint_fixed_16_16_t
4551 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
4552 u8 cpp, u32 latency, u32 dbuf_block_size)
4554 u32 wm_intermediate_val;
4555 uint_fixed_16_16_t ret;
4558 return FP_16_16_MAX;
4560 wm_intermediate_val = latency * pixel_rate * cpp;
4561 ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
4563 if (INTEL_GEN(dev_priv) >= 10)
4564 ret = add_fixed16_u32(ret, 1);
4569 static uint_fixed_16_16_t
4570 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
4571 uint_fixed_16_16_t plane_blocks_per_line)
4573 u32 wm_intermediate_val;
4574 uint_fixed_16_16_t ret;
4577 return FP_16_16_MAX;
4579 wm_intermediate_val = latency * pixel_rate;
4580 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4581 pipe_htotal * 1000);
4582 ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4586 static uint_fixed_16_16_t
4587 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
4591 uint_fixed_16_16_t linetime_us;
4593 if (!crtc_state->base.active)
4594 return u32_to_fixed16(0);
4596 pixel_rate = crtc_state->pixel_rate;
4598 if (WARN_ON(pixel_rate == 0))
4599 return u32_to_fixed16(0);
4601 crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
4602 linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4608 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
4609 const struct intel_plane_state *plane_state)
4611 u64 adjusted_pixel_rate;
4612 uint_fixed_16_16_t downscale_amount;
4614 /* Shouldn't reach here on disabled planes... */
4615 if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
4619 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4620 * with additional adjustments for plane-specific scaling.
4622 adjusted_pixel_rate = crtc_state->pixel_rate;
4623 downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4625 return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4630 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4631 int width, const struct drm_format_info *format,
4632 u64 modifier, unsigned int rotation,
4633 u32 plane_pixel_rate, struct skl_wm_params *wp,
4636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4640 /* only planar format has two planes */
4641 if (color_plane == 1 && !is_planar_yuv_format(format->format)) {
4642 DRM_DEBUG_KMS("Non planar format have single plane\n");
4646 wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
4647 modifier == I915_FORMAT_MOD_Yf_TILED ||
4648 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4649 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4650 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
4651 wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4652 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4653 wp->is_planar = is_planar_yuv_format(format->format);
4656 if (color_plane == 1 && wp->is_planar)
4659 wp->cpp = format->cpp[color_plane];
4660 wp->plane_pixel_rate = plane_pixel_rate;
4662 if (INTEL_GEN(dev_priv) >= 11 &&
4663 modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
4664 wp->dbuf_block_size = 256;
4666 wp->dbuf_block_size = 512;
4668 if (drm_rotation_90_or_270(rotation)) {
4671 wp->y_min_scanlines = 16;
4674 wp->y_min_scanlines = 8;
4677 wp->y_min_scanlines = 4;
4680 MISSING_CASE(wp->cpp);
4684 wp->y_min_scanlines = 4;
4687 if (skl_needs_memory_bw_wa(dev_priv))
4688 wp->y_min_scanlines *= 2;
4690 wp->plane_bytes_per_line = wp->width * wp->cpp;
4692 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
4693 wp->y_min_scanlines,
4694 wp->dbuf_block_size);
4696 if (INTEL_GEN(dev_priv) >= 10)
4699 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4700 wp->y_min_scanlines);
4701 } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
4702 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4703 wp->dbuf_block_size);
4704 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4706 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
4707 wp->dbuf_block_size) + 1;
4708 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4711 wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4712 wp->plane_blocks_per_line);
4714 wp->linetime_us = fixed16_to_u32_round_up(
4715 intel_get_linetime_us(crtc_state));
4721 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
4722 const struct intel_plane_state *plane_state,
4723 struct skl_wm_params *wp, int color_plane)
4725 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
4726 const struct drm_framebuffer *fb = plane_state->base.fb;
4729 if (plane->id == PLANE_CURSOR) {
4730 width = plane_state->base.crtc_w;
4733 * Src coordinates are already rotated by 270 degrees for
4734 * the 90/270 degree plane rotation cases (to match the
4735 * GTT mapping), hence no need to account for rotation here.
4737 width = drm_rect_width(&plane_state->base.src) >> 16;
4740 return skl_compute_wm_params(crtc_state, width,
4741 fb->format, fb->modifier,
4742 plane_state->base.rotation,
4743 skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
4747 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
4749 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4752 /* The number of lines are ignored for the level 0 watermark. */
4756 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4758 const struct skl_wm_params *wp,
4759 const struct skl_wm_level *result_prev,
4760 struct skl_wm_level *result /* out */)
4762 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4763 u32 latency = dev_priv->wm.skl_latency[level];
4764 uint_fixed_16_16_t method1, method2;
4765 uint_fixed_16_16_t selected_result;
4766 u32 res_blocks, res_lines, min_ddb_alloc = 0;
4770 result->min_ddb_alloc = U16_MAX;
4775 * WaIncreaseLatencyIPCEnabled: kbl,cfl
4776 * Display WA #1141: kbl,cfl
4778 if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) ||
4779 dev_priv->ipc_enabled)
4782 if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
4785 method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
4786 wp->cpp, latency, wp->dbuf_block_size);
4787 method2 = skl_wm_method2(wp->plane_pixel_rate,
4788 crtc_state->base.adjusted_mode.crtc_htotal,
4790 wp->plane_blocks_per_line);
4793 selected_result = max_fixed16(method2, wp->y_tile_minimum);
4795 if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
4796 wp->dbuf_block_size < 1) &&
4797 (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
4798 selected_result = method2;
4799 } else if (latency >= wp->linetime_us) {
4800 if (IS_GEN(dev_priv, 9) &&
4801 !IS_GEMINILAKE(dev_priv))
4802 selected_result = min_fixed16(method1, method2);
4804 selected_result = method2;
4806 selected_result = method1;
4810 res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4811 res_lines = div_round_up_fixed16(selected_result,
4812 wp->plane_blocks_per_line);
4814 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
4815 /* Display WA #1125: skl,bxt,kbl */
4816 if (level == 0 && wp->rc_surface)
4818 fixed16_to_u32_round_up(wp->y_tile_minimum);
4820 /* Display WA #1126: skl,bxt,kbl */
4821 if (level >= 1 && level <= 7) {
4824 fixed16_to_u32_round_up(wp->y_tile_minimum);
4825 res_lines += wp->y_min_scanlines;
4831 * Make sure result blocks for higher latency levels are
4832 * atleast as high as level below the current level.
4833 * Assumption in DDB algorithm optimization for special
4834 * cases. Also covers Display WA #1125 for RC.
4836 if (result_prev->plane_res_b > res_blocks)
4837 res_blocks = result_prev->plane_res_b;
4841 if (INTEL_GEN(dev_priv) >= 11) {
4845 if (res_lines % wp->y_min_scanlines == 0)
4846 extra_lines = wp->y_min_scanlines;
4848 extra_lines = wp->y_min_scanlines * 2 -
4849 res_lines % wp->y_min_scanlines;
4851 min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
4852 wp->plane_blocks_per_line);
4854 min_ddb_alloc = res_blocks +
4855 DIV_ROUND_UP(res_blocks, 10);
4859 if (!skl_wm_has_lines(dev_priv, level))
4862 if (res_lines > 31) {
4864 result->min_ddb_alloc = U16_MAX;
4869 * If res_lines is valid, assume we can use this watermark level
4870 * for now. We'll come back and disable it after we calculate the
4871 * DDB allocation if it turns out we don't actually have enough
4872 * blocks to satisfy it.
4874 result->plane_res_b = res_blocks;
4875 result->plane_res_l = res_lines;
4876 /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
4877 result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
4878 result->plane_en = true;
4882 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
4883 const struct skl_wm_params *wm_params,
4884 struct skl_wm_level *levels)
4886 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
4887 int level, max_level = ilk_wm_max_level(dev_priv);
4888 struct skl_wm_level *result_prev = &levels[0];
4890 for (level = 0; level <= max_level; level++) {
4891 struct skl_wm_level *result = &levels[level];
4893 skl_compute_plane_wm(crtc_state, level, wm_params,
4894 result_prev, result);
4896 result_prev = result;
4901 skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
4903 struct drm_atomic_state *state = crtc_state->base.state;
4904 struct drm_i915_private *dev_priv = to_i915(state->dev);
4905 uint_fixed_16_16_t linetime_us;
4908 linetime_us = intel_get_linetime_us(crtc_state);
4909 linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4911 /* Display WA #1135: BXT:ALL GLK:ALL */
4912 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
4918 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
4919 const struct skl_wm_params *wp,
4920 struct skl_plane_wm *wm)
4922 struct drm_device *dev = crtc_state->base.crtc->dev;
4923 const struct drm_i915_private *dev_priv = to_i915(dev);
4924 u16 trans_min, trans_y_tile_min;
4925 const u16 trans_amount = 10; /* This is configurable amount */
4926 u16 wm0_sel_res_b, trans_offset_b, res_blocks;
4928 /* Transition WM are not recommended by HW team for GEN9 */
4929 if (INTEL_GEN(dev_priv) <= 9)
4932 /* Transition WM don't make any sense if ipc is disabled */
4933 if (!dev_priv->ipc_enabled)
4937 if (INTEL_GEN(dev_priv) >= 11)
4940 trans_offset_b = trans_min + trans_amount;
4943 * The spec asks for Selected Result Blocks for wm0 (the real value),
4944 * not Result Blocks (the integer value). Pay attention to the capital
4945 * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
4946 * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
4947 * and since we later will have to get the ceiling of the sum in the
4948 * transition watermarks calculation, we can just pretend Selected
4949 * Result Blocks is Result Blocks minus 1 and it should work for the
4950 * current platforms.
4952 wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
4956 (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
4957 res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
4960 res_blocks = wm0_sel_res_b + trans_offset_b;
4962 /* WA BUG:1938466 add one block for non y-tile planes */
4963 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
4969 * Just assume we can enable the transition watermark. After
4970 * computing the DDB we'll come back and disable it if that
4971 * assumption turns out to be false.
4973 wm->trans_wm.plane_res_b = res_blocks + 1;
4974 wm->trans_wm.plane_en = true;
4977 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
4978 const struct intel_plane_state *plane_state,
4979 enum plane_id plane_id, int color_plane)
4981 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
4982 struct skl_wm_params wm_params;
4985 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
4986 &wm_params, color_plane);
4990 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
4991 skl_compute_transition_wm(crtc_state, &wm_params, wm);
4996 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
4997 const struct intel_plane_state *plane_state,
4998 enum plane_id plane_id)
5000 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5001 struct skl_wm_params wm_params;
5004 wm->is_planar = true;
5006 /* uv plane watermarks must also be validated for NV12/Planar */
5007 ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5012 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5017 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5018 const struct intel_plane_state *plane_state)
5020 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
5021 const struct drm_framebuffer *fb = plane_state->base.fb;
5022 enum plane_id plane_id = plane->id;
5025 if (!intel_wm_plane_visible(crtc_state, plane_state))
5028 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5033 if (fb->format->is_yuv && fb->format->num_planes > 1) {
5034 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5043 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5044 const struct intel_plane_state *plane_state)
5046 enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
5049 /* Watermarks calculated in master */
5050 if (plane_state->slave)
5053 if (plane_state->linked_plane) {
5054 const struct drm_framebuffer *fb = plane_state->base.fb;
5055 enum plane_id y_plane_id = plane_state->linked_plane->id;
5057 WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
5058 WARN_ON(!fb->format->is_yuv ||
5059 fb->format->num_planes == 1);
5061 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5066 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5070 } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5071 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5080 static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
5082 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5083 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5084 struct drm_plane *plane;
5085 const struct drm_plane_state *drm_plane_state;
5089 * We'll only calculate watermarks for planes that are actually
5090 * enabled, so make sure all other planes are set as disabled.
5092 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
5094 drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
5095 &crtc_state->base) {
5096 const struct intel_plane_state *plane_state =
5097 to_intel_plane_state(drm_plane_state);
5099 if (INTEL_GEN(dev_priv) >= 11)
5100 ret = icl_build_plane_wm(crtc_state, plane_state);
5102 ret = skl_build_plane_wm(crtc_state, plane_state);
5107 pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
5112 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5114 const struct skl_ddb_entry *entry)
5117 I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start);
5119 I915_WRITE_FW(reg, 0);
5122 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5124 const struct skl_wm_level *level)
5128 if (level->plane_en)
5130 if (level->ignore_lines)
5131 val |= PLANE_WM_IGNORE_LINES;
5132 val |= level->plane_res_b;
5133 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
5135 I915_WRITE_FW(reg, val);
5138 void skl_write_plane_wm(struct intel_plane *plane,
5139 const struct intel_crtc_state *crtc_state)
5141 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5142 int level, max_level = ilk_wm_max_level(dev_priv);
5143 enum plane_id plane_id = plane->id;
5144 enum pipe pipe = plane->pipe;
5145 const struct skl_plane_wm *wm =
5146 &crtc_state->wm.skl.optimal.planes[plane_id];
5147 const struct skl_ddb_entry *ddb_y =
5148 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5149 const struct skl_ddb_entry *ddb_uv =
5150 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5152 for (level = 0; level <= max_level; level++) {
5153 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5156 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5159 if (INTEL_GEN(dev_priv) >= 11) {
5160 skl_ddb_entry_write(dev_priv,
5161 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5166 swap(ddb_y, ddb_uv);
5168 skl_ddb_entry_write(dev_priv,
5169 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5170 skl_ddb_entry_write(dev_priv,
5171 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5174 void skl_write_cursor_wm(struct intel_plane *plane,
5175 const struct intel_crtc_state *crtc_state)
5177 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5178 int level, max_level = ilk_wm_max_level(dev_priv);
5179 enum plane_id plane_id = plane->id;
5180 enum pipe pipe = plane->pipe;
5181 const struct skl_plane_wm *wm =
5182 &crtc_state->wm.skl.optimal.planes[plane_id];
5183 const struct skl_ddb_entry *ddb =
5184 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5186 for (level = 0; level <= max_level; level++) {
5187 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5190 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5192 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5195 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5196 const struct skl_wm_level *l2)
5198 return l1->plane_en == l2->plane_en &&
5199 l1->ignore_lines == l2->ignore_lines &&
5200 l1->plane_res_l == l2->plane_res_l &&
5201 l1->plane_res_b == l2->plane_res_b;
5204 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5205 const struct skl_plane_wm *wm1,
5206 const struct skl_plane_wm *wm2)
5208 int level, max_level = ilk_wm_max_level(dev_priv);
5210 for (level = 0; level <= max_level; level++) {
5211 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
5212 !skl_wm_level_equals(&wm1->uv_wm[level], &wm2->uv_wm[level]))
5216 return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
5219 static bool skl_pipe_wm_equals(struct intel_crtc *crtc,
5220 const struct skl_pipe_wm *wm1,
5221 const struct skl_pipe_wm *wm2)
5223 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5224 enum plane_id plane_id;
5226 for_each_plane_id_on_crtc(crtc, plane_id) {
5227 if (!skl_plane_wm_equals(dev_priv,
5228 &wm1->planes[plane_id],
5229 &wm2->planes[plane_id]))
5233 return wm1->linetime == wm2->linetime;
5236 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5237 const struct skl_ddb_entry *b)
5239 return a->start < b->end && b->start < a->end;
5242 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
5243 const struct skl_ddb_entry *entries,
5244 int num_entries, int ignore_idx)
5248 for (i = 0; i < num_entries; i++) {
5249 if (i != ignore_idx &&
5250 skl_ddb_entries_overlap(ddb, &entries[i]))
5258 pipes_modified(struct intel_atomic_state *state)
5260 struct intel_crtc *crtc;
5261 struct intel_crtc_state *crtc_state;
5264 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
5265 ret |= drm_crtc_mask(&crtc->base);
5271 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5272 struct intel_crtc_state *new_crtc_state)
5274 struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->base.state);
5275 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
5276 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5277 struct intel_plane *plane;
5279 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5280 struct intel_plane_state *plane_state;
5281 enum plane_id plane_id = plane->id;
5283 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5284 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5285 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5286 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5289 plane_state = intel_atomic_get_plane_state(state, plane);
5290 if (IS_ERR(plane_state))
5291 return PTR_ERR(plane_state);
5293 new_crtc_state->update_planes |= BIT(plane_id);
5300 skl_compute_ddb(struct intel_atomic_state *state)
5302 const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5303 struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5304 struct intel_crtc_state *old_crtc_state;
5305 struct intel_crtc_state *new_crtc_state;
5306 struct intel_crtc *crtc;
5309 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
5311 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5312 new_crtc_state, i) {
5313 ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
5317 ret = skl_ddb_add_affected_planes(old_crtc_state,
5326 static char enast(bool enable)
5328 return enable ? '*' : ' ';
5332 skl_print_wm_changes(struct intel_atomic_state *state)
5334 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5335 const struct intel_crtc_state *old_crtc_state;
5336 const struct intel_crtc_state *new_crtc_state;
5337 struct intel_plane *plane;
5338 struct intel_crtc *crtc;
5341 if ((drm_debug & DRM_UT_KMS) == 0)
5344 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5345 new_crtc_state, i) {
5346 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
5348 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5349 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5351 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5352 enum plane_id plane_id = plane->id;
5353 const struct skl_ddb_entry *old, *new;
5355 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5356 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5358 if (skl_ddb_entry_equal(old, new))
5361 DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
5362 plane->base.base.id, plane->base.name,
5363 old->start, old->end, new->start, new->end,
5364 skl_ddb_entry_size(old), skl_ddb_entry_size(new));
5367 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5368 enum plane_id plane_id = plane->id;
5369 const struct skl_plane_wm *old_wm, *new_wm;
5371 old_wm = &old_pipe_wm->planes[plane_id];
5372 new_wm = &new_pipe_wm->planes[plane_id];
5374 if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
5377 DRM_DEBUG_KMS("[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
5378 " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
5379 plane->base.base.id, plane->base.name,
5380 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5381 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5382 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5383 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5384 enast(old_wm->trans_wm.plane_en),
5385 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5386 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5387 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5388 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5389 enast(new_wm->trans_wm.plane_en));
5391 DRM_DEBUG_KMS("[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5392 " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
5393 plane->base.base.id, plane->base.name,
5394 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5395 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5396 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5397 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5398 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5399 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5400 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5401 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5402 enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
5404 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5405 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5406 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5407 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5408 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5409 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5410 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5411 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5412 enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
5414 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5415 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5416 plane->base.base.id, plane->base.name,
5417 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5418 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5419 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5420 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5421 old_wm->trans_wm.plane_res_b,
5422 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5423 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5424 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5425 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5426 new_wm->trans_wm.plane_res_b);
5428 DRM_DEBUG_KMS("[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5429 " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5430 plane->base.base.id, plane->base.name,
5431 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5432 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5433 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5434 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5435 old_wm->trans_wm.min_ddb_alloc,
5436 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5437 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5438 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5439 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5440 new_wm->trans_wm.min_ddb_alloc);
5446 skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed)
5448 struct drm_device *dev = state->base.dev;
5449 const struct drm_i915_private *dev_priv = to_i915(dev);
5450 struct intel_crtc *crtc;
5451 struct intel_crtc_state *crtc_state;
5452 u32 realloc_pipes = pipes_modified(state);
5456 * When we distrust bios wm we always need to recompute to set the
5457 * expected DDB allocations for each CRTC.
5459 if (dev_priv->wm.distrust_bios_wm)
5463 * If this transaction isn't actually touching any CRTC's, don't
5464 * bother with watermark calculation. Note that if we pass this
5465 * test, we're guaranteed to hold at least one CRTC state mutex,
5466 * which means we can safely use values like dev_priv->active_crtcs
5467 * since any racing commits that want to update them would need to
5468 * hold _all_ CRTC state mutexes.
5470 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
5477 * If this is our first atomic update following hardware readout,
5478 * we can't trust the DDB that the BIOS programmed for us. Let's
5479 * pretend that all pipes switched active status so that we'll
5480 * ensure a full DDB recompute.
5482 if (dev_priv->wm.distrust_bios_wm) {
5483 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
5484 state->base.acquire_ctx);
5488 state->active_pipe_changes = ~0;
5491 * We usually only initialize state->active_crtcs if we
5492 * we're doing a modeset; make sure this field is always
5493 * initialized during the sanitization process that happens
5494 * on the first commit too.
5496 if (!state->modeset)
5497 state->active_crtcs = dev_priv->active_crtcs;
5501 * If the modeset changes which CRTC's are active, we need to
5502 * recompute the DDB allocation for *all* active pipes, even
5503 * those that weren't otherwise being modified in any way by this
5504 * atomic commit. Due to the shrinking of the per-pipe allocations
5505 * when new active CRTC's are added, it's possible for a pipe that
5506 * we were already using and aren't changing at all here to suddenly
5507 * become invalid if its DDB needs exceeds its new allocation.
5509 * Note that if we wind up doing a full DDB recompute, we can't let
5510 * any other display updates race with this transaction, so we need
5511 * to grab the lock on *all* CRTC's.
5513 if (state->active_pipe_changes || state->modeset) {
5515 state->wm_results.dirty_pipes = ~0;
5519 * We're not recomputing for the pipes not included in the commit, so
5520 * make sure we start with the current state.
5522 for_each_intel_crtc_mask(dev, crtc, realloc_pipes) {
5523 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5524 if (IS_ERR(crtc_state))
5525 return PTR_ERR(crtc_state);
5532 * To make sure the cursor watermark registers are always consistent
5533 * with our computed state the following scenario needs special
5537 * 2. move cursor entirely offscreen
5540 * Step 2. does call .disable_plane() but does not zero the watermarks
5541 * (since we consider an offscreen cursor still active for the purposes
5542 * of watermarks). Step 3. would not normally call .disable_plane()
5543 * because the actual plane visibility isn't changing, and we don't
5544 * deallocate the cursor ddb until the pipe gets disabled. So we must
5545 * force step 3. to call .disable_plane() to update the watermark
5546 * registers properly.
5548 * Other planes do not suffer from this issues as their watermarks are
5549 * calculated based on the actual plane visibility. The only time this
5550 * can trigger for the other planes is during the initial readout as the
5551 * default value of the watermarks registers is not zero.
5553 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
5554 struct intel_crtc *crtc)
5556 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5557 const struct intel_crtc_state *old_crtc_state =
5558 intel_atomic_get_old_crtc_state(state, crtc);
5559 struct intel_crtc_state *new_crtc_state =
5560 intel_atomic_get_new_crtc_state(state, crtc);
5561 struct intel_plane *plane;
5563 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5564 struct intel_plane_state *plane_state;
5565 enum plane_id plane_id = plane->id;
5568 * Force a full wm update for every plane on modeset.
5569 * Required because the reset value of the wm registers
5570 * is non-zero, whereas we want all disabled planes to
5571 * have zero watermarks. So if we turn off the relevant
5572 * power well the hardware state will go out of sync
5573 * with the software state.
5575 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) &&
5576 skl_plane_wm_equals(dev_priv,
5577 &old_crtc_state->wm.skl.optimal.planes[plane_id],
5578 &new_crtc_state->wm.skl.optimal.planes[plane_id]))
5581 plane_state = intel_atomic_get_plane_state(state, plane);
5582 if (IS_ERR(plane_state))
5583 return PTR_ERR(plane_state);
5585 new_crtc_state->update_planes |= BIT(plane_id);
5592 skl_compute_wm(struct intel_atomic_state *state)
5594 struct intel_crtc *crtc;
5595 struct intel_crtc_state *new_crtc_state;
5596 struct intel_crtc_state *old_crtc_state;
5597 struct skl_ddb_values *results = &state->wm_results;
5598 bool changed = false;
5601 /* Clear all dirty flags */
5602 results->dirty_pipes = 0;
5604 ret = skl_ddb_add_affected_pipes(state, &changed);
5605 if (ret || !changed)
5609 * Calculate WM's for all pipes that are part of this transaction.
5610 * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
5611 * weren't otherwise being modified (and set bits in dirty_pipes) if
5612 * pipe allocations had to change.
5614 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5615 new_crtc_state, i) {
5616 ret = skl_build_pipe_wm(new_crtc_state);
5620 ret = skl_wm_add_affected_planes(state, crtc);
5624 if (!skl_pipe_wm_equals(crtc,
5625 &old_crtc_state->wm.skl.optimal,
5626 &new_crtc_state->wm.skl.optimal))
5627 results->dirty_pipes |= drm_crtc_mask(&crtc->base);
5630 ret = skl_compute_ddb(state);
5634 skl_print_wm_changes(state);
5639 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5640 struct intel_crtc_state *crtc_state)
5642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5643 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5644 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5645 enum pipe pipe = crtc->pipe;
5647 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5650 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5653 static void skl_initial_wm(struct intel_atomic_state *state,
5654 struct intel_crtc_state *crtc_state)
5656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5657 struct drm_device *dev = intel_crtc->base.dev;
5658 struct drm_i915_private *dev_priv = to_i915(dev);
5659 struct skl_ddb_values *results = &state->wm_results;
5661 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5664 mutex_lock(&dev_priv->wm.wm_mutex);
5666 if (crtc_state->base.active_changed)
5667 skl_atomic_update_crtc_wm(state, crtc_state);
5669 mutex_unlock(&dev_priv->wm.wm_mutex);
5672 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
5673 struct intel_wm_config *config)
5675 struct intel_crtc *crtc;
5677 /* Compute the currently _active_ config */
5678 for_each_intel_crtc(&dev_priv->drm, crtc) {
5679 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5681 if (!wm->pipe_enabled)
5684 config->sprites_enabled |= wm->sprites_enabled;
5685 config->sprites_scaled |= wm->sprites_scaled;
5686 config->num_pipes_active++;
5690 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5692 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5693 struct ilk_wm_maximums max;
5694 struct intel_wm_config config = {};
5695 struct ilk_wm_values results = {};
5696 enum intel_ddb_partitioning partitioning;
5698 ilk_compute_wm_config(dev_priv, &config);
5700 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
5701 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
5703 /* 5/6 split only in single pipe config on IVB+ */
5704 if (INTEL_GEN(dev_priv) >= 7 &&
5705 config.num_pipes_active == 1 && config.sprites_enabled) {
5706 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
5707 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
5709 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
5711 best_lp_wm = &lp_wm_1_2;
5714 partitioning = (best_lp_wm == &lp_wm_1_2) ?
5715 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5717 ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
5719 ilk_write_wm_values(dev_priv, &results);
5722 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5723 struct intel_crtc_state *crtc_state)
5725 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5726 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5728 mutex_lock(&dev_priv->wm.wm_mutex);
5729 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
5730 ilk_program_watermarks(dev_priv);
5731 mutex_unlock(&dev_priv->wm.wm_mutex);
5734 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5735 struct intel_crtc_state *crtc_state)
5737 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
5738 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
5740 if (!crtc_state->wm.need_postvbl_update)
5743 mutex_lock(&dev_priv->wm.wm_mutex);
5744 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
5745 ilk_program_watermarks(dev_priv);
5746 mutex_unlock(&dev_priv->wm.wm_mutex);
5749 static inline void skl_wm_level_from_reg_val(u32 val,
5750 struct skl_wm_level *level)
5752 level->plane_en = val & PLANE_WM_EN;
5753 level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
5754 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5755 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5756 PLANE_WM_LINES_MASK;
5759 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
5760 struct skl_pipe_wm *out)
5762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5763 enum pipe pipe = crtc->pipe;
5764 int level, max_level;
5765 enum plane_id plane_id;
5768 max_level = ilk_wm_max_level(dev_priv);
5770 for_each_plane_id_on_crtc(crtc, plane_id) {
5771 struct skl_plane_wm *wm = &out->planes[plane_id];
5773 for (level = 0; level <= max_level; level++) {
5774 if (plane_id != PLANE_CURSOR)
5775 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5777 val = I915_READ(CUR_WM(pipe, level));
5779 skl_wm_level_from_reg_val(val, &wm->wm[level]);
5782 if (plane_id != PLANE_CURSOR)
5783 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5785 val = I915_READ(CUR_WM_TRANS(pipe));
5787 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5793 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5796 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
5798 struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
5799 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5800 struct intel_crtc *crtc;
5801 struct intel_crtc_state *crtc_state;
5803 skl_ddb_get_hw_state(dev_priv, ddb);
5804 for_each_intel_crtc(&dev_priv->drm, crtc) {
5805 crtc_state = to_intel_crtc_state(crtc->base.state);
5807 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
5810 hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
5813 if (dev_priv->active_crtcs) {
5814 /* Fully recompute DDB on first atomic commit */
5815 dev_priv->wm.distrust_bios_wm = true;
5819 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = to_i915(dev);
5823 struct ilk_wm_values *hw = &dev_priv->wm.hw;
5824 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
5825 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
5826 enum pipe pipe = crtc->pipe;
5827 static const i915_reg_t wm0_pipe_reg[] = {
5828 [PIPE_A] = WM0_PIPEA_ILK,
5829 [PIPE_B] = WM0_PIPEB_ILK,
5830 [PIPE_C] = WM0_PIPEC_IVB,
5833 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5834 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5835 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5837 memset(active, 0, sizeof(*active));
5839 active->pipe_enabled = crtc->active;
5841 if (active->pipe_enabled) {
5842 u32 tmp = hw->wm_pipe[pipe];
5845 * For active pipes LP0 watermark is marked as
5846 * enabled, and LP1+ watermaks as disabled since
5847 * we can't really reverse compute them in case
5848 * multiple pipes are active.
5850 active->wm[0].enable = true;
5851 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5852 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5853 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5854 active->linetime = hw->wm_linetime[pipe];
5856 int level, max_level = ilk_wm_max_level(dev_priv);
5859 * For inactive pipes, all watermark levels
5860 * should be marked as enabled but zeroed,
5861 * which is what we'd compute them to.
5863 for (level = 0; level <= max_level; level++)
5864 active->wm[level].enable = true;
5867 crtc->wm.active.ilk = *active;
5870 #define _FW_WM(value, plane) \
5871 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5872 #define _FW_WM_VLV(value, plane) \
5873 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5875 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5876 struct g4x_wm_values *wm)
5880 tmp = I915_READ(DSPFW1);
5881 wm->sr.plane = _FW_WM(tmp, SR);
5882 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5883 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5884 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5886 tmp = I915_READ(DSPFW2);
5887 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5888 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5889 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5890 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5891 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5892 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5894 tmp = I915_READ(DSPFW3);
5895 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5896 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5897 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5898 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5901 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5902 struct vlv_wm_values *wm)
5907 for_each_pipe(dev_priv, pipe) {
5908 tmp = I915_READ(VLV_DDL(pipe));
5910 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5911 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5912 wm->ddl[pipe].plane[PLANE_CURSOR] =
5913 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5914 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5915 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5916 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5917 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5920 tmp = I915_READ(DSPFW1);
5921 wm->sr.plane = _FW_WM(tmp, SR);
5922 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5923 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5924 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5926 tmp = I915_READ(DSPFW2);
5927 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5928 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5929 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5931 tmp = I915_READ(DSPFW3);
5932 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5934 if (IS_CHERRYVIEW(dev_priv)) {
5935 tmp = I915_READ(DSPFW7_CHV);
5936 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5937 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5939 tmp = I915_READ(DSPFW8_CHV);
5940 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5941 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5943 tmp = I915_READ(DSPFW9_CHV);
5944 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5945 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5947 tmp = I915_READ(DSPHOWM);
5948 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5949 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5950 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5951 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5952 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5953 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5954 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5955 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5956 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5957 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5959 tmp = I915_READ(DSPFW7);
5960 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5961 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5963 tmp = I915_READ(DSPHOWM);
5964 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5965 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5966 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5967 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5968 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5969 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5970 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5977 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
5979 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5980 struct intel_crtc *crtc;
5982 g4x_read_wm_values(dev_priv, wm);
5984 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5986 for_each_intel_crtc(&dev_priv->drm, crtc) {
5987 struct intel_crtc_state *crtc_state =
5988 to_intel_crtc_state(crtc->base.state);
5989 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5990 struct g4x_pipe_wm *raw;
5991 enum pipe pipe = crtc->pipe;
5992 enum plane_id plane_id;
5993 int level, max_level;
5995 active->cxsr = wm->cxsr;
5996 active->hpll_en = wm->hpll_en;
5997 active->fbc_en = wm->fbc_en;
5999 active->sr = wm->sr;
6000 active->hpll = wm->hpll;
6002 for_each_plane_id_on_crtc(crtc, plane_id) {
6003 active->wm.plane[plane_id] =
6004 wm->pipe[pipe].plane[plane_id];
6007 if (wm->cxsr && wm->hpll_en)
6008 max_level = G4X_WM_LEVEL_HPLL;
6010 max_level = G4X_WM_LEVEL_SR;
6012 max_level = G4X_WM_LEVEL_NORMAL;
6014 level = G4X_WM_LEVEL_NORMAL;
6015 raw = &crtc_state->wm.g4x.raw[level];
6016 for_each_plane_id_on_crtc(crtc, plane_id)
6017 raw->plane[plane_id] = active->wm.plane[plane_id];
6019 if (++level > max_level)
6022 raw = &crtc_state->wm.g4x.raw[level];
6023 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6024 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6025 raw->plane[PLANE_SPRITE0] = 0;
6026 raw->fbc = active->sr.fbc;
6028 if (++level > max_level)
6031 raw = &crtc_state->wm.g4x.raw[level];
6032 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6033 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6034 raw->plane[PLANE_SPRITE0] = 0;
6035 raw->fbc = active->hpll.fbc;
6038 for_each_plane_id_on_crtc(crtc, plane_id)
6039 g4x_raw_plane_wm_set(crtc_state, level,
6040 plane_id, USHRT_MAX);
6041 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6043 crtc_state->wm.g4x.optimal = *active;
6044 crtc_state->wm.g4x.intermediate = *active;
6046 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6048 wm->pipe[pipe].plane[PLANE_PRIMARY],
6049 wm->pipe[pipe].plane[PLANE_CURSOR],
6050 wm->pipe[pipe].plane[PLANE_SPRITE0]);
6053 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6054 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6055 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6056 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6057 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
6058 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6061 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6063 struct intel_plane *plane;
6064 struct intel_crtc *crtc;
6066 mutex_lock(&dev_priv->wm.wm_mutex);
6068 for_each_intel_plane(&dev_priv->drm, plane) {
6069 struct intel_crtc *crtc =
6070 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6071 struct intel_crtc_state *crtc_state =
6072 to_intel_crtc_state(crtc->base.state);
6073 struct intel_plane_state *plane_state =
6074 to_intel_plane_state(plane->base.state);
6075 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6076 enum plane_id plane_id = plane->id;
6079 if (plane_state->base.visible)
6082 for (level = 0; level < 3; level++) {
6083 struct g4x_pipe_wm *raw =
6084 &crtc_state->wm.g4x.raw[level];
6086 raw->plane[plane_id] = 0;
6087 wm_state->wm.plane[plane_id] = 0;
6090 if (plane_id == PLANE_PRIMARY) {
6091 for (level = 0; level < 3; level++) {
6092 struct g4x_pipe_wm *raw =
6093 &crtc_state->wm.g4x.raw[level];
6097 wm_state->sr.fbc = 0;
6098 wm_state->hpll.fbc = 0;
6099 wm_state->fbc_en = false;
6103 for_each_intel_crtc(&dev_priv->drm, crtc) {
6104 struct intel_crtc_state *crtc_state =
6105 to_intel_crtc_state(crtc->base.state);
6107 crtc_state->wm.g4x.intermediate =
6108 crtc_state->wm.g4x.optimal;
6109 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6112 g4x_program_watermarks(dev_priv);
6114 mutex_unlock(&dev_priv->wm.wm_mutex);
6117 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6119 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6120 struct intel_crtc *crtc;
6123 vlv_read_wm_values(dev_priv, wm);
6125 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6126 wm->level = VLV_WM_LEVEL_PM2;
6128 if (IS_CHERRYVIEW(dev_priv)) {
6129 vlv_punit_get(dev_priv);
6131 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6132 if (val & DSP_MAXFIFO_PM5_ENABLE)
6133 wm->level = VLV_WM_LEVEL_PM5;
6136 * If DDR DVFS is disabled in the BIOS, Punit
6137 * will never ack the request. So if that happens
6138 * assume we don't have to enable/disable DDR DVFS
6139 * dynamically. To test that just set the REQ_ACK
6140 * bit to poke the Punit, but don't change the
6141 * HIGH/LOW bits so that we don't actually change
6142 * the current state.
6144 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6145 val |= FORCE_DDR_FREQ_REQ_ACK;
6146 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6148 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6149 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6150 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
6151 "assuming DDR DVFS is disabled\n");
6152 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6154 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6155 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6156 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6159 vlv_punit_put(dev_priv);
6162 for_each_intel_crtc(&dev_priv->drm, crtc) {
6163 struct intel_crtc_state *crtc_state =
6164 to_intel_crtc_state(crtc->base.state);
6165 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6166 const struct vlv_fifo_state *fifo_state =
6167 &crtc_state->wm.vlv.fifo_state;
6168 enum pipe pipe = crtc->pipe;
6169 enum plane_id plane_id;
6172 vlv_get_fifo_size(crtc_state);
6174 active->num_levels = wm->level + 1;
6175 active->cxsr = wm->cxsr;
6177 for (level = 0; level < active->num_levels; level++) {
6178 struct g4x_pipe_wm *raw =
6179 &crtc_state->wm.vlv.raw[level];
6181 active->sr[level].plane = wm->sr.plane;
6182 active->sr[level].cursor = wm->sr.cursor;
6184 for_each_plane_id_on_crtc(crtc, plane_id) {
6185 active->wm[level].plane[plane_id] =
6186 wm->pipe[pipe].plane[plane_id];
6188 raw->plane[plane_id] =
6189 vlv_invert_wm_value(active->wm[level].plane[plane_id],
6190 fifo_state->plane[plane_id]);
6194 for_each_plane_id_on_crtc(crtc, plane_id)
6195 vlv_raw_plane_wm_set(crtc_state, level,
6196 plane_id, USHRT_MAX);
6197 vlv_invalidate_wms(crtc, active, level);
6199 crtc_state->wm.vlv.optimal = *active;
6200 crtc_state->wm.vlv.intermediate = *active;
6202 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6204 wm->pipe[pipe].plane[PLANE_PRIMARY],
6205 wm->pipe[pipe].plane[PLANE_CURSOR],
6206 wm->pipe[pipe].plane[PLANE_SPRITE0],
6207 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6210 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6211 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6214 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6216 struct intel_plane *plane;
6217 struct intel_crtc *crtc;
6219 mutex_lock(&dev_priv->wm.wm_mutex);
6221 for_each_intel_plane(&dev_priv->drm, plane) {
6222 struct intel_crtc *crtc =
6223 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6224 struct intel_crtc_state *crtc_state =
6225 to_intel_crtc_state(crtc->base.state);
6226 struct intel_plane_state *plane_state =
6227 to_intel_plane_state(plane->base.state);
6228 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6229 const struct vlv_fifo_state *fifo_state =
6230 &crtc_state->wm.vlv.fifo_state;
6231 enum plane_id plane_id = plane->id;
6234 if (plane_state->base.visible)
6237 for (level = 0; level < wm_state->num_levels; level++) {
6238 struct g4x_pipe_wm *raw =
6239 &crtc_state->wm.vlv.raw[level];
6241 raw->plane[plane_id] = 0;
6243 wm_state->wm[level].plane[plane_id] =
6244 vlv_invert_wm_value(raw->plane[plane_id],
6245 fifo_state->plane[plane_id]);
6249 for_each_intel_crtc(&dev_priv->drm, crtc) {
6250 struct intel_crtc_state *crtc_state =
6251 to_intel_crtc_state(crtc->base.state);
6253 crtc_state->wm.vlv.intermediate =
6254 crtc_state->wm.vlv.optimal;
6255 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6258 vlv_program_watermarks(dev_priv);
6260 mutex_unlock(&dev_priv->wm.wm_mutex);
6264 * FIXME should probably kill this and improve
6265 * the real watermark readout/sanitation instead
6267 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6269 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6270 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6271 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6274 * Don't touch WM1S_LP_EN here.
6275 * Doing so could cause underruns.
6279 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
6281 struct ilk_wm_values *hw = &dev_priv->wm.hw;
6282 struct intel_crtc *crtc;
6284 ilk_init_lp_watermarks(dev_priv);
6286 for_each_intel_crtc(&dev_priv->drm, crtc)
6287 ilk_pipe_wm_get_hw_state(crtc);
6289 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6290 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6291 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6293 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
6294 if (INTEL_GEN(dev_priv) >= 7) {
6295 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6296 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6299 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6300 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6301 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6302 else if (IS_IVYBRIDGE(dev_priv))
6303 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6304 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6307 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6311 * intel_update_watermarks - update FIFO watermark values based on current modes
6312 * @crtc: the #intel_crtc on which to compute the WM
6314 * Calculate watermark values for the various WM regs based on current mode
6315 * and plane configuration.
6317 * There are several cases to deal with here:
6318 * - normal (i.e. non-self-refresh)
6319 * - self-refresh (SR) mode
6320 * - lines are large relative to FIFO size (buffer can hold up to 2)
6321 * - lines are small relative to FIFO size (buffer can hold more than 2
6322 * lines), so need to account for TLB latency
6324 * The normal calculation is:
6325 * watermark = dotclock * bytes per pixel * latency
6326 * where latency is platform & configuration dependent (we assume pessimal
6329 * The SR calculation is:
6330 * watermark = (trunc(latency/line time)+1) * surface width *
6333 * line time = htotal / dotclock
6334 * surface width = hdisplay for normal plane and 64 for cursor
6335 * and latency is assumed to be high, as above.
6337 * The final value programmed to the register should always be rounded up,
6338 * and include an extra 2 entries to account for clock crossings.
6340 * We don't use the sprite, so we can ignore that. And on Crestline we have
6341 * to set the non-SR watermarks to 8.
6343 void intel_update_watermarks(struct intel_crtc *crtc)
6345 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6347 if (dev_priv->display.update_wm)
6348 dev_priv->display.update_wm(crtc);
6351 void intel_enable_ipc(struct drm_i915_private *dev_priv)
6355 if (!HAS_IPC(dev_priv))
6358 val = I915_READ(DISP_ARB_CTL2);
6360 if (dev_priv->ipc_enabled)
6361 val |= DISP_IPC_ENABLE;
6363 val &= ~DISP_IPC_ENABLE;
6365 I915_WRITE(DISP_ARB_CTL2, val);
6368 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
6370 /* Display WA #0477 WaDisableIPC: skl */
6371 if (IS_SKYLAKE(dev_priv))
6374 /* Display WA #1141: SKL:all KBL:all CFL */
6375 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
6376 return dev_priv->dram_info.symmetric_memory;
6381 void intel_init_ipc(struct drm_i915_private *dev_priv)
6383 if (!HAS_IPC(dev_priv))
6386 dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
6388 intel_enable_ipc(dev_priv);
6392 * Lock protecting IPS related data structures
6394 DEFINE_SPINLOCK(mchdev_lock);
6396 bool ironlake_set_drps(struct drm_i915_private *i915, u8 val)
6398 struct intel_uncore *uncore = &i915->uncore;
6401 lockdep_assert_held(&mchdev_lock);
6403 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
6404 if (rgvswctl & MEMCTL_CMD_STS) {
6405 DRM_DEBUG("gpu busy, RCS change rejected\n");
6406 return false; /* still busy with another command */
6409 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6410 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6411 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
6412 intel_uncore_posting_read16(uncore, MEMSWCTL);
6414 rgvswctl |= MEMCTL_CMD_STS;
6415 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
6420 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
6422 struct intel_uncore *uncore = &dev_priv->uncore;
6424 u8 fmax, fmin, fstart, vstart;
6426 spin_lock_irq(&mchdev_lock);
6428 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
6430 /* Enable temp reporting */
6431 intel_uncore_write16(uncore, PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6432 intel_uncore_write16(uncore, TSC1, I915_READ(TSC1) | TSE);
6434 /* 100ms RC evaluation intervals */
6435 intel_uncore_write(uncore, RCUPEI, 100000);
6436 intel_uncore_write(uncore, RCDNEI, 100000);
6438 /* Set max/min thresholds to 90ms and 80ms respectively */
6439 intel_uncore_write(uncore, RCBMAXAVG, 90000);
6440 intel_uncore_write(uncore, RCBMINAVG, 80000);
6442 intel_uncore_write(uncore, MEMIHYST, 1);
6444 /* Set up min, max, and cur for interrupt handling */
6445 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6446 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6447 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6448 MEMMODE_FSTART_SHIFT;
6450 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) &
6451 PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT;
6453 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
6454 dev_priv->ips.fstart = fstart;
6456 dev_priv->ips.max_delay = fstart;
6457 dev_priv->ips.min_delay = fmin;
6458 dev_priv->ips.cur_delay = fstart;
6460 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6461 fmax, fmin, fstart);
6463 intel_uncore_write(uncore,
6465 MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6468 * Interrupts will be enabled in ironlake_irq_postinstall
6471 intel_uncore_write(uncore, VIDSTART, vstart);
6472 intel_uncore_posting_read(uncore, VIDSTART);
6474 rgvmodectl |= MEMMODE_SWMODE_EN;
6475 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl);
6477 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
6478 MEMCTL_CMD_STS) == 0, 10))
6479 DRM_ERROR("stuck trying to change perf mode\n");
6482 ironlake_set_drps(dev_priv, fstart);
6484 dev_priv->ips.last_count1 =
6485 intel_uncore_read(uncore, DMIEC) +
6486 intel_uncore_read(uncore, DDREC) +
6487 intel_uncore_read(uncore, CSIEC);
6488 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
6489 dev_priv->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
6490 dev_priv->ips.last_time2 = ktime_get_raw_ns();
6492 spin_unlock_irq(&mchdev_lock);
6495 static void ironlake_disable_drps(struct drm_i915_private *i915)
6497 struct intel_uncore *uncore = &i915->uncore;
6500 spin_lock_irq(&mchdev_lock);
6502 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
6504 /* Ack interrupts, disable EFC interrupt */
6505 intel_uncore_write(uncore,
6507 intel_uncore_read(uncore, MEMINTREN) &
6508 ~MEMINT_EVAL_CHG_EN);
6509 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
6510 intel_uncore_write(uncore,
6512 intel_uncore_read(uncore, DEIER) & ~DE_PCU_EVENT);
6513 intel_uncore_write(uncore, DEIIR, DE_PCU_EVENT);
6514 intel_uncore_write(uncore,
6516 intel_uncore_read(uncore, DEIMR) | DE_PCU_EVENT);
6518 /* Go back to the starting frequency */
6519 ironlake_set_drps(i915, i915->ips.fstart);
6521 rgvswctl |= MEMCTL_CMD_STS;
6522 intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
6525 spin_unlock_irq(&mchdev_lock);
6528 /* There's a funny hw issue where the hw returns all 0 when reading from
6529 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
6530 * ourselves, instead of doing a rmw cycle (which might result in us clearing
6531 * all limits and the gpu stuck at whatever frequency it is at atm).
6533 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
6535 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6538 /* Only set the down limit when we've reached the lowest level to avoid
6539 * getting more interrupts, otherwise leave this clear. This prevents a
6540 * race in the hw when coming out of rc6: There's a tiny window where
6541 * the hw runs at the minimal clock before selecting the desired
6542 * frequency, if the down threshold expires in that window we will not
6543 * receive a down interrupt. */
6544 if (INTEL_GEN(dev_priv) >= 9) {
6545 limits = (rps->max_freq_softlimit) << 23;
6546 if (val <= rps->min_freq_softlimit)
6547 limits |= (rps->min_freq_softlimit) << 14;
6549 limits = rps->max_freq_softlimit << 24;
6550 if (val <= rps->min_freq_softlimit)
6551 limits |= rps->min_freq_softlimit << 16;
6557 static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
6559 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6560 u32 threshold_up = 0, threshold_down = 0; /* in % */
6561 u32 ei_up = 0, ei_down = 0;
6563 lockdep_assert_held(&rps->power.mutex);
6565 if (new_power == rps->power.mode)
6568 /* Note the units here are not exactly 1us, but 1280ns. */
6569 switch (new_power) {
6571 /* Upclock if more than 95% busy over 16ms */
6575 /* Downclock if less than 85% busy over 32ms */
6577 threshold_down = 85;
6581 /* Upclock if more than 90% busy over 13ms */
6585 /* Downclock if less than 75% busy over 32ms */
6587 threshold_down = 75;
6591 /* Upclock if more than 85% busy over 10ms */
6595 /* Downclock if less than 60% busy over 32ms */
6597 threshold_down = 60;
6601 /* When byt can survive without system hang with dynamic
6602 * sw freq adjustments, this restriction can be lifted.
6604 if (IS_VALLEYVIEW(dev_priv))
6607 I915_WRITE(GEN6_RP_UP_EI,
6608 GT_INTERVAL_FROM_US(dev_priv, ei_up));
6609 I915_WRITE(GEN6_RP_UP_THRESHOLD,
6610 GT_INTERVAL_FROM_US(dev_priv,
6611 ei_up * threshold_up / 100));
6613 I915_WRITE(GEN6_RP_DOWN_EI,
6614 GT_INTERVAL_FROM_US(dev_priv, ei_down));
6615 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
6616 GT_INTERVAL_FROM_US(dev_priv,
6617 ei_down * threshold_down / 100));
6619 I915_WRITE(GEN6_RP_CONTROL,
6620 (INTEL_GEN(dev_priv) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
6621 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6622 GEN6_RP_MEDIA_IS_GFX |
6624 GEN6_RP_UP_BUSY_AVG |
6625 GEN6_RP_DOWN_IDLE_AVG);
6628 rps->power.mode = new_power;
6629 rps->power.up_threshold = threshold_up;
6630 rps->power.down_threshold = threshold_down;
6633 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
6635 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6638 new_power = rps->power.mode;
6639 switch (rps->power.mode) {
6641 if (val > rps->efficient_freq + 1 &&
6642 val > rps->cur_freq)
6643 new_power = BETWEEN;
6647 if (val <= rps->efficient_freq &&
6648 val < rps->cur_freq)
6649 new_power = LOW_POWER;
6650 else if (val >= rps->rp0_freq &&
6651 val > rps->cur_freq)
6652 new_power = HIGH_POWER;
6656 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
6657 val < rps->cur_freq)
6658 new_power = BETWEEN;
6661 /* Max/min bins are special */
6662 if (val <= rps->min_freq_softlimit)
6663 new_power = LOW_POWER;
6664 if (val >= rps->max_freq_softlimit)
6665 new_power = HIGH_POWER;
6667 mutex_lock(&rps->power.mutex);
6668 if (rps->power.interactive)
6669 new_power = HIGH_POWER;
6670 rps_set_power(dev_priv, new_power);
6671 mutex_unlock(&rps->power.mutex);
6674 void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive)
6676 struct intel_rps *rps = &i915->gt_pm.rps;
6678 if (INTEL_GEN(i915) < 6)
6681 mutex_lock(&rps->power.mutex);
6683 if (!rps->power.interactive++ && READ_ONCE(i915->gt.awake))
6684 rps_set_power(i915, HIGH_POWER);
6686 GEM_BUG_ON(!rps->power.interactive);
6687 rps->power.interactive--;
6689 mutex_unlock(&rps->power.mutex);
6692 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6694 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6697 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6698 if (val > rps->min_freq_softlimit)
6699 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6700 if (val < rps->max_freq_softlimit)
6701 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6703 mask &= dev_priv->pm_rps_events;
6705 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6708 /* gen6_set_rps is called to update the frequency request, but should also be
6709 * called when the range (min_delay and max_delay) is modified so that we can
6710 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6711 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6713 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6715 /* min/max delay may still have been modified so be sure to
6716 * write the limits value.
6718 if (val != rps->cur_freq) {
6719 gen6_set_rps_thresholds(dev_priv, val);
6721 if (INTEL_GEN(dev_priv) >= 9)
6722 I915_WRITE(GEN6_RPNSWREQ,
6723 GEN9_FREQUENCY(val));
6724 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6725 I915_WRITE(GEN6_RPNSWREQ,
6726 HSW_FREQUENCY(val));
6728 I915_WRITE(GEN6_RPNSWREQ,
6729 GEN6_FREQUENCY(val) |
6731 GEN6_AGGRESSIVE_TURBO);
6734 /* Make sure we continue to get interrupts
6735 * until we hit the minimum or maximum frequencies.
6737 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6738 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6740 rps->cur_freq = val;
6741 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6746 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6750 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6751 "Odd GPU freq value\n"))
6754 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6756 if (val != dev_priv->gt_pm.rps.cur_freq) {
6757 vlv_punit_get(dev_priv);
6758 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6759 vlv_punit_put(dev_priv);
6763 gen6_set_rps_thresholds(dev_priv, val);
6766 dev_priv->gt_pm.rps.cur_freq = val;
6767 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6772 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6774 * * If Gfx is Idle, then
6775 * 1. Forcewake Media well.
6776 * 2. Request idle freq.
6777 * 3. Release Forcewake of Media well.
6779 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6781 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6782 u32 val = rps->idle_freq;
6785 if (rps->cur_freq <= val)
6788 /* The punit delays the write of the frequency and voltage until it
6789 * determines the GPU is awake. During normal usage we don't want to
6790 * waste power changing the frequency if the GPU is sleeping (rc6).
6791 * However, the GPU and driver is now idle and we do not want to delay
6792 * switching to minimum voltage (reducing power whilst idle) as we do
6793 * not expect to be woken in the near future and so must flush the
6794 * change by waking the device.
6796 * We choose to take the media powerwell (either would do to trick the
6797 * punit into committing the voltage change) as that takes a lot less
6798 * power than the render powerwell.
6800 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_MEDIA);
6801 err = valleyview_set_rps(dev_priv, val);
6802 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_MEDIA);
6805 DRM_ERROR("Failed to set RPS for idle\n");
6808 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6810 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6812 mutex_lock(&rps->lock);
6816 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6817 gen6_rps_reset_ei(dev_priv);
6818 I915_WRITE(GEN6_PMINTRMSK,
6819 gen6_rps_pm_mask(dev_priv, rps->cur_freq));
6821 gen6_enable_rps_interrupts(dev_priv);
6823 /* Use the user's desired frequency as a guide, but for better
6824 * performance, jump directly to RPe as our starting frequency.
6826 freq = max(rps->cur_freq,
6827 rps->efficient_freq);
6829 if (intel_set_rps(dev_priv,
6831 rps->min_freq_softlimit,
6832 rps->max_freq_softlimit)))
6833 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6835 mutex_unlock(&rps->lock);
6838 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6840 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6842 /* Flush our bottom-half so that it does not race with us
6843 * setting the idle frequency and so that it is bounded by
6844 * our rpm wakeref. And then disable the interrupts to stop any
6845 * futher RPS reclocking whilst we are asleep.
6847 gen6_disable_rps_interrupts(dev_priv);
6849 mutex_lock(&rps->lock);
6851 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6852 vlv_set_rps_idle(dev_priv);
6854 gen6_set_rps(dev_priv, rps->idle_freq);
6856 I915_WRITE(GEN6_PMINTRMSK,
6857 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6859 mutex_unlock(&rps->lock);
6862 void gen6_rps_boost(struct i915_request *rq)
6864 struct intel_rps *rps = &rq->i915->gt_pm.rps;
6865 unsigned long flags;
6868 /* This is intentionally racy! We peek at the state here, then
6869 * validate inside the RPS worker.
6874 if (i915_request_signaled(rq))
6877 /* Serializes with i915_request_retire() */
6879 spin_lock_irqsave(&rq->lock, flags);
6880 if (!i915_request_has_waitboost(rq) &&
6881 !dma_fence_is_signaled_locked(&rq->fence)) {
6882 boost = !atomic_fetch_inc(&rps->num_waiters);
6883 rq->flags |= I915_REQUEST_WAITBOOST;
6885 spin_unlock_irqrestore(&rq->lock, flags);
6889 if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
6890 schedule_work(&rps->work);
6892 atomic_inc(&rps->boosts);
6895 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6897 struct intel_rps *rps = &dev_priv->gt_pm.rps;
6900 lockdep_assert_held(&rps->lock);
6901 GEM_BUG_ON(val > rps->max_freq);
6902 GEM_BUG_ON(val < rps->min_freq);
6904 if (!rps->enabled) {
6905 rps->cur_freq = val;
6909 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6910 err = valleyview_set_rps(dev_priv, val);
6912 err = gen6_set_rps(dev_priv, val);
6917 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6919 I915_WRITE(GEN6_RC_CONTROL, 0);
6920 I915_WRITE(GEN9_PG_ENABLE, 0);
6923 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6925 I915_WRITE(GEN6_RP_CONTROL, 0);
6928 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
6930 I915_WRITE(GEN6_RC_CONTROL, 0);
6933 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6935 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6936 I915_WRITE(GEN6_RP_CONTROL, 0);
6939 static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
6941 I915_WRITE(GEN6_RC_CONTROL, 0);
6944 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6946 I915_WRITE(GEN6_RP_CONTROL, 0);
6949 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
6951 /* We're doing forcewake before Disabling RC6,
6952 * This what the BIOS expects when going into suspend */
6953 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
6955 I915_WRITE(GEN6_RC_CONTROL, 0);
6957 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
6960 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6962 I915_WRITE(GEN6_RP_CONTROL, 0);
6965 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6967 bool enable_rc6 = true;
6968 unsigned long rc6_ctx_base;
6972 rc_ctl = I915_READ(GEN6_RC_CONTROL);
6973 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6974 RC_SW_TARGET_STATE_SHIFT;
6975 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6976 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6977 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6978 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6981 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6982 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6987 * The exact context size is not known for BXT, so assume a page size
6990 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6991 if (!((rc6_ctx_base >= dev_priv->dsm_reserved.start) &&
6992 (rc6_ctx_base + PAGE_SIZE < dev_priv->dsm_reserved.end))) {
6993 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6997 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6998 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6999 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
7000 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
7001 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
7005 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
7006 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
7007 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
7008 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
7012 if (!I915_READ(GEN6_GFXPAUSE)) {
7013 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
7017 if (!I915_READ(GEN8_MISC_CTRL0)) {
7018 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
7025 static bool sanitize_rc6(struct drm_i915_private *i915)
7027 struct intel_device_info *info = mkwrite_device_info(i915);
7029 /* Powersaving is controlled by the host when inside a VM */
7030 if (intel_vgpu_active(i915)) {
7032 info->has_rps = false;
7035 if (info->has_rc6 &&
7036 IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) {
7037 DRM_INFO("RC6 disabled by BIOS\n");
7042 * We assume that we do not have any deep rc6 levels if we don't have
7043 * have the previous rc6 level supported, i.e. we use HAS_RC6()
7044 * as the initial coarse check for rc6 in general, moving on to
7045 * progressively finer/deeper levels.
7047 if (!info->has_rc6 && info->has_rc6p)
7050 return info->has_rc6;
7053 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
7055 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7057 /* All of these values are in units of 50MHz */
7059 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
7060 if (IS_GEN9_LP(dev_priv)) {
7061 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
7062 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
7063 rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
7064 rps->min_freq = (rp_state_cap >> 0) & 0xff;
7066 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7067 rps->rp0_freq = (rp_state_cap >> 0) & 0xff;
7068 rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
7069 rps->min_freq = (rp_state_cap >> 16) & 0xff;
7071 /* hw_max = RP0 until we check for overclocking */
7072 rps->max_freq = rps->rp0_freq;
7074 rps->efficient_freq = rps->rp1_freq;
7075 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
7076 IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7077 u32 ddcc_status = 0;
7079 if (sandybridge_pcode_read(dev_priv,
7080 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
7081 &ddcc_status, NULL) == 0)
7082 rps->efficient_freq =
7084 ((ddcc_status >> 8) & 0xff),
7089 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7090 /* Store the frequency values in 16.66 MHZ units, which is
7091 * the natural hardware unit for SKL
7093 rps->rp0_freq *= GEN9_FREQ_SCALER;
7094 rps->rp1_freq *= GEN9_FREQ_SCALER;
7095 rps->min_freq *= GEN9_FREQ_SCALER;
7096 rps->max_freq *= GEN9_FREQ_SCALER;
7097 rps->efficient_freq *= GEN9_FREQ_SCALER;
7101 static void reset_rps(struct drm_i915_private *dev_priv,
7102 int (*set)(struct drm_i915_private *, u8))
7104 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7105 u8 freq = rps->cur_freq;
7108 rps->power.mode = -1;
7111 if (set(dev_priv, freq))
7112 DRM_ERROR("Failed to reset RPS to initial values\n");
7115 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
7116 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
7118 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7120 /* Program defaults and thresholds for RPS */
7121 if (IS_GEN(dev_priv, 9))
7122 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7123 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
7125 /* 1 second timeout*/
7126 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
7127 GT_INTERVAL_FROM_US(dev_priv, 1000000));
7129 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
7131 /* Leaning on the below call to gen6_set_rps to program/setup the
7132 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
7133 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
7134 reset_rps(dev_priv, gen6_set_rps);
7136 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7139 static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
7141 struct intel_engine_cs *engine;
7142 enum intel_engine_id id;
7144 /* 1a: Software RC state - RC0 */
7145 I915_WRITE(GEN6_RC_STATE, 0);
7148 * 1b: Get forcewake during program sequence. Although the driver
7149 * hasn't enabled a state yet where we need forcewake, BIOS may have.
7151 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7153 /* 2a: Disable RC states. */
7154 I915_WRITE(GEN6_RC_CONTROL, 0);
7156 /* 2b: Program RC6 thresholds.*/
7157 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
7158 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
7160 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7161 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7162 for_each_engine(engine, dev_priv, id)
7163 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7165 if (HAS_GT_UC(dev_priv))
7166 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
7168 I915_WRITE(GEN6_RC_SLEEP, 0);
7170 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
7173 * 2c: Program Coarse Power Gating Policies.
7175 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
7176 * use instead is a more conservative estimate for the maximum time
7177 * it takes us to service a CS interrupt and submit a new ELSP - that
7178 * is the time which the GPU is idle waiting for the CPU to select the
7179 * next request to execute. If the idle hysteresis is less than that
7180 * interrupt service latency, the hardware will automatically gate
7181 * the power well and we will then incur the wake up cost on top of
7182 * the service latency. A similar guide from plane_state is that we
7183 * do not want the enable hysteresis to less than the wakeup latency.
7185 * igt/gem_exec_nop/sequential provides a rough estimate for the
7186 * service latency, and puts it around 10us for Broadwell (and other
7187 * big core) and around 40us for Broxton (and other low power cores).
7188 * [Note that for legacy ringbuffer submission, this is less than 1us!]
7189 * However, the wakeup latency on Broxton is closer to 100us. To be
7190 * conservative, we have to factor in a context switch on top (due
7193 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
7194 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
7196 /* 3a: Enable RC6 */
7197 I915_WRITE(GEN6_RC_CONTROL,
7198 GEN6_RC_CTL_HW_ENABLE |
7199 GEN6_RC_CTL_RC6_ENABLE |
7200 GEN6_RC_CTL_EI_MODE(1));
7202 /* 3b: Enable Coarse Power Gating only when RC6 is enabled. */
7203 I915_WRITE(GEN9_PG_ENABLE,
7204 GEN9_RENDER_PG_ENABLE |
7205 GEN9_MEDIA_PG_ENABLE |
7206 GEN11_MEDIA_SAMPLER_PG_ENABLE);
7208 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7211 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
7213 struct intel_engine_cs *engine;
7214 enum intel_engine_id id;
7217 /* 1a: Software RC state - RC0 */
7218 I915_WRITE(GEN6_RC_STATE, 0);
7220 /* 1b: Get forcewake during program sequence. Although the driver
7221 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7222 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7224 /* 2a: Disable RC states. */
7225 I915_WRITE(GEN6_RC_CONTROL, 0);
7227 /* 2b: Program RC6 thresholds.*/
7228 if (INTEL_GEN(dev_priv) >= 10) {
7229 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
7230 I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
7231 } else if (IS_SKYLAKE(dev_priv)) {
7233 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
7234 * when CPG is enabled
7236 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
7238 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
7241 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7242 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7243 for_each_engine(engine, dev_priv, id)
7244 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7246 if (HAS_GT_UC(dev_priv))
7247 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
7249 I915_WRITE(GEN6_RC_SLEEP, 0);
7252 * 2c: Program Coarse Power Gating Policies.
7254 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
7255 * use instead is a more conservative estimate for the maximum time
7256 * it takes us to service a CS interrupt and submit a new ELSP - that
7257 * is the time which the GPU is idle waiting for the CPU to select the
7258 * next request to execute. If the idle hysteresis is less than that
7259 * interrupt service latency, the hardware will automatically gate
7260 * the power well and we will then incur the wake up cost on top of
7261 * the service latency. A similar guide from plane_state is that we
7262 * do not want the enable hysteresis to less than the wakeup latency.
7264 * igt/gem_exec_nop/sequential provides a rough estimate for the
7265 * service latency, and puts it around 10us for Broadwell (and other
7266 * big core) and around 40us for Broxton (and other low power cores).
7267 * [Note that for legacy ringbuffer submission, this is less than 1us!]
7268 * However, the wakeup latency on Broxton is closer to 100us. To be
7269 * conservative, we have to factor in a context switch on top (due
7272 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
7273 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
7275 /* 3a: Enable RC6 */
7276 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
7278 /* WaRsUseTimeoutMode:cnl (pre-prod) */
7279 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
7280 rc6_mode = GEN7_RC_CTL_TO_MODE;
7282 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
7284 I915_WRITE(GEN6_RC_CONTROL,
7285 GEN6_RC_CTL_HW_ENABLE |
7286 GEN6_RC_CTL_RC6_ENABLE |
7290 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
7291 * WaRsDisableCoarsePowerGating:skl,cnl - Render/Media PG need to be disabled with RC6.
7293 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
7294 I915_WRITE(GEN9_PG_ENABLE, 0);
7296 I915_WRITE(GEN9_PG_ENABLE,
7297 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
7299 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7302 static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
7304 struct intel_engine_cs *engine;
7305 enum intel_engine_id id;
7307 /* 1a: Software RC state - RC0 */
7308 I915_WRITE(GEN6_RC_STATE, 0);
7310 /* 1b: Get forcewake during program sequence. Although the driver
7311 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7312 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7314 /* 2a: Disable RC states. */
7315 I915_WRITE(GEN6_RC_CONTROL, 0);
7317 /* 2b: Program RC6 thresholds.*/
7318 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7319 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7320 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7321 for_each_engine(engine, dev_priv, id)
7322 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7323 I915_WRITE(GEN6_RC_SLEEP, 0);
7324 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
7328 I915_WRITE(GEN6_RC_CONTROL,
7329 GEN6_RC_CTL_HW_ENABLE |
7330 GEN7_RC_CTL_TO_MODE |
7331 GEN6_RC_CTL_RC6_ENABLE);
7333 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7336 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
7338 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7340 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7342 /* 1 Program defaults and thresholds for RPS*/
7343 I915_WRITE(GEN6_RPNSWREQ,
7344 HSW_FREQUENCY(rps->rp1_freq));
7345 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7346 HSW_FREQUENCY(rps->rp1_freq));
7347 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
7348 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
7350 /* Docs recommend 900MHz, and 300 MHz respectively */
7351 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7352 rps->max_freq_softlimit << 24 |
7353 rps->min_freq_softlimit << 16);
7355 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
7356 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
7357 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
7358 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
7360 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7363 I915_WRITE(GEN6_RP_CONTROL,
7364 GEN6_RP_MEDIA_TURBO |
7365 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7366 GEN6_RP_MEDIA_IS_GFX |
7368 GEN6_RP_UP_BUSY_AVG |
7369 GEN6_RP_DOWN_IDLE_AVG);
7371 reset_rps(dev_priv, gen6_set_rps);
7373 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7376 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
7378 struct intel_engine_cs *engine;
7379 enum intel_engine_id id;
7380 u32 rc6vids, rc6_mask;
7384 I915_WRITE(GEN6_RC_STATE, 0);
7386 /* Clear the DBG now so we don't confuse earlier errors */
7387 gtfifodbg = I915_READ(GTFIFODBG);
7389 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
7390 I915_WRITE(GTFIFODBG, gtfifodbg);
7393 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7395 /* disable the counters and set deterministic thresholds */
7396 I915_WRITE(GEN6_RC_CONTROL, 0);
7398 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7399 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7400 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7401 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7402 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7404 for_each_engine(engine, dev_priv, id)
7405 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7407 I915_WRITE(GEN6_RC_SLEEP, 0);
7408 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7409 if (IS_IVYBRIDGE(dev_priv))
7410 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
7412 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7413 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
7414 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7416 /* We don't use those on Haswell */
7417 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
7418 if (HAS_RC6p(dev_priv))
7419 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
7420 if (HAS_RC6pp(dev_priv))
7421 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
7422 I915_WRITE(GEN6_RC_CONTROL,
7424 GEN6_RC_CTL_EI_MODE(1) |
7425 GEN6_RC_CTL_HW_ENABLE);
7428 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
7430 if (IS_GEN(dev_priv, 6) && ret) {
7431 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
7432 } else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
7433 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
7434 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
7435 rc6vids &= 0xffff00;
7436 rc6vids |= GEN6_ENCODE_RC6_VID(450);
7437 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
7439 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
7442 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7445 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
7447 /* Here begins a magic sequence of register writes to enable
7448 * auto-downclocking.
7450 * Perhaps there might be some value in exposing these to
7453 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7455 /* Power down if completely idle for over 50ms */
7456 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
7457 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7459 reset_rps(dev_priv, gen6_set_rps);
7461 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7464 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7466 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7467 const int min_freq = 15;
7468 const int scaling_factor = 180;
7469 unsigned int gpu_freq;
7470 unsigned int max_ia_freq, min_ring_freq;
7471 unsigned int max_gpu_freq, min_gpu_freq;
7472 struct cpufreq_policy *policy;
7474 lockdep_assert_held(&rps->lock);
7476 if (rps->max_freq <= rps->min_freq)
7479 policy = cpufreq_cpu_get(0);
7481 max_ia_freq = policy->cpuinfo.max_freq;
7482 cpufreq_cpu_put(policy);
7485 * Default to measured freq if none found, PCU will ensure we
7488 max_ia_freq = tsc_khz;
7491 /* Convert from kHz to MHz */
7492 max_ia_freq /= 1000;
7494 min_ring_freq = I915_READ(DCLK) & 0xf;
7495 /* convert DDR frequency from units of 266.6MHz to bandwidth */
7496 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
7498 min_gpu_freq = rps->min_freq;
7499 max_gpu_freq = rps->max_freq;
7500 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7501 /* Convert GT frequency to 50 HZ units */
7502 min_gpu_freq /= GEN9_FREQ_SCALER;
7503 max_gpu_freq /= GEN9_FREQ_SCALER;
7507 * For each potential GPU frequency, load a ring frequency we'd like
7508 * to use for memory access. We do this by specifying the IA frequency
7509 * the PCU should use as a reference to determine the ring frequency.
7511 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
7512 const int diff = max_gpu_freq - gpu_freq;
7513 unsigned int ia_freq = 0, ring_freq = 0;
7515 if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
7517 * ring_freq = 2 * GT. ring_freq is in 100MHz units
7518 * No floor required for ring frequency on SKL.
7520 ring_freq = gpu_freq;
7521 } else if (INTEL_GEN(dev_priv) >= 8) {
7522 /* max(2 * GT, DDR). NB: GT is 50MHz units */
7523 ring_freq = max(min_ring_freq, gpu_freq);
7524 } else if (IS_HASWELL(dev_priv)) {
7525 ring_freq = mult_frac(gpu_freq, 5, 4);
7526 ring_freq = max(min_ring_freq, ring_freq);
7527 /* leave ia_freq as the default, chosen by cpufreq */
7529 /* On older processors, there is no separate ring
7530 * clock domain, so in order to boost the bandwidth
7531 * of the ring, we need to upclock the CPU (ia_freq).
7533 * For GPU frequencies less than 750MHz,
7534 * just use the lowest ring freq.
7536 if (gpu_freq < min_freq)
7539 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7540 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7543 sandybridge_pcode_write(dev_priv,
7544 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
7545 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
7546 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
7551 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
7555 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7557 switch (RUNTIME_INFO(dev_priv)->sseu.eu_total) {
7559 /* (2 * 4) config */
7560 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
7563 /* (2 * 6) config */
7564 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
7567 /* (2 * 8) config */
7569 /* Setting (2 * 8) Min RP0 for any other combination */
7570 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
7574 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
7579 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7583 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
7584 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
7589 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
7593 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
7594 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
7599 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
7603 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
7604 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
7605 FB_GFX_FREQ_FUSE_MASK);
7610 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
7614 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7616 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
7621 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
7625 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
7627 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
7629 rp0 = min_t(u32, rp0, 0xea);
7634 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
7638 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
7639 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
7640 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
7641 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
7646 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
7650 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
7652 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7653 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7654 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7655 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7656 * to make sure it matches what Punit accepts.
7658 return max_t(u32, val, 0xc0);
7661 /* Check that the pctx buffer wasn't move under us. */
7662 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
7664 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7666 WARN_ON(pctx_addr != dev_priv->dsm.start +
7667 dev_priv->vlv_pctx->stolen->start);
7671 /* Check that the pcbr address is not empty. */
7672 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
7674 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7676 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
7679 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
7681 resource_size_t pctx_paddr, paddr;
7682 resource_size_t pctx_size = 32*1024;
7685 pcbr = I915_READ(VLV_PCBR);
7686 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
7687 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7688 paddr = dev_priv->dsm.end + 1 - pctx_size;
7689 GEM_BUG_ON(paddr > U32_MAX);
7691 pctx_paddr = (paddr & (~4095));
7692 I915_WRITE(VLV_PCBR, pctx_paddr);
7695 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7698 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
7700 struct drm_i915_gem_object *pctx;
7701 resource_size_t pctx_paddr;
7702 resource_size_t pctx_size = 24*1024;
7705 pcbr = I915_READ(VLV_PCBR);
7707 /* BIOS set it up already, grab the pre-alloc'd space */
7708 resource_size_t pcbr_offset;
7710 pcbr_offset = (pcbr & (~4095)) - dev_priv->dsm.start;
7711 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
7713 I915_GTT_OFFSET_NONE,
7718 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7721 * From the Gunit register HAS:
7722 * The Gfx driver is expected to program this register and ensure
7723 * proper allocation within Gfx stolen memory. For example, this
7724 * register should be programmed such than the PCBR range does not
7725 * overlap with other ranges, such as the frame buffer, protected
7726 * memory, or any other relevant ranges.
7728 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
7730 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7734 GEM_BUG_ON(range_overflows_t(u64,
7735 dev_priv->dsm.start,
7736 pctx->stolen->start,
7738 pctx_paddr = dev_priv->dsm.start + pctx->stolen->start;
7739 I915_WRITE(VLV_PCBR, pctx_paddr);
7742 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7743 dev_priv->vlv_pctx = pctx;
7746 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
7748 struct drm_i915_gem_object *pctx;
7750 pctx = fetch_and_zero(&dev_priv->vlv_pctx);
7752 i915_gem_object_put(pctx);
7755 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
7757 dev_priv->gt_pm.rps.gpll_ref_freq =
7758 vlv_get_cck_clock(dev_priv, "GPLL ref",
7759 CCK_GPLL_CLOCK_CONTROL,
7760 dev_priv->czclk_freq);
7762 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7763 dev_priv->gt_pm.rps.gpll_ref_freq);
7766 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
7768 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7771 valleyview_setup_pctx(dev_priv);
7773 vlv_iosf_sb_get(dev_priv,
7774 BIT(VLV_IOSF_SB_PUNIT) |
7775 BIT(VLV_IOSF_SB_NC) |
7776 BIT(VLV_IOSF_SB_CCK));
7778 vlv_init_gpll_ref_freq(dev_priv);
7780 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7781 switch ((val >> 6) & 3) {
7784 dev_priv->mem_freq = 800;
7787 dev_priv->mem_freq = 1066;
7790 dev_priv->mem_freq = 1333;
7793 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7795 rps->max_freq = valleyview_rps_max_freq(dev_priv);
7796 rps->rp0_freq = rps->max_freq;
7797 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7798 intel_gpu_freq(dev_priv, rps->max_freq),
7801 rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7802 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7803 intel_gpu_freq(dev_priv, rps->efficient_freq),
7804 rps->efficient_freq);
7806 rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
7807 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7808 intel_gpu_freq(dev_priv, rps->rp1_freq),
7811 rps->min_freq = valleyview_rps_min_freq(dev_priv);
7812 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7813 intel_gpu_freq(dev_priv, rps->min_freq),
7816 vlv_iosf_sb_put(dev_priv,
7817 BIT(VLV_IOSF_SB_PUNIT) |
7818 BIT(VLV_IOSF_SB_NC) |
7819 BIT(VLV_IOSF_SB_CCK));
7822 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7824 struct intel_rps *rps = &dev_priv->gt_pm.rps;
7827 cherryview_setup_pctx(dev_priv);
7829 vlv_iosf_sb_get(dev_priv,
7830 BIT(VLV_IOSF_SB_PUNIT) |
7831 BIT(VLV_IOSF_SB_NC) |
7832 BIT(VLV_IOSF_SB_CCK));
7834 vlv_init_gpll_ref_freq(dev_priv);
7836 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7838 switch ((val >> 2) & 0x7) {
7840 dev_priv->mem_freq = 2000;
7843 dev_priv->mem_freq = 1600;
7846 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7848 rps->max_freq = cherryview_rps_max_freq(dev_priv);
7849 rps->rp0_freq = rps->max_freq;
7850 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7851 intel_gpu_freq(dev_priv, rps->max_freq),
7854 rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7855 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7856 intel_gpu_freq(dev_priv, rps->efficient_freq),
7857 rps->efficient_freq);
7859 rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
7860 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7861 intel_gpu_freq(dev_priv, rps->rp1_freq),
7864 rps->min_freq = cherryview_rps_min_freq(dev_priv);
7865 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7866 intel_gpu_freq(dev_priv, rps->min_freq),
7869 vlv_iosf_sb_put(dev_priv,
7870 BIT(VLV_IOSF_SB_PUNIT) |
7871 BIT(VLV_IOSF_SB_NC) |
7872 BIT(VLV_IOSF_SB_CCK));
7874 WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
7876 "Odd GPU freq values\n");
7879 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7881 valleyview_cleanup_pctx(dev_priv);
7884 static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
7886 struct intel_engine_cs *engine;
7887 enum intel_engine_id id;
7888 u32 gtfifodbg, rc6_mode, pcbr;
7890 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7891 GT_FIFO_FREE_ENTRIES_CHV);
7893 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7895 I915_WRITE(GTFIFODBG, gtfifodbg);
7898 cherryview_check_pctx(dev_priv);
7900 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7901 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7902 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7904 /* Disable RC states. */
7905 I915_WRITE(GEN6_RC_CONTROL, 0);
7907 /* 2a: Program RC6 thresholds.*/
7908 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7909 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7910 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7912 for_each_engine(engine, dev_priv, id)
7913 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7914 I915_WRITE(GEN6_RC_SLEEP, 0);
7916 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7917 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7919 /* Allows RC6 residency counter to work */
7920 I915_WRITE(VLV_COUNTER_CONTROL,
7921 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7922 VLV_MEDIA_RC6_COUNT_EN |
7923 VLV_RENDER_RC6_COUNT_EN));
7925 /* For now we assume BIOS is allocating and populating the PCBR */
7926 pcbr = I915_READ(VLV_PCBR);
7930 if (pcbr >> VLV_PCBR_ADDR_SHIFT)
7931 rc6_mode = GEN7_RC_CTL_TO_MODE;
7932 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7934 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7937 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7941 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7943 /* 1: Program defaults and thresholds for RPS*/
7944 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7945 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7946 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7947 I915_WRITE(GEN6_RP_UP_EI, 66000);
7948 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7950 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7953 I915_WRITE(GEN6_RP_CONTROL,
7954 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7955 GEN6_RP_MEDIA_IS_GFX |
7957 GEN6_RP_UP_BUSY_AVG |
7958 GEN6_RP_DOWN_IDLE_AVG);
7960 /* Setting Fixed Bias */
7961 vlv_punit_get(dev_priv);
7963 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
7964 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7966 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7968 vlv_punit_put(dev_priv);
7970 /* RPS code assumes GPLL is used */
7971 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7973 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7974 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7976 reset_rps(dev_priv, valleyview_set_rps);
7978 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
7981 static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
7983 struct intel_engine_cs *engine;
7984 enum intel_engine_id id;
7987 valleyview_check_pctx(dev_priv);
7989 gtfifodbg = I915_READ(GTFIFODBG);
7991 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7993 I915_WRITE(GTFIFODBG, gtfifodbg);
7996 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
7998 /* Disable RC states. */
7999 I915_WRITE(GEN6_RC_CONTROL, 0);
8001 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
8002 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8003 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8005 for_each_engine(engine, dev_priv, id)
8006 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
8008 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
8010 /* Allows RC6 residency counter to work */
8011 I915_WRITE(VLV_COUNTER_CONTROL,
8012 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
8013 VLV_MEDIA_RC0_COUNT_EN |
8014 VLV_RENDER_RC0_COUNT_EN |
8015 VLV_MEDIA_RC6_COUNT_EN |
8016 VLV_RENDER_RC6_COUNT_EN));
8018 I915_WRITE(GEN6_RC_CONTROL,
8019 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL);
8021 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
8024 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
8028 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
8030 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8031 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
8032 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
8033 I915_WRITE(GEN6_RP_UP_EI, 66000);
8034 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
8036 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8038 I915_WRITE(GEN6_RP_CONTROL,
8039 GEN6_RP_MEDIA_TURBO |
8040 GEN6_RP_MEDIA_HW_NORMAL_MODE |
8041 GEN6_RP_MEDIA_IS_GFX |
8043 GEN6_RP_UP_BUSY_AVG |
8044 GEN6_RP_DOWN_IDLE_CONT);
8046 vlv_punit_get(dev_priv);
8048 /* Setting Fixed Bias */
8049 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
8050 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
8052 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
8054 vlv_punit_put(dev_priv);
8056 /* RPS code assumes GPLL is used */
8057 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
8059 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
8060 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
8062 reset_rps(dev_priv, valleyview_set_rps);
8064 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
8067 static unsigned long intel_pxfreq(u32 vidfreq)
8070 int div = (vidfreq & 0x3f0000) >> 16;
8071 int post = (vidfreq & 0x3000) >> 12;
8072 int pre = (vidfreq & 0x7);
8077 freq = ((div * 133333) / ((1<<post) * pre));
8082 static const struct cparams {
8088 { 1, 1333, 301, 28664 },
8089 { 1, 1066, 294, 24460 },
8090 { 1, 800, 294, 25192 },
8091 { 0, 1333, 276, 27605 },
8092 { 0, 1066, 276, 27605 },
8093 { 0, 800, 231, 23784 },
8096 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
8098 u64 total_count, diff, ret;
8099 u32 count1, count2, count3, m = 0, c = 0;
8100 unsigned long now = jiffies_to_msecs(jiffies), diff1;
8103 lockdep_assert_held(&mchdev_lock);
8105 diff1 = now - dev_priv->ips.last_time1;
8107 /* Prevent division-by-zero if we are asking too fast.
8108 * Also, we don't get interesting results if we are polling
8109 * faster than once in 10ms, so just return the saved value
8113 return dev_priv->ips.chipset_power;
8115 count1 = I915_READ(DMIEC);
8116 count2 = I915_READ(DDREC);
8117 count3 = I915_READ(CSIEC);
8119 total_count = count1 + count2 + count3;
8121 /* FIXME: handle per-counter overflow */
8122 if (total_count < dev_priv->ips.last_count1) {
8123 diff = ~0UL - dev_priv->ips.last_count1;
8124 diff += total_count;
8126 diff = total_count - dev_priv->ips.last_count1;
8129 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
8130 if (cparams[i].i == dev_priv->ips.c_m &&
8131 cparams[i].t == dev_priv->ips.r_t) {
8138 diff = div_u64(diff, diff1);
8139 ret = ((m * diff) + c);
8140 ret = div_u64(ret, 10);
8142 dev_priv->ips.last_count1 = total_count;
8143 dev_priv->ips.last_time1 = now;
8145 dev_priv->ips.chipset_power = ret;
8150 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
8152 intel_wakeref_t wakeref;
8153 unsigned long val = 0;
8155 if (!IS_GEN(dev_priv, 5))
8158 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8159 spin_lock_irq(&mchdev_lock);
8160 val = __i915_chipset_val(dev_priv);
8161 spin_unlock_irq(&mchdev_lock);
8167 unsigned long i915_mch_val(struct drm_i915_private *i915)
8169 unsigned long m, x, b;
8172 tsfs = intel_uncore_read(&i915->uncore, TSFS);
8174 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
8175 x = intel_uncore_read8(&i915->uncore, TR1);
8177 b = tsfs & TSFS_INTR_MASK;
8179 return ((m * x) / 127) - b;
8182 static int _pxvid_to_vd(u8 pxvid)
8187 if (pxvid >= 8 && pxvid < 31)
8190 return (pxvid + 2) * 125;
8193 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
8195 const int vd = _pxvid_to_vd(pxvid);
8196 const int vm = vd - 1125;
8198 if (INTEL_INFO(dev_priv)->is_mobile)
8199 return vm > 0 ? vm : 0;
8204 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
8206 u64 now, diff, diffms;
8209 lockdep_assert_held(&mchdev_lock);
8211 now = ktime_get_raw_ns();
8212 diffms = now - dev_priv->ips.last_time2;
8213 do_div(diffms, NSEC_PER_MSEC);
8215 /* Don't divide by 0 */
8219 count = I915_READ(GFXEC);
8221 if (count < dev_priv->ips.last_count2) {
8222 diff = ~0UL - dev_priv->ips.last_count2;
8225 diff = count - dev_priv->ips.last_count2;
8228 dev_priv->ips.last_count2 = count;
8229 dev_priv->ips.last_time2 = now;
8231 /* More magic constants... */
8233 diff = div_u64(diff, diffms * 10);
8234 dev_priv->ips.gfx_power = diff;
8237 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
8239 intel_wakeref_t wakeref;
8241 if (!IS_GEN(dev_priv, 5))
8244 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8245 spin_lock_irq(&mchdev_lock);
8246 __i915_update_gfx_val(dev_priv);
8247 spin_unlock_irq(&mchdev_lock);
8251 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
8253 unsigned long t, corr, state1, corr2, state2;
8256 lockdep_assert_held(&mchdev_lock);
8258 pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
8259 pxvid = (pxvid >> 24) & 0x7f;
8260 ext_v = pvid_to_extvid(dev_priv, pxvid);
8264 t = i915_mch_val(dev_priv);
8266 /* Revel in the empirically derived constants */
8268 /* Correction factor in 1/100000 units */
8270 corr = ((t * 2349) + 135940);
8272 corr = ((t * 964) + 29317);
8274 corr = ((t * 301) + 1004);
8276 corr = corr * ((150142 * state1) / 10000 - 78642);
8278 corr2 = (corr * dev_priv->ips.corr);
8280 state2 = (corr2 * state1) / 10000;
8281 state2 /= 100; /* convert to mW */
8283 __i915_update_gfx_val(dev_priv);
8285 return dev_priv->ips.gfx_power + state2;
8288 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
8290 intel_wakeref_t wakeref;
8291 unsigned long val = 0;
8293 if (!IS_GEN(dev_priv, 5))
8296 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
8297 spin_lock_irq(&mchdev_lock);
8298 val = __i915_gfx_val(dev_priv);
8299 spin_unlock_irq(&mchdev_lock);
8305 static struct drm_i915_private __rcu *i915_mch_dev;
8307 static struct drm_i915_private *mchdev_get(void)
8309 struct drm_i915_private *i915;
8312 i915 = rcu_dereference(i915_mch_dev);
8313 if (!kref_get_unless_zero(&i915->drm.ref))
8321 * i915_read_mch_val - return value for IPS use
8323 * Calculate and return a value for the IPS driver to use when deciding whether
8324 * we have thermal and power headroom to increase CPU or GPU power budget.
8326 unsigned long i915_read_mch_val(void)
8328 struct drm_i915_private *i915;
8329 unsigned long chipset_val = 0;
8330 unsigned long graphics_val = 0;
8331 intel_wakeref_t wakeref;
8333 i915 = mchdev_get();
8337 with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
8338 spin_lock_irq(&mchdev_lock);
8339 chipset_val = __i915_chipset_val(i915);
8340 graphics_val = __i915_gfx_val(i915);
8341 spin_unlock_irq(&mchdev_lock);
8344 drm_dev_put(&i915->drm);
8345 return chipset_val + graphics_val;
8347 EXPORT_SYMBOL_GPL(i915_read_mch_val);
8350 * i915_gpu_raise - raise GPU frequency limit
8352 * Raise the limit; IPS indicates we have thermal headroom.
8354 bool i915_gpu_raise(void)
8356 struct drm_i915_private *i915;
8358 i915 = mchdev_get();
8362 spin_lock_irq(&mchdev_lock);
8363 if (i915->ips.max_delay > i915->ips.fmax)
8364 i915->ips.max_delay--;
8365 spin_unlock_irq(&mchdev_lock);
8367 drm_dev_put(&i915->drm);
8370 EXPORT_SYMBOL_GPL(i915_gpu_raise);
8373 * i915_gpu_lower - lower GPU frequency limit
8375 * IPS indicates we're close to a thermal limit, so throttle back the GPU
8376 * frequency maximum.
8378 bool i915_gpu_lower(void)
8380 struct drm_i915_private *i915;
8382 i915 = mchdev_get();
8386 spin_lock_irq(&mchdev_lock);
8387 if (i915->ips.max_delay < i915->ips.min_delay)
8388 i915->ips.max_delay++;
8389 spin_unlock_irq(&mchdev_lock);
8391 drm_dev_put(&i915->drm);
8394 EXPORT_SYMBOL_GPL(i915_gpu_lower);
8397 * i915_gpu_busy - indicate GPU business to IPS
8399 * Tell the IPS driver whether or not the GPU is busy.
8401 bool i915_gpu_busy(void)
8403 struct drm_i915_private *i915;
8406 i915 = mchdev_get();
8410 ret = i915->gt.awake;
8412 drm_dev_put(&i915->drm);
8415 EXPORT_SYMBOL_GPL(i915_gpu_busy);
8418 * i915_gpu_turbo_disable - disable graphics turbo
8420 * Disable graphics turbo by resetting the max frequency and setting the
8421 * current frequency to the default.
8423 bool i915_gpu_turbo_disable(void)
8425 struct drm_i915_private *i915;
8428 i915 = mchdev_get();
8432 spin_lock_irq(&mchdev_lock);
8433 i915->ips.max_delay = i915->ips.fstart;
8434 ret = ironlake_set_drps(i915, i915->ips.fstart);
8435 spin_unlock_irq(&mchdev_lock);
8437 drm_dev_put(&i915->drm);
8440 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
8443 * Tells the intel_ips driver that the i915 driver is now loaded, if
8444 * IPS got loaded first.
8446 * This awkward dance is so that neither module has to depend on the
8447 * other in order for IPS to do the appropriate communication of
8448 * GPU turbo limits to i915.
8451 ips_ping_for_i915_load(void)
8455 link = symbol_get(ips_link_to_i915_driver);
8458 symbol_put(ips_link_to_i915_driver);
8462 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
8464 /* We only register the i915 ips part with intel-ips once everything is
8465 * set up, to avoid intel-ips sneaking in and reading bogus values. */
8466 rcu_assign_pointer(i915_mch_dev, dev_priv);
8468 ips_ping_for_i915_load();
8471 void intel_gpu_ips_teardown(void)
8473 rcu_assign_pointer(i915_mch_dev, NULL);
8476 static void intel_init_emon(struct drm_i915_private *dev_priv)
8482 /* Disable to program */
8486 /* Program energy weights for various events */
8487 I915_WRITE(SDEW, 0x15040d00);
8488 I915_WRITE(CSIEW0, 0x007f0000);
8489 I915_WRITE(CSIEW1, 0x1e220004);
8490 I915_WRITE(CSIEW2, 0x04000004);
8492 for (i = 0; i < 5; i++)
8493 I915_WRITE(PEW(i), 0);
8494 for (i = 0; i < 3; i++)
8495 I915_WRITE(DEW(i), 0);
8497 /* Program P-state weights to account for frequency power adjustment */
8498 for (i = 0; i < 16; i++) {
8499 u32 pxvidfreq = I915_READ(PXVFREQ(i));
8500 unsigned long freq = intel_pxfreq(pxvidfreq);
8501 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8506 val *= (freq / 1000);
8508 val /= (127*127*900);
8510 DRM_ERROR("bad pxval: %ld\n", val);
8513 /* Render standby states get 0 weight */
8517 for (i = 0; i < 4; i++) {
8518 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8519 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8520 I915_WRITE(PXW(i), val);
8523 /* Adjust magic regs to magic values (more experimental results) */
8524 I915_WRITE(OGW0, 0);
8525 I915_WRITE(OGW1, 0);
8526 I915_WRITE(EG0, 0x00007f00);
8527 I915_WRITE(EG1, 0x0000000e);
8528 I915_WRITE(EG2, 0x000e0000);
8529 I915_WRITE(EG3, 0x68000300);
8530 I915_WRITE(EG4, 0x42000000);
8531 I915_WRITE(EG5, 0x00140031);
8535 for (i = 0; i < 8; i++)
8536 I915_WRITE(PXWL(i), 0);
8538 /* Enable PMON + select events */
8539 I915_WRITE(ECR, 0x80000019);
8541 lcfuse = I915_READ(LCFUSE02);
8543 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
8546 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
8548 struct intel_rps *rps = &dev_priv->gt_pm.rps;
8551 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
8554 if (!sanitize_rc6(dev_priv)) {
8555 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
8556 pm_runtime_get(&dev_priv->drm.pdev->dev);
8559 /* Initialize RPS limits (for userspace) */
8560 if (IS_CHERRYVIEW(dev_priv))
8561 cherryview_init_gt_powersave(dev_priv);
8562 else if (IS_VALLEYVIEW(dev_priv))
8563 valleyview_init_gt_powersave(dev_priv);
8564 else if (INTEL_GEN(dev_priv) >= 6)
8565 gen6_init_rps_frequencies(dev_priv);
8567 /* Derive initial user preferences/limits from the hardware limits */
8568 rps->max_freq_softlimit = rps->max_freq;
8569 rps->min_freq_softlimit = rps->min_freq;
8571 /* After setting max-softlimit, find the overclock max freq */
8572 if (IS_GEN(dev_priv, 6) ||
8573 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
8576 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS,
8578 if (params & BIT(31)) { /* OC supported */
8579 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
8580 (rps->max_freq & 0xff) * 50,
8581 (params & 0xff) * 50);
8582 rps->max_freq = params & 0xff;
8586 /* Finally allow us to boost to max by default */
8587 rps->boost_freq = rps->max_freq;
8588 rps->idle_freq = rps->min_freq;
8589 rps->cur_freq = rps->idle_freq;
8592 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
8594 if (IS_VALLEYVIEW(dev_priv))
8595 valleyview_cleanup_gt_powersave(dev_priv);
8597 if (!HAS_RC6(dev_priv))
8598 pm_runtime_put(&dev_priv->drm.pdev->dev);
8601 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
8603 dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
8604 dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
8605 intel_disable_gt_powersave(dev_priv);
8607 if (INTEL_GEN(dev_priv) >= 11)
8608 gen11_reset_rps_interrupts(dev_priv);
8609 else if (INTEL_GEN(dev_priv) >= 6)
8610 gen6_reset_rps_interrupts(dev_priv);
8613 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
8615 lockdep_assert_held(&i915->gt_pm.rps.lock);
8617 if (!i915->gt_pm.llc_pstate.enabled)
8620 /* Currently there is no HW configuration to be done to disable. */
8622 i915->gt_pm.llc_pstate.enabled = false;
8625 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
8627 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8629 if (!dev_priv->gt_pm.rc6.enabled)
8632 if (INTEL_GEN(dev_priv) >= 9)
8633 gen9_disable_rc6(dev_priv);
8634 else if (IS_CHERRYVIEW(dev_priv))
8635 cherryview_disable_rc6(dev_priv);
8636 else if (IS_VALLEYVIEW(dev_priv))
8637 valleyview_disable_rc6(dev_priv);
8638 else if (INTEL_GEN(dev_priv) >= 6)
8639 gen6_disable_rc6(dev_priv);
8641 dev_priv->gt_pm.rc6.enabled = false;
8644 static void intel_disable_rps(struct drm_i915_private *dev_priv)
8646 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8648 if (!dev_priv->gt_pm.rps.enabled)
8651 if (INTEL_GEN(dev_priv) >= 9)
8652 gen9_disable_rps(dev_priv);
8653 else if (IS_CHERRYVIEW(dev_priv))
8654 cherryview_disable_rps(dev_priv);
8655 else if (IS_VALLEYVIEW(dev_priv))
8656 valleyview_disable_rps(dev_priv);
8657 else if (INTEL_GEN(dev_priv) >= 6)
8658 gen6_disable_rps(dev_priv);
8659 else if (IS_IRONLAKE_M(dev_priv))
8660 ironlake_disable_drps(dev_priv);
8662 dev_priv->gt_pm.rps.enabled = false;
8665 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8667 mutex_lock(&dev_priv->gt_pm.rps.lock);
8669 intel_disable_rc6(dev_priv);
8670 intel_disable_rps(dev_priv);
8671 if (HAS_LLC(dev_priv))
8672 intel_disable_llc_pstate(dev_priv);
8674 mutex_unlock(&dev_priv->gt_pm.rps.lock);
8677 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
8679 lockdep_assert_held(&i915->gt_pm.rps.lock);
8681 if (i915->gt_pm.llc_pstate.enabled)
8684 gen6_update_ring_freq(i915);
8686 i915->gt_pm.llc_pstate.enabled = true;
8689 static void intel_enable_rc6(struct drm_i915_private *dev_priv)
8691 lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
8693 if (dev_priv->gt_pm.rc6.enabled)
8696 if (IS_CHERRYVIEW(dev_priv))
8697 cherryview_enable_rc6(dev_priv);
8698 else if (IS_VALLEYVIEW(dev_priv))
8699 valleyview_enable_rc6(dev_priv);
8700 else if (INTEL_GEN(dev_priv) >= 11)
8701 gen11_enable_rc6(dev_priv);
8702 else if (INTEL_GEN(dev_priv) >= 9)
8703 gen9_enable_rc6(dev_priv);
8704 else if (IS_BROADWELL(dev_priv))
8705 gen8_enable_rc6(dev_priv);
8706 else if (INTEL_GEN(dev_priv) >= 6)
8707 gen6_enable_rc6(dev_priv);
8709 dev_priv->gt_pm.rc6.enabled = true;
8712 static void intel_enable_rps(struct drm_i915_private *dev_priv)
8714 struct intel_rps *rps = &dev_priv->gt_pm.rps;
8716 lockdep_assert_held(&rps->lock);
8721 if (IS_CHERRYVIEW(dev_priv)) {
8722 cherryview_enable_rps(dev_priv);
8723 } else if (IS_VALLEYVIEW(dev_priv)) {
8724 valleyview_enable_rps(dev_priv);
8725 } else if (INTEL_GEN(dev_priv) >= 9) {
8726 gen9_enable_rps(dev_priv);
8727 } else if (IS_BROADWELL(dev_priv)) {
8728 gen8_enable_rps(dev_priv);
8729 } else if (INTEL_GEN(dev_priv) >= 6) {
8730 gen6_enable_rps(dev_priv);
8731 } else if (IS_IRONLAKE_M(dev_priv)) {
8732 ironlake_enable_drps(dev_priv);
8733 intel_init_emon(dev_priv);
8736 WARN_ON(rps->max_freq < rps->min_freq);
8737 WARN_ON(rps->idle_freq > rps->max_freq);
8739 WARN_ON(rps->efficient_freq < rps->min_freq);
8740 WARN_ON(rps->efficient_freq > rps->max_freq);
8742 rps->enabled = true;
8745 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8747 /* Powersaving is controlled by the host when inside a VM */
8748 if (intel_vgpu_active(dev_priv))
8751 mutex_lock(&dev_priv->gt_pm.rps.lock);
8753 if (HAS_RC6(dev_priv))
8754 intel_enable_rc6(dev_priv);
8755 if (HAS_RPS(dev_priv))
8756 intel_enable_rps(dev_priv);
8757 if (HAS_LLC(dev_priv))
8758 intel_enable_llc_pstate(dev_priv);
8760 mutex_unlock(&dev_priv->gt_pm.rps.lock);
8763 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
8766 * On Ibex Peak and Cougar Point, we need to disable clock
8767 * gating for the panel power sequencer or it will fail to
8768 * start up when no ports are active.
8770 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8773 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
8777 for_each_pipe(dev_priv, pipe) {
8778 I915_WRITE(DSPCNTR(pipe),
8779 I915_READ(DSPCNTR(pipe)) |
8780 DISPPLANE_TRICKLE_FEED_DISABLE);
8782 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
8783 POSTING_READ(DSPSURF(pipe));
8787 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
8789 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8793 * WaFbcDisableDpfcClockGating:ilk
8795 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
8796 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
8797 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
8799 I915_WRITE(PCH_3DCGDIS0,
8800 MARIUNIT_CLOCK_GATE_DISABLE |
8801 SVSMUNIT_CLOCK_GATE_DISABLE);
8802 I915_WRITE(PCH_3DCGDIS1,
8803 VFMUNIT_CLOCK_GATE_DISABLE);
8806 * According to the spec the following bits should be set in
8807 * order to enable memory self-refresh
8808 * The bit 22/21 of 0x42004
8809 * The bit 5 of 0x42020
8810 * The bit 15 of 0x45000
8812 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8813 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8814 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8815 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8816 I915_WRITE(DISP_ARB_CTL,
8817 (I915_READ(DISP_ARB_CTL) |
8821 * Based on the document from hardware guys the following bits
8822 * should be set unconditionally in order to enable FBC.
8823 * The bit 22 of 0x42000
8824 * The bit 22 of 0x42004
8825 * The bit 7,8,9 of 0x42020.
8827 if (IS_IRONLAKE_M(dev_priv)) {
8828 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8829 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8830 I915_READ(ILK_DISPLAY_CHICKEN1) |
8832 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8833 I915_READ(ILK_DISPLAY_CHICKEN2) |
8837 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8839 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8840 I915_READ(ILK_DISPLAY_CHICKEN2) |
8841 ILK_ELPIN_409_SELECT);
8842 I915_WRITE(_3D_CHICKEN2,
8843 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8844 _3D_CHICKEN2_WM_READ_PIPELINED);
8846 /* WaDisableRenderCachePipelinedFlush:ilk */
8847 I915_WRITE(CACHE_MODE_0,
8848 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8850 /* WaDisable_RenderCache_OperationalFlush:ilk */
8851 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8853 g4x_disable_trickle_feed(dev_priv);
8855 ibx_init_clock_gating(dev_priv);
8858 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8864 * On Ibex Peak and Cougar Point, we need to disable clock
8865 * gating for the panel power sequencer or it will fail to
8866 * start up when no ports are active.
8868 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8869 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8870 PCH_CPUNIT_CLOCK_GATE_DISABLE);
8871 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8872 DPLS_EDP_PPS_FIX_DIS);
8873 /* The below fixes the weird display corruption, a few pixels shifted
8874 * downward, on (only) LVDS of some HP laptops with IVY.
8876 for_each_pipe(dev_priv, pipe) {
8877 val = I915_READ(TRANS_CHICKEN2(pipe));
8878 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8879 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8880 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8881 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8882 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8883 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8884 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8885 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8887 /* WADP0ClockGatingDisable */
8888 for_each_pipe(dev_priv, pipe) {
8889 I915_WRITE(TRANS_CHICKEN1(pipe),
8890 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8894 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8898 tmp = I915_READ(MCH_SSKPD);
8899 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8900 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8904 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8906 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8908 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8910 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8911 I915_READ(ILK_DISPLAY_CHICKEN2) |
8912 ILK_ELPIN_409_SELECT);
8914 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8915 I915_WRITE(_3D_CHICKEN,
8916 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8918 /* WaDisable_RenderCache_OperationalFlush:snb */
8919 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8922 * BSpec recoomends 8x4 when MSAA is used,
8923 * however in practice 16x4 seems fastest.
8925 * Note that PS/WM thread counts depend on the WIZ hashing
8926 * disable bit, which we don't touch here, but it's good
8927 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8929 I915_WRITE(GEN6_GT_MODE,
8930 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8932 I915_WRITE(CACHE_MODE_0,
8933 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8935 I915_WRITE(GEN6_UCGCTL1,
8936 I915_READ(GEN6_UCGCTL1) |
8937 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8938 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8940 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8941 * gating disable must be set. Failure to set it results in
8942 * flickering pixels due to Z write ordering failures after
8943 * some amount of runtime in the Mesa "fire" demo, and Unigine
8944 * Sanctuary and Tropics, and apparently anything else with
8945 * alpha test or pixel discard.
8947 * According to the spec, bit 11 (RCCUNIT) must also be set,
8948 * but we didn't debug actual testcases to find it out.
8950 * WaDisableRCCUnitClockGating:snb
8951 * WaDisableRCPBUnitClockGating:snb
8953 I915_WRITE(GEN6_UCGCTL2,
8954 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8955 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8957 /* WaStripsFansDisableFastClipPerformanceFix:snb */
8958 I915_WRITE(_3D_CHICKEN3,
8959 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8963 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8964 * 3DSTATE_SF number of SF output attributes is more than 16."
8966 I915_WRITE(_3D_CHICKEN3,
8967 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8970 * According to the spec the following bits should be
8971 * set in order to enable memory self-refresh and fbc:
8972 * The bit21 and bit22 of 0x42000
8973 * The bit21 and bit22 of 0x42004
8974 * The bit5 and bit7 of 0x42020
8975 * The bit14 of 0x70180
8976 * The bit14 of 0x71180
8978 * WaFbcAsynchFlipDisableFbcQueue:snb
8980 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8981 I915_READ(ILK_DISPLAY_CHICKEN1) |
8982 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8983 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8984 I915_READ(ILK_DISPLAY_CHICKEN2) |
8985 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8986 I915_WRITE(ILK_DSPCLK_GATE_D,
8987 I915_READ(ILK_DSPCLK_GATE_D) |
8988 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
8989 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8991 g4x_disable_trickle_feed(dev_priv);
8993 cpt_init_clock_gating(dev_priv);
8995 gen6_check_mch_setup(dev_priv);
8998 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
9000 u32 reg = I915_READ(GEN7_FF_THREAD_MODE);
9003 * WaVSThreadDispatchOverride:ivb,vlv
9005 * This actually overrides the dispatch
9006 * mode for all thread types.
9008 reg &= ~GEN7_FF_SCHED_MASK;
9009 reg |= GEN7_FF_TS_SCHED_HW;
9010 reg |= GEN7_FF_VS_SCHED_HW;
9011 reg |= GEN7_FF_DS_SCHED_HW;
9013 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
9016 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
9019 * TODO: this bit should only be enabled when really needed, then
9020 * disabled when not needed anymore in order to save power.
9022 if (HAS_PCH_LPT_LP(dev_priv))
9023 I915_WRITE(SOUTH_DSPCLK_GATE_D,
9024 I915_READ(SOUTH_DSPCLK_GATE_D) |
9025 PCH_LP_PARTITION_LEVEL_DISABLE);
9027 /* WADPOClockGatingDisable:hsw */
9028 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
9029 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
9030 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
9033 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
9035 if (HAS_PCH_LPT_LP(dev_priv)) {
9036 u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9038 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9039 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9043 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
9044 int general_prio_credits,
9045 int high_prio_credits)
9050 /* WaTempDisableDOPClkGating:bdw */
9051 misccpctl = I915_READ(GEN7_MISCCPCTL);
9052 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
9054 val = I915_READ(GEN8_L3SQCREG1);
9055 val &= ~L3_PRIO_CREDITS_MASK;
9056 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
9057 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
9058 I915_WRITE(GEN8_L3SQCREG1, val);
9061 * Wait at least 100 clocks before re-enabling clock gating.
9062 * See the definition of L3SQCREG1 in BSpec.
9064 POSTING_READ(GEN8_L3SQCREG1);
9066 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
9069 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
9071 /* This is not an Wa. Enable to reduce Sampler power */
9072 I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
9073 I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
9075 /* WaEnable32PlaneMode:icl */
9076 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
9077 _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
9080 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
9082 if (!HAS_PCH_CNP(dev_priv))
9085 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
9086 I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
9087 CNP_PWM_CGE_GATING_DISABLE);
9090 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
9093 cnp_init_clock_gating(dev_priv);
9095 /* This is not an Wa. Enable for better image quality */
9096 I915_WRITE(_3D_CHICKEN3,
9097 _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
9099 /* WaEnableChickenDCPR:cnl */
9100 I915_WRITE(GEN8_CHICKEN_DCPR_1,
9101 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
9103 /* WaFbcWakeMemOn:cnl */
9104 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
9105 DISP_FBC_MEMORY_WAKE);
9107 val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
9108 /* ReadHitWriteOnlyDisable:cnl */
9109 val |= RCCUNIT_CLKGATE_DIS;
9110 /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
9111 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
9112 val |= SARBUNIT_CLKGATE_DIS;
9113 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
9115 /* Wa_2201832410:cnl */
9116 val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
9117 val |= GWUNIT_CLKGATE_DIS;
9118 I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
9120 /* WaDisableVFclkgate:cnl */
9121 /* WaVFUnitClockGatingDisable:cnl */
9122 val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
9123 val |= VFUNIT_CLKGATE_DIS;
9124 I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
9127 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
9129 cnp_init_clock_gating(dev_priv);
9130 gen9_init_clock_gating(dev_priv);
9132 /* WaFbcNukeOnHostModify:cfl */
9133 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9134 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9137 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
9139 gen9_init_clock_gating(dev_priv);
9141 /* WaDisableSDEUnitClockGating:kbl */
9142 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
9143 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9144 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9146 /* WaDisableGamClockGating:kbl */
9147 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
9148 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
9149 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
9151 /* WaFbcNukeOnHostModify:kbl */
9152 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9153 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9156 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
9158 gen9_init_clock_gating(dev_priv);
9160 /* WAC6entrylatency:skl */
9161 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
9162 FBC_LLC_FULLY_OPEN);
9164 /* WaFbcNukeOnHostModify:skl */
9165 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
9166 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9169 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
9171 /* The GTT cache must be disabled if the system is using 2M pages. */
9172 bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
9173 I915_GTT_PAGE_SIZE_2M);
9176 /* WaSwitchSolVfFArbitrationPriority:bdw */
9177 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
9179 /* WaPsrDPAMaskVBlankInSRD:bdw */
9180 I915_WRITE(CHICKEN_PAR1_1,
9181 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
9183 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
9184 for_each_pipe(dev_priv, pipe) {
9185 I915_WRITE(CHICKEN_PIPESL_1(pipe),
9186 I915_READ(CHICKEN_PIPESL_1(pipe)) |
9187 BDW_DPRS_MASK_VBLANK_SRD);
9190 /* WaVSRefCountFullforceMissDisable:bdw */
9191 /* WaDSRefCountFullforceMissDisable:bdw */
9192 I915_WRITE(GEN7_FF_THREAD_MODE,
9193 I915_READ(GEN7_FF_THREAD_MODE) &
9194 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
9196 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
9197 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
9199 /* WaDisableSDEUnitClockGating:bdw */
9200 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9201 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9203 /* WaProgramL3SqcReg1Default:bdw */
9204 gen8_set_l3sqc_credits(dev_priv, 30, 2);
9206 /* WaGttCachingOffByDefault:bdw */
9207 I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
9209 /* WaKVMNotificationOnConfigChange:bdw */
9210 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
9211 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
9213 lpt_init_clock_gating(dev_priv);
9215 /* WaDisableDopClockGating:bdw
9217 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
9220 I915_WRITE(GEN6_UCGCTL1,
9221 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
9224 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
9226 /* L3 caching of data atomics doesn't work -- disable it. */
9227 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
9228 I915_WRITE(HSW_ROW_CHICKEN3,
9229 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
9231 /* This is required by WaCatErrorRejectionIssue:hsw */
9232 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9233 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9234 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9236 /* WaVSRefCountFullforceMissDisable:hsw */
9237 I915_WRITE(GEN7_FF_THREAD_MODE,
9238 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
9240 /* WaDisable_RenderCache_OperationalFlush:hsw */
9241 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9243 /* enable HiZ Raw Stall Optimization */
9244 I915_WRITE(CACHE_MODE_0_GEN7,
9245 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
9247 /* WaDisable4x2SubspanOptimization:hsw */
9248 I915_WRITE(CACHE_MODE_1,
9249 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9252 * BSpec recommends 8x4 when MSAA is used,
9253 * however in practice 16x4 seems fastest.
9255 * Note that PS/WM thread counts depend on the WIZ hashing
9256 * disable bit, which we don't touch here, but it's good
9257 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9259 I915_WRITE(GEN7_GT_MODE,
9260 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9262 /* WaSampleCChickenBitEnable:hsw */
9263 I915_WRITE(HALF_SLICE_CHICKEN3,
9264 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
9266 /* WaSwitchSolVfFArbitrationPriority:hsw */
9267 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
9269 lpt_init_clock_gating(dev_priv);
9272 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
9276 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
9278 /* WaDisableEarlyCull:ivb */
9279 I915_WRITE(_3D_CHICKEN3,
9280 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
9282 /* WaDisableBackToBackFlipFix:ivb */
9283 I915_WRITE(IVB_CHICKEN3,
9284 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9285 CHICKEN3_DGMG_DONE_FIX_DISABLE);
9287 /* WaDisablePSDDualDispatchEnable:ivb */
9288 if (IS_IVB_GT1(dev_priv))
9289 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
9290 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
9292 /* WaDisable_RenderCache_OperationalFlush:ivb */
9293 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9295 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
9296 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
9297 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
9299 /* WaApplyL3ControlAndL3ChickenMode:ivb */
9300 I915_WRITE(GEN7_L3CNTLREG1,
9301 GEN7_WA_FOR_GEN7_L3_CONTROL);
9302 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
9303 GEN7_WA_L3_CHICKEN_MODE);
9304 if (IS_IVB_GT1(dev_priv))
9305 I915_WRITE(GEN7_ROW_CHICKEN2,
9306 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9308 /* must write both registers */
9309 I915_WRITE(GEN7_ROW_CHICKEN2,
9310 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9311 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
9312 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9315 /* WaForceL3Serialization:ivb */
9316 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
9317 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
9320 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
9321 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
9323 I915_WRITE(GEN6_UCGCTL2,
9324 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9326 /* This is required by WaCatErrorRejectionIssue:ivb */
9327 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9328 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9329 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9331 g4x_disable_trickle_feed(dev_priv);
9333 gen7_setup_fixed_func_scheduler(dev_priv);
9335 if (0) { /* causes HiZ corruption on ivb:gt1 */
9336 /* enable HiZ Raw Stall Optimization */
9337 I915_WRITE(CACHE_MODE_0_GEN7,
9338 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
9341 /* WaDisable4x2SubspanOptimization:ivb */
9342 I915_WRITE(CACHE_MODE_1,
9343 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9346 * BSpec recommends 8x4 when MSAA is used,
9347 * however in practice 16x4 seems fastest.
9349 * Note that PS/WM thread counts depend on the WIZ hashing
9350 * disable bit, which we don't touch here, but it's good
9351 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9353 I915_WRITE(GEN7_GT_MODE,
9354 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9356 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
9357 snpcr &= ~GEN6_MBC_SNPCR_MASK;
9358 snpcr |= GEN6_MBC_SNPCR_MED;
9359 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
9361 if (!HAS_PCH_NOP(dev_priv))
9362 cpt_init_clock_gating(dev_priv);
9364 gen6_check_mch_setup(dev_priv);
9367 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
9369 /* WaDisableEarlyCull:vlv */
9370 I915_WRITE(_3D_CHICKEN3,
9371 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
9373 /* WaDisableBackToBackFlipFix:vlv */
9374 I915_WRITE(IVB_CHICKEN3,
9375 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
9376 CHICKEN3_DGMG_DONE_FIX_DISABLE);
9378 /* WaPsdDispatchEnable:vlv */
9379 /* WaDisablePSDDualDispatchEnable:vlv */
9380 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
9381 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
9382 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
9384 /* WaDisable_RenderCache_OperationalFlush:vlv */
9385 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9387 /* WaForceL3Serialization:vlv */
9388 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
9389 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
9391 /* WaDisableDopClockGating:vlv */
9392 I915_WRITE(GEN7_ROW_CHICKEN2,
9393 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
9395 /* This is required by WaCatErrorRejectionIssue:vlv */
9396 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
9397 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
9398 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
9400 gen7_setup_fixed_func_scheduler(dev_priv);
9403 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
9404 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
9406 I915_WRITE(GEN6_UCGCTL2,
9407 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
9409 /* WaDisableL3Bank2xClockGate:vlv
9410 * Disabling L3 clock gating- MMIO 940c[25] = 1
9411 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
9412 I915_WRITE(GEN7_UCGCTL4,
9413 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
9416 * BSpec says this must be set, even though
9417 * WaDisable4x2SubspanOptimization isn't listed for VLV.
9419 I915_WRITE(CACHE_MODE_1,
9420 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
9423 * BSpec recommends 8x4 when MSAA is used,
9424 * however in practice 16x4 seems fastest.
9426 * Note that PS/WM thread counts depend on the WIZ hashing
9427 * disable bit, which we don't touch here, but it's good
9428 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
9430 I915_WRITE(GEN7_GT_MODE,
9431 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
9434 * WaIncreaseL3CreditsForVLVB0:vlv
9435 * This is the hardware default actually.
9437 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
9440 * WaDisableVLVClockGating_VBIIssue:vlv
9441 * Disable clock gating on th GCFG unit to prevent a delay
9442 * in the reporting of vblank events.
9444 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
9447 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
9449 /* WaVSRefCountFullforceMissDisable:chv */
9450 /* WaDSRefCountFullforceMissDisable:chv */
9451 I915_WRITE(GEN7_FF_THREAD_MODE,
9452 I915_READ(GEN7_FF_THREAD_MODE) &
9453 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
9455 /* WaDisableSemaphoreAndSyncFlipWait:chv */
9456 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
9457 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
9459 /* WaDisableCSUnitClockGating:chv */
9460 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
9461 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
9463 /* WaDisableSDEUnitClockGating:chv */
9464 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9465 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
9468 * WaProgramL3SqcReg1Default:chv
9469 * See gfxspecs/Related Documents/Performance Guide/
9470 * LSQC Setting Recommendations.
9472 gen8_set_l3sqc_credits(dev_priv, 38, 2);
9475 * GTT cache may not work with big pages, so if those
9476 * are ever enabled GTT cache may need to be disabled.
9478 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
9481 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
9485 I915_WRITE(RENCLK_GATE_D1, 0);
9486 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
9487 GS_UNIT_CLOCK_GATE_DISABLE |
9488 CL_UNIT_CLOCK_GATE_DISABLE);
9489 I915_WRITE(RAMCLK_GATE_D, 0);
9490 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
9491 OVRUNIT_CLOCK_GATE_DISABLE |
9492 OVCUNIT_CLOCK_GATE_DISABLE;
9493 if (IS_GM45(dev_priv))
9494 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
9495 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
9497 /* WaDisableRenderCachePipelinedFlush */
9498 I915_WRITE(CACHE_MODE_0,
9499 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
9501 /* WaDisable_RenderCache_OperationalFlush:g4x */
9502 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9504 g4x_disable_trickle_feed(dev_priv);
9507 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
9509 struct intel_uncore *uncore = &dev_priv->uncore;
9511 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
9512 intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
9513 intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
9514 intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
9515 intel_uncore_write16(uncore, DEUC, 0);
9516 intel_uncore_write(uncore,
9518 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9520 /* WaDisable_RenderCache_OperationalFlush:gen4 */
9521 intel_uncore_write(uncore,
9523 _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9526 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
9528 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
9529 I965_RCC_CLOCK_GATE_DISABLE |
9530 I965_RCPB_CLOCK_GATE_DISABLE |
9531 I965_ISC_CLOCK_GATE_DISABLE |
9532 I965_FBC_CLOCK_GATE_DISABLE);
9533 I915_WRITE(RENCLK_GATE_D2, 0);
9534 I915_WRITE(MI_ARB_STATE,
9535 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9537 /* WaDisable_RenderCache_OperationalFlush:gen4 */
9538 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
9541 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
9543 u32 dstate = I915_READ(D_STATE);
9545 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
9546 DSTATE_DOT_CLOCK_GATING;
9547 I915_WRITE(D_STATE, dstate);
9549 if (IS_PINEVIEW(dev_priv))
9550 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
9552 /* IIR "flip pending" means done if this bit is set */
9553 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
9555 /* interrupts should cause a wake up from C3 */
9556 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
9558 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
9559 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
9561 I915_WRITE(MI_ARB_STATE,
9562 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
9565 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
9567 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
9569 /* interrupts should cause a wake up from C3 */
9570 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
9571 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
9573 I915_WRITE(MEM_MODE,
9574 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
9577 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
9579 I915_WRITE(MEM_MODE,
9580 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
9581 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
9584 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
9586 dev_priv->display.init_clock_gating(dev_priv);
9589 void intel_suspend_hw(struct drm_i915_private *dev_priv)
9591 if (HAS_PCH_LPT(dev_priv))
9592 lpt_suspend_hw(dev_priv);
9595 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
9597 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9601 * intel_init_clock_gating_hooks - setup the clock gating hooks
9602 * @dev_priv: device private
9604 * Setup the hooks that configure which clocks of a given platform can be
9605 * gated and also apply various GT and display specific workarounds for these
9606 * platforms. Note that some GT specific workarounds are applied separately
9607 * when GPU contexts or batchbuffers start their execution.
9609 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9611 if (IS_GEN(dev_priv, 11))
9612 dev_priv->display.init_clock_gating = icl_init_clock_gating;
9613 else if (IS_CANNONLAKE(dev_priv))
9614 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
9615 else if (IS_COFFEELAKE(dev_priv))
9616 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
9617 else if (IS_SKYLAKE(dev_priv))
9618 dev_priv->display.init_clock_gating = skl_init_clock_gating;
9619 else if (IS_KABYLAKE(dev_priv))
9620 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
9621 else if (IS_BROXTON(dev_priv))
9622 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9623 else if (IS_GEMINILAKE(dev_priv))
9624 dev_priv->display.init_clock_gating = glk_init_clock_gating;
9625 else if (IS_BROADWELL(dev_priv))
9626 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
9627 else if (IS_CHERRYVIEW(dev_priv))
9628 dev_priv->display.init_clock_gating = chv_init_clock_gating;
9629 else if (IS_HASWELL(dev_priv))
9630 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
9631 else if (IS_IVYBRIDGE(dev_priv))
9632 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9633 else if (IS_VALLEYVIEW(dev_priv))
9634 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9635 else if (IS_GEN(dev_priv, 6))
9636 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9637 else if (IS_GEN(dev_priv, 5))
9638 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9639 else if (IS_G4X(dev_priv))
9640 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9641 else if (IS_I965GM(dev_priv))
9642 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9643 else if (IS_I965G(dev_priv))
9644 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9645 else if (IS_GEN(dev_priv, 3))
9646 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9647 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9648 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9649 else if (IS_GEN(dev_priv, 2))
9650 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9652 MISSING_CASE(INTEL_DEVID(dev_priv));
9653 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9657 /* Set up chip specific power management-related functions */
9658 void intel_init_pm(struct drm_i915_private *dev_priv)
9661 if (IS_PINEVIEW(dev_priv))
9662 i915_pineview_get_mem_freq(dev_priv);
9663 else if (IS_GEN(dev_priv, 5))
9664 i915_ironlake_get_mem_freq(dev_priv);
9666 /* For FIFO watermark updates */
9667 if (INTEL_GEN(dev_priv) >= 9) {
9668 skl_setup_wm_latency(dev_priv);
9669 dev_priv->display.initial_watermarks = skl_initial_wm;
9670 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
9671 dev_priv->display.compute_global_watermarks = skl_compute_wm;
9672 } else if (HAS_PCH_SPLIT(dev_priv)) {
9673 ilk_setup_wm_latency(dev_priv);
9675 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
9676 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9677 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
9678 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9679 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9680 dev_priv->display.compute_intermediate_wm =
9681 ilk_compute_intermediate_wm;
9682 dev_priv->display.initial_watermarks =
9683 ilk_initial_watermarks;
9684 dev_priv->display.optimize_watermarks =
9685 ilk_optimize_watermarks;
9687 DRM_DEBUG_KMS("Failed to read display plane latency. "
9690 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9691 vlv_setup_wm_latency(dev_priv);
9692 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
9693 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
9694 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
9695 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
9696 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
9697 } else if (IS_G4X(dev_priv)) {
9698 g4x_setup_wm_latency(dev_priv);
9699 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
9700 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
9701 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
9702 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
9703 } else if (IS_PINEVIEW(dev_priv)) {
9704 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
9707 dev_priv->mem_freq)) {
9708 DRM_INFO("failed to find known CxSR latency "
9709 "(found ddr%s fsb freq %d, mem freq %d), "
9711 (dev_priv->is_ddr3 == 1) ? "3" : "2",
9712 dev_priv->fsb_freq, dev_priv->mem_freq);
9713 /* Disable CxSR and never update its watermark again */
9714 intel_set_memory_cxsr(dev_priv, false);
9715 dev_priv->display.update_wm = NULL;
9717 dev_priv->display.update_wm = pineview_update_wm;
9718 } else if (IS_GEN(dev_priv, 4)) {
9719 dev_priv->display.update_wm = i965_update_wm;
9720 } else if (IS_GEN(dev_priv, 3)) {
9721 dev_priv->display.update_wm = i9xx_update_wm;
9722 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9723 } else if (IS_GEN(dev_priv, 2)) {
9724 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9725 dev_priv->display.update_wm = i845_update_wm;
9726 dev_priv->display.get_fifo_size = i845_get_fifo_size;
9728 dev_priv->display.update_wm = i9xx_update_wm;
9729 dev_priv->display.get_fifo_size = i830_get_fifo_size;
9732 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9736 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9738 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9742 * Slow = Fast = GPLL ref * N
9744 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
9747 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9749 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9751 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
9754 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9756 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9760 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9762 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
9765 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9767 struct intel_rps *rps = &dev_priv->gt_pm.rps;
9769 /* CHV needs even values */
9770 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
9773 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9775 if (INTEL_GEN(dev_priv) >= 9)
9776 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9778 else if (IS_CHERRYVIEW(dev_priv))
9779 return chv_gpu_freq(dev_priv, val);
9780 else if (IS_VALLEYVIEW(dev_priv))
9781 return byt_gpu_freq(dev_priv, val);
9783 return val * GT_FREQUENCY_MULTIPLIER;
9786 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9788 if (INTEL_GEN(dev_priv) >= 9)
9789 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9790 GT_FREQUENCY_MULTIPLIER);
9791 else if (IS_CHERRYVIEW(dev_priv))
9792 return chv_freq_opcode(dev_priv, val);
9793 else if (IS_VALLEYVIEW(dev_priv))
9794 return byt_freq_opcode(dev_priv, val);
9796 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9799 void intel_pm_setup(struct drm_i915_private *dev_priv)
9801 mutex_init(&dev_priv->gt_pm.rps.lock);
9802 mutex_init(&dev_priv->gt_pm.rps.power.mutex);
9804 atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
9806 dev_priv->runtime_pm.suspended = false;
9807 atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
9810 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9811 const i915_reg_t reg)
9813 u32 lower, upper, tmp;
9817 * The register accessed do not need forcewake. We borrow
9818 * uncore lock to prevent concurrent access to range reg.
9820 lockdep_assert_held(&dev_priv->uncore.lock);
9823 * vlv and chv residency counters are 40 bits in width.
9824 * With a control bit, we can choose between upper or lower
9825 * 32bit window into this counter.
9827 * Although we always use the counter in high-range mode elsewhere,
9828 * userspace may attempt to read the value before rc6 is initialised,
9829 * before we have set the default VLV_COUNTER_CONTROL value. So always
9830 * set the high bit to be safe.
9832 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9833 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9834 upper = I915_READ_FW(reg);
9838 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9839 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9840 lower = I915_READ_FW(reg);
9842 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9843 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9844 upper = I915_READ_FW(reg);
9845 } while (upper != tmp && --loop);
9848 * Everywhere else we always use VLV_COUNTER_CONTROL with the
9849 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9853 return lower | (u64)upper << 8;
9856 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
9857 const i915_reg_t reg)
9859 struct intel_uncore *uncore = &dev_priv->uncore;
9860 u64 time_hw, prev_hw, overflow_hw;
9861 unsigned int fw_domains;
9862 unsigned long flags;
9866 if (!HAS_RC6(dev_priv))
9870 * Store previous hw counter values for counter wrap-around handling.
9872 * There are only four interesting registers and they live next to each
9873 * other so we can use the relative address, compared to the smallest
9874 * one as the index into driver storage.
9876 i = (i915_mmio_reg_offset(reg) -
9877 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
9878 if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
9881 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
9883 spin_lock_irqsave(&uncore->lock, flags);
9884 intel_uncore_forcewake_get__locked(uncore, fw_domains);
9886 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9887 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9889 div = dev_priv->czclk_freq;
9890 overflow_hw = BIT_ULL(40);
9891 time_hw = vlv_residency_raw(dev_priv, reg);
9893 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
9894 if (IS_GEN9_LP(dev_priv)) {
9902 overflow_hw = BIT_ULL(32);
9903 time_hw = intel_uncore_read_fw(uncore, reg);
9907 * Counter wrap handling.
9909 * But relying on a sufficient frequency of queries otherwise counters
9912 prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];
9913 dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;
9915 /* RC6 delta from last sample. */
9916 if (time_hw >= prev_hw)
9919 time_hw += overflow_hw - prev_hw;
9921 /* Add delta to RC6 extended raw driver copy. */
9922 time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
9923 dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
9925 intel_uncore_forcewake_put__locked(uncore, fw_domains);
9926 spin_unlock_irqrestore(&uncore->lock, flags);
9928 return mul_u64_u32_div(time_hw, mul, div);
9931 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9934 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
9937 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
9941 if (INTEL_GEN(dev_priv) >= 9)
9942 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
9943 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
9944 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
9946 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;