2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <drm/i915_powerwell.h>
35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
46 static bool intel_crtc_active(struct drm_crtc *crtc)
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
54 static void i8xx_disable_fbc(struct drm_device *dev)
56 struct drm_i915_private *dev_priv = dev->dev_private;
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
73 DRM_DEBUG_KMS("disabled FBC\n");
76 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
86 u32 fbc_ctl, fbc_ctl2;
88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
119 static bool i8xx_fbc_enabled(struct drm_device *dev)
121 struct drm_i915_private *dev_priv = dev->dev_private;
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
153 static void g4x_disable_fbc(struct drm_device *dev)
155 struct drm_i915_private *dev_priv = dev->dev_private;
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164 DRM_DEBUG_KMS("disabled FBC\n");
168 static bool g4x_fbc_enabled(struct drm_device *dev)
170 struct drm_i915_private *dev_priv = dev->dev_private;
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
175 static void sandybridge_blit_fbc_update(struct drm_device *dev)
177 struct drm_i915_private *dev_priv = dev->dev_private;
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
195 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
233 static void ironlake_disable_fbc(struct drm_device *dev)
235 struct drm_i915_private *dev_priv = dev->dev_private;
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244 if (IS_IVYBRIDGE(dev))
245 /* WaFbcDisableDpfcClockGating:ivb */
246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
251 /* WaFbcDisableDpfcClockGating:hsw */
252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
256 DRM_DEBUG_KMS("disabled FBC\n");
260 static bool ironlake_fbc_enabled(struct drm_device *dev)
262 struct drm_i915_private *dev_priv = dev->dev_private;
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
267 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282 if (IS_IVYBRIDGE(dev)) {
283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
285 /* WaFbcDisableDpfcClockGating:ivb */
286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
293 /* WaFbcDisableDpfcClockGating:hsw */
294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
303 sandybridge_blit_fbc_update(dev);
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
308 bool intel_fbc_enabled(struct drm_device *dev)
310 struct drm_i915_private *dev_priv = dev->dev_private;
312 if (!dev_priv->display.fbc_enabled)
315 return dev_priv->display.fbc_enabled(dev);
318 static void intel_fbc_work_fn(struct work_struct *__work)
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
326 mutex_lock(&dev->struct_mutex);
327 if (work == dev_priv->fbc.fbc_work) {
328 /* Double check that we haven't switched fb without cancelling
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
340 dev_priv->fbc.fbc_work = NULL;
342 mutex_unlock(&dev->struct_mutex);
347 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349 if (dev_priv->fbc.fbc_work == NULL)
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354 /* Synchronisation is provided by struct_mutex and checking of
355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
356 * entirely asynchronously.
358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
359 /* tasklet was killed before being run, clean up */
360 kfree(dev_priv->fbc.fbc_work);
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
367 dev_priv->fbc.fbc_work = NULL;
370 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
376 if (!dev_priv->display.enable_fbc)
379 intel_cancel_fbc_work(dev_priv);
381 work = kzalloc(sizeof *work, GFP_KERNEL);
383 DRM_ERROR("Failed to allocate FBC work structure\n");
384 dev_priv->display.enable_fbc(crtc, interval);
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
393 dev_priv->fbc.fbc_work = work;
395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
411 void intel_disable_fbc(struct drm_device *dev)
413 struct drm_i915_private *dev_priv = dev->dev_private;
415 intel_cancel_fbc_work(dev_priv);
417 if (!dev_priv->display.disable_fbc)
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->fbc.plane = -1;
424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
427 if (dev_priv->fbc.no_fbc_reason == reason)
430 dev_priv->fbc.no_fbc_reason = reason;
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
451 * We need to enable/disable FBC on a global basis.
453 void intel_update_fbc(struct drm_device *dev)
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
461 unsigned int max_hdisplay, max_vdisplay;
463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
495 if (!crtc || crtc->fb == NULL) {
496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
501 intel_crtc = to_intel_crtc(crtc);
503 intel_fb = to_intel_framebuffer(fb);
506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
512 if (!i915_enable_fbc) {
513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
555 /* If the kernel debugger is active, always disable compression */
559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
603 intel_enable_fbc(crtc, 500);
604 dev_priv->fbc.no_fbc_reason = FBC_OK;
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
613 i915_gem_stolen_cleanup_compression(dev);
616 static void i915_pineview_get_mem_freq(struct drm_device *dev)
618 drm_i915_private_t *dev_priv = dev->dev_private;
621 tmp = I915_READ(CLKCFG);
623 switch (tmp & CLKCFG_FSB_MASK) {
625 dev_priv->fsb_freq = 533; /* 133*4 */
628 dev_priv->fsb_freq = 800; /* 200*4 */
631 dev_priv->fsb_freq = 667; /* 167*4 */
634 dev_priv->fsb_freq = 400; /* 100*4 */
638 switch (tmp & CLKCFG_MEM_MASK) {
640 dev_priv->mem_freq = 533;
643 dev_priv->mem_freq = 667;
646 dev_priv->mem_freq = 800;
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
657 drm_i915_private_t *dev_priv = dev->dev_private;
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
663 switch (ddrpll & 0xff) {
665 dev_priv->mem_freq = 800;
668 dev_priv->mem_freq = 1066;
671 dev_priv->mem_freq = 1333;
674 dev_priv->mem_freq = 1600;
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
679 dev_priv->mem_freq = 0;
683 dev_priv->ips.r_t = dev_priv->mem_freq;
685 switch (csipll & 0x3ff) {
687 dev_priv->fsb_freq = 3200;
690 dev_priv->fsb_freq = 3733;
693 dev_priv->fsb_freq = 4266;
696 dev_priv->fsb_freq = 4800;
699 dev_priv->fsb_freq = 5333;
702 dev_priv->fsb_freq = 5866;
705 dev_priv->fsb_freq = 6400;
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
710 dev_priv->fsb_freq = 0;
714 if (dev_priv->fsb_freq == 3200) {
715 dev_priv->ips.c_m = 0;
716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
717 dev_priv->ips.c_m = 1;
719 dev_priv->ips.c_m = 2;
723 static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
766 const struct cxsr_latency *latency;
769 if (fsb == 0 || mem == 0)
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
785 static void pineview_disable_cxsr(struct drm_device *dev)
787 struct drm_i915_private *dev_priv = dev->dev_private;
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
807 static const int latency_ns = 5000;
809 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
815 size = dsparb & 0x7f;
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
825 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
831 size = dsparb & 0x1ff;
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
842 static int i845_get_fifo_size(struct drm_device *dev, int plane)
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
858 static int i830_get_fifo_size(struct drm_device *dev, int plane)
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
873 /* Pineview has different values for various configs */
874 static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
879 PINEVIEW_FIFO_LINE_SIZE
881 static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
884 PINEVIEW_DFT_HPLLOFF_WM,
886 PINEVIEW_FIFO_LINE_SIZE
888 static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
895 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
902 static const struct intel_watermark_params g4x_wm_info = {
909 static const struct intel_watermark_params g4x_cursor_wm_info = {
916 static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
923 static const struct intel_watermark_params valleyview_cursor_wm_info = {
925 VALLEYVIEW_CURSOR_MAX_WM,
930 static const struct intel_watermark_params i965_cursor_wm_info = {
937 static const struct intel_watermark_params i945_wm_info = {
944 static const struct intel_watermark_params i915_wm_info = {
951 static const struct intel_watermark_params i855_wm_info = {
958 static const struct intel_watermark_params i830_wm_info = {
966 static const struct intel_watermark_params ironlake_display_wm_info = {
973 static const struct intel_watermark_params ironlake_cursor_wm_info = {
980 static const struct intel_watermark_params ironlake_display_srwm_info = {
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
987 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
995 static const struct intel_watermark_params sandybridge_display_wm_info = {
1002 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1009 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1016 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1043 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1047 unsigned long latency_ns)
1049 long entries_required, wm_size;
1052 * Note: we need to make sure we don't overflow for various clock &
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1071 wm_size = wm->default_wm;
1075 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1077 struct drm_crtc *crtc, *enabled = NULL;
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1080 if (intel_crtc_active(crtc)) {
1090 static void pineview_update_wm(struct drm_device *dev)
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc;
1094 const struct cxsr_latency *latency;
1098 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099 dev_priv->fsb_freq, dev_priv->mem_freq);
1101 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102 pineview_disable_cxsr(dev);
1106 crtc = single_enabled_crtc(dev);
1108 int clock = crtc->mode.clock;
1109 int pixel_size = crtc->fb->bits_per_pixel / 8;
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1159 static bool g4x_compute_wm0(struct drm_device *dev,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1168 struct drm_crtc *crtc;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1173 crtc = intel_get_crtc_for_plane(dev, plane);
1174 if (!intel_crtc_active(crtc)) {
1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1180 htotal = crtc->mode.htotal;
1181 hdisplay = crtc->mode.hdisplay;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1185 /* Use the small buffer method to calculate plane watermark */
1186 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189 entries += tlb_miss;
1190 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191 *plane_wm = entries + display->guard_size;
1192 if (*plane_wm > (int)display->max_wm)
1193 *plane_wm = display->max_wm;
1195 /* Use the large buffer method to calculate cursor watermark */
1196 line_time_us = ((htotal * 1000) / clock);
1197 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198 entries = line_count * 64 * pixel_size;
1199 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201 entries += tlb_miss;
1202 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203 *cursor_wm = entries + cursor->guard_size;
1204 if (*cursor_wm > (int)cursor->max_wm)
1205 *cursor_wm = (int)cursor->max_wm;
1211 * Check the wm result.
1213 * If any calculated watermark values is larger than the maximum value that
1214 * can be programmed into the associated watermark register, that watermark
1217 static bool g4x_check_srwm(struct drm_device *dev,
1218 int display_wm, int cursor_wm,
1219 const struct intel_watermark_params *display,
1220 const struct intel_watermark_params *cursor)
1222 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223 display_wm, cursor_wm);
1225 if (display_wm > display->max_wm) {
1226 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227 display_wm, display->max_wm);
1231 if (cursor_wm > cursor->max_wm) {
1232 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233 cursor_wm, cursor->max_wm);
1237 if (!(display_wm || cursor_wm)) {
1238 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1245 static bool g4x_compute_srwm(struct drm_device *dev,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor,
1250 int *display_wm, int *cursor_wm)
1252 struct drm_crtc *crtc;
1253 int hdisplay, htotal, pixel_size, clock;
1254 unsigned long line_time_us;
1255 int line_count, line_size;
1260 *display_wm = *cursor_wm = 0;
1264 crtc = intel_get_crtc_for_plane(dev, plane);
1265 hdisplay = crtc->mode.hdisplay;
1266 htotal = crtc->mode.htotal;
1267 clock = crtc->mode.clock;
1268 pixel_size = crtc->fb->bits_per_pixel / 8;
1270 line_time_us = (htotal * 1000) / clock;
1271 line_count = (latency_ns / line_time_us + 1000) / 1000;
1272 line_size = hdisplay * pixel_size;
1274 /* Use the minimum of the small and large buffer method for primary */
1275 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276 large = line_count * line_size;
1278 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279 *display_wm = entries + display->guard_size;
1281 /* calculate the self-refresh watermark for display cursor */
1282 entries = line_count * pixel_size * 64;
1283 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284 *cursor_wm = entries + cursor->guard_size;
1286 return g4x_check_srwm(dev,
1287 *display_wm, *cursor_wm,
1291 static bool vlv_compute_drain_latency(struct drm_device *dev,
1293 int *plane_prec_mult,
1295 int *cursor_prec_mult,
1298 struct drm_crtc *crtc;
1299 int clock, pixel_size;
1302 crtc = intel_get_crtc_for_plane(dev, plane);
1303 if (!intel_crtc_active(crtc))
1306 clock = crtc->mode.clock; /* VESA DOT Clock */
1307 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1309 entries = (clock / 1000) * pixel_size;
1310 *plane_prec_mult = (entries > 256) ?
1311 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1315 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1316 *cursor_prec_mult = (entries > 256) ?
1317 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1324 * Update drain latency registers of memory arbiter
1326 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327 * to be programmed. Each plane has a drain latency multiplier and a drain
1331 static void vlv_update_drain_latency(struct drm_device *dev)
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1339 /* For plane A, Cursor A */
1340 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341 &cursor_prec_mult, &cursora_dl)) {
1342 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1347 I915_WRITE(VLV_DDL1, cursora_prec |
1348 (cursora_dl << DDL_CURSORA_SHIFT) |
1349 planea_prec | planea_dl);
1352 /* For plane B, Cursor B */
1353 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354 &cursor_prec_mult, &cursorb_dl)) {
1355 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1360 I915_WRITE(VLV_DDL2, cursorb_prec |
1361 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362 planeb_prec | planeb_dl);
1366 #define single_plane_enabled(mask) is_power_of_2(mask)
1368 static void valleyview_update_wm(struct drm_device *dev)
1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
1374 int ignore_plane_sr, ignore_cursor_sr;
1375 unsigned int enabled = 0;
1377 vlv_update_drain_latency(dev);
1379 if (g4x_compute_wm0(dev, PIPE_A,
1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
1383 enabled |= 1 << PIPE_A;
1385 if (g4x_compute_wm0(dev, PIPE_B,
1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
1389 enabled |= 1 << PIPE_B;
1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
1401 &ignore_plane_sr, &cursor_sr)) {
1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1406 plane_sr = cursor_sr = 0;
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1427 static void g4x_update_wm(struct drm_device *dev)
1429 static const int sr_latency_ns = 12000;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432 int plane_sr, cursor_sr;
1433 unsigned int enabled = 0;
1435 if (g4x_compute_wm0(dev, PIPE_A,
1436 &g4x_wm_info, latency_ns,
1437 &g4x_cursor_wm_info, latency_ns,
1438 &planea_wm, &cursora_wm))
1439 enabled |= 1 << PIPE_A;
1441 if (g4x_compute_wm0(dev, PIPE_B,
1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planeb_wm, &cursorb_wm))
1445 enabled |= 1 << PIPE_B;
1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1451 &g4x_cursor_wm_info,
1452 &plane_sr, &cursor_sr)) {
1453 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1455 I915_WRITE(FW_BLC_SELF,
1456 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1457 plane_sr = cursor_sr = 0;
1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461 planea_wm, cursora_wm,
1462 planeb_wm, cursorb_wm,
1463 plane_sr, cursor_sr);
1466 (plane_sr << DSPFW_SR_SHIFT) |
1467 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1471 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1472 (cursora_wm << DSPFW_CURSORA_SHIFT));
1473 /* HPLL off in SR has some issues on G4x... disable it */
1475 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1476 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1479 static void i965_update_wm(struct drm_device *dev)
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct drm_crtc *crtc;
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
1491 int clock = crtc->mode.clock;
1492 int htotal = crtc->mode.htotal;
1493 int hdisplay = crtc->mode.hdisplay;
1494 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495 unsigned long line_time_us;
1498 line_time_us = ((htotal * 1000) / clock);
1500 /* Use ns/us then divide to preserve precision */
1501 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502 pixel_size * hdisplay;
1503 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504 srwm = I965_FIFO_SIZE - entries;
1508 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1513 entries = DIV_ROUND_UP(entries,
1514 i965_cursor_wm_info.cacheline_size);
1515 cursor_sr = i965_cursor_wm_info.fifo_size -
1516 (entries + i965_cursor_wm_info.guard_size);
1518 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519 cursor_sr = i965_cursor_wm_info.max_wm;
1521 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522 "cursor %d\n", srwm, cursor_sr);
1524 if (IS_CRESTLINE(dev))
1525 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1527 /* Turn off self refresh if both pipes are enabled */
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1536 /* 965 has limitations... */
1537 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538 (8 << 16) | (8 << 8) | (8 << 0));
1539 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540 /* update cursor SR watermark */
1541 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1544 static void i9xx_update_wm(struct drm_device *dev)
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 const struct intel_watermark_params *wm_info;
1552 int planea_wm, planeb_wm;
1553 struct drm_crtc *crtc, *enabled = NULL;
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev))
1558 wm_info = &i915_wm_info;
1560 wm_info = &i855_wm_info;
1562 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563 crtc = intel_get_crtc_for_plane(dev, 0);
1564 if (intel_crtc_active(crtc)) {
1565 int cpp = crtc->fb->bits_per_pixel / 8;
1569 planea_wm = intel_calculate_wm(crtc->mode.clock,
1570 wm_info, fifo_size, cpp,
1574 planea_wm = fifo_size - wm_info->guard_size;
1576 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577 crtc = intel_get_crtc_for_plane(dev, 1);
1578 if (intel_crtc_active(crtc)) {
1579 int cpp = crtc->fb->bits_per_pixel / 8;
1583 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1584 wm_info, fifo_size, cpp,
1586 if (enabled == NULL)
1591 planeb_wm = fifo_size - wm_info->guard_size;
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1596 * Overlay gets an aggressive default since video jitter is bad.
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
1601 if (IS_I945G(dev) || IS_I945GM(dev))
1602 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603 else if (IS_I915GM(dev))
1604 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 int clock = enabled->mode.clock;
1611 int htotal = enabled->mode.htotal;
1612 int hdisplay = enabled->mode.hdisplay;
1613 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614 unsigned long line_time_us;
1617 line_time_us = (htotal * 1000) / clock;
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621 pixel_size * hdisplay;
1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1628 if (IS_I945G(dev) || IS_I945GM(dev))
1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631 else if (IS_I915GM(dev))
1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1648 if (HAS_FW_BLC(dev)) {
1650 if (IS_I945G(dev) || IS_I945GM(dev))
1651 I915_WRITE(FW_BLC_SELF,
1652 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653 else if (IS_I915GM(dev))
1654 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655 DRM_DEBUG_KMS("memory self refresh enabled\n");
1657 DRM_DEBUG_KMS("memory self refresh disabled\n");
1661 static void i830_update_wm(struct drm_device *dev)
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
1668 crtc = single_enabled_crtc(dev);
1672 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673 dev_priv->display.get_fifo_size(dev, 0),
1675 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676 fwater_lo |= (3<<8) | planea_wm;
1678 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1680 I915_WRITE(FW_BLC, fwater_lo);
1684 * Check the wm result.
1686 * If any calculated watermark values is larger than the maximum value that
1687 * can be programmed into the associated watermark register, that watermark
1690 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1691 int fbc_wm, int display_wm, int cursor_wm,
1692 const struct intel_watermark_params *display,
1693 const struct intel_watermark_params *cursor)
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1697 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1698 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1700 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1701 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1702 fbc_wm, SNB_FBC_MAX_SRWM, level);
1704 /* fbc has it's own way to disable FBC WM */
1705 I915_WRITE(DISP_ARB_CTL,
1706 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1708 } else if (INTEL_INFO(dev)->gen >= 6) {
1709 /* enable FBC WM (except on ILK, where it must remain off) */
1710 I915_WRITE(DISP_ARB_CTL,
1711 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1714 if (display_wm > display->max_wm) {
1715 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1716 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1720 if (cursor_wm > cursor->max_wm) {
1721 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1722 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1726 if (!(fbc_wm || display_wm || cursor_wm)) {
1727 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1735 * Compute watermark values of WM[1-3],
1737 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1739 const struct intel_watermark_params *display,
1740 const struct intel_watermark_params *cursor,
1741 int *fbc_wm, int *display_wm, int *cursor_wm)
1743 struct drm_crtc *crtc;
1744 unsigned long line_time_us;
1745 int hdisplay, htotal, pixel_size, clock;
1746 int line_count, line_size;
1751 *fbc_wm = *display_wm = *cursor_wm = 0;
1755 crtc = intel_get_crtc_for_plane(dev, plane);
1756 hdisplay = crtc->mode.hdisplay;
1757 htotal = crtc->mode.htotal;
1758 clock = crtc->mode.clock;
1759 pixel_size = crtc->fb->bits_per_pixel / 8;
1761 line_time_us = (htotal * 1000) / clock;
1762 line_count = (latency_ns / line_time_us + 1000) / 1000;
1763 line_size = hdisplay * pixel_size;
1765 /* Use the minimum of the small and large buffer method for primary */
1766 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1767 large = line_count * line_size;
1769 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1770 *display_wm = entries + display->guard_size;
1774 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1776 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1778 /* calculate the self-refresh watermark for display cursor */
1779 entries = line_count * pixel_size * 64;
1780 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1781 *cursor_wm = entries + cursor->guard_size;
1783 return ironlake_check_srwm(dev, level,
1784 *fbc_wm, *display_wm, *cursor_wm,
1788 static void ironlake_update_wm(struct drm_device *dev)
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int fbc_wm, plane_wm, cursor_wm;
1792 unsigned int enabled;
1795 if (g4x_compute_wm0(dev, PIPE_A,
1796 &ironlake_display_wm_info,
1797 dev_priv->wm.pri_latency[0] * 100,
1798 &ironlake_cursor_wm_info,
1799 dev_priv->wm.cur_latency[0] * 100,
1800 &plane_wm, &cursor_wm)) {
1801 I915_WRITE(WM0_PIPEA_ILK,
1802 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1803 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1804 " plane %d, " "cursor: %d\n",
1805 plane_wm, cursor_wm);
1806 enabled |= 1 << PIPE_A;
1809 if (g4x_compute_wm0(dev, PIPE_B,
1810 &ironlake_display_wm_info,
1811 dev_priv->wm.pri_latency[0] * 100,
1812 &ironlake_cursor_wm_info,
1813 dev_priv->wm.cur_latency[0] * 100,
1814 &plane_wm, &cursor_wm)) {
1815 I915_WRITE(WM0_PIPEB_ILK,
1816 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
1820 enabled |= 1 << PIPE_B;
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1827 I915_WRITE(WM3_LP_ILK, 0);
1828 I915_WRITE(WM2_LP_ILK, 0);
1829 I915_WRITE(WM1_LP_ILK, 0);
1831 if (!single_plane_enabled(enabled))
1833 enabled = ffs(enabled) - 1;
1836 if (!ironlake_compute_srwm(dev, 1, enabled,
1837 dev_priv->wm.pri_latency[1] * 500,
1838 &ironlake_display_srwm_info,
1839 &ironlake_cursor_srwm_info,
1840 &fbc_wm, &plane_wm, &cursor_wm))
1843 I915_WRITE(WM1_LP_ILK,
1845 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1846 (fbc_wm << WM1_LP_FBC_SHIFT) |
1847 (plane_wm << WM1_LP_SR_SHIFT) |
1851 if (!ironlake_compute_srwm(dev, 2, enabled,
1852 dev_priv->wm.pri_latency[2] * 500,
1853 &ironlake_display_srwm_info,
1854 &ironlake_cursor_srwm_info,
1855 &fbc_wm, &plane_wm, &cursor_wm))
1858 I915_WRITE(WM2_LP_ILK,
1860 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1861 (fbc_wm << WM1_LP_FBC_SHIFT) |
1862 (plane_wm << WM1_LP_SR_SHIFT) |
1866 * WM3 is unsupported on ILK, probably because we don't have latency
1867 * data for that power state
1871 static void sandybridge_update_wm(struct drm_device *dev)
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1876 int fbc_wm, plane_wm, cursor_wm;
1877 unsigned int enabled;
1880 if (g4x_compute_wm0(dev, PIPE_A,
1881 &sandybridge_display_wm_info, latency,
1882 &sandybridge_cursor_wm_info, latency,
1883 &plane_wm, &cursor_wm)) {
1884 val = I915_READ(WM0_PIPEA_ILK);
1885 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1886 I915_WRITE(WM0_PIPEA_ILK, val |
1887 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1888 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1889 " plane %d, " "cursor: %d\n",
1890 plane_wm, cursor_wm);
1891 enabled |= 1 << PIPE_A;
1894 if (g4x_compute_wm0(dev, PIPE_B,
1895 &sandybridge_display_wm_info, latency,
1896 &sandybridge_cursor_wm_info, latency,
1897 &plane_wm, &cursor_wm)) {
1898 val = I915_READ(WM0_PIPEB_ILK);
1899 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1900 I915_WRITE(WM0_PIPEB_ILK, val |
1901 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1902 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1903 " plane %d, cursor: %d\n",
1904 plane_wm, cursor_wm);
1905 enabled |= 1 << PIPE_B;
1909 * Calculate and update the self-refresh watermark only when one
1910 * display plane is used.
1912 * SNB support 3 levels of watermark.
1914 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1915 * and disabled in the descending order
1918 I915_WRITE(WM3_LP_ILK, 0);
1919 I915_WRITE(WM2_LP_ILK, 0);
1920 I915_WRITE(WM1_LP_ILK, 0);
1922 if (!single_plane_enabled(enabled) ||
1923 dev_priv->sprite_scaling_enabled)
1925 enabled = ffs(enabled) - 1;
1928 if (!ironlake_compute_srwm(dev, 1, enabled,
1929 dev_priv->wm.pri_latency[1] * 500,
1930 &sandybridge_display_srwm_info,
1931 &sandybridge_cursor_srwm_info,
1932 &fbc_wm, &plane_wm, &cursor_wm))
1935 I915_WRITE(WM1_LP_ILK,
1937 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1938 (fbc_wm << WM1_LP_FBC_SHIFT) |
1939 (plane_wm << WM1_LP_SR_SHIFT) |
1943 if (!ironlake_compute_srwm(dev, 2, enabled,
1944 dev_priv->wm.pri_latency[2] * 500,
1945 &sandybridge_display_srwm_info,
1946 &sandybridge_cursor_srwm_info,
1947 &fbc_wm, &plane_wm, &cursor_wm))
1950 I915_WRITE(WM2_LP_ILK,
1952 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1953 (fbc_wm << WM1_LP_FBC_SHIFT) |
1954 (plane_wm << WM1_LP_SR_SHIFT) |
1958 if (!ironlake_compute_srwm(dev, 3, enabled,
1959 dev_priv->wm.pri_latency[3] * 500,
1960 &sandybridge_display_srwm_info,
1961 &sandybridge_cursor_srwm_info,
1962 &fbc_wm, &plane_wm, &cursor_wm))
1965 I915_WRITE(WM3_LP_ILK,
1967 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1968 (fbc_wm << WM1_LP_FBC_SHIFT) |
1969 (plane_wm << WM1_LP_SR_SHIFT) |
1973 static void ivybridge_update_wm(struct drm_device *dev)
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
1978 int fbc_wm, plane_wm, cursor_wm;
1979 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1980 unsigned int enabled;
1983 if (g4x_compute_wm0(dev, PIPE_A,
1984 &sandybridge_display_wm_info, latency,
1985 &sandybridge_cursor_wm_info, latency,
1986 &plane_wm, &cursor_wm)) {
1987 val = I915_READ(WM0_PIPEA_ILK);
1988 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1989 I915_WRITE(WM0_PIPEA_ILK, val |
1990 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1991 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1992 " plane %d, " "cursor: %d\n",
1993 plane_wm, cursor_wm);
1994 enabled |= 1 << PIPE_A;
1997 if (g4x_compute_wm0(dev, PIPE_B,
1998 &sandybridge_display_wm_info, latency,
1999 &sandybridge_cursor_wm_info, latency,
2000 &plane_wm, &cursor_wm)) {
2001 val = I915_READ(WM0_PIPEB_ILK);
2002 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003 I915_WRITE(WM0_PIPEB_ILK, val |
2004 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2006 " plane %d, cursor: %d\n",
2007 plane_wm, cursor_wm);
2008 enabled |= 1 << PIPE_B;
2011 if (g4x_compute_wm0(dev, PIPE_C,
2012 &sandybridge_display_wm_info, latency,
2013 &sandybridge_cursor_wm_info, latency,
2014 &plane_wm, &cursor_wm)) {
2015 val = I915_READ(WM0_PIPEC_IVB);
2016 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2017 I915_WRITE(WM0_PIPEC_IVB, val |
2018 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2019 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2020 " plane %d, cursor: %d\n",
2021 plane_wm, cursor_wm);
2022 enabled |= 1 << PIPE_C;
2026 * Calculate and update the self-refresh watermark only when one
2027 * display plane is used.
2029 * SNB support 3 levels of watermark.
2031 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2032 * and disabled in the descending order
2035 I915_WRITE(WM3_LP_ILK, 0);
2036 I915_WRITE(WM2_LP_ILK, 0);
2037 I915_WRITE(WM1_LP_ILK, 0);
2039 if (!single_plane_enabled(enabled) ||
2040 dev_priv->sprite_scaling_enabled)
2042 enabled = ffs(enabled) - 1;
2045 if (!ironlake_compute_srwm(dev, 1, enabled,
2046 dev_priv->wm.pri_latency[1] * 500,
2047 &sandybridge_display_srwm_info,
2048 &sandybridge_cursor_srwm_info,
2049 &fbc_wm, &plane_wm, &cursor_wm))
2052 I915_WRITE(WM1_LP_ILK,
2054 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2055 (fbc_wm << WM1_LP_FBC_SHIFT) |
2056 (plane_wm << WM1_LP_SR_SHIFT) |
2060 if (!ironlake_compute_srwm(dev, 2, enabled,
2061 dev_priv->wm.pri_latency[2] * 500,
2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &fbc_wm, &plane_wm, &cursor_wm))
2067 I915_WRITE(WM2_LP_ILK,
2069 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2074 /* WM3, note we have to correct the cursor latency */
2075 if (!ironlake_compute_srwm(dev, 3, enabled,
2076 dev_priv->wm.pri_latency[3] * 500,
2077 &sandybridge_display_srwm_info,
2078 &sandybridge_cursor_srwm_info,
2079 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2080 !ironlake_compute_srwm(dev, 3, enabled,
2081 dev_priv->wm.cur_latency[3] * 500,
2082 &sandybridge_display_srwm_info,
2083 &sandybridge_cursor_srwm_info,
2084 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2087 I915_WRITE(WM3_LP_ILK,
2089 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2090 (fbc_wm << WM1_LP_FBC_SHIFT) |
2091 (plane_wm << WM1_LP_SR_SHIFT) |
2095 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2096 struct drm_crtc *crtc)
2098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099 uint32_t pixel_rate, pfit_size;
2101 pixel_rate = intel_crtc->config.adjusted_mode.clock;
2103 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2104 * adjust the pixel_rate here. */
2106 pfit_size = intel_crtc->config.pch_pfit.size;
2108 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2110 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2111 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2112 pfit_w = (pfit_size >> 16) & 0xFFFF;
2113 pfit_h = pfit_size & 0xFFFF;
2114 if (pipe_w < pfit_w)
2116 if (pipe_h < pfit_h)
2119 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2126 /* latency must be in 0.1us units. */
2127 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2132 if (WARN(latency == 0, "Latency value missing\n"))
2135 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2136 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2141 /* latency must be in 0.1us units. */
2142 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2143 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2148 if (WARN(latency == 0, "Latency value missing\n"))
2151 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2152 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2153 ret = DIV_ROUND_UP(ret, 64) + 2;
2157 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2158 uint8_t bytes_per_pixel)
2160 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2163 struct hsw_pipe_wm_parameters {
2165 bool sprite_enabled;
2166 uint8_t pri_bytes_per_pixel;
2167 uint8_t spr_bytes_per_pixel;
2168 uint8_t cur_bytes_per_pixel;
2169 uint32_t pri_horiz_pixels;
2170 uint32_t spr_horiz_pixels;
2171 uint32_t cur_horiz_pixels;
2172 uint32_t pipe_htotal;
2173 uint32_t pixel_rate;
2176 struct hsw_wm_maximums {
2183 struct hsw_wm_values {
2184 uint32_t wm_pipe[3];
2186 uint32_t wm_lp_spr[3];
2187 uint32_t wm_linetime[3];
2192 * For both WM_PIPE and WM_LP.
2193 * mem_value must be in 0.1us units.
2195 static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2199 uint32_t method1, method2;
2201 /* TODO: for now, assume the primary plane is always enabled. */
2202 if (!params->active)
2205 method1 = ilk_wm_method1(params->pixel_rate,
2206 params->pri_bytes_per_pixel,
2212 method2 = ilk_wm_method2(params->pixel_rate,
2213 params->pipe_htotal,
2214 params->pri_horiz_pixels,
2215 params->pri_bytes_per_pixel,
2218 return min(method1, method2);
2222 * For both WM_PIPE and WM_LP.
2223 * mem_value must be in 0.1us units.
2225 static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2228 uint32_t method1, method2;
2230 if (!params->active || !params->sprite_enabled)
2233 method1 = ilk_wm_method1(params->pixel_rate,
2234 params->spr_bytes_per_pixel,
2236 method2 = ilk_wm_method2(params->pixel_rate,
2237 params->pipe_htotal,
2238 params->spr_horiz_pixels,
2239 params->spr_bytes_per_pixel,
2241 return min(method1, method2);
2245 * For both WM_PIPE and WM_LP.
2246 * mem_value must be in 0.1us units.
2248 static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2251 if (!params->active)
2254 return ilk_wm_method2(params->pixel_rate,
2255 params->pipe_htotal,
2256 params->cur_horiz_pixels,
2257 params->cur_bytes_per_pixel,
2261 /* Only for WM_LP. */
2262 static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2265 if (!params->active)
2268 return ilk_wm_fbc(pri_val,
2269 params->pri_horiz_pixels,
2270 params->pri_bytes_per_pixel);
2273 static bool ilk_check_wm(int level,
2274 const struct hsw_wm_maximums *max,
2275 struct intel_wm_level *result)
2279 /* already determined to be invalid? */
2280 if (!result->enable)
2283 result->enable = result->pri_val <= max->pri &&
2284 result->spr_val <= max->spr &&
2285 result->cur_val <= max->cur;
2287 ret = result->enable;
2290 * HACK until we can pre-compute everything,
2291 * and thus fail gracefully if LP0 watermarks
2294 if (level == 0 && !result->enable) {
2295 if (result->pri_val > max->pri)
2296 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2297 level, result->pri_val, max->pri);
2298 if (result->spr_val > max->spr)
2299 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2300 level, result->spr_val, max->spr);
2301 if (result->cur_val > max->cur)
2302 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2303 level, result->cur_val, max->cur);
2305 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2306 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2307 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2308 result->enable = true;
2311 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2316 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2318 struct hsw_pipe_wm_parameters *p,
2319 struct intel_wm_level *result)
2321 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2322 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2323 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2325 /* WM1+ latency values stored in 0.5us units */
2332 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2333 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2334 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2335 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2336 result->enable = true;
2339 static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
2340 int level, struct hsw_wm_maximums *max,
2341 struct hsw_pipe_wm_parameters *params,
2342 struct intel_wm_level *result)
2345 struct intel_wm_level res[3];
2347 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2348 ilk_compute_wm_level(dev_priv, level, ¶ms[pipe], &res[pipe]);
2350 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2351 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2352 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2353 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2354 result->enable = true;
2356 return ilk_check_wm(level, max, result);
2359 static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2361 struct hsw_pipe_wm_parameters *params)
2363 uint32_t pri_val, cur_val, spr_val;
2364 /* WM0 latency values stored in 0.1us units */
2365 uint16_t pri_latency = dev_priv->wm.pri_latency[0];
2366 uint16_t spr_latency = dev_priv->wm.spr_latency[0];
2367 uint16_t cur_latency = dev_priv->wm.cur_latency[0];
2369 pri_val = ilk_compute_pri_wm(params, pri_latency, false);
2370 spr_val = ilk_compute_spr_wm(params, spr_latency);
2371 cur_val = ilk_compute_cur_wm(params, cur_latency);
2374 "Primary WM error, mode not supported for pipe %c\n",
2377 "Sprite WM error, mode not supported for pipe %c\n",
2380 "Cursor WM error, mode not supported for pipe %c\n",
2383 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2384 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2389 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2394 u32 linetime, ips_linetime;
2396 if (!intel_crtc_active(crtc))
2399 /* The WM are computed with base on how long it takes to fill a single
2400 * row at the given clock rate, multiplied by 8.
2402 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2403 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2404 intel_ddi_get_cdclk_freq(dev_priv));
2406 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2407 PIPE_WM_LINETIME_TIME(linetime);
2410 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2414 if (IS_HASWELL(dev)) {
2415 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2417 wm[0] = (sskpd >> 56) & 0xFF;
2419 wm[0] = sskpd & 0xF;
2420 wm[1] = (sskpd >> 4) & 0xFF;
2421 wm[2] = (sskpd >> 12) & 0xFF;
2422 wm[3] = (sskpd >> 20) & 0x1FF;
2423 wm[4] = (sskpd >> 32) & 0x1FF;
2424 } else if (INTEL_INFO(dev)->gen >= 6) {
2425 uint32_t sskpd = I915_READ(MCH_SSKPD);
2427 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2428 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2429 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2430 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2431 } else if (INTEL_INFO(dev)->gen >= 5) {
2432 uint32_t mltr = I915_READ(MLTR_ILK);
2434 /* ILK primary LP0 latency is 700 ns */
2436 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2437 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2441 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2443 /* ILK sprite LP0 latency is 1300 ns */
2444 if (INTEL_INFO(dev)->gen == 5)
2448 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2450 /* ILK cursor LP0 latency is 1300 ns */
2451 if (INTEL_INFO(dev)->gen == 5)
2454 /* WaDoubleCursorLP3Latency:ivb */
2455 if (IS_IVYBRIDGE(dev))
2459 static void intel_print_wm_latency(struct drm_device *dev,
2461 const uint16_t wm[5])
2463 int level, max_level;
2465 /* how many WM levels are we expecting */
2466 if (IS_HASWELL(dev))
2468 else if (INTEL_INFO(dev)->gen >= 6)
2473 for (level = 0; level <= max_level; level++) {
2474 unsigned int latency = wm[level];
2477 DRM_ERROR("%s WM%d latency not provided\n",
2482 /* WM1+ latency values in 0.5us units */
2486 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2487 name, level, wm[level],
2488 latency / 10, latency % 10);
2492 static void intel_setup_wm_latency(struct drm_device *dev)
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2496 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2498 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2499 sizeof(dev_priv->wm.pri_latency));
2500 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2501 sizeof(dev_priv->wm.pri_latency));
2503 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2504 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2506 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2507 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2508 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2511 static void hsw_compute_wm_parameters(struct drm_device *dev,
2512 struct hsw_pipe_wm_parameters *params,
2513 struct hsw_wm_maximums *lp_max_1_2,
2514 struct hsw_wm_maximums *lp_max_5_6)
2516 struct drm_crtc *crtc;
2517 struct drm_plane *plane;
2519 int pipes_active = 0, sprites_enabled = 0;
2521 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2523 struct hsw_pipe_wm_parameters *p;
2525 pipe = intel_crtc->pipe;
2528 p->active = intel_crtc_active(crtc);
2534 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2535 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2536 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2537 p->cur_bytes_per_pixel = 4;
2538 p->pri_horiz_pixels =
2539 intel_crtc->config.requested_mode.hdisplay;
2540 p->cur_horiz_pixels = 64;
2543 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2544 struct intel_plane *intel_plane = to_intel_plane(plane);
2545 struct hsw_pipe_wm_parameters *p;
2547 pipe = intel_plane->pipe;
2550 p->sprite_enabled = intel_plane->wm.enabled;
2551 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2552 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
2554 if (p->sprite_enabled)
2558 if (pipes_active > 1) {
2559 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2560 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2561 lp_max_1_2->cur = lp_max_5_6->cur = 64;
2563 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
2564 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
2565 lp_max_1_2->spr = 384;
2566 lp_max_5_6->spr = 640;
2567 lp_max_1_2->cur = lp_max_5_6->cur = 255;
2569 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
2572 static void hsw_compute_wm_results(struct drm_device *dev,
2573 struct hsw_pipe_wm_parameters *params,
2574 struct hsw_wm_maximums *lp_maximums,
2575 struct hsw_wm_values *results)
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct drm_crtc *crtc;
2579 struct intel_wm_level lp_results[4] = {};
2581 int level, max_level, wm_lp;
2583 for (level = 1; level <= 4; level++)
2584 if (!hsw_compute_lp_wm(dev_priv, level,
2585 lp_maximums, params,
2586 &lp_results[level - 1]))
2588 max_level = level - 1;
2590 /* The spec says it is preferred to disable FBC WMs instead of disabling
2592 results->enable_fbc_wm = true;
2593 for (level = 1; level <= max_level; level++) {
2594 if (!lp_results[level - 1].fbc_val > lp_maximums->fbc) {
2595 results->enable_fbc_wm = false;
2596 lp_results[level - 1].fbc_val = 0;
2600 memset(results, 0, sizeof(*results));
2601 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2602 const struct intel_wm_level *r;
2604 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2605 if (level > max_level)
2608 r = &lp_results[level - 1];
2609 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2613 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2617 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
2620 for_each_pipe(pipe) {
2621 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2622 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2626 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2627 * case both are at the same level. Prefer r1 in case they're the same. */
2628 static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2629 struct hsw_wm_values *r2)
2631 int i, val_r1 = 0, val_r2 = 0;
2633 for (i = 0; i < 3; i++) {
2634 if (r1->wm_lp[i] & WM3_LP_EN)
2635 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2636 if (r2->wm_lp[i] & WM3_LP_EN)
2637 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2640 if (val_r1 == val_r2) {
2641 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2645 } else if (val_r1 > val_r2) {
2653 * The spec says we shouldn't write when we don't need, because every write
2654 * causes WMs to be re-evaluated, expending some power.
2656 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2657 struct hsw_wm_values *results,
2658 enum intel_ddb_partitioning partitioning)
2660 struct hsw_wm_values previous;
2662 enum intel_ddb_partitioning prev_partitioning;
2663 bool prev_enable_fbc_wm;
2665 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2666 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2667 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2668 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2669 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2670 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2671 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2672 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2673 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2674 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2675 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2676 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2678 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2679 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2681 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2683 if (memcmp(results->wm_pipe, previous.wm_pipe,
2684 sizeof(results->wm_pipe)) == 0 &&
2685 memcmp(results->wm_lp, previous.wm_lp,
2686 sizeof(results->wm_lp)) == 0 &&
2687 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2688 sizeof(results->wm_lp_spr)) == 0 &&
2689 memcmp(results->wm_linetime, previous.wm_linetime,
2690 sizeof(results->wm_linetime)) == 0 &&
2691 partitioning == prev_partitioning &&
2692 results->enable_fbc_wm == prev_enable_fbc_wm)
2695 if (previous.wm_lp[2] != 0)
2696 I915_WRITE(WM3_LP_ILK, 0);
2697 if (previous.wm_lp[1] != 0)
2698 I915_WRITE(WM2_LP_ILK, 0);
2699 if (previous.wm_lp[0] != 0)
2700 I915_WRITE(WM1_LP_ILK, 0);
2702 if (previous.wm_pipe[0] != results->wm_pipe[0])
2703 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2704 if (previous.wm_pipe[1] != results->wm_pipe[1])
2705 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2706 if (previous.wm_pipe[2] != results->wm_pipe[2])
2707 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2709 if (previous.wm_linetime[0] != results->wm_linetime[0])
2710 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2711 if (previous.wm_linetime[1] != results->wm_linetime[1])
2712 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2713 if (previous.wm_linetime[2] != results->wm_linetime[2])
2714 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2716 if (prev_partitioning != partitioning) {
2717 val = I915_READ(WM_MISC);
2718 if (partitioning == INTEL_DDB_PART_1_2)
2719 val &= ~WM_MISC_DATA_PARTITION_5_6;
2721 val |= WM_MISC_DATA_PARTITION_5_6;
2722 I915_WRITE(WM_MISC, val);
2725 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2726 val = I915_READ(DISP_ARB_CTL);
2727 if (results->enable_fbc_wm)
2728 val &= ~DISP_FBC_WM_DIS;
2730 val |= DISP_FBC_WM_DIS;
2731 I915_WRITE(DISP_ARB_CTL, val);
2734 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2735 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2736 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2737 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2738 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2739 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2741 if (results->wm_lp[0] != 0)
2742 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2743 if (results->wm_lp[1] != 0)
2744 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2745 if (results->wm_lp[2] != 0)
2746 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2749 static void haswell_update_wm(struct drm_device *dev)
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
2753 struct hsw_pipe_wm_parameters params[3];
2754 struct hsw_wm_values results_1_2, results_5_6, *best_results;
2755 enum intel_ddb_partitioning partitioning;
2757 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
2759 hsw_compute_wm_results(dev, params,
2760 &lp_max_1_2, &results_1_2);
2761 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2762 hsw_compute_wm_results(dev, params,
2763 &lp_max_5_6, &results_5_6);
2764 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2766 best_results = &results_1_2;
2769 partitioning = (best_results == &results_1_2) ?
2770 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2772 hsw_write_wm_values(dev_priv, best_results, partitioning);
2775 static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2776 uint32_t sprite_width, int pixel_size,
2777 bool enabled, bool scaled)
2779 struct drm_plane *plane;
2781 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2782 struct intel_plane *intel_plane = to_intel_plane(plane);
2784 if (intel_plane->pipe == pipe) {
2785 intel_plane->wm.enabled = enabled;
2786 intel_plane->wm.scaled = scaled;
2787 intel_plane->wm.horiz_pixels = sprite_width;
2788 intel_plane->wm.bytes_per_pixel = pixel_size;
2793 haswell_update_wm(dev);
2797 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2798 uint32_t sprite_width, int pixel_size,
2799 const struct intel_watermark_params *display,
2800 int display_latency_ns, int *sprite_wm)
2802 struct drm_crtc *crtc;
2804 int entries, tlb_miss;
2806 crtc = intel_get_crtc_for_plane(dev, plane);
2807 if (!intel_crtc_active(crtc)) {
2808 *sprite_wm = display->guard_size;
2812 clock = crtc->mode.clock;
2814 /* Use the small buffer method to calculate the sprite watermark */
2815 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2816 tlb_miss = display->fifo_size*display->cacheline_size -
2819 entries += tlb_miss;
2820 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2821 *sprite_wm = entries + display->guard_size;
2822 if (*sprite_wm > (int)display->max_wm)
2823 *sprite_wm = display->max_wm;
2829 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2830 uint32_t sprite_width, int pixel_size,
2831 const struct intel_watermark_params *display,
2832 int latency_ns, int *sprite_wm)
2834 struct drm_crtc *crtc;
2835 unsigned long line_time_us;
2837 int line_count, line_size;
2846 crtc = intel_get_crtc_for_plane(dev, plane);
2847 clock = crtc->mode.clock;
2853 line_time_us = (sprite_width * 1000) / clock;
2854 if (!line_time_us) {
2859 line_count = (latency_ns / line_time_us + 1000) / 1000;
2860 line_size = sprite_width * pixel_size;
2862 /* Use the minimum of the small and large buffer method for primary */
2863 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2864 large = line_count * line_size;
2866 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2867 *sprite_wm = entries + display->guard_size;
2869 return *sprite_wm > 0x3ff ? false : true;
2872 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2873 uint32_t sprite_width, int pixel_size,
2874 bool enabled, bool scaled)
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
2887 reg = WM0_PIPEA_ILK;
2890 reg = WM0_PIPEB_ILK;
2893 reg = WM0_PIPEC_IVB;
2896 return; /* bad pipe */
2899 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2900 &sandybridge_display_wm_info,
2901 latency, &sprite_wm);
2903 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2908 val = I915_READ(reg);
2909 val &= ~WM0_PIPE_SPRITE_MASK;
2910 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2911 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2914 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2916 &sandybridge_display_srwm_info,
2917 dev_priv->wm.spr_latency[1] * 500,
2920 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2924 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2926 /* Only IVB has two more LP watermarks for sprite */
2927 if (!IS_IVYBRIDGE(dev))
2930 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2932 &sandybridge_display_srwm_info,
2933 dev_priv->wm.spr_latency[2] * 500,
2936 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2940 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2942 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2944 &sandybridge_display_srwm_info,
2945 dev_priv->wm.spr_latency[3] * 500,
2948 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2952 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2956 * intel_update_watermarks - update FIFO watermark values based on current modes
2958 * Calculate watermark values for the various WM regs based on current mode
2959 * and plane configuration.
2961 * There are several cases to deal with here:
2962 * - normal (i.e. non-self-refresh)
2963 * - self-refresh (SR) mode
2964 * - lines are large relative to FIFO size (buffer can hold up to 2)
2965 * - lines are small relative to FIFO size (buffer can hold more than 2
2966 * lines), so need to account for TLB latency
2968 * The normal calculation is:
2969 * watermark = dotclock * bytes per pixel * latency
2970 * where latency is platform & configuration dependent (we assume pessimal
2973 * The SR calculation is:
2974 * watermark = (trunc(latency/line time)+1) * surface width *
2977 * line time = htotal / dotclock
2978 * surface width = hdisplay for normal plane and 64 for cursor
2979 * and latency is assumed to be high, as above.
2981 * The final value programmed to the register should always be rounded up,
2982 * and include an extra 2 entries to account for clock crossings.
2984 * We don't use the sprite, so we can ignore that. And on Crestline we have
2985 * to set the non-SR watermarks to 8.
2987 void intel_update_watermarks(struct drm_device *dev)
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2991 if (dev_priv->display.update_wm)
2992 dev_priv->display.update_wm(dev);
2995 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2996 uint32_t sprite_width, int pixel_size,
2997 bool enabled, bool scaled)
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3001 if (dev_priv->display.update_sprite_wm)
3002 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
3003 pixel_size, enabled, scaled);
3006 static struct drm_i915_gem_object *
3007 intel_alloc_context_page(struct drm_device *dev)
3009 struct drm_i915_gem_object *ctx;
3012 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3014 ctx = i915_gem_alloc_object(dev, 4096);
3016 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3020 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3022 DRM_ERROR("failed to pin power context: %d\n", ret);
3026 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3028 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3035 i915_gem_object_unpin(ctx);
3037 drm_gem_object_unreference(&ctx->base);
3042 * Lock protecting IPS related data structures
3044 DEFINE_SPINLOCK(mchdev_lock);
3046 /* Global for IPS driver to get at the current i915 device. Protected by
3048 static struct drm_i915_private *i915_mch_dev;
3050 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3055 assert_spin_locked(&mchdev_lock);
3057 rgvswctl = I915_READ16(MEMSWCTL);
3058 if (rgvswctl & MEMCTL_CMD_STS) {
3059 DRM_DEBUG("gpu busy, RCS change rejected\n");
3060 return false; /* still busy with another command */
3063 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3064 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3065 I915_WRITE16(MEMSWCTL, rgvswctl);
3066 POSTING_READ16(MEMSWCTL);
3068 rgvswctl |= MEMCTL_CMD_STS;
3069 I915_WRITE16(MEMSWCTL, rgvswctl);
3074 static void ironlake_enable_drps(struct drm_device *dev)
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 u32 rgvmodectl = I915_READ(MEMMODECTL);
3078 u8 fmax, fmin, fstart, vstart;
3080 spin_lock_irq(&mchdev_lock);
3082 /* Enable temp reporting */
3083 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3084 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3086 /* 100ms RC evaluation intervals */
3087 I915_WRITE(RCUPEI, 100000);
3088 I915_WRITE(RCDNEI, 100000);
3090 /* Set max/min thresholds to 90ms and 80ms respectively */
3091 I915_WRITE(RCBMAXAVG, 90000);
3092 I915_WRITE(RCBMINAVG, 80000);
3094 I915_WRITE(MEMIHYST, 1);
3096 /* Set up min, max, and cur for interrupt handling */
3097 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3098 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3099 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3100 MEMMODE_FSTART_SHIFT;
3102 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3105 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3106 dev_priv->ips.fstart = fstart;
3108 dev_priv->ips.max_delay = fstart;
3109 dev_priv->ips.min_delay = fmin;
3110 dev_priv->ips.cur_delay = fstart;
3112 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3113 fmax, fmin, fstart);
3115 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3118 * Interrupts will be enabled in ironlake_irq_postinstall
3121 I915_WRITE(VIDSTART, vstart);
3122 POSTING_READ(VIDSTART);
3124 rgvmodectl |= MEMMODE_SWMODE_EN;
3125 I915_WRITE(MEMMODECTL, rgvmodectl);
3127 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3128 DRM_ERROR("stuck trying to change perf mode\n");
3131 ironlake_set_drps(dev, fstart);
3133 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3135 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3136 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3137 getrawmonotonic(&dev_priv->ips.last_time2);
3139 spin_unlock_irq(&mchdev_lock);
3142 static void ironlake_disable_drps(struct drm_device *dev)
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3147 spin_lock_irq(&mchdev_lock);
3149 rgvswctl = I915_READ16(MEMSWCTL);
3151 /* Ack interrupts, disable EFC interrupt */
3152 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3153 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3154 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3155 I915_WRITE(DEIIR, DE_PCU_EVENT);
3156 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3158 /* Go back to the starting frequency */
3159 ironlake_set_drps(dev, dev_priv->ips.fstart);
3161 rgvswctl |= MEMCTL_CMD_STS;
3162 I915_WRITE(MEMSWCTL, rgvswctl);
3165 spin_unlock_irq(&mchdev_lock);
3168 /* There's a funny hw issue where the hw returns all 0 when reading from
3169 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3170 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3171 * all limits and the gpu stuck at whatever frequency it is at atm).
3173 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3179 if (*val >= dev_priv->rps.max_delay)
3180 *val = dev_priv->rps.max_delay;
3181 limits |= dev_priv->rps.max_delay << 24;
3183 /* Only set the down limit when we've reached the lowest level to avoid
3184 * getting more interrupts, otherwise leave this clear. This prevents a
3185 * race in the hw when coming out of rc6: There's a tiny window where
3186 * the hw runs at the minimal clock before selecting the desired
3187 * frequency, if the down threshold expires in that window we will not
3188 * receive a down interrupt. */
3189 if (*val <= dev_priv->rps.min_delay) {
3190 *val = dev_priv->rps.min_delay;
3191 limits |= dev_priv->rps.min_delay << 16;
3197 void gen6_set_rps(struct drm_device *dev, u8 val)
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 u32 limits = gen6_rps_limits(dev_priv, &val);
3202 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3203 WARN_ON(val > dev_priv->rps.max_delay);
3204 WARN_ON(val < dev_priv->rps.min_delay);
3206 if (val == dev_priv->rps.cur_delay)
3209 if (IS_HASWELL(dev))
3210 I915_WRITE(GEN6_RPNSWREQ,
3211 HSW_FREQUENCY(val));
3213 I915_WRITE(GEN6_RPNSWREQ,
3214 GEN6_FREQUENCY(val) |
3216 GEN6_AGGRESSIVE_TURBO);
3218 /* Make sure we continue to get interrupts
3219 * until we hit the minimum or maximum frequencies.
3221 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3223 POSTING_READ(GEN6_RPNSWREQ);
3225 dev_priv->rps.cur_delay = val;
3227 trace_intel_gpu_freq_change(val * 50);
3231 * Wait until the previous freq change has completed,
3232 * or the timeout elapsed, and then update our notion
3233 * of the current GPU frequency.
3235 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3239 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3241 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3242 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3246 if (pval != dev_priv->rps.cur_delay)
3247 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3248 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3249 dev_priv->rps.cur_delay,
3250 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3252 dev_priv->rps.cur_delay = pval;
3255 void valleyview_set_rps(struct drm_device *dev, u8 val)
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3259 gen6_rps_limits(dev_priv, &val);
3261 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3262 WARN_ON(val > dev_priv->rps.max_delay);
3263 WARN_ON(val < dev_priv->rps.min_delay);
3265 vlv_update_rps_cur_delay(dev_priv);
3267 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3268 vlv_gpu_freq(dev_priv->mem_freq,
3269 dev_priv->rps.cur_delay),
3270 dev_priv->rps.cur_delay,
3271 vlv_gpu_freq(dev_priv->mem_freq, val), val);
3273 if (val == dev_priv->rps.cur_delay)
3276 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3278 dev_priv->rps.cur_delay = val;
3280 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3283 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3287 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3288 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3289 /* Complete PM interrupt masking here doesn't race with the rps work
3290 * item again unmasking PM interrupts because that is using a different
3291 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3292 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3294 spin_lock_irq(&dev_priv->irq_lock);
3295 dev_priv->rps.pm_iir = 0;
3296 spin_unlock_irq(&dev_priv->irq_lock);
3298 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3301 static void gen6_disable_rps(struct drm_device *dev)
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3305 I915_WRITE(GEN6_RC_CONTROL, 0);
3306 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3308 gen6_disable_rps_interrupts(dev);
3311 static void valleyview_disable_rps(struct drm_device *dev)
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3315 I915_WRITE(GEN6_RC_CONTROL, 0);
3317 gen6_disable_rps_interrupts(dev);
3319 if (dev_priv->vlv_pctx) {
3320 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3321 dev_priv->vlv_pctx = NULL;
3325 int intel_enable_rc6(const struct drm_device *dev)
3327 /* No RC6 before Ironlake */
3328 if (INTEL_INFO(dev)->gen < 5)
3331 /* Respect the kernel parameter if it is set */
3332 if (i915_enable_rc6 >= 0)
3333 return i915_enable_rc6;
3335 /* Disable RC6 on Ironlake */
3336 if (INTEL_INFO(dev)->gen == 5)
3339 if (IS_HASWELL(dev)) {
3340 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3341 return INTEL_RC6_ENABLE;
3344 /* snb/ivb have more than one rc6 state. */
3345 if (INTEL_INFO(dev)->gen == 6) {
3346 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3347 return INTEL_RC6_ENABLE;
3350 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3351 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3354 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3358 spin_lock_irq(&dev_priv->irq_lock);
3359 WARN_ON(dev_priv->rps.pm_iir);
3360 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3361 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3362 spin_unlock_irq(&dev_priv->irq_lock);
3363 /* unmask all PM interrupts */
3364 I915_WRITE(GEN6_PMINTRMSK, 0);
3367 static void gen6_enable_rps(struct drm_device *dev)
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 struct intel_ring_buffer *ring;
3373 u32 rc6vids, pcu_mbox, rc6_mask = 0;
3378 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3380 /* Here begins a magic sequence of register writes to enable
3381 * auto-downclocking.
3383 * Perhaps there might be some value in exposing these to
3386 I915_WRITE(GEN6_RC_STATE, 0);
3388 /* Clear the DBG now so we don't confuse earlier errors */
3389 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3390 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3391 I915_WRITE(GTFIFODBG, gtfifodbg);
3394 gen6_gt_force_wake_get(dev_priv);
3396 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3397 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3399 /* In units of 50MHz */
3400 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3401 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3402 dev_priv->rps.cur_delay = 0;
3404 /* disable the counters and set deterministic thresholds */
3405 I915_WRITE(GEN6_RC_CONTROL, 0);
3407 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3408 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3409 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3410 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3411 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3413 for_each_ring(ring, dev_priv, i)
3414 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3416 I915_WRITE(GEN6_RC_SLEEP, 0);
3417 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3418 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3419 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3420 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3422 /* Check if we are enabling RC6 */
3423 rc6_mode = intel_enable_rc6(dev_priv->dev);
3424 if (rc6_mode & INTEL_RC6_ENABLE)
3425 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3427 /* We don't use those on Haswell */
3428 if (!IS_HASWELL(dev)) {
3429 if (rc6_mode & INTEL_RC6p_ENABLE)
3430 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3432 if (rc6_mode & INTEL_RC6pp_ENABLE)
3433 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3436 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3437 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3438 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3439 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3441 I915_WRITE(GEN6_RC_CONTROL,
3443 GEN6_RC_CTL_EI_MODE(1) |
3444 GEN6_RC_CTL_HW_ENABLE);
3446 if (IS_HASWELL(dev)) {
3447 I915_WRITE(GEN6_RPNSWREQ,
3449 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3452 I915_WRITE(GEN6_RPNSWREQ,
3453 GEN6_FREQUENCY(10) |
3455 GEN6_AGGRESSIVE_TURBO);
3456 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3457 GEN6_FREQUENCY(12));
3460 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3461 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3462 dev_priv->rps.max_delay << 24 |
3463 dev_priv->rps.min_delay << 16);
3465 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3466 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3467 I915_WRITE(GEN6_RP_UP_EI, 66000);
3468 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3470 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3471 I915_WRITE(GEN6_RP_CONTROL,
3472 GEN6_RP_MEDIA_TURBO |
3473 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3474 GEN6_RP_MEDIA_IS_GFX |
3476 GEN6_RP_UP_BUSY_AVG |
3477 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
3479 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3482 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3483 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3484 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3485 (dev_priv->rps.max_delay & 0xff) * 50,
3486 (pcu_mbox & 0xff) * 50);
3487 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3490 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3493 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
3495 gen6_enable_rps_interrupts(dev);
3498 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3499 if (IS_GEN6(dev) && ret) {
3500 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3501 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3502 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3503 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3504 rc6vids &= 0xffff00;
3505 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3506 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3508 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3511 gen6_gt_force_wake_put(dev_priv);
3514 static void gen6_update_ring_freq(struct drm_device *dev)
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3518 unsigned int gpu_freq;
3519 unsigned int max_ia_freq, min_ring_freq;
3520 int scaling_factor = 180;
3522 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3524 max_ia_freq = cpufreq_quick_get_max(0);
3526 * Default to measured freq if none found, PCU will ensure we don't go
3530 max_ia_freq = tsc_khz;
3532 /* Convert from kHz to MHz */
3533 max_ia_freq /= 1000;
3535 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3536 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3537 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3540 * For each potential GPU frequency, load a ring frequency we'd like
3541 * to use for memory access. We do this by specifying the IA frequency
3542 * the PCU should use as a reference to determine the ring frequency.
3544 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3546 int diff = dev_priv->rps.max_delay - gpu_freq;
3547 unsigned int ia_freq = 0, ring_freq = 0;
3549 if (IS_HASWELL(dev)) {
3550 ring_freq = (gpu_freq * 5 + 3) / 4;
3551 ring_freq = max(min_ring_freq, ring_freq);
3552 /* leave ia_freq as the default, chosen by cpufreq */
3554 /* On older processors, there is no separate ring
3555 * clock domain, so in order to boost the bandwidth
3556 * of the ring, we need to upclock the CPU (ia_freq).
3558 * For GPU frequencies less than 750MHz,
3559 * just use the lowest ring freq.
3561 if (gpu_freq < min_freq)
3564 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3565 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3568 sandybridge_pcode_write(dev_priv,
3569 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3570 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3571 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3576 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3580 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3582 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3584 rp0 = min_t(u32, rp0, 0xea);
3589 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3593 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3594 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3595 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3596 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3601 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3603 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3606 static void vlv_rps_timer_work(struct work_struct *work)
3608 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3612 * Timer fired, we must be idle. Drop to min voltage state.
3613 * Note: we use RPe here since it should match the
3614 * Vmin we were shooting for. That should give us better
3615 * perf when we come back out of RC6 than if we used the
3616 * min freq available.
3618 mutex_lock(&dev_priv->rps.hw_lock);
3619 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3620 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3621 mutex_unlock(&dev_priv->rps.hw_lock);
3624 static void valleyview_setup_pctx(struct drm_device *dev)
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 struct drm_i915_gem_object *pctx;
3628 unsigned long pctx_paddr;
3630 int pctx_size = 24*1024;
3632 pcbr = I915_READ(VLV_PCBR);
3634 /* BIOS set it up already, grab the pre-alloc'd space */
3637 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3638 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3640 I915_GTT_OFFSET_NONE,
3646 * From the Gunit register HAS:
3647 * The Gfx driver is expected to program this register and ensure
3648 * proper allocation within Gfx stolen memory. For example, this
3649 * register should be programmed such than the PCBR range does not
3650 * overlap with other ranges, such as the frame buffer, protected
3651 * memory, or any other relevant ranges.
3653 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3655 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3659 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3660 I915_WRITE(VLV_PCBR, pctx_paddr);
3663 dev_priv->vlv_pctx = pctx;
3666 static void valleyview_enable_rps(struct drm_device *dev)
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 struct intel_ring_buffer *ring;
3673 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3675 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3676 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3677 I915_WRITE(GTFIFODBG, gtfifodbg);
3680 valleyview_setup_pctx(dev);
3682 gen6_gt_force_wake_get(dev_priv);
3684 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3685 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3686 I915_WRITE(GEN6_RP_UP_EI, 66000);
3687 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3689 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3691 I915_WRITE(GEN6_RP_CONTROL,
3692 GEN6_RP_MEDIA_TURBO |
3693 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3694 GEN6_RP_MEDIA_IS_GFX |
3696 GEN6_RP_UP_BUSY_AVG |
3697 GEN6_RP_DOWN_IDLE_CONT);
3699 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3700 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3701 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3703 for_each_ring(ring, dev_priv, i)
3704 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3706 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3708 /* allows RC6 residency counter to work */
3709 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3710 I915_WRITE(GEN6_RC_CONTROL,
3711 GEN7_RC_CTL_TO_MODE);
3713 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3714 switch ((val >> 6) & 3) {
3717 dev_priv->mem_freq = 800;
3720 dev_priv->mem_freq = 1066;
3723 dev_priv->mem_freq = 1333;
3726 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3728 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3729 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3731 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3732 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3733 vlv_gpu_freq(dev_priv->mem_freq,
3734 dev_priv->rps.cur_delay),
3735 dev_priv->rps.cur_delay);
3737 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3738 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3739 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3740 vlv_gpu_freq(dev_priv->mem_freq,
3741 dev_priv->rps.max_delay),
3742 dev_priv->rps.max_delay);
3744 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3745 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3746 vlv_gpu_freq(dev_priv->mem_freq,
3747 dev_priv->rps.rpe_delay),
3748 dev_priv->rps.rpe_delay);
3750 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3751 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3752 vlv_gpu_freq(dev_priv->mem_freq,
3753 dev_priv->rps.min_delay),
3754 dev_priv->rps.min_delay);
3756 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3757 vlv_gpu_freq(dev_priv->mem_freq,
3758 dev_priv->rps.rpe_delay),
3759 dev_priv->rps.rpe_delay);
3761 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3763 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3765 gen6_enable_rps_interrupts(dev);
3767 gen6_gt_force_wake_put(dev_priv);
3770 void ironlake_teardown_rc6(struct drm_device *dev)
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3774 if (dev_priv->ips.renderctx) {
3775 i915_gem_object_unpin(dev_priv->ips.renderctx);
3776 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3777 dev_priv->ips.renderctx = NULL;
3780 if (dev_priv->ips.pwrctx) {
3781 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3782 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3783 dev_priv->ips.pwrctx = NULL;
3787 static void ironlake_disable_rc6(struct drm_device *dev)
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3791 if (I915_READ(PWRCTXA)) {
3792 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3793 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3794 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3797 I915_WRITE(PWRCTXA, 0);
3798 POSTING_READ(PWRCTXA);
3800 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3801 POSTING_READ(RSTDBYCTL);
3805 static int ironlake_setup_rc6(struct drm_device *dev)
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3809 if (dev_priv->ips.renderctx == NULL)
3810 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3811 if (!dev_priv->ips.renderctx)
3814 if (dev_priv->ips.pwrctx == NULL)
3815 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3816 if (!dev_priv->ips.pwrctx) {
3817 ironlake_teardown_rc6(dev);
3824 static void ironlake_enable_rc6(struct drm_device *dev)
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3828 bool was_interruptible;
3831 /* rc6 disabled by default due to repeated reports of hanging during
3834 if (!intel_enable_rc6(dev))
3837 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3839 ret = ironlake_setup_rc6(dev);
3843 was_interruptible = dev_priv->mm.interruptible;
3844 dev_priv->mm.interruptible = false;
3847 * GPU can automatically power down the render unit if given a page
3850 ret = intel_ring_begin(ring, 6);
3852 ironlake_teardown_rc6(dev);
3853 dev_priv->mm.interruptible = was_interruptible;
3857 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3858 intel_ring_emit(ring, MI_SET_CONTEXT);
3859 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3861 MI_SAVE_EXT_STATE_EN |
3862 MI_RESTORE_EXT_STATE_EN |
3863 MI_RESTORE_INHIBIT);
3864 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3865 intel_ring_emit(ring, MI_NOOP);
3866 intel_ring_emit(ring, MI_FLUSH);
3867 intel_ring_advance(ring);
3870 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3871 * does an implicit flush, combined with MI_FLUSH above, it should be
3872 * safe to assume that renderctx is valid
3874 ret = intel_ring_idle(ring);
3875 dev_priv->mm.interruptible = was_interruptible;
3877 DRM_ERROR("failed to enable ironlake power savings\n");
3878 ironlake_teardown_rc6(dev);
3882 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3883 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3886 static unsigned long intel_pxfreq(u32 vidfreq)
3889 int div = (vidfreq & 0x3f0000) >> 16;
3890 int post = (vidfreq & 0x3000) >> 12;
3891 int pre = (vidfreq & 0x7);
3896 freq = ((div * 133333) / ((1<<post) * pre));
3901 static const struct cparams {
3907 { 1, 1333, 301, 28664 },
3908 { 1, 1066, 294, 24460 },
3909 { 1, 800, 294, 25192 },
3910 { 0, 1333, 276, 27605 },
3911 { 0, 1066, 276, 27605 },
3912 { 0, 800, 231, 23784 },
3915 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3917 u64 total_count, diff, ret;
3918 u32 count1, count2, count3, m = 0, c = 0;
3919 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3922 assert_spin_locked(&mchdev_lock);
3924 diff1 = now - dev_priv->ips.last_time1;
3926 /* Prevent division-by-zero if we are asking too fast.
3927 * Also, we don't get interesting results if we are polling
3928 * faster than once in 10ms, so just return the saved value
3932 return dev_priv->ips.chipset_power;
3934 count1 = I915_READ(DMIEC);
3935 count2 = I915_READ(DDREC);
3936 count3 = I915_READ(CSIEC);
3938 total_count = count1 + count2 + count3;
3940 /* FIXME: handle per-counter overflow */
3941 if (total_count < dev_priv->ips.last_count1) {
3942 diff = ~0UL - dev_priv->ips.last_count1;
3943 diff += total_count;
3945 diff = total_count - dev_priv->ips.last_count1;
3948 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3949 if (cparams[i].i == dev_priv->ips.c_m &&
3950 cparams[i].t == dev_priv->ips.r_t) {
3957 diff = div_u64(diff, diff1);
3958 ret = ((m * diff) + c);
3959 ret = div_u64(ret, 10);
3961 dev_priv->ips.last_count1 = total_count;
3962 dev_priv->ips.last_time1 = now;
3964 dev_priv->ips.chipset_power = ret;
3969 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3973 if (dev_priv->info->gen != 5)
3976 spin_lock_irq(&mchdev_lock);
3978 val = __i915_chipset_val(dev_priv);
3980 spin_unlock_irq(&mchdev_lock);
3985 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3987 unsigned long m, x, b;
3990 tsfs = I915_READ(TSFS);
3992 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3993 x = I915_READ8(TR1);
3995 b = tsfs & TSFS_INTR_MASK;
3997 return ((m * x) / 127) - b;
4000 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4002 static const struct v_table {
4003 u16 vd; /* in .1 mil */
4004 u16 vm; /* in .1 mil */
4135 if (dev_priv->info->is_mobile)
4136 return v_table[pxvid].vm;
4138 return v_table[pxvid].vd;
4141 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4143 struct timespec now, diff1;
4145 unsigned long diffms;
4148 assert_spin_locked(&mchdev_lock);
4150 getrawmonotonic(&now);
4151 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4153 /* Don't divide by 0 */
4154 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4158 count = I915_READ(GFXEC);
4160 if (count < dev_priv->ips.last_count2) {
4161 diff = ~0UL - dev_priv->ips.last_count2;
4164 diff = count - dev_priv->ips.last_count2;
4167 dev_priv->ips.last_count2 = count;
4168 dev_priv->ips.last_time2 = now;
4170 /* More magic constants... */
4172 diff = div_u64(diff, diffms * 10);
4173 dev_priv->ips.gfx_power = diff;
4176 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4178 if (dev_priv->info->gen != 5)
4181 spin_lock_irq(&mchdev_lock);
4183 __i915_update_gfx_val(dev_priv);
4185 spin_unlock_irq(&mchdev_lock);
4188 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4190 unsigned long t, corr, state1, corr2, state2;
4193 assert_spin_locked(&mchdev_lock);
4195 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4196 pxvid = (pxvid >> 24) & 0x7f;
4197 ext_v = pvid_to_extvid(dev_priv, pxvid);
4201 t = i915_mch_val(dev_priv);
4203 /* Revel in the empirically derived constants */
4205 /* Correction factor in 1/100000 units */
4207 corr = ((t * 2349) + 135940);
4209 corr = ((t * 964) + 29317);
4211 corr = ((t * 301) + 1004);
4213 corr = corr * ((150142 * state1) / 10000 - 78642);
4215 corr2 = (corr * dev_priv->ips.corr);
4217 state2 = (corr2 * state1) / 10000;
4218 state2 /= 100; /* convert to mW */
4220 __i915_update_gfx_val(dev_priv);
4222 return dev_priv->ips.gfx_power + state2;
4225 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4229 if (dev_priv->info->gen != 5)
4232 spin_lock_irq(&mchdev_lock);
4234 val = __i915_gfx_val(dev_priv);
4236 spin_unlock_irq(&mchdev_lock);
4242 * i915_read_mch_val - return value for IPS use
4244 * Calculate and return a value for the IPS driver to use when deciding whether
4245 * we have thermal and power headroom to increase CPU or GPU power budget.
4247 unsigned long i915_read_mch_val(void)
4249 struct drm_i915_private *dev_priv;
4250 unsigned long chipset_val, graphics_val, ret = 0;
4252 spin_lock_irq(&mchdev_lock);
4255 dev_priv = i915_mch_dev;
4257 chipset_val = __i915_chipset_val(dev_priv);
4258 graphics_val = __i915_gfx_val(dev_priv);
4260 ret = chipset_val + graphics_val;
4263 spin_unlock_irq(&mchdev_lock);
4267 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4270 * i915_gpu_raise - raise GPU frequency limit
4272 * Raise the limit; IPS indicates we have thermal headroom.
4274 bool i915_gpu_raise(void)
4276 struct drm_i915_private *dev_priv;
4279 spin_lock_irq(&mchdev_lock);
4280 if (!i915_mch_dev) {
4284 dev_priv = i915_mch_dev;
4286 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4287 dev_priv->ips.max_delay--;
4290 spin_unlock_irq(&mchdev_lock);
4294 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4297 * i915_gpu_lower - lower GPU frequency limit
4299 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4300 * frequency maximum.
4302 bool i915_gpu_lower(void)
4304 struct drm_i915_private *dev_priv;
4307 spin_lock_irq(&mchdev_lock);
4308 if (!i915_mch_dev) {
4312 dev_priv = i915_mch_dev;
4314 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4315 dev_priv->ips.max_delay++;
4318 spin_unlock_irq(&mchdev_lock);
4322 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4325 * i915_gpu_busy - indicate GPU business to IPS
4327 * Tell the IPS driver whether or not the GPU is busy.
4329 bool i915_gpu_busy(void)
4331 struct drm_i915_private *dev_priv;
4332 struct intel_ring_buffer *ring;
4336 spin_lock_irq(&mchdev_lock);
4339 dev_priv = i915_mch_dev;
4341 for_each_ring(ring, dev_priv, i)
4342 ret |= !list_empty(&ring->request_list);
4345 spin_unlock_irq(&mchdev_lock);
4349 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4352 * i915_gpu_turbo_disable - disable graphics turbo
4354 * Disable graphics turbo by resetting the max frequency and setting the
4355 * current frequency to the default.
4357 bool i915_gpu_turbo_disable(void)
4359 struct drm_i915_private *dev_priv;
4362 spin_lock_irq(&mchdev_lock);
4363 if (!i915_mch_dev) {
4367 dev_priv = i915_mch_dev;
4369 dev_priv->ips.max_delay = dev_priv->ips.fstart;
4371 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4375 spin_unlock_irq(&mchdev_lock);
4379 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4382 * Tells the intel_ips driver that the i915 driver is now loaded, if
4383 * IPS got loaded first.
4385 * This awkward dance is so that neither module has to depend on the
4386 * other in order for IPS to do the appropriate communication of
4387 * GPU turbo limits to i915.
4390 ips_ping_for_i915_load(void)
4394 link = symbol_get(ips_link_to_i915_driver);
4397 symbol_put(ips_link_to_i915_driver);
4401 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4403 /* We only register the i915 ips part with intel-ips once everything is
4404 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4405 spin_lock_irq(&mchdev_lock);
4406 i915_mch_dev = dev_priv;
4407 spin_unlock_irq(&mchdev_lock);
4409 ips_ping_for_i915_load();
4412 void intel_gpu_ips_teardown(void)
4414 spin_lock_irq(&mchdev_lock);
4415 i915_mch_dev = NULL;
4416 spin_unlock_irq(&mchdev_lock);
4418 static void intel_init_emon(struct drm_device *dev)
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4425 /* Disable to program */
4429 /* Program energy weights for various events */
4430 I915_WRITE(SDEW, 0x15040d00);
4431 I915_WRITE(CSIEW0, 0x007f0000);
4432 I915_WRITE(CSIEW1, 0x1e220004);
4433 I915_WRITE(CSIEW2, 0x04000004);
4435 for (i = 0; i < 5; i++)
4436 I915_WRITE(PEW + (i * 4), 0);
4437 for (i = 0; i < 3; i++)
4438 I915_WRITE(DEW + (i * 4), 0);
4440 /* Program P-state weights to account for frequency power adjustment */
4441 for (i = 0; i < 16; i++) {
4442 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4443 unsigned long freq = intel_pxfreq(pxvidfreq);
4444 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4449 val *= (freq / 1000);
4451 val /= (127*127*900);
4453 DRM_ERROR("bad pxval: %ld\n", val);
4456 /* Render standby states get 0 weight */
4460 for (i = 0; i < 4; i++) {
4461 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4462 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4463 I915_WRITE(PXW + (i * 4), val);
4466 /* Adjust magic regs to magic values (more experimental results) */
4467 I915_WRITE(OGW0, 0);
4468 I915_WRITE(OGW1, 0);
4469 I915_WRITE(EG0, 0x00007f00);
4470 I915_WRITE(EG1, 0x0000000e);
4471 I915_WRITE(EG2, 0x000e0000);
4472 I915_WRITE(EG3, 0x68000300);
4473 I915_WRITE(EG4, 0x42000000);
4474 I915_WRITE(EG5, 0x00140031);
4478 for (i = 0; i < 8; i++)
4479 I915_WRITE(PXWL + (i * 4), 0);
4481 /* Enable PMON + select events */
4482 I915_WRITE(ECR, 0x80000019);
4484 lcfuse = I915_READ(LCFUSE02);
4486 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4489 void intel_disable_gt_powersave(struct drm_device *dev)
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4493 /* Interrupts should be disabled already to avoid re-arming. */
4494 WARN_ON(dev->irq_enabled);
4496 if (IS_IRONLAKE_M(dev)) {
4497 ironlake_disable_drps(dev);
4498 ironlake_disable_rc6(dev);
4499 } else if (INTEL_INFO(dev)->gen >= 6) {
4500 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4501 cancel_work_sync(&dev_priv->rps.work);
4502 if (IS_VALLEYVIEW(dev))
4503 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4504 mutex_lock(&dev_priv->rps.hw_lock);
4505 if (IS_VALLEYVIEW(dev))
4506 valleyview_disable_rps(dev);
4508 gen6_disable_rps(dev);
4509 mutex_unlock(&dev_priv->rps.hw_lock);
4513 static void intel_gen6_powersave_work(struct work_struct *work)
4515 struct drm_i915_private *dev_priv =
4516 container_of(work, struct drm_i915_private,
4517 rps.delayed_resume_work.work);
4518 struct drm_device *dev = dev_priv->dev;
4520 mutex_lock(&dev_priv->rps.hw_lock);
4522 if (IS_VALLEYVIEW(dev)) {
4523 valleyview_enable_rps(dev);
4525 gen6_enable_rps(dev);
4526 gen6_update_ring_freq(dev);
4528 mutex_unlock(&dev_priv->rps.hw_lock);
4531 void intel_enable_gt_powersave(struct drm_device *dev)
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4535 if (IS_IRONLAKE_M(dev)) {
4536 ironlake_enable_drps(dev);
4537 ironlake_enable_rc6(dev);
4538 intel_init_emon(dev);
4539 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4541 * PCU communication is slow and this doesn't need to be
4542 * done at any specific time, so do this out of our fast path
4543 * to make resume and init faster.
4545 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4546 round_jiffies_up_relative(HZ));
4550 static void ibx_init_clock_gating(struct drm_device *dev)
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4555 * On Ibex Peak and Cougar Point, we need to disable clock
4556 * gating for the panel power sequencer or it will fail to
4557 * start up when no ports are active.
4559 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4562 static void g4x_disable_trickle_feed(struct drm_device *dev)
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4567 for_each_pipe(pipe) {
4568 I915_WRITE(DSPCNTR(pipe),
4569 I915_READ(DSPCNTR(pipe)) |
4570 DISPPLANE_TRICKLE_FEED_DISABLE);
4571 intel_flush_display_plane(dev_priv, pipe);
4575 static void ironlake_init_clock_gating(struct drm_device *dev)
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4582 * WaFbcDisableDpfcClockGating:ilk
4584 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4585 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4586 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4588 I915_WRITE(PCH_3DCGDIS0,
4589 MARIUNIT_CLOCK_GATE_DISABLE |
4590 SVSMUNIT_CLOCK_GATE_DISABLE);
4591 I915_WRITE(PCH_3DCGDIS1,
4592 VFMUNIT_CLOCK_GATE_DISABLE);
4595 * According to the spec the following bits should be set in
4596 * order to enable memory self-refresh
4597 * The bit 22/21 of 0x42004
4598 * The bit 5 of 0x42020
4599 * The bit 15 of 0x45000
4601 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4602 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4603 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4604 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4605 I915_WRITE(DISP_ARB_CTL,
4606 (I915_READ(DISP_ARB_CTL) |
4608 I915_WRITE(WM3_LP_ILK, 0);
4609 I915_WRITE(WM2_LP_ILK, 0);
4610 I915_WRITE(WM1_LP_ILK, 0);
4613 * Based on the document from hardware guys the following bits
4614 * should be set unconditionally in order to enable FBC.
4615 * The bit 22 of 0x42000
4616 * The bit 22 of 0x42004
4617 * The bit 7,8,9 of 0x42020.
4619 if (IS_IRONLAKE_M(dev)) {
4620 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4621 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4622 I915_READ(ILK_DISPLAY_CHICKEN1) |
4624 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4625 I915_READ(ILK_DISPLAY_CHICKEN2) |
4629 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4631 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4632 I915_READ(ILK_DISPLAY_CHICKEN2) |
4633 ILK_ELPIN_409_SELECT);
4634 I915_WRITE(_3D_CHICKEN2,
4635 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4636 _3D_CHICKEN2_WM_READ_PIPELINED);
4638 /* WaDisableRenderCachePipelinedFlush:ilk */
4639 I915_WRITE(CACHE_MODE_0,
4640 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4642 g4x_disable_trickle_feed(dev);
4644 ibx_init_clock_gating(dev);
4647 static void cpt_init_clock_gating(struct drm_device *dev)
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4654 * On Ibex Peak and Cougar Point, we need to disable clock
4655 * gating for the panel power sequencer or it will fail to
4656 * start up when no ports are active.
4658 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4659 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4660 DPLS_EDP_PPS_FIX_DIS);
4661 /* The below fixes the weird display corruption, a few pixels shifted
4662 * downward, on (only) LVDS of some HP laptops with IVY.
4664 for_each_pipe(pipe) {
4665 val = I915_READ(TRANS_CHICKEN2(pipe));
4666 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4667 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4668 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4669 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4670 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4671 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4672 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4673 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4675 /* WADP0ClockGatingDisable */
4676 for_each_pipe(pipe) {
4677 I915_WRITE(TRANS_CHICKEN1(pipe),
4678 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4682 static void gen6_check_mch_setup(struct drm_device *dev)
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4687 tmp = I915_READ(MCH_SSKPD);
4688 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4689 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4690 DRM_INFO("This can cause pipe underruns and display issues.\n");
4691 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4695 static void gen6_init_clock_gating(struct drm_device *dev)
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4700 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4702 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4703 I915_READ(ILK_DISPLAY_CHICKEN2) |
4704 ILK_ELPIN_409_SELECT);
4706 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4707 I915_WRITE(_3D_CHICKEN,
4708 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4710 /* WaSetupGtModeTdRowDispatch:snb */
4711 if (IS_SNB_GT1(dev))
4712 I915_WRITE(GEN6_GT_MODE,
4713 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4715 I915_WRITE(WM3_LP_ILK, 0);
4716 I915_WRITE(WM2_LP_ILK, 0);
4717 I915_WRITE(WM1_LP_ILK, 0);
4719 I915_WRITE(CACHE_MODE_0,
4720 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4722 I915_WRITE(GEN6_UCGCTL1,
4723 I915_READ(GEN6_UCGCTL1) |
4724 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4725 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4727 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4728 * gating disable must be set. Failure to set it results in
4729 * flickering pixels due to Z write ordering failures after
4730 * some amount of runtime in the Mesa "fire" demo, and Unigine
4731 * Sanctuary and Tropics, and apparently anything else with
4732 * alpha test or pixel discard.
4734 * According to the spec, bit 11 (RCCUNIT) must also be set,
4735 * but we didn't debug actual testcases to find it out.
4737 * Also apply WaDisableVDSUnitClockGating:snb and
4738 * WaDisableRCPBUnitClockGating:snb.
4740 I915_WRITE(GEN6_UCGCTL2,
4741 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4742 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4743 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4745 /* Bspec says we need to always set all mask bits. */
4746 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4747 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4750 * According to the spec the following bits should be
4751 * set in order to enable memory self-refresh and fbc:
4752 * The bit21 and bit22 of 0x42000
4753 * The bit21 and bit22 of 0x42004
4754 * The bit5 and bit7 of 0x42020
4755 * The bit14 of 0x70180
4756 * The bit14 of 0x71180
4758 * WaFbcAsynchFlipDisableFbcQueue:snb
4760 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4761 I915_READ(ILK_DISPLAY_CHICKEN1) |
4762 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4763 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4764 I915_READ(ILK_DISPLAY_CHICKEN2) |
4765 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4766 I915_WRITE(ILK_DSPCLK_GATE_D,
4767 I915_READ(ILK_DSPCLK_GATE_D) |
4768 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4769 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4771 /* WaMbcDriverBootEnable:snb */
4772 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4773 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4775 g4x_disable_trickle_feed(dev);
4777 /* The default value should be 0x200 according to docs, but the two
4778 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4779 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4780 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4782 cpt_init_clock_gating(dev);
4784 gen6_check_mch_setup(dev);
4787 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4789 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4791 reg &= ~GEN7_FF_SCHED_MASK;
4792 reg |= GEN7_FF_TS_SCHED_HW;
4793 reg |= GEN7_FF_VS_SCHED_HW;
4794 reg |= GEN7_FF_DS_SCHED_HW;
4796 if (IS_HASWELL(dev_priv->dev))
4797 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4799 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4802 static void lpt_init_clock_gating(struct drm_device *dev)
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4807 * TODO: this bit should only be enabled when really needed, then
4808 * disabled when not needed anymore in order to save power.
4810 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4811 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4812 I915_READ(SOUTH_DSPCLK_GATE_D) |
4813 PCH_LP_PARTITION_LEVEL_DISABLE);
4815 /* WADPOClockGatingDisable:hsw */
4816 I915_WRITE(_TRANSA_CHICKEN1,
4817 I915_READ(_TRANSA_CHICKEN1) |
4818 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4821 static void lpt_suspend_hw(struct drm_device *dev)
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4825 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4826 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4828 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4829 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4833 static void haswell_init_clock_gating(struct drm_device *dev)
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4837 I915_WRITE(WM3_LP_ILK, 0);
4838 I915_WRITE(WM2_LP_ILK, 0);
4839 I915_WRITE(WM1_LP_ILK, 0);
4841 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4842 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4844 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4846 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4847 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4848 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4850 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4851 I915_WRITE(GEN7_L3CNTLREG1,
4852 GEN7_WA_FOR_GEN7_L3_CONTROL);
4853 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4854 GEN7_WA_L3_CHICKEN_MODE);
4856 /* This is required by WaCatErrorRejectionIssue:hsw */
4857 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4858 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4859 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4861 g4x_disable_trickle_feed(dev);
4863 /* WaVSRefCountFullforceMissDisable:hsw */
4864 gen7_setup_fixed_func_scheduler(dev_priv);
4866 /* WaDisable4x2SubspanOptimization:hsw */
4867 I915_WRITE(CACHE_MODE_1,
4868 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4870 /* WaMbcDriverBootEnable:hsw */
4871 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4872 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4874 /* WaSwitchSolVfFArbitrationPriority:hsw */
4875 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4877 /* WaRsPkgCStateDisplayPMReq:hsw */
4878 I915_WRITE(CHICKEN_PAR1_1,
4879 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4881 lpt_init_clock_gating(dev);
4884 static void ivybridge_init_clock_gating(struct drm_device *dev)
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4889 I915_WRITE(WM3_LP_ILK, 0);
4890 I915_WRITE(WM2_LP_ILK, 0);
4891 I915_WRITE(WM1_LP_ILK, 0);
4893 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4895 /* WaDisableEarlyCull:ivb */
4896 I915_WRITE(_3D_CHICKEN3,
4897 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4899 /* WaDisableBackToBackFlipFix:ivb */
4900 I915_WRITE(IVB_CHICKEN3,
4901 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4902 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4904 /* WaDisablePSDDualDispatchEnable:ivb */
4905 if (IS_IVB_GT1(dev))
4906 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4907 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4909 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4910 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4912 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4913 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4914 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4916 /* WaApplyL3ControlAndL3ChickenMode:ivb */
4917 I915_WRITE(GEN7_L3CNTLREG1,
4918 GEN7_WA_FOR_GEN7_L3_CONTROL);
4919 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4920 GEN7_WA_L3_CHICKEN_MODE);
4921 if (IS_IVB_GT1(dev))
4922 I915_WRITE(GEN7_ROW_CHICKEN2,
4923 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4925 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4926 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4929 /* WaForceL3Serialization:ivb */
4930 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4931 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4933 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4934 * gating disable must be set. Failure to set it results in
4935 * flickering pixels due to Z write ordering failures after
4936 * some amount of runtime in the Mesa "fire" demo, and Unigine
4937 * Sanctuary and Tropics, and apparently anything else with
4938 * alpha test or pixel discard.
4940 * According to the spec, bit 11 (RCCUNIT) must also be set,
4941 * but we didn't debug actual testcases to find it out.
4943 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4944 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4946 I915_WRITE(GEN6_UCGCTL2,
4947 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4948 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4950 /* This is required by WaCatErrorRejectionIssue:ivb */
4951 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4952 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4953 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4955 g4x_disable_trickle_feed(dev);
4957 /* WaMbcDriverBootEnable:ivb */
4958 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4959 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4961 /* WaVSRefCountFullforceMissDisable:ivb */
4962 gen7_setup_fixed_func_scheduler(dev_priv);
4964 /* WaDisable4x2SubspanOptimization:ivb */
4965 I915_WRITE(CACHE_MODE_1,
4966 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4968 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4969 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4970 snpcr |= GEN6_MBC_SNPCR_MED;
4971 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4973 if (!HAS_PCH_NOP(dev))
4974 cpt_init_clock_gating(dev);
4976 gen6_check_mch_setup(dev);
4979 static void valleyview_init_clock_gating(struct drm_device *dev)
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4983 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
4985 /* WaDisableEarlyCull:vlv */
4986 I915_WRITE(_3D_CHICKEN3,
4987 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4989 /* WaDisableBackToBackFlipFix:vlv */
4990 I915_WRITE(IVB_CHICKEN3,
4991 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4992 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4994 /* WaDisablePSDDualDispatchEnable:vlv */
4995 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4996 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4997 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4999 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5000 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5001 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5003 /* WaApplyL3ControlAndL3ChickenMode:vlv */
5004 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5005 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5007 /* WaForceL3Serialization:vlv */
5008 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5009 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5011 /* WaDisableDopClockGating:vlv */
5012 I915_WRITE(GEN7_ROW_CHICKEN2,
5013 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5015 /* This is required by WaCatErrorRejectionIssue:vlv */
5016 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5017 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5018 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5020 /* WaMbcDriverBootEnable:vlv */
5021 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
5022 GEN6_MBCTL_ENABLE_BOOT_FETCH);
5025 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5026 * gating disable must be set. Failure to set it results in
5027 * flickering pixels due to Z write ordering failures after
5028 * some amount of runtime in the Mesa "fire" demo, and Unigine
5029 * Sanctuary and Tropics, and apparently anything else with
5030 * alpha test or pixel discard.
5032 * According to the spec, bit 11 (RCCUNIT) must also be set,
5033 * but we didn't debug actual testcases to find it out.
5035 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5036 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5038 * Also apply WaDisableVDSUnitClockGating:vlv and
5039 * WaDisableRCPBUnitClockGating:vlv.
5041 I915_WRITE(GEN6_UCGCTL2,
5042 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5043 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5044 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5045 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5046 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5048 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5050 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5052 I915_WRITE(CACHE_MODE_1,
5053 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5056 * WaDisableVLVClockGating_VBIIssue:vlv
5057 * Disable clock gating on th GCFG unit to prevent a delay
5058 * in the reporting of vblank events.
5060 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5062 /* Conservative clock gating settings for now */
5063 I915_WRITE(0x9400, 0xffffffff);
5064 I915_WRITE(0x9404, 0xffffffff);
5065 I915_WRITE(0x9408, 0xffffffff);
5066 I915_WRITE(0x940c, 0xffffffff);
5067 I915_WRITE(0x9410, 0xffffffff);
5068 I915_WRITE(0x9414, 0xffffffff);
5069 I915_WRITE(0x9418, 0xffffffff);
5072 static void g4x_init_clock_gating(struct drm_device *dev)
5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 uint32_t dspclk_gate;
5077 I915_WRITE(RENCLK_GATE_D1, 0);
5078 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5079 GS_UNIT_CLOCK_GATE_DISABLE |
5080 CL_UNIT_CLOCK_GATE_DISABLE);
5081 I915_WRITE(RAMCLK_GATE_D, 0);
5082 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5083 OVRUNIT_CLOCK_GATE_DISABLE |
5084 OVCUNIT_CLOCK_GATE_DISABLE;
5086 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5087 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5089 /* WaDisableRenderCachePipelinedFlush */
5090 I915_WRITE(CACHE_MODE_0,
5091 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5093 g4x_disable_trickle_feed(dev);
5096 static void crestline_init_clock_gating(struct drm_device *dev)
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5100 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5101 I915_WRITE(RENCLK_GATE_D2, 0);
5102 I915_WRITE(DSPCLK_GATE_D, 0);
5103 I915_WRITE(RAMCLK_GATE_D, 0);
5104 I915_WRITE16(DEUC, 0);
5105 I915_WRITE(MI_ARB_STATE,
5106 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5109 static void broadwater_init_clock_gating(struct drm_device *dev)
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5113 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5114 I965_RCC_CLOCK_GATE_DISABLE |
5115 I965_RCPB_CLOCK_GATE_DISABLE |
5116 I965_ISC_CLOCK_GATE_DISABLE |
5117 I965_FBC_CLOCK_GATE_DISABLE);
5118 I915_WRITE(RENCLK_GATE_D2, 0);
5119 I915_WRITE(MI_ARB_STATE,
5120 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5123 static void gen3_init_clock_gating(struct drm_device *dev)
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 u32 dstate = I915_READ(D_STATE);
5128 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5129 DSTATE_DOT_CLOCK_GATING;
5130 I915_WRITE(D_STATE, dstate);
5132 if (IS_PINEVIEW(dev))
5133 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5135 /* IIR "flip pending" means done if this bit is set */
5136 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5139 static void i85x_init_clock_gating(struct drm_device *dev)
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5143 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5146 static void i830_init_clock_gating(struct drm_device *dev)
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5150 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5153 void intel_init_clock_gating(struct drm_device *dev)
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5157 dev_priv->display.init_clock_gating(dev);
5160 void intel_suspend_hw(struct drm_device *dev)
5162 if (HAS_PCH_LPT(dev))
5163 lpt_suspend_hw(dev);
5167 * We should only use the power well if we explicitly asked the hardware to
5168 * enable it, so check if it's enabled and also check if we've requested it to
5171 bool intel_display_power_enabled(struct drm_device *dev,
5172 enum intel_display_power_domain domain)
5174 struct drm_i915_private *dev_priv = dev->dev_private;
5176 if (!HAS_POWER_WELL(dev))
5180 case POWER_DOMAIN_PIPE_A:
5181 case POWER_DOMAIN_TRANSCODER_EDP:
5183 case POWER_DOMAIN_PIPE_B:
5184 case POWER_DOMAIN_PIPE_C:
5185 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5186 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5187 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5188 case POWER_DOMAIN_TRANSCODER_A:
5189 case POWER_DOMAIN_TRANSCODER_B:
5190 case POWER_DOMAIN_TRANSCODER_C:
5191 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5192 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
5198 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 bool is_enabled, enable_requested;
5204 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5205 is_enabled = tmp & HSW_PWR_WELL_STATE;
5206 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
5209 if (!enable_requested)
5210 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
5213 DRM_DEBUG_KMS("Enabling power well\n");
5214 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5215 HSW_PWR_WELL_STATE), 20))
5216 DRM_ERROR("Timeout enabling power well\n");
5219 if (enable_requested) {
5220 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5221 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5226 static struct i915_power_well *hsw_pwr;
5228 /* Display audio driver power well request */
5229 void i915_request_power_well(void)
5231 if (WARN_ON(!hsw_pwr))
5234 spin_lock_irq(&hsw_pwr->lock);
5235 if (!hsw_pwr->count++ &&
5236 !hsw_pwr->i915_request)
5237 __intel_set_power_well(hsw_pwr->device, true);
5238 spin_unlock_irq(&hsw_pwr->lock);
5240 EXPORT_SYMBOL_GPL(i915_request_power_well);
5242 /* Display audio driver power well release */
5243 void i915_release_power_well(void)
5245 if (WARN_ON(!hsw_pwr))
5248 spin_lock_irq(&hsw_pwr->lock);
5249 WARN_ON(!hsw_pwr->count);
5250 if (!--hsw_pwr->count &&
5251 !hsw_pwr->i915_request)
5252 __intel_set_power_well(hsw_pwr->device, false);
5253 spin_unlock_irq(&hsw_pwr->lock);
5255 EXPORT_SYMBOL_GPL(i915_release_power_well);
5257 int i915_init_power_well(struct drm_device *dev)
5259 struct drm_i915_private *dev_priv = dev->dev_private;
5261 hsw_pwr = &dev_priv->power_well;
5263 hsw_pwr->device = dev;
5264 spin_lock_init(&hsw_pwr->lock);
5270 void i915_remove_power_well(struct drm_device *dev)
5275 void intel_set_power_well(struct drm_device *dev, bool enable)
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct i915_power_well *power_well = &dev_priv->power_well;
5280 if (!HAS_POWER_WELL(dev))
5283 if (!i915_disable_power_well && !enable)
5286 spin_lock_irq(&power_well->lock);
5287 power_well->i915_request = enable;
5289 /* only reject "disable" power well request */
5290 if (power_well->count && !enable) {
5291 spin_unlock_irq(&power_well->lock);
5295 __intel_set_power_well(dev, enable);
5296 spin_unlock_irq(&power_well->lock);
5300 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5301 * when not needed anymore. We have 4 registers that can request the power well
5302 * to be enabled, and it will only be disabled if none of the registers is
5303 * requesting it to be enabled.
5305 void intel_init_power_well(struct drm_device *dev)
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5309 if (!HAS_POWER_WELL(dev))
5312 /* For now, we need the power well to be always enabled. */
5313 intel_set_power_well(dev, true);
5315 /* We're taking over the BIOS, so clear any requests made by it since
5316 * the driver is in charge now. */
5317 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5318 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5321 /* Set up chip specific power management-related functions */
5322 void intel_init_pm(struct drm_device *dev)
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5326 if (I915_HAS_FBC(dev)) {
5327 if (HAS_PCH_SPLIT(dev)) {
5328 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5329 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5330 dev_priv->display.enable_fbc =
5333 dev_priv->display.enable_fbc =
5334 ironlake_enable_fbc;
5335 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5336 } else if (IS_GM45(dev)) {
5337 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5338 dev_priv->display.enable_fbc = g4x_enable_fbc;
5339 dev_priv->display.disable_fbc = g4x_disable_fbc;
5340 } else if (IS_CRESTLINE(dev)) {
5341 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5342 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5343 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5345 /* 855GM needs testing */
5349 if (IS_PINEVIEW(dev))
5350 i915_pineview_get_mem_freq(dev);
5351 else if (IS_GEN5(dev))
5352 i915_ironlake_get_mem_freq(dev);
5354 /* For FIFO watermark updates */
5355 if (HAS_PCH_SPLIT(dev)) {
5356 intel_setup_wm_latency(dev);
5359 if (dev_priv->wm.pri_latency[1] &&
5360 dev_priv->wm.spr_latency[1] &&
5361 dev_priv->wm.cur_latency[1])
5362 dev_priv->display.update_wm = ironlake_update_wm;
5364 DRM_DEBUG_KMS("Failed to get proper latency. "
5366 dev_priv->display.update_wm = NULL;
5368 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5369 } else if (IS_GEN6(dev)) {
5370 if (dev_priv->wm.pri_latency[0] &&
5371 dev_priv->wm.spr_latency[0] &&
5372 dev_priv->wm.cur_latency[0]) {
5373 dev_priv->display.update_wm = sandybridge_update_wm;
5374 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5376 DRM_DEBUG_KMS("Failed to read display plane latency. "
5378 dev_priv->display.update_wm = NULL;
5380 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5381 } else if (IS_IVYBRIDGE(dev)) {
5382 if (dev_priv->wm.pri_latency[0] &&
5383 dev_priv->wm.spr_latency[0] &&
5384 dev_priv->wm.cur_latency[0]) {
5385 dev_priv->display.update_wm = ivybridge_update_wm;
5386 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5388 DRM_DEBUG_KMS("Failed to read display plane latency. "
5390 dev_priv->display.update_wm = NULL;
5392 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5393 } else if (IS_HASWELL(dev)) {
5394 if (dev_priv->wm.pri_latency[0] &&
5395 dev_priv->wm.spr_latency[0] &&
5396 dev_priv->wm.cur_latency[0]) {
5397 dev_priv->display.update_wm = haswell_update_wm;
5398 dev_priv->display.update_sprite_wm =
5399 haswell_update_sprite_wm;
5401 DRM_DEBUG_KMS("Failed to read display plane latency. "
5403 dev_priv->display.update_wm = NULL;
5405 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5407 dev_priv->display.update_wm = NULL;
5408 } else if (IS_VALLEYVIEW(dev)) {
5409 dev_priv->display.update_wm = valleyview_update_wm;
5410 dev_priv->display.init_clock_gating =
5411 valleyview_init_clock_gating;
5412 } else if (IS_PINEVIEW(dev)) {
5413 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5416 dev_priv->mem_freq)) {
5417 DRM_INFO("failed to find known CxSR latency "
5418 "(found ddr%s fsb freq %d, mem freq %d), "
5420 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5421 dev_priv->fsb_freq, dev_priv->mem_freq);
5422 /* Disable CxSR and never update its watermark again */
5423 pineview_disable_cxsr(dev);
5424 dev_priv->display.update_wm = NULL;
5426 dev_priv->display.update_wm = pineview_update_wm;
5427 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5428 } else if (IS_G4X(dev)) {
5429 dev_priv->display.update_wm = g4x_update_wm;
5430 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5431 } else if (IS_GEN4(dev)) {
5432 dev_priv->display.update_wm = i965_update_wm;
5433 if (IS_CRESTLINE(dev))
5434 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5435 else if (IS_BROADWATER(dev))
5436 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5437 } else if (IS_GEN3(dev)) {
5438 dev_priv->display.update_wm = i9xx_update_wm;
5439 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5440 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5441 } else if (IS_I865G(dev)) {
5442 dev_priv->display.update_wm = i830_update_wm;
5443 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5444 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5445 } else if (IS_I85X(dev)) {
5446 dev_priv->display.update_wm = i9xx_update_wm;
5447 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5448 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5450 dev_priv->display.update_wm = i830_update_wm;
5451 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5453 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5455 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5459 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5461 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5463 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5464 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5468 I915_WRITE(GEN6_PCODE_DATA, *val);
5469 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5471 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5473 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5477 *val = I915_READ(GEN6_PCODE_DATA);
5478 I915_WRITE(GEN6_PCODE_DATA, 0);
5483 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5485 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5487 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5488 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5492 I915_WRITE(GEN6_PCODE_DATA, val);
5493 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5495 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5497 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5501 I915_WRITE(GEN6_PCODE_DATA, 0);
5506 int vlv_gpu_freq(int ddr_freq, int val)
5527 return ((val - 0xbd) * mult) + base;
5530 int vlv_freq_opcode(int ddr_freq, int val)
5561 void intel_pm_init(struct drm_device *dev)
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5565 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5566 intel_gen6_powersave_work);