2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
68 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_MEMORY_WAKE);
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
85 gen9_init_clock_gating(dev_priv);
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
102 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
103 PWM1_GATING_DIS | PWM2_GATING_DIS);
106 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
108 gen9_init_clock_gating(dev_priv);
111 * WaDisablePWMClockGating:glk
112 * Backlight PWM may stop in the asserted state, causing backlight
115 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
116 PWM1_GATING_DIS | PWM2_GATING_DIS);
118 /* WaDDIIOTimeout:glk */
119 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
120 u32 val = I915_READ(CHICKEN_MISC_2);
121 val &= ~(GLK_CL0_PWR_DOWN |
124 I915_WRITE(CHICKEN_MISC_2, val);
129 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
133 tmp = I915_READ(CLKCFG);
135 switch (tmp & CLKCFG_FSB_MASK) {
137 dev_priv->fsb_freq = 533; /* 133*4 */
140 dev_priv->fsb_freq = 800; /* 200*4 */
143 dev_priv->fsb_freq = 667; /* 167*4 */
146 dev_priv->fsb_freq = 400; /* 100*4 */
150 switch (tmp & CLKCFG_MEM_MASK) {
152 dev_priv->mem_freq = 533;
155 dev_priv->mem_freq = 667;
158 dev_priv->mem_freq = 800;
162 /* detect pineview DDR3 setting */
163 tmp = I915_READ(CSHRDDR3CTL);
164 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
167 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
171 ddrpll = I915_READ16(DDRMPLL1);
172 csipll = I915_READ16(CSIPLL0);
174 switch (ddrpll & 0xff) {
176 dev_priv->mem_freq = 800;
179 dev_priv->mem_freq = 1066;
182 dev_priv->mem_freq = 1333;
185 dev_priv->mem_freq = 1600;
188 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 dev_priv->mem_freq = 0;
194 dev_priv->ips.r_t = dev_priv->mem_freq;
196 switch (csipll & 0x3ff) {
198 dev_priv->fsb_freq = 3200;
201 dev_priv->fsb_freq = 3733;
204 dev_priv->fsb_freq = 4266;
207 dev_priv->fsb_freq = 4800;
210 dev_priv->fsb_freq = 5333;
213 dev_priv->fsb_freq = 5866;
216 dev_priv->fsb_freq = 6400;
219 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 dev_priv->fsb_freq = 0;
225 if (dev_priv->fsb_freq == 3200) {
226 dev_priv->ips.c_m = 0;
227 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
228 dev_priv->ips.c_m = 1;
230 dev_priv->ips.c_m = 2;
234 static const struct cxsr_latency cxsr_latency_table[] = {
235 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
236 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
237 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
238 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
239 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
242 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
243 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
244 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
245 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
248 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
249 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
250 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
251 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
254 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
255 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
256 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
257 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
260 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
261 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
262 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
263 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
266 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
267 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
268 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
269 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
272 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
277 const struct cxsr_latency *latency;
280 if (fsb == 0 || mem == 0)
283 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
284 latency = &cxsr_latency_table[i];
285 if (is_desktop == latency->is_desktop &&
286 is_ddr3 == latency->is_ddr3 &&
287 fsb == latency->fsb_freq && mem == latency->mem_freq)
291 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
296 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
300 mutex_lock(&dev_priv->rps.hw_lock);
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
304 val &= ~FORCE_DDR_HIGH_FREQ;
306 val |= FORCE_DDR_HIGH_FREQ;
307 val &= ~FORCE_DDR_LOW_FREQ;
308 val |= FORCE_DDR_FREQ_REQ_ACK;
309 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
311 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
312 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
313 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315 mutex_unlock(&dev_priv->rps.hw_lock);
318 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
322 mutex_lock(&dev_priv->rps.hw_lock);
324 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
326 val |= DSP_MAXFIFO_PM5_ENABLE;
328 val &= ~DSP_MAXFIFO_PM5_ENABLE;
329 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
331 mutex_unlock(&dev_priv->rps.hw_lock);
334 #define FW_WM(value, plane) \
335 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
342 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
343 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
344 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
345 POSTING_READ(FW_BLC_SELF_VLV);
346 } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
347 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
348 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
349 POSTING_READ(FW_BLC_SELF);
350 } else if (IS_PINEVIEW(dev_priv)) {
351 val = I915_READ(DSPFW3);
352 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
354 val |= PINEVIEW_SELF_REFRESH_EN;
356 val &= ~PINEVIEW_SELF_REFRESH_EN;
357 I915_WRITE(DSPFW3, val);
358 POSTING_READ(DSPFW3);
359 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
360 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
361 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
362 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
363 I915_WRITE(FW_BLC_SELF, val);
364 POSTING_READ(FW_BLC_SELF);
365 } else if (IS_I915GM(dev_priv)) {
367 * FIXME can't find a bit like this for 915G, and
368 * and yet it does have the related watermark in
369 * FW_BLC_SELF. What's going on?
371 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
372 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
373 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
374 I915_WRITE(INSTPM, val);
375 POSTING_READ(INSTPM);
380 trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
382 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
383 enableddisabled(enable),
384 enableddisabled(was_enabled));
390 * intel_set_memory_cxsr - Configure CxSR state
391 * @dev_priv: i915 device
392 * @enable: Allow vs. disallow CxSR
394 * Allow or disallow the system to enter a special CxSR
395 * (C-state self refresh) state. What typically happens in CxSR mode
396 * is that several display FIFOs may get combined into a single larger
397 * FIFO for a particular plane (so called max FIFO mode) to allow the
398 * system to defer memory fetches longer, and the memory will enter
401 * Note that enabling CxSR does not guarantee that the system enter
402 * this special mode, nor does it guarantee that the system stays
403 * in that mode once entered. So this just allows/disallows the system
404 * to autonomously utilize the CxSR mode. Other factors such as core
405 * C-states will affect when/if the system actually enters/exits the
408 * Note that on VLV/CHV this actually only controls the max FIFO mode,
409 * and the system is free to enter/exit memory self refresh at any time
410 * even when the use of CxSR has been disallowed.
412 * While the system is actually in the CxSR/max FIFO mode, some plane
413 * control registers will not get latched on vblank. Thus in order to
414 * guarantee the system will respond to changes in the plane registers
415 * we must always disallow CxSR prior to making changes to those registers.
416 * Unfortunately the system will re-evaluate the CxSR conditions at
417 * frame start which happens after vblank start (which is when the plane
418 * registers would get latched), so we can't proceed with the plane update
419 * during the same frame where we disallowed CxSR.
421 * Certain platforms also have a deeper HPLL SR mode. Fortunately the
422 * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
423 * the hardware w.r.t. HPLL SR when writing to plane registers.
424 * Disallowing just CxSR is sufficient.
426 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
430 mutex_lock(&dev_priv->wm.wm_mutex);
431 ret = _intel_set_memory_cxsr(dev_priv, enable);
432 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
433 dev_priv->wm.vlv.cxsr = enable;
434 else if (IS_G4X(dev_priv))
435 dev_priv->wm.g4x.cxsr = enable;
436 mutex_unlock(&dev_priv->wm.wm_mutex);
442 * Latency for FIFO fetches is dependent on several factors:
443 * - memory configuration (speed, channels)
445 * - current MCH state
446 * It can be fairly high in some situations, so here we assume a fairly
447 * pessimal value. It's a tradeoff between extra memory fetches (if we
448 * set this value too high, the FIFO will fetch frequently to stay full)
449 * and power consumption (set it too low to save power and we might see
450 * FIFO underruns and display "flicker").
452 * A value of 5us seems to be a good balance; safe for very low end
453 * platforms but not overly aggressive on lower latency configs.
455 static const int pessimal_latency_ns = 5000;
457 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
458 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
460 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
462 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
463 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
464 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
465 enum pipe pipe = crtc->pipe;
466 int sprite0_start, sprite1_start;
469 uint32_t dsparb, dsparb2, dsparb3;
471 dsparb = I915_READ(DSPARB);
472 dsparb2 = I915_READ(DSPARB2);
473 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
474 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
477 dsparb = I915_READ(DSPARB);
478 dsparb2 = I915_READ(DSPARB2);
479 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
480 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
483 dsparb2 = I915_READ(DSPARB2);
484 dsparb3 = I915_READ(DSPARB3);
485 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
486 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
493 fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
494 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
495 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
496 fifo_state->plane[PLANE_CURSOR] = 63;
499 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
501 uint32_t dsparb = I915_READ(DSPARB);
504 size = dsparb & 0x7f;
506 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
508 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
509 plane ? "B" : "A", size);
514 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
516 uint32_t dsparb = I915_READ(DSPARB);
519 size = dsparb & 0x1ff;
521 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
522 size >>= 1; /* Convert to cachelines */
524 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
525 plane ? "B" : "A", size);
530 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
532 uint32_t dsparb = I915_READ(DSPARB);
535 size = dsparb & 0x7f;
536 size >>= 2; /* Convert to cachelines */
538 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
545 /* Pineview has different values for various configs */
546 static const struct intel_watermark_params pineview_display_wm = {
547 .fifo_size = PINEVIEW_DISPLAY_FIFO,
548 .max_wm = PINEVIEW_MAX_WM,
549 .default_wm = PINEVIEW_DFT_WM,
550 .guard_size = PINEVIEW_GUARD_WM,
551 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
553 static const struct intel_watermark_params pineview_display_hplloff_wm = {
554 .fifo_size = PINEVIEW_DISPLAY_FIFO,
555 .max_wm = PINEVIEW_MAX_WM,
556 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
557 .guard_size = PINEVIEW_GUARD_WM,
558 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
560 static const struct intel_watermark_params pineview_cursor_wm = {
561 .fifo_size = PINEVIEW_CURSOR_FIFO,
562 .max_wm = PINEVIEW_CURSOR_MAX_WM,
563 .default_wm = PINEVIEW_CURSOR_DFT_WM,
564 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
565 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
567 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
568 .fifo_size = PINEVIEW_CURSOR_FIFO,
569 .max_wm = PINEVIEW_CURSOR_MAX_WM,
570 .default_wm = PINEVIEW_CURSOR_DFT_WM,
571 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
572 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
574 static const struct intel_watermark_params i965_cursor_wm_info = {
575 .fifo_size = I965_CURSOR_FIFO,
576 .max_wm = I965_CURSOR_MAX_WM,
577 .default_wm = I965_CURSOR_DFT_WM,
579 .cacheline_size = I915_FIFO_LINE_SIZE,
581 static const struct intel_watermark_params i945_wm_info = {
582 .fifo_size = I945_FIFO_SIZE,
583 .max_wm = I915_MAX_WM,
586 .cacheline_size = I915_FIFO_LINE_SIZE,
588 static const struct intel_watermark_params i915_wm_info = {
589 .fifo_size = I915_FIFO_SIZE,
590 .max_wm = I915_MAX_WM,
593 .cacheline_size = I915_FIFO_LINE_SIZE,
595 static const struct intel_watermark_params i830_a_wm_info = {
596 .fifo_size = I855GM_FIFO_SIZE,
597 .max_wm = I915_MAX_WM,
600 .cacheline_size = I830_FIFO_LINE_SIZE,
602 static const struct intel_watermark_params i830_bc_wm_info = {
603 .fifo_size = I855GM_FIFO_SIZE,
604 .max_wm = I915_MAX_WM/2,
607 .cacheline_size = I830_FIFO_LINE_SIZE,
609 static const struct intel_watermark_params i845_wm_info = {
610 .fifo_size = I830_FIFO_SIZE,
611 .max_wm = I915_MAX_WM,
614 .cacheline_size = I830_FIFO_LINE_SIZE,
618 * intel_wm_method1 - Method 1 / "small buffer" watermark formula
619 * @pixel_rate: Pipe pixel rate in kHz
620 * @cpp: Plane bytes per pixel
621 * @latency: Memory wakeup latency in 0.1us units
623 * Compute the watermark using the method 1 or "small buffer"
624 * formula. The caller may additonally add extra cachelines
625 * to account for TLB misses and clock crossings.
627 * This method is concerned with the short term drain rate
628 * of the FIFO, ie. it does not account for blanking periods
629 * which would effectively reduce the average drain rate across
630 * a longer period. The name "small" refers to the fact the
631 * FIFO is relatively small compared to the amount of data
634 * The FIFO level vs. time graph might look something like:
638 * __---__---__ (- plane active, _ blanking)
641 * or perhaps like this:
644 * __----__----__ (- plane active, _ blanking)
648 * The watermark in bytes
650 static unsigned int intel_wm_method1(unsigned int pixel_rate,
652 unsigned int latency)
656 ret = (uint64_t) pixel_rate * cpp * latency;
657 ret = DIV_ROUND_UP_ULL(ret, 10000);
663 * intel_wm_method2 - Method 2 / "large buffer" watermark formula
664 * @pixel_rate: Pipe pixel rate in kHz
665 * @htotal: Pipe horizontal total
666 * @width: Plane width in pixels
667 * @cpp: Plane bytes per pixel
668 * @latency: Memory wakeup latency in 0.1us units
670 * Compute the watermark using the method 2 or "large buffer"
671 * formula. The caller may additonally add extra cachelines
672 * to account for TLB misses and clock crossings.
674 * This method is concerned with the long term drain rate
675 * of the FIFO, ie. it does account for blanking periods
676 * which effectively reduce the average drain rate across
677 * a longer period. The name "large" refers to the fact the
678 * FIFO is relatively large compared to the amount of data
681 * The FIFO level vs. time graph might look something like:
686 * __ --__--__--__--__--__--__ (- plane active, _ blanking)
690 * The watermark in bytes
692 static unsigned int intel_wm_method2(unsigned int pixel_rate,
696 unsigned int latency)
701 * FIXME remove once all users are computing
702 * watermarks in the correct place.
704 if (WARN_ON_ONCE(htotal == 0))
707 ret = (latency * pixel_rate) / (htotal * 10000);
708 ret = (ret + 1) * width * cpp;
714 * intel_calculate_wm - calculate watermark level
715 * @pixel_rate: pixel clock
716 * @wm: chip FIFO params
717 * @cpp: bytes per pixel
718 * @latency_ns: memory latency for the platform
720 * Calculate the watermark level (the level at which the display plane will
721 * start fetching from memory again). Each chip has a different display
722 * FIFO size and allocation, so the caller needs to figure that out and pass
723 * in the correct intel_watermark_params structure.
725 * As the pixel clock runs, the FIFO will be drained at a rate that depends
726 * on the pixel size. When it reaches the watermark level, it'll start
727 * fetching FIFO line sized based chunks from memory until the FIFO fills
728 * past the watermark point. If the FIFO drains completely, a FIFO underrun
729 * will occur, and a display engine hang could result.
731 static unsigned int intel_calculate_wm(int pixel_rate,
732 const struct intel_watermark_params *wm,
733 int fifo_size, int cpp,
734 unsigned int latency_ns)
736 int entries, wm_size;
739 * Note: we need to make sure we don't overflow for various clock &
741 * clocks go from a few thousand to several hundred thousand.
742 * latency is usually a few thousand
744 entries = intel_wm_method1(pixel_rate, cpp,
746 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
748 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
750 wm_size = fifo_size - entries;
751 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
753 /* Don't promote wm_size to unsigned... */
754 if (wm_size > wm->max_wm)
755 wm_size = wm->max_wm;
757 wm_size = wm->default_wm;
760 * Bspec seems to indicate that the value shouldn't be lower than
761 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
762 * Lets go for 8 which is the burst size since certain platforms
763 * already use a hardcoded 8 (which is what the spec says should be
772 static bool is_disabling(int old, int new, int threshold)
774 return old >= threshold && new < threshold;
777 static bool is_enabling(int old, int new, int threshold)
779 return old < threshold && new >= threshold;
782 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
784 return dev_priv->wm.max_level + 1;
787 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
788 const struct intel_plane_state *plane_state)
790 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
792 /* FIXME check the 'enable' instead */
793 if (!crtc_state->base.active)
797 * Treat cursor with fb as always visible since cursor updates
798 * can happen faster than the vrefresh rate, and the current
799 * watermark code doesn't handle that correctly. Cursor updates
800 * which set/clear the fb or change the cursor size are going
801 * to get throttled by intel_legacy_cursor_update() to work
802 * around this problem with the watermark code.
804 if (plane->id == PLANE_CURSOR)
805 return plane_state->base.fb != NULL;
807 return plane_state->base.visible;
810 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
812 struct intel_crtc *crtc, *enabled = NULL;
814 for_each_intel_crtc(&dev_priv->drm, crtc) {
815 if (intel_crtc_active(crtc)) {
825 static void pineview_update_wm(struct intel_crtc *unused_crtc)
827 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
828 struct intel_crtc *crtc;
829 const struct cxsr_latency *latency;
833 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
838 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
839 intel_set_memory_cxsr(dev_priv, false);
843 crtc = single_enabled_crtc(dev_priv);
845 const struct drm_display_mode *adjusted_mode =
846 &crtc->config->base.adjusted_mode;
847 const struct drm_framebuffer *fb =
848 crtc->base.primary->state->fb;
849 int cpp = fb->format->cpp[0];
850 int clock = adjusted_mode->crtc_clock;
853 wm = intel_calculate_wm(clock, &pineview_display_wm,
854 pineview_display_wm.fifo_size,
855 cpp, latency->display_sr);
856 reg = I915_READ(DSPFW1);
857 reg &= ~DSPFW_SR_MASK;
858 reg |= FW_WM(wm, SR);
859 I915_WRITE(DSPFW1, reg);
860 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
863 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
864 pineview_display_wm.fifo_size,
865 4, latency->cursor_sr);
866 reg = I915_READ(DSPFW3);
867 reg &= ~DSPFW_CURSOR_SR_MASK;
868 reg |= FW_WM(wm, CURSOR_SR);
869 I915_WRITE(DSPFW3, reg);
871 /* Display HPLL off SR */
872 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
873 pineview_display_hplloff_wm.fifo_size,
874 cpp, latency->display_hpll_disable);
875 reg = I915_READ(DSPFW3);
876 reg &= ~DSPFW_HPLL_SR_MASK;
877 reg |= FW_WM(wm, HPLL_SR);
878 I915_WRITE(DSPFW3, reg);
880 /* cursor HPLL off SR */
881 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
882 pineview_display_hplloff_wm.fifo_size,
883 4, latency->cursor_hpll_disable);
884 reg = I915_READ(DSPFW3);
885 reg &= ~DSPFW_HPLL_CURSOR_MASK;
886 reg |= FW_WM(wm, HPLL_CURSOR);
887 I915_WRITE(DSPFW3, reg);
888 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
890 intel_set_memory_cxsr(dev_priv, true);
892 intel_set_memory_cxsr(dev_priv, false);
897 * Documentation says:
898 * "If the line size is small, the TLB fetches can get in the way of the
899 * data fetches, causing some lag in the pixel data return which is not
900 * accounted for in the above formulas. The following adjustment only
901 * needs to be applied if eight whole lines fit in the buffer at once.
902 * The WM is adjusted upwards by the difference between the FIFO size
903 * and the size of 8 whole lines. This adjustment is always performed
904 * in the actual pixel depth regardless of whether FBC is enabled or not."
906 static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
908 int tlb_miss = fifo_size * 64 - width * cpp * 8;
910 return max(0, tlb_miss);
913 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
914 const struct g4x_wm_values *wm)
918 for_each_pipe(dev_priv, pipe)
919 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
922 FW_WM(wm->sr.plane, SR) |
923 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
924 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
925 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
927 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
928 FW_WM(wm->sr.fbc, FBC_SR) |
929 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
930 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
931 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
932 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
934 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
935 FW_WM(wm->sr.cursor, CURSOR_SR) |
936 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
937 FW_WM(wm->hpll.plane, HPLL_SR));
939 POSTING_READ(DSPFW1);
942 #define FW_WM_VLV(value, plane) \
943 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
945 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
946 const struct vlv_wm_values *wm)
950 for_each_pipe(dev_priv, pipe) {
951 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
953 I915_WRITE(VLV_DDL(pipe),
954 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
955 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
956 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
957 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
961 * Zero the (unused) WM1 watermarks, and also clear all the
962 * high order bits so that there are no out of bounds values
963 * present in the registers during the reprogramming.
965 I915_WRITE(DSPHOWM, 0);
966 I915_WRITE(DSPHOWM1, 0);
967 I915_WRITE(DSPFW4, 0);
968 I915_WRITE(DSPFW5, 0);
969 I915_WRITE(DSPFW6, 0);
972 FW_WM(wm->sr.plane, SR) |
973 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
974 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
975 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
977 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
978 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
979 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
981 FW_WM(wm->sr.cursor, CURSOR_SR));
983 if (IS_CHERRYVIEW(dev_priv)) {
984 I915_WRITE(DSPFW7_CHV,
985 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
986 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
987 I915_WRITE(DSPFW8_CHV,
988 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
989 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
990 I915_WRITE(DSPFW9_CHV,
991 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
992 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
994 FW_WM(wm->sr.plane >> 9, SR_HI) |
995 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
996 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
997 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
998 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
999 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1000 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1001 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1002 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1003 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1006 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1007 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1009 FW_WM(wm->sr.plane >> 9, SR_HI) |
1010 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1011 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1012 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1013 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1014 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1015 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1018 POSTING_READ(DSPFW1);
1023 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1025 /* all latencies in usec */
1026 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1027 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1028 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1030 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1033 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1036 * DSPCNTR[13] supposedly controls whether the
1037 * primary plane can use the FIFO space otherwise
1038 * reserved for the sprite plane. It's not 100% clear
1039 * what the actual FIFO size is, but it looks like we
1040 * can happily set both primary and sprite watermarks
1041 * up to 127 cachelines. So that would seem to mean
1042 * that either DSPCNTR[13] doesn't do anything, or that
1043 * the total FIFO is >= 256 cachelines in size. Either
1044 * way, we don't seem to have to worry about this
1045 * repartitioning as the maximum watermark value the
1046 * register can hold for each plane is lower than the
1047 * minimum FIFO size.
1053 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1055 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1057 MISSING_CASE(plane_id);
1062 static int g4x_fbc_fifo_size(int level)
1065 case G4X_WM_LEVEL_SR:
1067 case G4X_WM_LEVEL_HPLL:
1070 MISSING_CASE(level);
1075 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1076 const struct intel_plane_state *plane_state,
1079 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1080 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1081 const struct drm_display_mode *adjusted_mode =
1082 &crtc_state->base.adjusted_mode;
1083 int clock, htotal, cpp, width, wm;
1084 int latency = dev_priv->wm.pri_latency[level] * 10;
1089 if (!intel_wm_plane_visible(crtc_state, plane_state))
1093 * Not 100% sure which way ELK should go here as the
1094 * spec only says CL/CTG should assume 32bpp and BW
1095 * doesn't need to. But as these things followed the
1096 * mobile vs. desktop lines on gen3 as well, let's
1097 * assume ELK doesn't need this.
1099 * The spec also fails to list such a restriction for
1100 * the HPLL watermark, which seems a little strange.
1101 * Let's use 32bpp for the HPLL watermark as well.
1103 if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1104 level != G4X_WM_LEVEL_NORMAL)
1107 cpp = plane_state->base.fb->format->cpp[0];
1109 clock = adjusted_mode->crtc_clock;
1110 htotal = adjusted_mode->crtc_htotal;
1112 if (plane->id == PLANE_CURSOR)
1113 width = plane_state->base.crtc_w;
1115 width = drm_rect_width(&plane_state->base.dst);
1117 if (plane->id == PLANE_CURSOR) {
1118 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1119 } else if (plane->id == PLANE_PRIMARY &&
1120 level == G4X_WM_LEVEL_NORMAL) {
1121 wm = intel_wm_method1(clock, cpp, latency);
1125 small = intel_wm_method1(clock, cpp, latency);
1126 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1128 wm = min(small, large);
1131 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1134 wm = DIV_ROUND_UP(wm, 64) + 2;
1136 return min_t(int, wm, USHRT_MAX);
1139 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1140 int level, enum plane_id plane_id, u16 value)
1142 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1145 for (; level < intel_wm_num_levels(dev_priv); level++) {
1146 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1148 dirty |= raw->plane[plane_id] != value;
1149 raw->plane[plane_id] = value;
1155 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1156 int level, u16 value)
1158 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1161 /* NORMAL level doesn't have an FBC watermark */
1162 level = max(level, G4X_WM_LEVEL_SR);
1164 for (; level < intel_wm_num_levels(dev_priv); level++) {
1165 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1167 dirty |= raw->fbc != value;
1174 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1175 const struct intel_plane_state *pstate,
1178 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1179 const struct intel_plane_state *plane_state)
1181 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1182 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1183 enum plane_id plane_id = plane->id;
1187 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1188 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1189 if (plane_id == PLANE_PRIMARY)
1190 dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1194 for (level = 0; level < num_levels; level++) {
1195 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1198 wm = g4x_compute_wm(crtc_state, plane_state, level);
1199 max_wm = g4x_plane_fifo_size(plane_id, level);
1204 dirty |= raw->plane[plane_id] != wm;
1205 raw->plane[plane_id] = wm;
1207 if (plane_id != PLANE_PRIMARY ||
1208 level == G4X_WM_LEVEL_NORMAL)
1211 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1212 raw->plane[plane_id]);
1213 max_wm = g4x_fbc_fifo_size(level);
1216 * FBC wm is not mandatory as we
1217 * can always just disable its use.
1222 dirty |= raw->fbc != wm;
1226 /* mark watermarks as invalid */
1227 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1229 if (plane_id == PLANE_PRIMARY)
1230 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1234 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1236 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1237 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1238 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1240 if (plane_id == PLANE_PRIMARY)
1241 DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1242 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1243 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1249 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1250 enum plane_id plane_id, int level)
1252 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1254 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1257 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1260 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1262 if (level > dev_priv->wm.max_level)
1265 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1266 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1267 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1270 /* mark all levels starting from 'level' as invalid */
1271 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1272 struct g4x_wm_state *wm_state, int level)
1274 if (level <= G4X_WM_LEVEL_NORMAL) {
1275 enum plane_id plane_id;
1277 for_each_plane_id_on_crtc(crtc, plane_id)
1278 wm_state->wm.plane[plane_id] = USHRT_MAX;
1281 if (level <= G4X_WM_LEVEL_SR) {
1282 wm_state->cxsr = false;
1283 wm_state->sr.cursor = USHRT_MAX;
1284 wm_state->sr.plane = USHRT_MAX;
1285 wm_state->sr.fbc = USHRT_MAX;
1288 if (level <= G4X_WM_LEVEL_HPLL) {
1289 wm_state->hpll_en = false;
1290 wm_state->hpll.cursor = USHRT_MAX;
1291 wm_state->hpll.plane = USHRT_MAX;
1292 wm_state->hpll.fbc = USHRT_MAX;
1296 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1299 struct intel_atomic_state *state =
1300 to_intel_atomic_state(crtc_state->base.state);
1301 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1302 int num_active_planes = hweight32(crtc_state->active_planes &
1303 ~BIT(PLANE_CURSOR));
1304 const struct g4x_pipe_wm *raw;
1305 struct intel_plane_state *plane_state;
1306 struct intel_plane *plane;
1307 enum plane_id plane_id;
1309 unsigned int dirty = 0;
1311 for_each_intel_plane_in_state(state, plane, plane_state, i) {
1312 const struct intel_plane_state *old_plane_state =
1313 to_intel_plane_state(plane->base.state);
1315 if (plane_state->base.crtc != &crtc->base &&
1316 old_plane_state->base.crtc != &crtc->base)
1319 if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
1320 dirty |= BIT(plane->id);
1326 level = G4X_WM_LEVEL_NORMAL;
1327 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1330 raw = &crtc_state->wm.g4x.raw[level];
1331 for_each_plane_id_on_crtc(crtc, plane_id)
1332 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1334 level = G4X_WM_LEVEL_SR;
1336 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1339 raw = &crtc_state->wm.g4x.raw[level];
1340 wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1341 wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1342 wm_state->sr.fbc = raw->fbc;
1344 wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1346 level = G4X_WM_LEVEL_HPLL;
1348 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1351 raw = &crtc_state->wm.g4x.raw[level];
1352 wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1353 wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1354 wm_state->hpll.fbc = raw->fbc;
1356 wm_state->hpll_en = wm_state->cxsr;
1361 if (level == G4X_WM_LEVEL_NORMAL)
1364 /* invalidate the higher levels */
1365 g4x_invalidate_wms(crtc, wm_state, level);
1368 * Determine if the FBC watermark(s) can be used. IF
1369 * this isn't the case we prefer to disable the FBC
1370 ( watermark(s) rather than disable the SR/HPLL
1371 * level(s) entirely.
1373 wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1375 if (level >= G4X_WM_LEVEL_SR &&
1376 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1377 wm_state->fbc_en = false;
1378 else if (level >= G4X_WM_LEVEL_HPLL &&
1379 wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1380 wm_state->fbc_en = false;
1385 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1386 struct intel_crtc *crtc,
1387 struct intel_crtc_state *crtc_state)
1389 struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
1390 const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
1391 const struct g4x_wm_state *active = &crtc->wm.active.g4x;
1392 enum plane_id plane_id;
1394 intermediate->cxsr = optimal->cxsr && active->cxsr &&
1395 !crtc_state->disable_cxsr;
1396 intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1397 !crtc_state->disable_cxsr;
1398 intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1400 for_each_plane_id_on_crtc(crtc, plane_id) {
1401 intermediate->wm.plane[plane_id] =
1402 max(optimal->wm.plane[plane_id],
1403 active->wm.plane[plane_id]);
1405 WARN_ON(intermediate->wm.plane[plane_id] >
1406 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1409 intermediate->sr.plane = max(optimal->sr.plane,
1411 intermediate->sr.cursor = max(optimal->sr.cursor,
1413 intermediate->sr.fbc = max(optimal->sr.fbc,
1416 intermediate->hpll.plane = max(optimal->hpll.plane,
1417 active->hpll.plane);
1418 intermediate->hpll.cursor = max(optimal->hpll.cursor,
1419 active->hpll.cursor);
1420 intermediate->hpll.fbc = max(optimal->hpll.fbc,
1423 WARN_ON((intermediate->sr.plane >
1424 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1425 intermediate->sr.cursor >
1426 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1427 intermediate->cxsr);
1428 WARN_ON((intermediate->sr.plane >
1429 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1430 intermediate->sr.cursor >
1431 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1432 intermediate->hpll_en);
1434 WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1435 intermediate->fbc_en && intermediate->cxsr);
1436 WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1437 intermediate->fbc_en && intermediate->hpll_en);
1440 * If our intermediate WM are identical to the final WM, then we can
1441 * omit the post-vblank programming; only update if it's different.
1443 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1444 crtc_state->wm.need_postvbl_update = true;
1449 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1450 struct g4x_wm_values *wm)
1452 struct intel_crtc *crtc;
1453 int num_active_crtcs = 0;
1459 for_each_intel_crtc(&dev_priv->drm, crtc) {
1460 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1465 if (!wm_state->cxsr)
1467 if (!wm_state->hpll_en)
1468 wm->hpll_en = false;
1469 if (!wm_state->fbc_en)
1475 if (num_active_crtcs != 1) {
1477 wm->hpll_en = false;
1481 for_each_intel_crtc(&dev_priv->drm, crtc) {
1482 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1483 enum pipe pipe = crtc->pipe;
1485 wm->pipe[pipe] = wm_state->wm;
1486 if (crtc->active && wm->cxsr)
1487 wm->sr = wm_state->sr;
1488 if (crtc->active && wm->hpll_en)
1489 wm->hpll = wm_state->hpll;
1493 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1495 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1496 struct g4x_wm_values new_wm = {};
1498 g4x_merge_wm(dev_priv, &new_wm);
1500 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1503 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1504 _intel_set_memory_cxsr(dev_priv, false);
1506 g4x_write_wm_values(dev_priv, &new_wm);
1508 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1509 _intel_set_memory_cxsr(dev_priv, true);
1514 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1515 struct intel_crtc_state *crtc_state)
1517 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1518 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1520 mutex_lock(&dev_priv->wm.wm_mutex);
1521 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1522 g4x_program_watermarks(dev_priv);
1523 mutex_unlock(&dev_priv->wm.wm_mutex);
1526 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1527 struct intel_crtc_state *crtc_state)
1529 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1532 if (!crtc_state->wm.need_postvbl_update)
1535 mutex_lock(&dev_priv->wm.wm_mutex);
1536 intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1537 g4x_program_watermarks(dev_priv);
1538 mutex_unlock(&dev_priv->wm.wm_mutex);
1541 /* latency must be in 0.1us units. */
1542 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1543 unsigned int htotal,
1546 unsigned int latency)
1550 ret = intel_wm_method2(pixel_rate, htotal,
1551 width, cpp, latency);
1552 ret = DIV_ROUND_UP(ret, 64);
1557 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1559 /* all latencies in usec */
1560 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1562 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1564 if (IS_CHERRYVIEW(dev_priv)) {
1565 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1566 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1568 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1572 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1573 const struct intel_plane_state *plane_state,
1576 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1577 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1578 const struct drm_display_mode *adjusted_mode =
1579 &crtc_state->base.adjusted_mode;
1580 int clock, htotal, cpp, width, wm;
1582 if (dev_priv->wm.pri_latency[level] == 0)
1585 if (!intel_wm_plane_visible(crtc_state, plane_state))
1588 cpp = plane_state->base.fb->format->cpp[0];
1589 clock = adjusted_mode->crtc_clock;
1590 htotal = adjusted_mode->crtc_htotal;
1591 width = crtc_state->pipe_src_w;
1593 if (plane->id == PLANE_CURSOR) {
1595 * FIXME the formula gives values that are
1596 * too big for the cursor FIFO, and hence we
1597 * would never be able to use cursors. For
1598 * now just hardcode the watermark.
1602 wm = vlv_wm_method2(clock, htotal, width, cpp,
1603 dev_priv->wm.pri_latency[level] * 10);
1606 return min_t(int, wm, USHRT_MAX);
1609 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1611 return (active_planes & (BIT(PLANE_SPRITE0) |
1612 BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1615 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1618 const struct g4x_pipe_wm *raw =
1619 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1620 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1621 unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1622 int num_active_planes = hweight32(active_planes);
1623 const int fifo_size = 511;
1624 int fifo_extra, fifo_left = fifo_size;
1625 int sprite0_fifo_extra = 0;
1626 unsigned int total_rate;
1627 enum plane_id plane_id;
1630 * When enabling sprite0 after sprite1 has already been enabled
1631 * we tend to get an underrun unless sprite0 already has some
1632 * FIFO space allcoated. Hence we always allocate at least one
1633 * cacheline for sprite0 whenever sprite1 is enabled.
1635 * All other plane enable sequences appear immune to this problem.
1637 if (vlv_need_sprite0_fifo_workaround(active_planes))
1638 sprite0_fifo_extra = 1;
1640 total_rate = raw->plane[PLANE_PRIMARY] +
1641 raw->plane[PLANE_SPRITE0] +
1642 raw->plane[PLANE_SPRITE1] +
1645 if (total_rate > fifo_size)
1648 if (total_rate == 0)
1651 for_each_plane_id_on_crtc(crtc, plane_id) {
1654 if ((active_planes & BIT(plane_id)) == 0) {
1655 fifo_state->plane[plane_id] = 0;
1659 rate = raw->plane[plane_id];
1660 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1661 fifo_left -= fifo_state->plane[plane_id];
1664 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1665 fifo_left -= sprite0_fifo_extra;
1667 fifo_state->plane[PLANE_CURSOR] = 63;
1669 fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1671 /* spread the remainder evenly */
1672 for_each_plane_id_on_crtc(crtc, plane_id) {
1678 if ((active_planes & BIT(plane_id)) == 0)
1681 plane_extra = min(fifo_extra, fifo_left);
1682 fifo_state->plane[plane_id] += plane_extra;
1683 fifo_left -= plane_extra;
1686 WARN_ON(active_planes != 0 && fifo_left != 0);
1688 /* give it all to the first plane if none are active */
1689 if (active_planes == 0) {
1690 WARN_ON(fifo_left != fifo_size);
1691 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1697 /* mark all levels starting from 'level' as invalid */
1698 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1699 struct vlv_wm_state *wm_state, int level)
1701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1703 for (; level < intel_wm_num_levels(dev_priv); level++) {
1704 enum plane_id plane_id;
1706 for_each_plane_id_on_crtc(crtc, plane_id)
1707 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1709 wm_state->sr[level].cursor = USHRT_MAX;
1710 wm_state->sr[level].plane = USHRT_MAX;
1714 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1719 return fifo_size - wm;
1723 * Starting from 'level' set all higher
1724 * levels to 'value' in the "raw" watermarks.
1726 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1727 int level, enum plane_id plane_id, u16 value)
1729 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1730 int num_levels = intel_wm_num_levels(dev_priv);
1733 for (; level < num_levels; level++) {
1734 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1736 dirty |= raw->plane[plane_id] != value;
1737 raw->plane[plane_id] = value;
1743 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1744 const struct intel_plane_state *plane_state)
1746 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1747 enum plane_id plane_id = plane->id;
1748 int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1752 if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1753 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1757 for (level = 0; level < num_levels; level++) {
1758 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1759 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1760 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1765 dirty |= raw->plane[plane_id] != wm;
1766 raw->plane[plane_id] = wm;
1769 /* mark all higher levels as invalid */
1770 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1774 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1776 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1777 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1778 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1783 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1784 enum plane_id plane_id, int level)
1786 const struct g4x_pipe_wm *raw =
1787 &crtc_state->wm.vlv.raw[level];
1788 const struct vlv_fifo_state *fifo_state =
1789 &crtc_state->wm.vlv.fifo_state;
1791 return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1794 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1796 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1797 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1798 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1799 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1802 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1805 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1806 struct intel_atomic_state *state =
1807 to_intel_atomic_state(crtc_state->base.state);
1808 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1809 const struct vlv_fifo_state *fifo_state =
1810 &crtc_state->wm.vlv.fifo_state;
1811 int num_active_planes = hweight32(crtc_state->active_planes &
1812 ~BIT(PLANE_CURSOR));
1813 bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1814 struct intel_plane_state *plane_state;
1815 struct intel_plane *plane;
1816 enum plane_id plane_id;
1818 unsigned int dirty = 0;
1820 for_each_intel_plane_in_state(state, plane, plane_state, i) {
1821 const struct intel_plane_state *old_plane_state =
1822 to_intel_plane_state(plane->base.state);
1824 if (plane_state->base.crtc != &crtc->base &&
1825 old_plane_state->base.crtc != &crtc->base)
1828 if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
1829 dirty |= BIT(plane->id);
1833 * DSPARB registers may have been reset due to the
1834 * power well being turned off. Make sure we restore
1835 * them to a consistent state even if no primary/sprite
1836 * planes are initially active.
1839 crtc_state->fifo_changed = true;
1844 /* cursor changes don't warrant a FIFO recompute */
1845 if (dirty & ~BIT(PLANE_CURSOR)) {
1846 const struct intel_crtc_state *old_crtc_state =
1847 to_intel_crtc_state(crtc->base.state);
1848 const struct vlv_fifo_state *old_fifo_state =
1849 &old_crtc_state->wm.vlv.fifo_state;
1851 ret = vlv_compute_fifo(crtc_state);
1855 if (needs_modeset ||
1856 memcmp(old_fifo_state, fifo_state,
1857 sizeof(*fifo_state)) != 0)
1858 crtc_state->fifo_changed = true;
1861 /* initially allow all levels */
1862 wm_state->num_levels = intel_wm_num_levels(dev_priv);
1864 * Note that enabling cxsr with no primary/sprite planes
1865 * enabled can wedge the pipe. Hence we only allow cxsr
1866 * with exactly one enabled primary/sprite plane.
1868 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1870 for (level = 0; level < wm_state->num_levels; level++) {
1871 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1872 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1874 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1877 for_each_plane_id_on_crtc(crtc, plane_id) {
1878 wm_state->wm[level].plane[plane_id] =
1879 vlv_invert_wm_value(raw->plane[plane_id],
1880 fifo_state->plane[plane_id]);
1883 wm_state->sr[level].plane =
1884 vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1885 raw->plane[PLANE_SPRITE0],
1886 raw->plane[PLANE_SPRITE1]),
1889 wm_state->sr[level].cursor =
1890 vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1897 /* limit to only levels we can actually handle */
1898 wm_state->num_levels = level;
1900 /* invalidate the higher levels */
1901 vlv_invalidate_wms(crtc, wm_state, level);
1906 #define VLV_FIFO(plane, value) \
1907 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1909 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1910 struct intel_crtc_state *crtc_state)
1912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1914 const struct vlv_fifo_state *fifo_state =
1915 &crtc_state->wm.vlv.fifo_state;
1916 int sprite0_start, sprite1_start, fifo_size;
1918 if (!crtc_state->fifo_changed)
1921 sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1922 sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1923 fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1925 WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1926 WARN_ON(fifo_size != 511);
1928 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1931 * uncore.lock serves a double purpose here. It allows us to
1932 * use the less expensive I915_{READ,WRITE}_FW() functions, and
1933 * it protects the DSPARB registers from getting clobbered by
1934 * parallel updates from multiple pipes.
1936 * intel_pipe_update_start() has already disabled interrupts
1937 * for us, so a plain spin_lock() is sufficient here.
1939 spin_lock(&dev_priv->uncore.lock);
1941 switch (crtc->pipe) {
1942 uint32_t dsparb, dsparb2, dsparb3;
1944 dsparb = I915_READ_FW(DSPARB);
1945 dsparb2 = I915_READ_FW(DSPARB2);
1947 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1948 VLV_FIFO(SPRITEB, 0xff));
1949 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1950 VLV_FIFO(SPRITEB, sprite1_start));
1952 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1953 VLV_FIFO(SPRITEB_HI, 0x1));
1954 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1955 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1957 I915_WRITE_FW(DSPARB, dsparb);
1958 I915_WRITE_FW(DSPARB2, dsparb2);
1961 dsparb = I915_READ_FW(DSPARB);
1962 dsparb2 = I915_READ_FW(DSPARB2);
1964 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1965 VLV_FIFO(SPRITED, 0xff));
1966 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1967 VLV_FIFO(SPRITED, sprite1_start));
1969 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1970 VLV_FIFO(SPRITED_HI, 0xff));
1971 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1972 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1974 I915_WRITE_FW(DSPARB, dsparb);
1975 I915_WRITE_FW(DSPARB2, dsparb2);
1978 dsparb3 = I915_READ_FW(DSPARB3);
1979 dsparb2 = I915_READ_FW(DSPARB2);
1981 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1982 VLV_FIFO(SPRITEF, 0xff));
1983 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1984 VLV_FIFO(SPRITEF, sprite1_start));
1986 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1987 VLV_FIFO(SPRITEF_HI, 0xff));
1988 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1989 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1991 I915_WRITE_FW(DSPARB3, dsparb3);
1992 I915_WRITE_FW(DSPARB2, dsparb2);
1998 POSTING_READ_FW(DSPARB);
2000 spin_unlock(&dev_priv->uncore.lock);
2005 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2006 struct intel_crtc *crtc,
2007 struct intel_crtc_state *crtc_state)
2009 struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
2010 const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
2011 const struct vlv_wm_state *active = &crtc->wm.active.vlv;
2014 intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2015 intermediate->cxsr = optimal->cxsr && active->cxsr &&
2016 !crtc_state->disable_cxsr;
2018 for (level = 0; level < intermediate->num_levels; level++) {
2019 enum plane_id plane_id;
2021 for_each_plane_id_on_crtc(crtc, plane_id) {
2022 intermediate->wm[level].plane[plane_id] =
2023 min(optimal->wm[level].plane[plane_id],
2024 active->wm[level].plane[plane_id]);
2027 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2028 active->sr[level].plane);
2029 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2030 active->sr[level].cursor);
2033 vlv_invalidate_wms(crtc, intermediate, level);
2036 * If our intermediate WM are identical to the final WM, then we can
2037 * omit the post-vblank programming; only update if it's different.
2039 if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2040 crtc_state->wm.need_postvbl_update = true;
2045 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2046 struct vlv_wm_values *wm)
2048 struct intel_crtc *crtc;
2049 int num_active_crtcs = 0;
2051 wm->level = dev_priv->wm.max_level;
2054 for_each_intel_crtc(&dev_priv->drm, crtc) {
2055 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2060 if (!wm_state->cxsr)
2064 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2067 if (num_active_crtcs != 1)
2070 if (num_active_crtcs > 1)
2071 wm->level = VLV_WM_LEVEL_PM2;
2073 for_each_intel_crtc(&dev_priv->drm, crtc) {
2074 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2075 enum pipe pipe = crtc->pipe;
2077 wm->pipe[pipe] = wm_state->wm[wm->level];
2078 if (crtc->active && wm->cxsr)
2079 wm->sr = wm_state->sr[wm->level];
2081 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2082 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2083 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2084 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2088 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2090 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2091 struct vlv_wm_values new_wm = {};
2093 vlv_merge_wm(dev_priv, &new_wm);
2095 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2098 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2099 chv_set_memory_dvfs(dev_priv, false);
2101 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2102 chv_set_memory_pm5(dev_priv, false);
2104 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2105 _intel_set_memory_cxsr(dev_priv, false);
2107 vlv_write_wm_values(dev_priv, &new_wm);
2109 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2110 _intel_set_memory_cxsr(dev_priv, true);
2112 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2113 chv_set_memory_pm5(dev_priv, true);
2115 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2116 chv_set_memory_dvfs(dev_priv, true);
2121 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2122 struct intel_crtc_state *crtc_state)
2124 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2125 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2127 mutex_lock(&dev_priv->wm.wm_mutex);
2128 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2129 vlv_program_watermarks(dev_priv);
2130 mutex_unlock(&dev_priv->wm.wm_mutex);
2133 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2134 struct intel_crtc_state *crtc_state)
2136 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2139 if (!crtc_state->wm.need_postvbl_update)
2142 mutex_lock(&dev_priv->wm.wm_mutex);
2143 intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2144 vlv_program_watermarks(dev_priv);
2145 mutex_unlock(&dev_priv->wm.wm_mutex);
2148 static void i965_update_wm(struct intel_crtc *unused_crtc)
2150 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2151 struct intel_crtc *crtc;
2156 /* Calc sr entries for one plane configs */
2157 crtc = single_enabled_crtc(dev_priv);
2159 /* self-refresh has much higher latency */
2160 static const int sr_latency_ns = 12000;
2161 const struct drm_display_mode *adjusted_mode =
2162 &crtc->config->base.adjusted_mode;
2163 const struct drm_framebuffer *fb =
2164 crtc->base.primary->state->fb;
2165 int clock = adjusted_mode->crtc_clock;
2166 int htotal = adjusted_mode->crtc_htotal;
2167 int hdisplay = crtc->config->pipe_src_w;
2168 int cpp = fb->format->cpp[0];
2171 entries = intel_wm_method2(clock, htotal,
2172 hdisplay, cpp, sr_latency_ns / 100);
2173 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2174 srwm = I965_FIFO_SIZE - entries;
2178 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2181 entries = intel_wm_method2(clock, htotal,
2182 crtc->base.cursor->state->crtc_w, 4,
2183 sr_latency_ns / 100);
2184 entries = DIV_ROUND_UP(entries,
2185 i965_cursor_wm_info.cacheline_size) +
2186 i965_cursor_wm_info.guard_size;
2188 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2189 if (cursor_sr > i965_cursor_wm_info.max_wm)
2190 cursor_sr = i965_cursor_wm_info.max_wm;
2192 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2193 "cursor %d\n", srwm, cursor_sr);
2195 cxsr_enabled = true;
2197 cxsr_enabled = false;
2198 /* Turn off self refresh if both pipes are enabled */
2199 intel_set_memory_cxsr(dev_priv, false);
2202 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2205 /* 965 has limitations... */
2206 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2210 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2211 FW_WM(8, PLANEC_OLD));
2212 /* update cursor SR watermark */
2213 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2216 intel_set_memory_cxsr(dev_priv, true);
2221 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2223 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2224 const struct intel_watermark_params *wm_info;
2229 int planea_wm, planeb_wm;
2230 struct intel_crtc *crtc, *enabled = NULL;
2232 if (IS_I945GM(dev_priv))
2233 wm_info = &i945_wm_info;
2234 else if (!IS_GEN2(dev_priv))
2235 wm_info = &i915_wm_info;
2237 wm_info = &i830_a_wm_info;
2239 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
2240 crtc = intel_get_crtc_for_plane(dev_priv, 0);
2241 if (intel_crtc_active(crtc)) {
2242 const struct drm_display_mode *adjusted_mode =
2243 &crtc->config->base.adjusted_mode;
2244 const struct drm_framebuffer *fb =
2245 crtc->base.primary->state->fb;
2248 if (IS_GEN2(dev_priv))
2251 cpp = fb->format->cpp[0];
2253 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2254 wm_info, fifo_size, cpp,
2255 pessimal_latency_ns);
2258 planea_wm = fifo_size - wm_info->guard_size;
2259 if (planea_wm > (long)wm_info->max_wm)
2260 planea_wm = wm_info->max_wm;
2263 if (IS_GEN2(dev_priv))
2264 wm_info = &i830_bc_wm_info;
2266 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
2267 crtc = intel_get_crtc_for_plane(dev_priv, 1);
2268 if (intel_crtc_active(crtc)) {
2269 const struct drm_display_mode *adjusted_mode =
2270 &crtc->config->base.adjusted_mode;
2271 const struct drm_framebuffer *fb =
2272 crtc->base.primary->state->fb;
2275 if (IS_GEN2(dev_priv))
2278 cpp = fb->format->cpp[0];
2280 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2281 wm_info, fifo_size, cpp,
2282 pessimal_latency_ns);
2283 if (enabled == NULL)
2288 planeb_wm = fifo_size - wm_info->guard_size;
2289 if (planeb_wm > (long)wm_info->max_wm)
2290 planeb_wm = wm_info->max_wm;
2293 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2295 if (IS_I915GM(dev_priv) && enabled) {
2296 struct drm_i915_gem_object *obj;
2298 obj = intel_fb_obj(enabled->base.primary->state->fb);
2300 /* self-refresh seems busted with untiled */
2301 if (!i915_gem_object_is_tiled(obj))
2306 * Overlay gets an aggressive default since video jitter is bad.
2310 /* Play safe and disable self-refresh before adjusting watermarks. */
2311 intel_set_memory_cxsr(dev_priv, false);
2313 /* Calc sr entries for one plane configs */
2314 if (HAS_FW_BLC(dev_priv) && enabled) {
2315 /* self-refresh has much higher latency */
2316 static const int sr_latency_ns = 6000;
2317 const struct drm_display_mode *adjusted_mode =
2318 &enabled->config->base.adjusted_mode;
2319 const struct drm_framebuffer *fb =
2320 enabled->base.primary->state->fb;
2321 int clock = adjusted_mode->crtc_clock;
2322 int htotal = adjusted_mode->crtc_htotal;
2323 int hdisplay = enabled->config->pipe_src_w;
2327 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2330 cpp = fb->format->cpp[0];
2332 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2333 sr_latency_ns / 100);
2334 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2335 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2336 srwm = wm_info->fifo_size - entries;
2340 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2341 I915_WRITE(FW_BLC_SELF,
2342 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2344 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2347 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2348 planea_wm, planeb_wm, cwm, srwm);
2350 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2351 fwater_hi = (cwm & 0x1f);
2353 /* Set request length to 8 cachelines per fetch */
2354 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2355 fwater_hi = fwater_hi | (1 << 8);
2357 I915_WRITE(FW_BLC, fwater_lo);
2358 I915_WRITE(FW_BLC2, fwater_hi);
2361 intel_set_memory_cxsr(dev_priv, true);
2364 static void i845_update_wm(struct intel_crtc *unused_crtc)
2366 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2367 struct intel_crtc *crtc;
2368 const struct drm_display_mode *adjusted_mode;
2372 crtc = single_enabled_crtc(dev_priv);
2376 adjusted_mode = &crtc->config->base.adjusted_mode;
2377 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2379 dev_priv->display.get_fifo_size(dev_priv, 0),
2380 4, pessimal_latency_ns);
2381 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2382 fwater_lo |= (3<<8) | planea_wm;
2384 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2386 I915_WRITE(FW_BLC, fwater_lo);
2389 /* latency must be in 0.1us units. */
2390 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2392 unsigned int latency)
2396 ret = intel_wm_method1(pixel_rate, cpp, latency);
2397 ret = DIV_ROUND_UP(ret, 64) + 2;
2402 /* latency must be in 0.1us units. */
2403 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2404 unsigned int htotal,
2407 unsigned int latency)
2411 ret = intel_wm_method2(pixel_rate, htotal,
2412 width, cpp, latency);
2413 ret = DIV_ROUND_UP(ret, 64) + 2;
2418 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2422 * Neither of these should be possible since this function shouldn't be
2423 * called if the CRTC is off or the plane is invisible. But let's be
2424 * extra paranoid to avoid a potential divide-by-zero if we screw up
2425 * elsewhere in the driver.
2429 if (WARN_ON(!horiz_pixels))
2432 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2435 struct ilk_wm_maximums {
2443 * For both WM_PIPE and WM_LP.
2444 * mem_value must be in 0.1us units.
2446 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2447 const struct intel_plane_state *pstate,
2451 uint32_t method1, method2;
2454 if (!intel_wm_plane_visible(cstate, pstate))
2457 cpp = pstate->base.fb->format->cpp[0];
2459 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2464 method2 = ilk_wm_method2(cstate->pixel_rate,
2465 cstate->base.adjusted_mode.crtc_htotal,
2466 drm_rect_width(&pstate->base.dst),
2469 return min(method1, method2);
2473 * For both WM_PIPE and WM_LP.
2474 * mem_value must be in 0.1us units.
2476 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2477 const struct intel_plane_state *pstate,
2480 uint32_t method1, method2;
2483 if (!intel_wm_plane_visible(cstate, pstate))
2486 cpp = pstate->base.fb->format->cpp[0];
2488 method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2489 method2 = ilk_wm_method2(cstate->pixel_rate,
2490 cstate->base.adjusted_mode.crtc_htotal,
2491 drm_rect_width(&pstate->base.dst),
2493 return min(method1, method2);
2497 * For both WM_PIPE and WM_LP.
2498 * mem_value must be in 0.1us units.
2500 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2501 const struct intel_plane_state *pstate,
2506 if (!intel_wm_plane_visible(cstate, pstate))
2509 cpp = pstate->base.fb->format->cpp[0];
2511 return ilk_wm_method2(cstate->pixel_rate,
2512 cstate->base.adjusted_mode.crtc_htotal,
2513 pstate->base.crtc_w, cpp, mem_value);
2516 /* Only for WM_LP. */
2517 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2518 const struct intel_plane_state *pstate,
2523 if (!intel_wm_plane_visible(cstate, pstate))
2526 cpp = pstate->base.fb->format->cpp[0];
2528 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2532 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2534 if (INTEL_GEN(dev_priv) >= 8)
2536 else if (INTEL_GEN(dev_priv) >= 7)
2543 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2544 int level, bool is_sprite)
2546 if (INTEL_GEN(dev_priv) >= 8)
2547 /* BDW primary/sprite plane watermarks */
2548 return level == 0 ? 255 : 2047;
2549 else if (INTEL_GEN(dev_priv) >= 7)
2550 /* IVB/HSW primary/sprite plane watermarks */
2551 return level == 0 ? 127 : 1023;
2552 else if (!is_sprite)
2553 /* ILK/SNB primary plane watermarks */
2554 return level == 0 ? 127 : 511;
2556 /* ILK/SNB sprite plane watermarks */
2557 return level == 0 ? 63 : 255;
2561 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2563 if (INTEL_GEN(dev_priv) >= 7)
2564 return level == 0 ? 63 : 255;
2566 return level == 0 ? 31 : 63;
2569 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2571 if (INTEL_GEN(dev_priv) >= 8)
2577 /* Calculate the maximum primary/sprite plane watermark */
2578 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2580 const struct intel_wm_config *config,
2581 enum intel_ddb_partitioning ddb_partitioning,
2584 struct drm_i915_private *dev_priv = to_i915(dev);
2585 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2587 /* if sprites aren't enabled, sprites get nothing */
2588 if (is_sprite && !config->sprites_enabled)
2591 /* HSW allows LP1+ watermarks even with multiple pipes */
2592 if (level == 0 || config->num_pipes_active > 1) {
2593 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2596 * For some reason the non self refresh
2597 * FIFO size is only half of the self
2598 * refresh FIFO size on ILK/SNB.
2600 if (INTEL_GEN(dev_priv) <= 6)
2604 if (config->sprites_enabled) {
2605 /* level 0 is always calculated with 1:1 split */
2606 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2615 /* clamp to max that the registers can hold */
2616 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2619 /* Calculate the maximum cursor plane watermark */
2620 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2622 const struct intel_wm_config *config)
2624 /* HSW LP1+ watermarks w/ multiple pipes */
2625 if (level > 0 && config->num_pipes_active > 1)
2628 /* otherwise just report max that registers can hold */
2629 return ilk_cursor_wm_reg_max(to_i915(dev), level);
2632 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2634 const struct intel_wm_config *config,
2635 enum intel_ddb_partitioning ddb_partitioning,
2636 struct ilk_wm_maximums *max)
2638 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2639 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2640 max->cur = ilk_cursor_wm_max(dev, level, config);
2641 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2644 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2646 struct ilk_wm_maximums *max)
2648 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2649 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2650 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2651 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2654 static bool ilk_validate_wm_level(int level,
2655 const struct ilk_wm_maximums *max,
2656 struct intel_wm_level *result)
2660 /* already determined to be invalid? */
2661 if (!result->enable)
2664 result->enable = result->pri_val <= max->pri &&
2665 result->spr_val <= max->spr &&
2666 result->cur_val <= max->cur;
2668 ret = result->enable;
2671 * HACK until we can pre-compute everything,
2672 * and thus fail gracefully if LP0 watermarks
2675 if (level == 0 && !result->enable) {
2676 if (result->pri_val > max->pri)
2677 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2678 level, result->pri_val, max->pri);
2679 if (result->spr_val > max->spr)
2680 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2681 level, result->spr_val, max->spr);
2682 if (result->cur_val > max->cur)
2683 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2684 level, result->cur_val, max->cur);
2686 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2687 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2688 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2689 result->enable = true;
2695 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2696 const struct intel_crtc *intel_crtc,
2698 struct intel_crtc_state *cstate,
2699 struct intel_plane_state *pristate,
2700 struct intel_plane_state *sprstate,
2701 struct intel_plane_state *curstate,
2702 struct intel_wm_level *result)
2704 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2705 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2706 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2708 /* WM1+ latency values stored in 0.5us units */
2716 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2717 pri_latency, level);
2718 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2722 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2725 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2727 result->enable = true;
2731 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2733 const struct intel_atomic_state *intel_state =
2734 to_intel_atomic_state(cstate->base.state);
2735 const struct drm_display_mode *adjusted_mode =
2736 &cstate->base.adjusted_mode;
2737 u32 linetime, ips_linetime;
2739 if (!cstate->base.active)
2741 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2743 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2746 /* The WM are computed with base on how long it takes to fill a single
2747 * row at the given clock rate, multiplied by 8.
2749 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2750 adjusted_mode->crtc_clock);
2751 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2752 intel_state->cdclk.logical.cdclk);
2754 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2755 PIPE_WM_LINETIME_TIME(linetime);
2758 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2761 if (IS_GEN9(dev_priv)) {
2764 int level, max_level = ilk_wm_max_level(dev_priv);
2766 /* read the first set of memory latencies[0:3] */
2767 val = 0; /* data0 to be programmed to 0 for first set */
2768 mutex_lock(&dev_priv->rps.hw_lock);
2769 ret = sandybridge_pcode_read(dev_priv,
2770 GEN9_PCODE_READ_MEM_LATENCY,
2772 mutex_unlock(&dev_priv->rps.hw_lock);
2775 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2779 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2780 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2781 GEN9_MEM_LATENCY_LEVEL_MASK;
2782 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2783 GEN9_MEM_LATENCY_LEVEL_MASK;
2784 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2785 GEN9_MEM_LATENCY_LEVEL_MASK;
2787 /* read the second set of memory latencies[4:7] */
2788 val = 1; /* data0 to be programmed to 1 for second set */
2789 mutex_lock(&dev_priv->rps.hw_lock);
2790 ret = sandybridge_pcode_read(dev_priv,
2791 GEN9_PCODE_READ_MEM_LATENCY,
2793 mutex_unlock(&dev_priv->rps.hw_lock);
2795 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2799 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2800 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2801 GEN9_MEM_LATENCY_LEVEL_MASK;
2802 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2803 GEN9_MEM_LATENCY_LEVEL_MASK;
2804 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2805 GEN9_MEM_LATENCY_LEVEL_MASK;
2808 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2809 * need to be disabled. We make sure to sanitize the values out
2810 * of the punit to satisfy this requirement.
2812 for (level = 1; level <= max_level; level++) {
2813 if (wm[level] == 0) {
2814 for (i = level + 1; i <= max_level; i++)
2821 * WaWmMemoryReadLatency:skl,glk
2823 * punit doesn't take into account the read latency so we need
2824 * to add 2us to the various latency levels we retrieve from the
2825 * punit when level 0 response data us 0us.
2829 for (level = 1; level <= max_level; level++) {
2836 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2837 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2839 wm[0] = (sskpd >> 56) & 0xFF;
2841 wm[0] = sskpd & 0xF;
2842 wm[1] = (sskpd >> 4) & 0xFF;
2843 wm[2] = (sskpd >> 12) & 0xFF;
2844 wm[3] = (sskpd >> 20) & 0x1FF;
2845 wm[4] = (sskpd >> 32) & 0x1FF;
2846 } else if (INTEL_GEN(dev_priv) >= 6) {
2847 uint32_t sskpd = I915_READ(MCH_SSKPD);
2849 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2850 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2851 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2852 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2853 } else if (INTEL_GEN(dev_priv) >= 5) {
2854 uint32_t mltr = I915_READ(MLTR_ILK);
2856 /* ILK primary LP0 latency is 700 ns */
2858 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2859 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2863 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2866 /* ILK sprite LP0 latency is 1300 ns */
2867 if (IS_GEN5(dev_priv))
2871 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2874 /* ILK cursor LP0 latency is 1300 ns */
2875 if (IS_GEN5(dev_priv))
2878 /* WaDoubleCursorLP3Latency:ivb */
2879 if (IS_IVYBRIDGE(dev_priv))
2883 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2885 /* how many WM levels are we expecting */
2886 if (INTEL_GEN(dev_priv) >= 9)
2888 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2890 else if (INTEL_GEN(dev_priv) >= 6)
2896 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2898 const uint16_t wm[8])
2900 int level, max_level = ilk_wm_max_level(dev_priv);
2902 for (level = 0; level <= max_level; level++) {
2903 unsigned int latency = wm[level];
2906 DRM_ERROR("%s WM%d latency not provided\n",
2912 * - latencies are in us on gen9.
2913 * - before then, WM1+ latency values are in 0.5us units
2915 if (IS_GEN9(dev_priv))
2920 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2921 name, level, wm[level],
2922 latency / 10, latency % 10);
2926 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2927 uint16_t wm[5], uint16_t min)
2929 int level, max_level = ilk_wm_max_level(dev_priv);
2934 wm[0] = max(wm[0], min);
2935 for (level = 1; level <= max_level; level++)
2936 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2941 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2946 * The BIOS provided WM memory latency values are often
2947 * inadequate for high resolution displays. Adjust them.
2949 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2950 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2951 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2956 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2957 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2958 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2959 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2962 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2964 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2966 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2967 sizeof(dev_priv->wm.pri_latency));
2968 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2969 sizeof(dev_priv->wm.pri_latency));
2971 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2972 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2974 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2975 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2976 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2978 if (IS_GEN6(dev_priv))
2979 snb_wm_latency_quirk(dev_priv);
2982 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2984 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2985 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2988 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2989 struct intel_pipe_wm *pipe_wm)
2991 /* LP0 watermark maximums depend on this pipe alone */
2992 const struct intel_wm_config config = {
2993 .num_pipes_active = 1,
2994 .sprites_enabled = pipe_wm->sprites_enabled,
2995 .sprites_scaled = pipe_wm->sprites_scaled,
2997 struct ilk_wm_maximums max;
2999 /* LP0 watermarks always use 1/2 DDB partitioning */
3000 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3002 /* At least LP0 must be valid */
3003 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3004 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3011 /* Compute new watermarks for the pipe */
3012 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3014 struct drm_atomic_state *state = cstate->base.state;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3016 struct intel_pipe_wm *pipe_wm;
3017 struct drm_device *dev = state->dev;
3018 const struct drm_i915_private *dev_priv = to_i915(dev);
3019 struct intel_plane *intel_plane;
3020 struct intel_plane_state *pristate = NULL;
3021 struct intel_plane_state *sprstate = NULL;
3022 struct intel_plane_state *curstate = NULL;
3023 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3024 struct ilk_wm_maximums max;
3026 pipe_wm = &cstate->wm.ilk.optimal;
3028 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3029 struct intel_plane_state *ps;
3031 ps = intel_atomic_get_existing_plane_state(state,
3036 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3038 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3040 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3044 pipe_wm->pipe_enabled = cstate->base.active;
3046 pipe_wm->sprites_enabled = sprstate->base.visible;
3047 pipe_wm->sprites_scaled = sprstate->base.visible &&
3048 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3049 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3052 usable_level = max_level;
3054 /* ILK/SNB: LP2+ watermarks only w/o sprites */
3055 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3058 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3059 if (pipe_wm->sprites_scaled)
3062 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3063 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3065 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3066 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3068 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3069 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3071 if (!ilk_validate_pipe_wm(dev, pipe_wm))
3074 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3076 for (level = 1; level <= max_level; level++) {
3077 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3079 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3080 pristate, sprstate, curstate, wm);
3083 * Disable any watermark level that exceeds the
3084 * register maximums since such watermarks are
3087 if (level > usable_level)
3090 if (ilk_validate_wm_level(level, &max, wm))
3091 pipe_wm->wm[level] = *wm;
3093 usable_level = level;
3100 * Build a set of 'intermediate' watermark values that satisfy both the old
3101 * state and the new state. These can be programmed to the hardware
3104 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3105 struct intel_crtc *intel_crtc,
3106 struct intel_crtc_state *newstate)
3108 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3109 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
3110 int level, max_level = ilk_wm_max_level(to_i915(dev));
3113 * Start with the final, target watermarks, then combine with the
3114 * currently active watermarks to get values that are safe both before
3115 * and after the vblank.
3117 *a = newstate->wm.ilk.optimal;
3118 a->pipe_enabled |= b->pipe_enabled;
3119 a->sprites_enabled |= b->sprites_enabled;
3120 a->sprites_scaled |= b->sprites_scaled;
3122 for (level = 0; level <= max_level; level++) {
3123 struct intel_wm_level *a_wm = &a->wm[level];
3124 const struct intel_wm_level *b_wm = &b->wm[level];
3126 a_wm->enable &= b_wm->enable;
3127 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3128 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3129 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3130 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3134 * We need to make sure that these merged watermark values are
3135 * actually a valid configuration themselves. If they're not,
3136 * there's no safe way to transition from the old state to
3137 * the new state, so we need to fail the atomic transaction.
3139 if (!ilk_validate_pipe_wm(dev, a))
3143 * If our intermediate WM are identical to the final WM, then we can
3144 * omit the post-vblank programming; only update if it's different.
3146 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3147 newstate->wm.need_postvbl_update = true;
3153 * Merge the watermarks from all active pipes for a specific level.
3155 static void ilk_merge_wm_level(struct drm_device *dev,
3157 struct intel_wm_level *ret_wm)
3159 const struct intel_crtc *intel_crtc;
3161 ret_wm->enable = true;
3163 for_each_intel_crtc(dev, intel_crtc) {
3164 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3165 const struct intel_wm_level *wm = &active->wm[level];
3167 if (!active->pipe_enabled)
3171 * The watermark values may have been used in the past,
3172 * so we must maintain them in the registers for some
3173 * time even if the level is now disabled.
3176 ret_wm->enable = false;
3178 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3179 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3180 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3181 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3186 * Merge all low power watermarks for all active pipes.
3188 static void ilk_wm_merge(struct drm_device *dev,
3189 const struct intel_wm_config *config,
3190 const struct ilk_wm_maximums *max,
3191 struct intel_pipe_wm *merged)
3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 int level, max_level = ilk_wm_max_level(dev_priv);
3195 int last_enabled_level = max_level;
3197 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3198 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3199 config->num_pipes_active > 1)
3200 last_enabled_level = 0;
3202 /* ILK: FBC WM must be disabled always */
3203 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3205 /* merge each WM1+ level */
3206 for (level = 1; level <= max_level; level++) {
3207 struct intel_wm_level *wm = &merged->wm[level];
3209 ilk_merge_wm_level(dev, level, wm);
3211 if (level > last_enabled_level)
3213 else if (!ilk_validate_wm_level(level, max, wm))
3214 /* make sure all following levels get disabled */
3215 last_enabled_level = level - 1;
3218 * The spec says it is preferred to disable
3219 * FBC WMs instead of disabling a WM level.
3221 if (wm->fbc_val > max->fbc) {
3223 merged->fbc_wm_enabled = false;
3228 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3230 * FIXME this is racy. FBC might get enabled later.
3231 * What we should check here is whether FBC can be
3232 * enabled sometime later.
3234 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3235 intel_fbc_is_active(dev_priv)) {
3236 for (level = 2; level <= max_level; level++) {
3237 struct intel_wm_level *wm = &merged->wm[level];
3244 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3246 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3247 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3250 /* The value we need to program into the WM_LPx latency field */
3251 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3253 struct drm_i915_private *dev_priv = to_i915(dev);
3255 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3258 return dev_priv->wm.pri_latency[level];
3261 static void ilk_compute_wm_results(struct drm_device *dev,
3262 const struct intel_pipe_wm *merged,
3263 enum intel_ddb_partitioning partitioning,
3264 struct ilk_wm_values *results)
3266 struct drm_i915_private *dev_priv = to_i915(dev);
3267 struct intel_crtc *intel_crtc;
3270 results->enable_fbc_wm = merged->fbc_wm_enabled;
3271 results->partitioning = partitioning;
3273 /* LP1+ register values */
3274 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3275 const struct intel_wm_level *r;
3277 level = ilk_wm_lp_to_level(wm_lp, merged);
3279 r = &merged->wm[level];
3282 * Maintain the watermark values even if the level is
3283 * disabled. Doing otherwise could cause underruns.
3285 results->wm_lp[wm_lp - 1] =
3286 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3287 (r->pri_val << WM1_LP_SR_SHIFT) |
3291 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3293 if (INTEL_GEN(dev_priv) >= 8)
3294 results->wm_lp[wm_lp - 1] |=
3295 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3297 results->wm_lp[wm_lp - 1] |=
3298 r->fbc_val << WM1_LP_FBC_SHIFT;
3301 * Always set WM1S_LP_EN when spr_val != 0, even if the
3302 * level is disabled. Doing otherwise could cause underruns.
3304 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3305 WARN_ON(wm_lp != 1);
3306 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3308 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3311 /* LP0 register values */
3312 for_each_intel_crtc(dev, intel_crtc) {
3313 enum pipe pipe = intel_crtc->pipe;
3314 const struct intel_wm_level *r =
3315 &intel_crtc->wm.active.ilk.wm[0];
3317 if (WARN_ON(!r->enable))
3320 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3322 results->wm_pipe[pipe] =
3323 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3324 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3329 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3330 * case both are at the same level. Prefer r1 in case they're the same. */
3331 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3332 struct intel_pipe_wm *r1,
3333 struct intel_pipe_wm *r2)
3335 int level, max_level = ilk_wm_max_level(to_i915(dev));
3336 int level1 = 0, level2 = 0;
3338 for (level = 1; level <= max_level; level++) {
3339 if (r1->wm[level].enable)
3341 if (r2->wm[level].enable)
3345 if (level1 == level2) {
3346 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3350 } else if (level1 > level2) {
3357 /* dirty bits used to track which watermarks need changes */
3358 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3359 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3360 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3361 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3362 #define WM_DIRTY_FBC (1 << 24)
3363 #define WM_DIRTY_DDB (1 << 25)
3365 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3366 const struct ilk_wm_values *old,
3367 const struct ilk_wm_values *new)
3369 unsigned int dirty = 0;
3373 for_each_pipe(dev_priv, pipe) {
3374 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3375 dirty |= WM_DIRTY_LINETIME(pipe);
3376 /* Must disable LP1+ watermarks too */
3377 dirty |= WM_DIRTY_LP_ALL;
3380 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3381 dirty |= WM_DIRTY_PIPE(pipe);
3382 /* Must disable LP1+ watermarks too */
3383 dirty |= WM_DIRTY_LP_ALL;
3387 if (old->enable_fbc_wm != new->enable_fbc_wm) {
3388 dirty |= WM_DIRTY_FBC;
3389 /* Must disable LP1+ watermarks too */
3390 dirty |= WM_DIRTY_LP_ALL;
3393 if (old->partitioning != new->partitioning) {
3394 dirty |= WM_DIRTY_DDB;
3395 /* Must disable LP1+ watermarks too */
3396 dirty |= WM_DIRTY_LP_ALL;
3399 /* LP1+ watermarks already deemed dirty, no need to continue */
3400 if (dirty & WM_DIRTY_LP_ALL)
3403 /* Find the lowest numbered LP1+ watermark in need of an update... */
3404 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3405 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3406 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3410 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3411 for (; wm_lp <= 3; wm_lp++)
3412 dirty |= WM_DIRTY_LP(wm_lp);
3417 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3420 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3421 bool changed = false;
3423 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3424 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3425 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3428 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3429 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3430 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3433 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3434 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3435 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3440 * Don't touch WM1S_LP_EN here.
3441 * Doing so could cause underruns.
3448 * The spec says we shouldn't write when we don't need, because every write
3449 * causes WMs to be re-evaluated, expending some power.
3451 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3452 struct ilk_wm_values *results)
3454 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3458 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3462 _ilk_disable_lp_wm(dev_priv, dirty);
3464 if (dirty & WM_DIRTY_PIPE(PIPE_A))
3465 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3466 if (dirty & WM_DIRTY_PIPE(PIPE_B))
3467 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3468 if (dirty & WM_DIRTY_PIPE(PIPE_C))
3469 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3471 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3472 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3473 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3474 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3475 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3476 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3478 if (dirty & WM_DIRTY_DDB) {
3479 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3480 val = I915_READ(WM_MISC);
3481 if (results->partitioning == INTEL_DDB_PART_1_2)
3482 val &= ~WM_MISC_DATA_PARTITION_5_6;
3484 val |= WM_MISC_DATA_PARTITION_5_6;
3485 I915_WRITE(WM_MISC, val);
3487 val = I915_READ(DISP_ARB_CTL2);
3488 if (results->partitioning == INTEL_DDB_PART_1_2)
3489 val &= ~DISP_DATA_PARTITION_5_6;
3491 val |= DISP_DATA_PARTITION_5_6;
3492 I915_WRITE(DISP_ARB_CTL2, val);
3496 if (dirty & WM_DIRTY_FBC) {
3497 val = I915_READ(DISP_ARB_CTL);
3498 if (results->enable_fbc_wm)
3499 val &= ~DISP_FBC_WM_DIS;
3501 val |= DISP_FBC_WM_DIS;
3502 I915_WRITE(DISP_ARB_CTL, val);
3505 if (dirty & WM_DIRTY_LP(1) &&
3506 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3507 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3509 if (INTEL_GEN(dev_priv) >= 7) {
3510 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3511 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3512 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3513 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3516 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3517 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3518 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3519 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3520 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3521 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3523 dev_priv->wm.hw = *results;
3526 bool ilk_disable_lp_wm(struct drm_device *dev)
3528 struct drm_i915_private *dev_priv = to_i915(dev);
3530 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3533 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
3536 * FIXME: We still don't have the proper code detect if we need to apply the WA,
3537 * so assume we'll always need it in order to avoid underruns.
3539 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3541 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3543 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3550 intel_has_sagv(struct drm_i915_private *dev_priv)
3552 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
3555 if (IS_SKYLAKE(dev_priv) &&
3556 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3563 * SAGV dynamically adjusts the system agent voltage and clock frequencies
3564 * depending on power and performance requirements. The display engine access
3565 * to system memory is blocked during the adjustment time. Because of the
3566 * blocking time, having this enabled can cause full system hangs and/or pipe
3567 * underruns if we don't meet all of the following requirements:
3569 * - <= 1 pipe enabled
3570 * - All planes can enable watermarks for latencies >= SAGV engine block time
3571 * - We're not using an interlaced display configuration
3574 intel_enable_sagv(struct drm_i915_private *dev_priv)
3578 if (!intel_has_sagv(dev_priv))
3581 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3584 DRM_DEBUG_KMS("Enabling the SAGV\n");
3585 mutex_lock(&dev_priv->rps.hw_lock);
3587 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3590 /* We don't need to wait for the SAGV when enabling */
3591 mutex_unlock(&dev_priv->rps.hw_lock);
3594 * Some skl systems, pre-release machines in particular,
3595 * don't actually have an SAGV.
3597 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3598 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3599 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3601 } else if (ret < 0) {
3602 DRM_ERROR("Failed to enable the SAGV\n");
3606 dev_priv->sagv_status = I915_SAGV_ENABLED;
3611 intel_disable_sagv(struct drm_i915_private *dev_priv)
3615 if (!intel_has_sagv(dev_priv))
3618 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3621 DRM_DEBUG_KMS("Disabling the SAGV\n");
3622 mutex_lock(&dev_priv->rps.hw_lock);
3624 /* bspec says to keep retrying for at least 1 ms */
3625 ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3627 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3629 mutex_unlock(&dev_priv->rps.hw_lock);
3632 * Some skl systems, pre-release machines in particular,
3633 * don't actually have an SAGV.
3635 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3636 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3637 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3639 } else if (ret < 0) {
3640 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3644 dev_priv->sagv_status = I915_SAGV_DISABLED;
3648 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3650 struct drm_device *dev = state->dev;
3651 struct drm_i915_private *dev_priv = to_i915(dev);
3652 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3653 struct intel_crtc *crtc;
3654 struct intel_plane *plane;
3655 struct intel_crtc_state *cstate;
3659 if (!intel_has_sagv(dev_priv))
3663 * SKL workaround: bspec recommends we disable the SAGV when we have
3664 * more then one pipe enabled
3666 * If there are no active CRTCs, no additional checks need be performed
3668 if (hweight32(intel_state->active_crtcs) == 0)
3670 else if (hweight32(intel_state->active_crtcs) > 1)
3673 /* Since we're now guaranteed to only have one active CRTC... */
3674 pipe = ffs(intel_state->active_crtcs) - 1;
3675 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3676 cstate = to_intel_crtc_state(crtc->base.state);
3678 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3681 for_each_intel_plane_on_crtc(dev, crtc, plane) {
3682 struct skl_plane_wm *wm =
3683 &cstate->wm.skl.optimal.planes[plane->id];
3685 /* Skip this plane if it's not enabled */
3686 if (!wm->wm[0].plane_en)
3689 /* Find the highest enabled wm level for this plane */
3690 for (level = ilk_wm_max_level(dev_priv);
3691 !wm->wm[level].plane_en; --level)
3694 latency = dev_priv->wm.skl_latency[level];
3696 if (skl_needs_memory_bw_wa(intel_state) &&
3697 plane->base.state->fb->modifier ==
3698 I915_FORMAT_MOD_X_TILED)
3702 * If any of the planes on this pipe don't enable wm levels
3703 * that incur memory latencies higher then 30µs we can't enable
3706 if (latency < SKL_SAGV_BLOCK_TIME)
3714 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3715 const struct intel_crtc_state *cstate,
3716 struct skl_ddb_entry *alloc, /* out */
3717 int *num_active /* out */)
3719 struct drm_atomic_state *state = cstate->base.state;
3720 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3721 struct drm_i915_private *dev_priv = to_i915(dev);
3722 struct drm_crtc *for_crtc = cstate->base.crtc;
3723 unsigned int pipe_size, ddb_size;
3724 int nth_active_pipe;
3726 if (WARN_ON(!state) || !cstate->base.active) {
3729 *num_active = hweight32(dev_priv->active_crtcs);
3733 if (intel_state->active_pipe_changes)
3734 *num_active = hweight32(intel_state->active_crtcs);
3736 *num_active = hweight32(dev_priv->active_crtcs);
3738 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3739 WARN_ON(ddb_size == 0);
3741 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3744 * If the state doesn't change the active CRTC's, then there's
3745 * no need to recalculate; the existing pipe allocation limits
3746 * should remain unchanged. Note that we're safe from racing
3747 * commits since any racing commit that changes the active CRTC
3748 * list would need to grab _all_ crtc locks, including the one
3749 * we currently hold.
3751 if (!intel_state->active_pipe_changes) {
3753 * alloc may be cleared by clear_intel_crtc_state,
3754 * copy from old state to be sure
3756 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3760 nth_active_pipe = hweight32(intel_state->active_crtcs &
3761 (drm_crtc_mask(for_crtc) - 1));
3762 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3763 alloc->start = nth_active_pipe * ddb_size / *num_active;
3764 alloc->end = alloc->start + pipe_size;
3767 static unsigned int skl_cursor_allocation(int num_active)
3769 if (num_active == 1)
3775 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3777 entry->start = reg & 0x3ff;
3778 entry->end = (reg >> 16) & 0x3ff;
3783 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3784 struct skl_ddb_allocation *ddb /* out */)
3786 struct intel_crtc *crtc;
3788 memset(ddb, 0, sizeof(*ddb));
3790 for_each_intel_crtc(&dev_priv->drm, crtc) {
3791 enum intel_display_power_domain power_domain;
3792 enum plane_id plane_id;
3793 enum pipe pipe = crtc->pipe;
3795 power_domain = POWER_DOMAIN_PIPE(pipe);
3796 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3799 for_each_plane_id_on_crtc(crtc, plane_id) {
3802 if (plane_id != PLANE_CURSOR)
3803 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3805 val = I915_READ(CUR_BUF_CFG(pipe));
3807 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3810 intel_display_power_put(dev_priv, power_domain);
3815 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3816 * The bspec defines downscale amount as:
3819 * Horizontal down scale amount = maximum[1, Horizontal source size /
3820 * Horizontal destination size]
3821 * Vertical down scale amount = maximum[1, Vertical source size /
3822 * Vertical destination size]
3823 * Total down scale amount = Horizontal down scale amount *
3824 * Vertical down scale amount
3827 * Return value is provided in 16.16 fixed point form to retain fractional part.
3828 * Caller should take care of dividing & rounding off the value.
3830 static uint_fixed_16_16_t
3831 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3832 const struct intel_plane_state *pstate)
3834 struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3835 uint32_t src_w, src_h, dst_w, dst_h;
3836 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3837 uint_fixed_16_16_t downscale_h, downscale_w;
3839 if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3840 return u32_to_fixed_16_16(0);
3842 /* n.b., src is 16.16 fixed point, dst is whole integer */
3843 if (plane->id == PLANE_CURSOR) {
3845 * Cursors only support 0/180 degree rotation,
3846 * hence no need to account for rotation here.
3848 src_w = pstate->base.src_w >> 16;
3849 src_h = pstate->base.src_h >> 16;
3850 dst_w = pstate->base.crtc_w;
3851 dst_h = pstate->base.crtc_h;
3854 * Src coordinates are already rotated by 270 degrees for
3855 * the 90/270 degree plane rotation cases (to match the
3856 * GTT mapping), hence no need to account for rotation here.
3858 src_w = drm_rect_width(&pstate->base.src) >> 16;
3859 src_h = drm_rect_height(&pstate->base.src) >> 16;
3860 dst_w = drm_rect_width(&pstate->base.dst);
3861 dst_h = drm_rect_height(&pstate->base.dst);
3864 fp_w_ratio = fixed_16_16_div(src_w, dst_w);
3865 fp_h_ratio = fixed_16_16_div(src_h, dst_h);
3866 downscale_w = max_fixed_16_16(fp_w_ratio, u32_to_fixed_16_16(1));
3867 downscale_h = max_fixed_16_16(fp_h_ratio, u32_to_fixed_16_16(1));
3869 return mul_fixed16(downscale_w, downscale_h);
3872 static uint_fixed_16_16_t
3873 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
3875 uint_fixed_16_16_t pipe_downscale = u32_to_fixed_16_16(1);
3877 if (!crtc_state->base.enable)
3878 return pipe_downscale;
3880 if (crtc_state->pch_pfit.enabled) {
3881 uint32_t src_w, src_h, dst_w, dst_h;
3882 uint32_t pfit_size = crtc_state->pch_pfit.size;
3883 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3884 uint_fixed_16_16_t downscale_h, downscale_w;
3886 src_w = crtc_state->pipe_src_w;
3887 src_h = crtc_state->pipe_src_h;
3888 dst_w = pfit_size >> 16;
3889 dst_h = pfit_size & 0xffff;
3891 if (!dst_w || !dst_h)
3892 return pipe_downscale;
3894 fp_w_ratio = fixed_16_16_div(src_w, dst_w);
3895 fp_h_ratio = fixed_16_16_div(src_h, dst_h);
3896 downscale_w = max_fixed_16_16(fp_w_ratio, u32_to_fixed_16_16(1));
3897 downscale_h = max_fixed_16_16(fp_h_ratio, u32_to_fixed_16_16(1));
3899 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
3902 return pipe_downscale;
3905 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
3906 struct intel_crtc_state *cstate)
3908 struct drm_crtc_state *crtc_state = &cstate->base;
3909 struct drm_atomic_state *state = crtc_state->state;
3910 struct drm_plane *plane;
3911 const struct drm_plane_state *pstate;
3912 struct intel_plane_state *intel_pstate;
3913 int crtc_clock, dotclk;
3914 uint32_t pipe_max_pixel_rate;
3915 uint_fixed_16_16_t pipe_downscale;
3916 uint_fixed_16_16_t max_downscale = u32_to_fixed_16_16(1);
3918 if (!cstate->base.enable)
3921 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
3922 uint_fixed_16_16_t plane_downscale;
3923 uint_fixed_16_16_t fp_9_div_8 = fixed_16_16_div(9, 8);
3926 if (!intel_wm_plane_visible(cstate,
3927 to_intel_plane_state(pstate)))
3930 if (WARN_ON(!pstate->fb))
3933 intel_pstate = to_intel_plane_state(pstate);
3934 plane_downscale = skl_plane_downscale_amount(cstate,
3936 bpp = pstate->fb->format->cpp[0] * 8;
3938 plane_downscale = mul_fixed16(plane_downscale,
3941 max_downscale = max_fixed_16_16(plane_downscale, max_downscale);
3943 pipe_downscale = skl_pipe_downscale_amount(cstate);
3945 pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
3947 crtc_clock = crtc_state->adjusted_mode.crtc_clock;
3948 dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
3950 if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
3953 pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
3955 if (pipe_max_pixel_rate < crtc_clock) {
3956 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3964 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3965 const struct drm_plane_state *pstate,
3968 struct intel_plane *plane = to_intel_plane(pstate->plane);
3969 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3971 uint32_t width = 0, height = 0;
3972 struct drm_framebuffer *fb;
3974 uint_fixed_16_16_t down_scale_amount;
3976 if (!intel_pstate->base.visible)
3980 format = fb->format->format;
3982 if (plane->id == PLANE_CURSOR)
3984 if (y && format != DRM_FORMAT_NV12)
3988 * Src coordinates are already rotated by 270 degrees for
3989 * the 90/270 degree plane rotation cases (to match the
3990 * GTT mapping), hence no need to account for rotation here.
3992 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3993 height = drm_rect_height(&intel_pstate->base.src) >> 16;
3995 /* for planar format */
3996 if (format == DRM_FORMAT_NV12) {
3997 if (y) /* y-plane data rate */
3998 data_rate = width * height *
4000 else /* uv-plane data rate */
4001 data_rate = (width / 2) * (height / 2) *
4004 /* for packed formats */
4005 data_rate = width * height * fb->format->cpp[0];
4008 down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4010 return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4014 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4015 * a 8192x4096@32bpp framebuffer:
4016 * 3 * 4096 * 8192 * 4 < 2^32
4019 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4020 unsigned *plane_data_rate,
4021 unsigned *plane_y_data_rate)
4023 struct drm_crtc_state *cstate = &intel_cstate->base;
4024 struct drm_atomic_state *state = cstate->state;
4025 struct drm_plane *plane;
4026 const struct drm_plane_state *pstate;
4027 unsigned int total_data_rate = 0;
4029 if (WARN_ON(!state))
4032 /* Calculate and cache data rate for each plane */
4033 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4034 enum plane_id plane_id = to_intel_plane(plane)->id;
4038 rate = skl_plane_relative_data_rate(intel_cstate,
4040 plane_data_rate[plane_id] = rate;
4042 total_data_rate += rate;
4045 rate = skl_plane_relative_data_rate(intel_cstate,
4047 plane_y_data_rate[plane_id] = rate;
4049 total_data_rate += rate;
4052 return total_data_rate;
4056 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4059 struct drm_framebuffer *fb = pstate->fb;
4060 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4061 uint32_t src_w, src_h;
4062 uint32_t min_scanlines = 8;
4068 /* For packed formats, no y-plane, return 0 */
4069 if (y && fb->format->format != DRM_FORMAT_NV12)
4072 /* For Non Y-tile return 8-blocks */
4073 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4074 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
4078 * Src coordinates are already rotated by 270 degrees for
4079 * the 90/270 degree plane rotation cases (to match the
4080 * GTT mapping), hence no need to account for rotation here.
4082 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4083 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4085 /* Halve UV plane width and height for NV12 */
4086 if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4091 if (fb->format->format == DRM_FORMAT_NV12 && !y)
4092 plane_bpp = fb->format->cpp[1];
4094 plane_bpp = fb->format->cpp[0];
4096 if (drm_rotation_90_or_270(pstate->rotation)) {
4097 switch (plane_bpp) {
4111 WARN(1, "Unsupported pixel depth %u for rotation",
4117 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4121 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4122 uint16_t *minimum, uint16_t *y_minimum)
4124 const struct drm_plane_state *pstate;
4125 struct drm_plane *plane;
4127 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4128 enum plane_id plane_id = to_intel_plane(plane)->id;
4130 if (plane_id == PLANE_CURSOR)
4133 if (!pstate->visible)
4136 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4137 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4140 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4144 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4145 struct skl_ddb_allocation *ddb /* out */)
4147 struct drm_atomic_state *state = cstate->base.state;
4148 struct drm_crtc *crtc = cstate->base.crtc;
4149 struct drm_device *dev = crtc->dev;
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151 enum pipe pipe = intel_crtc->pipe;
4152 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4153 uint16_t alloc_size, start;
4154 uint16_t minimum[I915_MAX_PLANES] = {};
4155 uint16_t y_minimum[I915_MAX_PLANES] = {};
4156 unsigned int total_data_rate;
4157 enum plane_id plane_id;
4159 unsigned plane_data_rate[I915_MAX_PLANES] = {};
4160 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4161 uint16_t total_min_blocks = 0;
4163 /* Clear the partitioning for disabled planes. */
4164 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4165 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4167 if (WARN_ON(!state))
4170 if (!cstate->base.active) {
4171 alloc->start = alloc->end = 0;
4175 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
4176 alloc_size = skl_ddb_entry_size(alloc);
4177 if (alloc_size == 0)
4180 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4183 * 1. Allocate the mininum required blocks for each active plane
4184 * and allocate the cursor, it doesn't require extra allocation
4185 * proportional to the data rate.
4188 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4189 total_min_blocks += minimum[plane_id];
4190 total_min_blocks += y_minimum[plane_id];
4193 if (total_min_blocks > alloc_size) {
4194 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4195 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4200 alloc_size -= total_min_blocks;
4201 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4202 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4205 * 2. Distribute the remaining space in proportion to the amount of
4206 * data each plane needs to fetch from memory.
4208 * FIXME: we may not allocate every single block here.
4210 total_data_rate = skl_get_total_relative_data_rate(cstate,
4213 if (total_data_rate == 0)
4216 start = alloc->start;
4217 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4218 unsigned int data_rate, y_data_rate;
4219 uint16_t plane_blocks, y_plane_blocks = 0;
4221 if (plane_id == PLANE_CURSOR)
4224 data_rate = plane_data_rate[plane_id];
4227 * allocation for (packed formats) or (uv-plane part of planar format):
4228 * promote the expression to 64 bits to avoid overflowing, the
4229 * result is < available as data_rate / total_data_rate < 1
4231 plane_blocks = minimum[plane_id];
4232 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4235 /* Leave disabled planes at (0,0) */
4237 ddb->plane[pipe][plane_id].start = start;
4238 ddb->plane[pipe][plane_id].end = start + plane_blocks;
4241 start += plane_blocks;
4244 * allocation for y_plane part of planar format:
4246 y_data_rate = plane_y_data_rate[plane_id];
4248 y_plane_blocks = y_minimum[plane_id];
4249 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4253 ddb->y_plane[pipe][plane_id].start = start;
4254 ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4257 start += y_plane_blocks;
4264 * The max latency should be 257 (max the punit can code is 255 and we add 2us
4265 * for the read latency) and cpp should always be <= 8, so that
4266 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4267 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4269 static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
4272 uint32_t wm_intermediate_val;
4273 uint_fixed_16_16_t ret;
4276 return FP_16_16_MAX;
4278 wm_intermediate_val = latency * pixel_rate * cpp;
4279 ret = fixed_16_16_div_u64(wm_intermediate_val, 1000 * 512);
4283 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4284 uint32_t pipe_htotal,
4286 uint_fixed_16_16_t plane_blocks_per_line)
4288 uint32_t wm_intermediate_val;
4289 uint_fixed_16_16_t ret;
4292 return FP_16_16_MAX;
4294 wm_intermediate_val = latency * pixel_rate;
4295 wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4296 pipe_htotal * 1000);
4297 ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
4301 static uint_fixed_16_16_t
4302 intel_get_linetime_us(struct intel_crtc_state *cstate)
4304 uint32_t pixel_rate;
4305 uint32_t crtc_htotal;
4306 uint_fixed_16_16_t linetime_us;
4308 if (!cstate->base.active)
4309 return u32_to_fixed_16_16(0);
4311 pixel_rate = cstate->pixel_rate;
4313 if (WARN_ON(pixel_rate == 0))
4314 return u32_to_fixed_16_16(0);
4316 crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4317 linetime_us = fixed_16_16_div_u64(crtc_htotal * 1000, pixel_rate);
4323 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4324 const struct intel_plane_state *pstate)
4326 uint64_t adjusted_pixel_rate;
4327 uint_fixed_16_16_t downscale_amount;
4329 /* Shouldn't reach here on disabled planes... */
4330 if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4334 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4335 * with additional adjustments for plane-specific scaling.
4337 adjusted_pixel_rate = cstate->pixel_rate;
4338 downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4340 return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4344 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4345 struct intel_crtc_state *cstate,
4346 const struct intel_plane_state *intel_pstate,
4347 uint16_t ddb_allocation,
4349 uint16_t *out_blocks, /* out */
4350 uint8_t *out_lines, /* out */
4351 bool *enabled /* out */)
4353 struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4354 const struct drm_plane_state *pstate = &intel_pstate->base;
4355 const struct drm_framebuffer *fb = pstate->fb;
4356 uint32_t latency = dev_priv->wm.skl_latency[level];
4357 uint_fixed_16_16_t method1, method2;
4358 uint_fixed_16_16_t plane_blocks_per_line;
4359 uint_fixed_16_16_t selected_result;
4360 uint32_t interm_pbpl;
4361 uint32_t plane_bytes_per_line;
4362 uint32_t res_blocks, res_lines;
4364 uint32_t width = 0, height = 0;
4365 uint32_t plane_pixel_rate;
4366 uint_fixed_16_16_t y_tile_minimum;
4367 uint32_t y_min_scanlines;
4368 struct intel_atomic_state *state =
4369 to_intel_atomic_state(cstate->base.state);
4370 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4371 bool y_tiled, x_tiled;
4374 !intel_wm_plane_visible(cstate, intel_pstate)) {
4379 y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4380 fb->modifier == I915_FORMAT_MOD_Yf_TILED;
4381 x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4383 /* Display WA #1141: kbl,cfl */
4384 if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
4385 dev_priv->ipc_enabled)
4388 if (apply_memory_bw_wa && x_tiled)
4391 if (plane->id == PLANE_CURSOR) {
4392 width = intel_pstate->base.crtc_w;
4393 height = intel_pstate->base.crtc_h;
4396 * Src coordinates are already rotated by 270 degrees for
4397 * the 90/270 degree plane rotation cases (to match the
4398 * GTT mapping), hence no need to account for rotation here.
4400 width = drm_rect_width(&intel_pstate->base.src) >> 16;
4401 height = drm_rect_height(&intel_pstate->base.src) >> 16;
4404 cpp = fb->format->cpp[0];
4405 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
4407 if (drm_rotation_90_or_270(pstate->rotation)) {
4408 int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
4409 fb->format->cpp[1] :
4414 y_min_scanlines = 16;
4417 y_min_scanlines = 8;
4420 y_min_scanlines = 4;
4427 y_min_scanlines = 4;
4430 if (apply_memory_bw_wa)
4431 y_min_scanlines *= 2;
4433 plane_bytes_per_line = width * cpp;
4435 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
4436 y_min_scanlines, 512);
4437 plane_blocks_per_line = fixed_16_16_div(interm_pbpl,
4439 } else if (x_tiled) {
4440 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
4441 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
4443 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
4444 plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
4447 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
4448 method2 = skl_wm_method2(plane_pixel_rate,
4449 cstate->base.adjusted_mode.crtc_htotal,
4451 plane_blocks_per_line);
4453 y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
4454 plane_blocks_per_line);
4457 selected_result = max_fixed_16_16(method2, y_tile_minimum);
4459 uint32_t linetime_us;
4461 linetime_us = fixed_16_16_to_u32_round_up(
4462 intel_get_linetime_us(cstate));
4463 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
4464 (plane_bytes_per_line / 512 < 1))
4465 selected_result = method2;
4466 else if ((ddb_allocation && ddb_allocation /
4467 fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
4468 selected_result = min_fixed_16_16(method1, method2);
4469 else if (latency >= linetime_us)
4470 selected_result = min_fixed_16_16(method1, method2);
4472 selected_result = method1;
4475 res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
4476 res_lines = div_round_up_fixed16(selected_result,
4477 plane_blocks_per_line);
4479 if (level >= 1 && level <= 7) {
4481 res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
4482 res_lines += y_min_scanlines;
4488 if (res_blocks >= ddb_allocation || res_lines > 31) {
4492 * If there are no valid level 0 watermarks, then we can't
4493 * support this display configuration.
4498 struct drm_plane *plane = pstate->plane;
4500 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4501 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4502 plane->base.id, plane->name,
4503 res_blocks, ddb_allocation, res_lines);
4508 *out_blocks = res_blocks;
4509 *out_lines = res_lines;
4516 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4517 struct skl_ddb_allocation *ddb,
4518 struct intel_crtc_state *cstate,
4519 const struct intel_plane_state *intel_pstate,
4520 struct skl_plane_wm *wm)
4522 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4523 struct drm_plane *plane = intel_pstate->base.plane;
4524 struct intel_plane *intel_plane = to_intel_plane(plane);
4525 uint16_t ddb_blocks;
4526 enum pipe pipe = intel_crtc->pipe;
4527 int level, max_level = ilk_wm_max_level(dev_priv);
4530 if (WARN_ON(!intel_pstate->base.fb))
4533 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4535 for (level = 0; level <= max_level; level++) {
4536 struct skl_wm_level *result = &wm->wm[level];
4538 ret = skl_compute_plane_wm(dev_priv,
4543 &result->plane_res_b,
4544 &result->plane_res_l,
4554 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4556 struct drm_atomic_state *state = cstate->base.state;
4557 struct drm_i915_private *dev_priv = to_i915(state->dev);
4558 uint_fixed_16_16_t linetime_us;
4559 uint32_t linetime_wm;
4561 linetime_us = intel_get_linetime_us(cstate);
4563 if (is_fixed16_zero(linetime_us))
4566 linetime_wm = fixed_16_16_to_u32_round_up(mul_u32_fixed_16_16(8,
4569 /* Display WA #1135: bxt. */
4570 if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
4571 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
4576 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4577 struct skl_wm_level *trans_wm /* out */)
4579 if (!cstate->base.active)
4582 /* Until we know more, just disable transition WMs */
4583 trans_wm->plane_en = false;
4586 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4587 struct skl_ddb_allocation *ddb,
4588 struct skl_pipe_wm *pipe_wm)
4590 struct drm_device *dev = cstate->base.crtc->dev;
4591 struct drm_crtc_state *crtc_state = &cstate->base;
4592 const struct drm_i915_private *dev_priv = to_i915(dev);
4593 struct drm_plane *plane;
4594 const struct drm_plane_state *pstate;
4595 struct skl_plane_wm *wm;
4599 * We'll only calculate watermarks for planes that are actually
4600 * enabled, so make sure all other planes are set as disabled.
4602 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4604 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4605 const struct intel_plane_state *intel_pstate =
4606 to_intel_plane_state(pstate);
4607 enum plane_id plane_id = to_intel_plane(plane)->id;
4609 wm = &pipe_wm->planes[plane_id];
4611 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4615 skl_compute_transition_wm(cstate, &wm->trans_wm);
4617 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4622 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4624 const struct skl_ddb_entry *entry)
4627 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4632 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4634 const struct skl_wm_level *level)
4638 if (level->plane_en) {
4640 val |= level->plane_res_b;
4641 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4644 I915_WRITE(reg, val);
4647 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4648 const struct skl_plane_wm *wm,
4649 const struct skl_ddb_allocation *ddb,
4650 enum plane_id plane_id)
4652 struct drm_crtc *crtc = &intel_crtc->base;
4653 struct drm_device *dev = crtc->dev;
4654 struct drm_i915_private *dev_priv = to_i915(dev);
4655 int level, max_level = ilk_wm_max_level(dev_priv);
4656 enum pipe pipe = intel_crtc->pipe;
4658 for (level = 0; level <= max_level; level++) {
4659 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4662 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4665 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4666 &ddb->plane[pipe][plane_id]);
4667 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4668 &ddb->y_plane[pipe][plane_id]);
4671 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4672 const struct skl_plane_wm *wm,
4673 const struct skl_ddb_allocation *ddb)
4675 struct drm_crtc *crtc = &intel_crtc->base;
4676 struct drm_device *dev = crtc->dev;
4677 struct drm_i915_private *dev_priv = to_i915(dev);
4678 int level, max_level = ilk_wm_max_level(dev_priv);
4679 enum pipe pipe = intel_crtc->pipe;
4681 for (level = 0; level <= max_level; level++) {
4682 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4685 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4687 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4688 &ddb->plane[pipe][PLANE_CURSOR]);
4691 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4692 const struct skl_wm_level *l2)
4694 if (l1->plane_en != l2->plane_en)
4697 /* If both planes aren't enabled, the rest shouldn't matter */
4701 return (l1->plane_res_l == l2->plane_res_l &&
4702 l1->plane_res_b == l2->plane_res_b);
4705 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4706 const struct skl_ddb_entry *b)
4708 return a->start < b->end && b->start < a->end;
4711 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
4712 const struct skl_ddb_entry *ddb,
4717 for (i = 0; i < I915_MAX_PIPES; i++)
4718 if (i != ignore && entries[i] &&
4719 skl_ddb_entries_overlap(ddb, entries[i]))
4725 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4726 const struct skl_pipe_wm *old_pipe_wm,
4727 struct skl_pipe_wm *pipe_wm, /* out */
4728 struct skl_ddb_allocation *ddb, /* out */
4729 bool *changed /* out */)
4731 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4734 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4738 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4747 pipes_modified(struct drm_atomic_state *state)
4749 struct drm_crtc *crtc;
4750 struct drm_crtc_state *cstate;
4751 uint32_t i, ret = 0;
4753 for_each_new_crtc_in_state(state, crtc, cstate, i)
4754 ret |= drm_crtc_mask(crtc);
4760 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4762 struct drm_atomic_state *state = cstate->base.state;
4763 struct drm_device *dev = state->dev;
4764 struct drm_crtc *crtc = cstate->base.crtc;
4765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4766 struct drm_i915_private *dev_priv = to_i915(dev);
4767 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4768 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4769 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4770 struct drm_plane_state *plane_state;
4771 struct drm_plane *plane;
4772 enum pipe pipe = intel_crtc->pipe;
4774 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4776 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4777 enum plane_id plane_id = to_intel_plane(plane)->id;
4779 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4780 &new_ddb->plane[pipe][plane_id]) &&
4781 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4782 &new_ddb->y_plane[pipe][plane_id]))
4785 plane_state = drm_atomic_get_plane_state(state, plane);
4786 if (IS_ERR(plane_state))
4787 return PTR_ERR(plane_state);
4794 skl_compute_ddb(struct drm_atomic_state *state)
4796 struct drm_device *dev = state->dev;
4797 struct drm_i915_private *dev_priv = to_i915(dev);
4798 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4799 struct intel_crtc *intel_crtc;
4800 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4801 uint32_t realloc_pipes = pipes_modified(state);
4805 * If this is our first atomic update following hardware readout,
4806 * we can't trust the DDB that the BIOS programmed for us. Let's
4807 * pretend that all pipes switched active status so that we'll
4808 * ensure a full DDB recompute.
4810 if (dev_priv->wm.distrust_bios_wm) {
4811 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4812 state->acquire_ctx);
4816 intel_state->active_pipe_changes = ~0;
4819 * We usually only initialize intel_state->active_crtcs if we
4820 * we're doing a modeset; make sure this field is always
4821 * initialized during the sanitization process that happens
4822 * on the first commit too.
4824 if (!intel_state->modeset)
4825 intel_state->active_crtcs = dev_priv->active_crtcs;
4829 * If the modeset changes which CRTC's are active, we need to
4830 * recompute the DDB allocation for *all* active pipes, even
4831 * those that weren't otherwise being modified in any way by this
4832 * atomic commit. Due to the shrinking of the per-pipe allocations
4833 * when new active CRTC's are added, it's possible for a pipe that
4834 * we were already using and aren't changing at all here to suddenly
4835 * become invalid if its DDB needs exceeds its new allocation.
4837 * Note that if we wind up doing a full DDB recompute, we can't let
4838 * any other display updates race with this transaction, so we need
4839 * to grab the lock on *all* CRTC's.
4841 if (intel_state->active_pipe_changes) {
4843 intel_state->wm_results.dirty_pipes = ~0;
4847 * We're not recomputing for the pipes not included in the commit, so
4848 * make sure we start with the current state.
4850 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4852 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4853 struct intel_crtc_state *cstate;
4855 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4857 return PTR_ERR(cstate);
4859 ret = skl_allocate_pipe_ddb(cstate, ddb);
4863 ret = skl_ddb_add_affected_planes(cstate);
4872 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4873 struct skl_wm_values *src,
4876 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4877 sizeof(dst->ddb.y_plane[pipe]));
4878 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4879 sizeof(dst->ddb.plane[pipe]));
4883 skl_print_wm_changes(const struct drm_atomic_state *state)
4885 const struct drm_device *dev = state->dev;
4886 const struct drm_i915_private *dev_priv = to_i915(dev);
4887 const struct intel_atomic_state *intel_state =
4888 to_intel_atomic_state(state);
4889 const struct drm_crtc *crtc;
4890 const struct drm_crtc_state *cstate;
4891 const struct intel_plane *intel_plane;
4892 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4893 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4896 for_each_new_crtc_in_state(state, crtc, cstate, i) {
4897 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898 enum pipe pipe = intel_crtc->pipe;
4900 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4901 enum plane_id plane_id = intel_plane->id;
4902 const struct skl_ddb_entry *old, *new;
4904 old = &old_ddb->plane[pipe][plane_id];
4905 new = &new_ddb->plane[pipe][plane_id];
4907 if (skl_ddb_entry_equal(old, new))
4910 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4911 intel_plane->base.base.id,
4912 intel_plane->base.name,
4913 old->start, old->end,
4914 new->start, new->end);
4920 skl_compute_wm(struct drm_atomic_state *state)
4922 struct drm_crtc *crtc;
4923 struct drm_crtc_state *cstate;
4924 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4925 struct skl_wm_values *results = &intel_state->wm_results;
4926 struct drm_device *dev = state->dev;
4927 struct skl_pipe_wm *pipe_wm;
4928 bool changed = false;
4932 * When we distrust bios wm we always need to recompute to set the
4933 * expected DDB allocations for each CRTC.
4935 if (to_i915(dev)->wm.distrust_bios_wm)
4939 * If this transaction isn't actually touching any CRTC's, don't
4940 * bother with watermark calculation. Note that if we pass this
4941 * test, we're guaranteed to hold at least one CRTC state mutex,
4942 * which means we can safely use values like dev_priv->active_crtcs
4943 * since any racing commits that want to update them would need to
4944 * hold _all_ CRTC state mutexes.
4946 for_each_new_crtc_in_state(state, crtc, cstate, i)
4952 /* Clear all dirty flags */
4953 results->dirty_pipes = 0;
4955 ret = skl_compute_ddb(state);
4960 * Calculate WM's for all pipes that are part of this transaction.
4961 * Note that the DDB allocation above may have added more CRTC's that
4962 * weren't otherwise being modified (and set bits in dirty_pipes) if
4963 * pipe allocations had to change.
4965 * FIXME: Now that we're doing this in the atomic check phase, we
4966 * should allow skl_update_pipe_wm() to return failure in cases where
4967 * no suitable watermark values can be found.
4969 for_each_new_crtc_in_state(state, crtc, cstate, i) {
4970 struct intel_crtc_state *intel_cstate =
4971 to_intel_crtc_state(cstate);
4972 const struct skl_pipe_wm *old_pipe_wm =
4973 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4975 pipe_wm = &intel_cstate->wm.skl.optimal;
4976 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4977 &results->ddb, &changed);
4982 results->dirty_pipes |= drm_crtc_mask(crtc);
4984 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4985 /* This pipe's WM's did not change */
4988 intel_cstate->update_wm_pre = true;
4991 skl_print_wm_changes(state);
4996 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4997 struct intel_crtc_state *cstate)
4999 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5000 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5001 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5002 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5003 enum pipe pipe = crtc->pipe;
5004 enum plane_id plane_id;
5006 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5009 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5011 for_each_plane_id_on_crtc(crtc, plane_id) {
5012 if (plane_id != PLANE_CURSOR)
5013 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5016 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5021 static void skl_initial_wm(struct intel_atomic_state *state,
5022 struct intel_crtc_state *cstate)
5024 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5025 struct drm_device *dev = intel_crtc->base.dev;
5026 struct drm_i915_private *dev_priv = to_i915(dev);
5027 struct skl_wm_values *results = &state->wm_results;
5028 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5029 enum pipe pipe = intel_crtc->pipe;
5031 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5034 mutex_lock(&dev_priv->wm.wm_mutex);
5036 if (cstate->base.active_changed)
5037 skl_atomic_update_crtc_wm(state, cstate);
5039 skl_copy_wm_for_pipe(hw_vals, results, pipe);
5041 mutex_unlock(&dev_priv->wm.wm_mutex);
5044 static void ilk_compute_wm_config(struct drm_device *dev,
5045 struct intel_wm_config *config)
5047 struct intel_crtc *crtc;
5049 /* Compute the currently _active_ config */
5050 for_each_intel_crtc(dev, crtc) {
5051 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5053 if (!wm->pipe_enabled)
5056 config->sprites_enabled |= wm->sprites_enabled;
5057 config->sprites_scaled |= wm->sprites_scaled;
5058 config->num_pipes_active++;
5062 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5064 struct drm_device *dev = &dev_priv->drm;
5065 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5066 struct ilk_wm_maximums max;
5067 struct intel_wm_config config = {};
5068 struct ilk_wm_values results = {};
5069 enum intel_ddb_partitioning partitioning;
5071 ilk_compute_wm_config(dev, &config);
5073 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5074 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5076 /* 5/6 split only in single pipe config on IVB+ */
5077 if (INTEL_GEN(dev_priv) >= 7 &&
5078 config.num_pipes_active == 1 && config.sprites_enabled) {
5079 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5080 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5082 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5084 best_lp_wm = &lp_wm_1_2;
5087 partitioning = (best_lp_wm == &lp_wm_1_2) ?
5088 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5090 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5092 ilk_write_wm_values(dev_priv, &results);
5095 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5096 struct intel_crtc_state *cstate)
5098 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5099 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5101 mutex_lock(&dev_priv->wm.wm_mutex);
5102 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5103 ilk_program_watermarks(dev_priv);
5104 mutex_unlock(&dev_priv->wm.wm_mutex);
5107 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5108 struct intel_crtc_state *cstate)
5110 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5111 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5113 mutex_lock(&dev_priv->wm.wm_mutex);
5114 if (cstate->wm.need_postvbl_update) {
5115 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5116 ilk_program_watermarks(dev_priv);
5118 mutex_unlock(&dev_priv->wm.wm_mutex);
5121 static inline void skl_wm_level_from_reg_val(uint32_t val,
5122 struct skl_wm_level *level)
5124 level->plane_en = val & PLANE_WM_EN;
5125 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5126 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5127 PLANE_WM_LINES_MASK;
5130 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5131 struct skl_pipe_wm *out)
5133 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135 enum pipe pipe = intel_crtc->pipe;
5136 int level, max_level;
5137 enum plane_id plane_id;
5140 max_level = ilk_wm_max_level(dev_priv);
5142 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5143 struct skl_plane_wm *wm = &out->planes[plane_id];
5145 for (level = 0; level <= max_level; level++) {
5146 if (plane_id != PLANE_CURSOR)
5147 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5149 val = I915_READ(CUR_WM(pipe, level));
5151 skl_wm_level_from_reg_val(val, &wm->wm[level]);
5154 if (plane_id != PLANE_CURSOR)
5155 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5157 val = I915_READ(CUR_WM_TRANS(pipe));
5159 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5162 if (!intel_crtc->active)
5165 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5168 void skl_wm_get_hw_state(struct drm_device *dev)
5170 struct drm_i915_private *dev_priv = to_i915(dev);
5171 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5172 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5173 struct drm_crtc *crtc;
5174 struct intel_crtc *intel_crtc;
5175 struct intel_crtc_state *cstate;
5177 skl_ddb_get_hw_state(dev_priv, ddb);
5178 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5179 intel_crtc = to_intel_crtc(crtc);
5180 cstate = to_intel_crtc_state(crtc->state);
5182 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5184 if (intel_crtc->active)
5185 hw->dirty_pipes |= drm_crtc_mask(crtc);
5188 if (dev_priv->active_crtcs) {
5189 /* Fully recompute DDB on first atomic commit */
5190 dev_priv->wm.distrust_bios_wm = true;
5192 /* Easy/common case; just sanitize DDB now if everything off */
5193 memset(ddb, 0, sizeof(*ddb));
5197 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5199 struct drm_device *dev = crtc->dev;
5200 struct drm_i915_private *dev_priv = to_i915(dev);
5201 struct ilk_wm_values *hw = &dev_priv->wm.hw;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5204 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5205 enum pipe pipe = intel_crtc->pipe;
5206 static const i915_reg_t wm0_pipe_reg[] = {
5207 [PIPE_A] = WM0_PIPEA_ILK,
5208 [PIPE_B] = WM0_PIPEB_ILK,
5209 [PIPE_C] = WM0_PIPEC_IVB,
5212 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5213 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5214 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5216 memset(active, 0, sizeof(*active));
5218 active->pipe_enabled = intel_crtc->active;
5220 if (active->pipe_enabled) {
5221 u32 tmp = hw->wm_pipe[pipe];
5224 * For active pipes LP0 watermark is marked as
5225 * enabled, and LP1+ watermaks as disabled since
5226 * we can't really reverse compute them in case
5227 * multiple pipes are active.
5229 active->wm[0].enable = true;
5230 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5231 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5232 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5233 active->linetime = hw->wm_linetime[pipe];
5235 int level, max_level = ilk_wm_max_level(dev_priv);
5238 * For inactive pipes, all watermark levels
5239 * should be marked as enabled but zeroed,
5240 * which is what we'd compute them to.
5242 for (level = 0; level <= max_level; level++)
5243 active->wm[level].enable = true;
5246 intel_crtc->wm.active.ilk = *active;
5249 #define _FW_WM(value, plane) \
5250 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5251 #define _FW_WM_VLV(value, plane) \
5252 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5254 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5255 struct g4x_wm_values *wm)
5259 tmp = I915_READ(DSPFW1);
5260 wm->sr.plane = _FW_WM(tmp, SR);
5261 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5262 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5263 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5265 tmp = I915_READ(DSPFW2);
5266 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5267 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5268 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5269 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5270 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5271 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5273 tmp = I915_READ(DSPFW3);
5274 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5275 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5276 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5277 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5280 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5281 struct vlv_wm_values *wm)
5286 for_each_pipe(dev_priv, pipe) {
5287 tmp = I915_READ(VLV_DDL(pipe));
5289 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5290 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5291 wm->ddl[pipe].plane[PLANE_CURSOR] =
5292 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5293 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5294 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5295 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5296 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5299 tmp = I915_READ(DSPFW1);
5300 wm->sr.plane = _FW_WM(tmp, SR);
5301 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5302 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5303 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5305 tmp = I915_READ(DSPFW2);
5306 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5307 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5308 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5310 tmp = I915_READ(DSPFW3);
5311 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5313 if (IS_CHERRYVIEW(dev_priv)) {
5314 tmp = I915_READ(DSPFW7_CHV);
5315 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5316 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5318 tmp = I915_READ(DSPFW8_CHV);
5319 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5320 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5322 tmp = I915_READ(DSPFW9_CHV);
5323 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5324 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5326 tmp = I915_READ(DSPHOWM);
5327 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5328 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5329 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5330 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5331 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5332 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5333 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5334 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5335 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5336 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5338 tmp = I915_READ(DSPFW7);
5339 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5340 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5342 tmp = I915_READ(DSPHOWM);
5343 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5344 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5345 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5346 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5347 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5348 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5349 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5356 void g4x_wm_get_hw_state(struct drm_device *dev)
5358 struct drm_i915_private *dev_priv = to_i915(dev);
5359 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5360 struct intel_crtc *crtc;
5362 g4x_read_wm_values(dev_priv, wm);
5364 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5366 for_each_intel_crtc(dev, crtc) {
5367 struct intel_crtc_state *crtc_state =
5368 to_intel_crtc_state(crtc->base.state);
5369 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5370 struct g4x_pipe_wm *raw;
5371 enum pipe pipe = crtc->pipe;
5372 enum plane_id plane_id;
5373 int level, max_level;
5375 active->cxsr = wm->cxsr;
5376 active->hpll_en = wm->hpll_en;
5377 active->fbc_en = wm->fbc_en;
5379 active->sr = wm->sr;
5380 active->hpll = wm->hpll;
5382 for_each_plane_id_on_crtc(crtc, plane_id) {
5383 active->wm.plane[plane_id] =
5384 wm->pipe[pipe].plane[plane_id];
5387 if (wm->cxsr && wm->hpll_en)
5388 max_level = G4X_WM_LEVEL_HPLL;
5390 max_level = G4X_WM_LEVEL_SR;
5392 max_level = G4X_WM_LEVEL_NORMAL;
5394 level = G4X_WM_LEVEL_NORMAL;
5395 raw = &crtc_state->wm.g4x.raw[level];
5396 for_each_plane_id_on_crtc(crtc, plane_id)
5397 raw->plane[plane_id] = active->wm.plane[plane_id];
5399 if (++level > max_level)
5402 raw = &crtc_state->wm.g4x.raw[level];
5403 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5404 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5405 raw->plane[PLANE_SPRITE0] = 0;
5406 raw->fbc = active->sr.fbc;
5408 if (++level > max_level)
5411 raw = &crtc_state->wm.g4x.raw[level];
5412 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5413 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5414 raw->plane[PLANE_SPRITE0] = 0;
5415 raw->fbc = active->hpll.fbc;
5418 for_each_plane_id_on_crtc(crtc, plane_id)
5419 g4x_raw_plane_wm_set(crtc_state, level,
5420 plane_id, USHRT_MAX);
5421 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5423 crtc_state->wm.g4x.optimal = *active;
5424 crtc_state->wm.g4x.intermediate = *active;
5426 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5428 wm->pipe[pipe].plane[PLANE_PRIMARY],
5429 wm->pipe[pipe].plane[PLANE_CURSOR],
5430 wm->pipe[pipe].plane[PLANE_SPRITE0]);
5433 DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5434 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5435 DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5436 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5437 DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5438 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5441 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5443 struct intel_plane *plane;
5444 struct intel_crtc *crtc;
5446 mutex_lock(&dev_priv->wm.wm_mutex);
5448 for_each_intel_plane(&dev_priv->drm, plane) {
5449 struct intel_crtc *crtc =
5450 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5451 struct intel_crtc_state *crtc_state =
5452 to_intel_crtc_state(crtc->base.state);
5453 struct intel_plane_state *plane_state =
5454 to_intel_plane_state(plane->base.state);
5455 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5456 enum plane_id plane_id = plane->id;
5459 if (plane_state->base.visible)
5462 for (level = 0; level < 3; level++) {
5463 struct g4x_pipe_wm *raw =
5464 &crtc_state->wm.g4x.raw[level];
5466 raw->plane[plane_id] = 0;
5467 wm_state->wm.plane[plane_id] = 0;
5470 if (plane_id == PLANE_PRIMARY) {
5471 for (level = 0; level < 3; level++) {
5472 struct g4x_pipe_wm *raw =
5473 &crtc_state->wm.g4x.raw[level];
5477 wm_state->sr.fbc = 0;
5478 wm_state->hpll.fbc = 0;
5479 wm_state->fbc_en = false;
5483 for_each_intel_crtc(&dev_priv->drm, crtc) {
5484 struct intel_crtc_state *crtc_state =
5485 to_intel_crtc_state(crtc->base.state);
5487 crtc_state->wm.g4x.intermediate =
5488 crtc_state->wm.g4x.optimal;
5489 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5492 g4x_program_watermarks(dev_priv);
5494 mutex_unlock(&dev_priv->wm.wm_mutex);
5497 void vlv_wm_get_hw_state(struct drm_device *dev)
5499 struct drm_i915_private *dev_priv = to_i915(dev);
5500 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5501 struct intel_crtc *crtc;
5504 vlv_read_wm_values(dev_priv, wm);
5506 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5507 wm->level = VLV_WM_LEVEL_PM2;
5509 if (IS_CHERRYVIEW(dev_priv)) {
5510 mutex_lock(&dev_priv->rps.hw_lock);
5512 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5513 if (val & DSP_MAXFIFO_PM5_ENABLE)
5514 wm->level = VLV_WM_LEVEL_PM5;
5517 * If DDR DVFS is disabled in the BIOS, Punit
5518 * will never ack the request. So if that happens
5519 * assume we don't have to enable/disable DDR DVFS
5520 * dynamically. To test that just set the REQ_ACK
5521 * bit to poke the Punit, but don't change the
5522 * HIGH/LOW bits so that we don't actually change
5523 * the current state.
5525 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5526 val |= FORCE_DDR_FREQ_REQ_ACK;
5527 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5529 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5530 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5531 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5532 "assuming DDR DVFS is disabled\n");
5533 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5535 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5536 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5537 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5540 mutex_unlock(&dev_priv->rps.hw_lock);
5543 for_each_intel_crtc(dev, crtc) {
5544 struct intel_crtc_state *crtc_state =
5545 to_intel_crtc_state(crtc->base.state);
5546 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5547 const struct vlv_fifo_state *fifo_state =
5548 &crtc_state->wm.vlv.fifo_state;
5549 enum pipe pipe = crtc->pipe;
5550 enum plane_id plane_id;
5553 vlv_get_fifo_size(crtc_state);
5555 active->num_levels = wm->level + 1;
5556 active->cxsr = wm->cxsr;
5558 for (level = 0; level < active->num_levels; level++) {
5559 struct g4x_pipe_wm *raw =
5560 &crtc_state->wm.vlv.raw[level];
5562 active->sr[level].plane = wm->sr.plane;
5563 active->sr[level].cursor = wm->sr.cursor;
5565 for_each_plane_id_on_crtc(crtc, plane_id) {
5566 active->wm[level].plane[plane_id] =
5567 wm->pipe[pipe].plane[plane_id];
5569 raw->plane[plane_id] =
5570 vlv_invert_wm_value(active->wm[level].plane[plane_id],
5571 fifo_state->plane[plane_id]);
5575 for_each_plane_id_on_crtc(crtc, plane_id)
5576 vlv_raw_plane_wm_set(crtc_state, level,
5577 plane_id, USHRT_MAX);
5578 vlv_invalidate_wms(crtc, active, level);
5580 crtc_state->wm.vlv.optimal = *active;
5581 crtc_state->wm.vlv.intermediate = *active;
5583 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5585 wm->pipe[pipe].plane[PLANE_PRIMARY],
5586 wm->pipe[pipe].plane[PLANE_CURSOR],
5587 wm->pipe[pipe].plane[PLANE_SPRITE0],
5588 wm->pipe[pipe].plane[PLANE_SPRITE1]);
5591 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5592 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5595 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5597 struct intel_plane *plane;
5598 struct intel_crtc *crtc;
5600 mutex_lock(&dev_priv->wm.wm_mutex);
5602 for_each_intel_plane(&dev_priv->drm, plane) {
5603 struct intel_crtc *crtc =
5604 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5605 struct intel_crtc_state *crtc_state =
5606 to_intel_crtc_state(crtc->base.state);
5607 struct intel_plane_state *plane_state =
5608 to_intel_plane_state(plane->base.state);
5609 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5610 const struct vlv_fifo_state *fifo_state =
5611 &crtc_state->wm.vlv.fifo_state;
5612 enum plane_id plane_id = plane->id;
5615 if (plane_state->base.visible)
5618 for (level = 0; level < wm_state->num_levels; level++) {
5619 struct g4x_pipe_wm *raw =
5620 &crtc_state->wm.vlv.raw[level];
5622 raw->plane[plane_id] = 0;
5624 wm_state->wm[level].plane[plane_id] =
5625 vlv_invert_wm_value(raw->plane[plane_id],
5626 fifo_state->plane[plane_id]);
5630 for_each_intel_crtc(&dev_priv->drm, crtc) {
5631 struct intel_crtc_state *crtc_state =
5632 to_intel_crtc_state(crtc->base.state);
5634 crtc_state->wm.vlv.intermediate =
5635 crtc_state->wm.vlv.optimal;
5636 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5639 vlv_program_watermarks(dev_priv);
5641 mutex_unlock(&dev_priv->wm.wm_mutex);
5644 void ilk_wm_get_hw_state(struct drm_device *dev)
5646 struct drm_i915_private *dev_priv = to_i915(dev);
5647 struct ilk_wm_values *hw = &dev_priv->wm.hw;
5648 struct drm_crtc *crtc;
5650 for_each_crtc(dev, crtc)
5651 ilk_pipe_wm_get_hw_state(crtc);
5653 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
5654 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
5655 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
5657 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
5658 if (INTEL_GEN(dev_priv) >= 7) {
5659 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
5660 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
5663 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5664 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
5665 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5666 else if (IS_IVYBRIDGE(dev_priv))
5667 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
5668 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5671 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
5675 * intel_update_watermarks - update FIFO watermark values based on current modes
5677 * Calculate watermark values for the various WM regs based on current mode
5678 * and plane configuration.
5680 * There are several cases to deal with here:
5681 * - normal (i.e. non-self-refresh)
5682 * - self-refresh (SR) mode
5683 * - lines are large relative to FIFO size (buffer can hold up to 2)
5684 * - lines are small relative to FIFO size (buffer can hold more than 2
5685 * lines), so need to account for TLB latency
5687 * The normal calculation is:
5688 * watermark = dotclock * bytes per pixel * latency
5689 * where latency is platform & configuration dependent (we assume pessimal
5692 * The SR calculation is:
5693 * watermark = (trunc(latency/line time)+1) * surface width *
5696 * line time = htotal / dotclock
5697 * surface width = hdisplay for normal plane and 64 for cursor
5698 * and latency is assumed to be high, as above.
5700 * The final value programmed to the register should always be rounded up,
5701 * and include an extra 2 entries to account for clock crossings.
5703 * We don't use the sprite, so we can ignore that. And on Crestline we have
5704 * to set the non-SR watermarks to 8.
5706 void intel_update_watermarks(struct intel_crtc *crtc)
5708 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5710 if (dev_priv->display.update_wm)
5711 dev_priv->display.update_wm(crtc);
5715 * Lock protecting IPS related data structures
5717 DEFINE_SPINLOCK(mchdev_lock);
5719 /* Global for IPS driver to get at the current i915 device. Protected by
5721 static struct drm_i915_private *i915_mch_dev;
5723 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
5727 lockdep_assert_held(&mchdev_lock);
5729 rgvswctl = I915_READ16(MEMSWCTL);
5730 if (rgvswctl & MEMCTL_CMD_STS) {
5731 DRM_DEBUG("gpu busy, RCS change rejected\n");
5732 return false; /* still busy with another command */
5735 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5736 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5737 I915_WRITE16(MEMSWCTL, rgvswctl);
5738 POSTING_READ16(MEMSWCTL);
5740 rgvswctl |= MEMCTL_CMD_STS;
5741 I915_WRITE16(MEMSWCTL, rgvswctl);
5746 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
5749 u8 fmax, fmin, fstart, vstart;
5751 spin_lock_irq(&mchdev_lock);
5753 rgvmodectl = I915_READ(MEMMODECTL);
5755 /* Enable temp reporting */
5756 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5757 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5759 /* 100ms RC evaluation intervals */
5760 I915_WRITE(RCUPEI, 100000);
5761 I915_WRITE(RCDNEI, 100000);
5763 /* Set max/min thresholds to 90ms and 80ms respectively */
5764 I915_WRITE(RCBMAXAVG, 90000);
5765 I915_WRITE(RCBMINAVG, 80000);
5767 I915_WRITE(MEMIHYST, 1);
5769 /* Set up min, max, and cur for interrupt handling */
5770 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5771 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5772 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5773 MEMMODE_FSTART_SHIFT;
5775 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5778 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5779 dev_priv->ips.fstart = fstart;
5781 dev_priv->ips.max_delay = fstart;
5782 dev_priv->ips.min_delay = fmin;
5783 dev_priv->ips.cur_delay = fstart;
5785 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5786 fmax, fmin, fstart);
5788 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5791 * Interrupts will be enabled in ironlake_irq_postinstall
5794 I915_WRITE(VIDSTART, vstart);
5795 POSTING_READ(VIDSTART);
5797 rgvmodectl |= MEMMODE_SWMODE_EN;
5798 I915_WRITE(MEMMODECTL, rgvmodectl);
5800 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5801 DRM_ERROR("stuck trying to change perf mode\n");
5804 ironlake_set_drps(dev_priv, fstart);
5806 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5807 I915_READ(DDREC) + I915_READ(CSIEC);
5808 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5809 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5810 dev_priv->ips.last_time2 = ktime_get_raw_ns();
5812 spin_unlock_irq(&mchdev_lock);
5815 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5819 spin_lock_irq(&mchdev_lock);
5821 rgvswctl = I915_READ16(MEMSWCTL);
5823 /* Ack interrupts, disable EFC interrupt */
5824 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5825 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5826 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5827 I915_WRITE(DEIIR, DE_PCU_EVENT);
5828 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5830 /* Go back to the starting frequency */
5831 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
5833 rgvswctl |= MEMCTL_CMD_STS;
5834 I915_WRITE(MEMSWCTL, rgvswctl);
5837 spin_unlock_irq(&mchdev_lock);
5840 /* There's a funny hw issue where the hw returns all 0 when reading from
5841 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5842 * ourselves, instead of doing a rmw cycle (which might result in us clearing
5843 * all limits and the gpu stuck at whatever frequency it is at atm).
5845 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
5849 /* Only set the down limit when we've reached the lowest level to avoid
5850 * getting more interrupts, otherwise leave this clear. This prevents a
5851 * race in the hw when coming out of rc6: There's a tiny window where
5852 * the hw runs at the minimal clock before selecting the desired
5853 * frequency, if the down threshold expires in that window we will not
5854 * receive a down interrupt. */
5855 if (IS_GEN9(dev_priv)) {
5856 limits = (dev_priv->rps.max_freq_softlimit) << 23;
5857 if (val <= dev_priv->rps.min_freq_softlimit)
5858 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
5860 limits = dev_priv->rps.max_freq_softlimit << 24;
5861 if (val <= dev_priv->rps.min_freq_softlimit)
5862 limits |= dev_priv->rps.min_freq_softlimit << 16;
5868 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
5871 u32 threshold_up = 0, threshold_down = 0; /* in % */
5872 u32 ei_up = 0, ei_down = 0;
5874 new_power = dev_priv->rps.power;
5875 switch (dev_priv->rps.power) {
5877 if (val > dev_priv->rps.efficient_freq + 1 &&
5878 val > dev_priv->rps.cur_freq)
5879 new_power = BETWEEN;
5883 if (val <= dev_priv->rps.efficient_freq &&
5884 val < dev_priv->rps.cur_freq)
5885 new_power = LOW_POWER;
5886 else if (val >= dev_priv->rps.rp0_freq &&
5887 val > dev_priv->rps.cur_freq)
5888 new_power = HIGH_POWER;
5892 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
5893 val < dev_priv->rps.cur_freq)
5894 new_power = BETWEEN;
5897 /* Max/min bins are special */
5898 if (val <= dev_priv->rps.min_freq_softlimit)
5899 new_power = LOW_POWER;
5900 if (val >= dev_priv->rps.max_freq_softlimit)
5901 new_power = HIGH_POWER;
5902 if (new_power == dev_priv->rps.power)
5905 /* Note the units here are not exactly 1us, but 1280ns. */
5906 switch (new_power) {
5908 /* Upclock if more than 95% busy over 16ms */
5912 /* Downclock if less than 85% busy over 32ms */
5914 threshold_down = 85;
5918 /* Upclock if more than 90% busy over 13ms */
5922 /* Downclock if less than 75% busy over 32ms */
5924 threshold_down = 75;
5928 /* Upclock if more than 85% busy over 10ms */
5932 /* Downclock if less than 60% busy over 32ms */
5934 threshold_down = 60;
5938 /* When byt can survive without system hang with dynamic
5939 * sw freq adjustments, this restriction can be lifted.
5941 if (IS_VALLEYVIEW(dev_priv))
5944 I915_WRITE(GEN6_RP_UP_EI,
5945 GT_INTERVAL_FROM_US(dev_priv, ei_up));
5946 I915_WRITE(GEN6_RP_UP_THRESHOLD,
5947 GT_INTERVAL_FROM_US(dev_priv,
5948 ei_up * threshold_up / 100));
5950 I915_WRITE(GEN6_RP_DOWN_EI,
5951 GT_INTERVAL_FROM_US(dev_priv, ei_down));
5952 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
5953 GT_INTERVAL_FROM_US(dev_priv,
5954 ei_down * threshold_down / 100));
5956 I915_WRITE(GEN6_RP_CONTROL,
5957 GEN6_RP_MEDIA_TURBO |
5958 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5959 GEN6_RP_MEDIA_IS_GFX |
5961 GEN6_RP_UP_BUSY_AVG |
5962 GEN6_RP_DOWN_IDLE_AVG);
5965 dev_priv->rps.power = new_power;
5966 dev_priv->rps.up_threshold = threshold_up;
5967 dev_priv->rps.down_threshold = threshold_down;
5968 dev_priv->rps.last_adj = 0;
5971 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
5975 /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
5976 if (val > dev_priv->rps.min_freq_softlimit)
5977 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
5978 if (val < dev_priv->rps.max_freq_softlimit)
5979 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
5981 mask &= dev_priv->pm_rps_events;
5983 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
5986 /* gen6_set_rps is called to update the frequency request, but should also be
5987 * called when the range (min_delay and max_delay) is modified so that we can
5988 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
5989 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
5991 /* min/max delay may still have been modified so be sure to
5992 * write the limits value.
5994 if (val != dev_priv->rps.cur_freq) {
5995 gen6_set_rps_thresholds(dev_priv, val);
5997 if (IS_GEN9(dev_priv))
5998 I915_WRITE(GEN6_RPNSWREQ,
5999 GEN9_FREQUENCY(val));
6000 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6001 I915_WRITE(GEN6_RPNSWREQ,
6002 HSW_FREQUENCY(val));
6004 I915_WRITE(GEN6_RPNSWREQ,
6005 GEN6_FREQUENCY(val) |
6007 GEN6_AGGRESSIVE_TURBO);
6010 /* Make sure we continue to get interrupts
6011 * until we hit the minimum or maximum frequencies.
6013 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6014 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6016 dev_priv->rps.cur_freq = val;
6017 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6022 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6026 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6027 "Odd GPU freq value\n"))
6030 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6032 if (val != dev_priv->rps.cur_freq) {
6033 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6037 gen6_set_rps_thresholds(dev_priv, val);
6040 dev_priv->rps.cur_freq = val;
6041 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6046 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6048 * * If Gfx is Idle, then
6049 * 1. Forcewake Media well.
6050 * 2. Request idle freq.
6051 * 3. Release Forcewake of Media well.
6053 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6055 u32 val = dev_priv->rps.idle_freq;
6058 if (dev_priv->rps.cur_freq <= val)
6061 /* The punit delays the write of the frequency and voltage until it
6062 * determines the GPU is awake. During normal usage we don't want to
6063 * waste power changing the frequency if the GPU is sleeping (rc6).
6064 * However, the GPU and driver is now idle and we do not want to delay
6065 * switching to minimum voltage (reducing power whilst idle) as we do
6066 * not expect to be woken in the near future and so must flush the
6067 * change by waking the device.
6069 * We choose to take the media powerwell (either would do to trick the
6070 * punit into committing the voltage change) as that takes a lot less
6071 * power than the render powerwell.
6073 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6074 err = valleyview_set_rps(dev_priv, val);
6075 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6078 DRM_ERROR("Failed to set RPS for idle\n");
6081 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6083 mutex_lock(&dev_priv->rps.hw_lock);
6084 if (dev_priv->rps.enabled) {
6087 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6088 gen6_rps_reset_ei(dev_priv);
6089 I915_WRITE(GEN6_PMINTRMSK,
6090 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
6092 gen6_enable_rps_interrupts(dev_priv);
6094 /* Use the user's desired frequency as a guide, but for better
6095 * performance, jump directly to RPe as our starting frequency.
6097 freq = max(dev_priv->rps.cur_freq,
6098 dev_priv->rps.efficient_freq);
6100 if (intel_set_rps(dev_priv,
6102 dev_priv->rps.min_freq_softlimit,
6103 dev_priv->rps.max_freq_softlimit)))
6104 DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6106 mutex_unlock(&dev_priv->rps.hw_lock);
6109 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6111 /* Flush our bottom-half so that it does not race with us
6112 * setting the idle frequency and so that it is bounded by
6113 * our rpm wakeref. And then disable the interrupts to stop any
6114 * futher RPS reclocking whilst we are asleep.
6116 gen6_disable_rps_interrupts(dev_priv);
6118 mutex_lock(&dev_priv->rps.hw_lock);
6119 if (dev_priv->rps.enabled) {
6120 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6121 vlv_set_rps_idle(dev_priv);
6123 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
6124 dev_priv->rps.last_adj = 0;
6125 I915_WRITE(GEN6_PMINTRMSK,
6126 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6128 mutex_unlock(&dev_priv->rps.hw_lock);
6131 void gen6_rps_boost(struct drm_i915_gem_request *rq,
6132 struct intel_rps_client *rps)
6134 struct drm_i915_private *i915 = rq->i915;
6137 /* This is intentionally racy! We peek at the state here, then
6138 * validate inside the RPS worker.
6140 if (!i915->rps.enabled)
6144 spin_lock_irq(&rq->lock);
6145 if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6146 atomic_inc(&i915->rps.num_waiters);
6147 rq->waitboost = true;
6150 spin_unlock_irq(&rq->lock);
6154 if (READ_ONCE(i915->rps.cur_freq) < i915->rps.boost_freq)
6155 schedule_work(&i915->rps.work);
6157 atomic_inc(rps ? &rps->boosts : &i915->rps.boosts);
6160 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6164 lockdep_assert_held(&dev_priv->rps.hw_lock);
6165 GEM_BUG_ON(val > dev_priv->rps.max_freq);
6166 GEM_BUG_ON(val < dev_priv->rps.min_freq);
6168 if (!dev_priv->rps.enabled) {
6169 dev_priv->rps.cur_freq = val;
6173 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6174 err = valleyview_set_rps(dev_priv, val);
6176 err = gen6_set_rps(dev_priv, val);
6181 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6183 I915_WRITE(GEN6_RC_CONTROL, 0);
6184 I915_WRITE(GEN9_PG_ENABLE, 0);
6187 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6189 I915_WRITE(GEN6_RP_CONTROL, 0);
6192 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6194 I915_WRITE(GEN6_RC_CONTROL, 0);
6195 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6196 I915_WRITE(GEN6_RP_CONTROL, 0);
6199 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6201 I915_WRITE(GEN6_RC_CONTROL, 0);
6204 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6206 /* we're doing forcewake before Disabling RC6,
6207 * This what the BIOS expects when going into suspend */
6208 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6210 I915_WRITE(GEN6_RC_CONTROL, 0);
6212 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6215 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
6217 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6218 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
6219 mode = GEN6_RC_CTL_RC6_ENABLE;
6223 if (HAS_RC6p(dev_priv))
6224 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6225 "RC6 %s RC6p %s RC6pp %s\n",
6226 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
6227 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
6228 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
6231 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6232 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
6235 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6237 struct i915_ggtt *ggtt = &dev_priv->ggtt;
6238 bool enable_rc6 = true;
6239 unsigned long rc6_ctx_base;
6243 rc_ctl = I915_READ(GEN6_RC_CONTROL);
6244 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6245 RC_SW_TARGET_STATE_SHIFT;
6246 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6247 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6248 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6249 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6252 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6253 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6258 * The exact context size is not known for BXT, so assume a page size
6261 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6262 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
6263 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
6264 ggtt->stolen_reserved_size))) {
6265 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6269 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6270 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6271 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6272 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6273 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6277 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6278 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6279 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6280 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6284 if (!I915_READ(GEN6_GFXPAUSE)) {
6285 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6289 if (!I915_READ(GEN8_MISC_CTRL0)) {
6290 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6297 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
6299 /* No RC6 before Ironlake and code is gone for ilk. */
6300 if (INTEL_INFO(dev_priv)->gen < 6)
6306 if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
6307 DRM_INFO("RC6 disabled by BIOS\n");
6311 /* Respect the kernel parameter if it is set */
6312 if (enable_rc6 >= 0) {
6315 if (HAS_RC6p(dev_priv))
6316 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
6319 mask = INTEL_RC6_ENABLE;
6321 if ((enable_rc6 & mask) != enable_rc6)
6322 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6323 "(requested %d, valid %d)\n",
6324 enable_rc6 & mask, enable_rc6, mask);
6326 return enable_rc6 & mask;
6329 if (IS_IVYBRIDGE(dev_priv))
6330 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
6332 return INTEL_RC6_ENABLE;
6335 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6337 /* All of these values are in units of 50MHz */
6339 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6340 if (IS_GEN9_LP(dev_priv)) {
6341 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6342 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
6343 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
6344 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
6346 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6347 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
6348 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
6349 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
6351 /* hw_max = RP0 until we check for overclocking */
6352 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
6354 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
6355 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6356 IS_GEN9_BC(dev_priv)) {
6357 u32 ddcc_status = 0;
6359 if (sandybridge_pcode_read(dev_priv,
6360 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6362 dev_priv->rps.efficient_freq =
6364 ((ddcc_status >> 8) & 0xff),
6365 dev_priv->rps.min_freq,
6366 dev_priv->rps.max_freq);
6369 if (IS_GEN9_BC(dev_priv)) {
6370 /* Store the frequency values in 16.66 MHZ units, which is
6371 * the natural hardware unit for SKL
6373 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
6374 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
6375 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
6376 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
6377 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
6381 static void reset_rps(struct drm_i915_private *dev_priv,
6382 int (*set)(struct drm_i915_private *, u8))
6384 u8 freq = dev_priv->rps.cur_freq;
6387 dev_priv->rps.power = -1;
6388 dev_priv->rps.cur_freq = -1;
6390 if (set(dev_priv, freq))
6391 DRM_ERROR("Failed to reset RPS to initial values\n");
6394 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6395 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6397 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6399 /* Program defaults and thresholds for RPS*/
6400 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6401 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
6403 /* 1 second timeout*/
6404 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6405 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6407 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6409 /* Leaning on the below call to gen6_set_rps to program/setup the
6410 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6411 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6412 reset_rps(dev_priv, gen6_set_rps);
6414 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6417 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6419 struct intel_engine_cs *engine;
6420 enum intel_engine_id id;
6421 uint32_t rc6_mask = 0;
6423 /* 1a: Software RC state - RC0 */
6424 I915_WRITE(GEN6_RC_STATE, 0);
6426 /* 1b: Get forcewake during program sequence. Although the driver
6427 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6428 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6430 /* 2a: Disable RC states. */
6431 I915_WRITE(GEN6_RC_CONTROL, 0);
6433 /* 2b: Program RC6 thresholds.*/
6435 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6436 if (IS_SKYLAKE(dev_priv))
6437 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6439 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6440 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6441 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6442 for_each_engine(engine, dev_priv, id)
6443 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6445 if (HAS_GUC(dev_priv))
6446 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6448 I915_WRITE(GEN6_RC_SLEEP, 0);
6450 /* 2c: Program Coarse Power Gating Policies. */
6451 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
6452 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
6454 /* 3a: Enable RC6 */
6455 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6456 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6457 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
6458 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6459 I915_WRITE(GEN6_RC_CONTROL,
6460 GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
6463 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6464 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6466 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6467 I915_WRITE(GEN9_PG_ENABLE, 0);
6469 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
6470 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
6472 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6475 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6477 struct intel_engine_cs *engine;
6478 enum intel_engine_id id;
6479 uint32_t rc6_mask = 0;
6481 /* 1a: Software RC state - RC0 */
6482 I915_WRITE(GEN6_RC_STATE, 0);
6484 /* 1c & 1d: Get forcewake during program sequence. Although the driver
6485 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6486 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6488 /* 2a: Disable RC states. */
6489 I915_WRITE(GEN6_RC_CONTROL, 0);
6491 /* 2b: Program RC6 thresholds.*/
6492 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6493 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6494 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6495 for_each_engine(engine, dev_priv, id)
6496 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6497 I915_WRITE(GEN6_RC_SLEEP, 0);
6498 if (IS_BROADWELL(dev_priv))
6499 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6501 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6504 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6505 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6506 intel_print_rc6_info(dev_priv, rc6_mask);
6507 if (IS_BROADWELL(dev_priv))
6508 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6509 GEN7_RC_CTL_TO_MODE |
6512 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6513 GEN6_RC_CTL_EI_MODE(1) |
6516 /* 4 Program defaults and thresholds for RPS*/
6517 I915_WRITE(GEN6_RPNSWREQ,
6518 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6519 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6520 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6521 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6522 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6524 /* Docs recommend 900MHz, and 300 MHz respectively */
6525 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6526 dev_priv->rps.max_freq_softlimit << 24 |
6527 dev_priv->rps.min_freq_softlimit << 16);
6529 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6530 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6531 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6532 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6534 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6537 I915_WRITE(GEN6_RP_CONTROL,
6538 GEN6_RP_MEDIA_TURBO |
6539 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6540 GEN6_RP_MEDIA_IS_GFX |
6542 GEN6_RP_UP_BUSY_AVG |
6543 GEN6_RP_DOWN_IDLE_AVG);
6545 /* 6: Ring frequency + overclocking (our driver does this later */
6547 reset_rps(dev_priv, gen6_set_rps);
6549 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6552 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
6554 struct intel_engine_cs *engine;
6555 enum intel_engine_id id;
6556 u32 rc6vids, rc6_mask = 0;
6561 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6563 /* Here begins a magic sequence of register writes to enable
6564 * auto-downclocking.
6566 * Perhaps there might be some value in exposing these to
6569 I915_WRITE(GEN6_RC_STATE, 0);
6571 /* Clear the DBG now so we don't confuse earlier errors */
6572 gtfifodbg = I915_READ(GTFIFODBG);
6574 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6575 I915_WRITE(GTFIFODBG, gtfifodbg);
6578 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6580 /* disable the counters and set deterministic thresholds */
6581 I915_WRITE(GEN6_RC_CONTROL, 0);
6583 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6584 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6585 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6586 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6587 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6589 for_each_engine(engine, dev_priv, id)
6590 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6592 I915_WRITE(GEN6_RC_SLEEP, 0);
6593 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6594 if (IS_IVYBRIDGE(dev_priv))
6595 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
6597 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6598 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
6599 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6601 /* Check if we are enabling RC6 */
6602 rc6_mode = intel_enable_rc6();
6603 if (rc6_mode & INTEL_RC6_ENABLE)
6604 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
6606 /* We don't use those on Haswell */
6607 if (!IS_HASWELL(dev_priv)) {
6608 if (rc6_mode & INTEL_RC6p_ENABLE)
6609 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
6611 if (rc6_mode & INTEL_RC6pp_ENABLE)
6612 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
6615 intel_print_rc6_info(dev_priv, rc6_mask);
6617 I915_WRITE(GEN6_RC_CONTROL,
6619 GEN6_RC_CTL_EI_MODE(1) |
6620 GEN6_RC_CTL_HW_ENABLE);
6622 /* Power down if completely idle for over 50ms */
6623 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
6624 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6626 reset_rps(dev_priv, gen6_set_rps);
6629 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
6630 if (IS_GEN6(dev_priv) && ret) {
6631 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6632 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
6633 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6634 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
6635 rc6vids &= 0xffff00;
6636 rc6vids |= GEN6_ENCODE_RC6_VID(450);
6637 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
6639 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6642 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6645 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
6648 unsigned int gpu_freq;
6649 unsigned int max_ia_freq, min_ring_freq;
6650 unsigned int max_gpu_freq, min_gpu_freq;
6651 int scaling_factor = 180;
6652 struct cpufreq_policy *policy;
6654 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6656 policy = cpufreq_cpu_get(0);
6658 max_ia_freq = policy->cpuinfo.max_freq;
6659 cpufreq_cpu_put(policy);
6662 * Default to measured freq if none found, PCU will ensure we
6665 max_ia_freq = tsc_khz;
6668 /* Convert from kHz to MHz */
6669 max_ia_freq /= 1000;
6671 min_ring_freq = I915_READ(DCLK) & 0xf;
6672 /* convert DDR frequency from units of 266.6MHz to bandwidth */
6673 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
6675 if (IS_GEN9_BC(dev_priv)) {
6676 /* Convert GT frequency to 50 HZ units */
6677 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
6678 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
6680 min_gpu_freq = dev_priv->rps.min_freq;
6681 max_gpu_freq = dev_priv->rps.max_freq;
6685 * For each potential GPU frequency, load a ring frequency we'd like
6686 * to use for memory access. We do this by specifying the IA frequency
6687 * the PCU should use as a reference to determine the ring frequency.
6689 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6690 int diff = max_gpu_freq - gpu_freq;
6691 unsigned int ia_freq = 0, ring_freq = 0;
6693 if (IS_GEN9_BC(dev_priv)) {
6695 * ring_freq = 2 * GT. ring_freq is in 100MHz units
6696 * No floor required for ring frequency on SKL.
6698 ring_freq = gpu_freq;
6699 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
6700 /* max(2 * GT, DDR). NB: GT is 50MHz units */
6701 ring_freq = max(min_ring_freq, gpu_freq);
6702 } else if (IS_HASWELL(dev_priv)) {
6703 ring_freq = mult_frac(gpu_freq, 5, 4);
6704 ring_freq = max(min_ring_freq, ring_freq);
6705 /* leave ia_freq as the default, chosen by cpufreq */
6707 /* On older processors, there is no separate ring
6708 * clock domain, so in order to boost the bandwidth
6709 * of the ring, we need to upclock the CPU (ia_freq).
6711 * For GPU frequencies less than 750MHz,
6712 * just use the lowest ring freq.
6714 if (gpu_freq < min_freq)
6717 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
6718 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
6721 sandybridge_pcode_write(dev_priv,
6722 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
6723 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
6724 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
6729 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
6733 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6735 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
6737 /* (2 * 4) config */
6738 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
6741 /* (2 * 6) config */
6742 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
6745 /* (2 * 8) config */
6747 /* Setting (2 * 8) Min RP0 for any other combination */
6748 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
6752 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
6757 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6761 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6762 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6767 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6771 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6772 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6777 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6781 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6782 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6783 FB_GFX_FREQ_FUSE_MASK);
6788 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
6792 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6794 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
6799 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
6803 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6805 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
6807 rp0 = min_t(u32, rp0, 0xea);
6812 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6816 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
6817 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
6818 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
6819 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
6824 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
6828 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
6830 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6831 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6832 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6833 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6834 * to make sure it matches what Punit accepts.
6836 return max_t(u32, val, 0xc0);
6839 /* Check that the pctx buffer wasn't move under us. */
6840 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
6842 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6844 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
6845 dev_priv->vlv_pctx->stolen->start);
6849 /* Check that the pcbr address is not empty. */
6850 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
6852 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6854 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
6857 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
6859 struct i915_ggtt *ggtt = &dev_priv->ggtt;
6860 unsigned long pctx_paddr, paddr;
6862 int pctx_size = 32*1024;
6864 pcbr = I915_READ(VLV_PCBR);
6865 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
6866 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6867 paddr = (dev_priv->mm.stolen_base +
6868 (ggtt->stolen_size - pctx_size));
6870 pctx_paddr = (paddr & (~4095));
6871 I915_WRITE(VLV_PCBR, pctx_paddr);
6874 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6877 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
6879 struct drm_i915_gem_object *pctx;
6880 unsigned long pctx_paddr;
6882 int pctx_size = 24*1024;
6884 pcbr = I915_READ(VLV_PCBR);
6886 /* BIOS set it up already, grab the pre-alloc'd space */
6889 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
6890 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
6892 I915_GTT_OFFSET_NONE,
6897 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6900 * From the Gunit register HAS:
6901 * The Gfx driver is expected to program this register and ensure
6902 * proper allocation within Gfx stolen memory. For example, this
6903 * register should be programmed such than the PCBR range does not
6904 * overlap with other ranges, such as the frame buffer, protected
6905 * memory, or any other relevant ranges.
6907 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
6909 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6913 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
6914 I915_WRITE(VLV_PCBR, pctx_paddr);
6917 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6918 dev_priv->vlv_pctx = pctx;
6921 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
6923 if (WARN_ON(!dev_priv->vlv_pctx))
6926 i915_gem_object_put(dev_priv->vlv_pctx);
6927 dev_priv->vlv_pctx = NULL;
6930 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
6932 dev_priv->rps.gpll_ref_freq =
6933 vlv_get_cck_clock(dev_priv, "GPLL ref",
6934 CCK_GPLL_CLOCK_CONTROL,
6935 dev_priv->czclk_freq);
6937 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6938 dev_priv->rps.gpll_ref_freq);
6941 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
6945 valleyview_setup_pctx(dev_priv);
6947 vlv_init_gpll_ref_freq(dev_priv);
6949 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6950 switch ((val >> 6) & 3) {
6953 dev_priv->mem_freq = 800;
6956 dev_priv->mem_freq = 1066;
6959 dev_priv->mem_freq = 1333;
6962 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
6964 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
6965 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
6966 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6967 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
6968 dev_priv->rps.max_freq);
6970 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
6971 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
6972 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
6973 dev_priv->rps.efficient_freq);
6975 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
6976 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
6977 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
6978 dev_priv->rps.rp1_freq);
6980 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
6981 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
6982 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
6983 dev_priv->rps.min_freq);
6986 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
6990 cherryview_setup_pctx(dev_priv);
6992 vlv_init_gpll_ref_freq(dev_priv);
6994 mutex_lock(&dev_priv->sb_lock);
6995 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
6996 mutex_unlock(&dev_priv->sb_lock);
6998 switch ((val >> 2) & 0x7) {
7000 dev_priv->mem_freq = 2000;
7003 dev_priv->mem_freq = 1600;
7006 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7008 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
7009 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
7010 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7011 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
7012 dev_priv->rps.max_freq);
7014 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7015 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7016 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
7017 dev_priv->rps.efficient_freq);
7019 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
7020 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7021 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7022 dev_priv->rps.rp1_freq);
7024 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
7025 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7026 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
7027 dev_priv->rps.min_freq);
7029 WARN_ONCE((dev_priv->rps.max_freq |
7030 dev_priv->rps.efficient_freq |
7031 dev_priv->rps.rp1_freq |
7032 dev_priv->rps.min_freq) & 1,
7033 "Odd GPU freq values\n");
7036 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7038 valleyview_cleanup_pctx(dev_priv);
7041 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7043 struct intel_engine_cs *engine;
7044 enum intel_engine_id id;
7045 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
7047 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7049 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7050 GT_FIFO_FREE_ENTRIES_CHV);
7052 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7054 I915_WRITE(GTFIFODBG, gtfifodbg);
7057 cherryview_check_pctx(dev_priv);
7059 /* 1a & 1b: Get forcewake during program sequence. Although the driver
7060 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7061 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7063 /* Disable RC states. */
7064 I915_WRITE(GEN6_RC_CONTROL, 0);
7066 /* 2a: Program RC6 thresholds.*/
7067 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7068 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7069 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7071 for_each_engine(engine, dev_priv, id)
7072 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7073 I915_WRITE(GEN6_RC_SLEEP, 0);
7075 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7076 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7078 /* allows RC6 residency counter to work */
7079 I915_WRITE(VLV_COUNTER_CONTROL,
7080 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7081 VLV_MEDIA_RC6_COUNT_EN |
7082 VLV_RENDER_RC6_COUNT_EN));
7084 /* For now we assume BIOS is allocating and populating the PCBR */
7085 pcbr = I915_READ(VLV_PCBR);
7088 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
7089 (pcbr >> VLV_PCBR_ADDR_SHIFT))
7090 rc6_mode = GEN7_RC_CTL_TO_MODE;
7092 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7094 /* 4 Program defaults and thresholds for RPS*/
7095 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7096 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7097 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7098 I915_WRITE(GEN6_RP_UP_EI, 66000);
7099 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7101 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7104 I915_WRITE(GEN6_RP_CONTROL,
7105 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7106 GEN6_RP_MEDIA_IS_GFX |
7108 GEN6_RP_UP_BUSY_AVG |
7109 GEN6_RP_DOWN_IDLE_AVG);
7111 /* Setting Fixed Bias */
7112 val = VLV_OVERRIDE_EN |
7114 CHV_BIAS_CPU_50_SOC_50;
7115 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7117 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7119 /* RPS code assumes GPLL is used */
7120 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7122 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7123 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7125 reset_rps(dev_priv, valleyview_set_rps);
7127 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7130 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7132 struct intel_engine_cs *engine;
7133 enum intel_engine_id id;
7134 u32 gtfifodbg, val, rc6_mode = 0;
7136 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7138 valleyview_check_pctx(dev_priv);
7140 gtfifodbg = I915_READ(GTFIFODBG);
7142 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7144 I915_WRITE(GTFIFODBG, gtfifodbg);
7147 /* If VLV, Forcewake all wells, else re-direct to regular path */
7148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7150 /* Disable RC states. */
7151 I915_WRITE(GEN6_RC_CONTROL, 0);
7153 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7154 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7155 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7156 I915_WRITE(GEN6_RP_UP_EI, 66000);
7157 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7159 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7161 I915_WRITE(GEN6_RP_CONTROL,
7162 GEN6_RP_MEDIA_TURBO |
7163 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7164 GEN6_RP_MEDIA_IS_GFX |
7166 GEN6_RP_UP_BUSY_AVG |
7167 GEN6_RP_DOWN_IDLE_CONT);
7169 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7170 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7171 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7173 for_each_engine(engine, dev_priv, id)
7174 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7176 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7178 /* allows RC6 residency counter to work */
7179 I915_WRITE(VLV_COUNTER_CONTROL,
7180 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7181 VLV_MEDIA_RC0_COUNT_EN |
7182 VLV_RENDER_RC0_COUNT_EN |
7183 VLV_MEDIA_RC6_COUNT_EN |
7184 VLV_RENDER_RC6_COUNT_EN));
7186 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
7187 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
7189 intel_print_rc6_info(dev_priv, rc6_mode);
7191 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7193 /* Setting Fixed Bias */
7194 val = VLV_OVERRIDE_EN |
7196 VLV_BIAS_CPU_125_SOC_875;
7197 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7199 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7201 /* RPS code assumes GPLL is used */
7202 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7204 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7205 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7207 reset_rps(dev_priv, valleyview_set_rps);
7209 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7212 static unsigned long intel_pxfreq(u32 vidfreq)
7215 int div = (vidfreq & 0x3f0000) >> 16;
7216 int post = (vidfreq & 0x3000) >> 12;
7217 int pre = (vidfreq & 0x7);
7222 freq = ((div * 133333) / ((1<<post) * pre));
7227 static const struct cparams {
7233 { 1, 1333, 301, 28664 },
7234 { 1, 1066, 294, 24460 },
7235 { 1, 800, 294, 25192 },
7236 { 0, 1333, 276, 27605 },
7237 { 0, 1066, 276, 27605 },
7238 { 0, 800, 231, 23784 },
7241 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7243 u64 total_count, diff, ret;
7244 u32 count1, count2, count3, m = 0, c = 0;
7245 unsigned long now = jiffies_to_msecs(jiffies), diff1;
7248 lockdep_assert_held(&mchdev_lock);
7250 diff1 = now - dev_priv->ips.last_time1;
7252 /* Prevent division-by-zero if we are asking too fast.
7253 * Also, we don't get interesting results if we are polling
7254 * faster than once in 10ms, so just return the saved value
7258 return dev_priv->ips.chipset_power;
7260 count1 = I915_READ(DMIEC);
7261 count2 = I915_READ(DDREC);
7262 count3 = I915_READ(CSIEC);
7264 total_count = count1 + count2 + count3;
7266 /* FIXME: handle per-counter overflow */
7267 if (total_count < dev_priv->ips.last_count1) {
7268 diff = ~0UL - dev_priv->ips.last_count1;
7269 diff += total_count;
7271 diff = total_count - dev_priv->ips.last_count1;
7274 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7275 if (cparams[i].i == dev_priv->ips.c_m &&
7276 cparams[i].t == dev_priv->ips.r_t) {
7283 diff = div_u64(diff, diff1);
7284 ret = ((m * diff) + c);
7285 ret = div_u64(ret, 10);
7287 dev_priv->ips.last_count1 = total_count;
7288 dev_priv->ips.last_time1 = now;
7290 dev_priv->ips.chipset_power = ret;
7295 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7299 if (INTEL_INFO(dev_priv)->gen != 5)
7302 spin_lock_irq(&mchdev_lock);
7304 val = __i915_chipset_val(dev_priv);
7306 spin_unlock_irq(&mchdev_lock);
7311 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7313 unsigned long m, x, b;
7316 tsfs = I915_READ(TSFS);
7318 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7319 x = I915_READ8(TR1);
7321 b = tsfs & TSFS_INTR_MASK;
7323 return ((m * x) / 127) - b;
7326 static int _pxvid_to_vd(u8 pxvid)
7331 if (pxvid >= 8 && pxvid < 31)
7334 return (pxvid + 2) * 125;
7337 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7339 const int vd = _pxvid_to_vd(pxvid);
7340 const int vm = vd - 1125;
7342 if (INTEL_INFO(dev_priv)->is_mobile)
7343 return vm > 0 ? vm : 0;
7348 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7350 u64 now, diff, diffms;
7353 lockdep_assert_held(&mchdev_lock);
7355 now = ktime_get_raw_ns();
7356 diffms = now - dev_priv->ips.last_time2;
7357 do_div(diffms, NSEC_PER_MSEC);
7359 /* Don't divide by 0 */
7363 count = I915_READ(GFXEC);
7365 if (count < dev_priv->ips.last_count2) {
7366 diff = ~0UL - dev_priv->ips.last_count2;
7369 diff = count - dev_priv->ips.last_count2;
7372 dev_priv->ips.last_count2 = count;
7373 dev_priv->ips.last_time2 = now;
7375 /* More magic constants... */
7377 diff = div_u64(diff, diffms * 10);
7378 dev_priv->ips.gfx_power = diff;
7381 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7383 if (INTEL_INFO(dev_priv)->gen != 5)
7386 spin_lock_irq(&mchdev_lock);
7388 __i915_update_gfx_val(dev_priv);
7390 spin_unlock_irq(&mchdev_lock);
7393 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7395 unsigned long t, corr, state1, corr2, state2;
7398 lockdep_assert_held(&mchdev_lock);
7400 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
7401 pxvid = (pxvid >> 24) & 0x7f;
7402 ext_v = pvid_to_extvid(dev_priv, pxvid);
7406 t = i915_mch_val(dev_priv);
7408 /* Revel in the empirically derived constants */
7410 /* Correction factor in 1/100000 units */
7412 corr = ((t * 2349) + 135940);
7414 corr = ((t * 964) + 29317);
7416 corr = ((t * 301) + 1004);
7418 corr = corr * ((150142 * state1) / 10000 - 78642);
7420 corr2 = (corr * dev_priv->ips.corr);
7422 state2 = (corr2 * state1) / 10000;
7423 state2 /= 100; /* convert to mW */
7425 __i915_update_gfx_val(dev_priv);
7427 return dev_priv->ips.gfx_power + state2;
7430 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7434 if (INTEL_INFO(dev_priv)->gen != 5)
7437 spin_lock_irq(&mchdev_lock);
7439 val = __i915_gfx_val(dev_priv);
7441 spin_unlock_irq(&mchdev_lock);
7447 * i915_read_mch_val - return value for IPS use
7449 * Calculate and return a value for the IPS driver to use when deciding whether
7450 * we have thermal and power headroom to increase CPU or GPU power budget.
7452 unsigned long i915_read_mch_val(void)
7454 struct drm_i915_private *dev_priv;
7455 unsigned long chipset_val, graphics_val, ret = 0;
7457 spin_lock_irq(&mchdev_lock);
7460 dev_priv = i915_mch_dev;
7462 chipset_val = __i915_chipset_val(dev_priv);
7463 graphics_val = __i915_gfx_val(dev_priv);
7465 ret = chipset_val + graphics_val;
7468 spin_unlock_irq(&mchdev_lock);
7472 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7475 * i915_gpu_raise - raise GPU frequency limit
7477 * Raise the limit; IPS indicates we have thermal headroom.
7479 bool i915_gpu_raise(void)
7481 struct drm_i915_private *dev_priv;
7484 spin_lock_irq(&mchdev_lock);
7485 if (!i915_mch_dev) {
7489 dev_priv = i915_mch_dev;
7491 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7492 dev_priv->ips.max_delay--;
7495 spin_unlock_irq(&mchdev_lock);
7499 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7502 * i915_gpu_lower - lower GPU frequency limit
7504 * IPS indicates we're close to a thermal limit, so throttle back the GPU
7505 * frequency maximum.
7507 bool i915_gpu_lower(void)
7509 struct drm_i915_private *dev_priv;
7512 spin_lock_irq(&mchdev_lock);
7513 if (!i915_mch_dev) {
7517 dev_priv = i915_mch_dev;
7519 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7520 dev_priv->ips.max_delay++;
7523 spin_unlock_irq(&mchdev_lock);
7527 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7530 * i915_gpu_busy - indicate GPU business to IPS
7532 * Tell the IPS driver whether or not the GPU is busy.
7534 bool i915_gpu_busy(void)
7538 spin_lock_irq(&mchdev_lock);
7540 ret = i915_mch_dev->gt.awake;
7541 spin_unlock_irq(&mchdev_lock);
7545 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7548 * i915_gpu_turbo_disable - disable graphics turbo
7550 * Disable graphics turbo by resetting the max frequency and setting the
7551 * current frequency to the default.
7553 bool i915_gpu_turbo_disable(void)
7555 struct drm_i915_private *dev_priv;
7558 spin_lock_irq(&mchdev_lock);
7559 if (!i915_mch_dev) {
7563 dev_priv = i915_mch_dev;
7565 dev_priv->ips.max_delay = dev_priv->ips.fstart;
7567 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
7571 spin_unlock_irq(&mchdev_lock);
7575 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
7578 * Tells the intel_ips driver that the i915 driver is now loaded, if
7579 * IPS got loaded first.
7581 * This awkward dance is so that neither module has to depend on the
7582 * other in order for IPS to do the appropriate communication of
7583 * GPU turbo limits to i915.
7586 ips_ping_for_i915_load(void)
7590 link = symbol_get(ips_link_to_i915_driver);
7593 symbol_put(ips_link_to_i915_driver);
7597 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
7599 /* We only register the i915 ips part with intel-ips once everything is
7600 * set up, to avoid intel-ips sneaking in and reading bogus values. */
7601 spin_lock_irq(&mchdev_lock);
7602 i915_mch_dev = dev_priv;
7603 spin_unlock_irq(&mchdev_lock);
7605 ips_ping_for_i915_load();
7608 void intel_gpu_ips_teardown(void)
7610 spin_lock_irq(&mchdev_lock);
7611 i915_mch_dev = NULL;
7612 spin_unlock_irq(&mchdev_lock);
7615 static void intel_init_emon(struct drm_i915_private *dev_priv)
7621 /* Disable to program */
7625 /* Program energy weights for various events */
7626 I915_WRITE(SDEW, 0x15040d00);
7627 I915_WRITE(CSIEW0, 0x007f0000);
7628 I915_WRITE(CSIEW1, 0x1e220004);
7629 I915_WRITE(CSIEW2, 0x04000004);
7631 for (i = 0; i < 5; i++)
7632 I915_WRITE(PEW(i), 0);
7633 for (i = 0; i < 3; i++)
7634 I915_WRITE(DEW(i), 0);
7636 /* Program P-state weights to account for frequency power adjustment */
7637 for (i = 0; i < 16; i++) {
7638 u32 pxvidfreq = I915_READ(PXVFREQ(i));
7639 unsigned long freq = intel_pxfreq(pxvidfreq);
7640 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7645 val *= (freq / 1000);
7647 val /= (127*127*900);
7649 DRM_ERROR("bad pxval: %ld\n", val);
7652 /* Render standby states get 0 weight */
7656 for (i = 0; i < 4; i++) {
7657 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7658 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7659 I915_WRITE(PXW(i), val);
7662 /* Adjust magic regs to magic values (more experimental results) */
7663 I915_WRITE(OGW0, 0);
7664 I915_WRITE(OGW1, 0);
7665 I915_WRITE(EG0, 0x00007f00);
7666 I915_WRITE(EG1, 0x0000000e);
7667 I915_WRITE(EG2, 0x000e0000);
7668 I915_WRITE(EG3, 0x68000300);
7669 I915_WRITE(EG4, 0x42000000);
7670 I915_WRITE(EG5, 0x00140031);
7674 for (i = 0; i < 8; i++)
7675 I915_WRITE(PXWL(i), 0);
7677 /* Enable PMON + select events */
7678 I915_WRITE(ECR, 0x80000019);
7680 lcfuse = I915_READ(LCFUSE02);
7682 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
7685 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7688 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7691 if (!i915.enable_rc6) {
7692 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7693 intel_runtime_pm_get(dev_priv);
7696 mutex_lock(&dev_priv->drm.struct_mutex);
7697 mutex_lock(&dev_priv->rps.hw_lock);
7699 /* Initialize RPS limits (for userspace) */
7700 if (IS_CHERRYVIEW(dev_priv))
7701 cherryview_init_gt_powersave(dev_priv);
7702 else if (IS_VALLEYVIEW(dev_priv))
7703 valleyview_init_gt_powersave(dev_priv);
7704 else if (INTEL_GEN(dev_priv) >= 6)
7705 gen6_init_rps_frequencies(dev_priv);
7707 /* Derive initial user preferences/limits from the hardware limits */
7708 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
7709 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
7711 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
7712 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
7714 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7715 dev_priv->rps.min_freq_softlimit =
7717 dev_priv->rps.efficient_freq,
7718 intel_freq_opcode(dev_priv, 450));
7720 /* After setting max-softlimit, find the overclock max freq */
7721 if (IS_GEN6(dev_priv) ||
7722 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
7725 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms);
7726 if (params & BIT(31)) { /* OC supported */
7727 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7728 (dev_priv->rps.max_freq & 0xff) * 50,
7729 (params & 0xff) * 50);
7730 dev_priv->rps.max_freq = params & 0xff;
7734 /* Finally allow us to boost to max by default */
7735 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
7737 mutex_unlock(&dev_priv->rps.hw_lock);
7738 mutex_unlock(&dev_priv->drm.struct_mutex);
7740 intel_autoenable_gt_powersave(dev_priv);
7743 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7745 if (IS_VALLEYVIEW(dev_priv))
7746 valleyview_cleanup_gt_powersave(dev_priv);
7748 if (!i915.enable_rc6)
7749 intel_runtime_pm_put(dev_priv);
7753 * intel_suspend_gt_powersave - suspend PM work and helper threads
7754 * @dev_priv: i915 device
7756 * We don't want to disable RC6 or other features here, we just want
7757 * to make sure any work we've queued has finished and won't bother
7758 * us while we're suspended.
7760 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7762 if (INTEL_GEN(dev_priv) < 6)
7765 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
7766 intel_runtime_pm_put(dev_priv);
7768 /* gen6_rps_idle() will be called later to disable interrupts */
7771 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7773 dev_priv->rps.enabled = true; /* force disabling */
7774 intel_disable_gt_powersave(dev_priv);
7776 gen6_reset_rps_interrupts(dev_priv);
7779 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
7781 if (!READ_ONCE(dev_priv->rps.enabled))
7784 mutex_lock(&dev_priv->rps.hw_lock);
7786 if (INTEL_GEN(dev_priv) >= 9) {
7787 gen9_disable_rc6(dev_priv);
7788 gen9_disable_rps(dev_priv);
7789 } else if (IS_CHERRYVIEW(dev_priv)) {
7790 cherryview_disable_rps(dev_priv);
7791 } else if (IS_VALLEYVIEW(dev_priv)) {
7792 valleyview_disable_rps(dev_priv);
7793 } else if (INTEL_GEN(dev_priv) >= 6) {
7794 gen6_disable_rps(dev_priv);
7795 } else if (IS_IRONLAKE_M(dev_priv)) {
7796 ironlake_disable_drps(dev_priv);
7799 dev_priv->rps.enabled = false;
7800 mutex_unlock(&dev_priv->rps.hw_lock);
7803 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
7805 /* We shouldn't be disabling as we submit, so this should be less
7806 * racy than it appears!
7808 if (READ_ONCE(dev_priv->rps.enabled))
7811 /* Powersaving is controlled by the host when inside a VM */
7812 if (intel_vgpu_active(dev_priv))
7815 mutex_lock(&dev_priv->rps.hw_lock);
7817 if (IS_CHERRYVIEW(dev_priv)) {
7818 cherryview_enable_rps(dev_priv);
7819 } else if (IS_VALLEYVIEW(dev_priv)) {
7820 valleyview_enable_rps(dev_priv);
7821 } else if (INTEL_GEN(dev_priv) >= 9) {
7822 gen9_enable_rc6(dev_priv);
7823 gen9_enable_rps(dev_priv);
7824 if (IS_GEN9_BC(dev_priv))
7825 gen6_update_ring_freq(dev_priv);
7826 } else if (IS_BROADWELL(dev_priv)) {
7827 gen8_enable_rps(dev_priv);
7828 gen6_update_ring_freq(dev_priv);
7829 } else if (INTEL_GEN(dev_priv) >= 6) {
7830 gen6_enable_rps(dev_priv);
7831 gen6_update_ring_freq(dev_priv);
7832 } else if (IS_IRONLAKE_M(dev_priv)) {
7833 ironlake_enable_drps(dev_priv);
7834 intel_init_emon(dev_priv);
7837 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
7838 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
7840 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
7841 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
7843 dev_priv->rps.enabled = true;
7844 mutex_unlock(&dev_priv->rps.hw_lock);
7847 static void __intel_autoenable_gt_powersave(struct work_struct *work)
7849 struct drm_i915_private *dev_priv =
7850 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
7851 struct intel_engine_cs *rcs;
7852 struct drm_i915_gem_request *req;
7854 if (READ_ONCE(dev_priv->rps.enabled))
7857 rcs = dev_priv->engine[RCS];
7858 if (rcs->last_retired_context)
7861 if (!rcs->init_context)
7864 mutex_lock(&dev_priv->drm.struct_mutex);
7866 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
7870 if (!i915.enable_execlists && i915_switch_context(req) == 0)
7871 rcs->init_context(req);
7873 /* Mark the device busy, calling intel_enable_gt_powersave() */
7874 i915_add_request(req);
7877 mutex_unlock(&dev_priv->drm.struct_mutex);
7879 intel_runtime_pm_put(dev_priv);
7882 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
7884 if (READ_ONCE(dev_priv->rps.enabled))
7887 if (IS_IRONLAKE_M(dev_priv)) {
7888 ironlake_enable_drps(dev_priv);
7889 intel_init_emon(dev_priv);
7890 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
7892 * PCU communication is slow and this doesn't need to be
7893 * done at any specific time, so do this out of our fast path
7894 * to make resume and init faster.
7896 * We depend on the HW RC6 power context save/restore
7897 * mechanism when entering D3 through runtime PM suspend. So
7898 * disable RPM until RPS/RC6 is properly setup. We can only
7899 * get here via the driver load/system resume/runtime resume
7900 * paths, so the _noresume version is enough (and in case of
7901 * runtime resume it's necessary).
7903 if (queue_delayed_work(dev_priv->wq,
7904 &dev_priv->rps.autoenable_work,
7905 round_jiffies_up_relative(HZ)))
7906 intel_runtime_pm_get_noresume(dev_priv);
7910 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7913 * On Ibex Peak and Cougar Point, we need to disable clock
7914 * gating for the panel power sequencer or it will fail to
7915 * start up when no ports are active.
7917 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7920 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7924 for_each_pipe(dev_priv, pipe) {
7925 I915_WRITE(DSPCNTR(pipe),
7926 I915_READ(DSPCNTR(pipe)) |
7927 DISPPLANE_TRICKLE_FEED_DISABLE);
7929 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
7930 POSTING_READ(DSPSURF(pipe));
7934 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7936 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
7937 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
7938 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
7941 * Don't touch WM1S_LP_EN here.
7942 * Doing so could cause underruns.
7946 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
7948 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7952 * WaFbcDisableDpfcClockGating:ilk
7954 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7955 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7956 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7958 I915_WRITE(PCH_3DCGDIS0,
7959 MARIUNIT_CLOCK_GATE_DISABLE |
7960 SVSMUNIT_CLOCK_GATE_DISABLE);
7961 I915_WRITE(PCH_3DCGDIS1,
7962 VFMUNIT_CLOCK_GATE_DISABLE);
7965 * According to the spec the following bits should be set in
7966 * order to enable memory self-refresh
7967 * The bit 22/21 of 0x42004
7968 * The bit 5 of 0x42020
7969 * The bit 15 of 0x45000
7971 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7972 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7973 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7974 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
7975 I915_WRITE(DISP_ARB_CTL,
7976 (I915_READ(DISP_ARB_CTL) |
7979 ilk_init_lp_watermarks(dev_priv);
7982 * Based on the document from hardware guys the following bits
7983 * should be set unconditionally in order to enable FBC.
7984 * The bit 22 of 0x42000
7985 * The bit 22 of 0x42004
7986 * The bit 7,8,9 of 0x42020.
7988 if (IS_IRONLAKE_M(dev_priv)) {
7989 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7990 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7991 I915_READ(ILK_DISPLAY_CHICKEN1) |
7993 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7994 I915_READ(ILK_DISPLAY_CHICKEN2) |
7998 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8000 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8001 I915_READ(ILK_DISPLAY_CHICKEN2) |
8002 ILK_ELPIN_409_SELECT);
8003 I915_WRITE(_3D_CHICKEN2,
8004 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8005 _3D_CHICKEN2_WM_READ_PIPELINED);
8007 /* WaDisableRenderCachePipelinedFlush:ilk */
8008 I915_WRITE(CACHE_MODE_0,
8009 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8011 /* WaDisable_RenderCache_OperationalFlush:ilk */
8012 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8014 g4x_disable_trickle_feed(dev_priv);
8016 ibx_init_clock_gating(dev_priv);
8019 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8025 * On Ibex Peak and Cougar Point, we need to disable clock
8026 * gating for the panel power sequencer or it will fail to
8027 * start up when no ports are active.
8029 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8030 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8031 PCH_CPUNIT_CLOCK_GATE_DISABLE);
8032 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8033 DPLS_EDP_PPS_FIX_DIS);
8034 /* The below fixes the weird display corruption, a few pixels shifted
8035 * downward, on (only) LVDS of some HP laptops with IVY.
8037 for_each_pipe(dev_priv, pipe) {
8038 val = I915_READ(TRANS_CHICKEN2(pipe));
8039 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8040 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8041 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8042 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8043 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8044 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8045 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8046 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8048 /* WADP0ClockGatingDisable */
8049 for_each_pipe(dev_priv, pipe) {
8050 I915_WRITE(TRANS_CHICKEN1(pipe),
8051 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8055 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8059 tmp = I915_READ(MCH_SSKPD);
8060 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8061 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8065 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8067 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8069 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8071 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8072 I915_READ(ILK_DISPLAY_CHICKEN2) |
8073 ILK_ELPIN_409_SELECT);
8075 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8076 I915_WRITE(_3D_CHICKEN,
8077 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8079 /* WaDisable_RenderCache_OperationalFlush:snb */
8080 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8083 * BSpec recoomends 8x4 when MSAA is used,
8084 * however in practice 16x4 seems fastest.
8086 * Note that PS/WM thread counts depend on the WIZ hashing
8087 * disable bit, which we don't touch here, but it's good
8088 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8090 I915_WRITE(GEN6_GT_MODE,
8091 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8093 ilk_init_lp_watermarks(dev_priv);
8095 I915_WRITE(CACHE_MODE_0,
8096 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8098 I915_WRITE(GEN6_UCGCTL1,
8099 I915_READ(GEN6_UCGCTL1) |
8100 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8101 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8103 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8104 * gating disable must be set. Failure to set it results in
8105 * flickering pixels due to Z write ordering failures after
8106 * some amount of runtime in the Mesa "fire" demo, and Unigine
8107 * Sanctuary and Tropics, and apparently anything else with
8108 * alpha test or pixel discard.
8110 * According to the spec, bit 11 (RCCUNIT) must also be set,
8111 * but we didn't debug actual testcases to find it out.
8113 * WaDisableRCCUnitClockGating:snb
8114 * WaDisableRCPBUnitClockGating:snb
8116 I915_WRITE(GEN6_UCGCTL2,
8117 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8118 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8120 /* WaStripsFansDisableFastClipPerformanceFix:snb */
8121 I915_WRITE(_3D_CHICKEN3,
8122 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8126 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8127 * 3DSTATE_SF number of SF output attributes is more than 16."
8129 I915_WRITE(_3D_CHICKEN3,
8130 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8133 * According to the spec the following bits should be
8134 * set in order to enable memory self-refresh and fbc:
8135 * The bit21 and bit22 of 0x42000
8136 * The bit21 and bit22 of 0x42004
8137 * The bit5 and bit7 of 0x42020
8138 * The bit14 of 0x70180
8139 * The bit14 of 0x71180
8141 * WaFbcAsynchFlipDisableFbcQueue:snb
8143 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8144 I915_READ(ILK_DISPLAY_CHICKEN1) |
8145 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8146 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8147 I915_READ(ILK_DISPLAY_CHICKEN2) |
8148 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8149 I915_WRITE(ILK_DSPCLK_GATE_D,
8150 I915_READ(ILK_DSPCLK_GATE_D) |
8151 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
8152 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8154 g4x_disable_trickle_feed(dev_priv);
8156 cpt_init_clock_gating(dev_priv);
8158 gen6_check_mch_setup(dev_priv);
8161 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8163 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8166 * WaVSThreadDispatchOverride:ivb,vlv
8168 * This actually overrides the dispatch
8169 * mode for all thread types.
8171 reg &= ~GEN7_FF_SCHED_MASK;
8172 reg |= GEN7_FF_TS_SCHED_HW;
8173 reg |= GEN7_FF_VS_SCHED_HW;
8174 reg |= GEN7_FF_DS_SCHED_HW;
8176 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8179 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8182 * TODO: this bit should only be enabled when really needed, then
8183 * disabled when not needed anymore in order to save power.
8185 if (HAS_PCH_LPT_LP(dev_priv))
8186 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8187 I915_READ(SOUTH_DSPCLK_GATE_D) |
8188 PCH_LP_PARTITION_LEVEL_DISABLE);
8190 /* WADPOClockGatingDisable:hsw */
8191 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8192 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8193 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8196 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8198 if (HAS_PCH_LPT_LP(dev_priv)) {
8199 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8201 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8202 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8206 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8207 int general_prio_credits,
8208 int high_prio_credits)
8212 /* WaTempDisableDOPClkGating:bdw */
8213 misccpctl = I915_READ(GEN7_MISCCPCTL);
8214 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8216 I915_WRITE(GEN8_L3SQCREG1,
8217 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
8218 L3_HIGH_PRIO_CREDITS(high_prio_credits));
8221 * Wait at least 100 clocks before re-enabling clock gating.
8222 * See the definition of L3SQCREG1 in BSpec.
8224 POSTING_READ(GEN8_L3SQCREG1);
8226 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8229 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
8231 gen9_init_clock_gating(dev_priv);
8233 /* WaDisableSDEUnitClockGating:kbl */
8234 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8235 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8236 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8238 /* WaDisableGamClockGating:kbl */
8239 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8240 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8241 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8243 /* WaFbcNukeOnHostModify:kbl,cfl */
8244 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8245 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8248 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
8250 gen9_init_clock_gating(dev_priv);
8252 /* WAC6entrylatency:skl */
8253 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8254 FBC_LLC_FULLY_OPEN);
8256 /* WaFbcNukeOnHostModify:skl */
8257 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8258 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8261 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
8265 ilk_init_lp_watermarks(dev_priv);
8267 /* WaSwitchSolVfFArbitrationPriority:bdw */
8268 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8270 /* WaPsrDPAMaskVBlankInSRD:bdw */
8271 I915_WRITE(CHICKEN_PAR1_1,
8272 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8274 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8275 for_each_pipe(dev_priv, pipe) {
8276 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8277 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8278 BDW_DPRS_MASK_VBLANK_SRD);
8281 /* WaVSRefCountFullforceMissDisable:bdw */
8282 /* WaDSRefCountFullforceMissDisable:bdw */
8283 I915_WRITE(GEN7_FF_THREAD_MODE,
8284 I915_READ(GEN7_FF_THREAD_MODE) &
8285 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8287 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8288 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8290 /* WaDisableSDEUnitClockGating:bdw */
8291 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8292 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8294 /* WaProgramL3SqcReg1Default:bdw */
8295 gen8_set_l3sqc_credits(dev_priv, 30, 2);
8298 * WaGttCachingOffByDefault:bdw
8299 * GTT cache may not work with big pages, so if those
8300 * are ever enabled GTT cache may need to be disabled.
8302 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8304 /* WaKVMNotificationOnConfigChange:bdw */
8305 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8306 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8308 lpt_init_clock_gating(dev_priv);
8310 /* WaDisableDopClockGating:bdw
8312 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8315 I915_WRITE(GEN6_UCGCTL1,
8316 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8319 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
8321 ilk_init_lp_watermarks(dev_priv);
8323 /* L3 caching of data atomics doesn't work -- disable it. */
8324 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8325 I915_WRITE(HSW_ROW_CHICKEN3,
8326 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8328 /* This is required by WaCatErrorRejectionIssue:hsw */
8329 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8330 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8331 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8333 /* WaVSRefCountFullforceMissDisable:hsw */
8334 I915_WRITE(GEN7_FF_THREAD_MODE,
8335 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8337 /* WaDisable_RenderCache_OperationalFlush:hsw */
8338 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8340 /* enable HiZ Raw Stall Optimization */
8341 I915_WRITE(CACHE_MODE_0_GEN7,
8342 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8344 /* WaDisable4x2SubspanOptimization:hsw */
8345 I915_WRITE(CACHE_MODE_1,
8346 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8349 * BSpec recommends 8x4 when MSAA is used,
8350 * however in practice 16x4 seems fastest.
8352 * Note that PS/WM thread counts depend on the WIZ hashing
8353 * disable bit, which we don't touch here, but it's good
8354 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8356 I915_WRITE(GEN7_GT_MODE,
8357 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8359 /* WaSampleCChickenBitEnable:hsw */
8360 I915_WRITE(HALF_SLICE_CHICKEN3,
8361 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8363 /* WaSwitchSolVfFArbitrationPriority:hsw */
8364 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8366 /* WaRsPkgCStateDisplayPMReq:hsw */
8367 I915_WRITE(CHICKEN_PAR1_1,
8368 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
8370 lpt_init_clock_gating(dev_priv);
8373 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
8377 ilk_init_lp_watermarks(dev_priv);
8379 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8381 /* WaDisableEarlyCull:ivb */
8382 I915_WRITE(_3D_CHICKEN3,
8383 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8385 /* WaDisableBackToBackFlipFix:ivb */
8386 I915_WRITE(IVB_CHICKEN3,
8387 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8388 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8390 /* WaDisablePSDDualDispatchEnable:ivb */
8391 if (IS_IVB_GT1(dev_priv))
8392 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8393 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8395 /* WaDisable_RenderCache_OperationalFlush:ivb */
8396 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8398 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8399 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8400 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8402 /* WaApplyL3ControlAndL3ChickenMode:ivb */
8403 I915_WRITE(GEN7_L3CNTLREG1,
8404 GEN7_WA_FOR_GEN7_L3_CONTROL);
8405 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8406 GEN7_WA_L3_CHICKEN_MODE);
8407 if (IS_IVB_GT1(dev_priv))
8408 I915_WRITE(GEN7_ROW_CHICKEN2,
8409 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8411 /* must write both registers */
8412 I915_WRITE(GEN7_ROW_CHICKEN2,
8413 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8414 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8415 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8418 /* WaForceL3Serialization:ivb */
8419 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8420 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8423 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8424 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8426 I915_WRITE(GEN6_UCGCTL2,
8427 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8429 /* This is required by WaCatErrorRejectionIssue:ivb */
8430 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8431 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8432 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8434 g4x_disable_trickle_feed(dev_priv);
8436 gen7_setup_fixed_func_scheduler(dev_priv);
8438 if (0) { /* causes HiZ corruption on ivb:gt1 */
8439 /* enable HiZ Raw Stall Optimization */
8440 I915_WRITE(CACHE_MODE_0_GEN7,
8441 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8444 /* WaDisable4x2SubspanOptimization:ivb */
8445 I915_WRITE(CACHE_MODE_1,
8446 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8449 * BSpec recommends 8x4 when MSAA is used,
8450 * however in practice 16x4 seems fastest.
8452 * Note that PS/WM thread counts depend on the WIZ hashing
8453 * disable bit, which we don't touch here, but it's good
8454 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8456 I915_WRITE(GEN7_GT_MODE,
8457 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8459 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8460 snpcr &= ~GEN6_MBC_SNPCR_MASK;
8461 snpcr |= GEN6_MBC_SNPCR_MED;
8462 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8464 if (!HAS_PCH_NOP(dev_priv))
8465 cpt_init_clock_gating(dev_priv);
8467 gen6_check_mch_setup(dev_priv);
8470 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
8472 /* WaDisableEarlyCull:vlv */
8473 I915_WRITE(_3D_CHICKEN3,
8474 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8476 /* WaDisableBackToBackFlipFix:vlv */
8477 I915_WRITE(IVB_CHICKEN3,
8478 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8479 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8481 /* WaPsdDispatchEnable:vlv */
8482 /* WaDisablePSDDualDispatchEnable:vlv */
8483 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8484 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8485 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8487 /* WaDisable_RenderCache_OperationalFlush:vlv */
8488 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8490 /* WaForceL3Serialization:vlv */
8491 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8492 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8494 /* WaDisableDopClockGating:vlv */
8495 I915_WRITE(GEN7_ROW_CHICKEN2,
8496 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8498 /* This is required by WaCatErrorRejectionIssue:vlv */
8499 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8500 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8501 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8503 gen7_setup_fixed_func_scheduler(dev_priv);
8506 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8507 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8509 I915_WRITE(GEN6_UCGCTL2,
8510 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8512 /* WaDisableL3Bank2xClockGate:vlv
8513 * Disabling L3 clock gating- MMIO 940c[25] = 1
8514 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8515 I915_WRITE(GEN7_UCGCTL4,
8516 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
8519 * BSpec says this must be set, even though
8520 * WaDisable4x2SubspanOptimization isn't listed for VLV.
8522 I915_WRITE(CACHE_MODE_1,
8523 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8526 * BSpec recommends 8x4 when MSAA is used,
8527 * however in practice 16x4 seems fastest.
8529 * Note that PS/WM thread counts depend on the WIZ hashing
8530 * disable bit, which we don't touch here, but it's good
8531 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8533 I915_WRITE(GEN7_GT_MODE,
8534 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8537 * WaIncreaseL3CreditsForVLVB0:vlv
8538 * This is the hardware default actually.
8540 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
8543 * WaDisableVLVClockGating_VBIIssue:vlv
8544 * Disable clock gating on th GCFG unit to prevent a delay
8545 * in the reporting of vblank events.
8547 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8550 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
8552 /* WaVSRefCountFullforceMissDisable:chv */
8553 /* WaDSRefCountFullforceMissDisable:chv */
8554 I915_WRITE(GEN7_FF_THREAD_MODE,
8555 I915_READ(GEN7_FF_THREAD_MODE) &
8556 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8558 /* WaDisableSemaphoreAndSyncFlipWait:chv */
8559 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8560 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8562 /* WaDisableCSUnitClockGating:chv */
8563 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8564 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8566 /* WaDisableSDEUnitClockGating:chv */
8567 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8568 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8571 * WaProgramL3SqcReg1Default:chv
8572 * See gfxspecs/Related Documents/Performance Guide/
8573 * LSQC Setting Recommendations.
8575 gen8_set_l3sqc_credits(dev_priv, 38, 2);
8578 * GTT cache may not work with big pages, so if those
8579 * are ever enabled GTT cache may need to be disabled.
8581 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8584 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8586 uint32_t dspclk_gate;
8588 I915_WRITE(RENCLK_GATE_D1, 0);
8589 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8590 GS_UNIT_CLOCK_GATE_DISABLE |
8591 CL_UNIT_CLOCK_GATE_DISABLE);
8592 I915_WRITE(RAMCLK_GATE_D, 0);
8593 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8594 OVRUNIT_CLOCK_GATE_DISABLE |
8595 OVCUNIT_CLOCK_GATE_DISABLE;
8596 if (IS_GM45(dev_priv))
8597 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8598 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8600 /* WaDisableRenderCachePipelinedFlush */
8601 I915_WRITE(CACHE_MODE_0,
8602 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8604 /* WaDisable_RenderCache_OperationalFlush:g4x */
8605 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8607 g4x_disable_trickle_feed(dev_priv);
8610 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
8612 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8613 I915_WRITE(RENCLK_GATE_D2, 0);
8614 I915_WRITE(DSPCLK_GATE_D, 0);
8615 I915_WRITE(RAMCLK_GATE_D, 0);
8616 I915_WRITE16(DEUC, 0);
8617 I915_WRITE(MI_ARB_STATE,
8618 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8620 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8621 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8624 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
8626 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8627 I965_RCC_CLOCK_GATE_DISABLE |
8628 I965_RCPB_CLOCK_GATE_DISABLE |
8629 I965_ISC_CLOCK_GATE_DISABLE |
8630 I965_FBC_CLOCK_GATE_DISABLE);
8631 I915_WRITE(RENCLK_GATE_D2, 0);
8632 I915_WRITE(MI_ARB_STATE,
8633 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8635 /* WaDisable_RenderCache_OperationalFlush:gen4 */
8636 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8639 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
8641 u32 dstate = I915_READ(D_STATE);
8643 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8644 DSTATE_DOT_CLOCK_GATING;
8645 I915_WRITE(D_STATE, dstate);
8647 if (IS_PINEVIEW(dev_priv))
8648 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
8650 /* IIR "flip pending" means done if this bit is set */
8651 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
8653 /* interrupts should cause a wake up from C3 */
8654 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
8656 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8657 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
8659 I915_WRITE(MI_ARB_STATE,
8660 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8663 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
8665 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8667 /* interrupts should cause a wake up from C3 */
8668 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
8669 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
8671 I915_WRITE(MEM_MODE,
8672 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
8675 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
8677 I915_WRITE(MEM_MODE,
8678 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
8679 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
8682 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
8684 dev_priv->display.init_clock_gating(dev_priv);
8687 void intel_suspend_hw(struct drm_i915_private *dev_priv)
8689 if (HAS_PCH_LPT(dev_priv))
8690 lpt_suspend_hw(dev_priv);
8693 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
8695 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
8699 * intel_init_clock_gating_hooks - setup the clock gating hooks
8700 * @dev_priv: device private
8702 * Setup the hooks that configure which clocks of a given platform can be
8703 * gated and also apply various GT and display specific workarounds for these
8704 * platforms. Note that some GT specific workarounds are applied separately
8705 * when GPU contexts or batchbuffers start their execution.
8707 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
8709 if (IS_SKYLAKE(dev_priv))
8710 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
8711 else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
8712 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
8713 else if (IS_BROXTON(dev_priv))
8714 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
8715 else if (IS_GEMINILAKE(dev_priv))
8716 dev_priv->display.init_clock_gating = glk_init_clock_gating;
8717 else if (IS_BROADWELL(dev_priv))
8718 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
8719 else if (IS_CHERRYVIEW(dev_priv))
8720 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
8721 else if (IS_HASWELL(dev_priv))
8722 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
8723 else if (IS_IVYBRIDGE(dev_priv))
8724 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8725 else if (IS_VALLEYVIEW(dev_priv))
8726 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
8727 else if (IS_GEN6(dev_priv))
8728 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8729 else if (IS_GEN5(dev_priv))
8730 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8731 else if (IS_G4X(dev_priv))
8732 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8733 else if (IS_I965GM(dev_priv))
8734 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8735 else if (IS_I965G(dev_priv))
8736 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8737 else if (IS_GEN3(dev_priv))
8738 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8739 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
8740 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8741 else if (IS_GEN2(dev_priv))
8742 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8744 MISSING_CASE(INTEL_DEVID(dev_priv));
8745 dev_priv->display.init_clock_gating = nop_init_clock_gating;
8749 /* Set up chip specific power management-related functions */
8750 void intel_init_pm(struct drm_i915_private *dev_priv)
8752 intel_fbc_init(dev_priv);
8755 if (IS_PINEVIEW(dev_priv))
8756 i915_pineview_get_mem_freq(dev_priv);
8757 else if (IS_GEN5(dev_priv))
8758 i915_ironlake_get_mem_freq(dev_priv);
8760 /* For FIFO watermark updates */
8761 if (INTEL_GEN(dev_priv) >= 9) {
8762 skl_setup_wm_latency(dev_priv);
8763 dev_priv->display.initial_watermarks = skl_initial_wm;
8764 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
8765 dev_priv->display.compute_global_watermarks = skl_compute_wm;
8766 } else if (HAS_PCH_SPLIT(dev_priv)) {
8767 ilk_setup_wm_latency(dev_priv);
8769 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
8770 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
8771 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
8772 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
8773 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
8774 dev_priv->display.compute_intermediate_wm =
8775 ilk_compute_intermediate_wm;
8776 dev_priv->display.initial_watermarks =
8777 ilk_initial_watermarks;
8778 dev_priv->display.optimize_watermarks =
8779 ilk_optimize_watermarks;
8781 DRM_DEBUG_KMS("Failed to read display plane latency. "
8784 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8785 vlv_setup_wm_latency(dev_priv);
8786 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
8787 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
8788 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
8789 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
8790 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
8791 } else if (IS_G4X(dev_priv)) {
8792 g4x_setup_wm_latency(dev_priv);
8793 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
8794 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
8795 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
8796 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
8797 } else if (IS_PINEVIEW(dev_priv)) {
8798 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
8801 dev_priv->mem_freq)) {
8802 DRM_INFO("failed to find known CxSR latency "
8803 "(found ddr%s fsb freq %d, mem freq %d), "
8805 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8806 dev_priv->fsb_freq, dev_priv->mem_freq);
8807 /* Disable CxSR and never update its watermark again */
8808 intel_set_memory_cxsr(dev_priv, false);
8809 dev_priv->display.update_wm = NULL;
8811 dev_priv->display.update_wm = pineview_update_wm;
8812 } else if (IS_GEN4(dev_priv)) {
8813 dev_priv->display.update_wm = i965_update_wm;
8814 } else if (IS_GEN3(dev_priv)) {
8815 dev_priv->display.update_wm = i9xx_update_wm;
8816 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8817 } else if (IS_GEN2(dev_priv)) {
8818 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
8819 dev_priv->display.update_wm = i845_update_wm;
8820 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8822 dev_priv->display.update_wm = i9xx_update_wm;
8823 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8826 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8830 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
8833 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8836 case GEN6_PCODE_SUCCESS:
8838 case GEN6_PCODE_UNIMPLEMENTED_CMD:
8839 case GEN6_PCODE_ILLEGAL_CMD:
8841 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8842 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8844 case GEN6_PCODE_TIMEOUT:
8847 MISSING_CASE(flags);
8852 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
8855 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8858 case GEN6_PCODE_SUCCESS:
8860 case GEN6_PCODE_ILLEGAL_CMD:
8862 case GEN7_PCODE_TIMEOUT:
8864 case GEN7_PCODE_ILLEGAL_DATA:
8866 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8869 MISSING_CASE(flags);
8874 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
8878 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8880 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8881 * use te fw I915_READ variants to reduce the amount of work
8882 * required when reading/writing.
8885 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8886 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
8890 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
8891 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8892 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8894 if (__intel_wait_for_register_fw(dev_priv,
8895 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8897 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
8901 *val = I915_READ_FW(GEN6_PCODE_DATA);
8902 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8904 if (INTEL_GEN(dev_priv) > 6)
8905 status = gen7_check_mailbox_status(dev_priv);
8907 status = gen6_check_mailbox_status(dev_priv);
8910 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
8918 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
8923 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8925 /* GEN6_PCODE_* are outside of the forcewake domain, we can
8926 * use te fw I915_READ variants to reduce the amount of work
8927 * required when reading/writing.
8930 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8931 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
8935 I915_WRITE_FW(GEN6_PCODE_DATA, val);
8936 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8937 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8939 if (__intel_wait_for_register_fw(dev_priv,
8940 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8942 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
8946 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8948 if (INTEL_GEN(dev_priv) > 6)
8949 status = gen7_check_mailbox_status(dev_priv);
8951 status = gen6_check_mailbox_status(dev_priv);
8954 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
8962 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
8963 u32 request, u32 reply_mask, u32 reply,
8968 *status = sandybridge_pcode_read(dev_priv, mbox, &val);
8970 return *status || ((val & reply_mask) == reply);
8974 * skl_pcode_request - send PCODE request until acknowledgment
8975 * @dev_priv: device private
8976 * @mbox: PCODE mailbox ID the request is targeted for
8977 * @request: request ID
8978 * @reply_mask: mask used to check for request acknowledgment
8979 * @reply: value used to check for request acknowledgment
8980 * @timeout_base_ms: timeout for polling with preemption enabled
8982 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
8983 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
8984 * The request is acknowledged once the PCODE reply dword equals @reply after
8985 * applying @reply_mask. Polling is first attempted with preemption enabled
8986 * for @timeout_base_ms and if this times out for another 50 ms with
8987 * preemption disabled.
8989 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
8990 * other error as reported by PCODE.
8992 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
8993 u32 reply_mask, u32 reply, int timeout_base_ms)
8998 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
9000 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9004 * Prime the PCODE by doing a request first. Normally it guarantees
9005 * that a subsequent request, at most @timeout_base_ms later, succeeds.
9006 * _wait_for() doesn't guarantee when its passed condition is evaluated
9007 * first, so send the first request explicitly.
9013 ret = _wait_for(COND, timeout_base_ms * 1000, 10);
9018 * The above can time out if the number of requests was low (2 in the
9019 * worst case) _and_ PCODE was busy for some reason even after a
9020 * (queued) request and @timeout_base_ms delay. As a workaround retry
9021 * the poll with preemption disabled to maximize the number of
9022 * requests. Increase the timeout from @timeout_base_ms to 50ms to
9023 * account for interrupts that could reduce the number of these
9024 * requests, and for any quirks of the PCODE firmware that delays
9025 * the request completion.
9027 DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9028 WARN_ON_ONCE(timeout_base_ms > 3);
9030 ret = wait_for_atomic(COND, 50);
9034 return ret ? ret : status;
9038 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9042 * Slow = Fast = GPLL ref * N
9044 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
9047 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9049 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
9052 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9056 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9058 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
9061 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9063 /* CHV needs even values */
9064 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
9067 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9069 if (IS_GEN9(dev_priv))
9070 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9072 else if (IS_CHERRYVIEW(dev_priv))
9073 return chv_gpu_freq(dev_priv, val);
9074 else if (IS_VALLEYVIEW(dev_priv))
9075 return byt_gpu_freq(dev_priv, val);
9077 return val * GT_FREQUENCY_MULTIPLIER;
9080 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9082 if (IS_GEN9(dev_priv))
9083 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9084 GT_FREQUENCY_MULTIPLIER);
9085 else if (IS_CHERRYVIEW(dev_priv))
9086 return chv_freq_opcode(dev_priv, val);
9087 else if (IS_VALLEYVIEW(dev_priv))
9088 return byt_freq_opcode(dev_priv, val);
9090 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9093 struct request_boost {
9094 struct work_struct work;
9095 struct drm_i915_gem_request *req;
9098 static void __intel_rps_boost_work(struct work_struct *work)
9100 struct request_boost *boost = container_of(work, struct request_boost, work);
9101 struct drm_i915_gem_request *req = boost->req;
9103 if (!i915_gem_request_completed(req))
9104 gen6_rps_boost(req, NULL);
9106 i915_gem_request_put(req);
9110 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
9112 struct request_boost *boost;
9114 if (req == NULL || INTEL_GEN(req->i915) < 6)
9117 if (i915_gem_request_completed(req))
9120 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
9124 boost->req = i915_gem_request_get(req);
9126 INIT_WORK(&boost->work, __intel_rps_boost_work);
9127 queue_work(req->i915->wq, &boost->work);
9130 void intel_pm_setup(struct drm_i915_private *dev_priv)
9132 mutex_init(&dev_priv->rps.hw_lock);
9134 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
9135 __intel_autoenable_gt_powersave);
9136 atomic_set(&dev_priv->rps.num_waiters, 0);
9138 dev_priv->pm.suspended = false;
9139 atomic_set(&dev_priv->pm.wakeref_count, 0);
9142 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9143 const i915_reg_t reg)
9145 u32 lower, upper, tmp;
9148 /* The register accessed do not need forcewake. We borrow
9149 * uncore lock to prevent concurrent access to range reg.
9151 spin_lock_irq(&dev_priv->uncore.lock);
9153 /* vlv and chv residency counters are 40 bits in width.
9154 * With a control bit, we can choose between upper or lower
9155 * 32bit window into this counter.
9157 * Although we always use the counter in high-range mode elsewhere,
9158 * userspace may attempt to read the value before rc6 is initialised,
9159 * before we have set the default VLV_COUNTER_CONTROL value. So always
9160 * set the high bit to be safe.
9162 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9163 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9164 upper = I915_READ_FW(reg);
9168 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9169 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9170 lower = I915_READ_FW(reg);
9172 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9173 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9174 upper = I915_READ_FW(reg);
9175 } while (upper != tmp && --loop);
9177 /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9178 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9182 spin_unlock_irq(&dev_priv->uncore.lock);
9184 return lower | (u64)upper << 8;
9187 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9188 const i915_reg_t reg)
9190 u64 time_hw, units, div;
9192 if (!intel_enable_rc6())
9195 intel_runtime_pm_get(dev_priv);
9197 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9198 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9200 div = dev_priv->czclk_freq;
9202 time_hw = vlv_residency_raw(dev_priv, reg);
9203 } else if (IS_GEN9_LP(dev_priv)) {
9205 div = 1200; /* 833.33ns */
9207 time_hw = I915_READ(reg);
9209 units = 128000; /* 1.28us */
9212 time_hw = I915_READ(reg);
9215 intel_runtime_pm_put(dev_priv);
9216 return DIV_ROUND_UP_ULL(time_hw * units, div);