2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
27 #include <linux/seq_file.h>
28 #include <linux/circ_buf.h>
29 #include <linux/ctype.h>
30 #include <linux/debugfs.h>
31 #include "intel_drv.h"
33 static const char * const pipe_crc_sources[] = {
46 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
49 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
50 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
53 case INTEL_PIPE_CRC_SOURCE_PIPE:
54 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
56 case INTEL_PIPE_CRC_SOURCE_NONE:
66 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
68 enum intel_pipe_crc_source *source)
70 struct drm_device *dev = &dev_priv->drm;
71 struct intel_encoder *encoder;
72 struct intel_crtc *crtc;
73 struct intel_digital_port *dig_port;
76 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
78 drm_modeset_lock_all(dev);
79 for_each_intel_encoder(dev, encoder) {
80 if (!encoder->base.crtc)
83 crtc = to_intel_crtc(encoder->base.crtc);
85 if (crtc->pipe != pipe)
88 switch (encoder->type) {
89 case INTEL_OUTPUT_TVOUT:
90 *source = INTEL_PIPE_CRC_SOURCE_TV;
93 case INTEL_OUTPUT_EDP:
94 dig_port = enc_to_dig_port(&encoder->base);
95 switch (dig_port->base.port) {
97 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
100 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
103 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
106 WARN(1, "nonexisting DP port %c\n",
107 port_name(dig_port->base.port));
115 drm_modeset_unlock_all(dev);
120 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
122 enum intel_pipe_crc_source *source,
125 bool need_stable_symbols = false;
127 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
128 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
134 case INTEL_PIPE_CRC_SOURCE_PIPE:
135 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
137 case INTEL_PIPE_CRC_SOURCE_DP_B:
138 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
139 need_stable_symbols = true;
141 case INTEL_PIPE_CRC_SOURCE_DP_C:
142 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
143 need_stable_symbols = true;
145 case INTEL_PIPE_CRC_SOURCE_DP_D:
146 if (!IS_CHERRYVIEW(dev_priv))
148 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
149 need_stable_symbols = true;
151 case INTEL_PIPE_CRC_SOURCE_NONE:
159 * When the pipe CRC tap point is after the transcoders we need
160 * to tweak symbol-level features to produce a deterministic series of
161 * symbols for a given frame. We need to reset those features only once
162 * a frame (instead of every nth symbol):
163 * - DC-balance: used to ensure a better clock recovery from the data
165 * - DisplayPort scrambling: used for EMI reduction
167 if (need_stable_symbols) {
168 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
170 tmp |= DC_BALANCE_RESET_VLV;
173 tmp |= PIPE_A_SCRAMBLE_RESET;
176 tmp |= PIPE_B_SCRAMBLE_RESET;
179 tmp |= PIPE_C_SCRAMBLE_RESET;
184 I915_WRITE(PORT_DFT2_G4X, tmp);
190 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
192 enum intel_pipe_crc_source *source,
195 bool need_stable_symbols = false;
197 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
198 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
204 case INTEL_PIPE_CRC_SOURCE_PIPE:
205 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
207 case INTEL_PIPE_CRC_SOURCE_TV:
208 if (!SUPPORTS_TV(dev_priv))
210 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
212 case INTEL_PIPE_CRC_SOURCE_DP_B:
213 if (!IS_G4X(dev_priv))
215 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
216 need_stable_symbols = true;
218 case INTEL_PIPE_CRC_SOURCE_DP_C:
219 if (!IS_G4X(dev_priv))
221 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
222 need_stable_symbols = true;
224 case INTEL_PIPE_CRC_SOURCE_DP_D:
225 if (!IS_G4X(dev_priv))
227 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
228 need_stable_symbols = true;
230 case INTEL_PIPE_CRC_SOURCE_NONE:
238 * When the pipe CRC tap point is after the transcoders we need
239 * to tweak symbol-level features to produce a deterministic series of
240 * symbols for a given frame. We need to reset those features only once
241 * a frame (instead of every nth symbol):
242 * - DC-balance: used to ensure a better clock recovery from the data
244 * - DisplayPort scrambling: used for EMI reduction
246 if (need_stable_symbols) {
247 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
249 WARN_ON(!IS_G4X(dev_priv));
251 I915_WRITE(PORT_DFT_I9XX,
252 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
255 tmp |= PIPE_A_SCRAMBLE_RESET;
257 tmp |= PIPE_B_SCRAMBLE_RESET;
259 I915_WRITE(PORT_DFT2_G4X, tmp);
265 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
268 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
272 tmp &= ~PIPE_A_SCRAMBLE_RESET;
275 tmp &= ~PIPE_B_SCRAMBLE_RESET;
278 tmp &= ~PIPE_C_SCRAMBLE_RESET;
283 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
284 tmp &= ~DC_BALANCE_RESET_VLV;
285 I915_WRITE(PORT_DFT2_G4X, tmp);
289 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
292 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
295 tmp &= ~PIPE_A_SCRAMBLE_RESET;
297 tmp &= ~PIPE_B_SCRAMBLE_RESET;
298 I915_WRITE(PORT_DFT2_G4X, tmp);
300 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
301 I915_WRITE(PORT_DFT_I9XX,
302 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
306 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
309 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
310 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
313 case INTEL_PIPE_CRC_SOURCE_PLANE1:
314 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
316 case INTEL_PIPE_CRC_SOURCE_PLANE2:
317 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
319 case INTEL_PIPE_CRC_SOURCE_PIPE:
320 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
322 case INTEL_PIPE_CRC_SOURCE_NONE:
332 static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
335 struct drm_device *dev = &dev_priv->drm;
336 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
337 struct intel_crtc_state *pipe_config;
338 struct drm_atomic_state *state;
339 struct drm_modeset_acquire_ctx ctx;
342 drm_modeset_acquire_init(&ctx, 0);
344 state = drm_atomic_state_alloc(dev);
350 state->acquire_ctx = &ctx;
353 pipe_config = intel_atomic_get_crtc_state(state, crtc);
354 if (IS_ERR(pipe_config)) {
355 ret = PTR_ERR(pipe_config);
359 if (HAS_IPS(dev_priv)) {
361 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
362 * enabled and disabled dynamically based on package C states,
363 * user space can't make reliable use of the CRCs, so let's just
364 * completely disable it.
366 pipe_config->ips_force_disable = enable;
369 if (IS_HASWELL(dev_priv)) {
370 pipe_config->pch_pfit.force_thru = enable;
371 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
372 pipe_config->pch_pfit.enabled != enable)
373 pipe_config->base.connectors_changed = true;
376 ret = drm_atomic_commit(state);
379 if (ret == -EDEADLK) {
380 drm_atomic_state_clear(state);
381 drm_modeset_backoff(&ctx);
385 drm_atomic_state_put(state);
387 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
388 drm_modeset_drop_locks(&ctx);
389 drm_modeset_acquire_fini(&ctx);
392 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
394 enum intel_pipe_crc_source *source,
398 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
399 *source = INTEL_PIPE_CRC_SOURCE_PF;
402 case INTEL_PIPE_CRC_SOURCE_PLANE1:
403 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
405 case INTEL_PIPE_CRC_SOURCE_PLANE2:
406 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
408 case INTEL_PIPE_CRC_SOURCE_PF:
409 if (set_wa && (IS_HASWELL(dev_priv) ||
410 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
411 hsw_pipe_A_crc_wa(dev_priv, true);
413 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
415 case INTEL_PIPE_CRC_SOURCE_NONE:
425 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
427 enum intel_pipe_crc_source *source, u32 *val,
430 if (IS_GEN2(dev_priv))
431 return i8xx_pipe_crc_ctl_reg(source, val);
432 else if (INTEL_GEN(dev_priv) < 5)
433 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
434 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
435 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
436 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
437 return ilk_pipe_crc_ctl_reg(source, val);
439 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
443 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
448 *s = INTEL_PIPE_CRC_SOURCE_NONE;
452 i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
460 void intel_display_crc_init(struct drm_i915_private *dev_priv)
464 for_each_pipe(dev_priv, pipe) {
465 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
467 spin_lock_init(&pipe_crc->lock);
471 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
474 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
475 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
476 enum intel_display_power_domain power_domain;
477 enum intel_pipe_crc_source source;
478 u32 val = 0; /* shut up gcc */
481 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
482 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
486 power_domain = POWER_DOMAIN_PIPE(crtc->index);
487 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
488 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
492 ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
496 pipe_crc->source = source;
497 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
498 POSTING_READ(PIPE_CRC_CTL(crtc->index));
501 if (IS_G4X(dev_priv))
502 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
503 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
504 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
505 else if ((IS_HASWELL(dev_priv) ||
506 IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
507 hsw_pipe_A_crc_wa(dev_priv, false);
510 pipe_crc->skipped = 0;
514 intel_display_power_put(dev_priv, power_domain);
519 void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
521 struct drm_crtc *crtc = &intel_crtc->base;
522 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
523 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
526 if (!crtc->crc.opened)
529 if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
532 /* Don't need pipe_crc->lock here, IRQs are not generated. */
533 pipe_crc->skipped = 0;
535 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
536 POSTING_READ(PIPE_CRC_CTL(crtc->index));
539 void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
541 struct drm_crtc *crtc = &intel_crtc->base;
542 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
543 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
545 /* Swallow crc's until we stop generating them. */
546 spin_lock_irq(&pipe_crc->lock);
547 pipe_crc->skipped = INT_MIN;
548 spin_unlock_irq(&pipe_crc->lock);
550 I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
551 POSTING_READ(PIPE_CRC_CTL(crtc->index));
552 synchronize_irq(dev_priv->drm.irq);