1 // SPDX-License-Identifier: MIT
3 * Copyright © 2013-2021 Intel Corporation
8 #include "intel_pcode.h"
10 static int gen6_check_mailbox_status(u32 mbox)
12 switch (mbox & GEN6_PCODE_ERROR_MASK) {
13 case GEN6_PCODE_SUCCESS:
15 case GEN6_PCODE_UNIMPLEMENTED_CMD:
17 case GEN6_PCODE_ILLEGAL_CMD:
19 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
20 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
22 case GEN6_PCODE_TIMEOUT:
25 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
30 static int gen7_check_mailbox_status(u32 mbox)
32 switch (mbox & GEN6_PCODE_ERROR_MASK) {
33 case GEN6_PCODE_SUCCESS:
35 case GEN6_PCODE_ILLEGAL_CMD:
37 case GEN7_PCODE_TIMEOUT:
39 case GEN7_PCODE_ILLEGAL_DATA:
41 case GEN11_PCODE_ILLEGAL_SUBCOMMAND:
43 case GEN11_PCODE_LOCKED:
45 case GEN11_PCODE_REJECTED:
47 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
50 MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
55 static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
57 int fast_timeout_us, int slow_timeout_ms,
60 lockdep_assert_held(&uncore->i915->sb_lock);
63 * GEN6_PCODE_* are outside of the forcewake domain, we can use
64 * intel_uncore_read/write_fw variants to reduce the amount of work
65 * required when reading/writing.
68 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
71 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
72 intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
73 intel_uncore_write_fw(uncore,
74 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
76 if (__intel_wait_for_register_fw(uncore,
85 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
89 if (GRAPHICS_VER(uncore->i915) > 6)
90 return gen7_check_mailbox_status(mbox);
92 return gen6_check_mailbox_status(mbox);
95 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
99 mutex_lock(&uncore->i915->sb_lock);
100 err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
101 mutex_unlock(&uncore->i915->sb_lock);
104 drm_dbg(&uncore->i915->drm,
105 "warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
106 mbox, __builtin_return_address(0), err);
112 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
113 int fast_timeout_us, int slow_timeout_ms)
117 mutex_lock(&uncore->i915->sb_lock);
118 err = __snb_pcode_rw(uncore, mbox, &val, NULL,
119 fast_timeout_us, slow_timeout_ms, false);
120 mutex_unlock(&uncore->i915->sb_lock);
123 drm_dbg(&uncore->i915->drm,
124 "warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
125 val, mbox, __builtin_return_address(0), err);
131 static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
132 u32 request, u32 reply_mask, u32 reply,
135 *status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
137 return (*status == 0) && ((request & reply_mask) == reply);
141 * skl_pcode_request - send PCODE request until acknowledgment
143 * @mbox: PCODE mailbox ID the request is targeted for
144 * @request: request ID
145 * @reply_mask: mask used to check for request acknowledgment
146 * @reply: value used to check for request acknowledgment
147 * @timeout_base_ms: timeout for polling with preemption enabled
149 * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
150 * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
151 * The request is acknowledged once the PCODE reply dword equals @reply after
152 * applying @reply_mask. Polling is first attempted with preemption enabled
153 * for @timeout_base_ms and if this times out for another 50 ms with
154 * preemption disabled.
156 * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
157 * other error as reported by PCODE.
159 int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
160 u32 reply_mask, u32 reply, int timeout_base_ms)
165 mutex_lock(&uncore->i915->sb_lock);
168 skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
171 * Prime the PCODE by doing a request first. Normally it guarantees
172 * that a subsequent request, at most @timeout_base_ms later, succeeds.
173 * _wait_for() doesn't guarantee when its passed condition is evaluated
174 * first, so send the first request explicitly.
180 ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
185 * The above can time out if the number of requests was low (2 in the
186 * worst case) _and_ PCODE was busy for some reason even after a
187 * (queued) request and @timeout_base_ms delay. As a workaround retry
188 * the poll with preemption disabled to maximize the number of
189 * requests. Increase the timeout from @timeout_base_ms to 50ms to
190 * account for interrupts that could reduce the number of these
191 * requests, and for any quirks of the PCODE firmware that delays
192 * the request completion.
194 drm_dbg_kms(&uncore->i915->drm,
195 "PCODE timeout, retrying with preemption disabled\n");
196 drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
198 ret = wait_for_atomic(COND, 50);
202 mutex_unlock(&uncore->i915->sb_lock);
203 return status ? status : ret;
207 int intel_pcode_init(struct intel_uncore *uncore)
209 if (!IS_DGFX(uncore->i915))
212 return skl_pcode_request(uncore, DG1_PCODE_STATUS,
213 DG1_UNCORE_GET_INIT_STATUS,
214 DG1_UNCORE_INIT_STATUS_COMPLETE,
215 DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
218 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
220 intel_wakeref_t wakeref;
224 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
225 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
226 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
228 with_intel_runtime_pm(uncore->rpm, wakeref)
229 err = snb_pcode_read(uncore, mbox, val, NULL);
234 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
236 intel_wakeref_t wakeref;
240 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
241 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
242 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
244 with_intel_runtime_pm(uncore->rpm, wakeref)
245 err = snb_pcode_write(uncore, mbox, val);