drivers/gpu/drm/i915/intel_pci_config.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_PCI_CONFIG_H__
   7 #define __INTEL_PCI_CONFIG_H__
   8
   9 /* PCI BARs */
  10 #define GEN2_GMADR_BAR                          0
  11 #define GEN2_MMADR_BAR                          1 /* MMIO+GTT, despite the name */
  12 #define GEN2_IO_BAR                             2 /* 85x/865 */
  13
  14 #define GEN3_MMADR_BAR                          0 /* MMIO only */
  15 #define GEN3_IO_BAR                             1
  16 #define GEN3_GMADR_BAR                          2
  17 #define GEN3_GTTADR_BAR                         3 /* GTT only */
  18
  19 #define GEN4_GTTMMADR_BAR                       0 /* MMIO+GTT */
  20 #define GEN4_GMADR_BAR                          2
  21 #define GEN4_IO_BAR                             4
  22
  23 #define GEN12_LMEM_BAR                          2
  24
  25 static inline int intel_mmio_bar(int graphics_ver)
  26 {
  27         switch (graphics_ver) {
  28         case 2: return GEN2_MMADR_BAR;
  29         case 3: return GEN3_MMADR_BAR;
  30         default: return GEN4_GTTMMADR_BAR;
  31         }
  32 }
  33
  34 /* BSM in include/drm/i915_drm.h */
  35
  36 #define MCHBAR_I915                             0x44
  37 #define MCHBAR_I965                             0x48
  38 #define   MCHBAR_SIZE                           (4 * 4096)
  39
  40 #define DEVEN                                   0x54
  41 #define   DEVEN_MCHBAR_EN                       (1 << 28)
  42
  43 #define HPLLCC                                  0xc0 /* 85x only */
  44 #define   GC_CLOCK_CONTROL_MASK                 (0x7 << 0)
  45 #define   GC_CLOCK_133_200                      (0 << 0)
  46 #define   GC_CLOCK_100_200                      (1 << 0)
  47 #define   GC_CLOCK_100_133                      (2 << 0)
  48 #define   GC_CLOCK_133_266                      (3 << 0)
  49 #define   GC_CLOCK_133_200_2                    (4 << 0)
  50 #define   GC_CLOCK_133_266_2                    (5 << 0)
  51 #define   GC_CLOCK_166_266                      (6 << 0)
  52 #define   GC_CLOCK_166_250                      (7 << 0)
  53
  54 #define I915_GDRST                              0xc0
  55 #define   GRDOM_FULL                            (0 << 2)
  56 #define   GRDOM_RENDER                          (1 << 2)
  57 #define   GRDOM_MEDIA                           (3 << 2)
  58 #define   GRDOM_MASK                            (3 << 2)
  59 #define   GRDOM_RESET_STATUS                    (1 << 1)
  60 #define   GRDOM_RESET_ENABLE                    (1 << 0)
  61
  62 /* BSpec only has register offset, PCI device and bit found empirically */
  63 #define I830_CLOCK_GATE                         0xc8 /* device 0 */
  64 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE      (1 << 2)
  65
  66 #define GCDGMBUS                                0xcc
  67
  68 #define GCFGC2                                  0xda
  69 #define GCFGC                                   0xf0 /* 915+ only */
  70 #define   GC_LOW_FREQUENCY_ENABLE               (1 << 7)
  71 #define   GC_DISPLAY_CLOCK_190_200_MHZ          (0 << 4)
  72 #define   GC_DISPLAY_CLOCK_333_320_MHZ          (4 << 4)
  73 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV          (0 << 4)
  74 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV          (1 << 4)
  75 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV          (2 << 4)
  76 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV          (5 << 4)
  77 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV          (6 << 4)
  78 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV          (7 << 4)
  79 #define   GC_DISPLAY_CLOCK_MASK                 (7 << 4)
  80 #define   GM45_GC_RENDER_CLOCK_MASK             (0xf << 0)
  81 #define   GM45_GC_RENDER_CLOCK_266_MHZ          (8 << 0)
  82 #define   GM45_GC_RENDER_CLOCK_320_MHZ          (9 << 0)
  83 #define   GM45_GC_RENDER_CLOCK_400_MHZ          (0xb << 0)
  84 #define   GM45_GC_RENDER_CLOCK_533_MHZ          (0xc << 0)
  85 #define   I965_GC_RENDER_CLOCK_MASK             (0xf << 0)
  86 #define   I965_GC_RENDER_CLOCK_267_MHZ          (2 << 0)
  87 #define   I965_GC_RENDER_CLOCK_333_MHZ          (3 << 0)
  88 #define   I965_GC_RENDER_CLOCK_444_MHZ          (4 << 0)
  89 #define   I965_GC_RENDER_CLOCK_533_MHZ          (5 << 0)
  90 #define   I945_GC_RENDER_CLOCK_MASK             (7 << 0)
  91 #define   I945_GC_RENDER_CLOCK_166_MHZ          (0 << 0)
  92 #define   I945_GC_RENDER_CLOCK_200_MHZ          (1 << 0)
  93 #define   I945_GC_RENDER_CLOCK_250_MHZ          (3 << 0)
  94 #define   I945_GC_RENDER_CLOCK_400_MHZ          (5 << 0)
  95 #define   I915_GC_RENDER_CLOCK_MASK             (7 << 0)
  96 #define   I915_GC_RENDER_CLOCK_166_MHZ          (0 << 0)
  97 #define   I915_GC_RENDER_CLOCK_200_MHZ          (1 << 0)
  98 #define   I915_GC_RENDER_CLOCK_333_MHZ          (4 << 0)
  99
 100 #define ASLE                                    0xe4
 101 #define ASLS                                    0xfc
 102
 103 #define SWSCI                                   0xe8
 104 #define   SWSCI_SCISEL                          (1 << 15)
 105 #define   SWSCI_GSSCIE                          (1 << 0)
 106
 107 /* legacy/combination backlight modes, also called LBB */
 108 #define LBPC                                    0xf4
 109
 110 #endif /* __INTEL_PCI_CONFIG_H__ */