drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33
  34 /* Limits for overlay size. According to intel doc, the real limits are:
  35  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  36  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  37  * the mininum of both.  */
  38 #define IMAGE_MAX_WIDTH         2048
  39 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  40 /* on 830 and 845 these large limits result in the card hanging */
  41 #define IMAGE_MAX_WIDTH_LEGACY  1024
  42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  43
  44 /* overlay register definitions */
  45 /* OCMD register */
  46 #define OCMD_TILED_SURFACE      (0x1<<19)
  47 #define OCMD_MIRROR_MASK        (0x3<<17)
  48 #define OCMD_MIRROR_MODE        (0x3<<17)
  49 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  50 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  51 #define OCMD_MIRROR_BOTH        (0x3<<17)
  52 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  53 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  54 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  55 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  57 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  58 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  60 #define OCMD_YUV_422_PACKED     (0x8<<10)
  61 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  62 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  63 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  64 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  65 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  66 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  67 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  68 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  69 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  70 #define OCMD_TEST_MODE          (0x1<<4)
  71 #define OCMD_BUFFER_SELECT      (0x3<<2)
  72 #define OCMD_BUFFER0            (0x0<<2)
  73 #define OCMD_BUFFER1            (0x1<<2)
  74 #define OCMD_FIELD_SELECT       (0x1<<2)
  75 #define OCMD_FIELD0             (0x0<<1)
  76 #define OCMD_FIELD1             (0x1<<1)
  77 #define OCMD_ENABLE             (0x1<<0)
  78
  79 /* OCONFIG register */
  80 #define OCONF_PIPE_MASK         (0x1<<18)
  81 #define OCONF_PIPE_A            (0x0<<18)
  82 #define OCONF_PIPE_B            (0x1<<18)
  83 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  84 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  85 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  86 #define OCONF_CSC_BYPASS        (0x1<<4)
  87 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  88 #define OCONF_TEST_MODE         (0x1<<2)
  89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  90 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  91
  92 /* DCLRKM (dst-key) register */
  93 #define DST_KEY_ENABLE          (0x1<<31)
  94 #define CLK_RGB24_MASK          0x0
  95 #define CLK_RGB16_MASK          0x070307
  96 #define CLK_RGB15_MASK          0x070707
  97 #define CLK_RGB8I_MASK          0xffffff
  98
  99 #define RGB16_TO_COLORKEY(c) \
 100         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 101 #define RGB15_TO_COLORKEY(c) \
 102         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 103
 104 /* overlay flip addr flag */
 105 #define OFC_UPDATE              0x1
 106
 107 /* polyphase filter coefficients */
 108 #define N_HORIZ_Y_TAPS          5
 109 #define N_VERT_Y_TAPS           3
 110 #define N_HORIZ_UV_TAPS         3
 111 #define N_VERT_UV_TAPS          3
 112 #define N_PHASES                17
 113 #define MAX_TAPS                5
 114
 115 /* memory bufferd overlay registers */
 116 struct overlay_registers {
 117         u32 OBUF_0Y;
 118         u32 OBUF_1Y;
 119         u32 OBUF_0U;
 120         u32 OBUF_0V;
 121         u32 OBUF_1U;
 122         u32 OBUF_1V;
 123         u32 OSTRIDE;
 124         u32 YRGB_VPH;
 125         u32 UV_VPH;
 126         u32 HORZ_PH;
 127         u32 INIT_PHS;
 128         u32 DWINPOS;
 129         u32 DWINSZ;
 130         u32 SWIDTH;
 131         u32 SWIDTHSW;
 132         u32 SHEIGHT;
 133         u32 YRGBSCALE;
 134         u32 UVSCALE;
 135         u32 OCLRC0;
 136         u32 OCLRC1;
 137         u32 DCLRKV;
 138         u32 DCLRKM;
 139         u32 SCLRKVH;
 140         u32 SCLRKVL;
 141         u32 SCLRKEN;
 142         u32 OCONFIG;
 143         u32 OCMD;
 144         u32 RESERVED1; /* 0x6C */
 145         u32 OSTART_0Y;
 146         u32 OSTART_1Y;
 147         u32 OSTART_0U;
 148         u32 OSTART_0V;
 149         u32 OSTART_1U;
 150         u32 OSTART_1V;
 151         u32 OTILEOFF_0Y;
 152         u32 OTILEOFF_1Y;
 153         u32 OTILEOFF_0U;
 154         u32 OTILEOFF_0V;
 155         u32 OTILEOFF_1U;
 156         u32 OTILEOFF_1V;
 157         u32 FASTHSCALE; /* 0xA0 */
 158         u32 UVSCALEV; /* 0xA4 */
 159         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 160         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 161         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 162         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 163         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 164         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 165         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 166         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 167         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 168 };
 169
 170 struct intel_overlay {
 171         struct drm_device *dev;
 172         struct intel_crtc *crtc;
 173         struct drm_i915_gem_object *vid_bo;
 174         struct drm_i915_gem_object *old_vid_bo;
 175         bool active;
 176         bool pfit_active;
 177         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 178         u32 color_key:24;
 179         u32 color_key_enabled:1;
 180         u32 brightness, contrast, saturation;
 181         u32 old_xscale, old_yscale;
 182         /* register access */
 183         u32 flip_addr;
 184         struct drm_i915_gem_object *reg_bo;
 185         /* flip handling */
 186         struct drm_i915_gem_request *last_flip_req;
 187         void (*flip_tail)(struct intel_overlay *);
 188 };
 189
 190 static struct overlay_registers __iomem *
 191 intel_overlay_map_regs(struct intel_overlay *overlay)
 192 {
 193         struct drm_i915_private *dev_priv = overlay->dev->dev_private;
 194         struct overlay_registers __iomem *regs;
 195
 196         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 197                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 198         else
 199                 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
 200                                          i915_gem_obj_ggtt_offset(overlay->reg_bo));
 201
 202         return regs;
 203 }
 204
 205 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 206                                      struct overlay_registers __iomem *regs)
 207 {
 208         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
 209                 io_mapping_unmap(regs);
 210 }
 211
 212 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 213                                          struct drm_i915_gem_request *req,
 214                                          void (*tail)(struct intel_overlay *))
 215 {
 216         int ret;
 217
 218         WARN_ON(overlay->last_flip_req);
 219         i915_gem_request_assign(&overlay->last_flip_req, req);
 220         i915_add_request(req);
 221
 222         overlay->flip_tail = tail;
 223         ret = i915_wait_request(overlay->last_flip_req);
 224         if (ret)
 225                 return ret;
 226
 227         i915_gem_request_assign(&overlay->last_flip_req, NULL);
 228         return 0;
 229 }
 230
 231 /* overlay needs to be disable in OCMD reg */
 232 static int intel_overlay_on(struct intel_overlay *overlay)
 233 {
 234         struct drm_device *dev = overlay->dev;
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 237         struct drm_i915_gem_request *req;
 238         int ret;
 239
 240         WARN_ON(overlay->active);
 241         WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 242
 243         req = i915_gem_request_alloc(engine, NULL);
 244         if (IS_ERR(req))
 245                 return PTR_ERR(req);
 246
 247         ret = intel_ring_begin(req, 4);
 248         if (ret) {
 249                 i915_gem_request_cancel(req);
 250                 return ret;
 251         }
 252
 253         overlay->active = true;
 254
 255         intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 256         intel_ring_emit(engine, overlay->flip_addr | OFC_UPDATE);
 257         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 258         intel_ring_emit(engine, MI_NOOP);
 259         intel_ring_advance(engine);
 260
 261         return intel_overlay_do_wait_request(overlay, req, NULL);
 262 }
 263
 264 /* overlay needs to be enabled in OCMD reg */
 265 static int intel_overlay_continue(struct intel_overlay *overlay,
 266                                   bool load_polyphase_filter)
 267 {
 268         struct drm_device *dev = overlay->dev;
 269         struct drm_i915_private *dev_priv = dev->dev_private;
 270         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 271         struct drm_i915_gem_request *req;
 272         u32 flip_addr = overlay->flip_addr;
 273         u32 tmp;
 274         int ret;
 275
 276         WARN_ON(!overlay->active);
 277
 278         if (load_polyphase_filter)
 279                 flip_addr |= OFC_UPDATE;
 280
 281         /* check for underruns */
 282         tmp = I915_READ(DOVSTA);
 283         if (tmp & (1 << 17))
 284                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 285
 286         req = i915_gem_request_alloc(engine, NULL);
 287         if (IS_ERR(req))
 288                 return PTR_ERR(req);
 289
 290         ret = intel_ring_begin(req, 2);
 291         if (ret) {
 292                 i915_gem_request_cancel(req);
 293                 return ret;
 294         }
 295
 296         intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 297         intel_ring_emit(engine, flip_addr);
 298         intel_ring_advance(engine);
 299
 300         WARN_ON(overlay->last_flip_req);
 301         i915_gem_request_assign(&overlay->last_flip_req, req);
 302         i915_add_request(req);
 303
 304         return 0;
 305 }
 306
 307 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 308 {
 309         struct drm_i915_gem_object *obj = overlay->old_vid_bo;
 310
 311         i915_gem_object_ggtt_unpin(obj);
 312         drm_gem_object_unreference(&obj->base);
 313
 314         overlay->old_vid_bo = NULL;
 315 }
 316
 317 static void intel_overlay_off_tail(struct intel_overlay *overlay)
 318 {
 319         struct drm_i915_gem_object *obj = overlay->vid_bo;
 320
 321         /* never have the overlay hw on without showing a frame */
 322         if (WARN_ON(!obj))
 323                 return;
 324
 325         i915_gem_object_ggtt_unpin(obj);
 326         drm_gem_object_unreference(&obj->base);
 327         overlay->vid_bo = NULL;
 328
 329         overlay->crtc->overlay = NULL;
 330         overlay->crtc = NULL;
 331         overlay->active = false;
 332 }
 333
 334 /* overlay needs to be disabled in OCMD reg */
 335 static int intel_overlay_off(struct intel_overlay *overlay)
 336 {
 337         struct drm_device *dev = overlay->dev;
 338         struct drm_i915_private *dev_priv = dev->dev_private;
 339         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 340         struct drm_i915_gem_request *req;
 341         u32 flip_addr = overlay->flip_addr;
 342         int ret;
 343
 344         WARN_ON(!overlay->active);
 345
 346         /* According to intel docs the overlay hw may hang (when switching
 347          * off) without loading the filter coeffs. It is however unclear whether
 348          * this applies to the disabling of the overlay or to the switching off
 349          * of the hw. Do it in both cases */
 350         flip_addr |= OFC_UPDATE;
 351
 352         req = i915_gem_request_alloc(engine, NULL);
 353         if (IS_ERR(req))
 354                 return PTR_ERR(req);
 355
 356         ret = intel_ring_begin(req, 6);
 357         if (ret) {
 358                 i915_gem_request_cancel(req);
 359                 return ret;
 360         }
 361
 362         /* wait for overlay to go idle */
 363         intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 364         intel_ring_emit(engine, flip_addr);
 365         intel_ring_emit(engine, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 366         /* turn overlay off */
 367         if (IS_I830(dev)) {
 368                 /* Workaround: Don't disable the overlay fully, since otherwise
 369                  * it dies on the next OVERLAY_ON cmd. */
 370                 intel_ring_emit(engine, MI_NOOP);
 371                 intel_ring_emit(engine, MI_NOOP);
 372                 intel_ring_emit(engine, MI_NOOP);
 373         } else {
 374                 intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 375                 intel_ring_emit(engine, flip_addr);
 376                 intel_ring_emit(engine,
 377                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 378         }
 379         intel_ring_advance(engine);
 380
 381         return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
 382 }
 383
 384 /* recover from an interruption due to a signal
 385  * We have to be careful not to repeat work forever an make forward progess. */
 386 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 387 {
 388         int ret;
 389
 390         if (overlay->last_flip_req == NULL)
 391                 return 0;
 392
 393         ret = i915_wait_request(overlay->last_flip_req);
 394         if (ret)
 395                 return ret;
 396
 397         if (overlay->flip_tail)
 398                 overlay->flip_tail(overlay);
 399
 400         i915_gem_request_assign(&overlay->last_flip_req, NULL);
 401         return 0;
 402 }
 403
 404 /* Wait for pending overlay flip and release old frame.
 405  * Needs to be called before the overlay register are changed
 406  * via intel_overlay_(un)map_regs
 407  */
 408 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 409 {
 410         struct drm_device *dev = overlay->dev;
 411         struct drm_i915_private *dev_priv = dev->dev_private;
 412         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 413         int ret;
 414
 415         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 416
 417         /* Only wait if there is actually an old frame to release to
 418          * guarantee forward progress.
 419          */
 420         if (!overlay->old_vid_bo)
 421                 return 0;
 422
 423         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 424                 /* synchronous slowpath */
 425                 struct drm_i915_gem_request *req;
 426
 427                 req = i915_gem_request_alloc(engine, NULL);
 428                 if (IS_ERR(req))
 429                         return PTR_ERR(req);
 430
 431                 ret = intel_ring_begin(req, 2);
 432                 if (ret) {
 433                         i915_gem_request_cancel(req);
 434                         return ret;
 435                 }
 436
 437                 intel_ring_emit(engine,
 438                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 439                 intel_ring_emit(engine, MI_NOOP);
 440                 intel_ring_advance(engine);
 441
 442                 ret = intel_overlay_do_wait_request(overlay, req,
 443                                                     intel_overlay_release_old_vid_tail);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         intel_overlay_release_old_vid_tail(overlay);
 449
 450
 451         i915_gem_track_fb(overlay->old_vid_bo, NULL,
 452                           INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 453         return 0;
 454 }
 455
 456 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 457 {
 458         struct intel_overlay *overlay = dev_priv->overlay;
 459
 460         if (!overlay)
 461                 return;
 462
 463         intel_overlay_release_old_vid(overlay);
 464
 465         overlay->last_flip_req = NULL;
 466         overlay->old_xscale = 0;
 467         overlay->old_yscale = 0;
 468         overlay->crtc = NULL;
 469         overlay->active = false;
 470 }
 471
 472 struct put_image_params {
 473         int format;
 474         short dst_x;
 475         short dst_y;
 476         short dst_w;
 477         short dst_h;
 478         short src_w;
 479         short src_scan_h;
 480         short src_scan_w;
 481         short src_h;
 482         short stride_Y;
 483         short stride_UV;
 484         int offset_Y;
 485         int offset_U;
 486         int offset_V;
 487 };
 488
 489 static int packed_depth_bytes(u32 format)
 490 {
 491         switch (format & I915_OVERLAY_DEPTH_MASK) {
 492         case I915_OVERLAY_YUV422:
 493                 return 4;
 494         case I915_OVERLAY_YUV411:
 495                 /* return 6; not implemented */
 496         default:
 497                 return -EINVAL;
 498         }
 499 }
 500
 501 static int packed_width_bytes(u32 format, short width)
 502 {
 503         switch (format & I915_OVERLAY_DEPTH_MASK) {
 504         case I915_OVERLAY_YUV422:
 505                 return width << 1;
 506         default:
 507                 return -EINVAL;
 508         }
 509 }
 510
 511 static int uv_hsubsampling(u32 format)
 512 {
 513         switch (format & I915_OVERLAY_DEPTH_MASK) {
 514         case I915_OVERLAY_YUV422:
 515         case I915_OVERLAY_YUV420:
 516                 return 2;
 517         case I915_OVERLAY_YUV411:
 518         case I915_OVERLAY_YUV410:
 519                 return 4;
 520         default:
 521                 return -EINVAL;
 522         }
 523 }
 524
 525 static int uv_vsubsampling(u32 format)
 526 {
 527         switch (format & I915_OVERLAY_DEPTH_MASK) {
 528         case I915_OVERLAY_YUV420:
 529         case I915_OVERLAY_YUV410:
 530                 return 2;
 531         case I915_OVERLAY_YUV422:
 532         case I915_OVERLAY_YUV411:
 533                 return 1;
 534         default:
 535                 return -EINVAL;
 536         }
 537 }
 538
 539 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
 540 {
 541         u32 mask, shift, ret;
 542         if (IS_GEN2(dev)) {
 543                 mask = 0x1f;
 544                 shift = 5;
 545         } else {
 546                 mask = 0x3f;
 547                 shift = 6;
 548         }
 549         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 550         if (!IS_GEN2(dev))
 551                 ret <<= 1;
 552         ret -= 1;
 553         return ret << 2;
 554 }
 555
 556 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 557         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 558         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 559         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 560         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 561         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 562         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 563         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 564         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 565         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 566         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 567         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 568         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 569         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 570         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 571         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 572         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 573         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 574 };
 575
 576 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 577         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 578         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 579         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 580         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 581         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 582         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 583         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 584         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 585         0x3000, 0x0800, 0x3000
 586 };
 587
 588 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 589 {
 590         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 591         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 592                     sizeof(uv_static_hcoeffs));
 593 }
 594
 595 static bool update_scaling_factors(struct intel_overlay *overlay,
 596                                    struct overlay_registers __iomem *regs,
 597                                    struct put_image_params *params)
 598 {
 599         /* fixed point with a 12 bit shift */
 600         u32 xscale, yscale, xscale_UV, yscale_UV;
 601 #define FP_SHIFT 12
 602 #define FRACT_MASK 0xfff
 603         bool scale_changed = false;
 604         int uv_hscale = uv_hsubsampling(params->format);
 605         int uv_vscale = uv_vsubsampling(params->format);
 606
 607         if (params->dst_w > 1)
 608                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 609                         /(params->dst_w);
 610         else
 611                 xscale = 1 << FP_SHIFT;
 612
 613         if (params->dst_h > 1)
 614                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 615                         /(params->dst_h);
 616         else
 617                 yscale = 1 << FP_SHIFT;
 618
 619         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 620         xscale_UV = xscale/uv_hscale;
 621         yscale_UV = yscale/uv_vscale;
 622         /* make the Y scale to UV scale ratio an exact multiply */
 623         xscale = xscale_UV * uv_hscale;
 624         yscale = yscale_UV * uv_vscale;
 625         /*} else {
 626           xscale_UV = 0;
 627           yscale_UV = 0;
 628           }*/
 629
 630         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 631                 scale_changed = true;
 632         overlay->old_xscale = xscale;
 633         overlay->old_yscale = yscale;
 634
 635         iowrite32(((yscale & FRACT_MASK) << 20) |
 636                   ((xscale >> FP_SHIFT)  << 16) |
 637                   ((xscale & FRACT_MASK) << 3),
 638                  &regs->YRGBSCALE);
 639
 640         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 641                   ((xscale_UV >> FP_SHIFT)  << 16) |
 642                   ((xscale_UV & FRACT_MASK) << 3),
 643                  &regs->UVSCALE);
 644
 645         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 646                    ((yscale_UV >> FP_SHIFT) << 0)),
 647                  &regs->UVSCALEV);
 648
 649         if (scale_changed)
 650                 update_polyphase_filter(regs);
 651
 652         return scale_changed;
 653 }
 654
 655 static void update_colorkey(struct intel_overlay *overlay,
 656                             struct overlay_registers __iomem *regs)
 657 {
 658         u32 key = overlay->color_key;
 659         u32 flags;
 660
 661         flags = 0;
 662         if (overlay->color_key_enabled)
 663                 flags |= DST_KEY_ENABLE;
 664
 665         switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
 666         case 8:
 667                 key = 0;
 668                 flags |= CLK_RGB8I_MASK;
 669                 break;
 670
 671         case 16:
 672                 if (overlay->crtc->base.primary->fb->depth == 15) {
 673                         key = RGB15_TO_COLORKEY(key);
 674                         flags |= CLK_RGB15_MASK;
 675                 } else {
 676                         key = RGB16_TO_COLORKEY(key);
 677                         flags |= CLK_RGB16_MASK;
 678                 }
 679                 break;
 680
 681         case 24:
 682         case 32:
 683                 flags |= CLK_RGB24_MASK;
 684                 break;
 685         }
 686
 687         iowrite32(key, &regs->DCLRKV);
 688         iowrite32(flags, &regs->DCLRKM);
 689 }
 690
 691 static u32 overlay_cmd_reg(struct put_image_params *params)
 692 {
 693         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 694
 695         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 696                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 697                 case I915_OVERLAY_YUV422:
 698                         cmd |= OCMD_YUV_422_PLANAR;
 699                         break;
 700                 case I915_OVERLAY_YUV420:
 701                         cmd |= OCMD_YUV_420_PLANAR;
 702                         break;
 703                 case I915_OVERLAY_YUV411:
 704                 case I915_OVERLAY_YUV410:
 705                         cmd |= OCMD_YUV_410_PLANAR;
 706                         break;
 707                 }
 708         } else { /* YUV packed */
 709                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 710                 case I915_OVERLAY_YUV422:
 711                         cmd |= OCMD_YUV_422_PACKED;
 712                         break;
 713                 case I915_OVERLAY_YUV411:
 714                         cmd |= OCMD_YUV_411_PACKED;
 715                         break;
 716                 }
 717
 718                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 719                 case I915_OVERLAY_NO_SWAP:
 720                         break;
 721                 case I915_OVERLAY_UV_SWAP:
 722                         cmd |= OCMD_UV_SWAP;
 723                         break;
 724                 case I915_OVERLAY_Y_SWAP:
 725                         cmd |= OCMD_Y_SWAP;
 726                         break;
 727                 case I915_OVERLAY_Y_AND_UV_SWAP:
 728                         cmd |= OCMD_Y_AND_UV_SWAP;
 729                         break;
 730                 }
 731         }
 732
 733         return cmd;
 734 }
 735
 736 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 737                                       struct drm_i915_gem_object *new_bo,
 738                                       struct put_image_params *params)
 739 {
 740         int ret, tmp_width;
 741         struct overlay_registers __iomem *regs;
 742         bool scale_changed = false;
 743         struct drm_device *dev = overlay->dev;
 744         u32 swidth, swidthsw, sheight, ostride;
 745         enum pipe pipe = overlay->crtc->pipe;
 746
 747         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 748         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 749
 750         ret = intel_overlay_release_old_vid(overlay);
 751         if (ret != 0)
 752                 return ret;
 753
 754         ret = i915_gem_object_pin_to_display_plane(new_bo, 0,
 755                                                    &i915_ggtt_view_normal);
 756         if (ret != 0)
 757                 return ret;
 758
 759         ret = i915_gem_object_put_fence(new_bo);
 760         if (ret)
 761                 goto out_unpin;
 762
 763         if (!overlay->active) {
 764                 u32 oconfig;
 765                 regs = intel_overlay_map_regs(overlay);
 766                 if (!regs) {
 767                         ret = -ENOMEM;
 768                         goto out_unpin;
 769                 }
 770                 oconfig = OCONF_CC_OUT_8BIT;
 771                 if (IS_GEN4(overlay->dev))
 772                         oconfig |= OCONF_CSC_MODE_BT709;
 773                 oconfig |= pipe == 0 ?
 774                         OCONF_PIPE_A : OCONF_PIPE_B;
 775                 iowrite32(oconfig, &regs->OCONFIG);
 776                 intel_overlay_unmap_regs(overlay, regs);
 777
 778                 ret = intel_overlay_on(overlay);
 779                 if (ret != 0)
 780                         goto out_unpin;
 781         }
 782
 783         regs = intel_overlay_map_regs(overlay);
 784         if (!regs) {
 785                 ret = -ENOMEM;
 786                 goto out_unpin;
 787         }
 788
 789         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 790         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 791
 792         if (params->format & I915_OVERLAY_YUV_PACKED)
 793                 tmp_width = packed_width_bytes(params->format, params->src_w);
 794         else
 795                 tmp_width = params->src_w;
 796
 797         swidth = params->src_w;
 798         swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
 799         sheight = params->src_h;
 800         iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y);
 801         ostride = params->stride_Y;
 802
 803         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 804                 int uv_hscale = uv_hsubsampling(params->format);
 805                 int uv_vscale = uv_vsubsampling(params->format);
 806                 u32 tmp_U, tmp_V;
 807                 swidth |= (params->src_w/uv_hscale) << 16;
 808                 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
 809                                       params->src_w/uv_hscale);
 810                 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
 811                                       params->src_w/uv_hscale);
 812                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 813                 sheight |= (params->src_h/uv_vscale) << 16;
 814                 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U);
 815                 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V);
 816                 ostride |= params->stride_UV << 16;
 817         }
 818
 819         iowrite32(swidth, &regs->SWIDTH);
 820         iowrite32(swidthsw, &regs->SWIDTHSW);
 821         iowrite32(sheight, &regs->SHEIGHT);
 822         iowrite32(ostride, &regs->OSTRIDE);
 823
 824         scale_changed = update_scaling_factors(overlay, regs, params);
 825
 826         update_colorkey(overlay, regs);
 827
 828         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 829
 830         intel_overlay_unmap_regs(overlay, regs);
 831
 832         ret = intel_overlay_continue(overlay, scale_changed);
 833         if (ret)
 834                 goto out_unpin;
 835
 836         i915_gem_track_fb(overlay->vid_bo, new_bo,
 837                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 838
 839         overlay->old_vid_bo = overlay->vid_bo;
 840         overlay->vid_bo = new_bo;
 841
 842         intel_frontbuffer_flip(dev,
 843                                INTEL_FRONTBUFFER_OVERLAY(pipe));
 844
 845         return 0;
 846
 847 out_unpin:
 848         i915_gem_object_ggtt_unpin(new_bo);
 849         return ret;
 850 }
 851
 852 int intel_overlay_switch_off(struct intel_overlay *overlay)
 853 {
 854         struct overlay_registers __iomem *regs;
 855         struct drm_device *dev = overlay->dev;
 856         int ret;
 857
 858         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 859         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 860
 861         ret = intel_overlay_recover_from_interrupt(overlay);
 862         if (ret != 0)
 863                 return ret;
 864
 865         if (!overlay->active)
 866                 return 0;
 867
 868         ret = intel_overlay_release_old_vid(overlay);
 869         if (ret != 0)
 870                 return ret;
 871
 872         regs = intel_overlay_map_regs(overlay);
 873         iowrite32(0, &regs->OCMD);
 874         intel_overlay_unmap_regs(overlay, regs);
 875
 876         ret = intel_overlay_off(overlay);
 877         if (ret != 0)
 878                 return ret;
 879
 880         intel_overlay_off_tail(overlay);
 881         return 0;
 882 }
 883
 884 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 885                                           struct intel_crtc *crtc)
 886 {
 887         if (!crtc->active)
 888                 return -EINVAL;
 889
 890         /* can't use the overlay with double wide pipe */
 891         if (crtc->config->double_wide)
 892                 return -EINVAL;
 893
 894         return 0;
 895 }
 896
 897 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 898 {
 899         struct drm_device *dev = overlay->dev;
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         u32 pfit_control = I915_READ(PFIT_CONTROL);
 902         u32 ratio;
 903
 904         /* XXX: This is not the same logic as in the xorg driver, but more in
 905          * line with the intel documentation for the i965
 906          */
 907         if (INTEL_INFO(dev)->gen >= 4) {
 908                 /* on i965 use the PGM reg to read out the autoscaler values */
 909                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 910         } else {
 911                 if (pfit_control & VERT_AUTO_SCALE)
 912                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 913                 else
 914                         ratio = I915_READ(PFIT_PGM_RATIOS);
 915                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 916         }
 917
 918         overlay->pfit_vscale_ratio = ratio;
 919 }
 920
 921 static int check_overlay_dst(struct intel_overlay *overlay,
 922                              struct drm_intel_overlay_put_image *rec)
 923 {
 924         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 925
 926         if (rec->dst_x < mode->hdisplay &&
 927             rec->dst_x + rec->dst_width <= mode->hdisplay &&
 928             rec->dst_y < mode->vdisplay &&
 929             rec->dst_y + rec->dst_height <= mode->vdisplay)
 930                 return 0;
 931         else
 932                 return -EINVAL;
 933 }
 934
 935 static int check_overlay_scaling(struct put_image_params *rec)
 936 {
 937         u32 tmp;
 938
 939         /* downscaling limit is 8.0 */
 940         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 941         if (tmp > 7)
 942                 return -EINVAL;
 943         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 944         if (tmp > 7)
 945                 return -EINVAL;
 946
 947         return 0;
 948 }
 949
 950 static int check_overlay_src(struct drm_device *dev,
 951                              struct drm_intel_overlay_put_image *rec,
 952                              struct drm_i915_gem_object *new_bo)
 953 {
 954         int uv_hscale = uv_hsubsampling(rec->flags);
 955         int uv_vscale = uv_vsubsampling(rec->flags);
 956         u32 stride_mask;
 957         int depth;
 958         u32 tmp;
 959
 960         /* check src dimensions */
 961         if (IS_845G(dev) || IS_I830(dev)) {
 962                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 963                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 964                         return -EINVAL;
 965         } else {
 966                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 967                     rec->src_width  > IMAGE_MAX_WIDTH)
 968                         return -EINVAL;
 969         }
 970
 971         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 972         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 973             rec->src_width  < N_HORIZ_Y_TAPS*4)
 974                 return -EINVAL;
 975
 976         /* check alignment constraints */
 977         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 978         case I915_OVERLAY_RGB:
 979                 /* not implemented */
 980                 return -EINVAL;
 981
 982         case I915_OVERLAY_YUV_PACKED:
 983                 if (uv_vscale != 1)
 984                         return -EINVAL;
 985
 986                 depth = packed_depth_bytes(rec->flags);
 987                 if (depth < 0)
 988                         return depth;
 989
 990                 /* ignore UV planes */
 991                 rec->stride_UV = 0;
 992                 rec->offset_U = 0;
 993                 rec->offset_V = 0;
 994                 /* check pixel alignment */
 995                 if (rec->offset_Y % depth)
 996                         return -EINVAL;
 997                 break;
 998
 999         case I915_OVERLAY_YUV_PLANAR:
1000                 if (uv_vscale < 0 || uv_hscale < 0)
1001                         return -EINVAL;
1002                 /* no offset restrictions for planar formats */
1003                 break;
1004
1005         default:
1006                 return -EINVAL;
1007         }
1008
1009         if (rec->src_width % uv_hscale)
1010                 return -EINVAL;
1011
1012         /* stride checking */
1013         if (IS_I830(dev) || IS_845G(dev))
1014                 stride_mask = 255;
1015         else
1016                 stride_mask = 63;
1017
1018         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1019                 return -EINVAL;
1020         if (IS_GEN4(dev) && rec->stride_Y < 512)
1021                 return -EINVAL;
1022
1023         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1024                 4096 : 8192;
1025         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1026                 return -EINVAL;
1027
1028         /* check buffer dimensions */
1029         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1030         case I915_OVERLAY_RGB:
1031         case I915_OVERLAY_YUV_PACKED:
1032                 /* always 4 Y values per depth pixels */
1033                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1034                         return -EINVAL;
1035
1036                 tmp = rec->stride_Y*rec->src_height;
1037                 if (rec->offset_Y + tmp > new_bo->base.size)
1038                         return -EINVAL;
1039                 break;
1040
1041         case I915_OVERLAY_YUV_PLANAR:
1042                 if (rec->src_width > rec->stride_Y)
1043                         return -EINVAL;
1044                 if (rec->src_width/uv_hscale > rec->stride_UV)
1045                         return -EINVAL;
1046
1047                 tmp = rec->stride_Y * rec->src_height;
1048                 if (rec->offset_Y + tmp > new_bo->base.size)
1049                         return -EINVAL;
1050
1051                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1052                 if (rec->offset_U + tmp > new_bo->base.size ||
1053                     rec->offset_V + tmp > new_bo->base.size)
1054                         return -EINVAL;
1055                 break;
1056         }
1057
1058         return 0;
1059 }
1060
1061 /**
1062  * Return the pipe currently connected to the panel fitter,
1063  * or -1 if the panel fitter is not present or not in use
1064  */
1065 static int intel_panel_fitter_pipe(struct drm_device *dev)
1066 {
1067         struct drm_i915_private *dev_priv = dev->dev_private;
1068         u32  pfit_control;
1069
1070         /* i830 doesn't have a panel fitter */
1071         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
1072                 return -1;
1073
1074         pfit_control = I915_READ(PFIT_CONTROL);
1075
1076         /* See if the panel fitter is in use */
1077         if ((pfit_control & PFIT_ENABLE) == 0)
1078                 return -1;
1079
1080         /* 965 can place panel fitter on either pipe */
1081         if (IS_GEN4(dev))
1082                 return (pfit_control >> 29) & 0x3;
1083
1084         /* older chips can only use pipe 1 */
1085         return 1;
1086 }
1087
1088 int intel_overlay_put_image(struct drm_device *dev, void *data,
1089                             struct drm_file *file_priv)
1090 {
1091         struct drm_intel_overlay_put_image *put_image_rec = data;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         struct intel_overlay *overlay;
1094         struct drm_crtc *drmmode_crtc;
1095         struct intel_crtc *crtc;
1096         struct drm_i915_gem_object *new_bo;
1097         struct put_image_params *params;
1098         int ret;
1099
1100         overlay = dev_priv->overlay;
1101         if (!overlay) {
1102                 DRM_DEBUG("userspace bug: no overlay\n");
1103                 return -ENODEV;
1104         }
1105
1106         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1107                 drm_modeset_lock_all(dev);
1108                 mutex_lock(&dev->struct_mutex);
1109
1110                 ret = intel_overlay_switch_off(overlay);
1111
1112                 mutex_unlock(&dev->struct_mutex);
1113                 drm_modeset_unlock_all(dev);
1114
1115                 return ret;
1116         }
1117
1118         params = kmalloc(sizeof(*params), GFP_KERNEL);
1119         if (!params)
1120                 return -ENOMEM;
1121
1122         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1123         if (!drmmode_crtc) {
1124                 ret = -ENOENT;
1125                 goto out_free;
1126         }
1127         crtc = to_intel_crtc(drmmode_crtc);
1128
1129         new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1130                                                    put_image_rec->bo_handle));
1131         if (&new_bo->base == NULL) {
1132                 ret = -ENOENT;
1133                 goto out_free;
1134         }
1135
1136         drm_modeset_lock_all(dev);
1137         mutex_lock(&dev->struct_mutex);
1138
1139         if (new_bo->tiling_mode) {
1140                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1141                 ret = -EINVAL;
1142                 goto out_unlock;
1143         }
1144
1145         ret = intel_overlay_recover_from_interrupt(overlay);
1146         if (ret != 0)
1147                 goto out_unlock;
1148
1149         if (overlay->crtc != crtc) {
1150                 struct drm_display_mode *mode = &crtc->base.mode;
1151                 ret = intel_overlay_switch_off(overlay);
1152                 if (ret != 0)
1153                         goto out_unlock;
1154
1155                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1156                 if (ret != 0)
1157                         goto out_unlock;
1158
1159                 overlay->crtc = crtc;
1160                 crtc->overlay = overlay;
1161
1162                 /* line too wide, i.e. one-line-mode */
1163                 if (mode->hdisplay > 1024 &&
1164                     intel_panel_fitter_pipe(dev) == crtc->pipe) {
1165                         overlay->pfit_active = true;
1166                         update_pfit_vscale_ratio(overlay);
1167                 } else
1168                         overlay->pfit_active = false;
1169         }
1170
1171         ret = check_overlay_dst(overlay, put_image_rec);
1172         if (ret != 0)
1173                 goto out_unlock;
1174
1175         if (overlay->pfit_active) {
1176                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1177                                  overlay->pfit_vscale_ratio);
1178                 /* shifting right rounds downwards, so add 1 */
1179                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1180                                  overlay->pfit_vscale_ratio) + 1;
1181         } else {
1182                 params->dst_y = put_image_rec->dst_y;
1183                 params->dst_h = put_image_rec->dst_height;
1184         }
1185         params->dst_x = put_image_rec->dst_x;
1186         params->dst_w = put_image_rec->dst_width;
1187
1188         params->src_w = put_image_rec->src_width;
1189         params->src_h = put_image_rec->src_height;
1190         params->src_scan_w = put_image_rec->src_scan_width;
1191         params->src_scan_h = put_image_rec->src_scan_height;
1192         if (params->src_scan_h > params->src_h ||
1193             params->src_scan_w > params->src_w) {
1194                 ret = -EINVAL;
1195                 goto out_unlock;
1196         }
1197
1198         ret = check_overlay_src(dev, put_image_rec, new_bo);
1199         if (ret != 0)
1200                 goto out_unlock;
1201         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1202         params->stride_Y = put_image_rec->stride_Y;
1203         params->stride_UV = put_image_rec->stride_UV;
1204         params->offset_Y = put_image_rec->offset_Y;
1205         params->offset_U = put_image_rec->offset_U;
1206         params->offset_V = put_image_rec->offset_V;
1207
1208         /* Check scaling after src size to prevent a divide-by-zero. */
1209         ret = check_overlay_scaling(params);
1210         if (ret != 0)
1211                 goto out_unlock;
1212
1213         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1214         if (ret != 0)
1215                 goto out_unlock;
1216
1217         mutex_unlock(&dev->struct_mutex);
1218         drm_modeset_unlock_all(dev);
1219
1220         kfree(params);
1221
1222         return 0;
1223
1224 out_unlock:
1225         mutex_unlock(&dev->struct_mutex);
1226         drm_modeset_unlock_all(dev);
1227         drm_gem_object_unreference_unlocked(&new_bo->base);
1228 out_free:
1229         kfree(params);
1230
1231         return ret;
1232 }
1233
1234 static void update_reg_attrs(struct intel_overlay *overlay,
1235                              struct overlay_registers __iomem *regs)
1236 {
1237         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1238                   &regs->OCLRC0);
1239         iowrite32(overlay->saturation, &regs->OCLRC1);
1240 }
1241
1242 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1243 {
1244         int i;
1245
1246         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1247                 return false;
1248
1249         for (i = 0; i < 3; i++) {
1250                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1251                         return false;
1252         }
1253
1254         return true;
1255 }
1256
1257 static bool check_gamma5_errata(u32 gamma5)
1258 {
1259         int i;
1260
1261         for (i = 0; i < 3; i++) {
1262                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1263                         return false;
1264         }
1265
1266         return true;
1267 }
1268
1269 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1270 {
1271         if (!check_gamma_bounds(0, attrs->gamma0) ||
1272             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1273             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1274             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1275             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1276             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1277             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1278                 return -EINVAL;
1279
1280         if (!check_gamma5_errata(attrs->gamma5))
1281                 return -EINVAL;
1282
1283         return 0;
1284 }
1285
1286 int intel_overlay_attrs(struct drm_device *dev, void *data,
1287                         struct drm_file *file_priv)
1288 {
1289         struct drm_intel_overlay_attrs *attrs = data;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct intel_overlay *overlay;
1292         struct overlay_registers __iomem *regs;
1293         int ret;
1294
1295         overlay = dev_priv->overlay;
1296         if (!overlay) {
1297                 DRM_DEBUG("userspace bug: no overlay\n");
1298                 return -ENODEV;
1299         }
1300
1301         drm_modeset_lock_all(dev);
1302         mutex_lock(&dev->struct_mutex);
1303
1304         ret = -EINVAL;
1305         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1306                 attrs->color_key  = overlay->color_key;
1307                 attrs->brightness = overlay->brightness;
1308                 attrs->contrast   = overlay->contrast;
1309                 attrs->saturation = overlay->saturation;
1310
1311                 if (!IS_GEN2(dev)) {
1312                         attrs->gamma0 = I915_READ(OGAMC0);
1313                         attrs->gamma1 = I915_READ(OGAMC1);
1314                         attrs->gamma2 = I915_READ(OGAMC2);
1315                         attrs->gamma3 = I915_READ(OGAMC3);
1316                         attrs->gamma4 = I915_READ(OGAMC4);
1317                         attrs->gamma5 = I915_READ(OGAMC5);
1318                 }
1319         } else {
1320                 if (attrs->brightness < -128 || attrs->brightness > 127)
1321                         goto out_unlock;
1322                 if (attrs->contrast > 255)
1323                         goto out_unlock;
1324                 if (attrs->saturation > 1023)
1325                         goto out_unlock;
1326
1327                 overlay->color_key  = attrs->color_key;
1328                 overlay->brightness = attrs->brightness;
1329                 overlay->contrast   = attrs->contrast;
1330                 overlay->saturation = attrs->saturation;
1331
1332                 regs = intel_overlay_map_regs(overlay);
1333                 if (!regs) {
1334                         ret = -ENOMEM;
1335                         goto out_unlock;
1336                 }
1337
1338                 update_reg_attrs(overlay, regs);
1339
1340                 intel_overlay_unmap_regs(overlay, regs);
1341
1342                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1343                         if (IS_GEN2(dev))
1344                                 goto out_unlock;
1345
1346                         if (overlay->active) {
1347                                 ret = -EBUSY;
1348                                 goto out_unlock;
1349                         }
1350
1351                         ret = check_gamma(attrs);
1352                         if (ret)
1353                                 goto out_unlock;
1354
1355                         I915_WRITE(OGAMC0, attrs->gamma0);
1356                         I915_WRITE(OGAMC1, attrs->gamma1);
1357                         I915_WRITE(OGAMC2, attrs->gamma2);
1358                         I915_WRITE(OGAMC3, attrs->gamma3);
1359                         I915_WRITE(OGAMC4, attrs->gamma4);
1360                         I915_WRITE(OGAMC5, attrs->gamma5);
1361                 }
1362         }
1363         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1364
1365         ret = 0;
1366 out_unlock:
1367         mutex_unlock(&dev->struct_mutex);
1368         drm_modeset_unlock_all(dev);
1369
1370         return ret;
1371 }
1372
1373 void intel_setup_overlay(struct drm_device *dev)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         struct intel_overlay *overlay;
1377         struct drm_i915_gem_object *reg_bo;
1378         struct overlay_registers __iomem *regs;
1379         int ret;
1380
1381         if (!HAS_OVERLAY(dev))
1382                 return;
1383
1384         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1385         if (!overlay)
1386                 return;
1387
1388         mutex_lock(&dev->struct_mutex);
1389         if (WARN_ON(dev_priv->overlay))
1390                 goto out_free;
1391
1392         overlay->dev = dev;
1393
1394         reg_bo = NULL;
1395         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1396                 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
1397         if (reg_bo == NULL)
1398                 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1399         if (reg_bo == NULL)
1400                 goto out_free;
1401         overlay->reg_bo = reg_bo;
1402
1403         if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1404                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1405                 if (ret) {
1406                         DRM_ERROR("failed to attach phys overlay regs\n");
1407                         goto out_free_bo;
1408                 }
1409                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1410         } else {
1411                 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
1412                 if (ret) {
1413                         DRM_ERROR("failed to pin overlay register bo\n");
1414                         goto out_free_bo;
1415                 }
1416                 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
1417
1418                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1419                 if (ret) {
1420                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1421                         goto out_unpin_bo;
1422                 }
1423         }
1424
1425         /* init all values */
1426         overlay->color_key = 0x0101fe;
1427         overlay->color_key_enabled = true;
1428         overlay->brightness = -19;
1429         overlay->contrast = 75;
1430         overlay->saturation = 146;
1431
1432         regs = intel_overlay_map_regs(overlay);
1433         if (!regs)
1434                 goto out_unpin_bo;
1435
1436         memset_io(regs, 0, sizeof(struct overlay_registers));
1437         update_polyphase_filter(regs);
1438         update_reg_attrs(overlay, regs);
1439
1440         intel_overlay_unmap_regs(overlay, regs);
1441
1442         dev_priv->overlay = overlay;
1443         mutex_unlock(&dev->struct_mutex);
1444         DRM_INFO("initialized overlay support\n");
1445         return;
1446
1447 out_unpin_bo:
1448         if (!OVERLAY_NEEDS_PHYSICAL(dev))
1449                 i915_gem_object_ggtt_unpin(reg_bo);
1450 out_free_bo:
1451         drm_gem_object_unreference(&reg_bo->base);
1452 out_free:
1453         mutex_unlock(&dev->struct_mutex);
1454         kfree(overlay);
1455         return;
1456 }
1457
1458 void intel_cleanup_overlay(struct drm_device *dev)
1459 {
1460         struct drm_i915_private *dev_priv = dev->dev_private;
1461
1462         if (!dev_priv->overlay)
1463                 return;
1464
1465         /* The bo's should be free'd by the generic code already.
1466          * Furthermore modesetting teardown happens beforehand so the
1467          * hardware should be off already */
1468         WARN_ON(dev_priv->overlay->active);
1469
1470         drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1471         kfree(dev_priv->overlay);
1472 }
1473
1474 struct intel_overlay_error_state {
1475         struct overlay_registers regs;
1476         unsigned long base;
1477         u32 dovsta;
1478         u32 isr;
1479 };
1480
1481 static struct overlay_registers __iomem *
1482 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1483 {
1484         struct drm_i915_private *dev_priv = overlay->dev->dev_private;
1485         struct overlay_registers __iomem *regs;
1486
1487         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1488                 /* Cast to make sparse happy, but it's wc memory anyway, so
1489                  * equivalent to the wc io mapping on X86. */
1490                 regs = (struct overlay_registers __iomem *)
1491                         overlay->reg_bo->phys_handle->vaddr;
1492         else
1493                 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1494                                                 i915_gem_obj_ggtt_offset(overlay->reg_bo));
1495
1496         return regs;
1497 }
1498
1499 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1500                                         struct overlay_registers __iomem *regs)
1501 {
1502         if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1503                 io_mapping_unmap_atomic(regs);
1504 }
1505
1506
1507 struct intel_overlay_error_state *
1508 intel_overlay_capture_error_state(struct drm_device *dev)
1509 {
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         struct intel_overlay *overlay = dev_priv->overlay;
1512         struct intel_overlay_error_state *error;
1513         struct overlay_registers __iomem *regs;
1514
1515         if (!overlay || !overlay->active)
1516                 return NULL;
1517
1518         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1519         if (error == NULL)
1520                 return NULL;
1521
1522         error->dovsta = I915_READ(DOVSTA);
1523         error->isr = I915_READ(ISR);
1524         if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1525                 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
1526         else
1527                 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
1528
1529         regs = intel_overlay_map_regs_atomic(overlay);
1530         if (!regs)
1531                 goto err;
1532
1533         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1534         intel_overlay_unmap_regs_atomic(overlay, regs);
1535
1536         return error;
1537
1538 err:
1539         kfree(error);
1540         return NULL;
1541 }
1542
1543 void
1544 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1545                                 struct intel_overlay_error_state *error)
1546 {
1547         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1548                           error->dovsta, error->isr);
1549         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1550                           error->base);
1551
1552 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1553         P(OBUF_0Y);
1554         P(OBUF_1Y);
1555         P(OBUF_0U);
1556         P(OBUF_0V);
1557         P(OBUF_1U);
1558         P(OBUF_1V);
1559         P(OSTRIDE);
1560         P(YRGB_VPH);
1561         P(UV_VPH);
1562         P(HORZ_PH);
1563         P(INIT_PHS);
1564         P(DWINPOS);
1565         P(DWINSZ);
1566         P(SWIDTH);
1567         P(SWIDTHSW);
1568         P(SHEIGHT);
1569         P(YRGBSCALE);
1570         P(UVSCALE);
1571         P(OCLRC0);
1572         P(OCLRC1);
1573         P(DCLRKV);
1574         P(DCLRKM);
1575         P(SCLRKVH);
1576         P(SCLRKVL);
1577         P(SCLRKEN);
1578         P(OCONFIG);
1579         P(OCMD);
1580         P(OSTART_0Y);
1581         P(OSTART_1Y);
1582         P(OSTART_0U);
1583         P(OSTART_0V);
1584         P(OSTART_1U);
1585         P(OSTART_1V);
1586         P(OTILEOFF_0Y);
1587         P(OTILEOFF_1Y);
1588         P(OTILEOFF_0U);
1589         P(OTILEOFF_0V);
1590         P(OTILEOFF_1U);
1591         P(OTILEOFF_1V);
1592         P(FASTHSCALE);
1593         P(UVSCALEV);
1594 #undef P
1595 }