2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "intel_lrc_reg.h"
141 #include "intel_mocs.h"
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define GEN8_CTX_STATUS_COMPLETED_MASK \
158 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
160 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
161 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
162 #define WA_TAIL_DWORDS 2
163 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
165 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
166 struct intel_engine_cs *engine);
167 static void execlists_init_reg_state(u32 *reg_state,
168 struct i915_gem_context *ctx,
169 struct intel_engine_cs *engine,
170 struct intel_ring *ring);
172 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
174 return rb_entry(rb, struct i915_priolist, node);
177 static inline int rq_prio(const struct i915_request *rq)
179 return rq->priotree.priority;
182 static inline bool need_preempt(const struct intel_engine_cs *engine,
183 const struct i915_request *last,
186 return engine->i915->preempt_context && prio > max(rq_prio(last), 0);
190 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
191 * descriptor for a pinned context
192 * @ctx: Context to work on
193 * @engine: Engine the descriptor will be used with
195 * The context descriptor encodes various attributes of a context,
196 * including its GTT address and some flags. Because it's fairly
197 * expensive to calculate, we'll just do it once and cache the result,
198 * which remains valid until the context is unpinned.
200 * This is what a descriptor looks like, from LSB to MSB::
202 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
203 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
204 * bits 32-52: ctx ID, a globally unique tag
205 * bits 53-54: mbz, reserved for use by hardware
206 * bits 55-63: group ID, currently unused and set to 0
208 * Starting from Gen11, the upper dword of the descriptor has a new format:
210 * bits 32-36: reserved
211 * bits 37-47: SW context ID
212 * bits 48:53: engine instance
213 * bit 54: mbz, reserved for use by hardware
214 * bits 55-60: SW counter
215 * bits 61-63: engine class
217 * engine info, SW context ID and SW counter need to form a unique number
218 * (Context ID) per lrc.
221 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
222 struct intel_engine_cs *engine)
224 struct intel_context *ce = &ctx->engine[engine->id];
227 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
228 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
230 desc = ctx->desc_template; /* bits 0-11 */
231 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
233 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
235 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
237 if (INTEL_GEN(ctx->i915) >= 11) {
238 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
239 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
242 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
245 /* TODO: decide what to do with SW counter (bits 55-60) */
247 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
250 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
251 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
257 static struct i915_priolist *
258 lookup_priolist(struct intel_engine_cs *engine,
259 struct i915_priotree *pt,
262 struct intel_engine_execlists * const execlists = &engine->execlists;
263 struct i915_priolist *p;
264 struct rb_node **parent, *rb;
267 if (unlikely(execlists->no_priolist))
268 prio = I915_PRIORITY_NORMAL;
271 /* most positive priority is scheduled first, equal priorities fifo */
273 parent = &execlists->queue.rb_node;
277 if (prio > p->priority) {
278 parent = &rb->rb_left;
279 } else if (prio < p->priority) {
280 parent = &rb->rb_right;
287 if (prio == I915_PRIORITY_NORMAL) {
288 p = &execlists->default_priolist;
290 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
291 /* Convert an allocation failure to a priority bump */
293 prio = I915_PRIORITY_NORMAL; /* recurses just once */
295 /* To maintain ordering with all rendering, after an
296 * allocation failure we have to disable all scheduling.
297 * Requests will then be executed in fifo, and schedule
298 * will ensure that dependencies are emitted in fifo.
299 * There will be still some reordering with existing
300 * requests, so if userspace lied about their
301 * dependencies that reordering may be visible.
303 execlists->no_priolist = true;
309 INIT_LIST_HEAD(&p->requests);
310 rb_link_node(&p->node, rb, parent);
311 rb_insert_color(&p->node, &execlists->queue);
314 execlists->first = &p->node;
319 static void unwind_wa_tail(struct i915_request *rq)
321 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
322 assert_ring_tail_valid(rq->ring, rq->tail);
325 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
327 struct i915_request *rq, *rn;
328 struct i915_priolist *uninitialized_var(p);
329 int last_prio = I915_PRIORITY_INVALID;
331 lockdep_assert_held(&engine->timeline->lock);
333 list_for_each_entry_safe_reverse(rq, rn,
334 &engine->timeline->requests,
336 if (i915_request_completed(rq))
339 __i915_request_unsubmit(rq);
342 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
343 if (rq_prio(rq) != last_prio) {
344 last_prio = rq_prio(rq);
345 p = lookup_priolist(engine, &rq->priotree, last_prio);
348 list_add(&rq->priotree.link, &p->requests);
353 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
355 struct intel_engine_cs *engine =
356 container_of(execlists, typeof(*engine), execlists);
358 spin_lock_irq(&engine->timeline->lock);
359 __unwind_incomplete_requests(engine);
360 spin_unlock_irq(&engine->timeline->lock);
364 execlists_context_status_change(struct i915_request *rq, unsigned long status)
367 * Only used when GVT-g is enabled now. When GVT-g is disabled,
368 * The compiler should eliminate this function as dead-code.
370 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
373 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
378 execlists_context_schedule_in(struct i915_request *rq)
380 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
381 intel_engine_context_in(rq->engine);
385 execlists_context_schedule_out(struct i915_request *rq)
387 intel_engine_context_out(rq->engine);
388 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
392 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
394 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
395 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
396 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
397 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
400 static u64 execlists_update_context(struct i915_request *rq)
402 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
403 struct i915_hw_ppgtt *ppgtt =
404 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
405 u32 *reg_state = ce->lrc_reg_state;
407 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
409 /* True 32b PPGTT with dynamic page allocation: update PDP
410 * registers and point the unallocated PDPs to scratch page.
411 * PML4 is allocated during ppgtt init, so this is not needed
414 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
415 execlists_update_context_pdps(ppgtt, reg_state);
420 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
422 if (execlists->ctrl_reg) {
423 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
424 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
426 writel(upper_32_bits(desc), execlists->submit_reg);
427 writel(lower_32_bits(desc), execlists->submit_reg);
431 static void execlists_submit_ports(struct intel_engine_cs *engine)
433 struct intel_engine_execlists *execlists = &engine->execlists;
434 struct execlist_port *port = execlists->port;
438 * ELSQ note: the submit queue is not cleared after being submitted
439 * to the HW so we need to make sure we always clean it up. This is
440 * currently ensured by the fact that we always write the same number
441 * of elsq entries, keep this in mind before changing the loop below.
443 for (n = execlists_num_ports(execlists); n--; ) {
444 struct i915_request *rq;
448 rq = port_unpack(&port[n], &count);
450 GEM_BUG_ON(count > !n);
452 execlists_context_schedule_in(rq);
453 port_set(&port[n], port_pack(rq, count));
454 desc = execlists_update_context(rq);
455 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
457 GEM_TRACE("%s in[%d]: ctx=%d.%d, seqno=%x, prio=%d\n",
459 port[n].context_id, count,
467 write_desc(execlists, desc, n);
470 /* we need to manually load the submit queue */
471 if (execlists->ctrl_reg)
472 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
474 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
477 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
479 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
480 i915_gem_context_force_single_submission(ctx));
483 static bool can_merge_ctx(const struct i915_gem_context *prev,
484 const struct i915_gem_context *next)
489 if (ctx_single_port_submission(prev))
495 static void port_assign(struct execlist_port *port, struct i915_request *rq)
497 GEM_BUG_ON(rq == port_request(port));
499 if (port_isset(port))
500 i915_request_put(port_request(port));
502 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
505 static void inject_preempt_context(struct intel_engine_cs *engine)
507 struct intel_engine_execlists *execlists = &engine->execlists;
508 struct intel_context *ce =
509 &engine->i915->preempt_context->engine[engine->id];
512 GEM_BUG_ON(execlists->preempt_complete_status !=
513 upper_32_bits(ce->lrc_desc));
514 GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
515 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
516 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=
517 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
518 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
521 * Switch to our empty preempt context so
522 * the state of the GPU is known (idle).
524 GEM_TRACE("%s\n", engine->name);
525 for (n = execlists_num_ports(execlists); --n; )
526 write_desc(execlists, 0, n);
528 write_desc(execlists, ce->lrc_desc, n);
530 /* we need to manually load the submit queue */
531 if (execlists->ctrl_reg)
532 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
534 execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
535 execlists_set_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT);
538 static void execlists_dequeue(struct intel_engine_cs *engine)
540 struct intel_engine_execlists * const execlists = &engine->execlists;
541 struct execlist_port *port = execlists->port;
542 const struct execlist_port * const last_port =
543 &execlists->port[execlists->port_mask];
544 struct i915_request *last = port_request(port);
548 /* Hardware submission is through 2 ports. Conceptually each port
549 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
550 * static for a context, and unique to each, so we only execute
551 * requests belonging to a single context from each ring. RING_HEAD
552 * is maintained by the CS in the context image, it marks the place
553 * where it got up to last time, and through RING_TAIL we tell the CS
554 * where we want to execute up to this time.
556 * In this list the requests are in order of execution. Consecutive
557 * requests from the same context are adjacent in the ringbuffer. We
558 * can combine these requests into a single RING_TAIL update:
560 * RING_HEAD...req1...req2
562 * since to execute req2 the CS must first execute req1.
564 * Our goal then is to point each port to the end of a consecutive
565 * sequence of requests as being the most optimal (fewest wake ups
566 * and context switches) submission.
569 spin_lock_irq(&engine->timeline->lock);
570 rb = execlists->first;
571 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
575 * Don't resubmit or switch until all outstanding
576 * preemptions (lite-restore) are seen. Then we
577 * know the next preemption status we see corresponds
578 * to this ELSP update.
580 GEM_BUG_ON(!port_count(&port[0]));
581 if (port_count(&port[0]) > 1)
585 * If we write to ELSP a second time before the HW has had
586 * a chance to respond to the previous write, we can confuse
587 * the HW and hit "undefined behaviour". After writing to ELSP,
588 * we must then wait until we see a context-switch event from
589 * the HW to indicate that it has had a chance to respond.
591 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
594 if (need_preempt(engine, last, execlists->queue_priority)) {
595 inject_preempt_context(engine);
600 * In theory, we could coalesce more requests onto
601 * the second port (the first port is active, with
602 * no preemptions pending). However, that means we
603 * then have to deal with the possible lite-restore
604 * of the second port (as we submit the ELSP, there
605 * may be a context-switch) but also we may complete
606 * the resubmission before the context-switch. Ergo,
607 * coalescing onto the second port will cause a
608 * preemption event, but we cannot predict whether
609 * that will affect port[0] or port[1].
611 * If the second port is already active, we can wait
612 * until the next context-switch before contemplating
613 * new requests. The GPU will be busy and we should be
614 * able to resubmit the new ELSP before it idles,
615 * avoiding pipeline bubbles (momentary pauses where
616 * the driver is unable to keep up the supply of new
617 * work). However, we have to double check that the
618 * priorities of the ports haven't been switch.
620 if (port_count(&port[1]))
624 * WaIdleLiteRestore:bdw,skl
625 * Apply the wa NOOPs to prevent
626 * ring:HEAD == rq:TAIL as we resubmit the
627 * request. See gen8_emit_breadcrumb() for
628 * where we prepare the padding after the
629 * end of the request.
631 last->tail = last->wa_tail;
635 struct i915_priolist *p = to_priolist(rb);
636 struct i915_request *rq, *rn;
638 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
640 * Can we combine this request with the current port?
641 * It has to be the same context/ringbuffer and not
642 * have any exceptions (e.g. GVT saying never to
645 * If we can combine the requests, we can execute both
646 * by updating the RING_TAIL to point to the end of the
647 * second request, and so we never need to tell the
648 * hardware about the first.
650 if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
652 * If we are on the second port and cannot
653 * combine this request with the last, then we
656 if (port == last_port) {
657 __list_del_many(&p->requests,
663 * If GVT overrides us we only ever submit
664 * port[0], leaving port[1] empty. Note that we
665 * also have to be careful that we don't queue
666 * the same context (even though a different
667 * request) to the second port.
669 if (ctx_single_port_submission(last->ctx) ||
670 ctx_single_port_submission(rq->ctx)) {
671 __list_del_many(&p->requests,
676 GEM_BUG_ON(last->ctx == rq->ctx);
679 port_assign(port, last);
682 GEM_BUG_ON(port_isset(port));
685 INIT_LIST_HEAD(&rq->priotree.link);
686 __i915_request_submit(rq);
687 trace_i915_request_in(rq, port_index(port, execlists));
693 rb_erase(&p->node, &execlists->queue);
694 INIT_LIST_HEAD(&p->requests);
695 if (p->priority != I915_PRIORITY_NORMAL)
696 kmem_cache_free(engine->i915->priorities, p);
699 execlists->queue_priority = rb ? to_priolist(rb)->priority : INT_MIN;
700 execlists->first = rb;
702 port_assign(port, last);
704 /* We must always keep the beast fed if we have work piled up */
705 GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
708 spin_unlock_irq(&engine->timeline->lock);
711 execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
712 execlists_submit_ports(engine);
715 GEM_BUG_ON(port_isset(execlists->port) &&
716 !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
720 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
722 struct execlist_port *port = execlists->port;
723 unsigned int num_ports = execlists_num_ports(execlists);
725 while (num_ports-- && port_isset(port)) {
726 struct i915_request *rq = port_request(port);
728 GEM_BUG_ON(!execlists->active);
729 intel_engine_context_out(rq->engine);
731 execlists_context_status_change(rq,
732 i915_request_completed(rq) ?
733 INTEL_CONTEXT_SCHEDULE_OUT :
734 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
736 i915_request_put(rq);
738 memset(port, 0, sizeof(*port));
743 static void execlists_cancel_requests(struct intel_engine_cs *engine)
745 struct intel_engine_execlists * const execlists = &engine->execlists;
746 struct i915_request *rq, *rn;
750 GEM_TRACE("%s\n", engine->name);
753 * Before we call engine->cancel_requests(), we should have exclusive
754 * access to the submission state. This is arranged for us by the
755 * caller disabling the interrupt generation, the tasklet and other
756 * threads that may then access the same state, giving us a free hand
757 * to reset state. However, we still need to let lockdep be aware that
758 * we know this state may be accessed in hardirq context, so we
759 * disable the irq around this manipulation and we want to keep
760 * the spinlock focused on its duties and not accidentally conflate
761 * coverage to the submission's irq state. (Similarly, although we
762 * shouldn't need to disable irq around the manipulation of the
763 * submission's irq state, we also wish to remind ourselves that
766 local_irq_save(flags);
768 /* Cancel the requests on the HW and clear the ELSP tracker. */
769 execlists_cancel_port_requests(execlists);
771 spin_lock(&engine->timeline->lock);
773 /* Mark all executing requests as skipped. */
774 list_for_each_entry(rq, &engine->timeline->requests, link) {
775 GEM_BUG_ON(!rq->global_seqno);
776 if (!i915_request_completed(rq))
777 dma_fence_set_error(&rq->fence, -EIO);
780 /* Flush the queued requests to the timeline list (for retiring). */
781 rb = execlists->first;
783 struct i915_priolist *p = to_priolist(rb);
785 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
786 INIT_LIST_HEAD(&rq->priotree.link);
788 dma_fence_set_error(&rq->fence, -EIO);
789 __i915_request_submit(rq);
793 rb_erase(&p->node, &execlists->queue);
794 INIT_LIST_HEAD(&p->requests);
795 if (p->priority != I915_PRIORITY_NORMAL)
796 kmem_cache_free(engine->i915->priorities, p);
799 /* Remaining _unready_ requests will be nop'ed when submitted */
801 execlists->queue_priority = INT_MIN;
802 execlists->queue = RB_ROOT;
803 execlists->first = NULL;
804 GEM_BUG_ON(port_isset(execlists->port));
806 spin_unlock(&engine->timeline->lock);
809 * The port is checked prior to scheduling a tasklet, but
810 * just in case we have suspended the tasklet to do the
811 * wedging make sure that when it wakes, it decides there
812 * is no work to do by clearing the irq_posted bit.
814 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
816 /* Mark all CS interrupts as complete */
817 execlists->active = 0;
819 local_irq_restore(flags);
823 * Check the unread Context Status Buffers and manage the submission of new
824 * contexts to the ELSP accordingly.
826 static void execlists_submission_tasklet(unsigned long data)
828 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
829 struct intel_engine_execlists * const execlists = &engine->execlists;
830 struct execlist_port * const port = execlists->port;
831 struct drm_i915_private *dev_priv = engine->i915;
835 * We can skip acquiring intel_runtime_pm_get() here as it was taken
836 * on our behalf by the request (see i915_gem_mark_busy()) and it will
837 * not be relinquished until the device is idle (see
838 * i915_gem_idle_work_handler()). As a precaution, we make sure
839 * that all ELSP are drained i.e. we have processed the CSB,
840 * before allowing ourselves to idle and calling intel_runtime_pm_put().
842 GEM_BUG_ON(!dev_priv->gt.awake);
845 * Prefer doing test_and_clear_bit() as a two stage operation to avoid
846 * imposing the cost of a locked atomic transaction when submitting a
847 * new request (outside of the context-switch interrupt).
849 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
850 /* The HWSP contains a (cacheable) mirror of the CSB */
852 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
853 unsigned int head, tail;
855 if (unlikely(execlists->csb_use_mmio)) {
856 buf = (u32 * __force)
857 (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
858 execlists->csb_head = -1; /* force mmio read of CSB ptrs */
861 /* Clear before reading to catch new interrupts */
862 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
863 smp_mb__after_atomic();
865 if (unlikely(execlists->csb_head == -1)) { /* following a reset */
867 intel_uncore_forcewake_get(dev_priv,
868 execlists->fw_domains);
872 head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
873 tail = GEN8_CSB_WRITE_PTR(head);
874 head = GEN8_CSB_READ_PTR(head);
875 execlists->csb_head = head;
877 const int write_idx =
878 intel_hws_csb_write_index(dev_priv) -
879 I915_HWS_CSB_BUF0_INDEX;
881 head = execlists->csb_head;
882 tail = READ_ONCE(buf[write_idx]);
884 GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
886 head, GEN8_CSB_READ_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?",
887 tail, GEN8_CSB_WRITE_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?");
889 while (head != tail) {
890 struct i915_request *rq;
894 if (++head == GEN8_CSB_ENTRIES)
897 /* We are flying near dragons again.
899 * We hold a reference to the request in execlist_port[]
900 * but no more than that. We are operating in softirq
901 * context and so cannot hold any mutex or sleep. That
902 * prevents us stopping the requests we are processing
903 * in port[] from being retired simultaneously (the
904 * breadcrumb will be complete before we see the
905 * context-switch). As we only hold the reference to the
906 * request, any pointer chasing underneath the request
907 * is subject to a potential use-after-free. Thus we
908 * store all of the bookkeeping within port[] as
909 * required, and avoid using unguarded pointers beneath
910 * request itself. The same applies to the atomic
914 status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
915 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
917 status, buf[2*head + 1],
920 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
921 GEN8_CTX_STATUS_PREEMPTED))
922 execlists_set_active(execlists,
923 EXECLISTS_ACTIVE_HWACK);
924 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
925 execlists_clear_active(execlists,
926 EXECLISTS_ACTIVE_HWACK);
928 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
931 /* We should never get a COMPLETED | IDLE_ACTIVE! */
932 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
934 if (status & GEN8_CTX_STATUS_COMPLETE &&
935 buf[2*head + 1] == execlists->preempt_complete_status) {
936 GEM_TRACE("%s preempt-idle\n", engine->name);
938 execlists_cancel_port_requests(execlists);
939 execlists_unwind_incomplete_requests(execlists);
941 GEM_BUG_ON(!execlists_is_active(execlists,
942 EXECLISTS_ACTIVE_PREEMPT));
943 execlists_clear_active(execlists,
944 EXECLISTS_ACTIVE_PREEMPT);
948 if (status & GEN8_CTX_STATUS_PREEMPTED &&
949 execlists_is_active(execlists,
950 EXECLISTS_ACTIVE_PREEMPT))
953 GEM_BUG_ON(!execlists_is_active(execlists,
954 EXECLISTS_ACTIVE_USER));
956 rq = port_unpack(port, &count);
957 GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x, prio=%d\n",
959 port->context_id, count,
960 rq ? rq->global_seqno : 0,
961 rq ? rq_prio(rq) : 0);
963 /* Check the context/desc id for this event matches */
964 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
966 GEM_BUG_ON(count == 0);
968 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
969 GEM_BUG_ON(port_isset(&port[1]) &&
970 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
971 GEM_BUG_ON(!i915_request_completed(rq));
972 execlists_context_schedule_out(rq);
973 trace_i915_request_out(rq);
974 i915_request_put(rq);
976 GEM_TRACE("%s completed ctx=%d\n",
977 engine->name, port->context_id);
979 execlists_port_complete(execlists, port);
981 port_set(port, port_pack(rq, count));
984 /* After the final element, the hw should be idle */
985 GEM_BUG_ON(port_count(port) == 0 &&
986 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
987 if (port_count(port) == 0)
988 execlists_clear_active(execlists,
989 EXECLISTS_ACTIVE_USER);
992 if (head != execlists->csb_head) {
993 execlists->csb_head = head;
994 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
995 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
999 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
1000 execlists_dequeue(engine);
1003 intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
1006 static void queue_request(struct intel_engine_cs *engine,
1007 struct i915_priotree *pt,
1010 list_add_tail(&pt->link, &lookup_priolist(engine, pt, prio)->requests);
1013 static void submit_queue(struct intel_engine_cs *engine, int prio)
1015 if (prio > engine->execlists.queue_priority) {
1016 engine->execlists.queue_priority = prio;
1017 tasklet_hi_schedule(&engine->execlists.tasklet);
1021 static void execlists_submit_request(struct i915_request *request)
1023 struct intel_engine_cs *engine = request->engine;
1024 unsigned long flags;
1026 /* Will be called from irq-context when using foreign fences. */
1027 spin_lock_irqsave(&engine->timeline->lock, flags);
1029 queue_request(engine, &request->priotree, rq_prio(request));
1030 submit_queue(engine, rq_prio(request));
1032 GEM_BUG_ON(!engine->execlists.first);
1033 GEM_BUG_ON(list_empty(&request->priotree.link));
1035 spin_unlock_irqrestore(&engine->timeline->lock, flags);
1038 static struct i915_request *pt_to_request(struct i915_priotree *pt)
1040 return container_of(pt, struct i915_request, priotree);
1043 static struct intel_engine_cs *
1044 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
1046 struct intel_engine_cs *engine = pt_to_request(pt)->engine;
1048 GEM_BUG_ON(!locked);
1050 if (engine != locked) {
1051 spin_unlock(&locked->timeline->lock);
1052 spin_lock(&engine->timeline->lock);
1058 static void execlists_schedule(struct i915_request *request, int prio)
1060 struct intel_engine_cs *engine;
1061 struct i915_dependency *dep, *p;
1062 struct i915_dependency stack;
1065 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
1067 if (i915_request_completed(request))
1070 if (prio <= READ_ONCE(request->priotree.priority))
1073 /* Need BKL in order to use the temporary link inside i915_dependency */
1074 lockdep_assert_held(&request->i915->drm.struct_mutex);
1076 stack.signaler = &request->priotree;
1077 list_add(&stack.dfs_link, &dfs);
1080 * Recursively bump all dependent priorities to match the new request.
1082 * A naive approach would be to use recursion:
1083 * static void update_priorities(struct i915_priotree *pt, prio) {
1084 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
1085 * update_priorities(dep->signal, prio)
1086 * queue_request(pt);
1088 * but that may have unlimited recursion depth and so runs a very
1089 * real risk of overunning the kernel stack. Instead, we build
1090 * a flat list of all dependencies starting with the current request.
1091 * As we walk the list of dependencies, we add all of its dependencies
1092 * to the end of the list (this may include an already visited
1093 * request) and continue to walk onwards onto the new dependencies. The
1094 * end result is a topological list of requests in reverse order, the
1095 * last element in the list is the request we must execute first.
1097 list_for_each_entry(dep, &dfs, dfs_link) {
1098 struct i915_priotree *pt = dep->signaler;
1101 * Within an engine, there can be no cycle, but we may
1102 * refer to the same dependency chain multiple times
1103 * (redundant dependencies are not eliminated) and across
1106 list_for_each_entry(p, &pt->signalers_list, signal_link) {
1107 GEM_BUG_ON(p == dep); /* no cycles! */
1109 if (i915_priotree_signaled(p->signaler))
1112 GEM_BUG_ON(p->signaler->priority < pt->priority);
1113 if (prio > READ_ONCE(p->signaler->priority))
1114 list_move_tail(&p->dfs_link, &dfs);
1119 * If we didn't need to bump any existing priorities, and we haven't
1120 * yet submitted this request (i.e. there is no potential race with
1121 * execlists_submit_request()), we can set our own priority and skip
1122 * acquiring the engine locks.
1124 if (request->priotree.priority == I915_PRIORITY_INVALID) {
1125 GEM_BUG_ON(!list_empty(&request->priotree.link));
1126 request->priotree.priority = prio;
1127 if (stack.dfs_link.next == stack.dfs_link.prev)
1129 __list_del_entry(&stack.dfs_link);
1132 engine = request->engine;
1133 spin_lock_irq(&engine->timeline->lock);
1135 /* Fifo and depth-first replacement ensure our deps execute before us */
1136 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1137 struct i915_priotree *pt = dep->signaler;
1139 INIT_LIST_HEAD(&dep->dfs_link);
1141 engine = pt_lock_engine(pt, engine);
1143 if (prio <= pt->priority)
1146 pt->priority = prio;
1147 if (!list_empty(&pt->link)) {
1148 __list_del_entry(&pt->link);
1149 queue_request(engine, pt, prio);
1151 submit_queue(engine, prio);
1154 spin_unlock_irq(&engine->timeline->lock);
1157 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1163 * Clear this page out of any CPU caches for coherent swap-in/out.
1164 * We only want to do this on the first bind so that we do not stall
1165 * on an active context (which by nature is already on the GPU).
1167 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1168 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1173 flags = PIN_GLOBAL | PIN_HIGH;
1174 if (ctx->ggtt_offset_bias)
1175 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1177 return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1180 static struct intel_ring *
1181 execlists_context_pin(struct intel_engine_cs *engine,
1182 struct i915_gem_context *ctx)
1184 struct intel_context *ce = &ctx->engine[engine->id];
1188 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1190 if (likely(ce->pin_count++))
1192 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1194 ret = execlists_context_deferred_alloc(ctx, engine);
1197 GEM_BUG_ON(!ce->state);
1199 ret = __context_pin(ctx, ce->state);
1203 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1204 if (IS_ERR(vaddr)) {
1205 ret = PTR_ERR(vaddr);
1209 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1213 intel_lr_context_descriptor_update(ctx, engine);
1215 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1216 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1217 i915_ggtt_offset(ce->ring->vma);
1219 ce->state->obj->pin_global++;
1220 i915_gem_context_get(ctx);
1225 i915_gem_object_unpin_map(ce->state->obj);
1227 __i915_vma_unpin(ce->state);
1230 return ERR_PTR(ret);
1233 static void execlists_context_unpin(struct intel_engine_cs *engine,
1234 struct i915_gem_context *ctx)
1236 struct intel_context *ce = &ctx->engine[engine->id];
1238 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1239 GEM_BUG_ON(ce->pin_count == 0);
1241 if (--ce->pin_count)
1244 intel_ring_unpin(ce->ring);
1246 ce->state->obj->pin_global--;
1247 i915_gem_object_unpin_map(ce->state->obj);
1248 i915_vma_unpin(ce->state);
1250 i915_gem_context_put(ctx);
1253 static int execlists_request_alloc(struct i915_request *request)
1255 struct intel_engine_cs *engine = request->engine;
1256 struct intel_context *ce = &request->ctx->engine[engine->id];
1259 GEM_BUG_ON(!ce->pin_count);
1261 /* Flush enough space to reduce the likelihood of waiting after
1262 * we start building the request - in which case we will just
1263 * have to repeat work.
1265 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1267 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1271 /* Note that after this point, we have committed to using
1272 * this request as it is being used to both track the
1273 * state of engine initialisation and liveness of the
1274 * golden renderstate above. Think twice before you try
1275 * to cancel/unwind this request now.
1278 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1283 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1284 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1285 * but there is a slight complication as this is applied in WA batch where the
1286 * values are only initialized once so we cannot take register value at the
1287 * beginning and reuse it further; hence we save its value to memory, upload a
1288 * constant value with bit21 set and then we restore it back with the saved value.
1289 * To simplify the WA, a constant value is formed by using the default value
1290 * of this register. This shouldn't be a problem because we are only modifying
1291 * it for a short period and this batch in non-premptible. We can ofcourse
1292 * use additional instructions that read the actual value of the register
1293 * at that time and set our bit of interest but it makes the WA complicated.
1295 * This WA is also required for Gen9 so extracting as a function avoids
1299 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1301 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1302 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1303 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1306 *batch++ = MI_LOAD_REGISTER_IMM(1);
1307 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1308 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1310 batch = gen8_emit_pipe_control(batch,
1311 PIPE_CONTROL_CS_STALL |
1312 PIPE_CONTROL_DC_FLUSH_ENABLE,
1315 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1316 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1317 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1324 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1325 * initialized at the beginning and shared across all contexts but this field
1326 * helps us to have multiple batches at different offsets and select them based
1327 * on a criteria. At the moment this batch always start at the beginning of the page
1328 * and at this point we don't have multiple wa_ctx batch buffers.
1330 * The number of WA applied are not known at the beginning; we use this field
1331 * to return the no of DWORDS written.
1333 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1334 * so it adds NOOPs as padding to make it cacheline aligned.
1335 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1336 * makes a complete batch buffer.
1338 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1340 /* WaDisableCtxRestoreArbitration:bdw,chv */
1341 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1343 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1344 if (IS_BROADWELL(engine->i915))
1345 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1347 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1348 /* Actual scratch location is at 128 bytes offset */
1349 batch = gen8_emit_pipe_control(batch,
1350 PIPE_CONTROL_FLUSH_L3 |
1351 PIPE_CONTROL_GLOBAL_GTT_IVB |
1352 PIPE_CONTROL_CS_STALL |
1353 PIPE_CONTROL_QW_WRITE,
1354 i915_ggtt_offset(engine->scratch) +
1355 2 * CACHELINE_BYTES);
1357 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1359 /* Pad to end of cacheline */
1360 while ((unsigned long)batch % CACHELINE_BYTES)
1364 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1365 * execution depends on the length specified in terms of cache lines
1366 * in the register CTX_RCS_INDIRECT_CTX
1372 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1374 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1376 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1377 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1379 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1380 *batch++ = MI_LOAD_REGISTER_IMM(1);
1381 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1382 *batch++ = _MASKED_BIT_DISABLE(
1383 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1386 /* WaClearSlmSpaceAtContextSwitch:kbl */
1387 /* Actual scratch location is at 128 bytes offset */
1388 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1389 batch = gen8_emit_pipe_control(batch,
1390 PIPE_CONTROL_FLUSH_L3 |
1391 PIPE_CONTROL_GLOBAL_GTT_IVB |
1392 PIPE_CONTROL_CS_STALL |
1393 PIPE_CONTROL_QW_WRITE,
1394 i915_ggtt_offset(engine->scratch)
1395 + 2 * CACHELINE_BYTES);
1398 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1399 if (HAS_POOLED_EU(engine->i915)) {
1401 * EU pool configuration is setup along with golden context
1402 * during context initialization. This value depends on
1403 * device type (2x6 or 3x6) and needs to be updated based
1404 * on which subslice is disabled especially for 2x6
1405 * devices, however it is safe to load default
1406 * configuration of 3x6 device instead of masking off
1407 * corresponding bits because HW ignores bits of a disabled
1408 * subslice and drops down to appropriate config. Please
1409 * see render_state_setup() in i915_gem_render_state.c for
1410 * possible configurations, to avoid duplication they are
1411 * not shown here again.
1413 *batch++ = GEN9_MEDIA_POOL_STATE;
1414 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1415 *batch++ = 0x00777000;
1421 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1423 /* Pad to end of cacheline */
1424 while ((unsigned long)batch % CACHELINE_BYTES)
1431 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1436 * WaPipeControlBefore3DStateSamplePattern: cnl
1438 * Ensure the engine is idle prior to programming a
1439 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1441 batch = gen8_emit_pipe_control(batch,
1442 PIPE_CONTROL_CS_STALL,
1445 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1446 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1447 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1448 * confusing. Since gen8_emit_pipe_control() already advances the
1449 * batch by 6 dwords, we advance the other 10 here, completing a
1450 * cacheline. It's not clear if the workaround requires this padding
1451 * before other commands, or if it's just the regular padding we would
1452 * already have for the workaround bb, so leave it here for now.
1454 for (i = 0; i < 10; i++)
1457 /* Pad to end of cacheline */
1458 while ((unsigned long)batch % CACHELINE_BYTES)
1464 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1466 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1468 struct drm_i915_gem_object *obj;
1469 struct i915_vma *vma;
1472 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1474 return PTR_ERR(obj);
1476 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1482 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1486 engine->wa_ctx.vma = vma;
1490 i915_gem_object_put(obj);
1494 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1496 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1499 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1501 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1503 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1504 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1506 wa_bb_func_t wa_bb_fn[2];
1508 void *batch, *batch_ptr;
1512 if (GEM_WARN_ON(engine->id != RCS))
1515 switch (INTEL_GEN(engine->i915)) {
1517 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1521 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1525 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1529 MISSING_CASE(INTEL_GEN(engine->i915));
1533 ret = lrc_setup_wa_ctx(engine);
1535 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1539 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1540 batch = batch_ptr = kmap_atomic(page);
1543 * Emit the two workaround batch buffers, recording the offset from the
1544 * start of the workaround batch buffer object for each and their
1547 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1548 wa_bb[i]->offset = batch_ptr - batch;
1549 if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1550 CACHELINE_BYTES))) {
1555 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1556 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1559 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1561 kunmap_atomic(batch);
1563 lrc_destroy_wa_ctx(engine);
1568 static u8 gtiir[] = {
1576 static void enable_execlists(struct intel_engine_cs *engine)
1578 struct drm_i915_private *dev_priv = engine->i915;
1580 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1583 * Make sure we're not enabling the new 12-deep CSB
1584 * FIFO as that requires a slightly updated handling
1585 * in the ctx switch irq. Since we're currently only
1586 * using only 2 elements of the enhanced execlists the
1587 * deeper FIFO it's not needed and it's not worth adding
1588 * more statements to the irq handler to support it.
1590 if (INTEL_GEN(dev_priv) >= 11)
1591 I915_WRITE(RING_MODE_GEN7(engine),
1592 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1594 I915_WRITE(RING_MODE_GEN7(engine),
1595 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1597 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1598 engine->status_page.ggtt_offset);
1599 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1601 /* Following the reset, we need to reload the CSB read/write pointers */
1602 engine->execlists.csb_head = -1;
1605 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1607 struct intel_engine_execlists * const execlists = &engine->execlists;
1610 ret = intel_mocs_init_engine(engine);
1614 intel_engine_reset_breadcrumbs(engine);
1615 intel_engine_init_hangcheck(engine);
1617 enable_execlists(engine);
1619 /* After a GPU reset, we may have requests to replay */
1620 if (execlists->first)
1621 tasklet_schedule(&execlists->tasklet);
1626 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1628 struct drm_i915_private *dev_priv = engine->i915;
1631 ret = gen8_init_common_ring(engine);
1635 /* We need to disable the AsyncFlip performance optimisations in order
1636 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1637 * programmed to '1' on all products.
1639 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1641 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1643 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1645 return init_workarounds_ring(engine);
1648 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1652 ret = gen8_init_common_ring(engine);
1656 return init_workarounds_ring(engine);
1659 static void reset_irq(struct intel_engine_cs *engine)
1661 struct drm_i915_private *dev_priv = engine->i915;
1664 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1667 * Clear any pending interrupt state.
1669 * We do it twice out of paranoia that some of the IIR are double
1670 * buffered, and if we only reset it once there may still be
1671 * an interrupt pending.
1673 for (i = 0; i < 2; i++) {
1674 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1675 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1676 POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
1678 GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
1679 (GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift));
1681 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1684 static void reset_common_ring(struct intel_engine_cs *engine,
1685 struct i915_request *request)
1687 struct intel_engine_execlists * const execlists = &engine->execlists;
1688 struct intel_context *ce;
1689 unsigned long flags;
1691 GEM_TRACE("%s seqno=%x\n",
1692 engine->name, request ? request->global_seqno : 0);
1694 /* See execlists_cancel_requests() for the irq/spinlock split. */
1695 local_irq_save(flags);
1700 * Catch up with any missed context-switch interrupts.
1702 * Ideally we would just read the remaining CSB entries now that we
1703 * know the gpu is idle. However, the CSB registers are sometimes^W
1704 * often trashed across a GPU reset! Instead we have to rely on
1705 * guessing the missed context-switch events by looking at what
1706 * requests were completed.
1708 execlists_cancel_port_requests(execlists);
1710 /* Push back any incomplete requests for replay after the reset. */
1711 spin_lock(&engine->timeline->lock);
1712 __unwind_incomplete_requests(engine);
1713 spin_unlock(&engine->timeline->lock);
1715 /* Mark all CS interrupts as complete */
1716 execlists->active = 0;
1718 local_irq_restore(flags);
1721 * If the request was innocent, we leave the request in the ELSP
1722 * and will try to replay it on restarting. The context image may
1723 * have been corrupted by the reset, in which case we may have
1724 * to service a new GPU hang, but more likely we can continue on
1727 * If the request was guilty, we presume the context is corrupt
1728 * and have to at least restore the RING register in the context
1729 * image back to the expected values to skip over the guilty request.
1731 if (!request || request->fence.error != -EIO)
1735 * We want a simple context + ring to execute the breadcrumb update.
1736 * We cannot rely on the context being intact across the GPU hang,
1737 * so clear it and rebuild just what we need for the breadcrumb.
1738 * All pending requests for this context will be zapped, and any
1739 * future request will be after userspace has had the opportunity
1740 * to recreate its own state.
1742 ce = &request->ctx->engine[engine->id];
1743 execlists_init_reg_state(ce->lrc_reg_state,
1744 request->ctx, engine, ce->ring);
1746 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1747 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1748 i915_ggtt_offset(ce->ring->vma);
1749 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1751 request->ring->head = request->postfix;
1752 intel_ring_update_space(request->ring);
1754 /* Reset WaIdleLiteRestore:bdw,skl as well */
1755 unwind_wa_tail(request);
1758 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
1760 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
1761 struct intel_engine_cs *engine = rq->engine;
1762 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1766 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
1770 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1771 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1772 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1774 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1775 *cs++ = upper_32_bits(pd_daddr);
1776 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1777 *cs++ = lower_32_bits(pd_daddr);
1781 intel_ring_advance(rq, cs);
1786 static int gen8_emit_bb_start(struct i915_request *rq,
1787 u64 offset, u32 len,
1788 const unsigned int flags)
1793 /* Don't rely in hw updating PDPs, specially in lite-restore.
1794 * Ideally, we should set Force PD Restore in ctx descriptor,
1795 * but we can't. Force Restore would be a second option, but
1796 * it is unsafe in case of lite-restore (because the ctx is
1797 * not idle). PML4 is allocated during ppgtt init so this is
1798 * not needed in 48-bit.*/
1799 if (rq->ctx->ppgtt &&
1800 (intel_engine_flag(rq->engine) & rq->ctx->ppgtt->pd_dirty_rings) &&
1801 !i915_vm_is_48bit(&rq->ctx->ppgtt->base) &&
1802 !intel_vgpu_active(rq->i915)) {
1803 ret = intel_logical_ring_emit_pdps(rq);
1807 rq->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
1810 cs = intel_ring_begin(rq, 4);
1815 * WaDisableCtxRestoreArbitration:bdw,chv
1817 * We don't need to perform MI_ARB_ENABLE as often as we do (in
1818 * particular all the gen that do not need the w/a at all!), if we
1819 * took care to make sure that on every switch into this context
1820 * (both ordinary and for preemption) that arbitrartion was enabled
1821 * we would be fine. However, there doesn't seem to be a downside to
1822 * being paranoid and making sure it is set before each batch and
1823 * every context-switch.
1825 * Note that if we fail to enable arbitration before the request
1826 * is complete, then we do not see the context-switch interrupt and
1827 * the engine hangs (with RING_HEAD == RING_TAIL).
1829 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1831 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1833 /* FIXME(BDW): Address space and security selectors. */
1834 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1835 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1836 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1837 *cs++ = lower_32_bits(offset);
1838 *cs++ = upper_32_bits(offset);
1839 intel_ring_advance(rq, cs);
1844 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1846 struct drm_i915_private *dev_priv = engine->i915;
1847 I915_WRITE_IMR(engine,
1848 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1849 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1852 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1854 struct drm_i915_private *dev_priv = engine->i915;
1855 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1858 static int gen8_emit_flush(struct i915_request *request, u32 mode)
1862 cs = intel_ring_begin(request, 4);
1866 cmd = MI_FLUSH_DW + 1;
1868 /* We always require a command barrier so that subsequent
1869 * commands, such as breadcrumb interrupts, are strictly ordered
1870 * wrt the contents of the write cache being flushed to memory
1871 * (and thus being coherent from the CPU).
1873 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1875 if (mode & EMIT_INVALIDATE) {
1876 cmd |= MI_INVALIDATE_TLB;
1877 if (request->engine->id == VCS)
1878 cmd |= MI_INVALIDATE_BSD;
1882 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1883 *cs++ = 0; /* upper addr */
1884 *cs++ = 0; /* value */
1885 intel_ring_advance(request, cs);
1890 static int gen8_emit_flush_render(struct i915_request *request,
1893 struct intel_engine_cs *engine = request->engine;
1895 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1896 bool vf_flush_wa = false, dc_flush_wa = false;
1900 flags |= PIPE_CONTROL_CS_STALL;
1902 if (mode & EMIT_FLUSH) {
1903 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1904 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1905 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1906 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1909 if (mode & EMIT_INVALIDATE) {
1910 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1911 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1912 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1913 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1914 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1915 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1916 flags |= PIPE_CONTROL_QW_WRITE;
1917 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1920 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1923 if (IS_GEN9(request->i915))
1926 /* WaForGAMHang:kbl */
1927 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1939 cs = intel_ring_begin(request, len);
1944 cs = gen8_emit_pipe_control(cs, 0, 0);
1947 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1950 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1953 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1955 intel_ring_advance(request, cs);
1961 * Reserve space for 2 NOOPs at the end of each request to be
1962 * used as a workaround for not being allowed to do lite
1963 * restore with HEAD==TAIL (WaIdleLiteRestore).
1965 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
1967 /* Ensure there's always at least one preemption point per-request. */
1968 *cs++ = MI_ARB_CHECK;
1970 request->wa_tail = intel_ring_offset(request, cs);
1973 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
1975 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1976 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1978 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
1979 intel_hws_seqno_address(request->engine));
1980 *cs++ = MI_USER_INTERRUPT;
1982 request->tail = intel_ring_offset(request, cs);
1983 assert_ring_tail_valid(request->ring, request->tail);
1985 gen8_emit_wa_tail(request, cs);
1987 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1989 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
1991 /* We're using qword write, seqno should be aligned to 8 bytes. */
1992 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1994 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
1995 intel_hws_seqno_address(request->engine));
1996 *cs++ = MI_USER_INTERRUPT;
1998 request->tail = intel_ring_offset(request, cs);
1999 assert_ring_tail_valid(request->ring, request->tail);
2001 gen8_emit_wa_tail(request, cs);
2003 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2005 static int gen8_init_rcs_context(struct i915_request *rq)
2009 ret = intel_ring_workarounds_emit(rq);
2013 ret = intel_rcs_context_init_mocs(rq);
2015 * Failing to program the MOCS is non-fatal.The system will not
2016 * run at peak performance. So generate an error and carry on.
2019 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2021 return i915_gem_render_state_emit(rq);
2025 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2026 * @engine: Engine Command Streamer.
2028 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2030 struct drm_i915_private *dev_priv;
2033 * Tasklet cannot be active at this point due intel_mark_active/idle
2034 * so this is just for documentation.
2036 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2037 &engine->execlists.tasklet.state)))
2038 tasklet_kill(&engine->execlists.tasklet);
2040 dev_priv = engine->i915;
2042 if (engine->buffer) {
2043 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2046 if (engine->cleanup)
2047 engine->cleanup(engine);
2049 intel_engine_cleanup_common(engine);
2051 lrc_destroy_wa_ctx(engine);
2053 engine->i915 = NULL;
2054 dev_priv->engine[engine->id] = NULL;
2058 static void execlists_set_default_submission(struct intel_engine_cs *engine)
2060 engine->submit_request = execlists_submit_request;
2061 engine->cancel_requests = execlists_cancel_requests;
2062 engine->schedule = execlists_schedule;
2063 engine->execlists.tasklet.func = execlists_submission_tasklet;
2065 engine->park = NULL;
2066 engine->unpark = NULL;
2068 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2070 engine->i915->caps.scheduler =
2071 I915_SCHEDULER_CAP_ENABLED |
2072 I915_SCHEDULER_CAP_PRIORITY;
2073 if (engine->i915->preempt_context)
2074 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2078 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2080 /* Default vfuncs which can be overriden by each engine. */
2081 engine->init_hw = gen8_init_common_ring;
2082 engine->reset_hw = reset_common_ring;
2084 engine->context_pin = execlists_context_pin;
2085 engine->context_unpin = execlists_context_unpin;
2087 engine->request_alloc = execlists_request_alloc;
2089 engine->emit_flush = gen8_emit_flush;
2090 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2091 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2093 engine->set_default_submission = execlists_set_default_submission;
2095 if (INTEL_GEN(engine->i915) < 11) {
2096 engine->irq_enable = gen8_logical_ring_enable_irq;
2097 engine->irq_disable = gen8_logical_ring_disable_irq;
2100 * TODO: On Gen11 interrupt masks need to be clear
2101 * to allow C6 entry. Keep interrupts enabled at
2102 * and take the hit of generating extra interrupts
2103 * until a more refined solution exists.
2106 engine->emit_bb_start = gen8_emit_bb_start;
2110 logical_ring_default_irqs(struct intel_engine_cs *engine)
2112 unsigned shift = engine->irq_shift;
2113 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2114 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2118 logical_ring_setup(struct intel_engine_cs *engine)
2120 struct drm_i915_private *dev_priv = engine->i915;
2121 enum forcewake_domains fw_domains;
2123 intel_engine_setup_common(engine);
2125 /* Intentionally left blank. */
2126 engine->buffer = NULL;
2128 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
2132 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2133 RING_CONTEXT_STATUS_PTR(engine),
2134 FW_REG_READ | FW_REG_WRITE);
2136 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2137 RING_CONTEXT_STATUS_BUF_BASE(engine),
2140 engine->execlists.fw_domains = fw_domains;
2142 tasklet_init(&engine->execlists.tasklet,
2143 execlists_submission_tasklet, (unsigned long)engine);
2145 logical_ring_default_vfuncs(engine);
2146 logical_ring_default_irqs(engine);
2149 static int logical_ring_init(struct intel_engine_cs *engine)
2153 ret = intel_engine_init_common(engine);
2157 if (HAS_LOGICAL_RING_ELSQ(engine->i915)) {
2158 engine->execlists.submit_reg = engine->i915->regs +
2159 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2160 engine->execlists.ctrl_reg = engine->i915->regs +
2161 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2163 engine->execlists.submit_reg = engine->i915->regs +
2164 i915_mmio_reg_offset(RING_ELSP(engine));
2167 engine->execlists.preempt_complete_status = ~0u;
2168 if (engine->i915->preempt_context)
2169 engine->execlists.preempt_complete_status =
2170 upper_32_bits(engine->i915->preempt_context->engine[engine->id].lrc_desc);
2175 intel_logical_ring_cleanup(engine);
2179 int logical_render_ring_init(struct intel_engine_cs *engine)
2181 struct drm_i915_private *dev_priv = engine->i915;
2184 logical_ring_setup(engine);
2186 if (HAS_L3_DPF(dev_priv))
2187 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2189 /* Override some for render ring. */
2190 if (INTEL_GEN(dev_priv) >= 9)
2191 engine->init_hw = gen9_init_render_ring;
2193 engine->init_hw = gen8_init_render_ring;
2194 engine->init_context = gen8_init_rcs_context;
2195 engine->emit_flush = gen8_emit_flush_render;
2196 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2197 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2199 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2203 ret = intel_init_workaround_bb(engine);
2206 * We continue even if we fail to initialize WA batch
2207 * because we only expect rare glitches but nothing
2208 * critical to prevent us from using GPU
2210 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2214 return logical_ring_init(engine);
2217 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2219 logical_ring_setup(engine);
2221 return logical_ring_init(engine);
2225 make_rpcs(struct drm_i915_private *dev_priv)
2230 * No explicit RPCS request is needed to ensure full
2231 * slice/subslice/EU enablement prior to Gen9.
2233 if (INTEL_GEN(dev_priv) < 9)
2237 * Starting in Gen9, render power gating can leave
2238 * slice/subslice/EU in a partially enabled state. We
2239 * must make an explicit request through RPCS for full
2242 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2243 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2244 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2245 GEN8_RPCS_S_CNT_SHIFT;
2246 rpcs |= GEN8_RPCS_ENABLE;
2249 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2250 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2251 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
2252 GEN8_RPCS_SS_CNT_SHIFT;
2253 rpcs |= GEN8_RPCS_ENABLE;
2256 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2257 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2258 GEN8_RPCS_EU_MIN_SHIFT;
2259 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2260 GEN8_RPCS_EU_MAX_SHIFT;
2261 rpcs |= GEN8_RPCS_ENABLE;
2267 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2269 u32 indirect_ctx_offset;
2271 switch (INTEL_GEN(engine->i915)) {
2273 MISSING_CASE(INTEL_GEN(engine->i915));
2276 indirect_ctx_offset =
2277 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2280 indirect_ctx_offset =
2281 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2284 indirect_ctx_offset =
2285 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2288 indirect_ctx_offset =
2289 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2293 return indirect_ctx_offset;
2296 static void execlists_init_reg_state(u32 *regs,
2297 struct i915_gem_context *ctx,
2298 struct intel_engine_cs *engine,
2299 struct intel_ring *ring)
2301 struct drm_i915_private *dev_priv = engine->i915;
2302 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2303 u32 base = engine->mmio_base;
2304 bool rcs = engine->id == RCS;
2306 /* A context is actually a big batch buffer with several
2307 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2308 * values we are setting here are only for the first context restore:
2309 * on a subsequent save, the GPU will recreate this batchbuffer with new
2310 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2311 * we are not initializing here).
2313 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2314 MI_LRI_FORCE_POSTED;
2316 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2317 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2318 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) |
2319 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2320 (HAS_RESOURCE_STREAMER(dev_priv) ?
2321 CTX_CTRL_RS_CTX_ENABLE : 0)));
2322 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2323 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2324 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2325 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2326 RING_CTL_SIZE(ring->size) | RING_VALID);
2327 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2328 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2329 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2330 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2331 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2332 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2334 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2336 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2337 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2338 RING_INDIRECT_CTX_OFFSET(base), 0);
2339 if (wa_ctx->indirect_ctx.size) {
2340 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2342 regs[CTX_RCS_INDIRECT_CTX + 1] =
2343 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2344 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2346 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2347 intel_lr_indirect_ctx_offset(engine) << 6;
2350 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2351 if (wa_ctx->per_ctx.size) {
2352 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2354 regs[CTX_BB_PER_CTX_PTR + 1] =
2355 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2359 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2361 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2362 /* PDP values well be assigned later if needed */
2363 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2364 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2365 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2366 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2367 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2368 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2369 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2370 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2372 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
2373 /* 64b PPGTT (48bit canonical)
2374 * PDP0_DESCRIPTOR contains the base address to PML4 and
2375 * other PDP Descriptors are ignored.
2377 ASSIGN_CTX_PML4(ppgtt, regs);
2381 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2382 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2383 make_rpcs(dev_priv));
2385 i915_oa_init_reg_state(engine, ctx, regs);
2390 populate_lr_context(struct i915_gem_context *ctx,
2391 struct drm_i915_gem_object *ctx_obj,
2392 struct intel_engine_cs *engine,
2393 struct intel_ring *ring)
2399 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2401 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2405 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2406 if (IS_ERR(vaddr)) {
2407 ret = PTR_ERR(vaddr);
2408 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2411 ctx_obj->mm.dirty = true;
2413 if (engine->default_state) {
2415 * We only want to copy over the template context state;
2416 * skipping over the headers reserved for GuC communication,
2417 * leaving those as zero.
2419 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2422 defaults = i915_gem_object_pin_map(engine->default_state,
2424 if (IS_ERR(defaults))
2425 return PTR_ERR(defaults);
2427 memcpy(vaddr + start, defaults + start, engine->context_size);
2428 i915_gem_object_unpin_map(engine->default_state);
2431 /* The second page of the context object contains some fields which must
2432 * be set up prior to the first execution. */
2433 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2434 execlists_init_reg_state(regs, ctx, engine, ring);
2435 if (!engine->default_state)
2436 regs[CTX_CONTEXT_CONTROL + 1] |=
2437 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2438 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2439 regs[CTX_CONTEXT_CONTROL + 1] |=
2440 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2441 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2443 i915_gem_object_unpin_map(ctx_obj);
2448 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2449 struct intel_engine_cs *engine)
2451 struct drm_i915_gem_object *ctx_obj;
2452 struct intel_context *ce = &ctx->engine[engine->id];
2453 struct i915_vma *vma;
2454 uint32_t context_size;
2455 struct intel_ring *ring;
2461 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2464 * Before the actual start of the context image, we insert a few pages
2465 * for our own use and for sharing with the GuC.
2467 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2469 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2470 if (IS_ERR(ctx_obj)) {
2471 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2472 return PTR_ERR(ctx_obj);
2475 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2478 goto error_deref_obj;
2481 ring = intel_engine_create_ring(engine, ctx->ring_size);
2483 ret = PTR_ERR(ring);
2484 goto error_deref_obj;
2487 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2489 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2490 goto error_ring_free;
2499 intel_ring_free(ring);
2501 i915_gem_object_put(ctx_obj);
2505 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2507 struct intel_engine_cs *engine;
2508 struct i915_gem_context *ctx;
2509 enum intel_engine_id id;
2511 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2512 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2513 * that stored in context. As we only write new commands from
2514 * ce->ring->tail onwards, everything before that is junk. If the GPU
2515 * starts reading from its RING_HEAD from the context, it may try to
2516 * execute that junk and die.
2518 * So to avoid that we reset the context images upon resume. For
2519 * simplicity, we just zero everything out.
2521 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2522 for_each_engine(engine, dev_priv, id) {
2523 struct intel_context *ce = &ctx->engine[engine->id];
2529 reg = i915_gem_object_pin_map(ce->state->obj,
2531 if (WARN_ON(IS_ERR(reg)))
2534 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2535 reg[CTX_RING_HEAD+1] = 0;
2536 reg[CTX_RING_TAIL+1] = 0;
2538 ce->state->obj->mm.dirty = true;
2539 i915_gem_object_unpin_map(ce->state->obj);
2541 intel_ring_reset(ce->ring, 0);