2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
161 GEN8_CTX_STATUS_PREEMPTED | \
162 GEN8_CTX_STATUS_ELEMENT_SWITCH)
164 #define CTX_LRI_HEADER_0 0x01
165 #define CTX_CONTEXT_CONTROL 0x02
166 #define CTX_RING_HEAD 0x04
167 #define CTX_RING_TAIL 0x06
168 #define CTX_RING_BUFFER_START 0x08
169 #define CTX_RING_BUFFER_CONTROL 0x0a
170 #define CTX_BB_HEAD_U 0x0c
171 #define CTX_BB_HEAD_L 0x0e
172 #define CTX_BB_STATE 0x10
173 #define CTX_SECOND_BB_HEAD_U 0x12
174 #define CTX_SECOND_BB_HEAD_L 0x14
175 #define CTX_SECOND_BB_STATE 0x16
176 #define CTX_BB_PER_CTX_PTR 0x18
177 #define CTX_RCS_INDIRECT_CTX 0x1a
178 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
179 #define CTX_LRI_HEADER_1 0x21
180 #define CTX_CTX_TIMESTAMP 0x22
181 #define CTX_PDP3_UDW 0x24
182 #define CTX_PDP3_LDW 0x26
183 #define CTX_PDP2_UDW 0x28
184 #define CTX_PDP2_LDW 0x2a
185 #define CTX_PDP1_UDW 0x2c
186 #define CTX_PDP1_LDW 0x2e
187 #define CTX_PDP0_UDW 0x30
188 #define CTX_PDP0_LDW 0x32
189 #define CTX_LRI_HEADER_2 0x41
190 #define CTX_R_PWR_CLK_STATE 0x42
191 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
193 #define GEN8_CTX_VALID (1<<0)
194 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
195 #define GEN8_CTX_FORCE_RESTORE (1<<2)
196 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
197 #define GEN8_CTX_PRIVILEGE (1<<8)
199 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
200 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
201 (reg_state)[(pos)+1] = (val); \
204 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
205 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
206 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
207 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
210 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
211 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
212 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
217 FAULT_AND_HALT, /* Debug only */
219 FAULT_AND_CONTINUE /* Unsupported */
221 #define GEN8_CTX_ID_SHIFT 32
222 #define GEN8_CTX_ID_WIDTH 21
223 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
224 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
226 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
227 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
229 #define WA_TAIL_DWORDS 2
231 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
232 struct intel_engine_cs *engine);
233 static void execlists_init_reg_state(u32 *reg_state,
234 struct i915_gem_context *ctx,
235 struct intel_engine_cs *engine,
236 struct intel_ring *ring);
239 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
240 * @dev_priv: i915 device private
241 * @enable_execlists: value of i915.enable_execlists module parameter.
243 * Only certain platforms support Execlists (the prerequisites being
244 * support for Logical Ring Contexts and Aliasing PPGTT or better).
246 * Return: 1 if Execlists is supported and has to be enabled.
248 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
250 /* On platforms with execlist available, vGPU will only
251 * support execlist mode, no ring buffer mode.
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
256 if (INTEL_GEN(dev_priv) >= 9)
259 if (enable_execlists == 0)
262 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
263 USES_PPGTT(dev_priv) &&
264 i915.use_mmio_flip >= 0)
271 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
273 struct drm_i915_private *dev_priv = engine->i915;
275 engine->disable_lite_restore_wa =
276 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
277 (engine->id == VCS || engine->id == VCS2);
279 engine->ctx_desc_template = GEN8_CTX_VALID;
280 if (IS_GEN8(dev_priv))
281 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
282 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
284 /* TODO: WaDisableLiteRestore when we start using semaphore
285 * signalling between Command Streamers */
286 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
290 if (engine->disable_lite_restore_wa)
291 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
295 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
296 * descriptor for a pinned context
297 * @ctx: Context to work on
298 * @engine: Engine the descriptor will be used with
300 * The context descriptor encodes various attributes of a context,
301 * including its GTT address and some flags. Because it's fairly
302 * expensive to calculate, we'll just do it once and cache the result,
303 * which remains valid until the context is unpinned.
305 * This is what a descriptor looks like, from LSB to MSB::
307 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
308 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
309 * bits 32-52: ctx ID, a globally unique tag
310 * bits 53-54: mbz, reserved for use by hardware
311 * bits 55-63: group ID, currently unused and set to 0
314 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
315 struct intel_engine_cs *engine)
317 struct intel_context *ce = &ctx->engine[engine->id];
320 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
322 desc = ctx->desc_template; /* bits 3-4 */
323 desc |= engine->ctx_desc_template; /* bits 0-11 */
324 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
326 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
331 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
332 struct intel_engine_cs *engine)
334 return ctx->engine[engine->id].lrc_desc;
338 execlists_context_status_change(struct drm_i915_gem_request *rq,
339 unsigned long status)
342 * Only used when GVT-g is enabled now. When GVT-g is disabled,
343 * The compiler should eliminate this function as dead-code.
345 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
348 atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
352 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
354 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
355 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
356 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
357 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
360 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
362 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
363 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
364 u32 *reg_state = ce->lrc_reg_state;
366 reg_state[CTX_RING_TAIL+1] = rq->tail;
368 /* True 32b PPGTT with dynamic page allocation: update PDP
369 * registers and point the unallocated PDPs to scratch page.
370 * PML4 is allocated during ppgtt init, so this is not needed
373 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
374 execlists_update_context_pdps(ppgtt, reg_state);
379 static void execlists_submit_ports(struct intel_engine_cs *engine)
381 struct drm_i915_private *dev_priv = engine->i915;
382 struct execlist_port *port = engine->execlist_port;
384 dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
388 execlists_context_status_change(port[0].request,
389 INTEL_CONTEXT_SCHEDULE_IN);
390 desc[0] = execlists_update_context(port[0].request);
391 engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */
393 if (port[1].request) {
394 GEM_BUG_ON(port[1].count);
395 execlists_context_status_change(port[1].request,
396 INTEL_CONTEXT_SCHEDULE_IN);
397 desc[1] = execlists_update_context(port[1].request);
402 GEM_BUG_ON(desc[0] == desc[1]);
404 /* You must always write both descriptors in the order below. */
405 writel(upper_32_bits(desc[1]), elsp);
406 writel(lower_32_bits(desc[1]), elsp);
408 writel(upper_32_bits(desc[0]), elsp);
409 /* The context is automatically loaded after the following */
410 writel(lower_32_bits(desc[0]), elsp);
413 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
415 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
416 ctx->execlists_force_single_submission);
419 static bool can_merge_ctx(const struct i915_gem_context *prev,
420 const struct i915_gem_context *next)
425 if (ctx_single_port_submission(prev))
431 static void execlists_dequeue(struct intel_engine_cs *engine)
433 struct drm_i915_gem_request *last;
434 struct execlist_port *port = engine->execlist_port;
439 last = port->request;
441 /* WaIdleLiteRestore:bdw,skl
442 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
443 * as we resubmit the request. See gen8_emit_breadcrumb()
444 * for where we prepare the padding after the end of the
447 last->tail = last->wa_tail;
449 GEM_BUG_ON(port[1].request);
451 /* Hardware submission is through 2 ports. Conceptually each port
452 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
453 * static for a context, and unique to each, so we only execute
454 * requests belonging to a single context from each ring. RING_HEAD
455 * is maintained by the CS in the context image, it marks the place
456 * where it got up to last time, and through RING_TAIL we tell the CS
457 * where we want to execute up to this time.
459 * In this list the requests are in order of execution. Consecutive
460 * requests from the same context are adjacent in the ringbuffer. We
461 * can combine these requests into a single RING_TAIL update:
463 * RING_HEAD...req1...req2
465 * since to execute req2 the CS must first execute req1.
467 * Our goal then is to point each port to the end of a consecutive
468 * sequence of requests as being the most optimal (fewest wake ups
469 * and context switches) submission.
472 spin_lock_irqsave(&engine->timeline->lock, flags);
473 rb = engine->execlist_first;
475 struct drm_i915_gem_request *cursor =
476 rb_entry(rb, typeof(*cursor), priotree.node);
478 /* Can we combine this request with the current port? It has to
479 * be the same context/ringbuffer and not have any exceptions
480 * (e.g. GVT saying never to combine contexts).
482 * If we can combine the requests, we can execute both by
483 * updating the RING_TAIL to point to the end of the second
484 * request, and so we never need to tell the hardware about
487 if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
488 /* If we are on the second port and cannot combine
489 * this request with the last, then we are done.
491 if (port != engine->execlist_port)
494 /* If GVT overrides us we only ever submit port[0],
495 * leaving port[1] empty. Note that we also have
496 * to be careful that we don't queue the same
497 * context (even though a different request) to
500 if (ctx_single_port_submission(last->ctx) ||
501 ctx_single_port_submission(cursor->ctx))
504 GEM_BUG_ON(last->ctx == cursor->ctx);
506 i915_gem_request_assign(&port->request, last);
511 rb_erase(&cursor->priotree.node, &engine->execlist_queue);
512 RB_CLEAR_NODE(&cursor->priotree.node);
513 cursor->priotree.priority = INT_MAX;
515 __i915_gem_request_submit(cursor);
520 i915_gem_request_assign(&port->request, last);
521 engine->execlist_first = rb;
523 spin_unlock_irqrestore(&engine->timeline->lock, flags);
526 execlists_submit_ports(engine);
529 static bool execlists_elsp_idle(struct intel_engine_cs *engine)
531 return !engine->execlist_port[0].request;
535 * intel_execlists_idle() - Determine if all engine submission ports are idle
536 * @dev_priv: i915 device private
538 * Return true if there are no requests pending on any of the submission ports
541 bool intel_execlists_idle(struct drm_i915_private *dev_priv)
543 struct intel_engine_cs *engine;
544 enum intel_engine_id id;
546 if (!i915.enable_execlists)
549 for_each_engine(engine, dev_priv, id)
550 if (!execlists_elsp_idle(engine))
556 static bool execlists_elsp_ready(struct intel_engine_cs *engine)
560 port = 1; /* wait for a free slot */
561 if (engine->disable_lite_restore_wa || engine->preempt_wa)
562 port = 0; /* wait for GPU to be idle before continuing */
564 return !engine->execlist_port[port].request;
568 * Check the unread Context Status Buffers and manage the submission of new
569 * contexts to the ELSP accordingly.
571 static void intel_lrc_irq_handler(unsigned long data)
573 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
574 struct execlist_port *port = engine->execlist_port;
575 struct drm_i915_private *dev_priv = engine->i915;
577 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
579 if (!execlists_elsp_idle(engine)) {
580 u32 __iomem *csb_mmio =
581 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
583 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
584 unsigned int csb, head, tail;
586 csb = readl(csb_mmio);
587 head = GEN8_CSB_READ_PTR(csb);
588 tail = GEN8_CSB_WRITE_PTR(csb);
590 tail += GEN8_CSB_ENTRIES;
591 while (head < tail) {
592 unsigned int idx = ++head % GEN8_CSB_ENTRIES;
593 unsigned int status = readl(buf + 2 * idx);
595 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
598 GEM_BUG_ON(port[0].count == 0);
599 if (--port[0].count == 0) {
600 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
601 execlists_context_status_change(port[0].request,
602 INTEL_CONTEXT_SCHEDULE_OUT);
604 i915_gem_request_put(port[0].request);
606 memset(&port[1], 0, sizeof(port[1]));
608 engine->preempt_wa = false;
611 GEM_BUG_ON(port[0].count == 0 &&
612 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
615 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
616 GEN8_CSB_WRITE_PTR(csb) << 8),
620 if (execlists_elsp_ready(engine))
621 execlists_dequeue(engine);
623 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
626 static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
628 struct rb_node **p, *rb;
631 /* most positive priority is scheduled first, equal priorities fifo */
635 struct i915_priotree *pos;
638 pos = rb_entry(rb, typeof(*pos), node);
639 if (pt->priority > pos->priority) {
646 rb_link_node(&pt->node, rb, p);
647 rb_insert_color(&pt->node, root);
652 static void execlists_submit_request(struct drm_i915_gem_request *request)
654 struct intel_engine_cs *engine = request->engine;
657 /* Will be called from irq-context when using foreign fences. */
658 spin_lock_irqsave(&engine->timeline->lock, flags);
660 if (insert_request(&request->priotree, &engine->execlist_queue))
661 engine->execlist_first = &request->priotree.node;
662 if (execlists_elsp_idle(engine))
663 tasklet_hi_schedule(&engine->irq_tasklet);
665 spin_unlock_irqrestore(&engine->timeline->lock, flags);
668 static struct intel_engine_cs *
669 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
671 struct intel_engine_cs *engine;
673 engine = container_of(pt,
674 struct drm_i915_gem_request,
676 if (engine != locked) {
678 spin_unlock_irq(&locked->timeline->lock);
679 spin_lock_irq(&engine->timeline->lock);
685 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
687 struct intel_engine_cs *engine = NULL;
688 struct i915_dependency *dep, *p;
689 struct i915_dependency stack;
692 if (prio <= READ_ONCE(request->priotree.priority))
695 /* Need BKL in order to use the temporary link inside i915_dependency */
696 lockdep_assert_held(&request->i915->drm.struct_mutex);
698 stack.signaler = &request->priotree;
699 list_add(&stack.dfs_link, &dfs);
701 /* Recursively bump all dependent priorities to match the new request.
703 * A naive approach would be to use recursion:
704 * static void update_priorities(struct i915_priotree *pt, prio) {
705 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
706 * update_priorities(dep->signal, prio)
707 * insert_request(pt);
709 * but that may have unlimited recursion depth and so runs a very
710 * real risk of overunning the kernel stack. Instead, we build
711 * a flat list of all dependencies starting with the current request.
712 * As we walk the list of dependencies, we add all of its dependencies
713 * to the end of the list (this may include an already visited
714 * request) and continue to walk onwards onto the new dependencies. The
715 * end result is a topological list of requests in reverse order, the
716 * last element in the list is the request we must execute first.
718 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
719 struct i915_priotree *pt = dep->signaler;
721 list_for_each_entry(p, &pt->signalers_list, signal_link)
722 if (prio > READ_ONCE(p->signaler->priority))
723 list_move_tail(&p->dfs_link, &dfs);
725 list_safe_reset_next(dep, p, dfs_link);
726 if (!RB_EMPTY_NODE(&pt->node))
729 engine = pt_lock_engine(pt, engine);
731 /* If it is not already in the rbtree, we can update the
732 * priority inplace and skip over it (and its dependencies)
733 * if it is referenced *again* as we descend the dfs.
735 if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
737 list_del_init(&dep->dfs_link);
741 /* Fifo and depth-first replacement ensure our deps execute before us */
742 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
743 struct i915_priotree *pt = dep->signaler;
745 INIT_LIST_HEAD(&dep->dfs_link);
747 engine = pt_lock_engine(pt, engine);
749 if (prio <= pt->priority)
752 GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));
755 rb_erase(&pt->node, &engine->execlist_queue);
756 if (insert_request(pt, &engine->execlist_queue))
757 engine->execlist_first = &pt->node;
761 spin_unlock_irq(&engine->timeline->lock);
763 /* XXX Do we need to preempt to make room for us and our deps? */
766 static int execlists_context_pin(struct intel_engine_cs *engine,
767 struct i915_gem_context *ctx)
769 struct intel_context *ce = &ctx->engine[engine->id];
774 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
780 ret = execlists_context_deferred_alloc(ctx, engine);
785 flags = PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL;
786 if (ctx == ctx->i915->kernel_context)
789 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
793 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
795 ret = PTR_ERR(vaddr);
799 ret = intel_ring_pin(ce->ring);
803 intel_lr_context_descriptor_update(ctx, engine);
805 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
806 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
807 i915_ggtt_offset(ce->ring->vma);
809 ce->state->obj->mm.dirty = true;
811 /* Invalidate GuC TLB. */
812 if (i915.enable_guc_submission) {
813 struct drm_i915_private *dev_priv = ctx->i915;
814 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
817 i915_gem_context_get(ctx);
821 i915_gem_object_unpin_map(ce->state->obj);
823 __i915_vma_unpin(ce->state);
829 static void execlists_context_unpin(struct intel_engine_cs *engine,
830 struct i915_gem_context *ctx)
832 struct intel_context *ce = &ctx->engine[engine->id];
834 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
835 GEM_BUG_ON(ce->pin_count == 0);
840 intel_ring_unpin(ce->ring);
842 i915_gem_object_unpin_map(ce->state->obj);
843 i915_vma_unpin(ce->state);
845 i915_gem_context_put(ctx);
848 static int execlists_request_alloc(struct drm_i915_gem_request *request)
850 struct intel_engine_cs *engine = request->engine;
851 struct intel_context *ce = &request->ctx->engine[engine->id];
854 GEM_BUG_ON(!ce->pin_count);
856 /* Flush enough space to reduce the likelihood of waiting after
857 * we start building the request - in which case we will just
858 * have to repeat work.
860 request->reserved_space += EXECLISTS_REQUEST_SIZE;
862 GEM_BUG_ON(!ce->ring);
863 request->ring = ce->ring;
865 if (i915.enable_guc_submission) {
867 * Check that the GuC has space for the request before
868 * going any further, as the i915_add_request() call
869 * later on mustn't fail ...
871 ret = i915_guc_wq_reserve(request);
876 ret = intel_ring_begin(request, 0);
880 if (!ce->initialised) {
881 ret = engine->init_context(request);
885 ce->initialised = true;
888 /* Note that after this point, we have committed to using
889 * this request as it is being used to both track the
890 * state of engine initialisation and liveness of the
891 * golden renderstate above. Think twice before you try
892 * to cancel/unwind this request now.
895 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
899 if (i915.enable_guc_submission)
900 i915_guc_wq_unreserve(request);
905 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
908 struct intel_ring *ring = req->ring;
909 struct i915_workarounds *w = &req->i915->workarounds;
914 ret = req->engine->emit_flush(req, EMIT_BARRIER);
918 ret = intel_ring_begin(req, w->count * 2 + 2);
922 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
923 for (i = 0; i < w->count; i++) {
924 intel_ring_emit_reg(ring, w->reg[i].addr);
925 intel_ring_emit(ring, w->reg[i].value);
927 intel_ring_emit(ring, MI_NOOP);
929 intel_ring_advance(ring);
931 ret = req->engine->emit_flush(req, EMIT_BARRIER);
938 #define wa_ctx_emit(batch, index, cmd) \
940 int __index = (index)++; \
941 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
944 batch[__index] = (cmd); \
947 #define wa_ctx_emit_reg(batch, index, reg) \
948 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
951 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
952 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
953 * but there is a slight complication as this is applied in WA batch where the
954 * values are only initialized once so we cannot take register value at the
955 * beginning and reuse it further; hence we save its value to memory, upload a
956 * constant value with bit21 set and then we restore it back with the saved value.
957 * To simplify the WA, a constant value is formed by using the default value
958 * of this register. This shouldn't be a problem because we are only modifying
959 * it for a short period and this batch in non-premptible. We can ofcourse
960 * use additional instructions that read the actual value of the register
961 * at that time and set our bit of interest but it makes the WA complicated.
963 * This WA is also required for Gen9 so extracting as a function avoids
966 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
970 struct drm_i915_private *dev_priv = engine->i915;
971 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
974 * WaDisableLSQCROPERFforOCL:kbl
975 * This WA is implemented in skl_init_clock_gating() but since
976 * this batch updates GEN8_L3SQCREG4 with default value we need to
977 * set this bit here to retain the WA during flush.
979 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
980 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
982 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
983 MI_SRM_LRM_GLOBAL_GTT));
984 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
985 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
986 wa_ctx_emit(batch, index, 0);
988 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
989 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
990 wa_ctx_emit(batch, index, l3sqc4_flush);
992 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
993 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
994 PIPE_CONTROL_DC_FLUSH_ENABLE));
995 wa_ctx_emit(batch, index, 0);
996 wa_ctx_emit(batch, index, 0);
997 wa_ctx_emit(batch, index, 0);
998 wa_ctx_emit(batch, index, 0);
1000 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
1001 MI_SRM_LRM_GLOBAL_GTT));
1002 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
1003 wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
1004 wa_ctx_emit(batch, index, 0);
1009 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
1011 uint32_t start_alignment)
1013 return wa_ctx->offset = ALIGN(offset, start_alignment);
1016 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
1018 uint32_t size_alignment)
1020 wa_ctx->size = offset - wa_ctx->offset;
1022 WARN(wa_ctx->size % size_alignment,
1023 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
1024 wa_ctx->size, size_alignment);
1029 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1030 * initialized at the beginning and shared across all contexts but this field
1031 * helps us to have multiple batches at different offsets and select them based
1032 * on a criteria. At the moment this batch always start at the beginning of the page
1033 * and at this point we don't have multiple wa_ctx batch buffers.
1035 * The number of WA applied are not known at the beginning; we use this field
1036 * to return the no of DWORDS written.
1038 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1039 * so it adds NOOPs as padding to make it cacheline aligned.
1040 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1041 * makes a complete batch buffer.
1043 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1044 struct i915_wa_ctx_bb *wa_ctx,
1048 uint32_t scratch_addr;
1049 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1051 /* WaDisableCtxRestoreArbitration:bdw,chv */
1052 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1054 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1055 if (IS_BROADWELL(engine->i915)) {
1056 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1062 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1063 /* Actual scratch location is at 128 bytes offset */
1064 scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1066 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1067 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1068 PIPE_CONTROL_GLOBAL_GTT_IVB |
1069 PIPE_CONTROL_CS_STALL |
1070 PIPE_CONTROL_QW_WRITE));
1071 wa_ctx_emit(batch, index, scratch_addr);
1072 wa_ctx_emit(batch, index, 0);
1073 wa_ctx_emit(batch, index, 0);
1074 wa_ctx_emit(batch, index, 0);
1076 /* Pad to end of cacheline */
1077 while (index % CACHELINE_DWORDS)
1078 wa_ctx_emit(batch, index, MI_NOOP);
1081 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1082 * execution depends on the length specified in terms of cache lines
1083 * in the register CTX_RCS_INDIRECT_CTX
1086 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1090 * This batch is started immediately after indirect_ctx batch. Since we ensure
1091 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1093 * The number of DWORDS written are returned using this field.
1095 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1096 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1098 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1099 struct i915_wa_ctx_bb *wa_ctx,
1103 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1105 /* WaDisableCtxRestoreArbitration:bdw,chv */
1106 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1108 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1110 return wa_ctx_end(wa_ctx, *offset = index, 1);
1113 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1114 struct i915_wa_ctx_bb *wa_ctx,
1119 struct drm_i915_private *dev_priv = engine->i915;
1120 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1122 /* WaDisableCtxRestoreArbitration:bxt */
1123 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1124 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1126 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1127 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1132 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1133 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1134 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
1135 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
1136 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
1137 wa_ctx_emit(batch, index, MI_NOOP);
1139 /* WaClearSlmSpaceAtContextSwitch:kbl */
1140 /* Actual scratch location is at 128 bytes offset */
1141 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1143 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1145 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1146 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1147 PIPE_CONTROL_GLOBAL_GTT_IVB |
1148 PIPE_CONTROL_CS_STALL |
1149 PIPE_CONTROL_QW_WRITE));
1150 wa_ctx_emit(batch, index, scratch_addr);
1151 wa_ctx_emit(batch, index, 0);
1152 wa_ctx_emit(batch, index, 0);
1153 wa_ctx_emit(batch, index, 0);
1156 /* WaMediaPoolStateCmdInWABB:bxt */
1157 if (HAS_POOLED_EU(engine->i915)) {
1159 * EU pool configuration is setup along with golden context
1160 * during context initialization. This value depends on
1161 * device type (2x6 or 3x6) and needs to be updated based
1162 * on which subslice is disabled especially for 2x6
1163 * devices, however it is safe to load default
1164 * configuration of 3x6 device instead of masking off
1165 * corresponding bits because HW ignores bits of a disabled
1166 * subslice and drops down to appropriate config. Please
1167 * see render_state_setup() in i915_gem_render_state.c for
1168 * possible configurations, to avoid duplication they are
1169 * not shown here again.
1171 u32 eu_pool_config = 0x00777000;
1172 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
1173 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
1174 wa_ctx_emit(batch, index, eu_pool_config);
1175 wa_ctx_emit(batch, index, 0);
1176 wa_ctx_emit(batch, index, 0);
1177 wa_ctx_emit(batch, index, 0);
1180 /* Pad to end of cacheline */
1181 while (index % CACHELINE_DWORDS)
1182 wa_ctx_emit(batch, index, MI_NOOP);
1184 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1187 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1188 struct i915_wa_ctx_bb *wa_ctx,
1192 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1194 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
1195 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1196 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1197 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1198 wa_ctx_emit(batch, index,
1199 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1200 wa_ctx_emit(batch, index, MI_NOOP);
1203 /* WaClearTdlStateAckDirtyBits:bxt */
1204 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1205 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1207 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1208 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1210 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1211 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1213 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1214 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1216 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1217 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1218 wa_ctx_emit(batch, index, 0x0);
1219 wa_ctx_emit(batch, index, MI_NOOP);
1222 /* WaDisableCtxRestoreArbitration:bxt */
1223 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1224 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1226 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1228 return wa_ctx_end(wa_ctx, *offset = index, 1);
1231 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1233 struct drm_i915_gem_object *obj;
1234 struct i915_vma *vma;
1237 obj = i915_gem_object_create(engine->i915, PAGE_ALIGN(size));
1239 return PTR_ERR(obj);
1241 vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
1247 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1251 engine->wa_ctx.vma = vma;
1255 i915_gem_object_put(obj);
1259 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1261 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1264 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1266 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1272 WARN_ON(engine->id != RCS);
1274 /* update this when WA for higher Gen are added */
1275 if (INTEL_GEN(engine->i915) > 9) {
1276 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1277 INTEL_GEN(engine->i915));
1281 /* some WA perform writes to scratch page, ensure it is valid */
1282 if (!engine->scratch) {
1283 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1287 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1289 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1293 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1294 batch = kmap_atomic(page);
1297 if (IS_GEN8(engine->i915)) {
1298 ret = gen8_init_indirectctx_bb(engine,
1299 &wa_ctx->indirect_ctx,
1305 ret = gen8_init_perctx_bb(engine,
1311 } else if (IS_GEN9(engine->i915)) {
1312 ret = gen9_init_indirectctx_bb(engine,
1313 &wa_ctx->indirect_ctx,
1319 ret = gen9_init_perctx_bb(engine,
1328 kunmap_atomic(batch);
1330 lrc_destroy_wa_ctx_obj(engine);
1335 static void lrc_init_hws(struct intel_engine_cs *engine)
1337 struct drm_i915_private *dev_priv = engine->i915;
1339 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1340 engine->status_page.ggtt_offset);
1341 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1344 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1346 struct drm_i915_private *dev_priv = engine->i915;
1349 ret = intel_mocs_init_engine(engine);
1353 lrc_init_hws(engine);
1355 intel_engine_reset_breadcrumbs(engine);
1357 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1359 I915_WRITE(RING_MODE_GEN7(engine),
1360 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1361 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1363 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1365 intel_engine_init_hangcheck(engine);
1367 /* After a GPU reset, we may have requests to replay */
1368 if (!execlists_elsp_idle(engine)) {
1369 engine->execlist_port[0].count = 0;
1370 engine->execlist_port[1].count = 0;
1371 execlists_submit_ports(engine);
1377 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1379 struct drm_i915_private *dev_priv = engine->i915;
1382 ret = gen8_init_common_ring(engine);
1386 /* We need to disable the AsyncFlip performance optimisations in order
1387 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1388 * programmed to '1' on all products.
1390 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1392 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1394 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1396 return init_workarounds_ring(engine);
1399 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1403 ret = gen8_init_common_ring(engine);
1407 return init_workarounds_ring(engine);
1410 static void reset_common_ring(struct intel_engine_cs *engine,
1411 struct drm_i915_gem_request *request)
1413 struct drm_i915_private *dev_priv = engine->i915;
1414 struct execlist_port *port = engine->execlist_port;
1415 struct intel_context *ce = &request->ctx->engine[engine->id];
1417 /* We want a simple context + ring to execute the breadcrumb update.
1418 * We cannot rely on the context being intact across the GPU hang,
1419 * so clear it and rebuild just what we need for the breadcrumb.
1420 * All pending requests for this context will be zapped, and any
1421 * future request will be after userspace has had the opportunity
1422 * to recreate its own state.
1424 execlists_init_reg_state(ce->lrc_reg_state,
1425 request->ctx, engine, ce->ring);
1427 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1428 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1429 i915_ggtt_offset(ce->ring->vma);
1430 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1432 request->ring->head = request->postfix;
1433 request->ring->last_retired_head = -1;
1434 intel_ring_update_space(request->ring);
1436 if (i915.enable_guc_submission)
1439 /* Catch up with any missed context-switch interrupts */
1440 I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0));
1441 if (request->ctx != port[0].request->ctx) {
1442 i915_gem_request_put(port[0].request);
1444 memset(&port[1], 0, sizeof(port[1]));
1447 GEM_BUG_ON(request->ctx != port[0].request->ctx);
1449 /* Reset WaIdleLiteRestore:bdw,skl as well */
1450 request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
1453 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1455 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1456 struct intel_ring *ring = req->ring;
1457 struct intel_engine_cs *engine = req->engine;
1458 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1461 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1465 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1466 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1467 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1469 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
1470 intel_ring_emit(ring, upper_32_bits(pd_daddr));
1471 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
1472 intel_ring_emit(ring, lower_32_bits(pd_daddr));
1475 intel_ring_emit(ring, MI_NOOP);
1476 intel_ring_advance(ring);
1481 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1482 u64 offset, u32 len,
1483 unsigned int dispatch_flags)
1485 struct intel_ring *ring = req->ring;
1486 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1489 /* Don't rely in hw updating PDPs, specially in lite-restore.
1490 * Ideally, we should set Force PD Restore in ctx descriptor,
1491 * but we can't. Force Restore would be a second option, but
1492 * it is unsafe in case of lite-restore (because the ctx is
1493 * not idle). PML4 is allocated during ppgtt init so this is
1494 * not needed in 48-bit.*/
1495 if (req->ctx->ppgtt &&
1496 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1497 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1498 !intel_vgpu_active(req->i915)) {
1499 ret = intel_logical_ring_emit_pdps(req);
1504 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1507 ret = intel_ring_begin(req, 4);
1511 /* FIXME(BDW): Address space and security selectors. */
1512 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
1514 (dispatch_flags & I915_DISPATCH_RS ?
1515 MI_BATCH_RESOURCE_STREAMER : 0));
1516 intel_ring_emit(ring, lower_32_bits(offset));
1517 intel_ring_emit(ring, upper_32_bits(offset));
1518 intel_ring_emit(ring, MI_NOOP);
1519 intel_ring_advance(ring);
1524 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1526 struct drm_i915_private *dev_priv = engine->i915;
1527 I915_WRITE_IMR(engine,
1528 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1529 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1532 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1534 struct drm_i915_private *dev_priv = engine->i915;
1535 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1538 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1540 struct intel_ring *ring = request->ring;
1544 ret = intel_ring_begin(request, 4);
1548 cmd = MI_FLUSH_DW + 1;
1550 /* We always require a command barrier so that subsequent
1551 * commands, such as breadcrumb interrupts, are strictly ordered
1552 * wrt the contents of the write cache being flushed to memory
1553 * (and thus being coherent from the CPU).
1555 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1557 if (mode & EMIT_INVALIDATE) {
1558 cmd |= MI_INVALIDATE_TLB;
1559 if (request->engine->id == VCS)
1560 cmd |= MI_INVALIDATE_BSD;
1563 intel_ring_emit(ring, cmd);
1564 intel_ring_emit(ring,
1565 I915_GEM_HWS_SCRATCH_ADDR |
1566 MI_FLUSH_DW_USE_GTT);
1567 intel_ring_emit(ring, 0); /* upper addr */
1568 intel_ring_emit(ring, 0); /* value */
1569 intel_ring_advance(ring);
1574 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1577 struct intel_ring *ring = request->ring;
1578 struct intel_engine_cs *engine = request->engine;
1580 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1581 bool vf_flush_wa = false, dc_flush_wa = false;
1586 flags |= PIPE_CONTROL_CS_STALL;
1588 if (mode & EMIT_FLUSH) {
1589 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1590 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1591 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1592 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1595 if (mode & EMIT_INVALIDATE) {
1596 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1597 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1598 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1599 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1600 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1601 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1602 flags |= PIPE_CONTROL_QW_WRITE;
1603 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1606 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1609 if (IS_GEN9(request->i915))
1612 /* WaForGAMHang:kbl */
1613 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1625 ret = intel_ring_begin(request, len);
1630 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1631 intel_ring_emit(ring, 0);
1632 intel_ring_emit(ring, 0);
1633 intel_ring_emit(ring, 0);
1634 intel_ring_emit(ring, 0);
1635 intel_ring_emit(ring, 0);
1639 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1640 intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
1641 intel_ring_emit(ring, 0);
1642 intel_ring_emit(ring, 0);
1643 intel_ring_emit(ring, 0);
1644 intel_ring_emit(ring, 0);
1647 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1648 intel_ring_emit(ring, flags);
1649 intel_ring_emit(ring, scratch_addr);
1650 intel_ring_emit(ring, 0);
1651 intel_ring_emit(ring, 0);
1652 intel_ring_emit(ring, 0);
1655 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1656 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
1657 intel_ring_emit(ring, 0);
1658 intel_ring_emit(ring, 0);
1659 intel_ring_emit(ring, 0);
1660 intel_ring_emit(ring, 0);
1663 intel_ring_advance(ring);
1668 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1671 * On BXT A steppings there is a HW coherency issue whereby the
1672 * MI_STORE_DATA_IMM storing the completed request's seqno
1673 * occasionally doesn't invalidate the CPU cache. Work around this by
1674 * clflushing the corresponding cacheline whenever the caller wants
1675 * the coherency to be guaranteed. Note that this cacheline is known
1676 * to be clean at this point, since we only write it in
1677 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1678 * this clflush in practice becomes an invalidate operation.
1680 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1684 * Reserve space for 2 NOOPs at the end of each request to be
1685 * used as a workaround for not being allowed to do lite
1686 * restore with HEAD==TAIL (WaIdleLiteRestore).
1688 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out)
1692 request->wa_tail = intel_ring_offset(request->ring, out);
1695 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request,
1698 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1699 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1701 *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1702 *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1704 *out++ = request->global_seqno;
1705 *out++ = MI_USER_INTERRUPT;
1707 request->tail = intel_ring_offset(request->ring, out);
1709 gen8_emit_wa_tail(request, out);
1712 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1714 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1717 /* We're using qword write, seqno should be aligned to 8 bytes. */
1718 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1720 /* w/a for post sync ops following a GPGPU operation we
1721 * need a prior CS_STALL, which is emitted by the flush
1722 * following the batch.
1724 *out++ = GFX_OP_PIPE_CONTROL(6);
1725 *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB |
1726 PIPE_CONTROL_CS_STALL |
1727 PIPE_CONTROL_QW_WRITE);
1728 *out++ = intel_hws_seqno_address(request->engine);
1730 *out++ = request->global_seqno;
1731 /* We're thrashing one dword of HWS. */
1733 *out++ = MI_USER_INTERRUPT;
1735 request->tail = intel_ring_offset(request->ring, out);
1737 gen8_emit_wa_tail(request, out);
1740 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1742 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1746 ret = intel_logical_ring_workarounds_emit(req);
1750 ret = intel_rcs_context_init_mocs(req);
1752 * Failing to program the MOCS is non-fatal.The system will not
1753 * run at peak performance. So generate an error and carry on.
1756 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1758 return i915_gem_render_state_emit(req);
1762 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1763 * @engine: Engine Command Streamer.
1765 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1767 struct drm_i915_private *dev_priv;
1770 * Tasklet cannot be active at this point due intel_mark_active/idle
1771 * so this is just for documentation.
1773 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1774 tasklet_kill(&engine->irq_tasklet);
1776 dev_priv = engine->i915;
1778 if (engine->buffer) {
1779 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1782 if (engine->cleanup)
1783 engine->cleanup(engine);
1785 if (engine->status_page.vma) {
1786 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1787 engine->status_page.vma = NULL;
1790 intel_engine_cleanup_common(engine);
1792 lrc_destroy_wa_ctx_obj(engine);
1793 engine->i915 = NULL;
1794 dev_priv->engine[engine->id] = NULL;
1798 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1800 struct intel_engine_cs *engine;
1801 enum intel_engine_id id;
1803 for_each_engine(engine, dev_priv, id) {
1804 engine->submit_request = execlists_submit_request;
1805 engine->schedule = execlists_schedule;
1810 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1812 /* Default vfuncs which can be overriden by each engine. */
1813 engine->init_hw = gen8_init_common_ring;
1814 engine->reset_hw = reset_common_ring;
1816 engine->context_pin = execlists_context_pin;
1817 engine->context_unpin = execlists_context_unpin;
1819 engine->request_alloc = execlists_request_alloc;
1821 engine->emit_flush = gen8_emit_flush;
1822 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1823 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1824 engine->submit_request = execlists_submit_request;
1825 engine->schedule = execlists_schedule;
1827 engine->irq_enable = gen8_logical_ring_enable_irq;
1828 engine->irq_disable = gen8_logical_ring_disable_irq;
1829 engine->emit_bb_start = gen8_emit_bb_start;
1830 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1831 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1835 logical_ring_default_irqs(struct intel_engine_cs *engine)
1837 unsigned shift = engine->irq_shift;
1838 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1839 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1843 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1845 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1848 /* The HWSP is part of the default context object in LRC mode. */
1849 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1851 return PTR_ERR(hws);
1853 engine->status_page.page_addr = hws + hws_offset;
1854 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1855 engine->status_page.vma = vma;
1861 logical_ring_setup(struct intel_engine_cs *engine)
1863 struct drm_i915_private *dev_priv = engine->i915;
1864 enum forcewake_domains fw_domains;
1866 intel_engine_setup_common(engine);
1868 /* Intentionally left blank. */
1869 engine->buffer = NULL;
1871 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1875 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1876 RING_CONTEXT_STATUS_PTR(engine),
1877 FW_REG_READ | FW_REG_WRITE);
1879 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1880 RING_CONTEXT_STATUS_BUF_BASE(engine),
1883 engine->fw_domains = fw_domains;
1885 tasklet_init(&engine->irq_tasklet,
1886 intel_lrc_irq_handler, (unsigned long)engine);
1888 logical_ring_init_platform_invariants(engine);
1889 logical_ring_default_vfuncs(engine);
1890 logical_ring_default_irqs(engine);
1894 logical_ring_init(struct intel_engine_cs *engine)
1896 struct i915_gem_context *dctx = engine->i915->kernel_context;
1899 ret = intel_engine_init_common(engine);
1903 /* And setup the hardware status page. */
1904 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1906 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1913 intel_logical_ring_cleanup(engine);
1917 int logical_render_ring_init(struct intel_engine_cs *engine)
1919 struct drm_i915_private *dev_priv = engine->i915;
1922 logical_ring_setup(engine);
1924 if (HAS_L3_DPF(dev_priv))
1925 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1927 /* Override some for render ring. */
1928 if (INTEL_GEN(dev_priv) >= 9)
1929 engine->init_hw = gen9_init_render_ring;
1931 engine->init_hw = gen8_init_render_ring;
1932 engine->init_context = gen8_init_rcs_context;
1933 engine->emit_flush = gen8_emit_flush_render;
1934 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1935 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1937 ret = intel_engine_create_scratch(engine, 4096);
1941 ret = intel_init_workaround_bb(engine);
1944 * We continue even if we fail to initialize WA batch
1945 * because we only expect rare glitches but nothing
1946 * critical to prevent us from using GPU
1948 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1952 return logical_ring_init(engine);
1955 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1957 logical_ring_setup(engine);
1959 return logical_ring_init(engine);
1963 make_rpcs(struct drm_i915_private *dev_priv)
1968 * No explicit RPCS request is needed to ensure full
1969 * slice/subslice/EU enablement prior to Gen9.
1971 if (INTEL_GEN(dev_priv) < 9)
1975 * Starting in Gen9, render power gating can leave
1976 * slice/subslice/EU in a partially enabled state. We
1977 * must make an explicit request through RPCS for full
1980 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1981 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1982 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1983 GEN8_RPCS_S_CNT_SHIFT;
1984 rpcs |= GEN8_RPCS_ENABLE;
1987 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1988 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1989 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1990 GEN8_RPCS_SS_CNT_SHIFT;
1991 rpcs |= GEN8_RPCS_ENABLE;
1994 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
1995 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1996 GEN8_RPCS_EU_MIN_SHIFT;
1997 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1998 GEN8_RPCS_EU_MAX_SHIFT;
1999 rpcs |= GEN8_RPCS_ENABLE;
2005 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2007 u32 indirect_ctx_offset;
2009 switch (INTEL_GEN(engine->i915)) {
2011 MISSING_CASE(INTEL_GEN(engine->i915));
2014 indirect_ctx_offset =
2015 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2018 indirect_ctx_offset =
2019 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2023 return indirect_ctx_offset;
2026 static void execlists_init_reg_state(u32 *reg_state,
2027 struct i915_gem_context *ctx,
2028 struct intel_engine_cs *engine,
2029 struct intel_ring *ring)
2031 struct drm_i915_private *dev_priv = engine->i915;
2032 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2034 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
2035 * commands followed by (reg, value) pairs. The values we are setting here are
2036 * only for the first context restore: on a subsequent save, the GPU will
2037 * recreate this batchbuffer with new values (including all the missing
2038 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
2039 reg_state[CTX_LRI_HEADER_0] =
2040 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
2041 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
2042 RING_CONTEXT_CONTROL(engine),
2043 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2044 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2045 (HAS_RESOURCE_STREAMER(dev_priv) ?
2046 CTX_CTRL_RS_CTX_ENABLE : 0)));
2047 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
2049 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2051 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2052 RING_START(engine->mmio_base), 0);
2053 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2054 RING_CTL(engine->mmio_base),
2055 RING_CTL_SIZE(ring->size) | RING_VALID);
2056 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2057 RING_BBADDR_UDW(engine->mmio_base), 0);
2058 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2059 RING_BBADDR(engine->mmio_base), 0);
2060 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2061 RING_BBSTATE(engine->mmio_base),
2063 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2064 RING_SBBADDR_UDW(engine->mmio_base), 0);
2065 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2066 RING_SBBADDR(engine->mmio_base), 0);
2067 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2068 RING_SBBSTATE(engine->mmio_base), 0);
2069 if (engine->id == RCS) {
2070 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2071 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2072 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2073 RING_INDIRECT_CTX(engine->mmio_base), 0);
2074 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2075 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2076 if (engine->wa_ctx.vma) {
2077 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2078 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2080 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2081 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2082 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2084 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2085 intel_lr_indirect_ctx_offset(engine) << 6;
2087 reg_state[CTX_BB_PER_CTX_PTR+1] =
2088 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2092 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2093 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2094 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2095 /* PDP values well be assigned later if needed */
2096 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2098 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2100 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2102 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2104 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2106 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2108 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2110 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2113 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2114 /* 64b PPGTT (48bit canonical)
2115 * PDP0_DESCRIPTOR contains the base address to PML4 and
2116 * other PDP Descriptors are ignored.
2118 ASSIGN_CTX_PML4(ppgtt, reg_state);
2121 * PDP*_DESCRIPTOR contains the base address of space supported.
2122 * With dynamic page allocation, PDPs may not be allocated at
2123 * this point. Point the unallocated PDPs to the scratch page
2125 execlists_update_context_pdps(ppgtt, reg_state);
2128 if (engine->id == RCS) {
2129 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2130 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2131 make_rpcs(dev_priv));
2136 populate_lr_context(struct i915_gem_context *ctx,
2137 struct drm_i915_gem_object *ctx_obj,
2138 struct intel_engine_cs *engine,
2139 struct intel_ring *ring)
2144 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2146 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2150 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2151 if (IS_ERR(vaddr)) {
2152 ret = PTR_ERR(vaddr);
2153 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2156 ctx_obj->mm.dirty = true;
2158 /* The second page of the context object contains some fields which must
2159 * be set up prior to the first execution. */
2161 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
2164 i915_gem_object_unpin_map(ctx_obj);
2170 * intel_lr_context_size() - return the size of the context for an engine
2171 * @engine: which engine to find the context size for
2173 * Each engine may require a different amount of space for a context image,
2174 * so when allocating (or copying) an image, this function can be used to
2175 * find the right size for the specific engine.
2177 * Return: size (in bytes) of an engine-specific context image
2179 * Note: this size includes the HWSP, which is part of the context image
2180 * in LRC mode, but does not include the "shared data page" used with
2181 * GuC submission. The caller should account for this if using the GuC.
2183 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2187 WARN_ON(INTEL_GEN(engine->i915) < 8);
2189 switch (engine->id) {
2191 if (INTEL_GEN(engine->i915) >= 9)
2192 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2194 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2200 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2207 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2208 struct intel_engine_cs *engine)
2210 struct drm_i915_gem_object *ctx_obj;
2211 struct intel_context *ce = &ctx->engine[engine->id];
2212 struct i915_vma *vma;
2213 uint32_t context_size;
2214 struct intel_ring *ring;
2219 context_size = round_up(intel_lr_context_size(engine), 4096);
2221 /* One extra page as the sharing data between driver and GuC */
2222 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2224 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2225 if (IS_ERR(ctx_obj)) {
2226 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2227 return PTR_ERR(ctx_obj);
2230 vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL);
2233 goto error_deref_obj;
2236 ring = intel_engine_create_ring(engine, ctx->ring_size);
2238 ret = PTR_ERR(ring);
2239 goto error_deref_obj;
2242 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2244 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2245 goto error_ring_free;
2250 ce->initialised = engine->init_context == NULL;
2255 intel_ring_free(ring);
2257 i915_gem_object_put(ctx_obj);
2261 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2263 struct intel_engine_cs *engine;
2264 struct i915_gem_context *ctx;
2265 enum intel_engine_id id;
2267 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2268 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2269 * that stored in context. As we only write new commands from
2270 * ce->ring->tail onwards, everything before that is junk. If the GPU
2271 * starts reading from its RING_HEAD from the context, it may try to
2272 * execute that junk and die.
2274 * So to avoid that we reset the context images upon resume. For
2275 * simplicity, we just zero everything out.
2277 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2278 for_each_engine(engine, dev_priv, id) {
2279 struct intel_context *ce = &ctx->engine[engine->id];
2285 reg = i915_gem_object_pin_map(ce->state->obj,
2287 if (WARN_ON(IS_ERR(reg)))
2290 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2291 reg[CTX_RING_HEAD+1] = 0;
2292 reg[CTX_RING_TAIL+1] = 0;
2294 ce->state->obj->mm.dirty = true;
2295 i915_gem_object_unpin_map(ce->state->obj);
2297 ce->ring->head = ce->ring->tail = 0;
2298 ce->ring->last_retired_head = -1;
2299 intel_ring_update_space(ce->ring);