2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 static const struct gmbus_port gmbus_ports[] = {
51 /* Intel GPIO access functions */
53 #define I2C_RISEFALL_TIME 10
55 static inline struct intel_gmbus *
56 to_intel_gmbus(struct i2c_adapter *i2c)
58 return container_of(i2c, struct intel_gmbus, adapter);
62 intel_i2c_reset(struct drm_device *dev)
64 struct drm_i915_private *dev_priv = dev->dev_private;
65 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
68 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
72 /* When using bit bashing for I2C, this bit needs to be set to 1 */
73 if (!IS_PINEVIEW(dev_priv->dev))
76 val = I915_READ(DSPCLK_GATE_D);
78 val |= DPCUNIT_CLOCK_GATE_DISABLE;
80 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
81 I915_WRITE(DSPCLK_GATE_D, val);
84 static u32 get_reserved(struct intel_gmbus *bus)
86 struct drm_i915_private *dev_priv = bus->dev_priv;
87 struct drm_device *dev = dev_priv->dev;
90 /* On most chips, these bits must be preserved in software. */
91 if (!IS_I830(dev) && !IS_845G(dev))
92 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
93 (GPIO_DATA_PULLUP_DISABLE |
94 GPIO_CLOCK_PULLUP_DISABLE);
99 static int get_clock(void *data)
101 struct intel_gmbus *bus = data;
102 struct drm_i915_private *dev_priv = bus->dev_priv;
103 u32 reserved = get_reserved(bus);
104 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
105 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
106 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
109 static int get_data(void *data)
111 struct intel_gmbus *bus = data;
112 struct drm_i915_private *dev_priv = bus->dev_priv;
113 u32 reserved = get_reserved(bus);
114 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
115 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
116 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
119 static void set_clock(void *data, int state_high)
121 struct intel_gmbus *bus = data;
122 struct drm_i915_private *dev_priv = bus->dev_priv;
123 u32 reserved = get_reserved(bus);
127 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
129 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
132 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
133 POSTING_READ(bus->gpio_reg);
136 static void set_data(void *data, int state_high)
138 struct intel_gmbus *bus = data;
139 struct drm_i915_private *dev_priv = bus->dev_priv;
140 u32 reserved = get_reserved(bus);
144 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
146 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
149 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
150 POSTING_READ(bus->gpio_reg);
154 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
156 struct intel_gmbus *bus = container_of(adapter,
159 struct drm_i915_private *dev_priv = bus->dev_priv;
161 intel_i2c_reset(dev_priv->dev);
162 intel_i2c_quirk_set(dev_priv, true);
165 udelay(I2C_RISEFALL_TIME);
170 intel_gpio_post_xfer(struct i2c_adapter *adapter)
172 struct intel_gmbus *bus = container_of(adapter,
175 struct drm_i915_private *dev_priv = bus->dev_priv;
179 intel_i2c_quirk_set(dev_priv, false);
183 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
185 struct drm_i915_private *dev_priv = bus->dev_priv;
186 struct i2c_algo_bit_data *algo;
188 algo = &bus->bit_algo;
190 /* -1 to map pin pair to gmbus index */
191 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
193 bus->adapter.algo_data = algo;
194 algo->setsda = set_data;
195 algo->setscl = set_clock;
196 algo->getsda = get_data;
197 algo->getscl = get_clock;
198 algo->pre_xfer = intel_gpio_pre_xfer;
199 algo->post_xfer = intel_gpio_post_xfer;
200 algo->udelay = I2C_RISEFALL_TIME;
201 algo->timeout = usecs_to_jiffies(2200);
206 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
209 int reg_offset = dev_priv->gpio_mmio_base;
213 I915_WRITE(GMBUS1 + reg_offset,
216 (len << GMBUS_BYTE_COUNT_SHIFT) |
217 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
218 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
224 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
225 (GMBUS_SATOER | GMBUS_HW_RDY),
229 if (gmbus2 & GMBUS_SATOER)
232 val = I915_READ(GMBUS3 + reg_offset);
236 } while (--len && ++loop < 4);
243 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
245 int reg_offset = dev_priv->gpio_mmio_base;
251 while (len && loop < 4) {
252 val |= *buf++ << (8 * loop++);
256 I915_WRITE(GMBUS3 + reg_offset, val);
257 I915_WRITE(GMBUS1 + reg_offset,
259 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
260 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
261 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
268 val |= *buf++ << (8 * loop);
269 } while (--len && ++loop < 4);
271 I915_WRITE(GMBUS3 + reg_offset, val);
273 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
274 (GMBUS_SATOER | GMBUS_HW_RDY),
278 if (gmbus2 & GMBUS_SATOER)
285 * The gmbus controller can combine a 1 or 2 byte write with a read that
286 * immediately follows it by using an "INDEX" cycle.
289 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
291 return (i + 1 < num &&
292 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
293 (msgs[i + 1].flags & I2C_M_RD));
297 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
299 int reg_offset = dev_priv->gpio_mmio_base;
300 u32 gmbus1_index = 0;
304 if (msgs[0].len == 2)
305 gmbus5 = GMBUS_2BYTE_INDEX_EN |
306 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
307 if (msgs[0].len == 1)
308 gmbus1_index = GMBUS_CYCLE_INDEX |
309 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
311 /* GMBUS5 holds 16-bit index */
313 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
315 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
317 /* Clear GMBUS5 after each index transfer */
319 I915_WRITE(GMBUS5 + reg_offset, 0);
325 gmbus_xfer(struct i2c_adapter *adapter,
326 struct i2c_msg *msgs,
329 struct intel_gmbus *bus = container_of(adapter,
332 struct drm_i915_private *dev_priv = bus->dev_priv;
336 mutex_lock(&dev_priv->gmbus_mutex);
338 if (bus->force_bit) {
339 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
343 reg_offset = dev_priv->gpio_mmio_base;
345 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
347 for (i = 0; i < num; i++) {
350 if (gmbus_is_index_read(msgs, i, num)) {
351 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
352 i += 1; /* set i to the index of the read xfer */
353 } else if (msgs[i].flags & I2C_M_RD) {
354 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
356 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
359 if (ret == -ETIMEDOUT)
364 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
365 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
369 if (gmbus2 & GMBUS_SATOER)
373 /* Generate a STOP condition on the bus. Note that gmbus can't generata
374 * a STOP on the very first cycle. To simplify the code we
375 * unconditionally generate the STOP condition with an additional gmbus
377 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
379 /* Mark the GMBUS interface as disabled after waiting for idle.
380 * We will re-enable it at the start of the next xfer,
381 * till then let it sleep.
383 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
385 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
389 I915_WRITE(GMBUS0 + reg_offset, 0);
395 * Wait for bus to IDLE before clearing NAK.
396 * If we clear the NAK while bus is still active, then it will stay
397 * active and the next transaction may fail.
399 * If no ACK is received during the address phase of a transaction, the
400 * adapter must report -ENXIO. It is not clear what to return if no ACK
401 * is received at other times. But we have to be careful to not return
402 * spurious -ENXIO because that will prevent i2c and drm edid functions
403 * from retrying. So return -ENXIO only when gmbus properly quiescents -
404 * timing out seems to happen when there _is_ a ddc chip present, but
405 * it's slow responding and only answers on the 2nd retry.
408 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
410 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
415 /* Toggle the Software Clear Interrupt bit. This has the effect
416 * of resetting the GMBUS controller and so clearing the
417 * BUS_ERROR raised by the slave's NAK.
419 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
420 I915_WRITE(GMBUS1 + reg_offset, 0);
421 I915_WRITE(GMBUS0 + reg_offset, 0);
423 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
424 adapter->name, msgs[i].addr,
425 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
430 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
431 bus->adapter.name, bus->reg0 & 0xff);
432 I915_WRITE(GMBUS0 + reg_offset, 0);
434 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
435 bus->force_bit = true;
436 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
439 mutex_unlock(&dev_priv->gmbus_mutex);
443 static u32 gmbus_func(struct i2c_adapter *adapter)
445 return i2c_bit_algo.functionality(adapter) &
446 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
447 /* I2C_FUNC_10BIT_ADDR | */
448 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
449 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
452 static const struct i2c_algorithm gmbus_algorithm = {
453 .master_xfer = gmbus_xfer,
454 .functionality = gmbus_func
458 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
461 int intel_setup_gmbus(struct drm_device *dev)
463 struct drm_i915_private *dev_priv = dev->dev_private;
466 if (HAS_PCH_SPLIT(dev))
467 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
469 dev_priv->gpio_mmio_base = 0;
471 mutex_init(&dev_priv->gmbus_mutex);
473 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
474 struct intel_gmbus *bus = &dev_priv->gmbus[i];
475 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
477 bus->adapter.owner = THIS_MODULE;
478 bus->adapter.class = I2C_CLASS_DDC;
479 snprintf(bus->adapter.name,
480 sizeof(bus->adapter.name),
482 gmbus_ports[i].name);
484 bus->adapter.dev.parent = &dev->pdev->dev;
485 bus->dev_priv = dev_priv;
487 bus->adapter.algo = &gmbus_algorithm;
489 /* By default use a conservative clock rate */
490 bus->reg0 = port | GMBUS_RATE_100KHZ;
492 /* gmbus seems to be broken on i830 */
494 bus->force_bit = true;
496 intel_gpio_setup(bus, port);
498 ret = i2c_add_adapter(&bus->adapter);
503 intel_i2c_reset(dev_priv->dev);
509 struct intel_gmbus *bus = &dev_priv->gmbus[i];
510 i2c_del_adapter(&bus->adapter);
515 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
518 WARN_ON(!intel_gmbus_is_port_valid(port));
519 /* -1 to map pin pair to gmbus index */
520 return (intel_gmbus_is_port_valid(port)) ?
521 &dev_priv->gmbus[port - 1].adapter : NULL;
524 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
526 struct intel_gmbus *bus = to_intel_gmbus(adapter);
528 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
531 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
533 struct intel_gmbus *bus = to_intel_gmbus(adapter);
535 bus->force_bit = force_bit;
538 void intel_teardown_gmbus(struct drm_device *dev)
540 struct drm_i915_private *dev_priv = dev->dev_private;
543 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
544 struct intel_gmbus *bus = &dev_priv->gmbus[i];
545 i2c_del_adapter(&bus->adapter);