drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include <drm/intel_lpe_audio.h>
  42 #include "i915_drv.h"
  43
  44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  45 {
  46         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  47 }
  48
  49 static void
  50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  51 {
  52         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  53         struct drm_i915_private *dev_priv = to_i915(dev);
  54         uint32_t enabled_bits;
  55
  56         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  57
  58         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  59              "HDMI port enabled, expecting disabled\n");
  60 }
  61
  62 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  63 {
  64         struct intel_digital_port *intel_dig_port =
  65                 container_of(encoder, struct intel_digital_port, base.base);
  66         return &intel_dig_port->hdmi;
  67 }
  68
  69 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  70 {
  71         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  72 }
  73
  74 static u32 g4x_infoframe_index(unsigned int type)
  75 {
  76         switch (type) {
  77         case HDMI_INFOFRAME_TYPE_AVI:
  78                 return VIDEO_DIP_SELECT_AVI;
  79         case HDMI_INFOFRAME_TYPE_SPD:
  80                 return VIDEO_DIP_SELECT_SPD;
  81         case HDMI_INFOFRAME_TYPE_VENDOR:
  82                 return VIDEO_DIP_SELECT_VENDOR;
  83         default:
  84                 MISSING_CASE(type);
  85                 return 0;
  86         }
  87 }
  88
  89 static u32 g4x_infoframe_enable(unsigned int type)
  90 {
  91         switch (type) {
  92         case HDMI_INFOFRAME_TYPE_AVI:
  93                 return VIDEO_DIP_ENABLE_AVI;
  94         case HDMI_INFOFRAME_TYPE_SPD:
  95                 return VIDEO_DIP_ENABLE_SPD;
  96         case HDMI_INFOFRAME_TYPE_VENDOR:
  97                 return VIDEO_DIP_ENABLE_VENDOR;
  98         default:
  99                 MISSING_CASE(type);
 100                 return 0;
 101         }
 102 }
 103
 104 static u32 hsw_infoframe_enable(unsigned int type)
 105 {
 106         switch (type) {
 107         case DP_SDP_VSC:
 108                 return VIDEO_DIP_ENABLE_VSC_HSW;
 109         case HDMI_INFOFRAME_TYPE_AVI:
 110                 return VIDEO_DIP_ENABLE_AVI_HSW;
 111         case HDMI_INFOFRAME_TYPE_SPD:
 112                 return VIDEO_DIP_ENABLE_SPD_HSW;
 113         case HDMI_INFOFRAME_TYPE_VENDOR:
 114                 return VIDEO_DIP_ENABLE_VS_HSW;
 115         default:
 116                 MISSING_CASE(type);
 117                 return 0;
 118         }
 119 }
 120
 121 static i915_reg_t
 122 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 123                  enum transcoder cpu_transcoder,
 124                  unsigned int type,
 125                  int i)
 126 {
 127         switch (type) {
 128         case DP_SDP_VSC:
 129                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 130         case HDMI_INFOFRAME_TYPE_AVI:
 131                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 132         case HDMI_INFOFRAME_TYPE_SPD:
 133                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 134         case HDMI_INFOFRAME_TYPE_VENDOR:
 135                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 136         default:
 137                 MISSING_CASE(type);
 138                 return INVALID_MMIO_REG;
 139         }
 140 }
 141
 142 static void g4x_write_infoframe(struct drm_encoder *encoder,
 143                                 const struct intel_crtc_state *crtc_state,
 144                                 unsigned int type,
 145                                 const void *frame, ssize_t len)
 146 {
 147         const uint32_t *data = frame;
 148         struct drm_device *dev = encoder->dev;
 149         struct drm_i915_private *dev_priv = to_i915(dev);
 150         u32 val = I915_READ(VIDEO_DIP_CTL);
 151         int i;
 152
 153         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 154
 155         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 156         val |= g4x_infoframe_index(type);
 157
 158         val &= ~g4x_infoframe_enable(type);
 159
 160         I915_WRITE(VIDEO_DIP_CTL, val);
 161
 162         mmiowb();
 163         for (i = 0; i < len; i += 4) {
 164                 I915_WRITE(VIDEO_DIP_DATA, *data);
 165                 data++;
 166         }
 167         /* Write every possible data byte to force correct ECC calculation. */
 168         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 169                 I915_WRITE(VIDEO_DIP_DATA, 0);
 170         mmiowb();
 171
 172         val |= g4x_infoframe_enable(type);
 173         val &= ~VIDEO_DIP_FREQ_MASK;
 174         val |= VIDEO_DIP_FREQ_VSYNC;
 175
 176         I915_WRITE(VIDEO_DIP_CTL, val);
 177         POSTING_READ(VIDEO_DIP_CTL);
 178 }
 179
 180 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 181                                   const struct intel_crtc_state *pipe_config)
 182 {
 183         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 184         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 185         u32 val = I915_READ(VIDEO_DIP_CTL);
 186
 187         if ((val & VIDEO_DIP_ENABLE) == 0)
 188                 return false;
 189
 190         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 191                 return false;
 192
 193         return val & (VIDEO_DIP_ENABLE_AVI |
 194                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 195 }
 196
 197 static void ibx_write_infoframe(struct drm_encoder *encoder,
 198                                 const struct intel_crtc_state *crtc_state,
 199                                 unsigned int type,
 200                                 const void *frame, ssize_t len)
 201 {
 202         const uint32_t *data = frame;
 203         struct drm_device *dev = encoder->dev;
 204         struct drm_i915_private *dev_priv = to_i915(dev);
 205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 206         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 207         u32 val = I915_READ(reg);
 208         int i;
 209
 210         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 211
 212         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 213         val |= g4x_infoframe_index(type);
 214
 215         val &= ~g4x_infoframe_enable(type);
 216
 217         I915_WRITE(reg, val);
 218
 219         mmiowb();
 220         for (i = 0; i < len; i += 4) {
 221                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 222                 data++;
 223         }
 224         /* Write every possible data byte to force correct ECC calculation. */
 225         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 226                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 227         mmiowb();
 228
 229         val |= g4x_infoframe_enable(type);
 230         val &= ~VIDEO_DIP_FREQ_MASK;
 231         val |= VIDEO_DIP_FREQ_VSYNC;
 232
 233         I915_WRITE(reg, val);
 234         POSTING_READ(reg);
 235 }
 236
 237 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 238                                   const struct intel_crtc_state *pipe_config)
 239 {
 240         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 241         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 242         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 243         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 244         u32 val = I915_READ(reg);
 245
 246         if ((val & VIDEO_DIP_ENABLE) == 0)
 247                 return false;
 248
 249         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 250                 return false;
 251
 252         return val & (VIDEO_DIP_ENABLE_AVI |
 253                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 254                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 255 }
 256
 257 static void cpt_write_infoframe(struct drm_encoder *encoder,
 258                                 const struct intel_crtc_state *crtc_state,
 259                                 unsigned int type,
 260                                 const void *frame, ssize_t len)
 261 {
 262         const uint32_t *data = frame;
 263         struct drm_device *dev = encoder->dev;
 264         struct drm_i915_private *dev_priv = to_i915(dev);
 265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 266         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 267         u32 val = I915_READ(reg);
 268         int i;
 269
 270         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 271
 272         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 273         val |= g4x_infoframe_index(type);
 274
 275         /* The DIP control register spec says that we need to update the AVI
 276          * infoframe without clearing its enable bit */
 277         if (type != HDMI_INFOFRAME_TYPE_AVI)
 278                 val &= ~g4x_infoframe_enable(type);
 279
 280         I915_WRITE(reg, val);
 281
 282         mmiowb();
 283         for (i = 0; i < len; i += 4) {
 284                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 285                 data++;
 286         }
 287         /* Write every possible data byte to force correct ECC calculation. */
 288         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 289                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 290         mmiowb();
 291
 292         val |= g4x_infoframe_enable(type);
 293         val &= ~VIDEO_DIP_FREQ_MASK;
 294         val |= VIDEO_DIP_FREQ_VSYNC;
 295
 296         I915_WRITE(reg, val);
 297         POSTING_READ(reg);
 298 }
 299
 300 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 301                                   const struct intel_crtc_state *pipe_config)
 302 {
 303         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 304         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 305         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 306
 307         if ((val & VIDEO_DIP_ENABLE) == 0)
 308                 return false;
 309
 310         return val & (VIDEO_DIP_ENABLE_AVI |
 311                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 312                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 313 }
 314
 315 static void vlv_write_infoframe(struct drm_encoder *encoder,
 316                                 const struct intel_crtc_state *crtc_state,
 317                                 unsigned int type,
 318                                 const void *frame, ssize_t len)
 319 {
 320         const uint32_t *data = frame;
 321         struct drm_device *dev = encoder->dev;
 322         struct drm_i915_private *dev_priv = to_i915(dev);
 323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 324         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 325         u32 val = I915_READ(reg);
 326         int i;
 327
 328         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 329
 330         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 331         val |= g4x_infoframe_index(type);
 332
 333         val &= ~g4x_infoframe_enable(type);
 334
 335         I915_WRITE(reg, val);
 336
 337         mmiowb();
 338         for (i = 0; i < len; i += 4) {
 339                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 340                 data++;
 341         }
 342         /* Write every possible data byte to force correct ECC calculation. */
 343         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 344                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 345         mmiowb();
 346
 347         val |= g4x_infoframe_enable(type);
 348         val &= ~VIDEO_DIP_FREQ_MASK;
 349         val |= VIDEO_DIP_FREQ_VSYNC;
 350
 351         I915_WRITE(reg, val);
 352         POSTING_READ(reg);
 353 }
 354
 355 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 356                                   const struct intel_crtc_state *pipe_config)
 357 {
 358         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 359         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 360         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 361         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 362
 363         if ((val & VIDEO_DIP_ENABLE) == 0)
 364                 return false;
 365
 366         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 367                 return false;
 368
 369         return val & (VIDEO_DIP_ENABLE_AVI |
 370                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 371                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 372 }
 373
 374 static void hsw_write_infoframe(struct drm_encoder *encoder,
 375                                 const struct intel_crtc_state *crtc_state,
 376                                 unsigned int type,
 377                                 const void *frame, ssize_t len)
 378 {
 379         const uint32_t *data = frame;
 380         struct drm_device *dev = encoder->dev;
 381         struct drm_i915_private *dev_priv = to_i915(dev);
 382         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 383         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 384         i915_reg_t data_reg;
 385         int data_size = type == DP_SDP_VSC ?
 386                 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
 387         int i;
 388         u32 val = I915_READ(ctl_reg);
 389
 390         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 391
 392         val &= ~hsw_infoframe_enable(type);
 393         I915_WRITE(ctl_reg, val);
 394
 395         mmiowb();
 396         for (i = 0; i < len; i += 4) {
 397                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 398                                             type, i >> 2), *data);
 399                 data++;
 400         }
 401         /* Write every possible data byte to force correct ECC calculation. */
 402         for (; i < data_size; i += 4)
 403                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 404                                             type, i >> 2), 0);
 405         mmiowb();
 406
 407         val |= hsw_infoframe_enable(type);
 408         I915_WRITE(ctl_reg, val);
 409         POSTING_READ(ctl_reg);
 410 }
 411
 412 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 413                                   const struct intel_crtc_state *pipe_config)
 414 {
 415         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 416         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 417
 418         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 419                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 420                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 421 }
 422
 423 /*
 424  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 425  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 426  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 427  * used for both technologies.
 428  *
 429  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 430  * DW1:       DB3       | DB2 | DB1 | DB0
 431  * DW2:       DB7       | DB6 | DB5 | DB4
 432  * DW3: ...
 433  *
 434  * (HB is Header Byte, DB is Data Byte)
 435  *
 436  * The hdmi pack() functions don't know about that hardware specific hole so we
 437  * trick them by giving an offset into the buffer and moving back the header
 438  * bytes by one.
 439  */
 440 static void intel_write_infoframe(struct drm_encoder *encoder,
 441                                   const struct intel_crtc_state *crtc_state,
 442                                   union hdmi_infoframe *frame)
 443 {
 444         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 445         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 446         ssize_t len;
 447
 448         /* see comment above for the reason for this offset */
 449         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 450         if (len < 0)
 451                 return;
 452
 453         /* Insert the 'hole' (see big comment above) at position 3 */
 454         buffer[0] = buffer[1];
 455         buffer[1] = buffer[2];
 456         buffer[2] = buffer[3];
 457         buffer[3] = 0;
 458         len++;
 459
 460         intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 461 }
 462
 463 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 464                                          const struct intel_crtc_state *crtc_state)
 465 {
 466         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 467         const struct drm_display_mode *adjusted_mode =
 468                 &crtc_state->base.adjusted_mode;
 469         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 470         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
 471         union hdmi_infoframe frame;
 472         int ret;
 473
 474         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 475                                                        adjusted_mode,
 476                                                        is_hdmi2_sink);
 477         if (ret < 0) {
 478                 DRM_ERROR("couldn't fill AVI infoframe\n");
 479                 return;
 480         }
 481
 482         if (crtc_state->ycbcr420)
 483                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 484         else
 485                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 486
 487         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 488                                            crtc_state->limited_color_range ?
 489                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 490                                            HDMI_QUANTIZATION_RANGE_FULL,
 491                                            intel_hdmi->rgb_quant_range_selectable,
 492                                            is_hdmi2_sink);
 493
 494         /* TODO: handle pixel repetition for YCBCR420 outputs */
 495         intel_write_infoframe(encoder, crtc_state, &frame);
 496 }
 497
 498 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 499                                          const struct intel_crtc_state *crtc_state)
 500 {
 501         union hdmi_infoframe frame;
 502         int ret;
 503
 504         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 505         if (ret < 0) {
 506                 DRM_ERROR("couldn't fill SPD infoframe\n");
 507                 return;
 508         }
 509
 510         frame.spd.sdi = HDMI_SPD_SDI_PC;
 511
 512         intel_write_infoframe(encoder, crtc_state, &frame);
 513 }
 514
 515 static void
 516 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 517                               const struct intel_crtc_state *crtc_state,
 518                               const struct drm_connector_state *conn_state)
 519 {
 520         union hdmi_infoframe frame;
 521         int ret;
 522
 523         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 524                                                           conn_state->connector,
 525                                                           &crtc_state->base.adjusted_mode);
 526         if (ret < 0)
 527                 return;
 528
 529         intel_write_infoframe(encoder, crtc_state, &frame);
 530 }
 531
 532 static void g4x_set_infoframes(struct drm_encoder *encoder,
 533                                bool enable,
 534                                const struct intel_crtc_state *crtc_state,
 535                                const struct drm_connector_state *conn_state)
 536 {
 537         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 538         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 539         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 540         i915_reg_t reg = VIDEO_DIP_CTL;
 541         u32 val = I915_READ(reg);
 542         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 543
 544         assert_hdmi_port_disabled(intel_hdmi);
 545
 546         /* If the registers were not initialized yet, they might be zeroes,
 547          * which means we're selecting the AVI DIP and we're setting its
 548          * frequency to once. This seems to really confuse the HW and make
 549          * things stop working (the register spec says the AVI always needs to
 550          * be sent every VSync). So here we avoid writing to the register more
 551          * than we need and also explicitly select the AVI DIP and explicitly
 552          * set its frequency to every VSync. Avoiding to write it twice seems to
 553          * be enough to solve the problem, but being defensive shouldn't hurt us
 554          * either. */
 555         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 556
 557         if (!enable) {
 558                 if (!(val & VIDEO_DIP_ENABLE))
 559                         return;
 560                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 561                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 562                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 563                         return;
 564                 }
 565                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 566                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 567                 I915_WRITE(reg, val);
 568                 POSTING_READ(reg);
 569                 return;
 570         }
 571
 572         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 573                 if (val & VIDEO_DIP_ENABLE) {
 574                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 575                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 576                         return;
 577                 }
 578                 val &= ~VIDEO_DIP_PORT_MASK;
 579                 val |= port;
 580         }
 581
 582         val |= VIDEO_DIP_ENABLE;
 583         val &= ~(VIDEO_DIP_ENABLE_AVI |
 584                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 585
 586         I915_WRITE(reg, val);
 587         POSTING_READ(reg);
 588
 589         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 590         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 591         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 592 }
 593
 594 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 595 {
 596         struct drm_connector *connector = conn_state->connector;
 597
 598         /*
 599          * HDMI cloning is only supported on g4x which doesn't
 600          * support deep color or GCP infoframes anyway so no
 601          * need to worry about multiple HDMI sinks here.
 602          */
 603
 604         return connector->display_info.bpc > 8;
 605 }
 606
 607 /*
 608  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 609  *
 610  * From HDMI specification 1.4a:
 611  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 612  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 613  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 614  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 615  *   phase of 0
 616  */
 617 static bool gcp_default_phase_possible(int pipe_bpp,
 618                                        const struct drm_display_mode *mode)
 619 {
 620         unsigned int pixels_per_group;
 621
 622         switch (pipe_bpp) {
 623         case 30:
 624                 /* 4 pixels in 5 clocks */
 625                 pixels_per_group = 4;
 626                 break;
 627         case 36:
 628                 /* 2 pixels in 3 clocks */
 629                 pixels_per_group = 2;
 630                 break;
 631         case 48:
 632                 /* 1 pixel in 2 clocks */
 633                 pixels_per_group = 1;
 634                 break;
 635         default:
 636                 /* phase information not relevant for 8bpc */
 637                 return false;
 638         }
 639
 640         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 641                 mode->crtc_htotal % pixels_per_group == 0 &&
 642                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 643                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 644                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 645                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 646                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 647                  mode->crtc_htotal/2 % pixels_per_group == 0);
 648 }
 649
 650 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 651                                          const struct intel_crtc_state *crtc_state,
 652                                          const struct drm_connector_state *conn_state)
 653 {
 654         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 655         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 656         i915_reg_t reg;
 657         u32 val = 0;
 658
 659         if (HAS_DDI(dev_priv))
 660                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 661         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 662                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 663         else if (HAS_PCH_SPLIT(dev_priv))
 664                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 665         else
 666                 return false;
 667
 668         /* Indicate color depth whenever the sink supports deep color */
 669         if (hdmi_sink_is_deep_color(conn_state))
 670                 val |= GCP_COLOR_INDICATION;
 671
 672         /* Enable default_phase whenever the display mode is suitably aligned */
 673         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 674                                        &crtc_state->base.adjusted_mode))
 675                 val |= GCP_DEFAULT_PHASE_ENABLE;
 676
 677         I915_WRITE(reg, val);
 678
 679         return val != 0;
 680 }
 681
 682 static void ibx_set_infoframes(struct drm_encoder *encoder,
 683                                bool enable,
 684                                const struct intel_crtc_state *crtc_state,
 685                                const struct drm_connector_state *conn_state)
 686 {
 687         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 689         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 690         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 691         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 692         u32 val = I915_READ(reg);
 693         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 694
 695         assert_hdmi_port_disabled(intel_hdmi);
 696
 697         /* See the big comment in g4x_set_infoframes() */
 698         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 699
 700         if (!enable) {
 701                 if (!(val & VIDEO_DIP_ENABLE))
 702                         return;
 703                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 704                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 705                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 706                 I915_WRITE(reg, val);
 707                 POSTING_READ(reg);
 708                 return;
 709         }
 710
 711         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 712                 WARN(val & VIDEO_DIP_ENABLE,
 713                      "DIP already enabled on port %c\n",
 714                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 715                 val &= ~VIDEO_DIP_PORT_MASK;
 716                 val |= port;
 717         }
 718
 719         val |= VIDEO_DIP_ENABLE;
 720         val &= ~(VIDEO_DIP_ENABLE_AVI |
 721                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 722                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 723
 724         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 725                 val |= VIDEO_DIP_ENABLE_GCP;
 726
 727         I915_WRITE(reg, val);
 728         POSTING_READ(reg);
 729
 730         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 731         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 732         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 733 }
 734
 735 static void cpt_set_infoframes(struct drm_encoder *encoder,
 736                                bool enable,
 737                                const struct intel_crtc_state *crtc_state,
 738                                const struct drm_connector_state *conn_state)
 739 {
 740         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 742         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 743         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 744         u32 val = I915_READ(reg);
 745
 746         assert_hdmi_port_disabled(intel_hdmi);
 747
 748         /* See the big comment in g4x_set_infoframes() */
 749         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 750
 751         if (!enable) {
 752                 if (!(val & VIDEO_DIP_ENABLE))
 753                         return;
 754                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 755                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 756                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 757                 I915_WRITE(reg, val);
 758                 POSTING_READ(reg);
 759                 return;
 760         }
 761
 762         /* Set both together, unset both together: see the spec. */
 763         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 764         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 765                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 766
 767         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 768                 val |= VIDEO_DIP_ENABLE_GCP;
 769
 770         I915_WRITE(reg, val);
 771         POSTING_READ(reg);
 772
 773         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 774         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 775         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 776 }
 777
 778 static void vlv_set_infoframes(struct drm_encoder *encoder,
 779                                bool enable,
 780                                const struct intel_crtc_state *crtc_state,
 781                                const struct drm_connector_state *conn_state)
 782 {
 783         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 784         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 786         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 787         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 788         u32 val = I915_READ(reg);
 789         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 790
 791         assert_hdmi_port_disabled(intel_hdmi);
 792
 793         /* See the big comment in g4x_set_infoframes() */
 794         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 795
 796         if (!enable) {
 797                 if (!(val & VIDEO_DIP_ENABLE))
 798                         return;
 799                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 800                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 801                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 802                 I915_WRITE(reg, val);
 803                 POSTING_READ(reg);
 804                 return;
 805         }
 806
 807         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 808                 WARN(val & VIDEO_DIP_ENABLE,
 809                      "DIP already enabled on port %c\n",
 810                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 811                 val &= ~VIDEO_DIP_PORT_MASK;
 812                 val |= port;
 813         }
 814
 815         val |= VIDEO_DIP_ENABLE;
 816         val &= ~(VIDEO_DIP_ENABLE_AVI |
 817                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 818                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 819
 820         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 821                 val |= VIDEO_DIP_ENABLE_GCP;
 822
 823         I915_WRITE(reg, val);
 824         POSTING_READ(reg);
 825
 826         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 827         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 828         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 829 }
 830
 831 static void hsw_set_infoframes(struct drm_encoder *encoder,
 832                                bool enable,
 833                                const struct intel_crtc_state *crtc_state,
 834                                const struct drm_connector_state *conn_state)
 835 {
 836         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 837         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 838         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 839         u32 val = I915_READ(reg);
 840
 841         assert_hdmi_port_disabled(intel_hdmi);
 842
 843         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 844                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 845                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 846
 847         if (!enable) {
 848                 I915_WRITE(reg, val);
 849                 POSTING_READ(reg);
 850                 return;
 851         }
 852
 853         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 854                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 855
 856         I915_WRITE(reg, val);
 857         POSTING_READ(reg);
 858
 859         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 860         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 861         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 862 }
 863
 864 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 865 {
 866         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 867         struct i2c_adapter *adapter =
 868                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 869
 870         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 871                 return;
 872
 873         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 874                       enable ? "Enabling" : "Disabling");
 875
 876         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 877                                          adapter, enable);
 878 }
 879
 880 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
 881                                 unsigned int offset, void *buffer, size_t size)
 882 {
 883         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 884         struct drm_i915_private *dev_priv =
 885                 intel_dig_port->base.base.dev->dev_private;
 886         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 887                                                               hdmi->ddc_bus);
 888         int ret;
 889         u8 start = offset & 0xff;
 890         struct i2c_msg msgs[] = {
 891                 {
 892                         .addr = DRM_HDCP_DDC_ADDR,
 893                         .flags = 0,
 894                         .len = 1,
 895                         .buf = &start,
 896                 },
 897                 {
 898                         .addr = DRM_HDCP_DDC_ADDR,
 899                         .flags = I2C_M_RD,
 900                         .len = size,
 901                         .buf = buffer
 902                 }
 903         };
 904         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
 905         if (ret == ARRAY_SIZE(msgs))
 906                 return 0;
 907         return ret >= 0 ? -EIO : ret;
 908 }
 909
 910 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
 911                                  unsigned int offset, void *buffer, size_t size)
 912 {
 913         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 914         struct drm_i915_private *dev_priv =
 915                 intel_dig_port->base.base.dev->dev_private;
 916         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 917                                                               hdmi->ddc_bus);
 918         int ret;
 919         u8 *write_buf;
 920         struct i2c_msg msg;
 921
 922         write_buf = kzalloc(size + 1, GFP_KERNEL);
 923         if (!write_buf)
 924                 return -ENOMEM;
 925
 926         write_buf[0] = offset & 0xff;
 927         memcpy(&write_buf[1], buffer, size);
 928
 929         msg.addr = DRM_HDCP_DDC_ADDR;
 930         msg.flags = 0,
 931         msg.len = size + 1,
 932         msg.buf = write_buf;
 933
 934         ret = i2c_transfer(adapter, &msg, 1);
 935         if (ret == 1)
 936                 return 0;
 937         return ret >= 0 ? -EIO : ret;
 938 }
 939
 940 static
 941 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
 942                                   u8 *an)
 943 {
 944         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 945         struct drm_i915_private *dev_priv =
 946                 intel_dig_port->base.base.dev->dev_private;
 947         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 948                                                               hdmi->ddc_bus);
 949         int ret;
 950
 951         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
 952                                     DRM_HDCP_AN_LEN);
 953         if (ret) {
 954                 DRM_ERROR("Write An over DDC failed (%d)\n", ret);
 955                 return ret;
 956         }
 957
 958         ret = intel_gmbus_output_aksv(adapter);
 959         if (ret < 0) {
 960                 DRM_ERROR("Failed to output aksv (%d)\n", ret);
 961                 return ret;
 962         }
 963         return 0;
 964 }
 965
 966 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
 967                                      u8 *bksv)
 968 {
 969         int ret;
 970         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
 971                                    DRM_HDCP_KSV_LEN);
 972         if (ret)
 973                 DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret);
 974         return ret;
 975 }
 976
 977 static
 978 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
 979                                  u8 *bstatus)
 980 {
 981         int ret;
 982         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
 983                                    bstatus, DRM_HDCP_BSTATUS_LEN);
 984         if (ret)
 985                 DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret);
 986         return ret;
 987 }
 988
 989 static
 990 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
 991                                      bool *repeater_present)
 992 {
 993         int ret;
 994         u8 val;
 995
 996         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
 997         if (ret) {
 998                 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
 999                 return ret;
1000         }
1001         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1002         return 0;
1003 }
1004
1005 static
1006 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1007                                   u8 *ri_prime)
1008 {
1009         int ret;
1010         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1011                                    ri_prime, DRM_HDCP_RI_LEN);
1012         if (ret)
1013                 DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret);
1014         return ret;
1015 }
1016
1017 static
1018 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1019                                    bool *ksv_ready)
1020 {
1021         int ret;
1022         u8 val;
1023
1024         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1025         if (ret) {
1026                 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1027                 return ret;
1028         }
1029         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1030         return 0;
1031 }
1032
1033 static
1034 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1035                                   int num_downstream, u8 *ksv_fifo)
1036 {
1037         int ret;
1038         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1039                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1040         if (ret) {
1041                 DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret);
1042                 return ret;
1043         }
1044         return 0;
1045 }
1046
1047 static
1048 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1049                                       int i, u32 *part)
1050 {
1051         int ret;
1052
1053         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1054                 return -EINVAL;
1055
1056         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1057                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1058         if (ret)
1059                 DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret);
1060         return ret;
1061 }
1062
1063 static
1064 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1065                                       bool enable)
1066 {
1067         int ret;
1068
1069         if (!enable)
1070                 usleep_range(6, 60); /* Bspec says >= 6us */
1071
1072         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1073         if (ret) {
1074                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1075                           enable ? "Enable" : "Disable", ret);
1076                 return ret;
1077         }
1078         return 0;
1079 }
1080
1081 static
1082 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1083 {
1084         struct drm_i915_private *dev_priv =
1085                 intel_dig_port->base.base.dev->dev_private;
1086         enum port port = intel_dig_port->base.port;
1087         int ret;
1088         union {
1089                 u32 reg;
1090                 u8 shim[DRM_HDCP_RI_LEN];
1091         } ri;
1092
1093         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1094         if (ret)
1095                 return false;
1096
1097         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1098
1099         /* Wait for Ri prime match */
1100         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1101                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1102                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1103                           I915_READ(PORT_HDCP_STATUS(port)));
1104                 return false;
1105         }
1106         return true;
1107 }
1108
1109 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1110         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1111         .read_bksv = intel_hdmi_hdcp_read_bksv,
1112         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1113         .repeater_present = intel_hdmi_hdcp_repeater_present,
1114         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1115         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1116         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1117         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1118         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1119         .check_link = intel_hdmi_hdcp_check_link,
1120 };
1121
1122 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1123                                const struct intel_crtc_state *crtc_state)
1124 {
1125         struct drm_device *dev = encoder->base.dev;
1126         struct drm_i915_private *dev_priv = to_i915(dev);
1127         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1128         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1129         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1130         u32 hdmi_val;
1131
1132         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1133
1134         hdmi_val = SDVO_ENCODING_HDMI;
1135         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1136                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1137         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1138                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1139         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1140                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1141
1142         if (crtc_state->pipe_bpp > 24)
1143                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1144         else
1145                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1146
1147         if (crtc_state->has_hdmi_sink)
1148                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1149
1150         if (HAS_PCH_CPT(dev_priv))
1151                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1152         else if (IS_CHERRYVIEW(dev_priv))
1153                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1154         else
1155                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1156
1157         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1158         POSTING_READ(intel_hdmi->hdmi_reg);
1159 }
1160
1161 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1162                                     enum pipe *pipe)
1163 {
1164         struct drm_device *dev = encoder->base.dev;
1165         struct drm_i915_private *dev_priv = to_i915(dev);
1166         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1167         u32 tmp;
1168         bool ret;
1169
1170         if (!intel_display_power_get_if_enabled(dev_priv,
1171                                                 encoder->power_domain))
1172                 return false;
1173
1174         ret = false;
1175
1176         tmp = I915_READ(intel_hdmi->hdmi_reg);
1177
1178         if (!(tmp & SDVO_ENABLE))
1179                 goto out;
1180
1181         if (HAS_PCH_CPT(dev_priv))
1182                 *pipe = PORT_TO_PIPE_CPT(tmp);
1183         else if (IS_CHERRYVIEW(dev_priv))
1184                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
1185         else
1186                 *pipe = PORT_TO_PIPE(tmp);
1187
1188         ret = true;
1189
1190 out:
1191         intel_display_power_put(dev_priv, encoder->power_domain);
1192
1193         return ret;
1194 }
1195
1196 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1197                                   struct intel_crtc_state *pipe_config)
1198 {
1199         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1200         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1201         struct drm_device *dev = encoder->base.dev;
1202         struct drm_i915_private *dev_priv = to_i915(dev);
1203         u32 tmp, flags = 0;
1204         int dotclock;
1205
1206         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1207
1208         tmp = I915_READ(intel_hdmi->hdmi_reg);
1209
1210         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1211                 flags |= DRM_MODE_FLAG_PHSYNC;
1212         else
1213                 flags |= DRM_MODE_FLAG_NHSYNC;
1214
1215         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1216                 flags |= DRM_MODE_FLAG_PVSYNC;
1217         else
1218                 flags |= DRM_MODE_FLAG_NVSYNC;
1219
1220         if (tmp & HDMI_MODE_SELECT_HDMI)
1221                 pipe_config->has_hdmi_sink = true;
1222
1223         if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
1224                 pipe_config->has_infoframe = true;
1225
1226         if (tmp & SDVO_AUDIO_ENABLE)
1227                 pipe_config->has_audio = true;
1228
1229         if (!HAS_PCH_SPLIT(dev_priv) &&
1230             tmp & HDMI_COLOR_RANGE_16_235)
1231                 pipe_config->limited_color_range = true;
1232
1233         pipe_config->base.adjusted_mode.flags |= flags;
1234
1235         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1236                 dotclock = pipe_config->port_clock * 2 / 3;
1237         else
1238                 dotclock = pipe_config->port_clock;
1239
1240         if (pipe_config->pixel_multiplier)
1241                 dotclock /= pipe_config->pixel_multiplier;
1242
1243         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1244
1245         pipe_config->lane_count = 4;
1246 }
1247
1248 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1249                                     const struct intel_crtc_state *pipe_config,
1250                                     const struct drm_connector_state *conn_state)
1251 {
1252         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1253
1254         WARN_ON(!pipe_config->has_hdmi_sink);
1255         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1256                          pipe_name(crtc->pipe));
1257         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1258 }
1259
1260 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1261                             const struct intel_crtc_state *pipe_config,
1262                             const struct drm_connector_state *conn_state)
1263 {
1264         struct drm_device *dev = encoder->base.dev;
1265         struct drm_i915_private *dev_priv = to_i915(dev);
1266         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1267         u32 temp;
1268
1269         temp = I915_READ(intel_hdmi->hdmi_reg);
1270
1271         temp |= SDVO_ENABLE;
1272         if (pipe_config->has_audio)
1273                 temp |= SDVO_AUDIO_ENABLE;
1274
1275         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1276         POSTING_READ(intel_hdmi->hdmi_reg);
1277
1278         if (pipe_config->has_audio)
1279                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1280 }
1281
1282 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1283                             const struct intel_crtc_state *pipe_config,
1284                             const struct drm_connector_state *conn_state)
1285 {
1286         struct drm_device *dev = encoder->base.dev;
1287         struct drm_i915_private *dev_priv = to_i915(dev);
1288         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1289         u32 temp;
1290
1291         temp = I915_READ(intel_hdmi->hdmi_reg);
1292
1293         temp |= SDVO_ENABLE;
1294         if (pipe_config->has_audio)
1295                 temp |= SDVO_AUDIO_ENABLE;
1296
1297         /*
1298          * HW workaround, need to write this twice for issue
1299          * that may result in first write getting masked.
1300          */
1301         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1302         POSTING_READ(intel_hdmi->hdmi_reg);
1303         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1304         POSTING_READ(intel_hdmi->hdmi_reg);
1305
1306         /*
1307          * HW workaround, need to toggle enable bit off and on
1308          * for 12bpc with pixel repeat.
1309          *
1310          * FIXME: BSpec says this should be done at the end of
1311          * of the modeset sequence, so not sure if this isn't too soon.
1312          */
1313         if (pipe_config->pipe_bpp > 24 &&
1314             pipe_config->pixel_multiplier > 1) {
1315                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1316                 POSTING_READ(intel_hdmi->hdmi_reg);
1317
1318                 /*
1319                  * HW workaround, need to write this twice for issue
1320                  * that may result in first write getting masked.
1321                  */
1322                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1323                 POSTING_READ(intel_hdmi->hdmi_reg);
1324                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1325                 POSTING_READ(intel_hdmi->hdmi_reg);
1326         }
1327
1328         if (pipe_config->has_audio)
1329                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1330 }
1331
1332 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1333                             const struct intel_crtc_state *pipe_config,
1334                             const struct drm_connector_state *conn_state)
1335 {
1336         struct drm_device *dev = encoder->base.dev;
1337         struct drm_i915_private *dev_priv = to_i915(dev);
1338         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1339         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1340         enum pipe pipe = crtc->pipe;
1341         u32 temp;
1342
1343         temp = I915_READ(intel_hdmi->hdmi_reg);
1344
1345         temp |= SDVO_ENABLE;
1346         if (pipe_config->has_audio)
1347                 temp |= SDVO_AUDIO_ENABLE;
1348
1349         /*
1350          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1351          *
1352          * The procedure for 12bpc is as follows:
1353          * 1. disable HDMI clock gating
1354          * 2. enable HDMI with 8bpc
1355          * 3. enable HDMI with 12bpc
1356          * 4. enable HDMI clock gating
1357          */
1358
1359         if (pipe_config->pipe_bpp > 24) {
1360                 I915_WRITE(TRANS_CHICKEN1(pipe),
1361                            I915_READ(TRANS_CHICKEN1(pipe)) |
1362                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1363
1364                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1365                 temp |= SDVO_COLOR_FORMAT_8bpc;
1366         }
1367
1368         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1369         POSTING_READ(intel_hdmi->hdmi_reg);
1370
1371         if (pipe_config->pipe_bpp > 24) {
1372                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1373                 temp |= HDMI_COLOR_FORMAT_12bpc;
1374
1375                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1376                 POSTING_READ(intel_hdmi->hdmi_reg);
1377
1378                 I915_WRITE(TRANS_CHICKEN1(pipe),
1379                            I915_READ(TRANS_CHICKEN1(pipe)) &
1380                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1381         }
1382
1383         if (pipe_config->has_audio)
1384                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1385 }
1386
1387 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1388                             const struct intel_crtc_state *pipe_config,
1389                             const struct drm_connector_state *conn_state)
1390 {
1391 }
1392
1393 static void intel_disable_hdmi(struct intel_encoder *encoder,
1394                                const struct intel_crtc_state *old_crtc_state,
1395                                const struct drm_connector_state *old_conn_state)
1396 {
1397         struct drm_device *dev = encoder->base.dev;
1398         struct drm_i915_private *dev_priv = to_i915(dev);
1399         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1400         struct intel_digital_port *intel_dig_port =
1401                 hdmi_to_dig_port(intel_hdmi);
1402         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1403         u32 temp;
1404
1405         temp = I915_READ(intel_hdmi->hdmi_reg);
1406
1407         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1408         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1409         POSTING_READ(intel_hdmi->hdmi_reg);
1410
1411         /*
1412          * HW workaround for IBX, we need to move the port
1413          * to transcoder A after disabling it to allow the
1414          * matching DP port to be enabled on transcoder A.
1415          */
1416         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1417                 /*
1418                  * We get CPU/PCH FIFO underruns on the other pipe when
1419                  * doing the workaround. Sweep them under the rug.
1420                  */
1421                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1422                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1423
1424                 temp &= ~SDVO_PIPE_B_SELECT;
1425                 temp |= SDVO_ENABLE;
1426                 /*
1427                  * HW workaround, need to write this twice for issue
1428                  * that may result in first write getting masked.
1429                  */
1430                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1431                 POSTING_READ(intel_hdmi->hdmi_reg);
1432                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1433                 POSTING_READ(intel_hdmi->hdmi_reg);
1434
1435                 temp &= ~SDVO_ENABLE;
1436                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1437                 POSTING_READ(intel_hdmi->hdmi_reg);
1438
1439                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1440                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1441                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1442         }
1443
1444         intel_dig_port->set_infoframes(&encoder->base, false,
1445                                        old_crtc_state, old_conn_state);
1446
1447         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1448 }
1449
1450 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1451                              const struct intel_crtc_state *old_crtc_state,
1452                              const struct drm_connector_state *old_conn_state)
1453 {
1454         if (old_crtc_state->has_audio)
1455                 intel_audio_codec_disable(encoder,
1456                                           old_crtc_state, old_conn_state);
1457
1458         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1459 }
1460
1461 static void pch_disable_hdmi(struct intel_encoder *encoder,
1462                              const struct intel_crtc_state *old_crtc_state,
1463                              const struct drm_connector_state *old_conn_state)
1464 {
1465         if (old_crtc_state->has_audio)
1466                 intel_audio_codec_disable(encoder,
1467                                           old_crtc_state, old_conn_state);
1468 }
1469
1470 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1471                                   const struct intel_crtc_state *old_crtc_state,
1472                                   const struct drm_connector_state *old_conn_state)
1473 {
1474         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1475 }
1476
1477 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1478 {
1479         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1480         const struct ddi_vbt_port_info *info =
1481                 &dev_priv->vbt.ddi_port_info[encoder->port];
1482         int max_tmds_clock;
1483
1484         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1485                 max_tmds_clock = 594000;
1486         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1487                 max_tmds_clock = 300000;
1488         else if (INTEL_GEN(dev_priv) >= 5)
1489                 max_tmds_clock = 225000;
1490         else
1491                 max_tmds_clock = 165000;
1492
1493         if (info->max_tmds_clock)
1494                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1495
1496         return max_tmds_clock;
1497 }
1498
1499 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1500                                  bool respect_downstream_limits,
1501                                  bool force_dvi)
1502 {
1503         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1504         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1505
1506         if (respect_downstream_limits) {
1507                 struct intel_connector *connector = hdmi->attached_connector;
1508                 const struct drm_display_info *info = &connector->base.display_info;
1509
1510                 if (hdmi->dp_dual_mode.max_tmds_clock)
1511                         max_tmds_clock = min(max_tmds_clock,
1512                                              hdmi->dp_dual_mode.max_tmds_clock);
1513
1514                 if (info->max_tmds_clock)
1515                         max_tmds_clock = min(max_tmds_clock,
1516                                              info->max_tmds_clock);
1517                 else if (!hdmi->has_hdmi_sink || force_dvi)
1518                         max_tmds_clock = min(max_tmds_clock, 165000);
1519         }
1520
1521         return max_tmds_clock;
1522 }
1523
1524 static enum drm_mode_status
1525 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1526                       int clock, bool respect_downstream_limits,
1527                       bool force_dvi)
1528 {
1529         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1530
1531         if (clock < 25000)
1532                 return MODE_CLOCK_LOW;
1533         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1534                 return MODE_CLOCK_HIGH;
1535
1536         /* BXT DPLL can't generate 223-240 MHz */
1537         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1538                 return MODE_CLOCK_RANGE;
1539
1540         /* CHV DPLL can't generate 216-240 MHz */
1541         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1542                 return MODE_CLOCK_RANGE;
1543
1544         return MODE_OK;
1545 }
1546
1547 static enum drm_mode_status
1548 intel_hdmi_mode_valid(struct drm_connector *connector,
1549                       struct drm_display_mode *mode)
1550 {
1551         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1552         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1553         struct drm_i915_private *dev_priv = to_i915(dev);
1554         enum drm_mode_status status;
1555         int clock;
1556         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1557         bool force_dvi =
1558                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1559
1560         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1561                 return MODE_NO_DBLESCAN;
1562
1563         clock = mode->clock;
1564
1565         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1566                 clock *= 2;
1567
1568         if (clock > max_dotclk)
1569                 return MODE_CLOCK_HIGH;
1570
1571         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1572                 clock *= 2;
1573
1574         if (drm_mode_is_420_only(&connector->display_info, mode))
1575                 clock /= 2;
1576
1577         /* check if we can do 8bpc */
1578         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1579
1580         /* if we can't do 8bpc we may still be able to do 12bpc */
1581         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1582                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1583
1584         return status;
1585 }
1586
1587 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1588 {
1589         struct drm_i915_private *dev_priv =
1590                 to_i915(crtc_state->base.crtc->dev);
1591         struct drm_atomic_state *state = crtc_state->base.state;
1592         struct drm_connector_state *connector_state;
1593         struct drm_connector *connector;
1594         int i;
1595
1596         if (HAS_GMCH_DISPLAY(dev_priv))
1597                 return false;
1598
1599         if (crtc_state->pipe_bpp <= 8*3)
1600                 return false;
1601
1602         if (!crtc_state->has_hdmi_sink)
1603                 return false;
1604
1605         /*
1606          * HDMI 12bpc affects the clocks, so it's only possible
1607          * when not cloning with other encoder types.
1608          */
1609         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1610                 return false;
1611
1612         for_each_new_connector_in_state(state, connector, connector_state, i) {
1613                 const struct drm_display_info *info = &connector->display_info;
1614
1615                 if (connector_state->crtc != crtc_state->base.crtc)
1616                         continue;
1617
1618                 if (crtc_state->ycbcr420) {
1619                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1620
1621                         if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1622                                 return false;
1623                 } else {
1624                         if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1625                                 return false;
1626                 }
1627         }
1628
1629         /* Display WA #1139: glk */
1630         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1631             crtc_state->base.adjusted_mode.htotal > 5460)
1632                 return false;
1633
1634         return true;
1635 }
1636
1637 static bool
1638 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1639                            struct intel_crtc_state *config,
1640                            int *clock_12bpc, int *clock_8bpc)
1641 {
1642         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1643
1644         if (!connector->ycbcr_420_allowed) {
1645                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1646                 return false;
1647         }
1648
1649         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1650         config->port_clock /= 2;
1651         *clock_12bpc /= 2;
1652         *clock_8bpc /= 2;
1653         config->ycbcr420 = true;
1654
1655         /* YCBCR 420 output conversion needs a scaler */
1656         if (skl_update_scaler_crtc(config)) {
1657                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1658                 return false;
1659         }
1660
1661         intel_pch_panel_fitting(intel_crtc, config,
1662                                 DRM_MODE_SCALE_FULLSCREEN);
1663
1664         return true;
1665 }
1666
1667 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1668                                struct intel_crtc_state *pipe_config,
1669                                struct drm_connector_state *conn_state)
1670 {
1671         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1672         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1673         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1674         struct drm_connector *connector = conn_state->connector;
1675         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1676         struct intel_digital_connector_state *intel_conn_state =
1677                 to_intel_digital_connector_state(conn_state);
1678         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1679         int clock_12bpc = clock_8bpc * 3 / 2;
1680         int desired_bpp;
1681         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1682
1683         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1684                 return false;
1685
1686         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1687
1688         if (pipe_config->has_hdmi_sink)
1689                 pipe_config->has_infoframe = true;
1690
1691         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1692                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1693                 pipe_config->limited_color_range =
1694                         pipe_config->has_hdmi_sink &&
1695                         drm_default_rgb_quant_range(adjusted_mode) ==
1696                         HDMI_QUANTIZATION_RANGE_LIMITED;
1697         } else {
1698                 pipe_config->limited_color_range =
1699                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1700         }
1701
1702         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1703                 pipe_config->pixel_multiplier = 2;
1704                 clock_8bpc *= 2;
1705                 clock_12bpc *= 2;
1706         }
1707
1708         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1709                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1710                                                 &clock_12bpc, &clock_8bpc)) {
1711                         DRM_ERROR("Can't support YCBCR420 output\n");
1712                         return false;
1713                 }
1714         }
1715
1716         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1717                 pipe_config->has_pch_encoder = true;
1718
1719         if (pipe_config->has_hdmi_sink) {
1720                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1721                         pipe_config->has_audio = intel_hdmi->has_audio;
1722                 else
1723                         pipe_config->has_audio =
1724                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1725         }
1726
1727         /*
1728          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1729          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1730          * outputs. We also need to check that the higher clock still fits
1731          * within limits.
1732          */
1733         if (hdmi_12bpc_possible(pipe_config) &&
1734             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
1735                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1736                 desired_bpp = 12*3;
1737
1738                 /* Need to adjust the port link by 1.5x for 12bpc. */
1739                 pipe_config->port_clock = clock_12bpc;
1740         } else {
1741                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1742                 desired_bpp = 8*3;
1743
1744                 pipe_config->port_clock = clock_8bpc;
1745         }
1746
1747         if (!pipe_config->bw_constrained) {
1748                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1749                 pipe_config->pipe_bpp = desired_bpp;
1750         }
1751
1752         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1753                                   false, force_dvi) != MODE_OK) {
1754                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1755                 return false;
1756         }
1757
1758         /* Set user selected PAR to incoming mode's member */
1759         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1760
1761         pipe_config->lane_count = 4;
1762
1763         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1764                                            IS_GEMINILAKE(dev_priv))) {
1765                 if (scdc->scrambling.low_rates)
1766                         pipe_config->hdmi_scrambling = true;
1767
1768                 if (pipe_config->port_clock > 340000) {
1769                         pipe_config->hdmi_scrambling = true;
1770                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1771                 }
1772         }
1773
1774         return true;
1775 }
1776
1777 static void
1778 intel_hdmi_unset_edid(struct drm_connector *connector)
1779 {
1780         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1781
1782         intel_hdmi->has_hdmi_sink = false;
1783         intel_hdmi->has_audio = false;
1784         intel_hdmi->rgb_quant_range_selectable = false;
1785
1786         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1787         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1788
1789         kfree(to_intel_connector(connector)->detect_edid);
1790         to_intel_connector(connector)->detect_edid = NULL;
1791 }
1792
1793 static void
1794 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1795 {
1796         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1797         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1798         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1799         struct i2c_adapter *adapter =
1800                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1801         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1802
1803         /*
1804          * Type 1 DVI adaptors are not required to implement any
1805          * registers, so we can't always detect their presence.
1806          * Ideally we should be able to check the state of the
1807          * CONFIG1 pin, but no such luck on our hardware.
1808          *
1809          * The only method left to us is to check the VBT to see
1810          * if the port is a dual mode capable DP port. But let's
1811          * only do that when we sucesfully read the EDID, to avoid
1812          * confusing log messages about DP dual mode adaptors when
1813          * there's nothing connected to the port.
1814          */
1815         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1816                 /* An overridden EDID imply that we want this port for testing.
1817                  * Make sure not to set limits for that port.
1818                  */
1819                 if (has_edid && !connector->override_edid &&
1820                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1821                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1822                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1823                 } else {
1824                         type = DRM_DP_DUAL_MODE_NONE;
1825                 }
1826         }
1827
1828         if (type == DRM_DP_DUAL_MODE_NONE)
1829                 return;
1830
1831         hdmi->dp_dual_mode.type = type;
1832         hdmi->dp_dual_mode.max_tmds_clock =
1833                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1834
1835         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1836                       drm_dp_get_dual_mode_type_name(type),
1837                       hdmi->dp_dual_mode.max_tmds_clock);
1838 }
1839
1840 static bool
1841 intel_hdmi_set_edid(struct drm_connector *connector)
1842 {
1843         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1844         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1845         struct edid *edid;
1846         bool connected = false;
1847         struct i2c_adapter *i2c;
1848
1849         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1850
1851         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1852
1853         edid = drm_get_edid(connector, i2c);
1854
1855         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1856                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1857                 intel_gmbus_force_bit(i2c, true);
1858                 edid = drm_get_edid(connector, i2c);
1859                 intel_gmbus_force_bit(i2c, false);
1860         }
1861
1862         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1863
1864         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1865
1866         to_intel_connector(connector)->detect_edid = edid;
1867         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1868                 intel_hdmi->rgb_quant_range_selectable =
1869                         drm_rgb_quant_range_selectable(edid);
1870
1871                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1872                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1873
1874                 connected = true;
1875         }
1876
1877         return connected;
1878 }
1879
1880 static enum drm_connector_status
1881 intel_hdmi_detect(struct drm_connector *connector, bool force)
1882 {
1883         enum drm_connector_status status;
1884         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1885
1886         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1887                       connector->base.id, connector->name);
1888
1889         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1890
1891         intel_hdmi_unset_edid(connector);
1892
1893         if (intel_hdmi_set_edid(connector))
1894                 status = connector_status_connected;
1895         else
1896                 status = connector_status_disconnected;
1897
1898         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1899
1900         return status;
1901 }
1902
1903 static void
1904 intel_hdmi_force(struct drm_connector *connector)
1905 {
1906         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1907                       connector->base.id, connector->name);
1908
1909         intel_hdmi_unset_edid(connector);
1910
1911         if (connector->status != connector_status_connected)
1912                 return;
1913
1914         intel_hdmi_set_edid(connector);
1915 }
1916
1917 static int intel_hdmi_get_modes(struct drm_connector *connector)
1918 {
1919         struct edid *edid;
1920
1921         edid = to_intel_connector(connector)->detect_edid;
1922         if (edid == NULL)
1923                 return 0;
1924
1925         return intel_connector_update_modes(connector, edid);
1926 }
1927
1928 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1929                                   const struct intel_crtc_state *pipe_config,
1930                                   const struct drm_connector_state *conn_state)
1931 {
1932         struct intel_digital_port *intel_dig_port =
1933                 enc_to_dig_port(&encoder->base);
1934
1935         intel_hdmi_prepare(encoder, pipe_config);
1936
1937         intel_dig_port->set_infoframes(&encoder->base,
1938                                        pipe_config->has_infoframe,
1939                                        pipe_config, conn_state);
1940 }
1941
1942 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1943                                 const struct intel_crtc_state *pipe_config,
1944                                 const struct drm_connector_state *conn_state)
1945 {
1946         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1947         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1948
1949         vlv_phy_pre_encoder_enable(encoder, pipe_config);
1950
1951         /* HDMI 1.0V-2dB */
1952         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1953                                  0x2b247878);
1954
1955         dport->set_infoframes(&encoder->base,
1956                               pipe_config->has_infoframe,
1957                               pipe_config, conn_state);
1958
1959         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1960
1961         vlv_wait_port_ready(dev_priv, dport, 0x0);
1962 }
1963
1964 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1965                                     const struct intel_crtc_state *pipe_config,
1966                                     const struct drm_connector_state *conn_state)
1967 {
1968         intel_hdmi_prepare(encoder, pipe_config);
1969
1970         vlv_phy_pre_pll_enable(encoder, pipe_config);
1971 }
1972
1973 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1974                                     const struct intel_crtc_state *pipe_config,
1975                                     const struct drm_connector_state *conn_state)
1976 {
1977         intel_hdmi_prepare(encoder, pipe_config);
1978
1979         chv_phy_pre_pll_enable(encoder, pipe_config);
1980 }
1981
1982 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1983                                       const struct intel_crtc_state *old_crtc_state,
1984                                       const struct drm_connector_state *old_conn_state)
1985 {
1986         chv_phy_post_pll_disable(encoder, old_crtc_state);
1987 }
1988
1989 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1990                                   const struct intel_crtc_state *old_crtc_state,
1991                                   const struct drm_connector_state *old_conn_state)
1992 {
1993         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1994         vlv_phy_reset_lanes(encoder, old_crtc_state);
1995 }
1996
1997 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1998                                   const struct intel_crtc_state *old_crtc_state,
1999                                   const struct drm_connector_state *old_conn_state)
2000 {
2001         struct drm_device *dev = encoder->base.dev;
2002         struct drm_i915_private *dev_priv = to_i915(dev);
2003
2004         mutex_lock(&dev_priv->sb_lock);
2005
2006         /* Assert data lane reset */
2007         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2008
2009         mutex_unlock(&dev_priv->sb_lock);
2010 }
2011
2012 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2013                                 const struct intel_crtc_state *pipe_config,
2014                                 const struct drm_connector_state *conn_state)
2015 {
2016         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2017         struct drm_device *dev = encoder->base.dev;
2018         struct drm_i915_private *dev_priv = to_i915(dev);
2019
2020         chv_phy_pre_encoder_enable(encoder, pipe_config);
2021
2022         /* FIXME: Program the support xxx V-dB */
2023         /* Use 800mV-0dB */
2024         chv_set_phy_signal_level(encoder, 128, 102, false);
2025
2026         dport->set_infoframes(&encoder->base,
2027                               pipe_config->has_infoframe,
2028                               pipe_config, conn_state);
2029
2030         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2031
2032         vlv_wait_port_ready(dev_priv, dport, 0x0);
2033
2034         /* Second common lane will stay alive on its own now */
2035         chv_phy_release_cl2_override(encoder);
2036 }
2037
2038 static void intel_hdmi_destroy(struct drm_connector *connector)
2039 {
2040         kfree(to_intel_connector(connector)->detect_edid);
2041         drm_connector_cleanup(connector);
2042         kfree(connector);
2043 }
2044
2045 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2046         .detect = intel_hdmi_detect,
2047         .force = intel_hdmi_force,
2048         .fill_modes = drm_helper_probe_single_connector_modes,
2049         .atomic_get_property = intel_digital_connector_atomic_get_property,
2050         .atomic_set_property = intel_digital_connector_atomic_set_property,
2051         .late_register = intel_connector_register,
2052         .early_unregister = intel_connector_unregister,
2053         .destroy = intel_hdmi_destroy,
2054         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2055         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2056 };
2057
2058 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2059         .get_modes = intel_hdmi_get_modes,
2060         .mode_valid = intel_hdmi_mode_valid,
2061         .atomic_check = intel_digital_connector_atomic_check,
2062 };
2063
2064 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2065         .destroy = intel_encoder_destroy,
2066 };
2067
2068 static void
2069 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2070 {
2071         intel_attach_force_audio_property(connector);
2072         intel_attach_broadcast_rgb_property(connector);
2073         intel_attach_aspect_ratio_property(connector);
2074         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2075 }
2076
2077 /*
2078  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2079  * @encoder: intel_encoder
2080  * @connector: drm_connector
2081  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2082  *  or reset the high tmds clock ratio for scrambling
2083  * @scrambling: bool to Indicate if the function needs to set or reset
2084  *  sink scrambling
2085  *
2086  * This function handles scrambling on HDMI 2.0 capable sinks.
2087  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2088  * it enables scrambling. This should be called before enabling the HDMI
2089  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2090  * detect a scrambled clock within 100 ms.
2091  *
2092  * Returns:
2093  * True on success, false on failure.
2094  */
2095 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2096                                        struct drm_connector *connector,
2097                                        bool high_tmds_clock_ratio,
2098                                        bool scrambling)
2099 {
2100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2101         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2102         struct drm_scrambling *sink_scrambling =
2103                 &connector->display_info.hdmi.scdc.scrambling;
2104         struct i2c_adapter *adapter =
2105                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2106
2107         if (!sink_scrambling->supported)
2108                 return true;
2109
2110         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2111                       connector->base.id, connector->name,
2112                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2113
2114         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2115         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2116                                                   high_tmds_clock_ratio) &&
2117                 drm_scdc_set_scrambling(adapter, scrambling);
2118 }
2119
2120 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2121 {
2122         u8 ddc_pin;
2123
2124         switch (port) {
2125         case PORT_B:
2126                 ddc_pin = GMBUS_PIN_DPB;
2127                 break;
2128         case PORT_C:
2129                 ddc_pin = GMBUS_PIN_DPC;
2130                 break;
2131         case PORT_D:
2132                 ddc_pin = GMBUS_PIN_DPD_CHV;
2133                 break;
2134         default:
2135                 MISSING_CASE(port);
2136                 ddc_pin = GMBUS_PIN_DPB;
2137                 break;
2138         }
2139         return ddc_pin;
2140 }
2141
2142 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2143 {
2144         u8 ddc_pin;
2145
2146         switch (port) {
2147         case PORT_B:
2148                 ddc_pin = GMBUS_PIN_1_BXT;
2149                 break;
2150         case PORT_C:
2151                 ddc_pin = GMBUS_PIN_2_BXT;
2152                 break;
2153         default:
2154                 MISSING_CASE(port);
2155                 ddc_pin = GMBUS_PIN_1_BXT;
2156                 break;
2157         }
2158         return ddc_pin;
2159 }
2160
2161 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2162                               enum port port)
2163 {
2164         u8 ddc_pin;
2165
2166         switch (port) {
2167         case PORT_B:
2168                 ddc_pin = GMBUS_PIN_1_BXT;
2169                 break;
2170         case PORT_C:
2171                 ddc_pin = GMBUS_PIN_2_BXT;
2172                 break;
2173         case PORT_D:
2174                 ddc_pin = GMBUS_PIN_4_CNP;
2175                 break;
2176         case PORT_F:
2177                 ddc_pin = GMBUS_PIN_3_BXT;
2178                 break;
2179         default:
2180                 MISSING_CASE(port);
2181                 ddc_pin = GMBUS_PIN_1_BXT;
2182                 break;
2183         }
2184         return ddc_pin;
2185 }
2186
2187 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2188 {
2189         u8 ddc_pin;
2190
2191         switch (port) {
2192         case PORT_A:
2193                 ddc_pin = GMBUS_PIN_1_BXT;
2194                 break;
2195         case PORT_B:
2196                 ddc_pin = GMBUS_PIN_2_BXT;
2197                 break;
2198         case PORT_C:
2199                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2200                 break;
2201         case PORT_D:
2202                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2203                 break;
2204         case PORT_E:
2205                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2206                 break;
2207         case PORT_F:
2208                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2209                 break;
2210         default:
2211                 MISSING_CASE(port);
2212                 ddc_pin = GMBUS_PIN_2_BXT;
2213                 break;
2214         }
2215         return ddc_pin;
2216 }
2217
2218 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2219                               enum port port)
2220 {
2221         u8 ddc_pin;
2222
2223         switch (port) {
2224         case PORT_B:
2225                 ddc_pin = GMBUS_PIN_DPB;
2226                 break;
2227         case PORT_C:
2228                 ddc_pin = GMBUS_PIN_DPC;
2229                 break;
2230         case PORT_D:
2231                 ddc_pin = GMBUS_PIN_DPD;
2232                 break;
2233         default:
2234                 MISSING_CASE(port);
2235                 ddc_pin = GMBUS_PIN_DPB;
2236                 break;
2237         }
2238         return ddc_pin;
2239 }
2240
2241 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2242                              enum port port)
2243 {
2244         const struct ddi_vbt_port_info *info =
2245                 &dev_priv->vbt.ddi_port_info[port];
2246         u8 ddc_pin;
2247
2248         if (info->alternate_ddc_pin) {
2249                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2250                               info->alternate_ddc_pin, port_name(port));
2251                 return info->alternate_ddc_pin;
2252         }
2253
2254         if (IS_CHERRYVIEW(dev_priv))
2255                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2256         else if (IS_GEN9_LP(dev_priv))
2257                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2258         else if (HAS_PCH_CNP(dev_priv))
2259                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2260         else if (IS_ICELAKE(dev_priv))
2261                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2262         else
2263                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2264
2265         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2266                       ddc_pin, port_name(port));
2267
2268         return ddc_pin;
2269 }
2270
2271 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2272 {
2273         struct drm_i915_private *dev_priv =
2274                 to_i915(intel_dig_port->base.base.dev);
2275
2276         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2277                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2278                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2279                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2280         } else if (IS_G4X(dev_priv)) {
2281                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2282                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2283                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2284         } else if (HAS_DDI(dev_priv)) {
2285                 intel_dig_port->write_infoframe = hsw_write_infoframe;
2286                 intel_dig_port->set_infoframes = hsw_set_infoframes;
2287                 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2288         } else if (HAS_PCH_IBX(dev_priv)) {
2289                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2290                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2291                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2292         } else {
2293                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2294                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2295                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2296         }
2297 }
2298
2299 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2300                                struct intel_connector *intel_connector)
2301 {
2302         struct drm_connector *connector = &intel_connector->base;
2303         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2304         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2305         struct drm_device *dev = intel_encoder->base.dev;
2306         struct drm_i915_private *dev_priv = to_i915(dev);
2307         enum port port = intel_encoder->port;
2308
2309         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2310                       port_name(port));
2311
2312         if (WARN(intel_dig_port->max_lanes < 4,
2313                  "Not enough lanes (%d) for HDMI on port %c\n",
2314                  intel_dig_port->max_lanes, port_name(port)))
2315                 return;
2316
2317         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2318                            DRM_MODE_CONNECTOR_HDMIA);
2319         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2320
2321         connector->interlace_allowed = 1;
2322         connector->doublescan_allowed = 0;
2323         connector->stereo_allowed = 1;
2324
2325         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2326                 connector->ycbcr_420_allowed = true;
2327
2328         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2329
2330         if (WARN_ON(port == PORT_A))
2331                 return;
2332         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2333
2334         if (HAS_DDI(dev_priv))
2335                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2336         else
2337                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2338
2339         intel_hdmi_add_properties(intel_hdmi, connector);
2340
2341         if (is_hdcp_supported(dev_priv, port)) {
2342                 int ret = intel_hdcp_init(intel_connector,
2343                                           &intel_hdmi_hdcp_shim);
2344                 if (ret)
2345                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2346         }
2347
2348         intel_connector_attach_encoder(intel_connector, intel_encoder);
2349         intel_hdmi->attached_connector = intel_connector;
2350
2351         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2352          * 0xd.  Failure to do so will result in spurious interrupts being
2353          * generated on the port when a cable is not attached.
2354          */
2355         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2356                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2357                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2358         }
2359 }
2360
2361 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2362                      i915_reg_t hdmi_reg, enum port port)
2363 {
2364         struct intel_digital_port *intel_dig_port;
2365         struct intel_encoder *intel_encoder;
2366         struct intel_connector *intel_connector;
2367
2368         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2369         if (!intel_dig_port)
2370                 return;
2371
2372         intel_connector = intel_connector_alloc();
2373         if (!intel_connector) {
2374                 kfree(intel_dig_port);
2375                 return;
2376         }
2377
2378         intel_encoder = &intel_dig_port->base;
2379
2380         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2381                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2382                          "HDMI %c", port_name(port));
2383
2384         intel_encoder->hotplug = intel_encoder_hotplug;
2385         intel_encoder->compute_config = intel_hdmi_compute_config;
2386         if (HAS_PCH_SPLIT(dev_priv)) {
2387                 intel_encoder->disable = pch_disable_hdmi;
2388                 intel_encoder->post_disable = pch_post_disable_hdmi;
2389         } else {
2390                 intel_encoder->disable = g4x_disable_hdmi;
2391         }
2392         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2393         intel_encoder->get_config = intel_hdmi_get_config;
2394         if (IS_CHERRYVIEW(dev_priv)) {
2395                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2396                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2397                 intel_encoder->enable = vlv_enable_hdmi;
2398                 intel_encoder->post_disable = chv_hdmi_post_disable;
2399                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2400         } else if (IS_VALLEYVIEW(dev_priv)) {
2401                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2402                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2403                 intel_encoder->enable = vlv_enable_hdmi;
2404                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2405         } else {
2406                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2407                 if (HAS_PCH_CPT(dev_priv))
2408                         intel_encoder->enable = cpt_enable_hdmi;
2409                 else if (HAS_PCH_IBX(dev_priv))
2410                         intel_encoder->enable = ibx_enable_hdmi;
2411                 else
2412                         intel_encoder->enable = g4x_enable_hdmi;
2413         }
2414
2415         intel_encoder->type = INTEL_OUTPUT_HDMI;
2416         intel_encoder->power_domain = intel_port_to_power_domain(port);
2417         intel_encoder->port = port;
2418         if (IS_CHERRYVIEW(dev_priv)) {
2419                 if (port == PORT_D)
2420                         intel_encoder->crtc_mask = 1 << 2;
2421                 else
2422                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2423         } else {
2424                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2425         }
2426         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2427         /*
2428          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2429          * to work on real hardware. And since g4x can send infoframes to
2430          * only one port anyway, nothing is lost by allowing it.
2431          */
2432         if (IS_G4X(dev_priv))
2433                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2434
2435         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2436         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2437         intel_dig_port->max_lanes = 4;
2438
2439         intel_infoframe_init(intel_dig_port);
2440
2441         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2442 }