drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include <drm/intel_lpe_audio.h>
  42 #include "i915_drv.h"
  43
  44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  45 {
  46         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  47 }
  48
  49 static void
  50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  51 {
  52         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  53         struct drm_i915_private *dev_priv = to_i915(dev);
  54         u32 enabled_bits;
  55
  56         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  57
  58         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  59              "HDMI port enabled, expecting disabled\n");
  60 }
  61
  62 static void
  63 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  64                                      enum transcoder cpu_transcoder)
  65 {
  66         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  67              TRANS_DDI_FUNC_ENABLE,
  68              "HDMI transcoder function enabled, expecting disabled\n");
  69 }
  70
  71 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  72 {
  73         struct intel_digital_port *intel_dig_port =
  74                 container_of(encoder, struct intel_digital_port, base.base);
  75         return &intel_dig_port->hdmi;
  76 }
  77
  78 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  79 {
  80         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  81 }
  82
  83 static u32 g4x_infoframe_index(unsigned int type)
  84 {
  85         switch (type) {
  86         case HDMI_INFOFRAME_TYPE_AVI:
  87                 return VIDEO_DIP_SELECT_AVI;
  88         case HDMI_INFOFRAME_TYPE_SPD:
  89                 return VIDEO_DIP_SELECT_SPD;
  90         case HDMI_INFOFRAME_TYPE_VENDOR:
  91                 return VIDEO_DIP_SELECT_VENDOR;
  92         default:
  93                 MISSING_CASE(type);
  94                 return 0;
  95         }
  96 }
  97
  98 static u32 g4x_infoframe_enable(unsigned int type)
  99 {
 100         switch (type) {
 101         case HDMI_INFOFRAME_TYPE_AVI:
 102                 return VIDEO_DIP_ENABLE_AVI;
 103         case HDMI_INFOFRAME_TYPE_SPD:
 104                 return VIDEO_DIP_ENABLE_SPD;
 105         case HDMI_INFOFRAME_TYPE_VENDOR:
 106                 return VIDEO_DIP_ENABLE_VENDOR;
 107         default:
 108                 MISSING_CASE(type);
 109                 return 0;
 110         }
 111 }
 112
 113 static u32 hsw_infoframe_enable(unsigned int type)
 114 {
 115         switch (type) {
 116         case DP_SDP_VSC:
 117                 return VIDEO_DIP_ENABLE_VSC_HSW;
 118         case DP_SDP_PPS:
 119                 return VDIP_ENABLE_PPS;
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return VIDEO_DIP_ENABLE_AVI_HSW;
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return VIDEO_DIP_ENABLE_SPD_HSW;
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return VIDEO_DIP_ENABLE_VS_HSW;
 126         default:
 127                 MISSING_CASE(type);
 128                 return 0;
 129         }
 130 }
 131
 132 static i915_reg_t
 133 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 134                  enum transcoder cpu_transcoder,
 135                  unsigned int type,
 136                  int i)
 137 {
 138         switch (type) {
 139         case DP_SDP_VSC:
 140                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 141         case DP_SDP_PPS:
 142                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 143         case HDMI_INFOFRAME_TYPE_AVI:
 144                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 145         case HDMI_INFOFRAME_TYPE_SPD:
 146                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 147         case HDMI_INFOFRAME_TYPE_VENDOR:
 148                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 149         default:
 150                 MISSING_CASE(type);
 151                 return INVALID_MMIO_REG;
 152         }
 153 }
 154
 155 static int hsw_dip_data_size(unsigned int type)
 156 {
 157         switch (type) {
 158         case DP_SDP_VSC:
 159                 return VIDEO_DIP_VSC_DATA_SIZE;
 160         case DP_SDP_PPS:
 161                 return VIDEO_DIP_PPS_DATA_SIZE;
 162         default:
 163                 return VIDEO_DIP_DATA_SIZE;
 164         }
 165 }
 166
 167 static void g4x_write_infoframe(struct intel_encoder *encoder,
 168                                 const struct intel_crtc_state *crtc_state,
 169                                 unsigned int type,
 170                                 const void *frame, ssize_t len)
 171 {
 172         const u32 *data = frame;
 173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 174         u32 val = I915_READ(VIDEO_DIP_CTL);
 175         int i;
 176
 177         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 178
 179         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 180         val |= g4x_infoframe_index(type);
 181
 182         val &= ~g4x_infoframe_enable(type);
 183
 184         I915_WRITE(VIDEO_DIP_CTL, val);
 185
 186         mmiowb();
 187         for (i = 0; i < len; i += 4) {
 188                 I915_WRITE(VIDEO_DIP_DATA, *data);
 189                 data++;
 190         }
 191         /* Write every possible data byte to force correct ECC calculation. */
 192         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 193                 I915_WRITE(VIDEO_DIP_DATA, 0);
 194         mmiowb();
 195
 196         val |= g4x_infoframe_enable(type);
 197         val &= ~VIDEO_DIP_FREQ_MASK;
 198         val |= VIDEO_DIP_FREQ_VSYNC;
 199
 200         I915_WRITE(VIDEO_DIP_CTL, val);
 201         POSTING_READ(VIDEO_DIP_CTL);
 202 }
 203
 204 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
 205                                   const struct intel_crtc_state *pipe_config)
 206 {
 207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 208         u32 val = I915_READ(VIDEO_DIP_CTL);
 209
 210         if ((val & VIDEO_DIP_ENABLE) == 0)
 211                 return false;
 212
 213         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 214                 return false;
 215
 216         return val & (VIDEO_DIP_ENABLE_AVI |
 217                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 218 }
 219
 220 static void ibx_write_infoframe(struct intel_encoder *encoder,
 221                                 const struct intel_crtc_state *crtc_state,
 222                                 unsigned int type,
 223                                 const void *frame, ssize_t len)
 224 {
 225         const u32 *data = frame;
 226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 228         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 229         u32 val = I915_READ(reg);
 230         int i;
 231
 232         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 233
 234         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 235         val |= g4x_infoframe_index(type);
 236
 237         val &= ~g4x_infoframe_enable(type);
 238
 239         I915_WRITE(reg, val);
 240
 241         mmiowb();
 242         for (i = 0; i < len; i += 4) {
 243                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 244                 data++;
 245         }
 246         /* Write every possible data byte to force correct ECC calculation. */
 247         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 248                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 249         mmiowb();
 250
 251         val |= g4x_infoframe_enable(type);
 252         val &= ~VIDEO_DIP_FREQ_MASK;
 253         val |= VIDEO_DIP_FREQ_VSYNC;
 254
 255         I915_WRITE(reg, val);
 256         POSTING_READ(reg);
 257 }
 258
 259 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
 260                                   const struct intel_crtc_state *pipe_config)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 264         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 265         u32 val = I915_READ(reg);
 266
 267         if ((val & VIDEO_DIP_ENABLE) == 0)
 268                 return false;
 269
 270         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 271                 return false;
 272
 273         return val & (VIDEO_DIP_ENABLE_AVI |
 274                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 275                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 276 }
 277
 278 static void cpt_write_infoframe(struct intel_encoder *encoder,
 279                                 const struct intel_crtc_state *crtc_state,
 280                                 unsigned int type,
 281                                 const void *frame, ssize_t len)
 282 {
 283         const u32 *data = frame;
 284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 286         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 287         u32 val = I915_READ(reg);
 288         int i;
 289
 290         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 291
 292         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 293         val |= g4x_infoframe_index(type);
 294
 295         /* The DIP control register spec says that we need to update the AVI
 296          * infoframe without clearing its enable bit */
 297         if (type != HDMI_INFOFRAME_TYPE_AVI)
 298                 val &= ~g4x_infoframe_enable(type);
 299
 300         I915_WRITE(reg, val);
 301
 302         mmiowb();
 303         for (i = 0; i < len; i += 4) {
 304                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 305                 data++;
 306         }
 307         /* Write every possible data byte to force correct ECC calculation. */
 308         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 309                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 310         mmiowb();
 311
 312         val |= g4x_infoframe_enable(type);
 313         val &= ~VIDEO_DIP_FREQ_MASK;
 314         val |= VIDEO_DIP_FREQ_VSYNC;
 315
 316         I915_WRITE(reg, val);
 317         POSTING_READ(reg);
 318 }
 319
 320 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
 321                                   const struct intel_crtc_state *pipe_config)
 322 {
 323         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 324         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 325         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 326
 327         if ((val & VIDEO_DIP_ENABLE) == 0)
 328                 return false;
 329
 330         return val & (VIDEO_DIP_ENABLE_AVI |
 331                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 332                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 333 }
 334
 335 static void vlv_write_infoframe(struct intel_encoder *encoder,
 336                                 const struct intel_crtc_state *crtc_state,
 337                                 unsigned int type,
 338                                 const void *frame, ssize_t len)
 339 {
 340         const u32 *data = frame;
 341         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 343         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 344         u32 val = I915_READ(reg);
 345         int i;
 346
 347         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 348
 349         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 350         val |= g4x_infoframe_index(type);
 351
 352         val &= ~g4x_infoframe_enable(type);
 353
 354         I915_WRITE(reg, val);
 355
 356         mmiowb();
 357         for (i = 0; i < len; i += 4) {
 358                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 359                 data++;
 360         }
 361         /* Write every possible data byte to force correct ECC calculation. */
 362         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 363                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 364         mmiowb();
 365
 366         val |= g4x_infoframe_enable(type);
 367         val &= ~VIDEO_DIP_FREQ_MASK;
 368         val |= VIDEO_DIP_FREQ_VSYNC;
 369
 370         I915_WRITE(reg, val);
 371         POSTING_READ(reg);
 372 }
 373
 374 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
 375                                   const struct intel_crtc_state *pipe_config)
 376 {
 377         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 378         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 379         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 380
 381         if ((val & VIDEO_DIP_ENABLE) == 0)
 382                 return false;
 383
 384         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 385                 return false;
 386
 387         return val & (VIDEO_DIP_ENABLE_AVI |
 388                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 389                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 390 }
 391
 392 static void hsw_write_infoframe(struct intel_encoder *encoder,
 393                                 const struct intel_crtc_state *crtc_state,
 394                                 unsigned int type,
 395                                 const void *frame, ssize_t len)
 396 {
 397         const u32 *data = frame;
 398         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 399         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 400         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 401         int data_size;
 402         int i;
 403         u32 val = I915_READ(ctl_reg);
 404
 405         data_size = hsw_dip_data_size(type);
 406
 407         val &= ~hsw_infoframe_enable(type);
 408         I915_WRITE(ctl_reg, val);
 409
 410         mmiowb();
 411         for (i = 0; i < len; i += 4) {
 412                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 413                                             type, i >> 2), *data);
 414                 data++;
 415         }
 416         /* Write every possible data byte to force correct ECC calculation. */
 417         for (; i < data_size; i += 4)
 418                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 419                                             type, i >> 2), 0);
 420         mmiowb();
 421
 422         val |= hsw_infoframe_enable(type);
 423         I915_WRITE(ctl_reg, val);
 424         POSTING_READ(ctl_reg);
 425 }
 426
 427 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
 428                                   const struct intel_crtc_state *pipe_config)
 429 {
 430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 431         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 432
 433         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 434                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 435                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 436 }
 437
 438 /*
 439  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 440  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 441  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 442  * used for both technologies.
 443  *
 444  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 445  * DW1:       DB3       | DB2 | DB1 | DB0
 446  * DW2:       DB7       | DB6 | DB5 | DB4
 447  * DW3: ...
 448  *
 449  * (HB is Header Byte, DB is Data Byte)
 450  *
 451  * The hdmi pack() functions don't know about that hardware specific hole so we
 452  * trick them by giving an offset into the buffer and moving back the header
 453  * bytes by one.
 454  */
 455 static void intel_write_infoframe(struct intel_encoder *encoder,
 456                                   const struct intel_crtc_state *crtc_state,
 457                                   union hdmi_infoframe *frame)
 458 {
 459         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 460         u8 buffer[VIDEO_DIP_DATA_SIZE];
 461         ssize_t len;
 462
 463         /* see comment above for the reason for this offset */
 464         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 465         if (len < 0)
 466                 return;
 467
 468         /* Insert the 'hole' (see big comment above) at position 3 */
 469         memmove(&buffer[0], &buffer[1], 3);
 470         buffer[3] = 0;
 471         len++;
 472
 473         intel_dig_port->write_infoframe(encoder,
 474                                         crtc_state,
 475                                         frame->any.type, buffer, len);
 476 }
 477
 478 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
 479                                          const struct intel_crtc_state *crtc_state,
 480                                          const struct drm_connector_state *conn_state)
 481 {
 482         const struct drm_display_mode *adjusted_mode =
 483                 &crtc_state->base.adjusted_mode;
 484         union hdmi_infoframe frame;
 485         int ret;
 486
 487         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 488                                                        conn_state->connector,
 489                                                        adjusted_mode);
 490         if (ret < 0) {
 491                 DRM_ERROR("couldn't fill AVI infoframe\n");
 492                 return;
 493         }
 494
 495         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 496                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 497         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 498                 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 499         else
 500                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 501
 502         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 503                                            conn_state->connector,
 504                                            adjusted_mode,
 505                                            crtc_state->limited_color_range ?
 506                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 507                                            HDMI_QUANTIZATION_RANGE_FULL);
 508
 509         drm_hdmi_avi_infoframe_content_type(&frame.avi,
 510                                             conn_state);
 511
 512         /* TODO: handle pixel repetition for YCBCR420 outputs */
 513         intel_write_infoframe(encoder, crtc_state,
 514                               &frame);
 515 }
 516
 517 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
 518                                          const struct intel_crtc_state *crtc_state)
 519 {
 520         union hdmi_infoframe frame;
 521         int ret;
 522
 523         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 524         if (ret < 0) {
 525                 DRM_ERROR("couldn't fill SPD infoframe\n");
 526                 return;
 527         }
 528
 529         frame.spd.sdi = HDMI_SPD_SDI_PC;
 530
 531         intel_write_infoframe(encoder, crtc_state,
 532                               &frame);
 533 }
 534
 535 static void
 536 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
 537                               const struct intel_crtc_state *crtc_state,
 538                               const struct drm_connector_state *conn_state)
 539 {
 540         union hdmi_infoframe frame;
 541         int ret;
 542
 543         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 544                                                           conn_state->connector,
 545                                                           &crtc_state->base.adjusted_mode);
 546         if (ret < 0)
 547                 return;
 548
 549         intel_write_infoframe(encoder, crtc_state,
 550                               &frame);
 551 }
 552
 553 static void g4x_set_infoframes(struct intel_encoder *encoder,
 554                                bool enable,
 555                                const struct intel_crtc_state *crtc_state,
 556                                const struct drm_connector_state *conn_state)
 557 {
 558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 559         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 560         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 561         i915_reg_t reg = VIDEO_DIP_CTL;
 562         u32 val = I915_READ(reg);
 563         u32 port = VIDEO_DIP_PORT(encoder->port);
 564
 565         assert_hdmi_port_disabled(intel_hdmi);
 566
 567         /* If the registers were not initialized yet, they might be zeroes,
 568          * which means we're selecting the AVI DIP and we're setting its
 569          * frequency to once. This seems to really confuse the HW and make
 570          * things stop working (the register spec says the AVI always needs to
 571          * be sent every VSync). So here we avoid writing to the register more
 572          * than we need and also explicitly select the AVI DIP and explicitly
 573          * set its frequency to every VSync. Avoiding to write it twice seems to
 574          * be enough to solve the problem, but being defensive shouldn't hurt us
 575          * either. */
 576         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 577
 578         if (!enable) {
 579                 if (!(val & VIDEO_DIP_ENABLE))
 580                         return;
 581                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 582                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 583                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 584                         return;
 585                 }
 586                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 587                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 588                 I915_WRITE(reg, val);
 589                 POSTING_READ(reg);
 590                 return;
 591         }
 592
 593         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 594                 if (val & VIDEO_DIP_ENABLE) {
 595                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 596                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 597                         return;
 598                 }
 599                 val &= ~VIDEO_DIP_PORT_MASK;
 600                 val |= port;
 601         }
 602
 603         val |= VIDEO_DIP_ENABLE;
 604         val &= ~(VIDEO_DIP_ENABLE_AVI |
 605                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 606
 607         I915_WRITE(reg, val);
 608         POSTING_READ(reg);
 609
 610         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 611         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 612         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 613 }
 614
 615 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 616 {
 617         struct drm_connector *connector = conn_state->connector;
 618
 619         /*
 620          * HDMI cloning is only supported on g4x which doesn't
 621          * support deep color or GCP infoframes anyway so no
 622          * need to worry about multiple HDMI sinks here.
 623          */
 624
 625         return connector->display_info.bpc > 8;
 626 }
 627
 628 /*
 629  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 630  *
 631  * From HDMI specification 1.4a:
 632  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 633  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 634  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 635  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 636  *   phase of 0
 637  */
 638 static bool gcp_default_phase_possible(int pipe_bpp,
 639                                        const struct drm_display_mode *mode)
 640 {
 641         unsigned int pixels_per_group;
 642
 643         switch (pipe_bpp) {
 644         case 30:
 645                 /* 4 pixels in 5 clocks */
 646                 pixels_per_group = 4;
 647                 break;
 648         case 36:
 649                 /* 2 pixels in 3 clocks */
 650                 pixels_per_group = 2;
 651                 break;
 652         case 48:
 653                 /* 1 pixel in 2 clocks */
 654                 pixels_per_group = 1;
 655                 break;
 656         default:
 657                 /* phase information not relevant for 8bpc */
 658                 return false;
 659         }
 660
 661         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 662                 mode->crtc_htotal % pixels_per_group == 0 &&
 663                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 664                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 665                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 666                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 667                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 668                  mode->crtc_htotal/2 % pixels_per_group == 0);
 669 }
 670
 671 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 672                                          const struct intel_crtc_state *crtc_state,
 673                                          const struct drm_connector_state *conn_state)
 674 {
 675         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 676         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 677         i915_reg_t reg;
 678         u32 val = 0;
 679
 680         if (HAS_DDI(dev_priv))
 681                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 682         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 683                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 684         else if (HAS_PCH_SPLIT(dev_priv))
 685                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 686         else
 687                 return false;
 688
 689         /* Indicate color depth whenever the sink supports deep color */
 690         if (hdmi_sink_is_deep_color(conn_state))
 691                 val |= GCP_COLOR_INDICATION;
 692
 693         /* Enable default_phase whenever the display mode is suitably aligned */
 694         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 695                                        &crtc_state->base.adjusted_mode))
 696                 val |= GCP_DEFAULT_PHASE_ENABLE;
 697
 698         I915_WRITE(reg, val);
 699
 700         return val != 0;
 701 }
 702
 703 static void ibx_set_infoframes(struct intel_encoder *encoder,
 704                                bool enable,
 705                                const struct intel_crtc_state *crtc_state,
 706                                const struct drm_connector_state *conn_state)
 707 {
 708         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 710         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 711         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 712         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 713         u32 val = I915_READ(reg);
 714         u32 port = VIDEO_DIP_PORT(encoder->port);
 715
 716         assert_hdmi_port_disabled(intel_hdmi);
 717
 718         /* See the big comment in g4x_set_infoframes() */
 719         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 720
 721         if (!enable) {
 722                 if (!(val & VIDEO_DIP_ENABLE))
 723                         return;
 724                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 725                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 726                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 727                 I915_WRITE(reg, val);
 728                 POSTING_READ(reg);
 729                 return;
 730         }
 731
 732         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 733                 WARN(val & VIDEO_DIP_ENABLE,
 734                      "DIP already enabled on port %c\n",
 735                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 736                 val &= ~VIDEO_DIP_PORT_MASK;
 737                 val |= port;
 738         }
 739
 740         val |= VIDEO_DIP_ENABLE;
 741         val &= ~(VIDEO_DIP_ENABLE_AVI |
 742                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 743                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 744
 745         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 746                 val |= VIDEO_DIP_ENABLE_GCP;
 747
 748         I915_WRITE(reg, val);
 749         POSTING_READ(reg);
 750
 751         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 752         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 753         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 754 }
 755
 756 static void cpt_set_infoframes(struct intel_encoder *encoder,
 757                                bool enable,
 758                                const struct intel_crtc_state *crtc_state,
 759                                const struct drm_connector_state *conn_state)
 760 {
 761         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 763         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 764         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 765         u32 val = I915_READ(reg);
 766
 767         assert_hdmi_port_disabled(intel_hdmi);
 768
 769         /* See the big comment in g4x_set_infoframes() */
 770         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 771
 772         if (!enable) {
 773                 if (!(val & VIDEO_DIP_ENABLE))
 774                         return;
 775                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 776                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 777                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 778                 I915_WRITE(reg, val);
 779                 POSTING_READ(reg);
 780                 return;
 781         }
 782
 783         /* Set both together, unset both together: see the spec. */
 784         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 785         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 786                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 787
 788         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 789                 val |= VIDEO_DIP_ENABLE_GCP;
 790
 791         I915_WRITE(reg, val);
 792         POSTING_READ(reg);
 793
 794         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 795         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 796         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 797 }
 798
 799 static void vlv_set_infoframes(struct intel_encoder *encoder,
 800                                bool enable,
 801                                const struct intel_crtc_state *crtc_state,
 802                                const struct drm_connector_state *conn_state)
 803 {
 804         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 806         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 807         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 808         u32 val = I915_READ(reg);
 809         u32 port = VIDEO_DIP_PORT(encoder->port);
 810
 811         assert_hdmi_port_disabled(intel_hdmi);
 812
 813         /* See the big comment in g4x_set_infoframes() */
 814         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 815
 816         if (!enable) {
 817                 if (!(val & VIDEO_DIP_ENABLE))
 818                         return;
 819                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 820                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 821                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 822                 I915_WRITE(reg, val);
 823                 POSTING_READ(reg);
 824                 return;
 825         }
 826
 827         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 828                 WARN(val & VIDEO_DIP_ENABLE,
 829                      "DIP already enabled on port %c\n",
 830                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 831                 val &= ~VIDEO_DIP_PORT_MASK;
 832                 val |= port;
 833         }
 834
 835         val |= VIDEO_DIP_ENABLE;
 836         val &= ~(VIDEO_DIP_ENABLE_AVI |
 837                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 838                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 839
 840         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 841                 val |= VIDEO_DIP_ENABLE_GCP;
 842
 843         I915_WRITE(reg, val);
 844         POSTING_READ(reg);
 845
 846         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 847         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 848         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 849 }
 850
 851 static void hsw_set_infoframes(struct intel_encoder *encoder,
 852                                bool enable,
 853                                const struct intel_crtc_state *crtc_state,
 854                                const struct drm_connector_state *conn_state)
 855 {
 856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 857         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 858         u32 val = I915_READ(reg);
 859
 860         assert_hdmi_transcoder_func_disabled(dev_priv,
 861                                              crtc_state->cpu_transcoder);
 862
 863         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 864                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 865                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 866
 867         if (!enable) {
 868                 I915_WRITE(reg, val);
 869                 POSTING_READ(reg);
 870                 return;
 871         }
 872
 873         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 874                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 875
 876         I915_WRITE(reg, val);
 877         POSTING_READ(reg);
 878
 879         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 880         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 881         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 882 }
 883
 884 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 885 {
 886         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 887         struct i2c_adapter *adapter =
 888                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 889
 890         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 891                 return;
 892
 893         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 894                       enable ? "Enabling" : "Disabling");
 895
 896         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 897                                          adapter, enable);
 898 }
 899
 900 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
 901                                 unsigned int offset, void *buffer, size_t size)
 902 {
 903         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 904         struct drm_i915_private *dev_priv =
 905                 intel_dig_port->base.base.dev->dev_private;
 906         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 907                                                               hdmi->ddc_bus);
 908         int ret;
 909         u8 start = offset & 0xff;
 910         struct i2c_msg msgs[] = {
 911                 {
 912                         .addr = DRM_HDCP_DDC_ADDR,
 913                         .flags = 0,
 914                         .len = 1,
 915                         .buf = &start,
 916                 },
 917                 {
 918                         .addr = DRM_HDCP_DDC_ADDR,
 919                         .flags = I2C_M_RD,
 920                         .len = size,
 921                         .buf = buffer
 922                 }
 923         };
 924         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
 925         if (ret == ARRAY_SIZE(msgs))
 926                 return 0;
 927         return ret >= 0 ? -EIO : ret;
 928 }
 929
 930 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
 931                                  unsigned int offset, void *buffer, size_t size)
 932 {
 933         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 934         struct drm_i915_private *dev_priv =
 935                 intel_dig_port->base.base.dev->dev_private;
 936         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 937                                                               hdmi->ddc_bus);
 938         int ret;
 939         u8 *write_buf;
 940         struct i2c_msg msg;
 941
 942         write_buf = kzalloc(size + 1, GFP_KERNEL);
 943         if (!write_buf)
 944                 return -ENOMEM;
 945
 946         write_buf[0] = offset & 0xff;
 947         memcpy(&write_buf[1], buffer, size);
 948
 949         msg.addr = DRM_HDCP_DDC_ADDR;
 950         msg.flags = 0,
 951         msg.len = size + 1,
 952         msg.buf = write_buf;
 953
 954         ret = i2c_transfer(adapter, &msg, 1);
 955         if (ret == 1)
 956                 ret = 0;
 957         else if (ret >= 0)
 958                 ret = -EIO;
 959
 960         kfree(write_buf);
 961         return ret;
 962 }
 963
 964 static
 965 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
 966                                   u8 *an)
 967 {
 968         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 969         struct drm_i915_private *dev_priv =
 970                 intel_dig_port->base.base.dev->dev_private;
 971         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 972                                                               hdmi->ddc_bus);
 973         int ret;
 974
 975         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
 976                                     DRM_HDCP_AN_LEN);
 977         if (ret) {
 978                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
 979                 return ret;
 980         }
 981
 982         ret = intel_gmbus_output_aksv(adapter);
 983         if (ret < 0) {
 984                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
 985                 return ret;
 986         }
 987         return 0;
 988 }
 989
 990 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
 991                                      u8 *bksv)
 992 {
 993         int ret;
 994         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
 995                                    DRM_HDCP_KSV_LEN);
 996         if (ret)
 997                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
 998         return ret;
 999 }
1000
1001 static
1002 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1003                                  u8 *bstatus)
1004 {
1005         int ret;
1006         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1007                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1008         if (ret)
1009                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1010         return ret;
1011 }
1012
1013 static
1014 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1015                                      bool *repeater_present)
1016 {
1017         int ret;
1018         u8 val;
1019
1020         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1021         if (ret) {
1022                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1023                 return ret;
1024         }
1025         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1026         return 0;
1027 }
1028
1029 static
1030 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1031                                   u8 *ri_prime)
1032 {
1033         int ret;
1034         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1035                                    ri_prime, DRM_HDCP_RI_LEN);
1036         if (ret)
1037                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1038         return ret;
1039 }
1040
1041 static
1042 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1043                                    bool *ksv_ready)
1044 {
1045         int ret;
1046         u8 val;
1047
1048         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1049         if (ret) {
1050                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1051                 return ret;
1052         }
1053         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1054         return 0;
1055 }
1056
1057 static
1058 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1059                                   int num_downstream, u8 *ksv_fifo)
1060 {
1061         int ret;
1062         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1063                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1064         if (ret) {
1065                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1066                 return ret;
1067         }
1068         return 0;
1069 }
1070
1071 static
1072 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1073                                       int i, u32 *part)
1074 {
1075         int ret;
1076
1077         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1078                 return -EINVAL;
1079
1080         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1081                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1082         if (ret)
1083                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1084         return ret;
1085 }
1086
1087 static
1088 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1089                                       bool enable)
1090 {
1091         int ret;
1092
1093         if (!enable)
1094                 usleep_range(6, 60); /* Bspec says >= 6us */
1095
1096         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1097         if (ret) {
1098                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1099                           enable ? "Enable" : "Disable", ret);
1100                 return ret;
1101         }
1102         return 0;
1103 }
1104
1105 static
1106 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1107 {
1108         struct drm_i915_private *dev_priv =
1109                 intel_dig_port->base.base.dev->dev_private;
1110         enum port port = intel_dig_port->base.port;
1111         int ret;
1112         union {
1113                 u32 reg;
1114                 u8 shim[DRM_HDCP_RI_LEN];
1115         } ri;
1116
1117         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1118         if (ret)
1119                 return false;
1120
1121         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1122
1123         /* Wait for Ri prime match */
1124         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1125                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1126                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1127                           I915_READ(PORT_HDCP_STATUS(port)));
1128                 return false;
1129         }
1130         return true;
1131 }
1132
1133 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1134         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1135         .read_bksv = intel_hdmi_hdcp_read_bksv,
1136         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1137         .repeater_present = intel_hdmi_hdcp_repeater_present,
1138         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1139         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1140         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1141         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1142         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1143         .check_link = intel_hdmi_hdcp_check_link,
1144 };
1145
1146 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1147                                const struct intel_crtc_state *crtc_state)
1148 {
1149         struct drm_device *dev = encoder->base.dev;
1150         struct drm_i915_private *dev_priv = to_i915(dev);
1151         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1152         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1153         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1154         u32 hdmi_val;
1155
1156         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1157
1158         hdmi_val = SDVO_ENCODING_HDMI;
1159         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1160                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1161         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1162                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1163         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1164                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1165
1166         if (crtc_state->pipe_bpp > 24)
1167                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1168         else
1169                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1170
1171         if (crtc_state->has_hdmi_sink)
1172                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1173
1174         if (HAS_PCH_CPT(dev_priv))
1175                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1176         else if (IS_CHERRYVIEW(dev_priv))
1177                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1178         else
1179                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1180
1181         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1182         POSTING_READ(intel_hdmi->hdmi_reg);
1183 }
1184
1185 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1186                                     enum pipe *pipe)
1187 {
1188         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1189         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1190         bool ret;
1191
1192         if (!intel_display_power_get_if_enabled(dev_priv,
1193                                                 encoder->power_domain))
1194                 return false;
1195
1196         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1197
1198         intel_display_power_put(dev_priv, encoder->power_domain);
1199
1200         return ret;
1201 }
1202
1203 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1204                                   struct intel_crtc_state *pipe_config)
1205 {
1206         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1207         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1208         struct drm_device *dev = encoder->base.dev;
1209         struct drm_i915_private *dev_priv = to_i915(dev);
1210         u32 tmp, flags = 0;
1211         int dotclock;
1212
1213         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1214
1215         tmp = I915_READ(intel_hdmi->hdmi_reg);
1216
1217         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1218                 flags |= DRM_MODE_FLAG_PHSYNC;
1219         else
1220                 flags |= DRM_MODE_FLAG_NHSYNC;
1221
1222         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1223                 flags |= DRM_MODE_FLAG_PVSYNC;
1224         else
1225                 flags |= DRM_MODE_FLAG_NVSYNC;
1226
1227         if (tmp & HDMI_MODE_SELECT_HDMI)
1228                 pipe_config->has_hdmi_sink = true;
1229
1230         if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1231                 pipe_config->has_infoframe = true;
1232
1233         if (tmp & SDVO_AUDIO_ENABLE)
1234                 pipe_config->has_audio = true;
1235
1236         if (!HAS_PCH_SPLIT(dev_priv) &&
1237             tmp & HDMI_COLOR_RANGE_16_235)
1238                 pipe_config->limited_color_range = true;
1239
1240         pipe_config->base.adjusted_mode.flags |= flags;
1241
1242         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1243                 dotclock = pipe_config->port_clock * 2 / 3;
1244         else
1245                 dotclock = pipe_config->port_clock;
1246
1247         if (pipe_config->pixel_multiplier)
1248                 dotclock /= pipe_config->pixel_multiplier;
1249
1250         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1251
1252         pipe_config->lane_count = 4;
1253 }
1254
1255 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1256                                     const struct intel_crtc_state *pipe_config,
1257                                     const struct drm_connector_state *conn_state)
1258 {
1259         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1260
1261         WARN_ON(!pipe_config->has_hdmi_sink);
1262         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1263                          pipe_name(crtc->pipe));
1264         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1265 }
1266
1267 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1268                             const struct intel_crtc_state *pipe_config,
1269                             const struct drm_connector_state *conn_state)
1270 {
1271         struct drm_device *dev = encoder->base.dev;
1272         struct drm_i915_private *dev_priv = to_i915(dev);
1273         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1274         u32 temp;
1275
1276         temp = I915_READ(intel_hdmi->hdmi_reg);
1277
1278         temp |= SDVO_ENABLE;
1279         if (pipe_config->has_audio)
1280                 temp |= SDVO_AUDIO_ENABLE;
1281
1282         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1283         POSTING_READ(intel_hdmi->hdmi_reg);
1284
1285         if (pipe_config->has_audio)
1286                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1287 }
1288
1289 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1290                             const struct intel_crtc_state *pipe_config,
1291                             const struct drm_connector_state *conn_state)
1292 {
1293         struct drm_device *dev = encoder->base.dev;
1294         struct drm_i915_private *dev_priv = to_i915(dev);
1295         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1296         u32 temp;
1297
1298         temp = I915_READ(intel_hdmi->hdmi_reg);
1299
1300         temp |= SDVO_ENABLE;
1301         if (pipe_config->has_audio)
1302                 temp |= SDVO_AUDIO_ENABLE;
1303
1304         /*
1305          * HW workaround, need to write this twice for issue
1306          * that may result in first write getting masked.
1307          */
1308         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1309         POSTING_READ(intel_hdmi->hdmi_reg);
1310         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1311         POSTING_READ(intel_hdmi->hdmi_reg);
1312
1313         /*
1314          * HW workaround, need to toggle enable bit off and on
1315          * for 12bpc with pixel repeat.
1316          *
1317          * FIXME: BSpec says this should be done at the end of
1318          * of the modeset sequence, so not sure if this isn't too soon.
1319          */
1320         if (pipe_config->pipe_bpp > 24 &&
1321             pipe_config->pixel_multiplier > 1) {
1322                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1323                 POSTING_READ(intel_hdmi->hdmi_reg);
1324
1325                 /*
1326                  * HW workaround, need to write this twice for issue
1327                  * that may result in first write getting masked.
1328                  */
1329                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1330                 POSTING_READ(intel_hdmi->hdmi_reg);
1331                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1332                 POSTING_READ(intel_hdmi->hdmi_reg);
1333         }
1334
1335         if (pipe_config->has_audio)
1336                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1337 }
1338
1339 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1340                             const struct intel_crtc_state *pipe_config,
1341                             const struct drm_connector_state *conn_state)
1342 {
1343         struct drm_device *dev = encoder->base.dev;
1344         struct drm_i915_private *dev_priv = to_i915(dev);
1345         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1346         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1347         enum pipe pipe = crtc->pipe;
1348         u32 temp;
1349
1350         temp = I915_READ(intel_hdmi->hdmi_reg);
1351
1352         temp |= SDVO_ENABLE;
1353         if (pipe_config->has_audio)
1354                 temp |= SDVO_AUDIO_ENABLE;
1355
1356         /*
1357          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1358          *
1359          * The procedure for 12bpc is as follows:
1360          * 1. disable HDMI clock gating
1361          * 2. enable HDMI with 8bpc
1362          * 3. enable HDMI with 12bpc
1363          * 4. enable HDMI clock gating
1364          */
1365
1366         if (pipe_config->pipe_bpp > 24) {
1367                 I915_WRITE(TRANS_CHICKEN1(pipe),
1368                            I915_READ(TRANS_CHICKEN1(pipe)) |
1369                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1370
1371                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1372                 temp |= SDVO_COLOR_FORMAT_8bpc;
1373         }
1374
1375         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1376         POSTING_READ(intel_hdmi->hdmi_reg);
1377
1378         if (pipe_config->pipe_bpp > 24) {
1379                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1380                 temp |= HDMI_COLOR_FORMAT_12bpc;
1381
1382                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1383                 POSTING_READ(intel_hdmi->hdmi_reg);
1384
1385                 I915_WRITE(TRANS_CHICKEN1(pipe),
1386                            I915_READ(TRANS_CHICKEN1(pipe)) &
1387                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1388         }
1389
1390         if (pipe_config->has_audio)
1391                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1392 }
1393
1394 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1395                             const struct intel_crtc_state *pipe_config,
1396                             const struct drm_connector_state *conn_state)
1397 {
1398 }
1399
1400 static void intel_disable_hdmi(struct intel_encoder *encoder,
1401                                const struct intel_crtc_state *old_crtc_state,
1402                                const struct drm_connector_state *old_conn_state)
1403 {
1404         struct drm_device *dev = encoder->base.dev;
1405         struct drm_i915_private *dev_priv = to_i915(dev);
1406         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1407         struct intel_digital_port *intel_dig_port =
1408                 hdmi_to_dig_port(intel_hdmi);
1409         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1410         u32 temp;
1411
1412         temp = I915_READ(intel_hdmi->hdmi_reg);
1413
1414         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1415         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1416         POSTING_READ(intel_hdmi->hdmi_reg);
1417
1418         /*
1419          * HW workaround for IBX, we need to move the port
1420          * to transcoder A after disabling it to allow the
1421          * matching DP port to be enabled on transcoder A.
1422          */
1423         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1424                 /*
1425                  * We get CPU/PCH FIFO underruns on the other pipe when
1426                  * doing the workaround. Sweep them under the rug.
1427                  */
1428                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1429                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1430
1431                 temp &= ~SDVO_PIPE_SEL_MASK;
1432                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1433                 /*
1434                  * HW workaround, need to write this twice for issue
1435                  * that may result in first write getting masked.
1436                  */
1437                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1438                 POSTING_READ(intel_hdmi->hdmi_reg);
1439                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1440                 POSTING_READ(intel_hdmi->hdmi_reg);
1441
1442                 temp &= ~SDVO_ENABLE;
1443                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1444                 POSTING_READ(intel_hdmi->hdmi_reg);
1445
1446                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1447                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1448                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1449         }
1450
1451         intel_dig_port->set_infoframes(encoder,
1452                                        false,
1453                                        old_crtc_state, old_conn_state);
1454
1455         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1456 }
1457
1458 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1459                              const struct intel_crtc_state *old_crtc_state,
1460                              const struct drm_connector_state *old_conn_state)
1461 {
1462         if (old_crtc_state->has_audio)
1463                 intel_audio_codec_disable(encoder,
1464                                           old_crtc_state, old_conn_state);
1465
1466         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1467 }
1468
1469 static void pch_disable_hdmi(struct intel_encoder *encoder,
1470                              const struct intel_crtc_state *old_crtc_state,
1471                              const struct drm_connector_state *old_conn_state)
1472 {
1473         if (old_crtc_state->has_audio)
1474                 intel_audio_codec_disable(encoder,
1475                                           old_crtc_state, old_conn_state);
1476 }
1477
1478 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1479                                   const struct intel_crtc_state *old_crtc_state,
1480                                   const struct drm_connector_state *old_conn_state)
1481 {
1482         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1483 }
1484
1485 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1486 {
1487         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1488         const struct ddi_vbt_port_info *info =
1489                 &dev_priv->vbt.ddi_port_info[encoder->port];
1490         int max_tmds_clock;
1491
1492         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1493                 max_tmds_clock = 594000;
1494         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1495                 max_tmds_clock = 300000;
1496         else if (INTEL_GEN(dev_priv) >= 5)
1497                 max_tmds_clock = 225000;
1498         else
1499                 max_tmds_clock = 165000;
1500
1501         if (info->max_tmds_clock)
1502                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1503
1504         return max_tmds_clock;
1505 }
1506
1507 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1508                                  bool respect_downstream_limits,
1509                                  bool force_dvi)
1510 {
1511         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1512         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1513
1514         if (respect_downstream_limits) {
1515                 struct intel_connector *connector = hdmi->attached_connector;
1516                 const struct drm_display_info *info = &connector->base.display_info;
1517
1518                 if (hdmi->dp_dual_mode.max_tmds_clock)
1519                         max_tmds_clock = min(max_tmds_clock,
1520                                              hdmi->dp_dual_mode.max_tmds_clock);
1521
1522                 if (info->max_tmds_clock)
1523                         max_tmds_clock = min(max_tmds_clock,
1524                                              info->max_tmds_clock);
1525                 else if (!hdmi->has_hdmi_sink || force_dvi)
1526                         max_tmds_clock = min(max_tmds_clock, 165000);
1527         }
1528
1529         return max_tmds_clock;
1530 }
1531
1532 static enum drm_mode_status
1533 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1534                       int clock, bool respect_downstream_limits,
1535                       bool force_dvi)
1536 {
1537         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1538
1539         if (clock < 25000)
1540                 return MODE_CLOCK_LOW;
1541         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1542                 return MODE_CLOCK_HIGH;
1543
1544         /* BXT DPLL can't generate 223-240 MHz */
1545         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1546                 return MODE_CLOCK_RANGE;
1547
1548         /* CHV DPLL can't generate 216-240 MHz */
1549         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1550                 return MODE_CLOCK_RANGE;
1551
1552         return MODE_OK;
1553 }
1554
1555 static enum drm_mode_status
1556 intel_hdmi_mode_valid(struct drm_connector *connector,
1557                       struct drm_display_mode *mode)
1558 {
1559         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1560         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1561         struct drm_i915_private *dev_priv = to_i915(dev);
1562         enum drm_mode_status status;
1563         int clock;
1564         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1565         bool force_dvi =
1566                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1567
1568         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1569                 return MODE_NO_DBLESCAN;
1570
1571         clock = mode->clock;
1572
1573         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1574                 clock *= 2;
1575
1576         if (clock > max_dotclk)
1577                 return MODE_CLOCK_HIGH;
1578
1579         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1580                 clock *= 2;
1581
1582         if (drm_mode_is_420_only(&connector->display_info, mode))
1583                 clock /= 2;
1584
1585         /* check if we can do 8bpc */
1586         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1587
1588         if (hdmi->has_hdmi_sink && !force_dvi) {
1589                 /* if we can't do 8bpc we may still be able to do 12bpc */
1590                 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1591                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1592                                                        true, force_dvi);
1593
1594                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1595                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1596                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1597                                                        true, force_dvi);
1598         }
1599
1600         return status;
1601 }
1602
1603 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1604                                      int bpc)
1605 {
1606         struct drm_i915_private *dev_priv =
1607                 to_i915(crtc_state->base.crtc->dev);
1608         struct drm_atomic_state *state = crtc_state->base.state;
1609         struct drm_connector_state *connector_state;
1610         struct drm_connector *connector;
1611         const struct drm_display_mode *adjusted_mode =
1612                 &crtc_state->base.adjusted_mode;
1613         int i;
1614
1615         if (HAS_GMCH_DISPLAY(dev_priv))
1616                 return false;
1617
1618         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1619                 return false;
1620
1621         if (crtc_state->pipe_bpp <= 8*3)
1622                 return false;
1623
1624         if (!crtc_state->has_hdmi_sink)
1625                 return false;
1626
1627         /*
1628          * HDMI deep color affects the clocks, so it's only possible
1629          * when not cloning with other encoder types.
1630          */
1631         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1632                 return false;
1633
1634         for_each_new_connector_in_state(state, connector, connector_state, i) {
1635                 const struct drm_display_info *info = &connector->display_info;
1636
1637                 if (connector_state->crtc != crtc_state->base.crtc)
1638                         continue;
1639
1640                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1641                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1642
1643                         if (bpc == 12 && !(hdmi->y420_dc_modes &
1644                                            DRM_EDID_YCBCR420_DC_36))
1645                                 return false;
1646                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
1647                                                 DRM_EDID_YCBCR420_DC_30))
1648                                 return false;
1649                 } else {
1650                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1651                                            DRM_EDID_HDMI_DC_36))
1652                                 return false;
1653                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1654                                                 DRM_EDID_HDMI_DC_30))
1655                                 return false;
1656                 }
1657         }
1658
1659         /* Display WA #1139: glk */
1660         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1661             adjusted_mode->htotal > 5460)
1662                 return false;
1663
1664         /* Display Wa_1405510057:icl */
1665         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1666             bpc == 10 && IS_ICELAKE(dev_priv) &&
1667             (adjusted_mode->crtc_hblank_end -
1668              adjusted_mode->crtc_hblank_start) % 8 == 2)
1669                 return false;
1670
1671         return true;
1672 }
1673
1674 static bool
1675 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1676                            struct intel_crtc_state *config,
1677                            int *clock_12bpc, int *clock_10bpc,
1678                            int *clock_8bpc)
1679 {
1680         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1681
1682         if (!connector->ycbcr_420_allowed) {
1683                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1684                 return false;
1685         }
1686
1687         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1688         config->port_clock /= 2;
1689         *clock_12bpc /= 2;
1690         *clock_10bpc /= 2;
1691         *clock_8bpc /= 2;
1692         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1693
1694         /* YCBCR 420 output conversion needs a scaler */
1695         if (skl_update_scaler_crtc(config)) {
1696                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1697                 return false;
1698         }
1699
1700         intel_pch_panel_fitting(intel_crtc, config,
1701                                 DRM_MODE_SCALE_FULLSCREEN);
1702
1703         return true;
1704 }
1705
1706 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1707                                struct intel_crtc_state *pipe_config,
1708                                struct drm_connector_state *conn_state)
1709 {
1710         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1711         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1712         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1713         struct drm_connector *connector = conn_state->connector;
1714         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1715         struct intel_digital_connector_state *intel_conn_state =
1716                 to_intel_digital_connector_state(conn_state);
1717         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1718         int clock_10bpc = clock_8bpc * 5 / 4;
1719         int clock_12bpc = clock_8bpc * 3 / 2;
1720         int desired_bpp;
1721         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1722
1723         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1724                 return false;
1725
1726         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1727         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1728
1729         if (pipe_config->has_hdmi_sink)
1730                 pipe_config->has_infoframe = true;
1731
1732         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1733                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1734                 pipe_config->limited_color_range =
1735                         pipe_config->has_hdmi_sink &&
1736                         drm_default_rgb_quant_range(adjusted_mode) ==
1737                         HDMI_QUANTIZATION_RANGE_LIMITED;
1738         } else {
1739                 pipe_config->limited_color_range =
1740                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1741         }
1742
1743         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1744                 pipe_config->pixel_multiplier = 2;
1745                 clock_8bpc *= 2;
1746                 clock_10bpc *= 2;
1747                 clock_12bpc *= 2;
1748         }
1749
1750         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1751                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1752                                                 &clock_12bpc, &clock_10bpc,
1753                                                 &clock_8bpc)) {
1754                         DRM_ERROR("Can't support YCBCR420 output\n");
1755                         return false;
1756                 }
1757         }
1758
1759         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1760                 pipe_config->has_pch_encoder = true;
1761
1762         if (pipe_config->has_hdmi_sink) {
1763                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1764                         pipe_config->has_audio = intel_hdmi->has_audio;
1765                 else
1766                         pipe_config->has_audio =
1767                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1768         }
1769
1770         /*
1771          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1772          * to check that the higher clock still fits within limits.
1773          */
1774         if (hdmi_deep_color_possible(pipe_config, 12) &&
1775             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1776                                   true, force_dvi) == MODE_OK) {
1777                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1778                 desired_bpp = 12*3;
1779
1780                 /* Need to adjust the port link by 1.5x for 12bpc. */
1781                 pipe_config->port_clock = clock_12bpc;
1782         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1783                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1784                                          true, force_dvi) == MODE_OK) {
1785                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1786                 desired_bpp = 10 * 3;
1787
1788                 /* Need to adjust the port link by 1.25x for 10bpc. */
1789                 pipe_config->port_clock = clock_10bpc;
1790         } else {
1791                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1792                 desired_bpp = 8*3;
1793
1794                 pipe_config->port_clock = clock_8bpc;
1795         }
1796
1797         if (!pipe_config->bw_constrained) {
1798                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1799                 pipe_config->pipe_bpp = desired_bpp;
1800         }
1801
1802         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1803                                   false, force_dvi) != MODE_OK) {
1804                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1805                 return false;
1806         }
1807
1808         /* Set user selected PAR to incoming mode's member */
1809         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1810
1811         pipe_config->lane_count = 4;
1812
1813         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1814                                            IS_GEMINILAKE(dev_priv))) {
1815                 if (scdc->scrambling.low_rates)
1816                         pipe_config->hdmi_scrambling = true;
1817
1818                 if (pipe_config->port_clock > 340000) {
1819                         pipe_config->hdmi_scrambling = true;
1820                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1821                 }
1822         }
1823
1824         return true;
1825 }
1826
1827 static void
1828 intel_hdmi_unset_edid(struct drm_connector *connector)
1829 {
1830         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1831
1832         intel_hdmi->has_hdmi_sink = false;
1833         intel_hdmi->has_audio = false;
1834
1835         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1836         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1837
1838         kfree(to_intel_connector(connector)->detect_edid);
1839         to_intel_connector(connector)->detect_edid = NULL;
1840 }
1841
1842 static void
1843 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1844 {
1845         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1846         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1847         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1848         struct i2c_adapter *adapter =
1849                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1850         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1851
1852         /*
1853          * Type 1 DVI adaptors are not required to implement any
1854          * registers, so we can't always detect their presence.
1855          * Ideally we should be able to check the state of the
1856          * CONFIG1 pin, but no such luck on our hardware.
1857          *
1858          * The only method left to us is to check the VBT to see
1859          * if the port is a dual mode capable DP port. But let's
1860          * only do that when we sucesfully read the EDID, to avoid
1861          * confusing log messages about DP dual mode adaptors when
1862          * there's nothing connected to the port.
1863          */
1864         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1865                 /* An overridden EDID imply that we want this port for testing.
1866                  * Make sure not to set limits for that port.
1867                  */
1868                 if (has_edid && !connector->override_edid &&
1869                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1870                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1871                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1872                 } else {
1873                         type = DRM_DP_DUAL_MODE_NONE;
1874                 }
1875         }
1876
1877         if (type == DRM_DP_DUAL_MODE_NONE)
1878                 return;
1879
1880         hdmi->dp_dual_mode.type = type;
1881         hdmi->dp_dual_mode.max_tmds_clock =
1882                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1883
1884         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1885                       drm_dp_get_dual_mode_type_name(type),
1886                       hdmi->dp_dual_mode.max_tmds_clock);
1887 }
1888
1889 static bool
1890 intel_hdmi_set_edid(struct drm_connector *connector)
1891 {
1892         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1893         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1894         struct edid *edid;
1895         bool connected = false;
1896         struct i2c_adapter *i2c;
1897
1898         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1899
1900         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1901
1902         edid = drm_get_edid(connector, i2c);
1903
1904         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1905                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1906                 intel_gmbus_force_bit(i2c, true);
1907                 edid = drm_get_edid(connector, i2c);
1908                 intel_gmbus_force_bit(i2c, false);
1909         }
1910
1911         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1912
1913         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1914
1915         to_intel_connector(connector)->detect_edid = edid;
1916         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1917                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1918                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1919
1920                 connected = true;
1921         }
1922
1923         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1924
1925         return connected;
1926 }
1927
1928 static enum drm_connector_status
1929 intel_hdmi_detect(struct drm_connector *connector, bool force)
1930 {
1931         enum drm_connector_status status = connector_status_disconnected;
1932         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1933         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1934         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1935
1936         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1937                       connector->base.id, connector->name);
1938
1939         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1940
1941         if (IS_ICELAKE(dev_priv) &&
1942             !intel_digital_port_connected(encoder))
1943                 goto out;
1944
1945         intel_hdmi_unset_edid(connector);
1946
1947         if (intel_hdmi_set_edid(connector))
1948                 status = connector_status_connected;
1949
1950 out:
1951         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1952
1953         if (status != connector_status_connected)
1954                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1955
1956         return status;
1957 }
1958
1959 static void
1960 intel_hdmi_force(struct drm_connector *connector)
1961 {
1962         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1963                       connector->base.id, connector->name);
1964
1965         intel_hdmi_unset_edid(connector);
1966
1967         if (connector->status != connector_status_connected)
1968                 return;
1969
1970         intel_hdmi_set_edid(connector);
1971 }
1972
1973 static int intel_hdmi_get_modes(struct drm_connector *connector)
1974 {
1975         struct edid *edid;
1976
1977         edid = to_intel_connector(connector)->detect_edid;
1978         if (edid == NULL)
1979                 return 0;
1980
1981         return intel_connector_update_modes(connector, edid);
1982 }
1983
1984 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1985                                   const struct intel_crtc_state *pipe_config,
1986                                   const struct drm_connector_state *conn_state)
1987 {
1988         struct intel_digital_port *intel_dig_port =
1989                 enc_to_dig_port(&encoder->base);
1990
1991         intel_hdmi_prepare(encoder, pipe_config);
1992
1993         intel_dig_port->set_infoframes(encoder,
1994                                        pipe_config->has_infoframe,
1995                                        pipe_config, conn_state);
1996 }
1997
1998 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1999                                 const struct intel_crtc_state *pipe_config,
2000                                 const struct drm_connector_state *conn_state)
2001 {
2002         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2003         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2004
2005         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2006
2007         /* HDMI 1.0V-2dB */
2008         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2009                                  0x2b247878);
2010
2011         dport->set_infoframes(encoder,
2012                               pipe_config->has_infoframe,
2013                               pipe_config, conn_state);
2014
2015         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2016
2017         vlv_wait_port_ready(dev_priv, dport, 0x0);
2018 }
2019
2020 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2021                                     const struct intel_crtc_state *pipe_config,
2022                                     const struct drm_connector_state *conn_state)
2023 {
2024         intel_hdmi_prepare(encoder, pipe_config);
2025
2026         vlv_phy_pre_pll_enable(encoder, pipe_config);
2027 }
2028
2029 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2030                                     const struct intel_crtc_state *pipe_config,
2031                                     const struct drm_connector_state *conn_state)
2032 {
2033         intel_hdmi_prepare(encoder, pipe_config);
2034
2035         chv_phy_pre_pll_enable(encoder, pipe_config);
2036 }
2037
2038 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2039                                       const struct intel_crtc_state *old_crtc_state,
2040                                       const struct drm_connector_state *old_conn_state)
2041 {
2042         chv_phy_post_pll_disable(encoder, old_crtc_state);
2043 }
2044
2045 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2046                                   const struct intel_crtc_state *old_crtc_state,
2047                                   const struct drm_connector_state *old_conn_state)
2048 {
2049         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2050         vlv_phy_reset_lanes(encoder, old_crtc_state);
2051 }
2052
2053 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2054                                   const struct intel_crtc_state *old_crtc_state,
2055                                   const struct drm_connector_state *old_conn_state)
2056 {
2057         struct drm_device *dev = encoder->base.dev;
2058         struct drm_i915_private *dev_priv = to_i915(dev);
2059
2060         mutex_lock(&dev_priv->sb_lock);
2061
2062         /* Assert data lane reset */
2063         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2064
2065         mutex_unlock(&dev_priv->sb_lock);
2066 }
2067
2068 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2069                                 const struct intel_crtc_state *pipe_config,
2070                                 const struct drm_connector_state *conn_state)
2071 {
2072         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2073         struct drm_device *dev = encoder->base.dev;
2074         struct drm_i915_private *dev_priv = to_i915(dev);
2075
2076         chv_phy_pre_encoder_enable(encoder, pipe_config);
2077
2078         /* FIXME: Program the support xxx V-dB */
2079         /* Use 800mV-0dB */
2080         chv_set_phy_signal_level(encoder, 128, 102, false);
2081
2082         dport->set_infoframes(encoder,
2083                               pipe_config->has_infoframe,
2084                               pipe_config, conn_state);
2085
2086         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2087
2088         vlv_wait_port_ready(dev_priv, dport, 0x0);
2089
2090         /* Second common lane will stay alive on its own now */
2091         chv_phy_release_cl2_override(encoder);
2092 }
2093
2094 static int
2095 intel_hdmi_connector_register(struct drm_connector *connector)
2096 {
2097         int ret;
2098
2099         ret = intel_connector_register(connector);
2100         if (ret)
2101                 return ret;
2102
2103         i915_debugfs_connector_add(connector);
2104
2105         return ret;
2106 }
2107
2108 static void intel_hdmi_destroy(struct drm_connector *connector)
2109 {
2110         if (intel_attached_hdmi(connector)->cec_notifier)
2111                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2112
2113         intel_connector_destroy(connector);
2114 }
2115
2116 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2117         .detect = intel_hdmi_detect,
2118         .force = intel_hdmi_force,
2119         .fill_modes = drm_helper_probe_single_connector_modes,
2120         .atomic_get_property = intel_digital_connector_atomic_get_property,
2121         .atomic_set_property = intel_digital_connector_atomic_set_property,
2122         .late_register = intel_hdmi_connector_register,
2123         .early_unregister = intel_connector_unregister,
2124         .destroy = intel_hdmi_destroy,
2125         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2126         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2127 };
2128
2129 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2130         .get_modes = intel_hdmi_get_modes,
2131         .mode_valid = intel_hdmi_mode_valid,
2132         .atomic_check = intel_digital_connector_atomic_check,
2133 };
2134
2135 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2136         .destroy = intel_encoder_destroy,
2137 };
2138
2139 static void
2140 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2141 {
2142         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2143
2144         intel_attach_force_audio_property(connector);
2145         intel_attach_broadcast_rgb_property(connector);
2146         intel_attach_aspect_ratio_property(connector);
2147         drm_connector_attach_content_type_property(connector);
2148         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2149
2150         if (!HAS_GMCH_DISPLAY(dev_priv))
2151                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2152 }
2153
2154 /*
2155  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2156  * @encoder: intel_encoder
2157  * @connector: drm_connector
2158  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2159  *  or reset the high tmds clock ratio for scrambling
2160  * @scrambling: bool to Indicate if the function needs to set or reset
2161  *  sink scrambling
2162  *
2163  * This function handles scrambling on HDMI 2.0 capable sinks.
2164  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2165  * it enables scrambling. This should be called before enabling the HDMI
2166  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2167  * detect a scrambled clock within 100 ms.
2168  *
2169  * Returns:
2170  * True on success, false on failure.
2171  */
2172 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2173                                        struct drm_connector *connector,
2174                                        bool high_tmds_clock_ratio,
2175                                        bool scrambling)
2176 {
2177         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2178         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2179         struct drm_scrambling *sink_scrambling =
2180                 &connector->display_info.hdmi.scdc.scrambling;
2181         struct i2c_adapter *adapter =
2182                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2183
2184         if (!sink_scrambling->supported)
2185                 return true;
2186
2187         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2188                       connector->base.id, connector->name,
2189                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2190
2191         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2192         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2193                                                   high_tmds_clock_ratio) &&
2194                 drm_scdc_set_scrambling(adapter, scrambling);
2195 }
2196
2197 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2198 {
2199         u8 ddc_pin;
2200
2201         switch (port) {
2202         case PORT_B:
2203                 ddc_pin = GMBUS_PIN_DPB;
2204                 break;
2205         case PORT_C:
2206                 ddc_pin = GMBUS_PIN_DPC;
2207                 break;
2208         case PORT_D:
2209                 ddc_pin = GMBUS_PIN_DPD_CHV;
2210                 break;
2211         default:
2212                 MISSING_CASE(port);
2213                 ddc_pin = GMBUS_PIN_DPB;
2214                 break;
2215         }
2216         return ddc_pin;
2217 }
2218
2219 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2220 {
2221         u8 ddc_pin;
2222
2223         switch (port) {
2224         case PORT_B:
2225                 ddc_pin = GMBUS_PIN_1_BXT;
2226                 break;
2227         case PORT_C:
2228                 ddc_pin = GMBUS_PIN_2_BXT;
2229                 break;
2230         default:
2231                 MISSING_CASE(port);
2232                 ddc_pin = GMBUS_PIN_1_BXT;
2233                 break;
2234         }
2235         return ddc_pin;
2236 }
2237
2238 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2239                               enum port port)
2240 {
2241         u8 ddc_pin;
2242
2243         switch (port) {
2244         case PORT_B:
2245                 ddc_pin = GMBUS_PIN_1_BXT;
2246                 break;
2247         case PORT_C:
2248                 ddc_pin = GMBUS_PIN_2_BXT;
2249                 break;
2250         case PORT_D:
2251                 ddc_pin = GMBUS_PIN_4_CNP;
2252                 break;
2253         case PORT_F:
2254                 ddc_pin = GMBUS_PIN_3_BXT;
2255                 break;
2256         default:
2257                 MISSING_CASE(port);
2258                 ddc_pin = GMBUS_PIN_1_BXT;
2259                 break;
2260         }
2261         return ddc_pin;
2262 }
2263
2264 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2265 {
2266         u8 ddc_pin;
2267
2268         switch (port) {
2269         case PORT_A:
2270                 ddc_pin = GMBUS_PIN_1_BXT;
2271                 break;
2272         case PORT_B:
2273                 ddc_pin = GMBUS_PIN_2_BXT;
2274                 break;
2275         case PORT_C:
2276                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2277                 break;
2278         case PORT_D:
2279                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2280                 break;
2281         case PORT_E:
2282                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2283                 break;
2284         case PORT_F:
2285                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2286                 break;
2287         default:
2288                 MISSING_CASE(port);
2289                 ddc_pin = GMBUS_PIN_2_BXT;
2290                 break;
2291         }
2292         return ddc_pin;
2293 }
2294
2295 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2296                               enum port port)
2297 {
2298         u8 ddc_pin;
2299
2300         switch (port) {
2301         case PORT_B:
2302                 ddc_pin = GMBUS_PIN_DPB;
2303                 break;
2304         case PORT_C:
2305                 ddc_pin = GMBUS_PIN_DPC;
2306                 break;
2307         case PORT_D:
2308                 ddc_pin = GMBUS_PIN_DPD;
2309                 break;
2310         default:
2311                 MISSING_CASE(port);
2312                 ddc_pin = GMBUS_PIN_DPB;
2313                 break;
2314         }
2315         return ddc_pin;
2316 }
2317
2318 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2319                              enum port port)
2320 {
2321         const struct ddi_vbt_port_info *info =
2322                 &dev_priv->vbt.ddi_port_info[port];
2323         u8 ddc_pin;
2324
2325         if (info->alternate_ddc_pin) {
2326                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2327                               info->alternate_ddc_pin, port_name(port));
2328                 return info->alternate_ddc_pin;
2329         }
2330
2331         if (IS_CHERRYVIEW(dev_priv))
2332                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2333         else if (IS_GEN9_LP(dev_priv))
2334                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2335         else if (HAS_PCH_CNP(dev_priv))
2336                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2337         else if (HAS_PCH_ICP(dev_priv))
2338                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2339         else
2340                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2341
2342         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2343                       ddc_pin, port_name(port));
2344
2345         return ddc_pin;
2346 }
2347
2348 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2349 {
2350         struct drm_i915_private *dev_priv =
2351                 to_i915(intel_dig_port->base.base.dev);
2352
2353         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2354                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2355                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2356                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2357         } else if (IS_G4X(dev_priv)) {
2358                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2359                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2360                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2361         } else if (HAS_DDI(dev_priv)) {
2362                 if (intel_dig_port->lspcon.active) {
2363                         intel_dig_port->write_infoframe =
2364                                         lspcon_write_infoframe;
2365                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2366                         intel_dig_port->infoframe_enabled =
2367                                                 lspcon_infoframe_enabled;
2368                 } else {
2369                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2370                         intel_dig_port->infoframe_enabled =
2371                                                 hsw_infoframe_enabled;
2372                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2373                 }
2374         } else if (HAS_PCH_IBX(dev_priv)) {
2375                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2376                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2377                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2378         } else {
2379                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2380                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2381                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2382         }
2383 }
2384
2385 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2386                                struct intel_connector *intel_connector)
2387 {
2388         struct drm_connector *connector = &intel_connector->base;
2389         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2390         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2391         struct drm_device *dev = intel_encoder->base.dev;
2392         struct drm_i915_private *dev_priv = to_i915(dev);
2393         enum port port = intel_encoder->port;
2394
2395         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2396                       port_name(port));
2397
2398         if (WARN(intel_dig_port->max_lanes < 4,
2399                  "Not enough lanes (%d) for HDMI on port %c\n",
2400                  intel_dig_port->max_lanes, port_name(port)))
2401                 return;
2402
2403         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2404                            DRM_MODE_CONNECTOR_HDMIA);
2405         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2406
2407         connector->interlace_allowed = 1;
2408         connector->doublescan_allowed = 0;
2409         connector->stereo_allowed = 1;
2410
2411         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2412                 connector->ycbcr_420_allowed = true;
2413
2414         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2415
2416         if (WARN_ON(port == PORT_A))
2417                 return;
2418         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2419
2420         if (HAS_DDI(dev_priv))
2421                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2422         else
2423                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2424
2425         intel_hdmi_add_properties(intel_hdmi, connector);
2426
2427         if (is_hdcp_supported(dev_priv, port)) {
2428                 int ret = intel_hdcp_init(intel_connector,
2429                                           &intel_hdmi_hdcp_shim);
2430                 if (ret)
2431                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2432         }
2433
2434         intel_connector_attach_encoder(intel_connector, intel_encoder);
2435         intel_hdmi->attached_connector = intel_connector;
2436
2437         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2438          * 0xd.  Failure to do so will result in spurious interrupts being
2439          * generated on the port when a cable is not attached.
2440          */
2441         if (IS_G45(dev_priv)) {
2442                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2443                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2444         }
2445
2446         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2447                                                          port_identifier(port));
2448         if (!intel_hdmi->cec_notifier)
2449                 DRM_DEBUG_KMS("CEC notifier get failed\n");
2450 }
2451
2452 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2453                      i915_reg_t hdmi_reg, enum port port)
2454 {
2455         struct intel_digital_port *intel_dig_port;
2456         struct intel_encoder *intel_encoder;
2457         struct intel_connector *intel_connector;
2458
2459         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2460         if (!intel_dig_port)
2461                 return;
2462
2463         intel_connector = intel_connector_alloc();
2464         if (!intel_connector) {
2465                 kfree(intel_dig_port);
2466                 return;
2467         }
2468
2469         intel_encoder = &intel_dig_port->base;
2470
2471         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2472                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2473                          "HDMI %c", port_name(port));
2474
2475         intel_encoder->hotplug = intel_encoder_hotplug;
2476         intel_encoder->compute_config = intel_hdmi_compute_config;
2477         if (HAS_PCH_SPLIT(dev_priv)) {
2478                 intel_encoder->disable = pch_disable_hdmi;
2479                 intel_encoder->post_disable = pch_post_disable_hdmi;
2480         } else {
2481                 intel_encoder->disable = g4x_disable_hdmi;
2482         }
2483         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2484         intel_encoder->get_config = intel_hdmi_get_config;
2485         if (IS_CHERRYVIEW(dev_priv)) {
2486                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2487                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2488                 intel_encoder->enable = vlv_enable_hdmi;
2489                 intel_encoder->post_disable = chv_hdmi_post_disable;
2490                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2491         } else if (IS_VALLEYVIEW(dev_priv)) {
2492                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2493                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2494                 intel_encoder->enable = vlv_enable_hdmi;
2495                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2496         } else {
2497                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2498                 if (HAS_PCH_CPT(dev_priv))
2499                         intel_encoder->enable = cpt_enable_hdmi;
2500                 else if (HAS_PCH_IBX(dev_priv))
2501                         intel_encoder->enable = ibx_enable_hdmi;
2502                 else
2503                         intel_encoder->enable = g4x_enable_hdmi;
2504         }
2505
2506         intel_encoder->type = INTEL_OUTPUT_HDMI;
2507         intel_encoder->power_domain = intel_port_to_power_domain(port);
2508         intel_encoder->port = port;
2509         if (IS_CHERRYVIEW(dev_priv)) {
2510                 if (port == PORT_D)
2511                         intel_encoder->crtc_mask = 1 << 2;
2512                 else
2513                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2514         } else {
2515                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2516         }
2517         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2518         /*
2519          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2520          * to work on real hardware. And since g4x can send infoframes to
2521          * only one port anyway, nothing is lost by allowing it.
2522          */
2523         if (IS_G4X(dev_priv))
2524                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2525
2526         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2527         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2528         intel_dig_port->max_lanes = 4;
2529
2530         intel_infoframe_init(intel_dig_port);
2531
2532         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2533         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2534 }