2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = to_i915(dev);
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
117 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
123 case HDMI_INFOFRAME_TYPE_AVI:
124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
125 case HDMI_INFOFRAME_TYPE_SPD:
126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
127 case HDMI_INFOFRAME_TYPE_VENDOR:
128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
131 return INVALID_MMIO_REG;
135 static void g4x_write_infoframe(struct drm_encoder *encoder,
136 enum hdmi_infoframe_type type,
137 const void *frame, ssize_t len)
139 const uint32_t *data = frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = to_i915(dev);
142 u32 val = I915_READ(VIDEO_DIP_CTL);
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(type);
150 val &= ~g4x_infoframe_enable(type);
152 I915_WRITE(VIDEO_DIP_CTL, val);
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
164 val |= g4x_infoframe_enable(type);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
172 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
177 u32 val = I915_READ(VIDEO_DIP_CTL);
179 if ((val & VIDEO_DIP_ENABLE) == 0)
182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
189 static void ibx_write_infoframe(struct drm_encoder *encoder,
190 enum hdmi_infoframe_type type,
191 const void *frame, ssize_t len)
193 const uint32_t *data = frame;
194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = to_i915(dev);
196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
198 u32 val = I915_READ(reg);
201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
204 val |= g4x_infoframe_index(type);
206 val &= ~g4x_infoframe_enable(type);
208 I915_WRITE(reg, val);
211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
220 val |= g4x_infoframe_enable(type);
221 val &= ~VIDEO_DIP_FREQ_MASK;
222 val |= VIDEO_DIP_FREQ_VSYNC;
224 I915_WRITE(reg, val);
228 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
235 u32 val = I915_READ(reg);
237 if ((val & VIDEO_DIP_ENABLE) == 0)
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
248 static void cpt_write_infoframe(struct drm_encoder *encoder,
249 enum hdmi_infoframe_type type,
250 const void *frame, ssize_t len)
252 const uint32_t *data = frame;
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = to_i915(dev);
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
257 u32 val = I915_READ(reg);
260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
263 val |= g4x_infoframe_index(type);
265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
270 I915_WRITE(reg, val);
273 for (i = 0; i < len; i += 4) {
274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
282 val |= g4x_infoframe_enable(type);
283 val &= ~VIDEO_DIP_FREQ_MASK;
284 val |= VIDEO_DIP_FREQ_VSYNC;
286 I915_WRITE(reg, val);
290 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
297 if ((val & VIDEO_DIP_ENABLE) == 0)
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
305 static void vlv_write_infoframe(struct drm_encoder *encoder,
306 enum hdmi_infoframe_type type,
307 const void *frame, ssize_t len)
309 const uint32_t *data = frame;
310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = to_i915(dev);
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
314 u32 val = I915_READ(reg);
317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
320 val |= g4x_infoframe_index(type);
322 val &= ~g4x_infoframe_enable(type);
324 I915_WRITE(reg, val);
327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
336 val |= g4x_infoframe_enable(type);
337 val &= ~VIDEO_DIP_FREQ_MASK;
338 val |= VIDEO_DIP_FREQ_VSYNC;
340 I915_WRITE(reg, val);
344 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
352 if ((val & VIDEO_DIP_ENABLE) == 0)
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
363 static void hsw_write_infoframe(struct drm_encoder *encoder,
364 enum hdmi_infoframe_type type,
365 const void *frame, ssize_t len)
367 const uint32_t *data = frame;
368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = to_i915(dev);
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
375 u32 val = I915_READ(ctl_reg);
377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
421 * (HB is Header Byte, DB is Data Byte)
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
427 static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
450 const struct drm_display_mode *adjusted_mode)
452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
454 union hdmi_infoframe frame;
457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
460 DRM_ERROR("couldn't fill AVI infoframe\n");
464 if (intel_hdmi->rgb_quant_range_selectable) {
465 if (intel_crtc->config->limited_color_range)
466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
473 intel_write_infoframe(encoder, &frame);
476 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
478 union hdmi_infoframe frame;
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
483 DRM_ERROR("couldn't fill SPD infoframe\n");
487 frame.spd.sdi = HDMI_SPD_SDI_PC;
489 intel_write_infoframe(encoder, &frame);
493 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
494 const struct drm_display_mode *adjusted_mode)
496 union hdmi_infoframe frame;
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
504 intel_write_infoframe(encoder, &frame);
507 static void g4x_set_infoframes(struct drm_encoder *encoder,
509 const struct drm_display_mode *adjusted_mode)
511 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
514 i915_reg_t reg = VIDEO_DIP_CTL;
515 u32 val = I915_READ(reg);
516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
518 assert_hdmi_port_disabled(intel_hdmi);
520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
532 if (!(val & VIDEO_DIP_ENABLE))
534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
541 I915_WRITE(reg, val);
546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
552 val &= ~VIDEO_DIP_PORT_MASK;
556 val |= VIDEO_DIP_ENABLE;
557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
560 I915_WRITE(reg, val);
563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
568 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
597 static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
600 unsigned int pixels_per_group;
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
616 /* phase information not relevant for 8bpc */
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
630 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
632 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
641 else if (HAS_PCH_SPLIT(dev_priv))
642 reg = TVIDEO_DIP_GCP(crtc->pipe);
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
655 I915_WRITE(reg, val);
660 static void ibx_set_infoframes(struct drm_encoder *encoder,
662 const struct drm_display_mode *adjusted_mode)
664 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
669 u32 val = I915_READ(reg);
670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
672 assert_hdmi_port_disabled(intel_hdmi);
674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
678 if (!(val & VIDEO_DIP_ENABLE))
680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
683 I915_WRITE(reg, val);
688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
692 val &= ~VIDEO_DIP_PORT_MASK;
696 val |= VIDEO_DIP_ENABLE;
697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
704 I915_WRITE(reg, val);
707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
712 static void cpt_set_infoframes(struct drm_encoder *encoder,
714 const struct drm_display_mode *adjusted_mode)
716 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
720 u32 val = I915_READ(reg);
722 assert_hdmi_port_disabled(intel_hdmi);
724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
728 if (!(val & VIDEO_DIP_ENABLE))
730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
733 I915_WRITE(reg, val);
738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
746 I915_WRITE(reg, val);
749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
754 static void vlv_set_infoframes(struct drm_encoder *encoder,
756 const struct drm_display_mode *adjusted_mode)
758 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
763 u32 val = I915_READ(reg);
764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
766 assert_hdmi_port_disabled(intel_hdmi);
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
772 if (!(val & VIDEO_DIP_ENABLE))
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
786 val &= ~VIDEO_DIP_PORT_MASK;
790 val |= VIDEO_DIP_ENABLE;
791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
798 I915_WRITE(reg, val);
801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
806 static void hsw_set_infoframes(struct drm_encoder *encoder,
808 const struct drm_display_mode *adjusted_mode)
810 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
814 u32 val = I915_READ(reg);
816 assert_hdmi_port_disabled(intel_hdmi);
818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
823 I915_WRITE(reg, val);
828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
831 I915_WRITE(reg, val);
834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
839 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
842 struct i2c_adapter *adapter =
843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
849 enable ? "Enabling" : "Disabling");
851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
855 static void intel_hdmi_prepare(struct intel_encoder *encoder)
857 struct drm_device *dev = encoder->base.dev;
858 struct drm_i915_private *dev_priv = to_i915(dev);
859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
866 hdmi_val = SDVO_ENCODING_HDMI;
867 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
868 hdmi_val |= HDMI_COLOR_RANGE_16_235;
869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
874 if (crtc->config->pipe_bpp > 24)
875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
879 if (crtc->config->has_hdmi_sink)
880 hdmi_val |= HDMI_MODE_SELECT_HDMI;
882 if (HAS_PCH_CPT(dev))
883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
884 else if (IS_CHERRYVIEW(dev))
885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
890 POSTING_READ(intel_hdmi->hdmi_reg);
893 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
896 struct drm_device *dev = encoder->base.dev;
897 struct drm_i915_private *dev_priv = to_i915(dev);
898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
899 enum intel_display_power_domain power_domain;
903 power_domain = intel_display_port_power_domain(encoder);
904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
909 tmp = I915_READ(intel_hdmi->hdmi_reg);
911 if (!(tmp & SDVO_ENABLE))
914 if (HAS_PCH_CPT(dev))
915 *pipe = PORT_TO_PIPE_CPT(tmp);
916 else if (IS_CHERRYVIEW(dev))
917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
919 *pipe = PORT_TO_PIPE(tmp);
924 intel_display_power_put(dev_priv, power_domain);
929 static void intel_hdmi_get_config(struct intel_encoder *encoder,
930 struct intel_crtc_state *pipe_config)
932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
933 struct drm_device *dev = encoder->base.dev;
934 struct drm_i915_private *dev_priv = to_i915(dev);
938 tmp = I915_READ(intel_hdmi->hdmi_reg);
940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
941 flags |= DRM_MODE_FLAG_PHSYNC;
943 flags |= DRM_MODE_FLAG_NHSYNC;
945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
946 flags |= DRM_MODE_FLAG_PVSYNC;
948 flags |= DRM_MODE_FLAG_NVSYNC;
950 if (tmp & HDMI_MODE_SELECT_HDMI)
951 pipe_config->has_hdmi_sink = true;
953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
954 pipe_config->has_infoframe = true;
956 if (tmp & SDVO_AUDIO_ENABLE)
957 pipe_config->has_audio = true;
959 if (!HAS_PCH_SPLIT(dev) &&
960 tmp & HDMI_COLOR_RANGE_16_235)
961 pipe_config->limited_color_range = true;
963 pipe_config->base.adjusted_mode.flags |= flags;
965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
966 dotclock = pipe_config->port_clock * 2 / 3;
968 dotclock = pipe_config->port_clock;
970 if (pipe_config->pixel_multiplier)
971 dotclock /= pipe_config->pixel_multiplier;
973 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
975 pipe_config->lane_count = 4;
978 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
982 WARN_ON(!crtc->config->has_hdmi_sink);
983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
984 pipe_name(crtc->pipe));
985 intel_audio_codec_enable(encoder);
988 static void g4x_enable_hdmi(struct intel_encoder *encoder)
990 struct drm_device *dev = encoder->base.dev;
991 struct drm_i915_private *dev_priv = to_i915(dev);
992 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
993 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
996 temp = I915_READ(intel_hdmi->hdmi_reg);
999 if (crtc->config->has_audio)
1000 temp |= SDVO_AUDIO_ENABLE;
1002 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1003 POSTING_READ(intel_hdmi->hdmi_reg);
1005 if (crtc->config->has_audio)
1006 intel_enable_hdmi_audio(encoder);
1009 static void ibx_enable_hdmi(struct intel_encoder *encoder)
1011 struct drm_device *dev = encoder->base.dev;
1012 struct drm_i915_private *dev_priv = to_i915(dev);
1013 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1014 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1017 temp = I915_READ(intel_hdmi->hdmi_reg);
1019 temp |= SDVO_ENABLE;
1020 if (crtc->config->has_audio)
1021 temp |= SDVO_AUDIO_ENABLE;
1024 * HW workaround, need to write this twice for issue
1025 * that may result in first write getting masked.
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1029 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1030 POSTING_READ(intel_hdmi->hdmi_reg);
1033 * HW workaround, need to toggle enable bit off and on
1034 * for 12bpc with pixel repeat.
1036 * FIXME: BSpec says this should be done at the end of
1037 * of the modeset sequence, so not sure if this isn't too soon.
1039 if (crtc->config->pipe_bpp > 24 &&
1040 crtc->config->pixel_multiplier > 1) {
1041 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1042 POSTING_READ(intel_hdmi->hdmi_reg);
1045 * HW workaround, need to write this twice for issue
1046 * that may result in first write getting masked.
1048 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1049 POSTING_READ(intel_hdmi->hdmi_reg);
1050 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1051 POSTING_READ(intel_hdmi->hdmi_reg);
1054 if (crtc->config->has_audio)
1055 intel_enable_hdmi_audio(encoder);
1058 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1060 struct drm_device *dev = encoder->base.dev;
1061 struct drm_i915_private *dev_priv = to_i915(dev);
1062 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1063 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1064 enum pipe pipe = crtc->pipe;
1067 temp = I915_READ(intel_hdmi->hdmi_reg);
1069 temp |= SDVO_ENABLE;
1070 if (crtc->config->has_audio)
1071 temp |= SDVO_AUDIO_ENABLE;
1074 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1076 * The procedure for 12bpc is as follows:
1077 * 1. disable HDMI clock gating
1078 * 2. enable HDMI with 8bpc
1079 * 3. enable HDMI with 12bpc
1080 * 4. enable HDMI clock gating
1083 if (crtc->config->pipe_bpp > 24) {
1084 I915_WRITE(TRANS_CHICKEN1(pipe),
1085 I915_READ(TRANS_CHICKEN1(pipe)) |
1086 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1088 temp &= ~SDVO_COLOR_FORMAT_MASK;
1089 temp |= SDVO_COLOR_FORMAT_8bpc;
1092 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1093 POSTING_READ(intel_hdmi->hdmi_reg);
1095 if (crtc->config->pipe_bpp > 24) {
1096 temp &= ~SDVO_COLOR_FORMAT_MASK;
1097 temp |= HDMI_COLOR_FORMAT_12bpc;
1099 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1100 POSTING_READ(intel_hdmi->hdmi_reg);
1102 I915_WRITE(TRANS_CHICKEN1(pipe),
1103 I915_READ(TRANS_CHICKEN1(pipe)) &
1104 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1107 if (crtc->config->has_audio)
1108 intel_enable_hdmi_audio(encoder);
1111 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1115 static void intel_disable_hdmi(struct intel_encoder *encoder)
1117 struct drm_device *dev = encoder->base.dev;
1118 struct drm_i915_private *dev_priv = to_i915(dev);
1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1120 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1123 temp = I915_READ(intel_hdmi->hdmi_reg);
1125 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1126 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1127 POSTING_READ(intel_hdmi->hdmi_reg);
1130 * HW workaround for IBX, we need to move the port
1131 * to transcoder A after disabling it to allow the
1132 * matching DP port to be enabled on transcoder A.
1134 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1136 * We get CPU/PCH FIFO underruns on the other pipe when
1137 * doing the workaround. Sweep them under the rug.
1139 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1140 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1142 temp &= ~SDVO_PIPE_B_SELECT;
1143 temp |= SDVO_ENABLE;
1145 * HW workaround, need to write this twice for issue
1146 * that may result in first write getting masked.
1148 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1149 POSTING_READ(intel_hdmi->hdmi_reg);
1150 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1151 POSTING_READ(intel_hdmi->hdmi_reg);
1153 temp &= ~SDVO_ENABLE;
1154 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1155 POSTING_READ(intel_hdmi->hdmi_reg);
1157 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
1158 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1159 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1162 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1164 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1167 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1169 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1171 if (crtc->config->has_audio)
1172 intel_audio_codec_disable(encoder);
1174 intel_disable_hdmi(encoder);
1177 static void pch_disable_hdmi(struct intel_encoder *encoder)
1179 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1181 if (crtc->config->has_audio)
1182 intel_audio_codec_disable(encoder);
1185 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1187 intel_disable_hdmi(encoder);
1190 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1192 if (IS_G4X(dev_priv))
1194 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1200 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1201 bool respect_downstream_limits)
1203 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1204 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1206 if (respect_downstream_limits) {
1207 if (hdmi->dp_dual_mode.max_tmds_clock)
1208 max_tmds_clock = min(max_tmds_clock,
1209 hdmi->dp_dual_mode.max_tmds_clock);
1210 if (!hdmi->has_hdmi_sink)
1211 max_tmds_clock = min(max_tmds_clock, 165000);
1214 return max_tmds_clock;
1217 static enum drm_mode_status
1218 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1219 int clock, bool respect_downstream_limits)
1221 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1224 return MODE_CLOCK_LOW;
1225 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
1226 return MODE_CLOCK_HIGH;
1228 /* BXT DPLL can't generate 223-240 MHz */
1229 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1230 return MODE_CLOCK_RANGE;
1232 /* CHV DPLL can't generate 216-240 MHz */
1233 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1234 return MODE_CLOCK_RANGE;
1239 static enum drm_mode_status
1240 intel_hdmi_mode_valid(struct drm_connector *connector,
1241 struct drm_display_mode *mode)
1243 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1245 enum drm_mode_status status;
1247 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1249 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1250 return MODE_NO_DBLESCAN;
1252 clock = mode->clock;
1254 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1257 if (clock > max_dotclk)
1258 return MODE_CLOCK_HIGH;
1260 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1263 /* check if we can do 8bpc */
1264 status = hdmi_port_clock_valid(hdmi, clock, true);
1266 /* if we can't do 8bpc we may still be able to do 12bpc */
1267 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1268 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1273 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1275 struct drm_device *dev = crtc_state->base.crtc->dev;
1277 if (HAS_GMCH_DISPLAY(dev))
1281 * HDMI 12bpc affects the clocks, so it's only possible
1282 * when not cloning with other encoder types.
1284 return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI;
1287 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1288 struct intel_crtc_state *pipe_config)
1290 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1291 struct drm_device *dev = encoder->base.dev;
1292 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1293 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1294 int clock_12bpc = clock_8bpc * 3 / 2;
1297 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1299 if (pipe_config->has_hdmi_sink)
1300 pipe_config->has_infoframe = true;
1302 if (intel_hdmi->color_range_auto) {
1303 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1304 pipe_config->limited_color_range =
1305 pipe_config->has_hdmi_sink &&
1306 drm_match_cea_mode(adjusted_mode) > 1;
1308 pipe_config->limited_color_range =
1309 intel_hdmi->limited_color_range;
1312 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1313 pipe_config->pixel_multiplier = 2;
1318 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1319 pipe_config->has_pch_encoder = true;
1321 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1322 pipe_config->has_audio = true;
1325 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1326 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1327 * outputs. We also need to check that the higher clock still fits
1330 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1331 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
1332 hdmi_12bpc_possible(pipe_config)) {
1333 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1336 /* Need to adjust the port link by 1.5x for 12bpc. */
1337 pipe_config->port_clock = clock_12bpc;
1339 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1342 pipe_config->port_clock = clock_8bpc;
1345 if (!pipe_config->bw_constrained) {
1346 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1347 pipe_config->pipe_bpp = desired_bpp;
1350 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1351 false) != MODE_OK) {
1352 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1356 /* Set user selected PAR to incoming mode's member */
1357 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1359 pipe_config->lane_count = 4;
1365 intel_hdmi_unset_edid(struct drm_connector *connector)
1367 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1369 intel_hdmi->has_hdmi_sink = false;
1370 intel_hdmi->has_audio = false;
1371 intel_hdmi->rgb_quant_range_selectable = false;
1373 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1374 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1376 kfree(to_intel_connector(connector)->detect_edid);
1377 to_intel_connector(connector)->detect_edid = NULL;
1381 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1383 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1384 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1385 enum port port = hdmi_to_dig_port(hdmi)->port;
1386 struct i2c_adapter *adapter =
1387 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1388 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1391 * Type 1 DVI adaptors are not required to implement any
1392 * registers, so we can't always detect their presence.
1393 * Ideally we should be able to check the state of the
1394 * CONFIG1 pin, but no such luck on our hardware.
1396 * The only method left to us is to check the VBT to see
1397 * if the port is a dual mode capable DP port. But let's
1398 * only do that when we sucesfully read the EDID, to avoid
1399 * confusing log messages about DP dual mode adaptors when
1400 * there's nothing connected to the port.
1402 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1404 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1405 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1406 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1408 type = DRM_DP_DUAL_MODE_NONE;
1412 if (type == DRM_DP_DUAL_MODE_NONE)
1415 hdmi->dp_dual_mode.type = type;
1416 hdmi->dp_dual_mode.max_tmds_clock =
1417 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1419 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1420 drm_dp_get_dual_mode_type_name(type),
1421 hdmi->dp_dual_mode.max_tmds_clock);
1425 intel_hdmi_set_edid(struct drm_connector *connector, bool force)
1427 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1428 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1429 struct edid *edid = NULL;
1430 bool connected = false;
1433 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1435 edid = drm_get_edid(connector,
1436 intel_gmbus_get_adapter(dev_priv,
1437 intel_hdmi->ddc_bus));
1439 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1441 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1444 to_intel_connector(connector)->detect_edid = edid;
1445 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1446 intel_hdmi->rgb_quant_range_selectable =
1447 drm_rgb_quant_range_selectable(edid);
1449 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1450 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1451 intel_hdmi->has_audio =
1452 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1454 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1455 intel_hdmi->has_hdmi_sink =
1456 drm_detect_hdmi_monitor(edid);
1464 static enum drm_connector_status
1465 intel_hdmi_detect(struct drm_connector *connector, bool force)
1467 enum drm_connector_status status;
1468 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1469 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1470 bool live_status = false;
1473 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1474 connector->base.id, connector->name);
1476 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1478 for (try = 0; !live_status && try < 9; try++) {
1481 live_status = intel_digital_port_connected(dev_priv,
1482 hdmi_to_dig_port(intel_hdmi));
1486 DRM_DEBUG_KMS("HDMI live status down\n");
1488 * Live status register is not reliable on all intel platforms.
1489 * So consider live_status only for certain platforms, for
1490 * others, read EDID to determine presence of sink.
1492 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1496 intel_hdmi_unset_edid(connector);
1498 if (intel_hdmi_set_edid(connector, live_status)) {
1499 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1501 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1502 status = connector_status_connected;
1504 status = connector_status_disconnected;
1506 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1512 intel_hdmi_force(struct drm_connector *connector)
1514 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1516 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1517 connector->base.id, connector->name);
1519 intel_hdmi_unset_edid(connector);
1521 if (connector->status != connector_status_connected)
1524 intel_hdmi_set_edid(connector, true);
1525 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1528 static int intel_hdmi_get_modes(struct drm_connector *connector)
1532 edid = to_intel_connector(connector)->detect_edid;
1536 return intel_connector_update_modes(connector, edid);
1540 intel_hdmi_detect_audio(struct drm_connector *connector)
1542 bool has_audio = false;
1545 edid = to_intel_connector(connector)->detect_edid;
1546 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1547 has_audio = drm_detect_monitor_audio(edid);
1553 intel_hdmi_set_property(struct drm_connector *connector,
1554 struct drm_property *property,
1557 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1558 struct intel_digital_port *intel_dig_port =
1559 hdmi_to_dig_port(intel_hdmi);
1560 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1563 ret = drm_object_property_set_value(&connector->base, property, val);
1567 if (property == dev_priv->force_audio_property) {
1568 enum hdmi_force_audio i = val;
1571 if (i == intel_hdmi->force_audio)
1574 intel_hdmi->force_audio = i;
1576 if (i == HDMI_AUDIO_AUTO)
1577 has_audio = intel_hdmi_detect_audio(connector);
1579 has_audio = (i == HDMI_AUDIO_ON);
1581 if (i == HDMI_AUDIO_OFF_DVI)
1582 intel_hdmi->has_hdmi_sink = 0;
1584 intel_hdmi->has_audio = has_audio;
1588 if (property == dev_priv->broadcast_rgb_property) {
1589 bool old_auto = intel_hdmi->color_range_auto;
1590 bool old_range = intel_hdmi->limited_color_range;
1593 case INTEL_BROADCAST_RGB_AUTO:
1594 intel_hdmi->color_range_auto = true;
1596 case INTEL_BROADCAST_RGB_FULL:
1597 intel_hdmi->color_range_auto = false;
1598 intel_hdmi->limited_color_range = false;
1600 case INTEL_BROADCAST_RGB_LIMITED:
1601 intel_hdmi->color_range_auto = false;
1602 intel_hdmi->limited_color_range = true;
1608 if (old_auto == intel_hdmi->color_range_auto &&
1609 old_range == intel_hdmi->limited_color_range)
1615 if (property == connector->dev->mode_config.aspect_ratio_property) {
1617 case DRM_MODE_PICTURE_ASPECT_NONE:
1618 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1620 case DRM_MODE_PICTURE_ASPECT_4_3:
1621 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1623 case DRM_MODE_PICTURE_ASPECT_16_9:
1624 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1635 if (intel_dig_port->base.base.crtc)
1636 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1641 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1643 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1644 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1645 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1647 intel_hdmi_prepare(encoder);
1649 intel_hdmi->set_infoframes(&encoder->base,
1650 intel_crtc->config->has_hdmi_sink,
1654 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1656 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1657 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1658 struct drm_device *dev = encoder->base.dev;
1659 struct drm_i915_private *dev_priv = to_i915(dev);
1660 struct intel_crtc *intel_crtc =
1661 to_intel_crtc(encoder->base.crtc);
1662 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1664 vlv_phy_pre_encoder_enable(encoder);
1667 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1670 intel_hdmi->set_infoframes(&encoder->base,
1671 intel_crtc->config->has_hdmi_sink,
1674 g4x_enable_hdmi(encoder);
1676 vlv_wait_port_ready(dev_priv, dport, 0x0);
1679 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1681 intel_hdmi_prepare(encoder);
1683 vlv_phy_pre_pll_enable(encoder);
1686 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1688 intel_hdmi_prepare(encoder);
1690 chv_phy_pre_pll_enable(encoder);
1693 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1695 chv_phy_post_pll_disable(encoder);
1698 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1700 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1701 vlv_phy_reset_lanes(encoder);
1704 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1706 struct drm_device *dev = encoder->base.dev;
1707 struct drm_i915_private *dev_priv = to_i915(dev);
1709 mutex_lock(&dev_priv->sb_lock);
1711 /* Assert data lane reset */
1712 chv_data_lane_soft_reset(encoder, true);
1714 mutex_unlock(&dev_priv->sb_lock);
1717 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1719 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1720 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1721 struct drm_device *dev = encoder->base.dev;
1722 struct drm_i915_private *dev_priv = to_i915(dev);
1723 struct intel_crtc *intel_crtc =
1724 to_intel_crtc(encoder->base.crtc);
1725 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1727 chv_phy_pre_encoder_enable(encoder);
1729 /* FIXME: Program the support xxx V-dB */
1731 chv_set_phy_signal_level(encoder, 128, 102, false);
1733 intel_hdmi->set_infoframes(&encoder->base,
1734 intel_crtc->config->has_hdmi_sink,
1737 g4x_enable_hdmi(encoder);
1739 vlv_wait_port_ready(dev_priv, dport, 0x0);
1741 /* Second common lane will stay alive on its own now */
1742 chv_phy_release_cl2_override(encoder);
1745 static void intel_hdmi_destroy(struct drm_connector *connector)
1747 kfree(to_intel_connector(connector)->detect_edid);
1748 drm_connector_cleanup(connector);
1752 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1753 .dpms = drm_atomic_helper_connector_dpms,
1754 .detect = intel_hdmi_detect,
1755 .force = intel_hdmi_force,
1756 .fill_modes = drm_helper_probe_single_connector_modes,
1757 .set_property = intel_hdmi_set_property,
1758 .atomic_get_property = intel_connector_atomic_get_property,
1759 .late_register = intel_connector_register,
1760 .early_unregister = intel_connector_unregister,
1761 .destroy = intel_hdmi_destroy,
1762 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1763 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1766 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1767 .get_modes = intel_hdmi_get_modes,
1768 .mode_valid = intel_hdmi_mode_valid,
1771 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1772 .destroy = intel_encoder_destroy,
1776 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1778 intel_attach_force_audio_property(connector);
1779 intel_attach_broadcast_rgb_property(connector);
1780 intel_hdmi->color_range_auto = true;
1781 intel_attach_aspect_ratio_property(connector);
1782 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1785 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1786 struct intel_connector *intel_connector)
1788 struct drm_connector *connector = &intel_connector->base;
1789 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1790 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1791 struct drm_device *dev = intel_encoder->base.dev;
1792 struct drm_i915_private *dev_priv = to_i915(dev);
1793 enum port port = intel_dig_port->port;
1794 uint8_t alternate_ddc_pin;
1796 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
1799 if (WARN(intel_dig_port->max_lanes < 4,
1800 "Not enough lanes (%d) for HDMI on port %c\n",
1801 intel_dig_port->max_lanes, port_name(port)))
1804 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1805 DRM_MODE_CONNECTOR_HDMIA);
1806 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1808 connector->interlace_allowed = 1;
1809 connector->doublescan_allowed = 0;
1810 connector->stereo_allowed = 1;
1814 if (IS_BROXTON(dev_priv))
1815 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1817 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1819 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1820 * interrupts to check the external panel connection.
1822 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1823 intel_encoder->hpd_pin = HPD_PORT_A;
1825 intel_encoder->hpd_pin = HPD_PORT_B;
1828 if (IS_BROXTON(dev_priv))
1829 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1831 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1832 intel_encoder->hpd_pin = HPD_PORT_C;
1835 if (WARN_ON(IS_BROXTON(dev_priv)))
1836 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1837 else if (IS_CHERRYVIEW(dev_priv))
1838 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1840 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1841 intel_encoder->hpd_pin = HPD_PORT_D;
1844 /* On SKL PORT E doesn't have seperate GMBUS pin
1845 * We rely on VBT to set a proper alternate GMBUS pin. */
1847 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
1848 switch (alternate_ddc_pin) {
1850 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1853 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1856 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1859 MISSING_CASE(alternate_ddc_pin);
1861 intel_encoder->hpd_pin = HPD_PORT_E;
1864 intel_encoder->hpd_pin = HPD_PORT_A;
1865 /* Internal port only for eDP. */
1870 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1871 intel_hdmi->write_infoframe = vlv_write_infoframe;
1872 intel_hdmi->set_infoframes = vlv_set_infoframes;
1873 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
1874 } else if (IS_G4X(dev)) {
1875 intel_hdmi->write_infoframe = g4x_write_infoframe;
1876 intel_hdmi->set_infoframes = g4x_set_infoframes;
1877 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
1878 } else if (HAS_DDI(dev)) {
1879 intel_hdmi->write_infoframe = hsw_write_infoframe;
1880 intel_hdmi->set_infoframes = hsw_set_infoframes;
1881 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
1882 } else if (HAS_PCH_IBX(dev)) {
1883 intel_hdmi->write_infoframe = ibx_write_infoframe;
1884 intel_hdmi->set_infoframes = ibx_set_infoframes;
1885 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
1887 intel_hdmi->write_infoframe = cpt_write_infoframe;
1888 intel_hdmi->set_infoframes = cpt_set_infoframes;
1889 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
1893 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1895 intel_connector->get_hw_state = intel_connector_get_hw_state;
1897 intel_hdmi_add_properties(intel_hdmi, connector);
1899 intel_connector_attach_encoder(intel_connector, intel_encoder);
1900 intel_hdmi->attached_connector = intel_connector;
1902 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1903 * 0xd. Failure to do so will result in spurious interrupts being
1904 * generated on the port when a cable is not attached.
1906 if (IS_G4X(dev) && !IS_GM45(dev)) {
1907 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1908 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1912 void intel_hdmi_init(struct drm_device *dev,
1913 i915_reg_t hdmi_reg, enum port port)
1915 struct intel_digital_port *intel_dig_port;
1916 struct intel_encoder *intel_encoder;
1917 struct intel_connector *intel_connector;
1919 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1920 if (!intel_dig_port)
1923 intel_connector = intel_connector_alloc();
1924 if (!intel_connector) {
1925 kfree(intel_dig_port);
1929 intel_encoder = &intel_dig_port->base;
1931 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1932 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
1934 intel_encoder->compute_config = intel_hdmi_compute_config;
1935 if (HAS_PCH_SPLIT(dev)) {
1936 intel_encoder->disable = pch_disable_hdmi;
1937 intel_encoder->post_disable = pch_post_disable_hdmi;
1939 intel_encoder->disable = g4x_disable_hdmi;
1941 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1942 intel_encoder->get_config = intel_hdmi_get_config;
1943 if (IS_CHERRYVIEW(dev)) {
1944 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1945 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1946 intel_encoder->enable = vlv_enable_hdmi;
1947 intel_encoder->post_disable = chv_hdmi_post_disable;
1948 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
1949 } else if (IS_VALLEYVIEW(dev)) {
1950 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1951 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1952 intel_encoder->enable = vlv_enable_hdmi;
1953 intel_encoder->post_disable = vlv_hdmi_post_disable;
1955 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1956 if (HAS_PCH_CPT(dev))
1957 intel_encoder->enable = cpt_enable_hdmi;
1958 else if (HAS_PCH_IBX(dev))
1959 intel_encoder->enable = ibx_enable_hdmi;
1961 intel_encoder->enable = g4x_enable_hdmi;
1964 intel_encoder->type = INTEL_OUTPUT_HDMI;
1965 if (IS_CHERRYVIEW(dev)) {
1967 intel_encoder->crtc_mask = 1 << 2;
1969 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1971 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1973 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1975 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1976 * to work on real hardware. And since g4x can send infoframes to
1977 * only one port anyway, nothing is lost by allowing it.
1980 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1982 intel_dig_port->port = port;
1983 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1984 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
1985 intel_dig_port->max_lanes = 4;
1987 intel_hdmi_init_connector(intel_dig_port, intel_connector);