drivers/gpu/drm/i915/intel_guc_loader.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Vinit Azad <vinit.azad@intel.com>
  25  *    Ben Widawsky <ben@bwidawsk.net>
  26  *    Dave Gordon <david.s.gordon@intel.com>
  27  *    Alex Dai <yu.dai@intel.com>
  28  */
  29 #include <linux/firmware.h>
  30 #include "i915_drv.h"
  31 #include "intel_guc.h"
  32
  33 /**
  34  * DOC: GuC
  35  *
  36  * intel_guc:
  37  * Top level structure of guc. It handles firmware loading and manages client
  38  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  39  * ExecList submission.
  40  *
  41  * Firmware versioning:
  42  * The firmware build process will generate a version header file with major and
  43  * minor version defined. The versions are built into CSS header of firmware.
  44  * i915 kernel driver set the minimal firmware version required per platform.
  45  * The firmware installation package will install (symbolic link) proper version
  46  * of firmware.
  47  *
  48  * GuC address space:
  49  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  50  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  51  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  52  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  53  *
  54  * Firmware log:
  55  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  56  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  57  * i915_guc_load_status will print out firmware loading status and scratch
  58  * registers value.
  59  *
  60  */
  61
  62 #define I915_SKL_GUC_UCODE "i915/skl_guc_ver3.bin"
  63 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  64
  65 /* User-friendly representation of an enum */
  66 const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  67 {
  68         switch (status) {
  69         case GUC_FIRMWARE_FAIL:
  70                 return "FAIL";
  71         case GUC_FIRMWARE_NONE:
  72                 return "NONE";
  73         case GUC_FIRMWARE_PENDING:
  74                 return "PENDING";
  75         case GUC_FIRMWARE_SUCCESS:
  76                 return "SUCCESS";
  77         default:
  78                 return "UNKNOWN!";
  79         }
  80 };
  81
  82 static u32 get_gttype(struct drm_i915_private *dev_priv)
  83 {
  84         /* XXX: GT type based on PCI device ID? field seems unused by fw */
  85         return 0;
  86 }
  87
  88 static u32 get_core_family(struct drm_i915_private *dev_priv)
  89 {
  90         switch (INTEL_INFO(dev_priv)->gen) {
  91         case 9:
  92                 return GFXCORE_FAMILY_GEN9;
  93
  94         default:
  95                 DRM_ERROR("GUC: unsupported core family\n");
  96                 return GFXCORE_FAMILY_UNKNOWN;
  97         }
  98 }
  99
 100 static void set_guc_init_params(struct drm_i915_private *dev_priv)
 101 {
 102         struct intel_guc *guc = &dev_priv->guc;
 103         u32 params[GUC_CTL_MAX_DWORDS];
 104         int i;
 105
 106         memset(&params, 0, sizeof(params));
 107
 108         params[GUC_CTL_DEVICE_INFO] |=
 109                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
 110                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
 111
 112         /*
 113          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 114          * second. This ARAR is calculated by:
 115          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 116          */
 117         params[GUC_CTL_ARAT_HIGH] = 0;
 118         params[GUC_CTL_ARAT_LOW] = 100000000;
 119
 120         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 121
 122         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 123                         GUC_CTL_VCS2_ENABLED;
 124
 125         if (i915.guc_log_level >= 0) {
 126                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
 127                 params[GUC_CTL_DEBUG] =
 128                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 129         }
 130
 131         /* If GuC submission is enabled, set up additional parameters here */
 132         if (i915.enable_guc_submission) {
 133                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
 134                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
 135
 136                 pgs >>= PAGE_SHIFT;
 137                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 138                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 139
 140                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 141
 142                 /* Unmask this bit to enable the GuC's internal scheduler */
 143                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 144         }
 145
 146         I915_WRITE(SOFT_SCRATCH(0), 0);
 147
 148         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 149                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 150 }
 151
 152 /*
 153  * Read the GuC status register (GUC_STATUS) and store it in the
 154  * specified location; then return a boolean indicating whether
 155  * the value matches either of two values representing completion
 156  * of the GuC boot process.
 157  *
 158  * This is used for polling the GuC status in a wait_for_atomic()
 159  * loop below.
 160  */
 161 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
 162                                       u32 *status)
 163 {
 164         u32 val = I915_READ(GUC_STATUS);
 165         *status = val;
 166         return ((val & GS_UKERNEL_MASK) == GS_UKERNEL_READY ||
 167                 (val & GS_UKERNEL_MASK) == GS_UKERNEL_LAPIC_DONE);
 168 }
 169
 170 /*
 171  * Transfer the firmware image to RAM for execution by the microcontroller.
 172  *
 173  * GuC Firmware layout:
 174  * +-------------------------------+  ----
 175  * |          CSS header           |  128B
 176  * | contains major/minor version  |
 177  * +-------------------------------+  ----
 178  * |             uCode             |
 179  * +-------------------------------+  ----
 180  * |         RSA signature         |  256B
 181  * +-------------------------------+  ----
 182  * |         RSA public Key        |  256B
 183  * +-------------------------------+  ----
 184  * |       Public key modulus      |    4B
 185  * +-------------------------------+  ----
 186  *
 187  * Architecturally, the DMA engine is bidirectional, and can potentially even
 188  * transfer between GTT locations. This functionality is left out of the API
 189  * for now as there is no need for it.
 190  *
 191  * Note that GuC needs the CSS header plus uKernel code to be copied by the
 192  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
 193  */
 194
 195 #define UOS_CSS_HEADER_OFFSET           0
 196 #define UOS_VER_MINOR_OFFSET            0x44
 197 #define UOS_VER_MAJOR_OFFSET            0x46
 198 #define UOS_CSS_HEADER_SIZE             0x80
 199 #define UOS_RSA_SIG_SIZE                0x100
 200 #define UOS_CSS_SIGNING_SIZE            0x204
 201
 202 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
 203 {
 204         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 205         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
 206         unsigned long offset;
 207         struct sg_table *sg = fw_obj->pages;
 208         u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
 209         int i, ret = 0;
 210
 211         /* uCode size, also is where RSA signature starts */
 212         offset = ucode_size = guc_fw->guc_fw_size - UOS_CSS_SIGNING_SIZE;
 213         I915_WRITE(DMA_COPY_SIZE, ucode_size);
 214
 215         /* Copy RSA signature from the fw image to HW for verification */
 216         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
 217         for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
 218                 I915_WRITE(UOS_RSA_SCRATCH_0 + i * sizeof(u32), rsa[i]);
 219
 220         /* Set the source address for the new blob */
 221         offset = i915_gem_obj_ggtt_offset(fw_obj);
 222         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 223         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 224
 225         /*
 226          * Set the DMA destination. Current uCode expects the code to be
 227          * loaded at 8k; locations below this are used for the stack.
 228          */
 229         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
 230         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 231
 232         /* Finally start the DMA */
 233         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 234
 235         /*
 236          * Spin-wait for the DMA to complete & the GuC to start up.
 237          * NB: Docs recommend not using the interrupt for completion.
 238          * Measurements indicate this should take no more than 20ms, so a
 239          * timeout here indicates that the GuC has failed and is unusable.
 240          * (Higher levels of the driver will attempt to fall back to
 241          * execlist mode if this happens.)
 242          */
 243         ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
 244
 245         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 246                         I915_READ(DMA_CTRL), status);
 247
 248         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 249                 DRM_ERROR("GuC firmware signature verification failed\n");
 250                 ret = -ENOEXEC;
 251         }
 252
 253         DRM_DEBUG_DRIVER("returning %d\n", ret);
 254
 255         return ret;
 256 }
 257
 258 /*
 259  * Load the GuC firmware blob into the MinuteIA.
 260  */
 261 static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 262 {
 263         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 264         struct drm_device *dev = dev_priv->dev;
 265         int ret;
 266
 267         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
 268         if (ret) {
 269                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
 270                 return ret;
 271         }
 272
 273         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
 274         if (ret) {
 275                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
 276                 return ret;
 277         }
 278
 279         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
 280         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 281
 282         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 283
 284         /* init WOPCM */
 285         I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
 286         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 287
 288         /* Enable MIA caching. GuC clock gating is disabled. */
 289         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 290
 291         /* WaC6DisallowByGfxPause*/
 292         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 293
 294         if (IS_BROXTON(dev))
 295                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 296         else
 297                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
 298
 299         if (IS_GEN9(dev)) {
 300                 /* DOP Clock Gating Enable for GuC clocks */
 301                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
 302                                             I915_READ(GEN7_MISCCPCTL)));
 303
 304                 /* allows for 5us before GT can go to RC6 */
 305                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
 306         }
 307
 308         set_guc_init_params(dev_priv);
 309
 310         ret = guc_ucode_xfer_dma(dev_priv);
 311
 312         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 313
 314         /*
 315          * We keep the object pages for reuse during resume. But we can unpin it
 316          * now that DMA has completed, so it doesn't continue to take up space.
 317          */
 318         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
 319
 320         return ret;
 321 }
 322
 323 /**
 324  * intel_guc_ucode_load() - load GuC uCode into the device
 325  * @dev:        drm device
 326  *
 327  * Called from gem_init_hw() during driver loading and also after a GPU reset.
 328  *
 329  * The firmware image should have already been fetched into memory by the
 330  * earlier call to intel_guc_ucode_init(), so here we need only check that
 331  * is succeeded, and then transfer the image to the h/w.
 332  *
 333  * Return:      non-zero code on error
 334  */
 335 int intel_guc_ucode_load(struct drm_device *dev)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 339         int err = 0;
 340
 341         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 342                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 343                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 344
 345         i915_guc_submission_disable(dev);
 346
 347         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
 348                 return 0;
 349
 350         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
 351             guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
 352                 return -ENOEXEC;
 353
 354         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
 355
 356         DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
 357                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 358
 359         switch (guc_fw->guc_fw_fetch_status) {
 360         case GUC_FIRMWARE_FAIL:
 361                 /* something went wrong :( */
 362                 err = -EIO;
 363                 goto fail;
 364
 365         case GUC_FIRMWARE_NONE:
 366         case GUC_FIRMWARE_PENDING:
 367         default:
 368                 /* "can't happen" */
 369                 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
 370                         guc_fw->guc_fw_path,
 371                         intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 372                         guc_fw->guc_fw_fetch_status);
 373                 err = -ENXIO;
 374                 goto fail;
 375
 376         case GUC_FIRMWARE_SUCCESS:
 377                 break;
 378         }
 379
 380         err = i915_guc_submission_init(dev);
 381         if (err)
 382                 goto fail;
 383
 384         err = guc_ucode_xfer(dev_priv);
 385         if (err)
 386                 goto fail;
 387
 388         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
 389
 390         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
 391                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
 392                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
 393
 394         if (i915.enable_guc_submission) {
 395                 err = i915_guc_submission_enable(dev);
 396                 if (err)
 397                         goto fail;
 398         }
 399
 400         return 0;
 401
 402 fail:
 403         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
 404                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
 405
 406         i915_guc_submission_disable(dev);
 407
 408         return err;
 409 }
 410
 411 static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 412 {
 413         struct drm_i915_gem_object *obj;
 414         const struct firmware *fw;
 415         const u8 *css_header;
 416         const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_CSS_SIGNING_SIZE;
 417         const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_CSS_SIGNING_SIZE
 418                         - 0x8000; /* 32k reserved (8K stack + 24k context) */
 419         int err;
 420
 421         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
 422                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
 423
 424         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
 425         if (err)
 426                 goto fail;
 427         if (!fw)
 428                 goto fail;
 429
 430         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
 431                 guc_fw->guc_fw_path, fw);
 432         DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
 433                 fw->size, minsize, maxsize);
 434
 435         /* Check the size of the blob befoe examining buffer contents */
 436         if (fw->size < minsize || fw->size > maxsize)
 437                 goto fail;
 438
 439         /*
 440          * The GuC firmware image has the version number embedded at a well-known
 441          * offset within the firmware blob; note that major / minor version are
 442          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
 443          * in terms of bytes (u8).
 444          */
 445         css_header = fw->data + UOS_CSS_HEADER_OFFSET;
 446         guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
 447         guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
 448
 449         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
 450             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
 451                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
 452                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 453                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 454                 err = -ENOEXEC;
 455                 goto fail;
 456         }
 457
 458         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
 459                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
 460                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
 461
 462         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
 463         if (IS_ERR_OR_NULL(obj)) {
 464                 err = obj ? PTR_ERR(obj) : -ENOMEM;
 465                 goto fail;
 466         }
 467
 468         guc_fw->guc_fw_obj = obj;
 469         guc_fw->guc_fw_size = fw->size;
 470
 471         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
 472                         guc_fw->guc_fw_obj);
 473
 474         release_firmware(fw);
 475         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
 476         return;
 477
 478 fail:
 479         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
 480                 err, fw, guc_fw->guc_fw_obj);
 481         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
 482                   guc_fw->guc_fw_path, err);
 483
 484         obj = guc_fw->guc_fw_obj;
 485         if (obj)
 486                 drm_gem_object_unreference(&obj->base);
 487         guc_fw->guc_fw_obj = NULL;
 488
 489         release_firmware(fw);           /* OK even if fw is NULL */
 490         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 491 }
 492
 493 /**
 494  * intel_guc_ucode_init() - define parameters and fetch firmware
 495  * @dev:        drm device
 496  *
 497  * Called early during driver load, but after GEM is initialised.
 498  * The device struct_mutex must be held by the caller, as we're
 499  * going to allocate a GEM object to hold the firmware image.
 500  *
 501  * The firmware will be transferred to the GuC's memory later,
 502  * when intel_guc_ucode_load() is called.
 503  */
 504 void intel_guc_ucode_init(struct drm_device *dev)
 505 {
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 508         const char *fw_path;
 509
 510         if (!HAS_GUC_SCHED(dev))
 511                 i915.enable_guc_submission = false;
 512
 513         if (!HAS_GUC_UCODE(dev)) {
 514                 fw_path = NULL;
 515         } else if (IS_SKYLAKE(dev)) {
 516                 fw_path = I915_SKL_GUC_UCODE;
 517                 guc_fw->guc_fw_major_wanted = 3;
 518                 guc_fw->guc_fw_minor_wanted = 0;
 519         } else {
 520                 i915.enable_guc_submission = false;
 521                 fw_path = "";   /* unknown device */
 522         }
 523
 524         guc_fw->guc_dev = dev;
 525         guc_fw->guc_fw_path = fw_path;
 526         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 527         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
 528
 529         if (fw_path == NULL)
 530                 return;
 531
 532         if (*fw_path == '\0') {
 533                 DRM_ERROR("No GuC firmware known for this platform\n");
 534                 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
 535                 return;
 536         }
 537
 538         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
 539         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
 540         guc_fw_fetch(dev, guc_fw);
 541         /* status must now be FAIL or SUCCESS */
 542 }
 543
 544 /**
 545  * intel_guc_ucode_fini() - clean up all allocated resources
 546  * @dev:        drm device
 547  */
 548 void intel_guc_ucode_fini(struct drm_device *dev)
 549 {
 550         struct drm_i915_private *dev_priv = dev->dev_private;
 551         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
 552
 553         i915_guc_submission_fini(dev);
 554
 555         if (guc_fw->guc_fw_obj)
 556                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
 557         guc_fw->guc_fw_obj = NULL;
 558
 559         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
 560 }