2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #ifndef _INTEL_GUC_FWIF_H
24 #define _INTEL_GUC_FWIF_H
26 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
27 #define GUC_CLIENT_PRIORITY_HIGH 1
28 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
29 #define GUC_CLIENT_PRIORITY_NORMAL 3
30 #define GUC_CLIENT_PRIORITY_NUM 4
32 #define GUC_MAX_STAGE_DESCRIPTORS 1024
33 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
35 #define GUC_RENDER_ENGINE 0
36 #define GUC_VIDEO_ENGINE 1
37 #define GUC_BLITTER_ENGINE 2
38 #define GUC_VIDEOENHANCE_ENGINE 3
39 #define GUC_VIDEO_ENGINE2 4
40 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
42 /* Work queue item header definitions */
43 #define WQ_STATUS_ACTIVE 1
44 #define WQ_STATUS_SUSPENDED 2
45 #define WQ_STATUS_CMD_ERROR 3
46 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
47 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
48 #define WQ_TYPE_SHIFT 0
49 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
50 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
51 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
52 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
53 #define WQ_TARGET_SHIFT 10
54 #define WQ_LEN_SHIFT 16
55 #define WQ_NO_WCFLUSH_WAIT (1 << 27)
56 #define WQ_PRESENT_WORKLOAD (1 << 28)
58 #define WQ_RING_TAIL_SHIFT 20
59 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
60 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
62 #define GUC_DOORBELL_ENABLED 1
63 #define GUC_DOORBELL_DISABLED 0
65 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
66 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
67 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
68 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
69 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
70 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
71 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
72 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
74 /* The guc control data is 10 DWORDs */
75 #define GUC_CTL_CTXINFO 0
76 #define GUC_CTL_CTXNUM_IN16_SHIFT 0
77 #define GUC_CTL_BASE_ADDR_SHIFT 12
79 #define GUC_CTL_ARAT_HIGH 1
80 #define GUC_CTL_ARAT_LOW 2
82 #define GUC_CTL_DEVICE_INFO 3
84 #define GUC_CTL_LOG_PARAMS 4
85 #define GUC_LOG_VALID (1 << 0)
86 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
87 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
88 #define GUC_LOG_CRASH_SHIFT 4
89 #define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
90 #define GUC_LOG_DPC_SHIFT 6
91 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
92 #define GUC_LOG_ISR_SHIFT 9
93 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
94 #define GUC_LOG_BUF_ADDR_SHIFT 12
96 #define GUC_CTL_PAGE_FAULT_CONTROL 5
99 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
101 #define GUC_CTL_FEATURE 7
102 #define GUC_CTL_VCS2_ENABLED (1 << 0)
103 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
104 #define GUC_CTL_FEATURE2 (1 << 2)
105 #define GUC_CTL_POWER_GATING (1 << 3)
106 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
107 #define GUC_CTL_PREEMPTION_LOG (1 << 5)
108 #define GUC_CTL_ENABLE_SLPC (1 << 7)
109 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
111 #define GUC_CTL_DEBUG 8
112 #define GUC_LOG_VERBOSITY_SHIFT 0
113 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
114 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
115 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
116 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
117 /* Verbosity range-check limits, without the shift */
118 #define GUC_LOG_VERBOSITY_MIN 0
119 #define GUC_LOG_VERBOSITY_MAX 3
120 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
121 #define GUC_LOG_DESTINATION_MASK (3 << 4)
122 #define GUC_LOG_DISABLED (1 << 6)
123 #define GUC_PROFILE_ENABLED (1 << 7)
124 #define GUC_WQ_TRACK_ENABLED (1 << 8)
125 #define GUC_ADS_ENABLED (1 << 9)
126 #define GUC_LOG_DEFAULT_DISABLED (1 << 10)
127 #define GUC_ADS_ADDR_SHIFT 11
128 #define GUC_ADS_ADDR_MASK 0xfffff800
130 #define GUC_CTL_RSRVD 9
132 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
135 * DOC: GuC Firmware Layout
137 * The GuC firmware layout looks like this:
139 * +-------------------------------+
142 * | contains major/minor version |
143 * +-------------------------------+
145 * +-------------------------------+
147 * +-------------------------------+
149 * +-------------------------------+
151 * +-------------------------------+
153 * The firmware may or may not have modulus key and exponent data. The header,
154 * uCode and RSA signature are must-have components that will be used by driver.
155 * Length of each components, which is all in dwords, can be found in header.
156 * In the case that modulus and exponent are not present in fw, a.k.a truncated
157 * image, the length value still appears in header.
159 * Driver will do some basic fw size validation based on the following rules:
161 * 1. Header, uCode and RSA are must-have components.
162 * 2. All firmware components, if they present, are in the sequence illustrated
163 * in the layout table above.
164 * 3. Length info of each component can be found in header, in dwords.
165 * 4. Modulus and exponent key are not required by driver. They may not appear
166 * in fw. So driver will load a truncated firmware in this case.
168 * HuC firmware layout is same as GuC firmware.
170 * HuC firmware css header is different. However, the only difference is where
171 * the version information is saved. The uc_css_header is unified to support
172 * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
173 * uc_css_header.guc_sw_version for GuC.
176 struct uc_css_header {
178 /* header_size includes all non-uCode bits, including css_header, rsa
179 * key, modulus key and exponent data. */
192 u32 size_dw; /* uCode plus header_size_dw */
195 u32 exponent_size_dw;
206 char buildnumber[12];
209 u32 branch_client_version;
222 struct guc_doorbell_info {
228 union guc_doorbell_qw {
236 #define GUC_NUM_DOORBELLS 256
237 #define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS)
239 #define GUC_DB_SIZE (PAGE_SIZE)
240 #define GUC_WQ_SIZE (PAGE_SIZE * 2)
242 /* Work item for submitting workloads into work queue of GuC. */
246 u32 submit_element_info;
250 struct guc_process_desc {
264 /* engine id and context id is packed into guc_execlist_context.context_id*/
265 #define GUC_ELC_CTXID_OFFSET 0
266 #define GUC_ELC_ENGINE_OFFSET 29
268 /* The execlist context including software and HW information */
269 struct guc_execlist_context {
276 u32 ring_next_free_location;
277 u32 ring_current_tail_pointer_value;
278 u8 engine_state_submit_value;
279 u8 engine_state_wait_value;
281 u16 engine_submit_queue_count;
285 * This structure describes a stage set arranged for a particular communication
286 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
287 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
288 * to avoid confusion with all the other things already named "context" in the
289 * driver. A static pool of these descriptors are stored inside a GEM object
290 * (stage_desc_pool) which is held for the entire lifetime of our interaction
291 * with the GuC, being allocated before the GuC is loaded with its firmware.
293 struct guc_stage_desc {
294 u32 sched_common_area;
303 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
309 u32 wq_sampled_tail_offset;
310 u32 wq_total_submit_enqueues;
327 * DOC: CTB based communication
329 * The CTB (command transport buffer) communication between Host and GuC
330 * is based on u32 data stream written to the shared buffer. One buffer can
331 * be used to transmit data only in one direction (one-directional channel).
333 * Current status of the each buffer is stored in the buffer descriptor.
334 * Buffer descriptor holds tail and head fields that represents active data
335 * stream. The tail field is updated by the data producer (sender), and head
336 * field is updated by the data consumer (receiver)::
339 * | DESCRIPTOR | +=================+============+========+
340 * +============+ | | MESSAGE(s) | |
341 * | address |--------->+=================+============+========+
343 * | head | ^-----head--------^
345 * | tail | ^---------tail-----------------^
347 * | size | ^---------------size--------------------^
350 * Each message in data stream starts with the single u32 treated as a header,
351 * followed by optional set of u32 data that makes message specific payload::
353 * +------------+---------+---------+---------+
355 * +------------+---------+---------+---------+
356 * | msg[0] | [1] | ... | [n-1] |
357 * +------------+---------+---------+---------+
358 * | MESSAGE | MESSAGE PAYLOAD |
359 * + HEADER +---------+---------+---------+
361 * +======+=====+=========+=========+=========+
362 * | 31:16| code| | | |
363 * +------+-----+ | | |
364 * | 15:5|flags| | | |
365 * +------+-----+ | | |
367 * +------+-----+---------+---------+---------+
369 * ^-------------len-------------^
371 * The message header consists of:
373 * - **len**, indicates length of the message payload (in u32)
374 * - **code**, indicates message code
375 * - **flags**, holds various bits to control message handling
379 * Describes single command transport buffer.
380 * Used by both guc-master and clients.
382 struct guc_ct_buffer_desc {
383 u32 addr; /* gfx address */
384 u64 host_private; /* host private data */
385 u32 size; /* size in bytes */
386 u32 head; /* offset updated by GuC*/
387 u32 tail; /* offset updated by owner */
388 u32 is_in_error; /* error indicator */
389 u32 fence; /* fence updated by GuC */
390 u32 status; /* status updated by GuC */
391 u32 owner; /* id of the channel owner */
392 u32 owner_sub_id; /* owner-defined field for extra tracking */
396 /* Type of command transport buffer */
397 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
398 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
401 * Definition of the command transport message header (DW0)
403 * bit[4..0] message len (in dwords)
405 * bit[8] write fence to desc
406 * bit[9] write status to H2G buff
407 * bit[10] send status (via G2H)
408 * bit[15..11] reserved
409 * bit[31..16] action code
411 #define GUC_CT_MSG_LEN_SHIFT 0
412 #define GUC_CT_MSG_LEN_MASK 0x1F
413 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
414 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
415 #define GUC_CT_MSG_SEND_STATUS (1 << 10)
416 #define GUC_CT_MSG_ACTION_SHIFT 16
417 #define GUC_CT_MSG_ACTION_MASK 0xFFFF
419 #define GUC_FORCEWAKE_RENDER (1 << 0)
420 #define GUC_FORCEWAKE_MEDIA (1 << 1)
422 #define GUC_POWER_UNSPECIFIED 0
423 #define GUC_POWER_D0 1
424 #define GUC_POWER_D1 2
425 #define GUC_POWER_D2 3
426 #define GUC_POWER_D3 4
428 /* Scheduling policy settings */
430 /* Reset engine upon preempt failure */
431 #define POLICY_RESET_ENGINE (1<<0)
432 /* Preempt to idle on quantum expiry */
433 #define POLICY_PREEMPT_TO_IDLE (1<<1)
435 #define POLICY_MAX_NUM_WI 15
436 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
437 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
438 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
439 #define POLICY_DEFAULT_FAULT_TIME_US 250000
442 /* Time for one workload to execute. (in micro seconds) */
443 u32 execution_quantum;
446 /* Time to wait for a preemption request to completed before issuing a
447 * reset. (in micro seconds). */
450 /* How much time to allow to run after the first fault is observed.
451 * Then preempt afterwards. (in micro seconds) */
458 struct guc_policies {
459 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
461 /* In micro seconds. How much time to allow before DPC processing is
462 * called back via interrupt (to prevent DPC queue drain starving).
463 * Typically 1000s of micro seconds (example only, not granularity). */
464 u32 dpc_promote_time;
466 /* Must be set to take these new values. */
469 /* Max number of WIs to process per call. A large value may keep CS
471 u32 max_num_work_items;
476 /* GuC MMIO reg state struct */
478 #define GUC_REGSET_FLAGS_NONE 0x0
479 #define GUC_REGSET_POWERCYCLE 0x1
480 #define GUC_REGSET_MASKED 0x2
481 #define GUC_REGSET_ENGINERESET 0x4
482 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
483 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
485 #define GUC_REGSET_MAX_REGISTERS 25
486 #define GUC_MMIO_WHITE_LIST_START 0x24d0
487 #define GUC_MMIO_WHITE_LIST_MAX 12
488 #define GUC_S3_SAVE_SPACE_PAGES 10
490 struct guc_mmio_regset {
495 } registers[GUC_REGSET_MAX_REGISTERS];
498 u32 number_of_registers;
501 /* MMIO registers that are set as non privileged */
502 struct mmio_white_list {
504 u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
508 struct guc_mmio_reg_state {
509 struct guc_mmio_regset global_reg;
510 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
511 struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
514 /* GuC Additional Data Struct */
518 u32 reg_state_buffer;
519 u32 golden_context_lrca;
520 u32 scheduler_policies;
522 u32 eng_state_size[GUC_MAX_ENGINES_NUM];
526 /* GuC logging structures */
528 enum guc_log_buffer_type {
531 GUC_CRASH_DUMP_LOG_BUFFER,
536 * Below state structure is used for coordination of retrieval of GuC firmware
537 * logs. Separate state is maintained for each log buffer type.
538 * read_ptr points to the location where i915 read last in log buffer and
539 * is read only for GuC firmware. write_ptr is incremented by GuC with number
540 * of bytes written for each log entry and is read only for i915.
541 * When any type of log buffer becomes half full, GuC sends a flush interrupt.
542 * GuC firmware expects that while it is writing to 2nd half of the buffer,
543 * first half would get consumed by Host and then get a flush completed
544 * acknowledgment from Host, so that it does not end up doing any overwrite
545 * causing loss of logs. So when buffer gets half filled & i915 has requested
546 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
547 * to the value of write_ptr and raise the interrupt.
548 * On receiving the interrupt i915 should read the buffer, clear flush_to_file
549 * field and also update read_ptr with the value of sample_write_ptr, before
550 * sending an acknowledgment to GuC. marker & version fields are for internal
551 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
552 * time GuC detects the log buffer overflow.
554 struct guc_log_buffer_state {
559 u32 sampled_write_ptr;
563 u32 buffer_full_cnt:4;
571 struct guc_ctx_report {
572 u32 report_return_status;
578 /* GuC Shared Context Data Struct */
579 struct guc_shared_ctx_data {
580 u32 addr_of_last_preempted_data_low;
581 u32 addr_of_last_preempted_data_high;
582 u32 addr_of_last_preempted_data_high_tmp;
584 u32 is_mapped_to_proxy;
586 u32 engine_reset_ctx_id;
587 u32 media_reset_count;
589 u32 uk_last_ctx_switch_reason;
594 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
598 * DOC: MMIO based communication
600 * The MMIO based communication between Host and GuC uses software scratch
601 * registers, where first register holds data treated as message header,
602 * and other registers are used to hold message payload.
604 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
606 * +-----------+---------+---------+---------+
607 * | MMIO[0] | MMIO[1] | ... | MMIO[n] |
608 * +-----------+---------+---------+---------+
609 * | header | optional payload |
610 * +======+====+=========+=========+=========+
611 * | 31:28|type| | | |
612 * +------+----+ | | |
613 * | 27:16|data| | | |
614 * +------+----+ | | |
616 * +------+----+---------+---------+---------+
618 * The message header consists of:
620 * - **type**, indicates message type
621 * - **code**, indicates message code, is specific for **type**
622 * - **data**, indicates message data, optional, depends on **code**
624 * The following message **types** are supported:
626 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
627 * must be priovided in **code** field. Optional action specific parameters
628 * can be provided in remaining payload registers or **data** field.
630 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
631 * action response status will be provided in **code** field. Optional
632 * response data can be returned in remaining payload registers or **data**
636 #define INTEL_GUC_MSG_TYPE_SHIFT 28
637 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
638 #define INTEL_GUC_MSG_DATA_SHIFT 16
639 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
640 #define INTEL_GUC_MSG_CODE_SHIFT 0
641 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
643 #define __INTEL_GUC_MSG_GET(T, m) \
644 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
645 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
646 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
647 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
649 enum intel_guc_msg_type {
650 INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
651 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
654 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \
655 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
656 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
657 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
659 enum intel_guc_action {
660 INTEL_GUC_ACTION_DEFAULT = 0x0,
661 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
662 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
663 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
664 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
665 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
666 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
667 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
668 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
669 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
670 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
671 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
672 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
673 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
674 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
675 INTEL_GUC_ACTION_LIMIT
678 enum intel_guc_preempt_options {
679 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
680 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
683 enum intel_guc_report_status {
684 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
685 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
686 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
687 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
690 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
691 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
692 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
693 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
695 enum intel_guc_response_status {
696 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
697 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
700 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
701 (typecheck(u32, (m)) && \
702 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
703 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
704 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
706 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
707 enum intel_guc_recv_message {
708 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
709 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)