2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 #ifndef _INTEL_GUC_FWIF_H
24 #define _INTEL_GUC_FWIF_H
26 #define GUC_CORE_FAMILY_GEN9 12
27 #define GUC_CORE_FAMILY_UNKNOWN 0x7fffffff
29 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
30 #define GUC_CLIENT_PRIORITY_HIGH 1
31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
32 #define GUC_CLIENT_PRIORITY_NORMAL 3
33 #define GUC_CLIENT_PRIORITY_NUM 4
35 #define GUC_MAX_STAGE_DESCRIPTORS 1024
36 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
38 #define GUC_RENDER_ENGINE 0
39 #define GUC_VIDEO_ENGINE 1
40 #define GUC_BLITTER_ENGINE 2
41 #define GUC_VIDEOENHANCE_ENGINE 3
42 #define GUC_VIDEO_ENGINE2 4
43 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
45 /* Work queue item header definitions */
46 #define WQ_STATUS_ACTIVE 1
47 #define WQ_STATUS_SUSPENDED 2
48 #define WQ_STATUS_CMD_ERROR 3
49 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
50 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
51 #define WQ_TYPE_SHIFT 0
52 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
53 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
54 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
55 #define WQ_TARGET_SHIFT 10
56 #define WQ_LEN_SHIFT 16
57 #define WQ_NO_WCFLUSH_WAIT (1 << 27)
58 #define WQ_PRESENT_WORKLOAD (1 << 28)
59 #define WQ_WORKLOAD_SHIFT 29
60 #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT)
61 #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT)
62 #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT)
64 #define WQ_RING_TAIL_SHIFT 20
65 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
66 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
68 #define GUC_DOORBELL_ENABLED 1
69 #define GUC_DOORBELL_DISABLED 0
71 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
72 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
73 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
74 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
75 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
76 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
77 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
78 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
80 /* The guc control data is 10 DWORDs */
81 #define GUC_CTL_CTXINFO 0
82 #define GUC_CTL_CTXNUM_IN16_SHIFT 0
83 #define GUC_CTL_BASE_ADDR_SHIFT 12
85 #define GUC_CTL_ARAT_HIGH 1
86 #define GUC_CTL_ARAT_LOW 2
88 #define GUC_CTL_DEVICE_INFO 3
89 #define GUC_CTL_GTTYPE_SHIFT 0
90 #define GUC_CTL_COREFAMILY_SHIFT 7
92 #define GUC_CTL_LOG_PARAMS 4
93 #define GUC_LOG_VALID (1 << 0)
94 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
95 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
96 #define GUC_LOG_CRASH_PAGES 1
97 #define GUC_LOG_CRASH_SHIFT 4
98 #define GUC_LOG_DPC_PAGES 7
99 #define GUC_LOG_DPC_SHIFT 6
100 #define GUC_LOG_ISR_PAGES 7
101 #define GUC_LOG_ISR_SHIFT 9
102 #define GUC_LOG_BUF_ADDR_SHIFT 12
104 #define GUC_CTL_PAGE_FAULT_CONTROL 5
107 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
109 #define GUC_CTL_FEATURE 7
110 #define GUC_CTL_VCS2_ENABLED (1 << 0)
111 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
112 #define GUC_CTL_FEATURE2 (1 << 2)
113 #define GUC_CTL_POWER_GATING (1 << 3)
114 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
115 #define GUC_CTL_PREEMPTION_LOG (1 << 5)
116 #define GUC_CTL_ENABLE_SLPC (1 << 7)
117 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
119 #define GUC_CTL_DEBUG 8
120 #define GUC_LOG_VERBOSITY_SHIFT 0
121 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
122 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
123 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
124 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
125 /* Verbosity range-check limits, without the shift */
126 #define GUC_LOG_VERBOSITY_MIN 0
127 #define GUC_LOG_VERBOSITY_MAX 3
128 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
129 #define GUC_LOG_DESTINATION_MASK (3 << 4)
130 #define GUC_LOG_DISABLED (1 << 6)
131 #define GUC_PROFILE_ENABLED (1 << 7)
132 #define GUC_WQ_TRACK_ENABLED (1 << 8)
133 #define GUC_ADS_ENABLED (1 << 9)
134 #define GUC_DEBUG_RESERVED (1 << 10)
135 #define GUC_ADS_ADDR_SHIFT 11
136 #define GUC_ADS_ADDR_MASK 0xfffff800
138 #define GUC_CTL_RSRVD 9
140 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
143 * DOC: GuC Firmware Layout
145 * The GuC firmware layout looks like this:
147 * +-------------------------------+
150 * | contains major/minor version |
151 * +-------------------------------+
153 * +-------------------------------+
155 * +-------------------------------+
157 * +-------------------------------+
159 * +-------------------------------+
161 * The firmware may or may not have modulus key and exponent data. The header,
162 * uCode and RSA signature are must-have components that will be used by driver.
163 * Length of each components, which is all in dwords, can be found in header.
164 * In the case that modulus and exponent are not present in fw, a.k.a truncated
165 * image, the length value still appears in header.
167 * Driver will do some basic fw size validation based on the following rules:
169 * 1. Header, uCode and RSA are must-have components.
170 * 2. All firmware components, if they present, are in the sequence illustrated
171 * in the layout table above.
172 * 3. Length info of each component can be found in header, in dwords.
173 * 4. Modulus and exponent key are not required by driver. They may not appear
174 * in fw. So driver will load a truncated firmware in this case.
176 * HuC firmware layout is same as GuC firmware.
178 * HuC firmware css header is different. However, the only difference is where
179 * the version information is saved. The uc_css_header is unified to support
180 * both. Driver should get HuC version from uc_css_header.huc_sw_version, while
181 * uc_css_header.guc_sw_version for GuC.
184 struct uc_css_header {
185 uint32_t module_type;
186 /* header_size includes all non-uCode bits, including css_header, rsa
187 * key, modulus key and exponent data. */
188 uint32_t header_size_dw;
189 uint32_t header_version;
191 uint32_t module_vendor;
200 uint32_t size_dw; /* uCode plus header_size_dw */
201 uint32_t key_size_dw;
202 uint32_t modulus_size_dw;
203 uint32_t exponent_size_dw;
214 char buildnumber[12];
217 uint32_t branch_client_version;
225 uint32_t prod_preprod_fw;
226 uint32_t reserved[12];
227 uint32_t header_info;
230 struct guc_doorbell_info {
236 union guc_doorbell_qw {
244 #define GUC_NUM_DOORBELLS 256
245 #define GUC_DOORBELL_INVALID (GUC_NUM_DOORBELLS)
247 #define GUC_DB_SIZE (PAGE_SIZE)
248 #define GUC_WQ_SIZE (PAGE_SIZE * 2)
250 /* Work item for submitting workloads into work queue of GuC. */
254 u32 submit_element_info;
258 struct guc_process_desc {
272 /* engine id and context id is packed into guc_execlist_context.context_id*/
273 #define GUC_ELC_CTXID_OFFSET 0
274 #define GUC_ELC_ENGINE_OFFSET 29
276 /* The execlist context including software and HW information */
277 struct guc_execlist_context {
284 u32 ring_next_free_location;
285 u32 ring_current_tail_pointer_value;
286 u8 engine_state_submit_value;
287 u8 engine_state_wait_value;
289 u16 engine_submit_queue_count;
293 * This structure describes a stage set arranged for a particular communication
294 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
295 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
296 * to avoid confusion with all the other things already named "context" in the
297 * driver. A static pool of these descriptors are stored inside a GEM object
298 * (stage_desc_pool) which is held for the entire lifetime of our interaction
299 * with the GuC, being allocated before the GuC is loaded with its firmware.
301 struct guc_stage_desc {
302 u32 sched_common_area;
311 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
317 u32 wq_sampled_tail_offset;
318 u32 wq_total_submit_enqueues;
335 * Describes single command transport buffer.
336 * Used by both guc-master and clients.
338 struct guc_ct_buffer_desc {
339 u32 addr; /* gfx address */
340 u64 host_private; /* host private data */
341 u32 size; /* size in bytes */
342 u32 head; /* offset updated by GuC*/
343 u32 tail; /* offset updated by owner */
344 u32 is_in_error; /* error indicator */
345 u32 fence; /* fence updated by GuC */
346 u32 status; /* status updated by GuC */
347 u32 owner; /* id of the channel owner */
348 u32 owner_sub_id; /* owner-defined field for extra tracking */
352 /* Type of command transport buffer */
353 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
354 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
357 * Definition of the command transport message header (DW0)
359 * bit[4..0] message len (in dwords)
361 * bit[8] write fence to desc
362 * bit[9] write status to H2G buff
363 * bit[10] send status (via G2H)
364 * bit[15..11] reserved
365 * bit[31..16] action code
367 #define GUC_CT_MSG_LEN_SHIFT 0
368 #define GUC_CT_MSG_LEN_MASK 0x1F
369 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
370 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
371 #define GUC_CT_MSG_SEND_STATUS (1 << 10)
372 #define GUC_CT_MSG_ACTION_SHIFT 16
373 #define GUC_CT_MSG_ACTION_MASK 0xFFFF
375 #define GUC_FORCEWAKE_RENDER (1 << 0)
376 #define GUC_FORCEWAKE_MEDIA (1 << 1)
378 #define GUC_POWER_UNSPECIFIED 0
379 #define GUC_POWER_D0 1
380 #define GUC_POWER_D1 2
381 #define GUC_POWER_D2 3
382 #define GUC_POWER_D3 4
384 /* Scheduling policy settings */
386 /* Reset engine upon preempt failure */
387 #define POLICY_RESET_ENGINE (1<<0)
388 /* Preempt to idle on quantum expiry */
389 #define POLICY_PREEMPT_TO_IDLE (1<<1)
391 #define POLICY_MAX_NUM_WI 15
394 /* Time for one workload to execute. (in micro seconds) */
395 u32 execution_quantum;
398 /* Time to wait for a preemption request to completed before issuing a
399 * reset. (in micro seconds). */
402 /* How much time to allow to run after the first fault is observed.
403 * Then preempt afterwards. (in micro seconds) */
410 struct guc_policies {
411 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
413 /* In micro seconds. How much time to allow before DPC processing is
414 * called back via interrupt (to prevent DPC queue drain starving).
415 * Typically 1000s of micro seconds (example only, not granularity). */
416 u32 dpc_promote_time;
418 /* Must be set to take these new values. */
421 /* Max number of WIs to process per call. A large value may keep CS
423 u32 max_num_work_items;
428 /* GuC MMIO reg state struct */
430 #define GUC_REGSET_FLAGS_NONE 0x0
431 #define GUC_REGSET_POWERCYCLE 0x1
432 #define GUC_REGSET_MASKED 0x2
433 #define GUC_REGSET_ENGINERESET 0x4
434 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
435 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
437 #define GUC_REGSET_MAX_REGISTERS 25
438 #define GUC_MMIO_WHITE_LIST_START 0x24d0
439 #define GUC_MMIO_WHITE_LIST_MAX 12
440 #define GUC_S3_SAVE_SPACE_PAGES 10
442 struct guc_mmio_regset {
447 } registers[GUC_REGSET_MAX_REGISTERS];
450 u32 number_of_registers;
453 /* MMIO registers that are set as non privileged */
454 struct mmio_white_list {
456 u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
460 struct guc_mmio_reg_state {
461 struct guc_mmio_regset global_reg;
462 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
463 struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
466 /* GuC Additional Data Struct */
470 u32 reg_state_buffer;
471 u32 golden_context_lrca;
472 u32 scheduler_policies;
474 u32 eng_state_size[GUC_MAX_ENGINES_NUM];
478 /* GuC logging structures */
480 enum guc_log_buffer_type {
483 GUC_CRASH_DUMP_LOG_BUFFER,
488 * DOC: GuC Log buffer Layout
490 * Page0 +-------------------------------+
491 * | ISR state header (32 bytes) |
492 * | DPC state header |
493 * | Crash dump state header |
494 * Page1 +-------------------------------+
496 * Page9 +-------------------------------+
498 * Page17 +-------------------------------+
499 * | Crash Dump logs |
500 * +-------------------------------+
502 * Below state structure is used for coordination of retrieval of GuC firmware
503 * logs. Separate state is maintained for each log buffer type.
504 * read_ptr points to the location where i915 read last in log buffer and
505 * is read only for GuC firmware. write_ptr is incremented by GuC with number
506 * of bytes written for each log entry and is read only for i915.
507 * When any type of log buffer becomes half full, GuC sends a flush interrupt.
508 * GuC firmware expects that while it is writing to 2nd half of the buffer,
509 * first half would get consumed by Host and then get a flush completed
510 * acknowledgment from Host, so that it does not end up doing any overwrite
511 * causing loss of logs. So when buffer gets half filled & i915 has requested
512 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
513 * to the value of write_ptr and raise the interrupt.
514 * On receiving the interrupt i915 should read the buffer, clear flush_to_file
515 * field and also update read_ptr with the value of sample_write_ptr, before
516 * sending an acknowledgment to GuC. marker & version fields are for internal
517 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
518 * time GuC detects the log buffer overflow.
520 struct guc_log_buffer_state {
525 u32 sampled_write_ptr;
529 u32 buffer_full_cnt:4;
537 union guc_log_control {
539 u32 logging_enabled:1;
547 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
548 enum intel_guc_action {
549 INTEL_GUC_ACTION_DEFAULT = 0x0,
550 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
551 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
552 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
553 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
554 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
555 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
556 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
557 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
558 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
559 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
560 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
561 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
562 INTEL_GUC_ACTION_LIMIT
566 * The GuC sends its response to a command by overwriting the
567 * command in SS0. The response is distinguishable from a command
568 * by the fact that all the MASK bits are set. The remaining bits
571 #define INTEL_GUC_RECV_MASK ((u32)0xF0000000)
572 #define INTEL_GUC_RECV_IS_RESPONSE(x) ((u32)(x) >= INTEL_GUC_RECV_MASK)
573 #define INTEL_GUC_RECV_STATUS(x) (INTEL_GUC_RECV_MASK | (x))
575 /* GUC will return status back to SOFT_SCRATCH_O_REG */
576 enum intel_guc_status {
577 INTEL_GUC_STATUS_SUCCESS = INTEL_GUC_RECV_STATUS(0x0),
578 INTEL_GUC_STATUS_ALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x10),
579 INTEL_GUC_STATUS_DEALLOCATE_DOORBELL_FAIL = INTEL_GUC_RECV_STATUS(0x20),
580 INTEL_GUC_STATUS_GENERIC_FAIL = INTEL_GUC_RECV_STATUS(0x0000F000)
583 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
584 enum intel_guc_recv_message {
585 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
586 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)