2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "intel_guc_fwif.h"
28 #include "i915_guc_reg.h"
30 struct drm_i915_gem_request;
33 * This structure primarily describes the GEM object shared with the GuC.
34 * The GEM object is held for the entire lifetime of our interaction with
35 * the GuC, being allocated before the GuC is loaded with its firmware.
36 * Because there's no way to update the address used by the GuC after
37 * initialisation, the shared object must stay pinned into the GGTT as
38 * long as the GuC is in use. We also keep the first page (only) mapped
39 * into kernel address space, as it includes shared data that must be
40 * updated on every request submission.
42 * The single GEM object described here is actually made up of several
43 * separate areas, as far as the GuC is concerned. The first page (kept
44 * kmap'd) includes the "process decriptor" which holds sequence data for
45 * the doorbell, and one cacheline which actually *is* the doorbell; a
46 * write to this will "ring the doorbell" (i.e. send an interrupt to the
47 * GuC). The subsequent pages of the client object constitute the work
48 * queue (a circular array of work items), again described in the process
49 * descriptor. Work queue pages are mapped momentarily as required.
51 * We also keep a few statistics on failures. Ideally, these should all
53 * no_wq_space: times that the submission pre-check found no space was
54 * available in the work queue (note, the queue is shared,
55 * not per-engine). It is OK for this to be nonzero, but
56 * it should not be huge!
57 * q_fail: failed to enqueue a work item. This should never happen,
58 * because we check for space beforehand.
59 * b_fail: failed to ring the doorbell. This should never happen, unless
60 * somehow the hardware misbehaves, or maybe if the GuC firmware
61 * crashes? We probably need to reset the GPU to recover.
62 * retcode: errno from last guc_submit()
64 struct i915_guc_client {
65 struct drm_i915_gem_object *client_obj;
66 void *client_base; /* first page (only) of above */
67 struct i915_gem_context *owner;
68 struct intel_guc *guc;
72 uint32_t proc_desc_offset;
73 uint32_t doorbell_offset;
76 uint16_t padding; /* Maintain alignment */
81 uint32_t unused; /* Was 'wq_head' */
84 uint32_t q_fail; /* No longer used */
88 /* Per-engine counts of GuC submissions */
89 uint64_t submissions[GUC_MAX_ENGINES_NUM];
92 enum intel_guc_fw_status {
93 GUC_FIRMWARE_FAIL = -1,
94 GUC_FIRMWARE_NONE = 0,
100 * This structure encapsulates all the data needed during the process
101 * of fetching, caching, and loading the firmware image into the GuC.
103 struct intel_guc_fw {
104 struct drm_device * guc_dev;
105 const char * guc_fw_path;
107 struct drm_i915_gem_object * guc_fw_obj;
108 enum intel_guc_fw_status guc_fw_fetch_status;
109 enum intel_guc_fw_status guc_fw_load_status;
111 uint16_t guc_fw_major_wanted;
112 uint16_t guc_fw_minor_wanted;
113 uint16_t guc_fw_major_found;
114 uint16_t guc_fw_minor_found;
116 uint32_t header_size;
117 uint32_t header_offset;
121 uint32_t ucode_offset;
125 struct intel_guc_fw guc_fw;
127 struct drm_i915_gem_object *log_obj;
129 struct drm_i915_gem_object *ads_obj;
131 struct drm_i915_gem_object *ctx_pool_obj;
134 struct i915_guc_client *execbuf_client;
136 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
137 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
139 /* Action status & statistics */
140 uint64_t action_count; /* Total commands issued */
141 uint32_t action_cmd; /* Last command word */
142 uint32_t action_status; /* Last return status */
143 uint32_t action_fail; /* Total number of failures */
144 int32_t action_err; /* Last error code */
146 uint64_t submissions[GUC_MAX_ENGINES_NUM];
147 uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
150 /* intel_guc_loader.c */
151 extern void intel_guc_init(struct drm_device *dev);
152 extern int intel_guc_setup(struct drm_device *dev);
153 extern void intel_guc_fini(struct drm_device *dev);
154 extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
155 extern int intel_guc_suspend(struct drm_device *dev);
156 extern int intel_guc_resume(struct drm_device *dev);
158 /* i915_guc_submission.c */
159 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
160 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
161 int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
162 int i915_guc_submit(struct drm_i915_gem_request *rq);
163 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
164 void i915_guc_submission_fini(struct drm_i915_private *dev_priv);