2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_guc.h"
28 static void gen8_guc_raise_irq(struct intel_guc *guc)
30 struct drm_i915_private *dev_priv = guc_to_i915(guc);
32 I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
35 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
37 GEM_BUG_ON(!guc->send_regs.base);
38 GEM_BUG_ON(!guc->send_regs.count);
39 GEM_BUG_ON(i >= guc->send_regs.count);
41 return _MMIO(guc->send_regs.base + 4 * i);
44 void intel_guc_init_send_regs(struct intel_guc *guc)
46 struct drm_i915_private *dev_priv = guc_to_i915(guc);
47 enum forcewake_domains fw_domains = 0;
50 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
51 guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
53 for (i = 0; i < guc->send_regs.count; i++) {
54 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
56 FW_REG_READ | FW_REG_WRITE);
58 guc->send_regs.fw_domains = fw_domains;
61 void intel_guc_init_early(struct intel_guc *guc)
63 intel_guc_ct_init_early(&guc->ct);
65 mutex_init(&guc->send_mutex);
66 guc->send = intel_guc_send_nop;
67 guc->notify = gen8_guc_raise_irq;
70 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
72 WARN(1, "Unexpected send: action=%#x\n", *action);
77 * This function implements the MMIO based host to GuC interface.
79 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
81 struct drm_i915_private *dev_priv = guc_to_i915(guc);
87 GEM_BUG_ON(len > guc->send_regs.count);
89 /* If CT is available, we expect to use MMIO only during init/fini */
90 GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
91 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
92 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
94 mutex_lock(&guc->send_mutex);
95 intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
97 for (i = 0; i < len; i++)
98 I915_WRITE(guc_send_reg(guc, i), action[i]);
100 POSTING_READ(guc_send_reg(guc, i - 1));
102 intel_guc_notify(guc);
105 * No GuC command should ever take longer than 10ms.
106 * Fast commands should still complete in 10us.
108 ret = __intel_wait_for_register_fw(dev_priv,
109 guc_send_reg(guc, 0),
113 if (status != INTEL_GUC_STATUS_SUCCESS) {
115 * Either the GuC explicitly returned an error (which
116 * we convert to -EIO here) or no response at all was
117 * received within the timeout limit (-ETIMEDOUT)
119 if (ret != -ETIMEDOUT)
122 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
123 " ret=%d status=0x%08X response=0x%08X\n",
124 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
127 intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
128 mutex_unlock(&guc->send_mutex);
133 int intel_guc_sample_forcewake(struct intel_guc *guc)
135 struct drm_i915_private *dev_priv = guc_to_i915(guc);
138 action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
139 /* WaRsDisableCoarsePowerGating:skl,bxt */
140 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
143 /* bit 0 and 1 are for Render and Media domain separately */
144 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
146 return intel_guc_send(guc, action, ARRAY_SIZE(action));
150 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
151 * @guc: intel_guc structure
152 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
154 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
155 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
158 * Return: non-zero code on error
160 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
163 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
167 return intel_guc_send(guc, action, ARRAY_SIZE(action));
171 * intel_guc_suspend() - notify GuC entering suspend state
172 * @dev_priv: i915 device private
174 int intel_guc_suspend(struct drm_i915_private *dev_priv)
176 struct intel_guc *guc = &dev_priv->guc;
177 struct i915_gem_context *ctx;
180 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
183 gen9_disable_guc_interrupts(dev_priv);
185 ctx = dev_priv->kernel_context;
187 data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
188 /* any value greater than GUC_POWER_D0 */
189 data[1] = GUC_POWER_D1;
190 /* first page is shared data with GuC */
191 data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
192 LRC_GUCSHR_PN * PAGE_SIZE;
194 return intel_guc_send(guc, data, ARRAY_SIZE(data));
198 * intel_guc_resume() - notify GuC resuming from suspend state
199 * @dev_priv: i915 device private
201 int intel_guc_resume(struct drm_i915_private *dev_priv)
203 struct intel_guc *guc = &dev_priv->guc;
204 struct i915_gem_context *ctx;
207 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
210 if (i915_modparams.guc_log_level >= 0)
211 gen9_enable_guc_interrupts(dev_priv);
213 ctx = dev_priv->kernel_context;
215 data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
216 data[1] = GUC_POWER_D0;
217 /* first page is shared data with GuC */
218 data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
219 LRC_GUCSHR_PN * PAGE_SIZE;
221 return intel_guc_send(guc, data, ARRAY_SIZE(data));
225 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
227 * @size: size of area to allocate (both virtual space and memory)
229 * This is a wrapper to create an object for use with the GuC. In order to
230 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
231 * both some backing storage and a range inside the Global GTT. We must pin
232 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
233 * range is reserved inside GuC.
235 * Return: A i915_vma if successful, otherwise an ERR_PTR.
237 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
239 struct drm_i915_private *dev_priv = guc_to_i915(guc);
240 struct drm_i915_gem_object *obj;
241 struct i915_vma *vma;
244 obj = i915_gem_object_create(dev_priv, size);
246 return ERR_CAST(obj);
248 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
252 ret = i915_vma_pin(vma, 0, PAGE_SIZE,
253 PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
262 i915_gem_object_put(obj);