drivers/gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "i915_drv.h"
  27
  28 static void gen8_guc_raise_irq(struct intel_guc *guc)
  29 {
  30         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  31
  32         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  33 }
  34
  35 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  36 {
  37         GEM_BUG_ON(!guc->send_regs.base);
  38         GEM_BUG_ON(!guc->send_regs.count);
  39         GEM_BUG_ON(i >= guc->send_regs.count);
  40
  41         return _MMIO(guc->send_regs.base + 4 * i);
  42 }
  43
  44 void intel_guc_init_send_regs(struct intel_guc *guc)
  45 {
  46         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  47         enum forcewake_domains fw_domains = 0;
  48         unsigned int i;
  49
  50         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  51         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
  52
  53         for (i = 0; i < guc->send_regs.count; i++) {
  54                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
  55                                         guc_send_reg(guc, i),
  56                                         FW_REG_READ | FW_REG_WRITE);
  57         }
  58         guc->send_regs.fw_domains = fw_domains;
  59 }
  60
  61 void intel_guc_init_early(struct intel_guc *guc)
  62 {
  63         intel_guc_ct_init_early(&guc->ct);
  64
  65         mutex_init(&guc->send_mutex);
  66         guc->send = intel_guc_send_nop;
  67         guc->notify = gen8_guc_raise_irq;
  68 }
  69
  70 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
  71 {
  72         WARN(1, "Unexpected send: action=%#x\n", *action);
  73         return -ENODEV;
  74 }
  75
  76 /*
  77  * This function implements the MMIO based host to GuC interface.
  78  */
  79 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
  80 {
  81         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  82         u32 status;
  83         int i;
  84         int ret;
  85
  86         GEM_BUG_ON(!len);
  87         GEM_BUG_ON(len > guc->send_regs.count);
  88
  89         /* If CT is available, we expect to use MMIO only during init/fini */
  90         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
  91                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
  92                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
  93
  94         mutex_lock(&guc->send_mutex);
  95         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
  96
  97         for (i = 0; i < len; i++)
  98                 I915_WRITE(guc_send_reg(guc, i), action[i]);
  99
 100         POSTING_READ(guc_send_reg(guc, i - 1));
 101
 102         intel_guc_notify(guc);
 103
 104         /*
 105          * No GuC command should ever take longer than 10ms.
 106          * Fast commands should still complete in 10us.
 107          */
 108         ret = __intel_wait_for_register_fw(dev_priv,
 109                                            guc_send_reg(guc, 0),
 110                                            INTEL_GUC_RECV_MASK,
 111                                            INTEL_GUC_RECV_MASK,
 112                                            10, 10, &status);
 113         if (status != INTEL_GUC_STATUS_SUCCESS) {
 114                 /*
 115                  * Either the GuC explicitly returned an error (which
 116                  * we convert to -EIO here) or no response at all was
 117                  * received within the timeout limit (-ETIMEDOUT)
 118                  */
 119                 if (ret != -ETIMEDOUT)
 120                         ret = -EIO;
 121
 122                 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
 123                          " ret=%d status=0x%08X response=0x%08X\n",
 124                          action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
 125         }
 126
 127         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 128         mutex_unlock(&guc->send_mutex);
 129
 130         return ret;
 131 }
 132
 133 int intel_guc_sample_forcewake(struct intel_guc *guc)
 134 {
 135         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 136         u32 action[2];
 137
 138         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 139         /* WaRsDisableCoarsePowerGating:skl,bxt */
 140         if (!intel_rc6_enabled() ||
 141             NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 142                 action[1] = 0;
 143         else
 144                 /* bit 0 and 1 are for Render and Media domain separately */
 145                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 146
 147         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 148 }
 149
 150 /**
 151  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 152  * @guc: intel_guc structure
 153  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 154  *
 155  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 156  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 157  * intel_huc_auth().
 158  *
 159  * Return:      non-zero code on error
 160  */
 161 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 162 {
 163         u32 action[] = {
 164                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 165                 rsa_offset
 166         };
 167
 168         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 169 }
 170
 171 /**
 172  * intel_guc_suspend() - notify GuC entering suspend state
 173  * @dev_priv:   i915 device private
 174  */
 175 int intel_guc_suspend(struct drm_i915_private *dev_priv)
 176 {
 177         struct intel_guc *guc = &dev_priv->guc;
 178         struct i915_gem_context *ctx;
 179         u32 data[3];
 180
 181         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 182                 return 0;
 183
 184         gen9_disable_guc_interrupts(dev_priv);
 185
 186         ctx = dev_priv->kernel_context;
 187
 188         data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 189         /* any value greater than GUC_POWER_D0 */
 190         data[1] = GUC_POWER_D1;
 191         /* first page is shared data with GuC */
 192         data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
 193                   LRC_GUCSHR_PN * PAGE_SIZE;
 194
 195         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 196 }
 197
 198 /**
 199  * intel_guc_resume() - notify GuC resuming from suspend state
 200  * @dev_priv:   i915 device private
 201  */
 202 int intel_guc_resume(struct drm_i915_private *dev_priv)
 203 {
 204         struct intel_guc *guc = &dev_priv->guc;
 205         struct i915_gem_context *ctx;
 206         u32 data[3];
 207
 208         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 209                 return 0;
 210
 211         if (i915_modparams.guc_log_level >= 0)
 212                 gen9_enable_guc_interrupts(dev_priv);
 213
 214         ctx = dev_priv->kernel_context;
 215
 216         data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 217         data[1] = GUC_POWER_D0;
 218         /* first page is shared data with GuC */
 219         data[2] = guc_ggtt_offset(ctx->engine[RCS].state) +
 220                   LRC_GUCSHR_PN * PAGE_SIZE;
 221
 222         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 223 }
 224
 225 /**
 226  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 227  * @guc:        the guc
 228  * @size:       size of area to allocate (both virtual space and memory)
 229  *
 230  * This is a wrapper to create an object for use with the GuC. In order to
 231  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 232  * both some backing storage and a range inside the Global GTT. We must pin
 233  * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
 234  * range is reserved inside GuC.
 235  *
 236  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 237  */
 238 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 239 {
 240         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 241         struct drm_i915_gem_object *obj;
 242         struct i915_vma *vma;
 243         int ret;
 244
 245         obj = i915_gem_object_create(dev_priv, size);
 246         if (IS_ERR(obj))
 247                 return ERR_CAST(obj);
 248
 249         vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
 250         if (IS_ERR(vma))
 251                 goto err;
 252
 253         ret = i915_vma_pin(vma, 0, PAGE_SIZE,
 254                            PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 255         if (ret) {
 256                 vma = ERR_PTR(ret);
 257                 goto err;
 258         }
 259
 260         return vma;
 261
 262 err:
 263         i915_gem_object_put(obj);
 264         return vma;
 265 }