drivers/gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "i915_drv.h"
  27 #include "i915_guc_submission.h"
  28
  29 static void gen8_guc_raise_irq(struct intel_guc *guc)
  30 {
  31         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  32
  33         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  34 }
  35
  36 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  37 {
  38         GEM_BUG_ON(!guc->send_regs.base);
  39         GEM_BUG_ON(!guc->send_regs.count);
  40         GEM_BUG_ON(i >= guc->send_regs.count);
  41
  42         return _MMIO(guc->send_regs.base + 4 * i);
  43 }
  44
  45 void intel_guc_init_send_regs(struct intel_guc *guc)
  46 {
  47         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  48         enum forcewake_domains fw_domains = 0;
  49         unsigned int i;
  50
  51         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  52         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
  53
  54         for (i = 0; i < guc->send_regs.count; i++) {
  55                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
  56                                         guc_send_reg(guc, i),
  57                                         FW_REG_READ | FW_REG_WRITE);
  58         }
  59         guc->send_regs.fw_domains = fw_domains;
  60 }
  61
  62 void intel_guc_init_early(struct intel_guc *guc)
  63 {
  64         intel_guc_ct_init_early(&guc->ct);
  65
  66         mutex_init(&guc->send_mutex);
  67         guc->send = intel_guc_send_nop;
  68         guc->notify = gen8_guc_raise_irq;
  69 }
  70
  71 static u32 get_gt_type(struct drm_i915_private *dev_priv)
  72 {
  73         /* XXX: GT type based on PCI device ID? field seems unused by fw */
  74         return 0;
  75 }
  76
  77 static u32 get_core_family(struct drm_i915_private *dev_priv)
  78 {
  79         u32 gen = INTEL_GEN(dev_priv);
  80
  81         switch (gen) {
  82         case 9:
  83                 return GUC_CORE_FAMILY_GEN9;
  84
  85         default:
  86                 MISSING_CASE(gen);
  87                 return GUC_CORE_FAMILY_UNKNOWN;
  88         }
  89 }
  90
  91 /*
  92  * Initialise the GuC parameter block before starting the firmware
  93  * transfer. These parameters are read by the firmware on startup
  94  * and cannot be changed thereafter.
  95  */
  96 void intel_guc_init_params(struct intel_guc *guc)
  97 {
  98         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  99         u32 params[GUC_CTL_MAX_DWORDS];
 100         int i;
 101
 102         memset(params, 0, sizeof(params));
 103
 104         params[GUC_CTL_DEVICE_INFO] |=
 105                 (get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
 106                 (get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
 107
 108         /*
 109          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 110          * second. This ARAR is calculated by:
 111          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 112          */
 113         params[GUC_CTL_ARAT_HIGH] = 0;
 114         params[GUC_CTL_ARAT_LOW] = 100000000;
 115
 116         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 117
 118         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 119                         GUC_CTL_VCS2_ENABLED;
 120
 121         params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 122
 123         if (i915_modparams.guc_log_level >= 0) {
 124                 params[GUC_CTL_DEBUG] =
 125                         i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 126         } else {
 127                 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 128         }
 129
 130         /* If GuC submission is enabled, set up additional parameters here */
 131         if (i915_modparams.enable_guc_submission) {
 132                 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 133                 u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
 134                 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 135
 136                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 137                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 138
 139                 pgs >>= PAGE_SHIFT;
 140                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 141                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 142
 143                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 144
 145                 /* Unmask this bit to enable the GuC's internal scheduler */
 146                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 147         }
 148
 149         /*
 150          * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
 151          * they are power context saved so it's ok to release forcewake
 152          * when we are done here and take it again at xfer time.
 153          */
 154         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 155
 156         I915_WRITE(SOFT_SCRATCH(0), 0);
 157
 158         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 159                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 160
 161         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
 162 }
 163
 164 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
 165 {
 166         WARN(1, "Unexpected send: action=%#x\n", *action);
 167         return -ENODEV;
 168 }
 169
 170 /*
 171  * This function implements the MMIO based host to GuC interface.
 172  */
 173 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 174 {
 175         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 176         u32 status;
 177         int i;
 178         int ret;
 179
 180         GEM_BUG_ON(!len);
 181         GEM_BUG_ON(len > guc->send_regs.count);
 182
 183         /* If CT is available, we expect to use MMIO only during init/fini */
 184         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
 185                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 186                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 187
 188         mutex_lock(&guc->send_mutex);
 189         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
 190
 191         for (i = 0; i < len; i++)
 192                 I915_WRITE(guc_send_reg(guc, i), action[i]);
 193
 194         POSTING_READ(guc_send_reg(guc, i - 1));
 195
 196         intel_guc_notify(guc);
 197
 198         /*
 199          * No GuC command should ever take longer than 10ms.
 200          * Fast commands should still complete in 10us.
 201          */
 202         ret = __intel_wait_for_register_fw(dev_priv,
 203                                            guc_send_reg(guc, 0),
 204                                            INTEL_GUC_RECV_MASK,
 205                                            INTEL_GUC_RECV_MASK,
 206                                            10, 10, &status);
 207         if (status != INTEL_GUC_STATUS_SUCCESS) {
 208                 /*
 209                  * Either the GuC explicitly returned an error (which
 210                  * we convert to -EIO here) or no response at all was
 211                  * received within the timeout limit (-ETIMEDOUT)
 212                  */
 213                 if (ret != -ETIMEDOUT)
 214                         ret = -EIO;
 215
 216                 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
 217                          " ret=%d status=0x%08X response=0x%08X\n",
 218                          action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
 219         }
 220
 221         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 222         mutex_unlock(&guc->send_mutex);
 223
 224         return ret;
 225 }
 226
 227 int intel_guc_sample_forcewake(struct intel_guc *guc)
 228 {
 229         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 230         u32 action[2];
 231
 232         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 233         /* WaRsDisableCoarsePowerGating:skl,bxt */
 234         if (!intel_rc6_enabled() ||
 235             NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 236                 action[1] = 0;
 237         else
 238                 /* bit 0 and 1 are for Render and Media domain separately */
 239                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 240
 241         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 242 }
 243
 244 /**
 245  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 246  * @guc: intel_guc structure
 247  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 248  *
 249  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 250  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 251  * intel_huc_auth().
 252  *
 253  * Return:      non-zero code on error
 254  */
 255 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 256 {
 257         u32 action[] = {
 258                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 259                 rsa_offset
 260         };
 261
 262         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 263 }
 264
 265 /**
 266  * intel_guc_suspend() - notify GuC entering suspend state
 267  * @dev_priv:   i915 device private
 268  */
 269 int intel_guc_suspend(struct drm_i915_private *dev_priv)
 270 {
 271         struct intel_guc *guc = &dev_priv->guc;
 272         u32 data[3];
 273
 274         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 275                 return 0;
 276
 277         gen9_disable_guc_interrupts(dev_priv);
 278
 279         data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 280         /* any value greater than GUC_POWER_D0 */
 281         data[1] = GUC_POWER_D1;
 282         data[2] = guc_ggtt_offset(guc->shared_data);
 283
 284         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 285 }
 286
 287 /**
 288  * intel_guc_reset_engine() - ask GuC to reset an engine
 289  * @guc:        intel_guc structure
 290  * @engine:     engine to be reset
 291  */
 292 int intel_guc_reset_engine(struct intel_guc *guc,
 293                            struct intel_engine_cs *engine)
 294 {
 295         u32 data[7];
 296
 297         GEM_BUG_ON(!guc->execbuf_client);
 298
 299         data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
 300         data[1] = engine->guc_id;
 301         data[2] = 0;
 302         data[3] = 0;
 303         data[4] = 0;
 304         data[5] = guc->execbuf_client->stage_id;
 305         data[6] = guc_ggtt_offset(guc->shared_data);
 306
 307         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 308 }
 309
 310 /**
 311  * intel_guc_resume() - notify GuC resuming from suspend state
 312  * @dev_priv:   i915 device private
 313  */
 314 int intel_guc_resume(struct drm_i915_private *dev_priv)
 315 {
 316         struct intel_guc *guc = &dev_priv->guc;
 317         u32 data[3];
 318
 319         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 320                 return 0;
 321
 322         if (i915_modparams.guc_log_level >= 0)
 323                 gen9_enable_guc_interrupts(dev_priv);
 324
 325         data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 326         data[1] = GUC_POWER_D0;
 327         data[2] = guc_ggtt_offset(guc->shared_data);
 328
 329         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 330 }
 331
 332 /**
 333  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 334  * @guc:        the guc
 335  * @size:       size of area to allocate (both virtual space and memory)
 336  *
 337  * This is a wrapper to create an object for use with the GuC. In order to
 338  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 339  * both some backing storage and a range inside the Global GTT. We must pin
 340  * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
 341  * range is reserved inside GuC.
 342  *
 343  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 344  */
 345 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 346 {
 347         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 348         struct drm_i915_gem_object *obj;
 349         struct i915_vma *vma;
 350         int ret;
 351
 352         obj = i915_gem_object_create(dev_priv, size);
 353         if (IS_ERR(obj))
 354                 return ERR_CAST(obj);
 355
 356         vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
 357         if (IS_ERR(vma))
 358                 goto err;
 359
 360         ret = i915_vma_pin(vma, 0, PAGE_SIZE,
 361                            PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 362         if (ret) {
 363                 vma = ERR_PTR(ret);
 364                 goto err;
 365         }
 366
 367         return vma;
 368
 369 err:
 370         i915_gem_object_put(obj);
 371         return vma;
 372 }
 373
 374 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
 375 {
 376         u32 wopcm_size = GUC_WOPCM_TOP;
 377
 378         /* On BXT, the top of WOPCM is reserved for RC6 context */
 379         if (IS_GEN9_LP(dev_priv))
 380                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 381
 382         return wopcm_size;
 383 }