drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_GEN(dev_priv) < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_GEN(dev_priv) <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  73 {
  74         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         if (width)
  86                 *width = cache->plane.src_w;
  87         if (height)
  88                 *height = cache->plane.src_h;
  89 }
  90
  91 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  92                                         struct intel_fbc_state_cache *cache)
  93 {
  94         int lines;
  95
  96         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  97         if (INTEL_GEN(dev_priv) == 7)
  98                 lines = min(lines, 2048);
  99         else if (INTEL_GEN(dev_priv) >= 8)
 100                 lines = min(lines, 2560);
 101
 102         /* Hardware needs the full buffer stride, not just the active area. */
 103         return lines * cache->fb.stride;
 104 }
 105
 106 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 107 {
 108         u32 fbc_ctl;
 109
 110         /* Disable compression */
 111         fbc_ctl = I915_READ(FBC_CONTROL);
 112         if ((fbc_ctl & FBC_CTL_EN) == 0)
 113                 return;
 114
 115         fbc_ctl &= ~FBC_CTL_EN;
 116         I915_WRITE(FBC_CONTROL, fbc_ctl);
 117
 118         /* Wait for compressing bit to clear */
 119         if (intel_wait_for_register(dev_priv,
 120                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 121                                     10)) {
 122                 DRM_DEBUG_KMS("FBC idle timed out\n");
 123                 return;
 124         }
 125 }
 126
 127 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 128 {
 129         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 130         int cfb_pitch;
 131         int i;
 132         u32 fbc_ctl;
 133
 134         /* Note: fbc.threshold == 1 for i8xx */
 135         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 136         if (params->fb.stride < cfb_pitch)
 137                 cfb_pitch = params->fb.stride;
 138
 139         /* FBC_CTL wants 32B or 64B units */
 140         if (IS_GEN2(dev_priv))
 141                 cfb_pitch = (cfb_pitch / 32) - 1;
 142         else
 143                 cfb_pitch = (cfb_pitch / 64) - 1;
 144
 145         /* Clear old tags */
 146         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 147                 I915_WRITE(FBC_TAG(i), 0);
 148
 149         if (IS_GEN4(dev_priv)) {
 150                 u32 fbc_ctl2;
 151
 152                 /* Set it up... */
 153                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 154                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 155                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 156                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 157         }
 158
 159         /* enable it... */
 160         fbc_ctl = I915_READ(FBC_CONTROL);
 161         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 162         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 163         if (IS_I945GM(dev_priv))
 164                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 165         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 166         fbc_ctl |= params->vma->fence->id;
 167         I915_WRITE(FBC_CONTROL, fbc_ctl);
 168 }
 169
 170 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 171 {
 172         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 173 }
 174
 175 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 176 {
 177         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 178         u32 dpfc_ctl;
 179
 180         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 181         if (params->fb.format->cpp[0] == 2)
 182                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 183         else
 184                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 185
 186         if (params->flags & PLANE_HAS_FENCE) {
 187                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 188                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 189         } else {
 190                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 191         }
 192
 193         /* enable it... */
 194         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 195 }
 196
 197 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 198 {
 199         u32 dpfc_ctl;
 200
 201         /* Disable compression */
 202         dpfc_ctl = I915_READ(DPFC_CONTROL);
 203         if (dpfc_ctl & DPFC_CTL_EN) {
 204                 dpfc_ctl &= ~DPFC_CTL_EN;
 205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 206         }
 207 }
 208
 209 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 210 {
 211         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 212 }
 213
 214 /* This function forces a CFB recompression through the nuke operation. */
 215 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 216 {
 217         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 218         POSTING_READ(MSG_FBC_REND_STATE);
 219 }
 220
 221 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 222 {
 223         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 224         u32 dpfc_ctl;
 225         int threshold = dev_priv->fbc.threshold;
 226
 227         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 228         if (params->fb.format->cpp[0] == 2)
 229                 threshold++;
 230
 231         switch (threshold) {
 232         case 4:
 233         case 3:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 235                 break;
 236         case 2:
 237                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 238                 break;
 239         case 1:
 240                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 241                 break;
 242         }
 243
 244         if (params->flags & PLANE_HAS_FENCE) {
 245                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246                 if (IS_GEN5(dev_priv))
 247                         dpfc_ctl |= params->vma->fence->id;
 248                 if (IS_GEN6(dev_priv)) {
 249                         I915_WRITE(SNB_DPFC_CTL_SA,
 250                                    SNB_CPU_FENCE_ENABLE |
 251                                    params->vma->fence->id);
 252                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 253                                    params->crtc.fence_y_offset);
 254                 }
 255         } else {
 256                 if (IS_GEN6(dev_priv)) {
 257                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 258                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 259                 }
 260         }
 261
 262         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 263         I915_WRITE(ILK_FBC_RT_BASE,
 264                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 265         /* enable it... */
 266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 267
 268         intel_fbc_recompress(dev_priv);
 269 }
 270
 271 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 272 {
 273         u32 dpfc_ctl;
 274
 275         /* Disable compression */
 276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 277         if (dpfc_ctl & DPFC_CTL_EN) {
 278                 dpfc_ctl &= ~DPFC_CTL_EN;
 279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 280         }
 281 }
 282
 283 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 284 {
 285         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 286 }
 287
 288 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 289 {
 290         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 291         u32 dpfc_ctl;
 292         int threshold = dev_priv->fbc.threshold;
 293
 294         /* Display WA #0529: skl, kbl, bxt. */
 295         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
 296                 u32 val = I915_READ(CHICKEN_MISC_4);
 297
 298                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 299
 300                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 301                     I915_TILING_X)
 302                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 303
 304                 I915_WRITE(CHICKEN_MISC_4, val);
 305         }
 306
 307         dpfc_ctl = 0;
 308         if (IS_IVYBRIDGE(dev_priv))
 309                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 310
 311         if (params->fb.format->cpp[0] == 2)
 312                 threshold++;
 313
 314         switch (threshold) {
 315         case 4:
 316         case 3:
 317                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 318                 break;
 319         case 2:
 320                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 321                 break;
 322         case 1:
 323                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 324                 break;
 325         }
 326
 327         if (params->flags & PLANE_HAS_FENCE) {
 328                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 329                 I915_WRITE(SNB_DPFC_CTL_SA,
 330                            SNB_CPU_FENCE_ENABLE |
 331                            params->vma->fence->id);
 332                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 333         } else {
 334                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 335                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 336         }
 337
 338         if (dev_priv->fbc.false_color)
 339                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 340
 341         if (IS_IVYBRIDGE(dev_priv)) {
 342                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 343                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 344                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 345                            ILK_FBCQ_DIS);
 346         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 347                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 348                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 349                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 350                            HSW_FBCQ_DIS);
 351         }
 352
 353         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 354
 355         intel_fbc_recompress(dev_priv);
 356 }
 357
 358 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 359 {
 360         if (INTEL_GEN(dev_priv) >= 5)
 361                 return ilk_fbc_is_active(dev_priv);
 362         else if (IS_GM45(dev_priv))
 363                 return g4x_fbc_is_active(dev_priv);
 364         else
 365                 return i8xx_fbc_is_active(dev_priv);
 366 }
 367
 368 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 369 {
 370         struct intel_fbc *fbc = &dev_priv->fbc;
 371
 372         fbc->active = true;
 373
 374         if (INTEL_GEN(dev_priv) >= 7)
 375                 gen7_fbc_activate(dev_priv);
 376         else if (INTEL_GEN(dev_priv) >= 5)
 377                 ilk_fbc_activate(dev_priv);
 378         else if (IS_GM45(dev_priv))
 379                 g4x_fbc_activate(dev_priv);
 380         else
 381                 i8xx_fbc_activate(dev_priv);
 382 }
 383
 384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 385 {
 386         struct intel_fbc *fbc = &dev_priv->fbc;
 387
 388         fbc->active = false;
 389
 390         if (INTEL_GEN(dev_priv) >= 5)
 391                 ilk_fbc_deactivate(dev_priv);
 392         else if (IS_GM45(dev_priv))
 393                 g4x_fbc_deactivate(dev_priv);
 394         else
 395                 i8xx_fbc_deactivate(dev_priv);
 396 }
 397
 398 /**
 399  * intel_fbc_is_active - Is FBC active?
 400  * @dev_priv: i915 device instance
 401  *
 402  * This function is used to verify the current state of FBC.
 403  *
 404  * FIXME: This should be tracked in the plane config eventually
 405  * instead of queried at runtime for most callers.
 406  */
 407 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 408 {
 409         return dev_priv->fbc.active;
 410 }
 411
 412 static void intel_fbc_work_fn(struct work_struct *__work)
 413 {
 414         struct drm_i915_private *dev_priv =
 415                 container_of(__work, struct drm_i915_private, fbc.work.work);
 416         struct intel_fbc *fbc = &dev_priv->fbc;
 417         struct intel_fbc_work *work = &fbc->work;
 418         struct intel_crtc *crtc = fbc->crtc;
 419         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 420
 421         if (drm_crtc_vblank_get(&crtc->base)) {
 422                 /* CRTC is now off, leave FBC deactivated */
 423                 mutex_lock(&fbc->lock);
 424                 work->scheduled = false;
 425                 mutex_unlock(&fbc->lock);
 426                 return;
 427         }
 428
 429 retry:
 430         /* Delay the actual enabling to let pageflipping cease and the
 431          * display to settle before starting the compression. Note that
 432          * this delay also serves a second purpose: it allows for a
 433          * vblank to pass after disabling the FBC before we attempt
 434          * to modify the control registers.
 435          *
 436          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 437          *
 438          * It is also worth mentioning that since work->scheduled_vblank can be
 439          * updated multiple times by the other threads, hitting the timeout is
 440          * not an error condition. We'll just end up hitting the "goto retry"
 441          * case below.
 442          */
 443         wait_event_timeout(vblank->queue,
 444                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 445                 msecs_to_jiffies(50));
 446
 447         mutex_lock(&fbc->lock);
 448
 449         /* Were we cancelled? */
 450         if (!work->scheduled)
 451                 goto out;
 452
 453         /* Were we delayed again while this function was sleeping? */
 454         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 455                 mutex_unlock(&fbc->lock);
 456                 goto retry;
 457         }
 458
 459         intel_fbc_hw_activate(dev_priv);
 460
 461         work->scheduled = false;
 462
 463 out:
 464         mutex_unlock(&fbc->lock);
 465         drm_crtc_vblank_put(&crtc->base);
 466 }
 467
 468 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 471         struct intel_fbc *fbc = &dev_priv->fbc;
 472         struct intel_fbc_work *work = &fbc->work;
 473
 474         WARN_ON(!mutex_is_locked(&fbc->lock));
 475         if (WARN_ON(!fbc->enabled))
 476                 return;
 477
 478         if (drm_crtc_vblank_get(&crtc->base)) {
 479                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 480                           pipe_name(crtc->pipe));
 481                 return;
 482         }
 483
 484         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 485          * this function since we're not releasing fbc.lock, so it won't have an
 486          * opportunity to grab it to discover that it was cancelled. So we just
 487          * update the expected jiffy count. */
 488         work->scheduled = true;
 489         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 490         drm_crtc_vblank_put(&crtc->base);
 491
 492         schedule_work(&work->work);
 493 }
 494
 495 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 496                                  const char *reason)
 497 {
 498         struct intel_fbc *fbc = &dev_priv->fbc;
 499
 500         WARN_ON(!mutex_is_locked(&fbc->lock));
 501
 502         /* Calling cancel_work() here won't help due to the fact that the work
 503          * function grabs fbc->lock. Just set scheduled to false so the work
 504          * function can know it was cancelled. */
 505         fbc->work.scheduled = false;
 506
 507         if (fbc->active)
 508                 intel_fbc_hw_deactivate(dev_priv);
 509
 510         fbc->no_fbc_reason = reason;
 511 }
 512
 513 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 514                               struct intel_plane_state *plane_state)
 515 {
 516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 517         struct intel_fbc *fbc = &dev_priv->fbc;
 518         enum pipe pipe = crtc->pipe;
 519
 520         /* Don't even bother tracking anything we don't need. */
 521         if (!no_fbc_on_multiple_pipes(dev_priv))
 522                 return true;
 523
 524         if (plane_state->base.visible)
 525                 fbc->visible_pipes_mask |= (1 << pipe);
 526         else
 527                 fbc->visible_pipes_mask &= ~(1 << pipe);
 528
 529         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 530 }
 531
 532 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 533                                       struct drm_mm_node *node,
 534                                       int size,
 535                                       int fb_cpp)
 536 {
 537         int compression_threshold = 1;
 538         int ret;
 539         u64 end;
 540
 541         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 542          * reserved range size, so it always assumes the maximum (8mb) is used.
 543          * If we enable FBC using a CFB on that memory range we'll get FIFO
 544          * underruns, even if that range is not reserved by the BIOS. */
 545         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 546                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 547         else
 548                 end = U64_MAX;
 549
 550         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 551          * code changes, this code needs to change as well.
 552          *
 553          * The enable_fbc code will attempt to use one of our 2 compression
 554          * thresholds, therefore, in that case, we only have 1 resort.
 555          */
 556
 557         /* Try to over-allocate to reduce reallocations and fragmentation. */
 558         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 559                                                    4096, 0, end);
 560         if (ret == 0)
 561                 return compression_threshold;
 562
 563 again:
 564         /* HW's ability to limit the CFB is 1:4 */
 565         if (compression_threshold > 4 ||
 566             (fb_cpp == 2 && compression_threshold == 2))
 567                 return 0;
 568
 569         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 570                                                    4096, 0, end);
 571         if (ret && INTEL_GEN(dev_priv) <= 4) {
 572                 return 0;
 573         } else if (ret) {
 574                 compression_threshold <<= 1;
 575                 goto again;
 576         } else {
 577                 return compression_threshold;
 578         }
 579 }
 580
 581 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 582 {
 583         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 584         struct intel_fbc *fbc = &dev_priv->fbc;
 585         struct drm_mm_node *uninitialized_var(compressed_llb);
 586         int size, fb_cpp, ret;
 587
 588         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 589
 590         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 591         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 592
 593         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 594                                          size, fb_cpp);
 595         if (!ret)
 596                 goto err_llb;
 597         else if (ret > 1) {
 598                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 599
 600         }
 601
 602         fbc->threshold = ret;
 603
 604         if (INTEL_GEN(dev_priv) >= 5)
 605                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 606         else if (IS_GM45(dev_priv)) {
 607                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 608         } else {
 609                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 610                 if (!compressed_llb)
 611                         goto err_fb;
 612
 613                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 614                                                   4096, 4096);
 615                 if (ret)
 616                         goto err_fb;
 617
 618                 fbc->compressed_llb = compressed_llb;
 619
 620                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 621                                              fbc->compressed_fb.start,
 622                                              U32_MAX));
 623                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 624                                              fbc->compressed_llb->start,
 625                                              U32_MAX));
 626                 I915_WRITE(FBC_CFB_BASE,
 627                            dev_priv->dsm.start + fbc->compressed_fb.start);
 628                 I915_WRITE(FBC_LL_BASE,
 629                            dev_priv->dsm.start + compressed_llb->start);
 630         }
 631
 632         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 633                       fbc->compressed_fb.size, fbc->threshold);
 634
 635         return 0;
 636
 637 err_fb:
 638         kfree(compressed_llb);
 639         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 640 err_llb:
 641         if (drm_mm_initialized(&dev_priv->mm.stolen))
 642                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 643         return -ENOSPC;
 644 }
 645
 646 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 647 {
 648         struct intel_fbc *fbc = &dev_priv->fbc;
 649
 650         if (drm_mm_node_allocated(&fbc->compressed_fb))
 651                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 652
 653         if (fbc->compressed_llb) {
 654                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 655                 kfree(fbc->compressed_llb);
 656         }
 657 }
 658
 659 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 660 {
 661         struct intel_fbc *fbc = &dev_priv->fbc;
 662
 663         if (!fbc_supported(dev_priv))
 664                 return;
 665
 666         mutex_lock(&fbc->lock);
 667         __intel_fbc_cleanup_cfb(dev_priv);
 668         mutex_unlock(&fbc->lock);
 669 }
 670
 671 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 672                             unsigned int stride)
 673 {
 674         /* This should have been caught earlier. */
 675         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 676                 return false;
 677
 678         /* Below are the additional FBC restrictions. */
 679         if (stride < 512)
 680                 return false;
 681
 682         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 683                 return stride == 4096 || stride == 8192;
 684
 685         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 686                 return false;
 687
 688         if (stride > 16384)
 689                 return false;
 690
 691         return true;
 692 }
 693
 694 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 695                                   uint32_t pixel_format)
 696 {
 697         switch (pixel_format) {
 698         case DRM_FORMAT_XRGB8888:
 699         case DRM_FORMAT_XBGR8888:
 700                 return true;
 701         case DRM_FORMAT_XRGB1555:
 702         case DRM_FORMAT_RGB565:
 703                 /* 16bpp not supported on gen2 */
 704                 if (IS_GEN2(dev_priv))
 705                         return false;
 706                 /* WaFbcOnly1to1Ratio:ctg */
 707                 if (IS_G4X(dev_priv))
 708                         return false;
 709                 return true;
 710         default:
 711                 return false;
 712         }
 713 }
 714
 715 /*
 716  * For some reason, the hardware tracking starts looking at whatever we
 717  * programmed as the display plane base address register. It does not look at
 718  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 719  * variables instead of just looking at the pipe/plane size.
 720  */
 721 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 722 {
 723         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 724         struct intel_fbc *fbc = &dev_priv->fbc;
 725         unsigned int effective_w, effective_h, max_w, max_h;
 726
 727         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 728                 max_w = 4096;
 729                 max_h = 4096;
 730         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 731                 max_w = 4096;
 732                 max_h = 2048;
 733         } else {
 734                 max_w = 2048;
 735                 max_h = 1536;
 736         }
 737
 738         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 739                                         &effective_h);
 740         effective_w += fbc->state_cache.plane.adjusted_x;
 741         effective_h += fbc->state_cache.plane.adjusted_y;
 742
 743         return effective_w <= max_w && effective_h <= max_h;
 744 }
 745
 746 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 747                                          struct intel_crtc_state *crtc_state,
 748                                          struct intel_plane_state *plane_state)
 749 {
 750         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 751         struct intel_fbc *fbc = &dev_priv->fbc;
 752         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 753         struct drm_framebuffer *fb = plane_state->base.fb;
 754
 755         cache->vma = NULL;
 756         cache->flags = 0;
 757
 758         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 759         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 760                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 761
 762         cache->plane.rotation = plane_state->base.rotation;
 763         /*
 764          * Src coordinates are already rotated by 270 degrees for
 765          * the 90/270 degree plane rotation cases (to match the
 766          * GTT mapping), hence no need to account for rotation here.
 767          */
 768         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 769         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 770         cache->plane.visible = plane_state->base.visible;
 771         cache->plane.adjusted_x = plane_state->main.x;
 772         cache->plane.adjusted_y = plane_state->main.y;
 773         cache->plane.y = plane_state->base.src.y1 >> 16;
 774
 775         if (!cache->plane.visible)
 776                 return;
 777
 778         cache->fb.format = fb->format;
 779         cache->fb.stride = fb->pitches[0];
 780
 781         cache->vma = plane_state->vma;
 782         cache->flags = plane_state->flags;
 783         if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
 784                 cache->flags &= ~PLANE_HAS_FENCE;
 785 }
 786
 787 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 788 {
 789         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 790         struct intel_fbc *fbc = &dev_priv->fbc;
 791         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 792
 793         /* We don't need to use a state cache here since this information is
 794          * global for all CRTC.
 795          */
 796         if (fbc->underrun_detected) {
 797                 fbc->no_fbc_reason = "underrun detected";
 798                 return false;
 799         }
 800
 801         if (!cache->vma) {
 802                 fbc->no_fbc_reason = "primary plane not visible";
 803                 return false;
 804         }
 805
 806         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 807                 fbc->no_fbc_reason = "incompatible mode";
 808                 return false;
 809         }
 810
 811         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 812                 fbc->no_fbc_reason = "mode too large for compression";
 813                 return false;
 814         }
 815
 816         /* The use of a CPU fence is mandatory in order to detect writes
 817          * by the CPU to the scanout and trigger updates to the FBC.
 818          *
 819          * Note that is possible for a tiled surface to be unmappable (and
 820          * so have no fence associated with it) due to aperture constaints
 821          * at the time of pinning.
 822          */
 823         if (!(cache->flags & PLANE_HAS_FENCE)) {
 824                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 825                 return false;
 826         }
 827         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 828             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 829                 fbc->no_fbc_reason = "rotation unsupported";
 830                 return false;
 831         }
 832
 833         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 834                 fbc->no_fbc_reason = "framebuffer stride not supported";
 835                 return false;
 836         }
 837
 838         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 839                 fbc->no_fbc_reason = "pixel format is invalid";
 840                 return false;
 841         }
 842
 843         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 844         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 845             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 846                 fbc->no_fbc_reason = "pixel rate is too big";
 847                 return false;
 848         }
 849
 850         /* It is possible for the required CFB size change without a
 851          * crtc->disable + crtc->enable since it is possible to change the
 852          * stride without triggering a full modeset. Since we try to
 853          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 854          * if this happens, but if we exceed the current CFB size we'll have to
 855          * disable FBC. Notice that it would be possible to disable FBC, wait
 856          * for a frame, free the stolen node, then try to reenable FBC in case
 857          * we didn't get any invalidate/deactivate calls, but this would require
 858          * a lot of tracking just for a specific case. If we conclude it's an
 859          * important case, we can implement it later. */
 860         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 861             fbc->compressed_fb.size * fbc->threshold) {
 862                 fbc->no_fbc_reason = "CFB requirements changed";
 863                 return false;
 864         }
 865
 866         return true;
 867 }
 868
 869 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 870 {
 871         struct intel_fbc *fbc = &dev_priv->fbc;
 872
 873         if (intel_vgpu_active(dev_priv)) {
 874                 fbc->no_fbc_reason = "VGPU is active";
 875                 return false;
 876         }
 877
 878         if (!i915_modparams.enable_fbc) {
 879                 fbc->no_fbc_reason = "disabled per module param or by default";
 880                 return false;
 881         }
 882
 883         if (fbc->underrun_detected) {
 884                 fbc->no_fbc_reason = "underrun detected";
 885                 return false;
 886         }
 887
 888         return true;
 889 }
 890
 891 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 892                                      struct intel_fbc_reg_params *params)
 893 {
 894         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 895         struct intel_fbc *fbc = &dev_priv->fbc;
 896         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 897
 898         /* Since all our fields are integer types, use memset here so the
 899          * comparison function can rely on memcmp because the padding will be
 900          * zero. */
 901         memset(params, 0, sizeof(*params));
 902
 903         params->vma = cache->vma;
 904         params->flags = cache->flags;
 905
 906         params->crtc.pipe = crtc->pipe;
 907         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 908         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 909
 910         params->fb.format = cache->fb.format;
 911         params->fb.stride = cache->fb.stride;
 912
 913         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 914
 915         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 916                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 917                                                 32 * fbc->threshold) * 8;
 918 }
 919
 920 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 921                                        struct intel_fbc_reg_params *params2)
 922 {
 923         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 924         return memcmp(params1, params2, sizeof(*params1)) == 0;
 925 }
 926
 927 void intel_fbc_pre_update(struct intel_crtc *crtc,
 928                           struct intel_crtc_state *crtc_state,
 929                           struct intel_plane_state *plane_state)
 930 {
 931         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 932         struct intel_fbc *fbc = &dev_priv->fbc;
 933         const char *reason = "update pending";
 934
 935         if (!fbc_supported(dev_priv))
 936                 return;
 937
 938         mutex_lock(&fbc->lock);
 939
 940         if (!multiple_pipes_ok(crtc, plane_state)) {
 941                 reason = "more than one pipe active";
 942                 goto deactivate;
 943         }
 944
 945         if (!fbc->enabled || fbc->crtc != crtc)
 946                 goto unlock;
 947
 948         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 949
 950 deactivate:
 951         intel_fbc_deactivate(dev_priv, reason);
 952 unlock:
 953         mutex_unlock(&fbc->lock);
 954 }
 955
 956 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 959         struct intel_fbc *fbc = &dev_priv->fbc;
 960         struct intel_fbc_reg_params old_params;
 961
 962         WARN_ON(!mutex_is_locked(&fbc->lock));
 963
 964         if (!fbc->enabled || fbc->crtc != crtc)
 965                 return;
 966
 967         if (!intel_fbc_can_activate(crtc)) {
 968                 WARN_ON(fbc->active);
 969                 return;
 970         }
 971
 972         old_params = fbc->params;
 973         intel_fbc_get_reg_params(crtc, &fbc->params);
 974
 975         /* If the scanout has not changed, don't modify the FBC settings.
 976          * Note that we make the fundamental assumption that the fb->obj
 977          * cannot be unpinned (and have its GTT offset and fence revoked)
 978          * without first being decoupled from the scanout and FBC disabled.
 979          */
 980         if (fbc->active &&
 981             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 982                 return;
 983
 984         intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
 985         intel_fbc_schedule_activation(crtc);
 986 }
 987
 988 void intel_fbc_post_update(struct intel_crtc *crtc)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 991         struct intel_fbc *fbc = &dev_priv->fbc;
 992
 993         if (!fbc_supported(dev_priv))
 994                 return;
 995
 996         mutex_lock(&fbc->lock);
 997         __intel_fbc_post_update(crtc);
 998         mutex_unlock(&fbc->lock);
 999 }
1000
1001 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1002 {
1003         if (fbc->enabled)
1004                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1005         else
1006                 return fbc->possible_framebuffer_bits;
1007 }
1008
1009 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1010                           unsigned int frontbuffer_bits,
1011                           enum fb_op_origin origin)
1012 {
1013         struct intel_fbc *fbc = &dev_priv->fbc;
1014
1015         if (!fbc_supported(dev_priv))
1016                 return;
1017
1018         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1019                 return;
1020
1021         mutex_lock(&fbc->lock);
1022
1023         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1024
1025         if (fbc->enabled && fbc->busy_bits)
1026                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1027
1028         mutex_unlock(&fbc->lock);
1029 }
1030
1031 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1032                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1033 {
1034         struct intel_fbc *fbc = &dev_priv->fbc;
1035
1036         if (!fbc_supported(dev_priv))
1037                 return;
1038
1039         mutex_lock(&fbc->lock);
1040
1041         fbc->busy_bits &= ~frontbuffer_bits;
1042
1043         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1044                 goto out;
1045
1046         if (!fbc->busy_bits && fbc->enabled &&
1047             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1048                 if (fbc->active)
1049                         intel_fbc_recompress(dev_priv);
1050                 else
1051                         __intel_fbc_post_update(fbc->crtc);
1052         }
1053
1054 out:
1055         mutex_unlock(&fbc->lock);
1056 }
1057
1058 /**
1059  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1060  * @dev_priv: i915 device instance
1061  * @state: the atomic state structure
1062  *
1063  * This function looks at the proposed state for CRTCs and planes, then chooses
1064  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1065  * true.
1066  *
1067  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1068  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1069  */
1070 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1071                            struct intel_atomic_state *state)
1072 {
1073         struct intel_fbc *fbc = &dev_priv->fbc;
1074         struct intel_plane *plane;
1075         struct intel_plane_state *plane_state;
1076         bool crtc_chosen = false;
1077         int i;
1078
1079         mutex_lock(&fbc->lock);
1080
1081         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1082         if (fbc->crtc &&
1083             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1084                 goto out;
1085
1086         if (!intel_fbc_can_enable(dev_priv))
1087                 goto out;
1088
1089         /* Simply choose the first CRTC that is compatible and has a visible
1090          * plane. We could go for fancier schemes such as checking the plane
1091          * size, but this would just affect the few platforms that don't tie FBC
1092          * to pipe or plane A. */
1093         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1094                 struct intel_crtc_state *crtc_state;
1095                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1096
1097                 if (!plane_state->base.visible)
1098                         continue;
1099
1100                 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1101                         continue;
1102
1103                 if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != PLANE_A)
1104                         continue;
1105
1106                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1107
1108                 crtc_state->enable_fbc = true;
1109                 crtc_chosen = true;
1110                 break;
1111         }
1112
1113         if (!crtc_chosen)
1114                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1115
1116 out:
1117         mutex_unlock(&fbc->lock);
1118 }
1119
1120 /**
1121  * intel_fbc_enable: tries to enable FBC on the CRTC
1122  * @crtc: the CRTC
1123  * @crtc_state: corresponding &drm_crtc_state for @crtc
1124  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1125  *
1126  * This function checks if the given CRTC was chosen for FBC, then enables it if
1127  * possible. Notice that it doesn't activate FBC. It is valid to call
1128  * intel_fbc_enable multiple times for the same pipe without an
1129  * intel_fbc_disable in the middle, as long as it is deactivated.
1130  */
1131 void intel_fbc_enable(struct intel_crtc *crtc,
1132                       struct intel_crtc_state *crtc_state,
1133                       struct intel_plane_state *plane_state)
1134 {
1135         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1136         struct intel_fbc *fbc = &dev_priv->fbc;
1137
1138         if (!fbc_supported(dev_priv))
1139                 return;
1140
1141         mutex_lock(&fbc->lock);
1142
1143         if (fbc->enabled) {
1144                 WARN_ON(fbc->crtc == NULL);
1145                 if (fbc->crtc == crtc) {
1146                         WARN_ON(!crtc_state->enable_fbc);
1147                         WARN_ON(fbc->active);
1148                 }
1149                 goto out;
1150         }
1151
1152         if (!crtc_state->enable_fbc)
1153                 goto out;
1154
1155         WARN_ON(fbc->active);
1156         WARN_ON(fbc->crtc != NULL);
1157
1158         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1159         if (intel_fbc_alloc_cfb(crtc)) {
1160                 fbc->no_fbc_reason = "not enough stolen memory";
1161                 goto out;
1162         }
1163
1164         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1165         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1166
1167         fbc->enabled = true;
1168         fbc->crtc = crtc;
1169 out:
1170         mutex_unlock(&fbc->lock);
1171 }
1172
1173 /**
1174  * __intel_fbc_disable - disable FBC
1175  * @dev_priv: i915 device instance
1176  *
1177  * This is the low level function that actually disables FBC. Callers should
1178  * grab the FBC lock.
1179  */
1180 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1181 {
1182         struct intel_fbc *fbc = &dev_priv->fbc;
1183         struct intel_crtc *crtc = fbc->crtc;
1184
1185         WARN_ON(!mutex_is_locked(&fbc->lock));
1186         WARN_ON(!fbc->enabled);
1187         WARN_ON(fbc->active);
1188         WARN_ON(crtc->active);
1189
1190         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1191
1192         __intel_fbc_cleanup_cfb(dev_priv);
1193
1194         fbc->enabled = false;
1195         fbc->crtc = NULL;
1196 }
1197
1198 /**
1199  * intel_fbc_disable - disable FBC if it's associated with crtc
1200  * @crtc: the CRTC
1201  *
1202  * This function disables FBC if it's associated with the provided CRTC.
1203  */
1204 void intel_fbc_disable(struct intel_crtc *crtc)
1205 {
1206         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1207         struct intel_fbc *fbc = &dev_priv->fbc;
1208
1209         if (!fbc_supported(dev_priv))
1210                 return;
1211
1212         mutex_lock(&fbc->lock);
1213         if (fbc->crtc == crtc)
1214                 __intel_fbc_disable(dev_priv);
1215         mutex_unlock(&fbc->lock);
1216
1217         cancel_work_sync(&fbc->work.work);
1218 }
1219
1220 /**
1221  * intel_fbc_global_disable - globally disable FBC
1222  * @dev_priv: i915 device instance
1223  *
1224  * This function disables FBC regardless of which CRTC is associated with it.
1225  */
1226 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1227 {
1228         struct intel_fbc *fbc = &dev_priv->fbc;
1229
1230         if (!fbc_supported(dev_priv))
1231                 return;
1232
1233         mutex_lock(&fbc->lock);
1234         if (fbc->enabled)
1235                 __intel_fbc_disable(dev_priv);
1236         mutex_unlock(&fbc->lock);
1237
1238         cancel_work_sync(&fbc->work.work);
1239 }
1240
1241 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1242 {
1243         struct drm_i915_private *dev_priv =
1244                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1245         struct intel_fbc *fbc = &dev_priv->fbc;
1246
1247         mutex_lock(&fbc->lock);
1248
1249         /* Maybe we were scheduled twice. */
1250         if (fbc->underrun_detected || !fbc->enabled)
1251                 goto out;
1252
1253         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1254         fbc->underrun_detected = true;
1255
1256         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1257 out:
1258         mutex_unlock(&fbc->lock);
1259 }
1260
1261 /**
1262  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1263  * @dev_priv: i915 device instance
1264  *
1265  * Without FBC, most underruns are harmless and don't really cause too many
1266  * problems, except for an annoying message on dmesg. With FBC, underruns can
1267  * become black screens or even worse, especially when paired with bad
1268  * watermarks. So in order for us to be on the safe side, completely disable FBC
1269  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1270  * already suggests that watermarks may be bad, so try to be as safe as
1271  * possible.
1272  *
1273  * This function is called from the IRQ handler.
1274  */
1275 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1276 {
1277         struct intel_fbc *fbc = &dev_priv->fbc;
1278
1279         if (!fbc_supported(dev_priv))
1280                 return;
1281
1282         /* There's no guarantee that underrun_detected won't be set to true
1283          * right after this check and before the work is scheduled, but that's
1284          * not a problem since we'll check it again under the work function
1285          * while FBC is locked. This check here is just to prevent us from
1286          * unnecessarily scheduling the work, and it relies on the fact that we
1287          * never switch underrun_detect back to false after it's true. */
1288         if (READ_ONCE(fbc->underrun_detected))
1289                 return;
1290
1291         schedule_work(&fbc->underrun_work);
1292 }
1293
1294 /**
1295  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1296  * @dev_priv: i915 device instance
1297  *
1298  * The FBC code needs to track CRTC visibility since the older platforms can't
1299  * have FBC enabled while multiple pipes are used. This function does the
1300  * initial setup at driver load to make sure FBC is matching the real hardware.
1301  */
1302 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1303 {
1304         struct intel_crtc *crtc;
1305
1306         /* Don't even bother tracking anything if we don't need. */
1307         if (!no_fbc_on_multiple_pipes(dev_priv))
1308                 return;
1309
1310         for_each_intel_crtc(&dev_priv->drm, crtc)
1311                 if (intel_crtc_active(crtc) &&
1312                     crtc->base.primary->state->visible)
1313                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1314 }
1315
1316 /*
1317  * The DDX driver changes its behavior depending on the value it reads from
1318  * i915.enable_fbc, so sanitize it by translating the default value into either
1319  * 0 or 1 in order to allow it to know what's going on.
1320  *
1321  * Notice that this is done at driver initialization and we still allow user
1322  * space to change the value during runtime without sanitizing it again. IGT
1323  * relies on being able to change i915.enable_fbc at runtime.
1324  */
1325 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1326 {
1327         if (i915_modparams.enable_fbc >= 0)
1328                 return !!i915_modparams.enable_fbc;
1329
1330         if (!HAS_FBC(dev_priv))
1331                 return 0;
1332
1333         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1334                 return 1;
1335
1336         return 0;
1337 }
1338
1339 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1340 {
1341         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1342         if (intel_vtd_active() &&
1343             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1344                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1345                 return true;
1346         }
1347
1348         return false;
1349 }
1350
1351 /**
1352  * intel_fbc_init - Initialize FBC
1353  * @dev_priv: the i915 device
1354  *
1355  * This function might be called during PM init process.
1356  */
1357 void intel_fbc_init(struct drm_i915_private *dev_priv)
1358 {
1359         struct intel_fbc *fbc = &dev_priv->fbc;
1360         enum pipe pipe;
1361
1362         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1363         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1364         mutex_init(&fbc->lock);
1365         fbc->enabled = false;
1366         fbc->active = false;
1367         fbc->work.scheduled = false;
1368
1369         if (need_fbc_vtd_wa(dev_priv))
1370                 mkwrite_device_info(dev_priv)->has_fbc = false;
1371
1372         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1373         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1374                       i915_modparams.enable_fbc);
1375
1376         if (!HAS_FBC(dev_priv)) {
1377                 fbc->no_fbc_reason = "unsupported by this chipset";
1378                 return;
1379         }
1380
1381         for_each_pipe(dev_priv, pipe) {
1382                 fbc->possible_framebuffer_bits |=
1383                         INTEL_FRONTBUFFER(pipe, PLANE_PRIMARY);
1384
1385                 if (fbc_on_pipe_a_only(dev_priv))
1386                         break;
1387         }
1388
1389         /* This value was pulled out of someone's hat */
1390         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1391                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1392
1393         /* We still don't have any sort of hardware state readout for FBC, so
1394          * deactivate it in case the BIOS activated it to make sure software
1395          * matches the hardware state. */
1396         if (intel_fbc_hw_is_active(dev_priv))
1397                 intel_fbc_hw_deactivate(dev_priv);
1398 }