2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
46 return HAS_FBC(dev_priv);
49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
51 return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
56 return INTEL_INFO(dev_priv)->gen < 4;
59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
61 return INTEL_INFO(dev_priv)->gen <= 3;
65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67 * origin so the x and y offsets can actually fit the registers. As a
68 * consequence, the fence doesn't really start exactly at the display plane
69 * address we program because it starts at the real start of the buffer, so we
70 * have to take this into consideration here.
72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
74 return crtc->base.y - crtc->adjusted_y;
78 * For SKL+, the plane source size used by the hardware is based on the value we
79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80 * we wrote to PIPESRC.
82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
83 int *width, int *height)
87 if (intel_rotation_90_or_270(cache->plane.rotation)) {
88 w = cache->plane.src_h;
89 h = cache->plane.src_w;
91 w = cache->plane.src_w;
92 h = cache->plane.src_h;
101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
102 struct intel_fbc_state_cache *cache)
106 intel_fbc_get_plane_source_size(cache, NULL, &lines);
107 if (INTEL_INFO(dev_priv)->gen >= 7)
108 lines = min(lines, 2048);
110 /* Hardware needs the full buffer stride, not just the active area. */
111 return lines * cache->fb.stride;
114 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
118 /* Disable compression */
119 fbc_ctl = I915_READ(FBC_CONTROL);
120 if ((fbc_ctl & FBC_CTL_EN) == 0)
123 fbc_ctl &= ~FBC_CTL_EN;
124 I915_WRITE(FBC_CONTROL, fbc_ctl);
126 /* Wait for compressing bit to clear */
127 if (intel_wait_for_register(dev_priv,
128 FBC_STATUS, FBC_STAT_COMPRESSING, 0,
130 DRM_DEBUG_KMS("FBC idle timed out\n");
135 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
137 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
142 /* Note: fbc.threshold == 1 for i8xx */
143 cfb_pitch = params->cfb_size / FBC_LL_SIZE;
144 if (params->fb.stride < cfb_pitch)
145 cfb_pitch = params->fb.stride;
147 /* FBC_CTL wants 32B or 64B units */
148 if (IS_GEN2(dev_priv))
149 cfb_pitch = (cfb_pitch / 32) - 1;
151 cfb_pitch = (cfb_pitch / 64) - 1;
154 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
155 I915_WRITE(FBC_TAG(i), 0);
157 if (IS_GEN4(dev_priv)) {
161 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
162 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
163 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
164 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
168 fbc_ctl = I915_READ(FBC_CONTROL);
169 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
170 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
171 if (IS_I945GM(dev_priv))
172 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
173 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
174 fbc_ctl |= params->fb.fence_reg;
175 I915_WRITE(FBC_CONTROL, fbc_ctl);
178 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
180 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
183 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
185 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
188 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
189 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
190 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
192 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
194 if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
195 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
196 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
198 I915_WRITE(DPFC_FENCE_YOFF, 0);
202 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
205 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
209 /* Disable compression */
210 dpfc_ctl = I915_READ(DPFC_CONTROL);
211 if (dpfc_ctl & DPFC_CTL_EN) {
212 dpfc_ctl &= ~DPFC_CTL_EN;
213 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
217 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
219 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
222 /* This function forces a CFB recompression through the nuke operation. */
223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
225 I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
226 POSTING_READ(MSG_FBC_REND_STATE);
229 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
231 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
233 int threshold = dev_priv->fbc.threshold;
235 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
236 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
242 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
245 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
248 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
252 if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
253 dpfc_ctl |= DPFC_CTL_FENCE_EN;
254 if (IS_GEN5(dev_priv))
255 dpfc_ctl |= params->fb.fence_reg;
256 if (IS_GEN6(dev_priv)) {
257 I915_WRITE(SNB_DPFC_CTL_SA,
258 SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
259 I915_WRITE(DPFC_CPU_FENCE_OFFSET,
260 params->crtc.fence_y_offset);
263 if (IS_GEN6(dev_priv)) {
264 I915_WRITE(SNB_DPFC_CTL_SA, 0);
265 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
269 I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
270 I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
272 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
274 intel_fbc_recompress(dev_priv);
277 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
281 /* Disable compression */
282 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
283 if (dpfc_ctl & DPFC_CTL_EN) {
284 dpfc_ctl &= ~DPFC_CTL_EN;
285 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
289 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
291 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
294 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
296 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
298 int threshold = dev_priv->fbc.threshold;
301 if (IS_IVYBRIDGE(dev_priv))
302 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
304 if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
310 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
313 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
316 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
320 if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
321 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
322 I915_WRITE(SNB_DPFC_CTL_SA,
323 SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
324 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
326 I915_WRITE(SNB_DPFC_CTL_SA,0);
327 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
330 if (dev_priv->fbc.false_color)
331 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
333 if (IS_IVYBRIDGE(dev_priv)) {
334 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
335 I915_WRITE(ILK_DISPLAY_CHICKEN1,
336 I915_READ(ILK_DISPLAY_CHICKEN1) |
338 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
339 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
340 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
341 I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
345 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
347 intel_fbc_recompress(dev_priv);
350 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
352 if (INTEL_INFO(dev_priv)->gen >= 5)
353 return ilk_fbc_is_active(dev_priv);
354 else if (IS_GM45(dev_priv))
355 return g4x_fbc_is_active(dev_priv);
357 return i8xx_fbc_is_active(dev_priv);
360 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
362 struct intel_fbc *fbc = &dev_priv->fbc;
366 if (INTEL_INFO(dev_priv)->gen >= 7)
367 gen7_fbc_activate(dev_priv);
368 else if (INTEL_INFO(dev_priv)->gen >= 5)
369 ilk_fbc_activate(dev_priv);
370 else if (IS_GM45(dev_priv))
371 g4x_fbc_activate(dev_priv);
373 i8xx_fbc_activate(dev_priv);
376 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
378 struct intel_fbc *fbc = &dev_priv->fbc;
382 if (INTEL_INFO(dev_priv)->gen >= 5)
383 ilk_fbc_deactivate(dev_priv);
384 else if (IS_GM45(dev_priv))
385 g4x_fbc_deactivate(dev_priv);
387 i8xx_fbc_deactivate(dev_priv);
391 * intel_fbc_is_active - Is FBC active?
392 * @dev_priv: i915 device instance
394 * This function is used to verify the current state of FBC.
396 * FIXME: This should be tracked in the plane config eventually
397 * instead of queried at runtime for most callers.
399 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
401 return dev_priv->fbc.active;
404 static void intel_fbc_work_fn(struct work_struct *__work)
406 struct drm_i915_private *dev_priv =
407 container_of(__work, struct drm_i915_private, fbc.work.work);
408 struct intel_fbc *fbc = &dev_priv->fbc;
409 struct intel_fbc_work *work = &fbc->work;
410 struct intel_crtc *crtc = fbc->crtc;
411 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
413 if (drm_crtc_vblank_get(&crtc->base)) {
414 DRM_ERROR("vblank not available for FBC on pipe %c\n",
415 pipe_name(crtc->pipe));
417 mutex_lock(&fbc->lock);
418 work->scheduled = false;
419 mutex_unlock(&fbc->lock);
424 /* Delay the actual enabling to let pageflipping cease and the
425 * display to settle before starting the compression. Note that
426 * this delay also serves a second purpose: it allows for a
427 * vblank to pass after disabling the FBC before we attempt
428 * to modify the control registers.
430 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
432 * It is also worth mentioning that since work->scheduled_vblank can be
433 * updated multiple times by the other threads, hitting the timeout is
434 * not an error condition. We'll just end up hitting the "goto retry"
437 wait_event_timeout(vblank->queue,
438 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
439 msecs_to_jiffies(50));
441 mutex_lock(&fbc->lock);
443 /* Were we cancelled? */
444 if (!work->scheduled)
447 /* Were we delayed again while this function was sleeping? */
448 if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
449 mutex_unlock(&fbc->lock);
453 intel_fbc_hw_activate(dev_priv);
455 work->scheduled = false;
458 mutex_unlock(&fbc->lock);
459 drm_crtc_vblank_put(&crtc->base);
462 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
465 struct intel_fbc *fbc = &dev_priv->fbc;
466 struct intel_fbc_work *work = &fbc->work;
468 WARN_ON(!mutex_is_locked(&fbc->lock));
470 if (drm_crtc_vblank_get(&crtc->base)) {
471 DRM_ERROR("vblank not available for FBC on pipe %c\n",
472 pipe_name(crtc->pipe));
476 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
477 * this function since we're not releasing fbc.lock, so it won't have an
478 * opportunity to grab it to discover that it was cancelled. So we just
479 * update the expected jiffy count. */
480 work->scheduled = true;
481 work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
482 drm_crtc_vblank_put(&crtc->base);
484 schedule_work(&work->work);
487 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
489 struct intel_fbc *fbc = &dev_priv->fbc;
491 WARN_ON(!mutex_is_locked(&fbc->lock));
493 /* Calling cancel_work() here won't help due to the fact that the work
494 * function grabs fbc->lock. Just set scheduled to false so the work
495 * function can know it was cancelled. */
496 fbc->work.scheduled = false;
499 intel_fbc_hw_deactivate(dev_priv);
502 static bool multiple_pipes_ok(struct intel_crtc *crtc,
503 struct intel_plane_state *plane_state)
505 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
506 struct intel_fbc *fbc = &dev_priv->fbc;
507 enum pipe pipe = crtc->pipe;
509 /* Don't even bother tracking anything we don't need. */
510 if (!no_fbc_on_multiple_pipes(dev_priv))
513 if (plane_state->base.visible)
514 fbc->visible_pipes_mask |= (1 << pipe);
516 fbc->visible_pipes_mask &= ~(1 << pipe);
518 return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
521 static int find_compression_threshold(struct drm_i915_private *dev_priv,
522 struct drm_mm_node *node,
526 struct i915_ggtt *ggtt = &dev_priv->ggtt;
527 int compression_threshold = 1;
531 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
532 * reserved range size, so it always assumes the maximum (8mb) is used.
533 * If we enable FBC using a CFB on that memory range we'll get FIFO
534 * underruns, even if that range is not reserved by the BIOS. */
535 if (IS_BROADWELL(dev_priv) ||
536 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
537 end = ggtt->stolen_size - 8 * 1024 * 1024;
539 end = ggtt->stolen_usable_size;
541 /* HACK: This code depends on what we will do in *_enable_fbc. If that
542 * code changes, this code needs to change as well.
544 * The enable_fbc code will attempt to use one of our 2 compression
545 * thresholds, therefore, in that case, we only have 1 resort.
548 /* Try to over-allocate to reduce reallocations and fragmentation. */
549 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
552 return compression_threshold;
555 /* HW's ability to limit the CFB is 1:4 */
556 if (compression_threshold > 4 ||
557 (fb_cpp == 2 && compression_threshold == 2))
560 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
562 if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
565 compression_threshold <<= 1;
568 return compression_threshold;
572 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
575 struct intel_fbc *fbc = &dev_priv->fbc;
576 struct drm_mm_node *uninitialized_var(compressed_llb);
577 int size, fb_cpp, ret;
579 WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
581 size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
582 fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
584 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
589 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
593 fbc->threshold = ret;
595 if (INTEL_INFO(dev_priv)->gen >= 5)
596 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
597 else if (IS_GM45(dev_priv)) {
598 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
600 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
604 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
609 fbc->compressed_llb = compressed_llb;
611 I915_WRITE(FBC_CFB_BASE,
612 dev_priv->mm.stolen_base + fbc->compressed_fb.start);
613 I915_WRITE(FBC_LL_BASE,
614 dev_priv->mm.stolen_base + compressed_llb->start);
617 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
618 fbc->compressed_fb.size, fbc->threshold);
623 kfree(compressed_llb);
624 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
626 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
630 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
632 struct intel_fbc *fbc = &dev_priv->fbc;
634 if (drm_mm_node_allocated(&fbc->compressed_fb))
635 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
637 if (fbc->compressed_llb) {
638 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
639 kfree(fbc->compressed_llb);
643 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
645 struct intel_fbc *fbc = &dev_priv->fbc;
647 if (!fbc_supported(dev_priv))
650 mutex_lock(&fbc->lock);
651 __intel_fbc_cleanup_cfb(dev_priv);
652 mutex_unlock(&fbc->lock);
655 static bool stride_is_valid(struct drm_i915_private *dev_priv,
658 /* These should have been caught earlier. */
659 WARN_ON(stride < 512);
660 WARN_ON((stride & (64 - 1)) != 0);
662 /* Below are the additional FBC restrictions. */
664 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
665 return stride == 4096 || stride == 8192;
667 if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
676 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
677 uint32_t pixel_format)
679 switch (pixel_format) {
680 case DRM_FORMAT_XRGB8888:
681 case DRM_FORMAT_XBGR8888:
683 case DRM_FORMAT_XRGB1555:
684 case DRM_FORMAT_RGB565:
685 /* 16bpp not supported on gen2 */
686 if (IS_GEN2(dev_priv))
688 /* WaFbcOnly1to1Ratio:ctg */
689 if (IS_G4X(dev_priv))
698 * For some reason, the hardware tracking starts looking at whatever we
699 * programmed as the display plane base address register. It does not look at
700 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
701 * variables instead of just looking at the pipe/plane size.
703 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
705 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
706 struct intel_fbc *fbc = &dev_priv->fbc;
707 unsigned int effective_w, effective_h, max_w, max_h;
709 if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
712 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
720 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
722 effective_w += crtc->adjusted_x;
723 effective_h += crtc->adjusted_y;
725 return effective_w <= max_w && effective_h <= max_h;
728 /* XXX replace me when we have VMA tracking for intel_plane_state */
729 static int get_fence_id(struct drm_framebuffer *fb)
731 struct i915_vma *vma = i915_gem_object_to_ggtt(intel_fb_obj(fb), NULL);
733 return vma && vma->fence ? vma->fence->id : I915_FENCE_REG_NONE;
736 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
737 struct intel_crtc_state *crtc_state,
738 struct intel_plane_state *plane_state)
740 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
741 struct intel_fbc *fbc = &dev_priv->fbc;
742 struct intel_fbc_state_cache *cache = &fbc->state_cache;
743 struct drm_framebuffer *fb = plane_state->base.fb;
744 struct drm_i915_gem_object *obj;
746 cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
747 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
748 cache->crtc.hsw_bdw_pixel_rate =
749 ilk_pipe_pixel_rate(crtc_state);
751 cache->plane.rotation = plane_state->base.rotation;
752 cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
753 cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
754 cache->plane.visible = plane_state->base.visible;
756 if (!cache->plane.visible)
759 obj = intel_fb_obj(fb);
761 /* FIXME: We lack the proper locking here, so only run this on the
762 * platforms that need. */
763 if (IS_GEN(dev_priv, 5, 6))
764 cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
765 cache->fb.pixel_format = fb->pixel_format;
766 cache->fb.stride = fb->pitches[0];
767 cache->fb.fence_reg = get_fence_id(fb);
768 cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
771 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
774 struct intel_fbc *fbc = &dev_priv->fbc;
775 struct intel_fbc_state_cache *cache = &fbc->state_cache;
777 if (!cache->plane.visible) {
778 fbc->no_fbc_reason = "primary plane not visible";
782 if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
783 (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
784 fbc->no_fbc_reason = "incompatible mode";
788 if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
789 fbc->no_fbc_reason = "mode too large for compression";
793 /* The use of a CPU fence is mandatory in order to detect writes
794 * by the CPU to the scanout and trigger updates to the FBC.
796 * Note that is possible for a tiled surface to be unmappable (and
797 * so have no fence associated with it) due to aperture constaints
798 * at the time of pinning.
800 if (cache->fb.tiling_mode != I915_TILING_X ||
801 cache->fb.fence_reg == I915_FENCE_REG_NONE) {
802 if (INTEL_GEN(dev_priv) < 5) {
803 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
807 if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
808 cache->plane.rotation != DRM_ROTATE_0) {
809 fbc->no_fbc_reason = "rotation unsupported";
813 if (!stride_is_valid(dev_priv, cache->fb.stride)) {
814 fbc->no_fbc_reason = "framebuffer stride not supported";
818 if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
819 fbc->no_fbc_reason = "pixel format is invalid";
823 /* WaFbcExceedCdClockThreshold:hsw,bdw */
824 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
825 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
826 fbc->no_fbc_reason = "pixel rate is too big";
830 /* It is possible for the required CFB size change without a
831 * crtc->disable + crtc->enable since it is possible to change the
832 * stride without triggering a full modeset. Since we try to
833 * over-allocate the CFB, there's a chance we may keep FBC enabled even
834 * if this happens, but if we exceed the current CFB size we'll have to
835 * disable FBC. Notice that it would be possible to disable FBC, wait
836 * for a frame, free the stolen node, then try to reenable FBC in case
837 * we didn't get any invalidate/deactivate calls, but this would require
838 * a lot of tracking just for a specific case. If we conclude it's an
839 * important case, we can implement it later. */
840 if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
841 fbc->compressed_fb.size * fbc->threshold) {
842 fbc->no_fbc_reason = "CFB requirements changed";
849 static bool intel_fbc_can_choose(struct intel_crtc *crtc)
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 struct intel_fbc *fbc = &dev_priv->fbc;
854 if (intel_vgpu_active(dev_priv)) {
855 fbc->no_fbc_reason = "VGPU is active";
859 if (!i915.enable_fbc) {
860 fbc->no_fbc_reason = "disabled per module param or by default";
864 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
865 fbc->no_fbc_reason = "no enabled pipes can have FBC";
869 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) {
870 fbc->no_fbc_reason = "no enabled planes can have FBC";
877 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
878 struct intel_fbc_reg_params *params)
880 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
881 struct intel_fbc *fbc = &dev_priv->fbc;
882 struct intel_fbc_state_cache *cache = &fbc->state_cache;
884 /* Since all our fields are integer types, use memset here so the
885 * comparison function can rely on memcmp because the padding will be
887 memset(params, 0, sizeof(*params));
889 params->crtc.pipe = crtc->pipe;
890 params->crtc.plane = crtc->plane;
891 params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
893 params->fb.pixel_format = cache->fb.pixel_format;
894 params->fb.stride = cache->fb.stride;
895 params->fb.fence_reg = cache->fb.fence_reg;
897 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
899 params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
902 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
903 struct intel_fbc_reg_params *params2)
905 /* We can use this since intel_fbc_get_reg_params() does a memset. */
906 return memcmp(params1, params2, sizeof(*params1)) == 0;
909 void intel_fbc_pre_update(struct intel_crtc *crtc,
910 struct intel_crtc_state *crtc_state,
911 struct intel_plane_state *plane_state)
913 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
914 struct intel_fbc *fbc = &dev_priv->fbc;
916 if (!fbc_supported(dev_priv))
919 mutex_lock(&fbc->lock);
921 if (!multiple_pipes_ok(crtc, plane_state)) {
922 fbc->no_fbc_reason = "more than one pipe active";
926 if (!fbc->enabled || fbc->crtc != crtc)
929 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
932 intel_fbc_deactivate(dev_priv);
934 mutex_unlock(&fbc->lock);
937 static void __intel_fbc_post_update(struct intel_crtc *crtc)
939 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
940 struct intel_fbc *fbc = &dev_priv->fbc;
941 struct intel_fbc_reg_params old_params;
943 WARN_ON(!mutex_is_locked(&fbc->lock));
945 if (!fbc->enabled || fbc->crtc != crtc)
948 if (!intel_fbc_can_activate(crtc)) {
949 WARN_ON(fbc->active);
953 old_params = fbc->params;
954 intel_fbc_get_reg_params(crtc, &fbc->params);
956 /* If the scanout has not changed, don't modify the FBC settings.
957 * Note that we make the fundamental assumption that the fb->obj
958 * cannot be unpinned (and have its GTT offset and fence revoked)
959 * without first being decoupled from the scanout and FBC disabled.
962 intel_fbc_reg_params_equal(&old_params, &fbc->params))
965 intel_fbc_deactivate(dev_priv);
966 intel_fbc_schedule_activation(crtc);
967 fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
970 void intel_fbc_post_update(struct intel_crtc *crtc)
972 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
973 struct intel_fbc *fbc = &dev_priv->fbc;
975 if (!fbc_supported(dev_priv))
978 mutex_lock(&fbc->lock);
979 __intel_fbc_post_update(crtc);
980 mutex_unlock(&fbc->lock);
983 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
986 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
988 return fbc->possible_framebuffer_bits;
991 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
992 unsigned int frontbuffer_bits,
993 enum fb_op_origin origin)
995 struct intel_fbc *fbc = &dev_priv->fbc;
997 if (!fbc_supported(dev_priv))
1000 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1003 mutex_lock(&fbc->lock);
1005 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1007 if (fbc->enabled && fbc->busy_bits)
1008 intel_fbc_deactivate(dev_priv);
1010 mutex_unlock(&fbc->lock);
1013 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1014 unsigned int frontbuffer_bits, enum fb_op_origin origin)
1016 struct intel_fbc *fbc = &dev_priv->fbc;
1018 if (!fbc_supported(dev_priv))
1021 mutex_lock(&fbc->lock);
1023 fbc->busy_bits &= ~frontbuffer_bits;
1025 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1028 if (!fbc->busy_bits && fbc->enabled &&
1029 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1031 intel_fbc_recompress(dev_priv);
1033 __intel_fbc_post_update(fbc->crtc);
1037 mutex_unlock(&fbc->lock);
1041 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1042 * @dev_priv: i915 device instance
1043 * @state: the atomic state structure
1045 * This function looks at the proposed state for CRTCs and planes, then chooses
1046 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1049 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1050 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1052 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1053 struct drm_atomic_state *state)
1055 struct intel_fbc *fbc = &dev_priv->fbc;
1056 struct drm_crtc *crtc;
1057 struct drm_crtc_state *crtc_state;
1058 struct drm_plane *plane;
1059 struct drm_plane_state *plane_state;
1060 bool fbc_crtc_present = false;
1063 mutex_lock(&fbc->lock);
1065 for_each_crtc_in_state(state, crtc, crtc_state, i) {
1066 if (fbc->crtc == to_intel_crtc(crtc)) {
1067 fbc_crtc_present = true;
1071 /* This atomic commit doesn't involve the CRTC currently tied to FBC. */
1072 if (!fbc_crtc_present && fbc->crtc != NULL)
1075 /* Simply choose the first CRTC that is compatible and has a visible
1076 * plane. We could go for fancier schemes such as checking the plane
1077 * size, but this would just affect the few platforms that don't tie FBC
1078 * to pipe or plane A. */
1079 for_each_plane_in_state(state, plane, plane_state, i) {
1080 struct intel_plane_state *intel_plane_state =
1081 to_intel_plane_state(plane_state);
1083 if (!intel_plane_state->base.visible)
1086 for_each_crtc_in_state(state, crtc, crtc_state, j) {
1087 struct intel_crtc_state *intel_crtc_state =
1088 to_intel_crtc_state(crtc_state);
1090 if (plane_state->crtc != crtc)
1093 if (!intel_fbc_can_choose(to_intel_crtc(crtc)))
1096 intel_crtc_state->enable_fbc = true;
1102 mutex_unlock(&fbc->lock);
1106 * intel_fbc_enable: tries to enable FBC on the CRTC
1108 * @crtc_state: corresponding &drm_crtc_state for @crtc
1109 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1111 * This function checks if the given CRTC was chosen for FBC, then enables it if
1112 * possible. Notice that it doesn't activate FBC. It is valid to call
1113 * intel_fbc_enable multiple times for the same pipe without an
1114 * intel_fbc_disable in the middle, as long as it is deactivated.
1116 void intel_fbc_enable(struct intel_crtc *crtc,
1117 struct intel_crtc_state *crtc_state,
1118 struct intel_plane_state *plane_state)
1120 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1121 struct intel_fbc *fbc = &dev_priv->fbc;
1123 if (!fbc_supported(dev_priv))
1126 mutex_lock(&fbc->lock);
1129 WARN_ON(fbc->crtc == NULL);
1130 if (fbc->crtc == crtc) {
1131 WARN_ON(!crtc_state->enable_fbc);
1132 WARN_ON(fbc->active);
1137 if (!crtc_state->enable_fbc)
1140 WARN_ON(fbc->active);
1141 WARN_ON(fbc->crtc != NULL);
1143 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1144 if (intel_fbc_alloc_cfb(crtc)) {
1145 fbc->no_fbc_reason = "not enough stolen memory";
1149 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1150 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1152 fbc->enabled = true;
1155 mutex_unlock(&fbc->lock);
1159 * __intel_fbc_disable - disable FBC
1160 * @dev_priv: i915 device instance
1162 * This is the low level function that actually disables FBC. Callers should
1163 * grab the FBC lock.
1165 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1167 struct intel_fbc *fbc = &dev_priv->fbc;
1168 struct intel_crtc *crtc = fbc->crtc;
1170 WARN_ON(!mutex_is_locked(&fbc->lock));
1171 WARN_ON(!fbc->enabled);
1172 WARN_ON(fbc->active);
1173 WARN_ON(crtc->active);
1175 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1177 __intel_fbc_cleanup_cfb(dev_priv);
1179 fbc->enabled = false;
1184 * intel_fbc_disable - disable FBC if it's associated with crtc
1187 * This function disables FBC if it's associated with the provided CRTC.
1189 void intel_fbc_disable(struct intel_crtc *crtc)
1191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1192 struct intel_fbc *fbc = &dev_priv->fbc;
1194 if (!fbc_supported(dev_priv))
1197 mutex_lock(&fbc->lock);
1198 if (fbc->crtc == crtc)
1199 __intel_fbc_disable(dev_priv);
1200 mutex_unlock(&fbc->lock);
1202 cancel_work_sync(&fbc->work.work);
1206 * intel_fbc_global_disable - globally disable FBC
1207 * @dev_priv: i915 device instance
1209 * This function disables FBC regardless of which CRTC is associated with it.
1211 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1213 struct intel_fbc *fbc = &dev_priv->fbc;
1215 if (!fbc_supported(dev_priv))
1218 mutex_lock(&fbc->lock);
1220 __intel_fbc_disable(dev_priv);
1221 mutex_unlock(&fbc->lock);
1223 cancel_work_sync(&fbc->work.work);
1227 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1228 * @dev_priv: i915 device instance
1230 * The FBC code needs to track CRTC visibility since the older platforms can't
1231 * have FBC enabled while multiple pipes are used. This function does the
1232 * initial setup at driver load to make sure FBC is matching the real hardware.
1234 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1236 struct intel_crtc *crtc;
1238 /* Don't even bother tracking anything if we don't need. */
1239 if (!no_fbc_on_multiple_pipes(dev_priv))
1242 for_each_intel_crtc(&dev_priv->drm, crtc)
1243 if (intel_crtc_active(&crtc->base) &&
1244 to_intel_plane_state(crtc->base.primary->state)->base.visible)
1245 dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1249 * The DDX driver changes its behavior depending on the value it reads from
1250 * i915.enable_fbc, so sanitize it by translating the default value into either
1251 * 0 or 1 in order to allow it to know what's going on.
1253 * Notice that this is done at driver initialization and we still allow user
1254 * space to change the value during runtime without sanitizing it again. IGT
1255 * relies on being able to change i915.enable_fbc at runtime.
1257 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1259 if (i915.enable_fbc >= 0)
1260 return !!i915.enable_fbc;
1262 if (!HAS_FBC(dev_priv))
1265 if (IS_BROADWELL(dev_priv))
1271 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1273 #ifdef CONFIG_INTEL_IOMMU
1274 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1275 if (intel_iommu_gfx_mapped &&
1276 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1277 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1286 * intel_fbc_init - Initialize FBC
1287 * @dev_priv: the i915 device
1289 * This function might be called during PM init process.
1291 void intel_fbc_init(struct drm_i915_private *dev_priv)
1293 struct intel_fbc *fbc = &dev_priv->fbc;
1296 INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1297 mutex_init(&fbc->lock);
1298 fbc->enabled = false;
1299 fbc->active = false;
1300 fbc->work.scheduled = false;
1302 if (need_fbc_vtd_wa(dev_priv))
1303 mkwrite_device_info(dev_priv)->has_fbc = false;
1305 i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1306 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1308 if (!HAS_FBC(dev_priv)) {
1309 fbc->no_fbc_reason = "unsupported by this chipset";
1313 for_each_pipe(dev_priv, pipe) {
1314 fbc->possible_framebuffer_bits |=
1315 INTEL_FRONTBUFFER_PRIMARY(pipe);
1317 if (fbc_on_pipe_a_only(dev_priv))
1321 /* This value was pulled out of someone's hat */
1322 if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_GM45(dev_priv))
1323 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1325 /* We still don't have any sort of hardware state readout for FBC, so
1326 * deactivate it in case the BIOS activated it to make sure software
1327 * matches the hardware state. */
1328 if (intel_fbc_hw_is_active(dev_priv))
1329 intel_fbc_hw_deactivate(dev_priv);