drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return dev_priv->fbc.enable_fbc != NULL;
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8;
  52 }
  53
  54 /*
  55  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  56  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  57  * origin so the x and y offsets can actually fit the registers. As a
  58  * consequence, the fence doesn't really start exactly at the display plane
  59  * address we program because it starts at the real start of the buffer, so we
  60  * have to take this into consideration here.
  61  */
  62 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  63 {
  64         return crtc->base.y - crtc->adjusted_y;
  65 }
  66
  67 static void i8xx_fbc_disable(struct drm_i915_private *dev_priv)
  68 {
  69         u32 fbc_ctl;
  70
  71         dev_priv->fbc.enabled = false;
  72
  73         /* Disable compression */
  74         fbc_ctl = I915_READ(FBC_CONTROL);
  75         if ((fbc_ctl & FBC_CTL_EN) == 0)
  76                 return;
  77
  78         fbc_ctl &= ~FBC_CTL_EN;
  79         I915_WRITE(FBC_CONTROL, fbc_ctl);
  80
  81         /* Wait for compressing bit to clear */
  82         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  83                 DRM_DEBUG_KMS("FBC idle timed out\n");
  84                 return;
  85         }
  86
  87         DRM_DEBUG_KMS("disabled FBC\n");
  88 }
  89
  90 static void i8xx_fbc_enable(struct intel_crtc *crtc)
  91 {
  92         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  93         struct drm_framebuffer *fb = crtc->base.primary->fb;
  94         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  95         int cfb_pitch;
  96         int i;
  97         u32 fbc_ctl;
  98
  99         dev_priv->fbc.enabled = true;
 100
 101         /* Note: fbc.threshold == 1 for i8xx */
 102         cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
 103         if (fb->pitches[0] < cfb_pitch)
 104                 cfb_pitch = fb->pitches[0];
 105
 106         /* FBC_CTL wants 32B or 64B units */
 107         if (IS_GEN2(dev_priv))
 108                 cfb_pitch = (cfb_pitch / 32) - 1;
 109         else
 110                 cfb_pitch = (cfb_pitch / 64) - 1;
 111
 112         /* Clear old tags */
 113         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 114                 I915_WRITE(FBC_TAG(i), 0);
 115
 116         if (IS_GEN4(dev_priv)) {
 117                 u32 fbc_ctl2;
 118
 119                 /* Set it up... */
 120                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 121                 fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane);
 122                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 123                 I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc));
 124         }
 125
 126         /* enable it... */
 127         fbc_ctl = I915_READ(FBC_CONTROL);
 128         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 129         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 130         if (IS_I945GM(dev_priv))
 131                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 132         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 133         fbc_ctl |= obj->fence_reg;
 134         I915_WRITE(FBC_CONTROL, fbc_ctl);
 135
 136         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 137                       cfb_pitch, crtc->base.y, plane_name(crtc->plane));
 138 }
 139
 140 static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv)
 141 {
 142         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 143 }
 144
 145 static void g4x_fbc_enable(struct intel_crtc *crtc)
 146 {
 147         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 148         struct drm_framebuffer *fb = crtc->base.primary->fb;
 149         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 150         u32 dpfc_ctl;
 151
 152         dev_priv->fbc.enabled = true;
 153
 154         dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN;
 155         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 156                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 157         else
 158                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 159         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 160
 161         I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc));
 162
 163         /* enable it... */
 164         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 165
 166         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 167 }
 168
 169 static void g4x_fbc_disable(struct drm_i915_private *dev_priv)
 170 {
 171         u32 dpfc_ctl;
 172
 173         dev_priv->fbc.enabled = false;
 174
 175         /* Disable compression */
 176         dpfc_ctl = I915_READ(DPFC_CONTROL);
 177         if (dpfc_ctl & DPFC_CTL_EN) {
 178                 dpfc_ctl &= ~DPFC_CTL_EN;
 179                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 180
 181                 DRM_DEBUG_KMS("disabled FBC\n");
 182         }
 183 }
 184
 185 static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv)
 186 {
 187         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 188 }
 189
 190 /* This function forces a CFB recompression through the nuke operation. */
 191 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 192 {
 193         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 194         POSTING_READ(MSG_FBC_REND_STATE);
 195 }
 196
 197 static void ilk_fbc_enable(struct intel_crtc *crtc)
 198 {
 199         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->base.primary->fb;
 201         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 202         u32 dpfc_ctl;
 203         int threshold = dev_priv->fbc.threshold;
 204         unsigned int y_offset;
 205
 206         dev_priv->fbc.enabled = true;
 207
 208         dpfc_ctl = DPFC_CTL_PLANE(crtc->plane);
 209         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 210                 threshold++;
 211
 212         switch (threshold) {
 213         case 4:
 214         case 3:
 215                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 216                 break;
 217         case 2:
 218                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 219                 break;
 220         case 1:
 221                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 222                 break;
 223         }
 224         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 225         if (IS_GEN5(dev_priv))
 226                 dpfc_ctl |= obj->fence_reg;
 227
 228         y_offset = get_crtc_fence_y_offset(crtc);
 229         I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset);
 230         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 231         /* enable it... */
 232         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 233
 234         if (IS_GEN6(dev_priv)) {
 235                 I915_WRITE(SNB_DPFC_CTL_SA,
 236                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 237                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset);
 238         }
 239
 240         intel_fbc_recompress(dev_priv);
 241
 242         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 243 }
 244
 245 static void ilk_fbc_disable(struct drm_i915_private *dev_priv)
 246 {
 247         u32 dpfc_ctl;
 248
 249         dev_priv->fbc.enabled = false;
 250
 251         /* Disable compression */
 252         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 253         if (dpfc_ctl & DPFC_CTL_EN) {
 254                 dpfc_ctl &= ~DPFC_CTL_EN;
 255                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 256
 257                 DRM_DEBUG_KMS("disabled FBC\n");
 258         }
 259 }
 260
 261 static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv)
 262 {
 263         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 264 }
 265
 266 static void gen7_fbc_enable(struct intel_crtc *crtc)
 267 {
 268         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 269         struct drm_framebuffer *fb = crtc->base.primary->fb;
 270         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 271         u32 dpfc_ctl;
 272         int threshold = dev_priv->fbc.threshold;
 273
 274         dev_priv->fbc.enabled = true;
 275
 276         dpfc_ctl = 0;
 277         if (IS_IVYBRIDGE(dev_priv))
 278                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane);
 279
 280         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 281                 threshold++;
 282
 283         switch (threshold) {
 284         case 4:
 285         case 3:
 286                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 287                 break;
 288         case 2:
 289                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 290                 break;
 291         case 1:
 292                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 293                 break;
 294         }
 295
 296         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 297
 298         if (dev_priv->fbc.false_color)
 299                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 300
 301         if (IS_IVYBRIDGE(dev_priv)) {
 302                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 303                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 304                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 305                            ILK_FBCQ_DIS);
 306         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 307                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 308                 I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe),
 309                            I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) |
 310                            HSW_FBCQ_DIS);
 311         }
 312
 313         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 314
 315         I915_WRITE(SNB_DPFC_CTL_SA,
 316                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 317         I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc));
 318
 319         intel_fbc_recompress(dev_priv);
 320
 321         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane));
 322 }
 323
 324 /**
 325  * intel_fbc_enabled - Is FBC enabled?
 326  * @dev_priv: i915 device instance
 327  *
 328  * This function is used to verify the current state of FBC.
 329  * FIXME: This should be tracked in the plane config eventually
 330  *        instead of queried at runtime for most callers.
 331  */
 332 bool intel_fbc_enabled(struct drm_i915_private *dev_priv)
 333 {
 334         return dev_priv->fbc.enabled;
 335 }
 336
 337 static void intel_fbc_enable(const struct drm_framebuffer *fb)
 338 {
 339         struct drm_i915_private *dev_priv = fb->dev->dev_private;
 340         struct intel_crtc *crtc = dev_priv->fbc.crtc;
 341
 342         dev_priv->fbc.enable_fbc(crtc);
 343
 344         dev_priv->fbc.fb_id = fb->base.id;
 345         dev_priv->fbc.y = crtc->base.y;
 346 }
 347
 348 static void intel_fbc_work_fn(struct work_struct *__work)
 349 {
 350         struct intel_fbc_work *work =
 351                 container_of(to_delayed_work(__work),
 352                              struct intel_fbc_work, work);
 353         struct drm_i915_private *dev_priv = work->fb->dev->dev_private;
 354         struct drm_framebuffer *crtc_fb = dev_priv->fbc.crtc->base.primary->fb;
 355
 356         mutex_lock(&dev_priv->fbc.lock);
 357         if (work == dev_priv->fbc.fbc_work) {
 358                 /* Double check that we haven't switched fb without cancelling
 359                  * the prior work.
 360                  */
 361                 if (crtc_fb == work->fb)
 362                         intel_fbc_enable(work->fb);
 363
 364                 dev_priv->fbc.fbc_work = NULL;
 365         }
 366         mutex_unlock(&dev_priv->fbc.lock);
 367
 368         kfree(work);
 369 }
 370
 371 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv)
 372 {
 373         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 374
 375         if (dev_priv->fbc.fbc_work == NULL)
 376                 return;
 377
 378         /* Synchronisation is provided by struct_mutex and checking of
 379          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 380          * entirely asynchronously.
 381          */
 382         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 383                 /* tasklet was killed before being run, clean up */
 384                 kfree(dev_priv->fbc.fbc_work);
 385
 386         /* Mark the work as no longer wanted so that if it does
 387          * wake-up (because the work was already running and waiting
 388          * for our mutex), it will discover that is no longer
 389          * necessary to run.
 390          */
 391         dev_priv->fbc.fbc_work = NULL;
 392 }
 393
 394 static void intel_fbc_schedule_enable(struct intel_crtc *crtc)
 395 {
 396         struct intel_fbc_work *work;
 397         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 398
 399         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 400
 401         intel_fbc_cancel_work(dev_priv);
 402         dev_priv->fbc.crtc = crtc;
 403
 404         work = kzalloc(sizeof(*work), GFP_KERNEL);
 405         if (work == NULL) {
 406                 DRM_ERROR("Failed to allocate FBC work structure\n");
 407                 intel_fbc_enable(crtc->base.primary->fb);
 408                 return;
 409         }
 410
 411         work->fb = crtc->base.primary->fb;
 412         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 413
 414         dev_priv->fbc.fbc_work = work;
 415
 416         /* Delay the actual enabling to let pageflipping cease and the
 417          * display to settle before starting the compression. Note that
 418          * this delay also serves a second purpose: it allows for a
 419          * vblank to pass after disabling the FBC before we attempt
 420          * to modify the control registers.
 421          *
 422          * A more complicated solution would involve tracking vblanks
 423          * following the termination of the page-flipping sequence
 424          * and indeed performing the enable as a co-routine and not
 425          * waiting synchronously upon the vblank.
 426          *
 427          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 428          */
 429         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 430 }
 431
 432 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 433 {
 434         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 435
 436         intel_fbc_cancel_work(dev_priv);
 437
 438         if (dev_priv->fbc.enabled)
 439                 dev_priv->fbc.disable_fbc(dev_priv);
 440 }
 441
 442 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 443 {
 444         intel_fbc_deactivate(dev_priv);
 445         dev_priv->fbc.crtc = NULL;
 446 }
 447
 448 /**
 449  * intel_fbc_disable - disable FBC
 450  * @dev_priv: i915 device instance
 451  *
 452  * This function disables FBC.
 453  */
 454 void intel_fbc_disable(struct drm_i915_private *dev_priv)
 455 {
 456         if (!fbc_supported(dev_priv))
 457                 return;
 458
 459         mutex_lock(&dev_priv->fbc.lock);
 460         __intel_fbc_disable(dev_priv);
 461         mutex_unlock(&dev_priv->fbc.lock);
 462 }
 463
 464 /*
 465  * intel_fbc_disable_crtc - disable FBC if it's associated with crtc
 466  * @crtc: the CRTC
 467  *
 468  * This function disables FBC if it's associated with the provided CRTC.
 469  */
 470 void intel_fbc_disable_crtc(struct intel_crtc *crtc)
 471 {
 472         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 473
 474         if (!fbc_supported(dev_priv))
 475                 return;
 476
 477         mutex_lock(&dev_priv->fbc.lock);
 478         if (dev_priv->fbc.crtc == crtc)
 479                 __intel_fbc_disable(dev_priv);
 480         mutex_unlock(&dev_priv->fbc.lock);
 481 }
 482
 483 static void set_no_fbc_reason(struct drm_i915_private *dev_priv,
 484                               const char *reason)
 485 {
 486         if (dev_priv->fbc.no_fbc_reason == reason)
 487                 return;
 488
 489         dev_priv->fbc.no_fbc_reason = reason;
 490         DRM_DEBUG_KMS("Disabling FBC: %s\n", reason);
 491 }
 492
 493 static bool crtc_is_valid(struct intel_crtc *crtc)
 494 {
 495         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 496
 497         if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
 498                 return false;
 499
 500         if (!intel_crtc_active(&crtc->base))
 501                 return false;
 502
 503         if (!to_intel_plane_state(crtc->base.primary->state)->visible)
 504                 return false;
 505
 506         return true;
 507 }
 508
 509 static bool multiple_pipes_ok(struct drm_i915_private *dev_priv)
 510 {
 511         enum pipe pipe;
 512         int n_pipes = 0;
 513         struct drm_crtc *crtc;
 514
 515         if (INTEL_INFO(dev_priv)->gen > 4)
 516                 return true;
 517
 518         for_each_pipe(dev_priv, pipe) {
 519                 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 520
 521                 if (intel_crtc_active(crtc) &&
 522                     to_intel_plane_state(crtc->primary->state)->visible)
 523                         n_pipes++;
 524         }
 525
 526         return (n_pipes < 2);
 527 }
 528
 529 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 530                                       struct drm_mm_node *node,
 531                                       int size,
 532                                       int fb_cpp)
 533 {
 534         int compression_threshold = 1;
 535         int ret;
 536         u64 end;
 537
 538         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 539          * reserved range size, so it always assumes the maximum (8mb) is used.
 540          * If we enable FBC using a CFB on that memory range we'll get FIFO
 541          * underruns, even if that range is not reserved by the BIOS. */
 542         if (IS_BROADWELL(dev_priv) ||
 543             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 544                 end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024;
 545         else
 546                 end = dev_priv->gtt.stolen_usable_size;
 547
 548         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 549          * code changes, this code needs to change as well.
 550          *
 551          * The enable_fbc code will attempt to use one of our 2 compression
 552          * thresholds, therefore, in that case, we only have 1 resort.
 553          */
 554
 555         /* Try to over-allocate to reduce reallocations and fragmentation. */
 556         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 557                                                    4096, 0, end);
 558         if (ret == 0)
 559                 return compression_threshold;
 560
 561 again:
 562         /* HW's ability to limit the CFB is 1:4 */
 563         if (compression_threshold > 4 ||
 564             (fb_cpp == 2 && compression_threshold == 2))
 565                 return 0;
 566
 567         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 568                                                    4096, 0, end);
 569         if (ret && INTEL_INFO(dev_priv)->gen <= 4) {
 570                 return 0;
 571         } else if (ret) {
 572                 compression_threshold <<= 1;
 573                 goto again;
 574         } else {
 575                 return compression_threshold;
 576         }
 577 }
 578
 579 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size,
 580                                int fb_cpp)
 581 {
 582         struct drm_mm_node *uninitialized_var(compressed_llb);
 583         int ret;
 584
 585         ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb,
 586                                          size, fb_cpp);
 587         if (!ret)
 588                 goto err_llb;
 589         else if (ret > 1) {
 590                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 591
 592         }
 593
 594         dev_priv->fbc.threshold = ret;
 595
 596         if (INTEL_INFO(dev_priv)->gen >= 5)
 597                 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
 598         else if (IS_GM45(dev_priv)) {
 599                 I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
 600         } else {
 601                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 602                 if (!compressed_llb)
 603                         goto err_fb;
 604
 605                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 606                                                   4096, 4096);
 607                 if (ret)
 608                         goto err_fb;
 609
 610                 dev_priv->fbc.compressed_llb = compressed_llb;
 611
 612                 I915_WRITE(FBC_CFB_BASE,
 613                            dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start);
 614                 I915_WRITE(FBC_LL_BASE,
 615                            dev_priv->mm.stolen_base + compressed_llb->start);
 616         }
 617
 618         dev_priv->fbc.uncompressed_size = size;
 619
 620         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 621                       dev_priv->fbc.compressed_fb.size,
 622                       dev_priv->fbc.threshold);
 623
 624         return 0;
 625
 626 err_fb:
 627         kfree(compressed_llb);
 628         i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb);
 629 err_llb:
 630         pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 631         return -ENOSPC;
 632 }
 633
 634 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 635 {
 636         if (dev_priv->fbc.uncompressed_size == 0)
 637                 return;
 638
 639         i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb);
 640
 641         if (dev_priv->fbc.compressed_llb) {
 642                 i915_gem_stolen_remove_node(dev_priv,
 643                                             dev_priv->fbc.compressed_llb);
 644                 kfree(dev_priv->fbc.compressed_llb);
 645         }
 646
 647         dev_priv->fbc.uncompressed_size = 0;
 648 }
 649
 650 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 651 {
 652         if (!fbc_supported(dev_priv))
 653                 return;
 654
 655         mutex_lock(&dev_priv->fbc.lock);
 656         __intel_fbc_cleanup_cfb(dev_priv);
 657         mutex_unlock(&dev_priv->fbc.lock);
 658 }
 659
 660 /*
 661  * For SKL+, the plane source size used by the hardware is based on the value we
 662  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
 663  * we wrote to PIPESRC.
 664  */
 665 static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc,
 666                                             int *width, int *height)
 667 {
 668         struct intel_plane_state *plane_state =
 669                         to_intel_plane_state(crtc->base.primary->state);
 670         int w, h;
 671
 672         if (intel_rotation_90_or_270(plane_state->base.rotation)) {
 673                 w = drm_rect_height(&plane_state->src) >> 16;
 674                 h = drm_rect_width(&plane_state->src) >> 16;
 675         } else {
 676                 w = drm_rect_width(&plane_state->src) >> 16;
 677                 h = drm_rect_height(&plane_state->src) >> 16;
 678         }
 679
 680         if (width)
 681                 *width = w;
 682         if (height)
 683                 *height = h;
 684 }
 685
 686 static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc)
 687 {
 688         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 689         struct drm_framebuffer *fb = crtc->base.primary->fb;
 690         int lines;
 691
 692         intel_fbc_get_plane_source_size(crtc, NULL, &lines);
 693         if (INTEL_INFO(dev_priv)->gen >= 7)
 694                 lines = min(lines, 2048);
 695
 696         /* Hardware needs the full buffer stride, not just the active area. */
 697         return lines * fb->pitches[0];
 698 }
 699
 700 static int intel_fbc_setup_cfb(struct intel_crtc *crtc)
 701 {
 702         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 703         struct drm_framebuffer *fb = crtc->base.primary->fb;
 704         int size, cpp;
 705
 706         size = intel_fbc_calculate_cfb_size(crtc);
 707         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 708
 709         if (drm_mm_node_allocated(&dev_priv->fbc.compressed_fb) &&
 710             size <= dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold)
 711                 return 0;
 712
 713         /* Release any current block */
 714         __intel_fbc_cleanup_cfb(dev_priv);
 715
 716         return intel_fbc_alloc_cfb(dev_priv, size, cpp);
 717 }
 718
 719 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 720                             unsigned int stride)
 721 {
 722         /* These should have been caught earlier. */
 723         WARN_ON(stride < 512);
 724         WARN_ON((stride & (64 - 1)) != 0);
 725
 726         /* Below are the additional FBC restrictions. */
 727
 728         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 729                 return stride == 4096 || stride == 8192;
 730
 731         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 732                 return false;
 733
 734         if (stride > 16384)
 735                 return false;
 736
 737         return true;
 738 }
 739
 740 static bool pixel_format_is_valid(struct drm_framebuffer *fb)
 741 {
 742         struct drm_device *dev = fb->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744
 745         switch (fb->pixel_format) {
 746         case DRM_FORMAT_XRGB8888:
 747         case DRM_FORMAT_XBGR8888:
 748                 return true;
 749         case DRM_FORMAT_XRGB1555:
 750         case DRM_FORMAT_RGB565:
 751                 /* 16bpp not supported on gen2 */
 752                 if (IS_GEN2(dev))
 753                         return false;
 754                 /* WaFbcOnly1to1Ratio:ctg */
 755                 if (IS_G4X(dev_priv))
 756                         return false;
 757                 return true;
 758         default:
 759                 return false;
 760         }
 761 }
 762
 763 /*
 764  * For some reason, the hardware tracking starts looking at whatever we
 765  * programmed as the display plane base address register. It does not look at
 766  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 767  * variables instead of just looking at the pipe/plane size.
 768  */
 769 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 770 {
 771         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 772         unsigned int effective_w, effective_h, max_w, max_h;
 773
 774         if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) {
 775                 max_w = 4096;
 776                 max_h = 4096;
 777         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
 778                 max_w = 4096;
 779                 max_h = 2048;
 780         } else {
 781                 max_w = 2048;
 782                 max_h = 1536;
 783         }
 784
 785         intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h);
 786         effective_w += crtc->adjusted_x;
 787         effective_h += crtc->adjusted_y;
 788
 789         return effective_w <= max_w && effective_h <= max_h;
 790 }
 791
 792 /**
 793  * __intel_fbc_update - enable/disable FBC as needed, unlocked
 794  * @crtc: the CRTC that triggered the update
 795  *
 796  * This function completely reevaluates the status of FBC, then enables,
 797  * disables or maintains it on the same state.
 798  */
 799 static void __intel_fbc_update(struct intel_crtc *crtc)
 800 {
 801         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 802         struct drm_framebuffer *fb;
 803         struct drm_i915_gem_object *obj;
 804         const struct drm_display_mode *adjusted_mode;
 805
 806         WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock));
 807
 808         if (!multiple_pipes_ok(dev_priv)) {
 809                 set_no_fbc_reason(dev_priv, "more than one pipe active");
 810                 goto out_disable;
 811         }
 812
 813         if (dev_priv->fbc.crtc != NULL && dev_priv->fbc.crtc != crtc)
 814                 return;
 815
 816         if (intel_vgpu_active(dev_priv->dev))
 817                 i915.enable_fbc = 0;
 818
 819         if (i915.enable_fbc < 0) {
 820                 set_no_fbc_reason(dev_priv, "disabled per chip default");
 821                 goto out_disable;
 822         }
 823
 824         if (!i915.enable_fbc) {
 825                 set_no_fbc_reason(dev_priv, "disabled per module param");
 826                 goto out_disable;
 827         }
 828
 829         if (!crtc_is_valid(crtc)) {
 830                 set_no_fbc_reason(dev_priv, "no output");
 831                 goto out_disable;
 832         }
 833
 834         fb = crtc->base.primary->fb;
 835         obj = intel_fb_obj(fb);
 836         adjusted_mode = &crtc->config->base.adjusted_mode;
 837
 838         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 839             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 840                 set_no_fbc_reason(dev_priv, "incompatible mode");
 841                 goto out_disable;
 842         }
 843
 844         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 845                 set_no_fbc_reason(dev_priv, "mode too large for compression");
 846                 goto out_disable;
 847         }
 848
 849         if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) &&
 850             crtc->plane != PLANE_A) {
 851                 set_no_fbc_reason(dev_priv, "FBC unsupported on plane");
 852                 goto out_disable;
 853         }
 854
 855         /* The use of a CPU fence is mandatory in order to detect writes
 856          * by the CPU to the scanout and trigger updates to the FBC.
 857          */
 858         if (obj->tiling_mode != I915_TILING_X ||
 859             obj->fence_reg == I915_FENCE_REG_NONE) {
 860                 set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced");
 861                 goto out_disable;
 862         }
 863         if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
 864             crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) {
 865                 set_no_fbc_reason(dev_priv, "rotation unsupported");
 866                 goto out_disable;
 867         }
 868
 869         if (!stride_is_valid(dev_priv, fb->pitches[0])) {
 870                 set_no_fbc_reason(dev_priv, "framebuffer stride not supported");
 871                 goto out_disable;
 872         }
 873
 874         if (!pixel_format_is_valid(fb)) {
 875                 set_no_fbc_reason(dev_priv, "pixel format is invalid");
 876                 goto out_disable;
 877         }
 878
 879         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 880         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 881             ilk_pipe_pixel_rate(crtc->config) >=
 882             dev_priv->cdclk_freq * 95 / 100) {
 883                 set_no_fbc_reason(dev_priv, "pixel rate is too big");
 884                 goto out_disable;
 885         }
 886
 887         if (intel_fbc_setup_cfb(crtc)) {
 888                 set_no_fbc_reason(dev_priv, "not enough stolen memory");
 889                 goto out_disable;
 890         }
 891
 892         /* If the scanout has not changed, don't modify the FBC settings.
 893          * Note that we make the fundamental assumption that the fb->obj
 894          * cannot be unpinned (and have its GTT offset and fence revoked)
 895          * without first being decoupled from the scanout and FBC disabled.
 896          */
 897         if (dev_priv->fbc.crtc == crtc &&
 898             dev_priv->fbc.fb_id == fb->base.id &&
 899             dev_priv->fbc.y == crtc->base.y &&
 900             dev_priv->fbc.enabled)
 901                 return;
 902
 903         if (intel_fbc_enabled(dev_priv)) {
 904                 /* We update FBC along two paths, after changing fb/crtc
 905                  * configuration (modeswitching) and after page-flipping
 906                  * finishes. For the latter, we know that not only did
 907                  * we disable the FBC at the start of the page-flip
 908                  * sequence, but also more than one vblank has passed.
 909                  *
 910                  * For the former case of modeswitching, it is possible
 911                  * to switch between two FBC valid configurations
 912                  * instantaneously so we do need to disable the FBC
 913                  * before we can modify its control registers. We also
 914                  * have to wait for the next vblank for that to take
 915                  * effect. However, since we delay enabling FBC we can
 916                  * assume that a vblank has passed since disabling and
 917                  * that we can safely alter the registers in the deferred
 918                  * callback.
 919                  *
 920                  * In the scenario that we go from a valid to invalid
 921                  * and then back to valid FBC configuration we have
 922                  * no strict enforcement that a vblank occurred since
 923                  * disabling the FBC. However, along all current pipe
 924                  * disabling paths we do need to wait for a vblank at
 925                  * some point. And we wait before enabling FBC anyway.
 926                  */
 927                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 928                 __intel_fbc_disable(dev_priv);
 929         }
 930
 931         intel_fbc_schedule_enable(crtc);
 932         dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)";
 933         return;
 934
 935 out_disable:
 936         /* Multiple disables should be harmless */
 937         if (intel_fbc_enabled(dev_priv)) {
 938                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 939                 __intel_fbc_disable(dev_priv);
 940         }
 941         __intel_fbc_cleanup_cfb(dev_priv);
 942 }
 943
 944 /*
 945  * intel_fbc_update - enable/disable FBC as needed
 946  * @crtc: the CRTC that triggered the update
 947  *
 948  * This function reevaluates the overall state and enables or disables FBC.
 949  */
 950 void intel_fbc_update(struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 953
 954         if (!fbc_supported(dev_priv))
 955                 return;
 956
 957         mutex_lock(&dev_priv->fbc.lock);
 958         __intel_fbc_update(crtc);
 959         mutex_unlock(&dev_priv->fbc.lock);
 960 }
 961
 962 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 963                           unsigned int frontbuffer_bits,
 964                           enum fb_op_origin origin)
 965 {
 966         unsigned int fbc_bits;
 967
 968         if (!fbc_supported(dev_priv))
 969                 return;
 970
 971         if (origin == ORIGIN_GTT)
 972                 return;
 973
 974         mutex_lock(&dev_priv->fbc.lock);
 975
 976         if (dev_priv->fbc.enabled || dev_priv->fbc.fbc_work)
 977                 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe);
 978         else
 979                 fbc_bits = dev_priv->fbc.possible_framebuffer_bits;
 980
 981         dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits);
 982
 983         if (dev_priv->fbc.busy_bits)
 984                 intel_fbc_deactivate(dev_priv);
 985
 986         mutex_unlock(&dev_priv->fbc.lock);
 987 }
 988
 989 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 990                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 991 {
 992         if (!fbc_supported(dev_priv))
 993                 return;
 994
 995         if (origin == ORIGIN_GTT)
 996                 return;
 997
 998         mutex_lock(&dev_priv->fbc.lock);
 999
1000         dev_priv->fbc.busy_bits &= ~frontbuffer_bits;
1001
1002         if (!dev_priv->fbc.busy_bits && dev_priv->fbc.crtc) {
1003                 intel_fbc_deactivate(dev_priv);
1004                 __intel_fbc_update(dev_priv->fbc.crtc);
1005         }
1006
1007         mutex_unlock(&dev_priv->fbc.lock);
1008 }
1009
1010 /**
1011  * intel_fbc_init - Initialize FBC
1012  * @dev_priv: the i915 device
1013  *
1014  * This function might be called during PM init process.
1015  */
1016 void intel_fbc_init(struct drm_i915_private *dev_priv)
1017 {
1018         enum pipe pipe;
1019
1020         mutex_init(&dev_priv->fbc.lock);
1021         dev_priv->fbc.enabled = false;
1022
1023         if (!HAS_FBC(dev_priv)) {
1024                 dev_priv->fbc.no_fbc_reason = "unsupported by this chipset";
1025                 return;
1026         }
1027
1028         for_each_pipe(dev_priv, pipe) {
1029                 dev_priv->fbc.possible_framebuffer_bits |=
1030                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1031
1032                 if (fbc_on_pipe_a_only(dev_priv))
1033                         break;
1034         }
1035
1036         if (INTEL_INFO(dev_priv)->gen >= 7) {
1037                 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled;
1038                 dev_priv->fbc.enable_fbc = gen7_fbc_enable;
1039                 dev_priv->fbc.disable_fbc = ilk_fbc_disable;
1040         } else if (INTEL_INFO(dev_priv)->gen >= 5) {
1041                 dev_priv->fbc.fbc_enabled = ilk_fbc_enabled;
1042                 dev_priv->fbc.enable_fbc = ilk_fbc_enable;
1043                 dev_priv->fbc.disable_fbc = ilk_fbc_disable;
1044         } else if (IS_GM45(dev_priv)) {
1045                 dev_priv->fbc.fbc_enabled = g4x_fbc_enabled;
1046                 dev_priv->fbc.enable_fbc = g4x_fbc_enable;
1047                 dev_priv->fbc.disable_fbc = g4x_fbc_disable;
1048         } else {
1049                 dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled;
1050                 dev_priv->fbc.enable_fbc = i8xx_fbc_enable;
1051                 dev_priv->fbc.disable_fbc = i8xx_fbc_disable;
1052
1053                 /* This value was pulled out of someone's hat */
1054                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1055         }
1056
1057         /* We still don't have any sort of hardware state readout for FBC, so
1058          * disable it in case the BIOS enabled it to make sure software matches
1059          * the hardware state. */
1060         if (dev_priv->fbc.fbc_enabled(dev_priv))
1061                 dev_priv->fbc.disable_fbc(dev_priv);
1062 }