drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * __wait_for - magic wait macro
  45  *
  46  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  47  * important that we check the condition again after having timed out, since the
  48  * timeout could be due to preemption or similar and we've never had a chance to
  49  * check the condition before the timeout.
  50  */
  51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  52         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  58                 OP;                                                     \
  59                 /* Guarantee COND check prior to timeout */             \
  60                 barrier();                                              \
  61                 if (COND) {                                             \
  62                         ret__ = 0;                                      \
  63                         break;                                          \
  64                 }                                                       \
  65                 if (expired__) {                                        \
  66                         ret__ = -ETIMEDOUT;                             \
  67                         break;                                          \
  68                 }                                                       \
  69                 usleep_range(wait__, wait__ * 2);                       \
  70                 if (wait__ < (Wmax))                                    \
  71                         wait__ <<= 1;                                   \
  72         }                                                               \
  73         ret__;                                                          \
  74 })
  75
  76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  77                                                    (Wmax))
  78 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  79
  80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  83 #else
  84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  85 #endif
  86
  87 #define _wait_for_atomic(COND, US, ATOMIC) \
  88 ({ \
  89         int cpu, ret, timeout = (US) * 1000; \
  90         u64 base; \
  91         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 /* Guarantee COND check prior to timeout */ \
 102                 barrier(); \
 103                 if (COND) { \
 104                         ret = 0; \
 105                         break; \
 106                 } \
 107                 if (now - base >= timeout) { \
 108                         ret = -ETIMEDOUT; \
 109                         break; \
 110                 } \
 111                 cpu_relax(); \
 112                 if (!(ATOMIC)) { \
 113                         preempt_disable(); \
 114                         if (unlikely(cpu != smp_processor_id())) { \
 115                                 timeout -= now - base; \
 116                                 cpu = smp_processor_id(); \
 117                                 base = local_clock(); \
 118                         } \
 119                 } \
 120         } \
 121         ret; \
 122 })
 123
 124 #define wait_for_us(COND, US) \
 125 ({ \
 126         int ret__; \
 127         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 128         if ((US) > 10) \
 129                 ret__ = _wait_for((COND), (US), 10, 10); \
 130         else \
 131                 ret__ = _wait_for_atomic((COND), (US), 0); \
 132         ret__; \
 133 })
 134
 135 #define wait_for_atomic_us(COND, US) \
 136 ({ \
 137         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 138         BUILD_BUG_ON((US) > 50000); \
 139         _wait_for_atomic((COND), (US), 1); \
 140 })
 141
 142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 143
 144 #define KHz(x) (1000 * (x))
 145 #define MHz(x) KHz(1000 * (x))
 146
 147 #define KBps(x) (1000 * (x))
 148 #define MBps(x) KBps(1000 * (x))
 149 #define GBps(x) ((u64)1000 * MBps((x)))
 150
 151 /*
 152  * Display related stuff
 153  */
 154
 155 /* store information about an Ixxx DVO */
 156 /* The i830->i865 use multiple DVOs with multiple i2cs */
 157 /* the i915, i945 have a single sDVO i2c bus - which is different */
 158 #define MAX_OUTPUTS 6
 159 /* maximum connectors per crtcs in the mode set */
 160
 161 #define INTEL_I2C_BUS_DVO 1
 162 #define INTEL_I2C_BUS_SDVO 2
 163
 164 /* these are outputs from the chip - integrated only
 165    external chips are via DVO or SDVO output */
 166 enum intel_output_type {
 167         INTEL_OUTPUT_UNUSED = 0,
 168         INTEL_OUTPUT_ANALOG = 1,
 169         INTEL_OUTPUT_DVO = 2,
 170         INTEL_OUTPUT_SDVO = 3,
 171         INTEL_OUTPUT_LVDS = 4,
 172         INTEL_OUTPUT_TVOUT = 5,
 173         INTEL_OUTPUT_HDMI = 6,
 174         INTEL_OUTPUT_DP = 7,
 175         INTEL_OUTPUT_EDP = 8,
 176         INTEL_OUTPUT_DSI = 9,
 177         INTEL_OUTPUT_DDI = 10,
 178         INTEL_OUTPUT_DP_MST = 11,
 179 };
 180
 181 #define INTEL_DVO_CHIP_NONE 0
 182 #define INTEL_DVO_CHIP_LVDS 1
 183 #define INTEL_DVO_CHIP_TMDS 2
 184 #define INTEL_DVO_CHIP_TVOUT 4
 185
 186 #define INTEL_DSI_VIDEO_MODE    0
 187 #define INTEL_DSI_COMMAND_MODE  1
 188
 189 struct intel_framebuffer {
 190         struct drm_framebuffer base;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         unsigned long vma_flags;
 209         async_cookie_t cookie;
 210         int preferred_bpp;
 211 };
 212
 213 struct intel_encoder {
 214         struct drm_encoder base;
 215
 216         enum intel_output_type type;
 217         enum port port;
 218         unsigned int cloneable;
 219         bool (*hotplug)(struct intel_encoder *encoder,
 220                         struct intel_connector *connector);
 221         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 222                                                       struct intel_crtc_state *,
 223                                                       struct drm_connector_state *);
 224         bool (*compute_config)(struct intel_encoder *,
 225                                struct intel_crtc_state *,
 226                                struct drm_connector_state *);
 227         void (*pre_pll_enable)(struct intel_encoder *,
 228                                const struct intel_crtc_state *,
 229                                const struct drm_connector_state *);
 230         void (*pre_enable)(struct intel_encoder *,
 231                            const struct intel_crtc_state *,
 232                            const struct drm_connector_state *);
 233         void (*enable)(struct intel_encoder *,
 234                        const struct intel_crtc_state *,
 235                        const struct drm_connector_state *);
 236         void (*disable)(struct intel_encoder *,
 237                         const struct intel_crtc_state *,
 238                         const struct drm_connector_state *);
 239         void (*post_disable)(struct intel_encoder *,
 240                              const struct intel_crtc_state *,
 241                              const struct drm_connector_state *);
 242         void (*post_pll_disable)(struct intel_encoder *,
 243                                  const struct intel_crtc_state *,
 244                                  const struct drm_connector_state *);
 245         /* Read out the current hw state of this connector, returning true if
 246          * the encoder is active. If the encoder is enabled it also set the pipe
 247          * it is connected to in the pipe parameter. */
 248         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 249         /* Reconstructs the equivalent mode flags for the current hardware
 250          * state. This must be called _after_ display->get_pipe_config has
 251          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 252          * be set correctly before calling this function. */
 253         void (*get_config)(struct intel_encoder *,
 254                            struct intel_crtc_state *pipe_config);
 255         /* Returns a mask of power domains that need to be referenced as part
 256          * of the hardware state readout code. */
 257         u64 (*get_power_domains)(struct intel_encoder *encoder,
 258                                  struct intel_crtc_state *crtc_state);
 259         /*
 260          * Called during system suspend after all pending requests for the
 261          * encoder are flushed (for example for DP AUX transactions) and
 262          * device interrupts are disabled.
 263          */
 264         void (*suspend)(struct intel_encoder *);
 265         int crtc_mask;
 266         enum hpd_pin hpd_pin;
 267         enum intel_display_power_domain power_domain;
 268         /* for communication with audio component; protected by av_mutex */
 269         const struct drm_connector *audio_connector;
 270 };
 271
 272 struct intel_panel {
 273         struct drm_display_mode *fixed_mode;
 274         struct drm_display_mode *downclock_mode;
 275
 276         /* backlight */
 277         struct {
 278                 bool present;
 279                 u32 level;
 280                 u32 min;
 281                 u32 max;
 282                 bool enabled;
 283                 bool combination_mode;  /* gen 2/4 only */
 284                 bool active_low_pwm;
 285                 bool alternate_pwm_increment;   /* lpt+ */
 286
 287                 /* PWM chip */
 288                 bool util_pin_active_low;       /* bxt+ */
 289                 u8 controller;          /* bxt+ only */
 290                 struct pwm_device *pwm;
 291
 292                 struct backlight_device *device;
 293
 294                 /* Connector and platform specific backlight functions */
 295                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 296                 uint32_t (*get)(struct intel_connector *connector);
 297                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 298                 void (*disable)(const struct drm_connector_state *conn_state);
 299                 void (*enable)(const struct intel_crtc_state *crtc_state,
 300                                const struct drm_connector_state *conn_state);
 301                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 302                                       uint32_t hz);
 303                 void (*power)(struct intel_connector *, bool enable);
 304         } backlight;
 305 };
 306
 307 struct intel_digital_port;
 308
 309 /*
 310  * This structure serves as a translation layer between the generic HDCP code
 311  * and the bus-specific code. What that means is that HDCP over HDMI differs
 312  * from HDCP over DP, so to account for these differences, we need to
 313  * communicate with the receiver through this shim.
 314  *
 315  * For completeness, the 2 buses differ in the following ways:
 316  *      - DP AUX vs. DDC
 317  *              HDCP registers on the receiver are set via DP AUX for DP, and
 318  *              they are set via DDC for HDMI.
 319  *      - Receiver register offsets
 320  *              The offsets of the registers are different for DP vs. HDMI
 321  *      - Receiver register masks/offsets
 322  *              For instance, the ready bit for the KSV fifo is in a different
 323  *              place on DP vs HDMI
 324  *      - Receiver register names
 325  *              Seriously. In the DP spec, the 16-bit register containing
 326  *              downstream information is called BINFO, on HDMI it's called
 327  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 328  *              with a completely different definition.
 329  *      - KSV FIFO
 330  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 331  *              be read 3 keys at a time
 332  *      - Aksv output
 333  *              Since Aksv is hidden in hardware, there's different procedures
 334  *              to send it over DP AUX vs DDC
 335  */
 336 struct intel_hdcp_shim {
 337         /* Outputs the transmitter's An and Aksv values to the receiver. */
 338         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 339
 340         /* Reads the receiver's key selection vector */
 341         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 342
 343         /*
 344          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 345          * definitions are the same in the respective specs, but the names are
 346          * different. Call it BSTATUS since that's the name the HDMI spec
 347          * uses and it was there first.
 348          */
 349         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 350                             u8 *bstatus);
 351
 352         /* Determines whether a repeater is present downstream */
 353         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 354                                 bool *repeater_present);
 355
 356         /* Reads the receiver's Ri' value */
 357         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 358
 359         /* Determines if the receiver's KSV FIFO is ready for consumption */
 360         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 361                               bool *ksv_ready);
 362
 363         /* Reads the ksv fifo for num_downstream devices */
 364         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 365                              int num_downstream, u8 *ksv_fifo);
 366
 367         /* Reads a 32-bit part of V' from the receiver */
 368         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 369                                  int i, u32 *part);
 370
 371         /* Enables HDCP signalling on the port */
 372         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 373                                  bool enable);
 374
 375         /* Ensures the link is still protected */
 376         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 377
 378         /* Detects panel's hdcp capability. This is optional for HDMI. */
 379         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 380                             bool *hdcp_capable);
 381 };
 382
 383 struct intel_connector {
 384         struct drm_connector base;
 385         /*
 386          * The fixed encoder this connector is connected to.
 387          */
 388         struct intel_encoder *encoder;
 389
 390         /* ACPI device id for ACPI and driver cooperation */
 391         u32 acpi_device_id;
 392
 393         /* Reads out the current hw, returning true if the connector is enabled
 394          * and active (i.e. dpms ON state). */
 395         bool (*get_hw_state)(struct intel_connector *);
 396
 397         /* Panel info for eDP and LVDS */
 398         struct intel_panel panel;
 399
 400         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 401         struct edid *edid;
 402         struct edid *detect_edid;
 403
 404         /* since POLL and HPD connectors may use the same HPD line keep the native
 405            state of connector->polled in case hotplug storm detection changes it */
 406         u8 polled;
 407
 408         void *port; /* store this opaque as its illegal to dereference it */
 409
 410         struct intel_dp *mst_port;
 411
 412         /* Work struct to schedule a uevent on link train failure */
 413         struct work_struct modeset_retry_work;
 414
 415         const struct intel_hdcp_shim *hdcp_shim;
 416         struct mutex hdcp_mutex;
 417         uint64_t hdcp_value; /* protected by hdcp_mutex */
 418         struct delayed_work hdcp_check_work;
 419         struct work_struct hdcp_prop_work;
 420 };
 421
 422 struct intel_digital_connector_state {
 423         struct drm_connector_state base;
 424
 425         enum hdmi_force_audio force_audio;
 426         int broadcast_rgb;
 427 };
 428
 429 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 430
 431 struct dpll {
 432         /* given values */
 433         int n;
 434         int m1, m2;
 435         int p1, p2;
 436         /* derived values */
 437         int     dot;
 438         int     vco;
 439         int     m;
 440         int     p;
 441 };
 442
 443 struct intel_atomic_state {
 444         struct drm_atomic_state base;
 445
 446         struct {
 447                 /*
 448                  * Logical state of cdclk (used for all scaling, watermark,
 449                  * etc. calculations and checks). This is computed as if all
 450                  * enabled crtcs were active.
 451                  */
 452                 struct intel_cdclk_state logical;
 453
 454                 /*
 455                  * Actual state of cdclk, can be different from the logical
 456                  * state only when all crtc's are DPMS off.
 457                  */
 458                 struct intel_cdclk_state actual;
 459         } cdclk;
 460
 461         bool dpll_set, modeset;
 462
 463         /*
 464          * Does this transaction change the pipes that are active?  This mask
 465          * tracks which CRTC's have changed their active state at the end of
 466          * the transaction (not counting the temporary disable during modesets).
 467          * This mask should only be non-zero when intel_state->modeset is true,
 468          * but the converse is not necessarily true; simply changing a mode may
 469          * not flip the final active status of any CRTC's
 470          */
 471         unsigned int active_pipe_changes;
 472
 473         unsigned int active_crtcs;
 474         /* minimum acceptable cdclk for each pipe */
 475         int min_cdclk[I915_MAX_PIPES];
 476         /* minimum acceptable voltage level for each pipe */
 477         u8 min_voltage_level[I915_MAX_PIPES];
 478
 479         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 480
 481         /*
 482          * Current watermarks can't be trusted during hardware readout, so
 483          * don't bother calculating intermediate watermarks.
 484          */
 485         bool skip_intermediate_wm;
 486
 487         bool rps_interactive;
 488
 489         /* Gen9+ only */
 490         struct skl_ddb_values wm_results;
 491
 492         struct i915_sw_fence commit_ready;
 493
 494         struct llist_node freed;
 495 };
 496
 497 struct intel_plane_state {
 498         struct drm_plane_state base;
 499         struct i915_vma *vma;
 500         unsigned long flags;
 501 #define PLANE_HAS_FENCE BIT(0)
 502
 503         struct {
 504                 u32 offset;
 505                 int x, y;
 506         } main;
 507         struct {
 508                 u32 offset;
 509                 int x, y;
 510         } aux;
 511
 512         /* plane control register */
 513         u32 ctl;
 514
 515         /* plane color control register */
 516         u32 color_ctl;
 517
 518         /*
 519          * scaler_id
 520          *    = -1 : not using a scaler
 521          *    >=  0 : using a scalers
 522          *
 523          * plane requiring a scaler:
 524          *   - During check_plane, its bit is set in
 525          *     crtc_state->scaler_state.scaler_users by calling helper function
 526          *     update_scaler_plane.
 527          *   - scaler_id indicates the scaler it got assigned.
 528          *
 529          * plane doesn't require a scaler:
 530          *   - this can happen when scaling is no more required or plane simply
 531          *     got disabled.
 532          *   - During check_plane, corresponding bit is reset in
 533          *     crtc_state->scaler_state.scaler_users by calling helper function
 534          *     update_scaler_plane.
 535          */
 536         int scaler_id;
 537
 538         struct drm_intel_sprite_colorkey ckey;
 539 };
 540
 541 struct intel_initial_plane_config {
 542         struct intel_framebuffer *fb;
 543         unsigned int tiling;
 544         int size;
 545         u32 base;
 546 };
 547
 548 #define SKL_MIN_SRC_W 8
 549 #define SKL_MAX_SRC_W 4096
 550 #define SKL_MIN_SRC_H 8
 551 #define SKL_MAX_SRC_H 4096
 552 #define SKL_MIN_DST_W 8
 553 #define SKL_MAX_DST_W 4096
 554 #define SKL_MIN_DST_H 8
 555 #define SKL_MAX_DST_H 4096
 556 #define ICL_MAX_SRC_W 5120
 557 #define ICL_MAX_SRC_H 4096
 558 #define ICL_MAX_DST_W 5120
 559 #define ICL_MAX_DST_H 4096
 560 #define SKL_MIN_YUV_420_SRC_W 16
 561 #define SKL_MIN_YUV_420_SRC_H 16
 562
 563 struct intel_scaler {
 564         int in_use;
 565         uint32_t mode;
 566 };
 567
 568 struct intel_crtc_scaler_state {
 569 #define SKL_NUM_SCALERS 2
 570         struct intel_scaler scalers[SKL_NUM_SCALERS];
 571
 572         /*
 573          * scaler_users: keeps track of users requesting scalers on this crtc.
 574          *
 575          *     If a bit is set, a user is using a scaler.
 576          *     Here user can be a plane or crtc as defined below:
 577          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 578          *       bit 31    - crtc
 579          *
 580          * Instead of creating a new index to cover planes and crtc, using
 581          * existing drm_plane_index for planes which is well less than 31
 582          * planes and bit 31 for crtc. This should be fine to cover all
 583          * our platforms.
 584          *
 585          * intel_atomic_setup_scalers will setup available scalers to users
 586          * requesting scalers. It will gracefully fail if request exceeds
 587          * avilability.
 588          */
 589 #define SKL_CRTC_INDEX 31
 590         unsigned scaler_users;
 591
 592         /* scaler used by crtc for panel fitting purpose */
 593         int scaler_id;
 594 };
 595
 596 /* drm_mode->private_flags */
 597 #define I915_MODE_FLAG_INHERITED 1
 598 /* Flag to get scanline using frame time stamps */
 599 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 600
 601 struct intel_pipe_wm {
 602         struct intel_wm_level wm[5];
 603         uint32_t linetime;
 604         bool fbc_wm_enabled;
 605         bool pipe_enabled;
 606         bool sprites_enabled;
 607         bool sprites_scaled;
 608 };
 609
 610 struct skl_plane_wm {
 611         struct skl_wm_level wm[8];
 612         struct skl_wm_level uv_wm[8];
 613         struct skl_wm_level trans_wm;
 614         bool is_planar;
 615 };
 616
 617 struct skl_pipe_wm {
 618         struct skl_plane_wm planes[I915_MAX_PLANES];
 619         uint32_t linetime;
 620 };
 621
 622 enum vlv_wm_level {
 623         VLV_WM_LEVEL_PM2,
 624         VLV_WM_LEVEL_PM5,
 625         VLV_WM_LEVEL_DDR_DVFS,
 626         NUM_VLV_WM_LEVELS,
 627 };
 628
 629 struct vlv_wm_state {
 630         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 631         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 632         uint8_t num_levels;
 633         bool cxsr;
 634 };
 635
 636 struct vlv_fifo_state {
 637         u16 plane[I915_MAX_PLANES];
 638 };
 639
 640 enum g4x_wm_level {
 641         G4X_WM_LEVEL_NORMAL,
 642         G4X_WM_LEVEL_SR,
 643         G4X_WM_LEVEL_HPLL,
 644         NUM_G4X_WM_LEVELS,
 645 };
 646
 647 struct g4x_wm_state {
 648         struct g4x_pipe_wm wm;
 649         struct g4x_sr_wm sr;
 650         struct g4x_sr_wm hpll;
 651         bool cxsr;
 652         bool hpll_en;
 653         bool fbc_en;
 654 };
 655
 656 struct intel_crtc_wm_state {
 657         union {
 658                 struct {
 659                         /*
 660                          * Intermediate watermarks; these can be
 661                          * programmed immediately since they satisfy
 662                          * both the current configuration we're
 663                          * switching away from and the new
 664                          * configuration we're switching to.
 665                          */
 666                         struct intel_pipe_wm intermediate;
 667
 668                         /*
 669                          * Optimal watermarks, programmed post-vblank
 670                          * when this state is committed.
 671                          */
 672                         struct intel_pipe_wm optimal;
 673                 } ilk;
 674
 675                 struct {
 676                         /* gen9+ only needs 1-step wm programming */
 677                         struct skl_pipe_wm optimal;
 678                         struct skl_ddb_entry ddb;
 679                 } skl;
 680
 681                 struct {
 682                         /* "raw" watermarks (not inverted) */
 683                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 684                         /* intermediate watermarks (inverted) */
 685                         struct vlv_wm_state intermediate;
 686                         /* optimal watermarks (inverted) */
 687                         struct vlv_wm_state optimal;
 688                         /* display FIFO split */
 689                         struct vlv_fifo_state fifo_state;
 690                 } vlv;
 691
 692                 struct {
 693                         /* "raw" watermarks */
 694                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 695                         /* intermediate watermarks */
 696                         struct g4x_wm_state intermediate;
 697                         /* optimal watermarks */
 698                         struct g4x_wm_state optimal;
 699                 } g4x;
 700         };
 701
 702         /*
 703          * Platforms with two-step watermark programming will need to
 704          * update watermark programming post-vblank to switch from the
 705          * safe intermediate watermarks to the optimal final
 706          * watermarks.
 707          */
 708         bool need_postvbl_update;
 709 };
 710
 711 struct intel_crtc_state {
 712         struct drm_crtc_state base;
 713
 714         /**
 715          * quirks - bitfield with hw state readout quirks
 716          *
 717          * For various reasons the hw state readout code might not be able to
 718          * completely faithfully read out the current state. These cases are
 719          * tracked with quirk flags so that fastboot and state checker can act
 720          * accordingly.
 721          */
 722 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 723         unsigned long quirks;
 724
 725         unsigned fb_bits; /* framebuffers to flip */
 726         bool update_pipe; /* can a fast modeset be performed? */
 727         bool disable_cxsr;
 728         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 729         bool fb_changed; /* fb on any of the planes is changed */
 730         bool fifo_changed; /* FIFO split is changed */
 731
 732         /* Pipe source size (ie. panel fitter input size)
 733          * All planes will be positioned inside this space,
 734          * and get clipped at the edges. */
 735         int pipe_src_w, pipe_src_h;
 736
 737         /*
 738          * Pipe pixel rate, adjusted for
 739          * panel fitter/pipe scaler downscaling.
 740          */
 741         unsigned int pixel_rate;
 742
 743         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 744          * between pch encoders and cpu encoders. */
 745         bool has_pch_encoder;
 746
 747         /* Are we sending infoframes on the attached port */
 748         bool has_infoframe;
 749
 750         /* CPU Transcoder for the pipe. Currently this can only differ from the
 751          * pipe on Haswell and later (where we have a special eDP transcoder)
 752          * and Broxton (where we have special DSI transcoders). */
 753         enum transcoder cpu_transcoder;
 754
 755         /*
 756          * Use reduced/limited/broadcast rbg range, compressing from the full
 757          * range fed into the crtcs.
 758          */
 759         bool limited_color_range;
 760
 761         /* Bitmask of encoder types (enum intel_output_type)
 762          * driven by the pipe.
 763          */
 764         unsigned int output_types;
 765
 766         /* Whether we should send NULL infoframes. Required for audio. */
 767         bool has_hdmi_sink;
 768
 769         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 770          * has_dp_encoder is set. */
 771         bool has_audio;
 772
 773         /*
 774          * Enable dithering, used when the selected pipe bpp doesn't match the
 775          * plane bpp.
 776          */
 777         bool dither;
 778
 779         /*
 780          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 781          * compliance video pattern tests.
 782          * Disable dither only if it is a compliance test request for
 783          * 18bpp.
 784          */
 785         bool dither_force_disable;
 786
 787         /* Controls for the clock computation, to override various stages. */
 788         bool clock_set;
 789
 790         /* SDVO TV has a bunch of special case. To make multifunction encoders
 791          * work correctly, we need to track this at runtime.*/
 792         bool sdvo_tv_clock;
 793
 794         /*
 795          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 796          * required. This is set in the 2nd loop of calling encoder's
 797          * ->compute_config if the first pick doesn't work out.
 798          */
 799         bool bw_constrained;
 800
 801         /* Settings for the intel dpll used on pretty much everything but
 802          * haswell. */
 803         struct dpll dpll;
 804
 805         /* Selected dpll when shared or NULL. */
 806         struct intel_shared_dpll *shared_dpll;
 807
 808         /* Actual register state of the dpll, for shared dpll cross-checking. */
 809         struct intel_dpll_hw_state dpll_hw_state;
 810
 811         /* DSI PLL registers */
 812         struct {
 813                 u32 ctrl, div;
 814         } dsi_pll;
 815
 816         int pipe_bpp;
 817         struct intel_link_m_n dp_m_n;
 818
 819         /* m2_n2 for eDP downclock */
 820         struct intel_link_m_n dp_m2_n2;
 821         bool has_drrs;
 822
 823         bool has_psr;
 824         bool has_psr2;
 825
 826         /*
 827          * Frequence the dpll for the port should run at. Differs from the
 828          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 829          * already multiplied by pixel_multiplier.
 830          */
 831         int port_clock;
 832
 833         /* Used by SDVO (and if we ever fix it, HDMI). */
 834         unsigned pixel_multiplier;
 835
 836         uint8_t lane_count;
 837
 838         /*
 839          * Used by platforms having DP/HDMI PHY with programmable lane
 840          * latency optimization.
 841          */
 842         uint8_t lane_lat_optim_mask;
 843
 844         /* minimum acceptable voltage level */
 845         u8 min_voltage_level;
 846
 847         /* Panel fitter controls for gen2-gen4 + VLV */
 848         struct {
 849                 u32 control;
 850                 u32 pgm_ratios;
 851                 u32 lvds_border_bits;
 852         } gmch_pfit;
 853
 854         /* Panel fitter placement and size for Ironlake+ */
 855         struct {
 856                 u32 pos;
 857                 u32 size;
 858                 bool enabled;
 859                 bool force_thru;
 860         } pch_pfit;
 861
 862         /* FDI configuration, only valid if has_pch_encoder is set. */
 863         int fdi_lanes;
 864         struct intel_link_m_n fdi_m_n;
 865
 866         bool ips_enabled;
 867         bool ips_force_disable;
 868
 869         bool enable_fbc;
 870
 871         bool double_wide;
 872
 873         int pbn;
 874
 875         struct intel_crtc_scaler_state scaler_state;
 876
 877         /* w/a for waiting 2 vblanks during crtc enable */
 878         enum pipe hsw_workaround_pipe;
 879
 880         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 881         bool disable_lp_wm;
 882
 883         struct intel_crtc_wm_state wm;
 884
 885         /* Gamma mode programmed on the pipe */
 886         uint32_t gamma_mode;
 887
 888         /* bitmask of visible planes (enum plane_id) */
 889         u8 active_planes;
 890         u8 nv12_planes;
 891
 892         /* HDMI scrambling status */
 893         bool hdmi_scrambling;
 894
 895         /* HDMI High TMDS char rate ratio */
 896         bool hdmi_high_tmds_clock_ratio;
 897
 898         /* output format is YCBCR 4:2:0 */
 899         bool ycbcr420;
 900 };
 901
 902 struct intel_crtc {
 903         struct drm_crtc base;
 904         enum pipe pipe;
 905         /*
 906          * Whether the crtc and the connected output pipeline is active. Implies
 907          * that crtc->enabled is set, i.e. the current mode configuration has
 908          * some outputs connected to this crtc.
 909          */
 910         bool active;
 911         u8 plane_ids_mask;
 912         unsigned long long enabled_power_domains;
 913         struct intel_overlay *overlay;
 914
 915         struct intel_crtc_state *config;
 916
 917         /* global reset count when the last flip was submitted */
 918         unsigned int reset_count;
 919
 920         /* Access to these should be protected by dev_priv->irq_lock. */
 921         bool cpu_fifo_underrun_disabled;
 922         bool pch_fifo_underrun_disabled;
 923
 924         /* per-pipe watermark state */
 925         struct {
 926                 /* watermarks currently being used  */
 927                 union {
 928                         struct intel_pipe_wm ilk;
 929                         struct vlv_wm_state vlv;
 930                         struct g4x_wm_state g4x;
 931                 } active;
 932         } wm;
 933
 934         int scanline_offset;
 935
 936         struct {
 937                 unsigned start_vbl_count;
 938                 ktime_t start_vbl_time;
 939                 int min_vbl, max_vbl;
 940                 int scanline_start;
 941         } debug;
 942
 943         /* scalers available on this crtc */
 944         int num_scalers;
 945 };
 946
 947 struct intel_plane {
 948         struct drm_plane base;
 949         enum i9xx_plane_id i9xx_plane;
 950         enum plane_id id;
 951         enum pipe pipe;
 952         bool can_scale;
 953         bool has_fbc;
 954         bool has_ccs;
 955         int max_downscale;
 956         uint32_t frontbuffer_bit;
 957
 958         struct {
 959                 u32 base, cntl, size;
 960         } cursor;
 961
 962         /*
 963          * NOTE: Do not place new plane state fields here (e.g., when adding
 964          * new plane properties).  New runtime state should now be placed in
 965          * the intel_plane_state structure and accessed via plane_state.
 966          */
 967
 968         void (*update_plane)(struct intel_plane *plane,
 969                              const struct intel_crtc_state *crtc_state,
 970                              const struct intel_plane_state *plane_state);
 971         void (*disable_plane)(struct intel_plane *plane,
 972                               struct intel_crtc *crtc);
 973         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
 974         int (*check_plane)(struct intel_plane *plane,
 975                            struct intel_crtc_state *crtc_state,
 976                            struct intel_plane_state *state);
 977 };
 978
 979 struct intel_watermark_params {
 980         u16 fifo_size;
 981         u16 max_wm;
 982         u8 default_wm;
 983         u8 guard_size;
 984         u8 cacheline_size;
 985 };
 986
 987 struct cxsr_latency {
 988         bool is_desktop : 1;
 989         bool is_ddr3 : 1;
 990         u16 fsb_freq;
 991         u16 mem_freq;
 992         u16 display_sr;
 993         u16 display_hpll_disable;
 994         u16 cursor_sr;
 995         u16 cursor_hpll_disable;
 996 };
 997
 998 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 999 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1000 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1001 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1002 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1003 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1004 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1005 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1006 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1007
1008 struct intel_hdmi {
1009         i915_reg_t hdmi_reg;
1010         int ddc_bus;
1011         struct {
1012                 enum drm_dp_dual_mode_type type;
1013                 int max_tmds_clock;
1014         } dp_dual_mode;
1015         bool has_hdmi_sink;
1016         bool has_audio;
1017         bool rgb_quant_range_selectable;
1018         struct intel_connector *attached_connector;
1019 };
1020
1021 struct intel_dp_mst_encoder;
1022 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1023
1024 /*
1025  * enum link_m_n_set:
1026  *      When platform provides two set of M_N registers for dp, we can
1027  *      program them and switch between them incase of DRRS.
1028  *      But When only one such register is provided, we have to program the
1029  *      required divider value on that registers itself based on the DRRS state.
1030  *
1031  * M1_N1        : Program dp_m_n on M1_N1 registers
1032  *                        dp_m2_n2 on M2_N2 registers (If supported)
1033  *
1034  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1035  *                        M2_N2 registers are not supported
1036  */
1037
1038 enum link_m_n_set {
1039         /* Sets the m1_n1 and m2_n2 */
1040         M1_N1 = 0,
1041         M2_N2
1042 };
1043
1044 struct intel_dp_compliance_data {
1045         unsigned long edid;
1046         uint8_t video_pattern;
1047         uint16_t hdisplay, vdisplay;
1048         uint8_t bpc;
1049 };
1050
1051 struct intel_dp_compliance {
1052         unsigned long test_type;
1053         struct intel_dp_compliance_data test_data;
1054         bool test_active;
1055         int test_link_rate;
1056         u8 test_lane_count;
1057 };
1058
1059 struct intel_dp {
1060         i915_reg_t output_reg;
1061         uint32_t DP;
1062         int link_rate;
1063         uint8_t lane_count;
1064         uint8_t sink_count;
1065         bool link_mst;
1066         bool link_trained;
1067         bool has_audio;
1068         bool detect_done;
1069         bool reset_link_params;
1070         enum aux_ch aux_ch;
1071         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1072         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1073         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1074         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1075         /* source rates */
1076         int num_source_rates;
1077         const int *source_rates;
1078         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1079         int num_sink_rates;
1080         int sink_rates[DP_MAX_SUPPORTED_RATES];
1081         bool use_rate_select;
1082         /* intersection of source and sink rates */
1083         int num_common_rates;
1084         int common_rates[DP_MAX_SUPPORTED_RATES];
1085         /* Max lane count for the current link */
1086         int max_link_lane_count;
1087         /* Max rate for the current link */
1088         int max_link_rate;
1089         /* sink or branch descriptor */
1090         struct drm_dp_desc desc;
1091         struct drm_dp_aux aux;
1092         enum intel_display_power_domain aux_power_domain;
1093         uint8_t train_set[4];
1094         int panel_power_up_delay;
1095         int panel_power_down_delay;
1096         int panel_power_cycle_delay;
1097         int backlight_on_delay;
1098         int backlight_off_delay;
1099         struct delayed_work panel_vdd_work;
1100         bool want_panel_vdd;
1101         unsigned long last_power_on;
1102         unsigned long last_backlight_off;
1103         ktime_t panel_power_off_time;
1104
1105         struct notifier_block edp_notifier;
1106
1107         /*
1108          * Pipe whose power sequencer is currently locked into
1109          * this port. Only relevant on VLV/CHV.
1110          */
1111         enum pipe pps_pipe;
1112         /*
1113          * Pipe currently driving the port. Used for preventing
1114          * the use of the PPS for any pipe currentrly driving
1115          * external DP as that will mess things up on VLV.
1116          */
1117         enum pipe active_pipe;
1118         /*
1119          * Set if the sequencer may be reset due to a power transition,
1120          * requiring a reinitialization. Only relevant on BXT.
1121          */
1122         bool pps_reset;
1123         struct edp_power_seq pps_delays;
1124
1125         bool can_mst; /* this port supports mst */
1126         bool is_mst;
1127         int active_mst_links;
1128         /* connector directly attached - won't be use for modeset in mst world */
1129         struct intel_connector *attached_connector;
1130
1131         /* mst connector list */
1132         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1133         struct drm_dp_mst_topology_mgr mst_mgr;
1134
1135         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1136         /*
1137          * This function returns the value we have to program the AUX_CTL
1138          * register with to kick off an AUX transaction.
1139          */
1140         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1141                                      int send_bytes,
1142                                      uint32_t aux_clock_divider);
1143
1144         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1145         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1146
1147         /* This is called before a link training is starterd */
1148         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1149
1150         /* Displayport compliance testing */
1151         struct intel_dp_compliance compliance;
1152 };
1153
1154 struct intel_lspcon {
1155         bool active;
1156         enum drm_lspcon_mode mode;
1157 };
1158
1159 struct intel_digital_port {
1160         struct intel_encoder base;
1161         u32 saved_port_bits;
1162         struct intel_dp dp;
1163         struct intel_hdmi hdmi;
1164         struct intel_lspcon lspcon;
1165         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1166         bool release_cl2_override;
1167         uint8_t max_lanes;
1168         enum intel_display_power_domain ddi_io_power_domain;
1169
1170         void (*write_infoframe)(struct drm_encoder *encoder,
1171                                 const struct intel_crtc_state *crtc_state,
1172                                 unsigned int type,
1173                                 const void *frame, ssize_t len);
1174         void (*set_infoframes)(struct drm_encoder *encoder,
1175                                bool enable,
1176                                const struct intel_crtc_state *crtc_state,
1177                                const struct drm_connector_state *conn_state);
1178         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1179                                   const struct intel_crtc_state *pipe_config);
1180 };
1181
1182 struct intel_dp_mst_encoder {
1183         struct intel_encoder base;
1184         enum pipe pipe;
1185         struct intel_digital_port *primary;
1186         struct intel_connector *connector;
1187 };
1188
1189 static inline enum dpio_channel
1190 vlv_dport_to_channel(struct intel_digital_port *dport)
1191 {
1192         switch (dport->base.port) {
1193         case PORT_B:
1194         case PORT_D:
1195                 return DPIO_CH0;
1196         case PORT_C:
1197                 return DPIO_CH1;
1198         default:
1199                 BUG();
1200         }
1201 }
1202
1203 static inline enum dpio_phy
1204 vlv_dport_to_phy(struct intel_digital_port *dport)
1205 {
1206         switch (dport->base.port) {
1207         case PORT_B:
1208         case PORT_C:
1209                 return DPIO_PHY0;
1210         case PORT_D:
1211                 return DPIO_PHY1;
1212         default:
1213                 BUG();
1214         }
1215 }
1216
1217 static inline enum dpio_channel
1218 vlv_pipe_to_channel(enum pipe pipe)
1219 {
1220         switch (pipe) {
1221         case PIPE_A:
1222         case PIPE_C:
1223                 return DPIO_CH0;
1224         case PIPE_B:
1225                 return DPIO_CH1;
1226         default:
1227                 BUG();
1228         }
1229 }
1230
1231 static inline struct intel_crtc *
1232 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1233 {
1234         return dev_priv->pipe_to_crtc_mapping[pipe];
1235 }
1236
1237 static inline struct intel_crtc *
1238 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1239 {
1240         return dev_priv->plane_to_crtc_mapping[plane];
1241 }
1242
1243 struct intel_load_detect_pipe {
1244         struct drm_atomic_state *restore_state;
1245 };
1246
1247 static inline struct intel_encoder *
1248 intel_attached_encoder(struct drm_connector *connector)
1249 {
1250         return to_intel_connector(connector)->encoder;
1251 }
1252
1253 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1254 {
1255         switch (encoder->type) {
1256         case INTEL_OUTPUT_DDI:
1257         case INTEL_OUTPUT_DP:
1258         case INTEL_OUTPUT_EDP:
1259         case INTEL_OUTPUT_HDMI:
1260                 return true;
1261         default:
1262                 return false;
1263         }
1264 }
1265
1266 static inline struct intel_digital_port *
1267 enc_to_dig_port(struct drm_encoder *encoder)
1268 {
1269         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1270
1271         if (intel_encoder_is_dig_port(intel_encoder))
1272                 return container_of(encoder, struct intel_digital_port,
1273                                     base.base);
1274         else
1275                 return NULL;
1276 }
1277
1278 static inline struct intel_dp_mst_encoder *
1279 enc_to_mst(struct drm_encoder *encoder)
1280 {
1281         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1282 }
1283
1284 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1285 {
1286         return &enc_to_dig_port(encoder)->dp;
1287 }
1288
1289 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1290 {
1291         switch (encoder->type) {
1292         case INTEL_OUTPUT_DP:
1293         case INTEL_OUTPUT_EDP:
1294                 return true;
1295         case INTEL_OUTPUT_DDI:
1296                 /* Skip pure HDMI/DVI DDI encoders */
1297                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1298         default:
1299                 return false;
1300         }
1301 }
1302
1303 static inline struct intel_digital_port *
1304 dp_to_dig_port(struct intel_dp *intel_dp)
1305 {
1306         return container_of(intel_dp, struct intel_digital_port, dp);
1307 }
1308
1309 static inline struct intel_lspcon *
1310 dp_to_lspcon(struct intel_dp *intel_dp)
1311 {
1312         return &dp_to_dig_port(intel_dp)->lspcon;
1313 }
1314
1315 static inline struct intel_digital_port *
1316 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1317 {
1318         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1319 }
1320
1321 static inline struct intel_plane_state *
1322 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1323                                  struct intel_plane *plane)
1324 {
1325         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1326                                                                    &plane->base));
1327 }
1328
1329 static inline struct intel_crtc_state *
1330 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1331                                 struct intel_crtc *crtc)
1332 {
1333         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1334                                                                  &crtc->base));
1335 }
1336
1337 static inline struct intel_crtc_state *
1338 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1339                                 struct intel_crtc *crtc)
1340 {
1341         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1342                                                                  &crtc->base));
1343 }
1344
1345 /* intel_fifo_underrun.c */
1346 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1347                                            enum pipe pipe, bool enable);
1348 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1349                                            enum pipe pch_transcoder,
1350                                            bool enable);
1351 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1352                                          enum pipe pipe);
1353 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1354                                          enum pipe pch_transcoder);
1355 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1356 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1357
1358 /* i915_irq.c */
1359 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1360 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1361 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1362 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1363 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1364 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1365 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1366 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1367
1368 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1369                                             u32 mask)
1370 {
1371         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1372 }
1373
1374 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1375 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1376 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1377 {
1378         /*
1379          * We only use drm_irq_uninstall() at unload and VT switch, so
1380          * this is the only thing we need to check.
1381          */
1382         return dev_priv->runtime_pm.irqs_enabled;
1383 }
1384
1385 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1386 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1387                                      u8 pipe_mask);
1388 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1389                                      u8 pipe_mask);
1390 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1391 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1392 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1393
1394 /* intel_crt.c */
1395 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1396                             i915_reg_t adpa_reg, enum pipe *pipe);
1397 void intel_crt_init(struct drm_i915_private *dev_priv);
1398 void intel_crt_reset(struct drm_encoder *encoder);
1399
1400 /* intel_ddi.c */
1401 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1402                                 const struct intel_crtc_state *old_crtc_state,
1403                                 const struct drm_connector_state *old_conn_state);
1404 void hsw_fdi_link_train(struct intel_crtc *crtc,
1405                         const struct intel_crtc_state *crtc_state);
1406 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1407 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1408 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1409 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1410 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1411 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1412 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1413 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1414 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1415 void intel_ddi_get_config(struct intel_encoder *encoder,
1416                           struct intel_crtc_state *pipe_config);
1417
1418 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1419                                     bool state);
1420 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1421                                          struct intel_crtc_state *crtc_state);
1422 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1423 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1424 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1425 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1426                                  u8 voltage_swing);
1427 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1428                                      bool enable);
1429 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1430                            struct intel_crtc_state *crtc_state,
1431                            struct drm_atomic_state *old_state);
1432 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1433                              struct intel_crtc_state *crtc_state,
1434                              struct drm_atomic_state *old_state);
1435
1436 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1437                                    int plane, unsigned int height);
1438
1439 /* intel_audio.c */
1440 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1441 void intel_audio_codec_enable(struct intel_encoder *encoder,
1442                               const struct intel_crtc_state *crtc_state,
1443                               const struct drm_connector_state *conn_state);
1444 void intel_audio_codec_disable(struct intel_encoder *encoder,
1445                                const struct intel_crtc_state *old_crtc_state,
1446                                const struct drm_connector_state *old_conn_state);
1447 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1448 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1449 void intel_audio_init(struct drm_i915_private *dev_priv);
1450 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1451
1452 /* intel_cdclk.c */
1453 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1454 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1455 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1456 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1457 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1458 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1459 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1460 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1461 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1462 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1463 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1464 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1465 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1466 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1467                                const struct intel_cdclk_state *b);
1468 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1469                          const struct intel_cdclk_state *b);
1470 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1471                      const struct intel_cdclk_state *cdclk_state);
1472 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1473                             const char *context);
1474
1475 /* intel_display.c */
1476 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1477 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1478 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1479 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1480 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1481 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1482                       const char *name, u32 reg, int ref_freq);
1483 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1484                            const char *name, u32 reg);
1485 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1486 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1487 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1488 unsigned int intel_fb_xy_to_linear(int x, int y,
1489                                    const struct intel_plane_state *state,
1490                                    int plane);
1491 void intel_add_fb_offsets(int *x, int *y,
1492                           const struct intel_plane_state *state, int plane);
1493 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1494 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1495 void intel_mark_busy(struct drm_i915_private *dev_priv);
1496 void intel_mark_idle(struct drm_i915_private *dev_priv);
1497 int intel_display_suspend(struct drm_device *dev);
1498 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1499 void intel_encoder_destroy(struct drm_encoder *encoder);
1500 int intel_connector_init(struct intel_connector *);
1501 struct intel_connector *intel_connector_alloc(void);
1502 void intel_connector_free(struct intel_connector *connector);
1503 bool intel_connector_get_hw_state(struct intel_connector *connector);
1504 void intel_connector_attach_encoder(struct intel_connector *connector,
1505                                     struct intel_encoder *encoder);
1506 struct drm_display_mode *
1507 intel_encoder_current_mode(struct intel_encoder *encoder);
1508 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1509 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1510                               enum port port);
1511
1512 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1513 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1514                                       struct drm_file *file_priv);
1515 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1516                                              enum pipe pipe);
1517 static inline bool
1518 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1519                     enum intel_output_type type)
1520 {
1521         return crtc_state->output_types & (1 << type);
1522 }
1523 static inline bool
1524 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1525 {
1526         return crtc_state->output_types &
1527                 ((1 << INTEL_OUTPUT_DP) |
1528                  (1 << INTEL_OUTPUT_DP_MST) |
1529                  (1 << INTEL_OUTPUT_EDP));
1530 }
1531 static inline void
1532 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1533 {
1534         drm_wait_one_vblank(&dev_priv->drm, pipe);
1535 }
1536 static inline void
1537 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1538 {
1539         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1540
1541         if (crtc->active)
1542                 intel_wait_for_vblank(dev_priv, pipe);
1543 }
1544
1545 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1546
1547 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1548 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1549                          struct intel_digital_port *dport,
1550                          unsigned int expected_mask);
1551 int intel_get_load_detect_pipe(struct drm_connector *connector,
1552                                const struct drm_display_mode *mode,
1553                                struct intel_load_detect_pipe *old,
1554                                struct drm_modeset_acquire_ctx *ctx);
1555 void intel_release_load_detect_pipe(struct drm_connector *connector,
1556                                     struct intel_load_detect_pipe *old,
1557                                     struct drm_modeset_acquire_ctx *ctx);
1558 struct i915_vma *
1559 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1560                            unsigned int rotation,
1561                            bool uses_fence,
1562                            unsigned long *out_flags);
1563 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1564 struct drm_framebuffer *
1565 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1566                          struct drm_mode_fb_cmd2 *mode_cmd);
1567 int intel_prepare_plane_fb(struct drm_plane *plane,
1568                            struct drm_plane_state *new_state);
1569 void intel_cleanup_plane_fb(struct drm_plane *plane,
1570                             struct drm_plane_state *old_state);
1571 int intel_plane_atomic_get_property(struct drm_plane *plane,
1572                                     const struct drm_plane_state *state,
1573                                     struct drm_property *property,
1574                                     uint64_t *val);
1575 int intel_plane_atomic_set_property(struct drm_plane *plane,
1576                                     struct drm_plane_state *state,
1577                                     struct drm_property *property,
1578                                     uint64_t val);
1579 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1580                                     struct drm_crtc_state *crtc_state,
1581                                     const struct intel_plane_state *old_plane_state,
1582                                     struct drm_plane_state *plane_state);
1583
1584 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1585                                     enum pipe pipe);
1586
1587 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1588                      const struct dpll *dpll);
1589 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1590 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1591
1592 /* modesetting asserts */
1593 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1594                            enum pipe pipe);
1595 void assert_pll(struct drm_i915_private *dev_priv,
1596                 enum pipe pipe, bool state);
1597 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1598 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1599 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1600 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1601 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1602 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1603                        enum pipe pipe, bool state);
1604 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1605 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1606 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1607 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1608 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1609 u32 intel_compute_tile_offset(int *x, int *y,
1610                               const struct intel_plane_state *state, int plane);
1611 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1612 void intel_finish_reset(struct drm_i915_private *dev_priv);
1613 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1614 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1615 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1616 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1617 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1618 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1619 unsigned int skl_cdclk_get_vco(unsigned int freq);
1620 void intel_dp_get_m_n(struct intel_crtc *crtc,
1621                       struct intel_crtc_state *pipe_config);
1622 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1623 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1624 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1625                         struct dpll *best_clock);
1626 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1627
1628 bool intel_crtc_active(struct intel_crtc *crtc);
1629 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1630 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1631 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1632 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1633 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1634                                  struct intel_crtc_state *pipe_config);
1635 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1636                                   struct intel_crtc_state *crtc_state);
1637
1638 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1639 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1640 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1641                   uint32_t pixel_format);
1642
1643 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1644 {
1645         return i915_ggtt_offset(state->vma);
1646 }
1647
1648 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1649                         const struct intel_plane_state *plane_state);
1650 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1651                   const struct intel_plane_state *plane_state);
1652 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1653 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1654                      unsigned int rotation);
1655 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1656                             struct intel_plane_state *plane_state);
1657 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1658 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1659
1660 /* intel_csr.c */
1661 void intel_csr_ucode_init(struct drm_i915_private *);
1662 void intel_csr_load_program(struct drm_i915_private *);
1663 void intel_csr_ucode_fini(struct drm_i915_private *);
1664 void intel_csr_ucode_suspend(struct drm_i915_private *);
1665 void intel_csr_ucode_resume(struct drm_i915_private *);
1666
1667 /* intel_dp.c */
1668 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1669                            i915_reg_t dp_reg, enum port port,
1670                            enum pipe *pipe);
1671 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1672                    enum port port);
1673 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1674                              struct intel_connector *intel_connector);
1675 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1676                               int link_rate, uint8_t lane_count,
1677                               bool link_mst);
1678 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1679                                             int link_rate, uint8_t lane_count);
1680 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1681 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1682 int intel_dp_retrain_link(struct intel_encoder *encoder,
1683                           struct drm_modeset_acquire_ctx *ctx);
1684 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1685 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1686 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1687 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1688 bool intel_dp_compute_config(struct intel_encoder *encoder,
1689                              struct intel_crtc_state *pipe_config,
1690                              struct drm_connector_state *conn_state);
1691 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1692 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1693 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1694                                   bool long_hpd);
1695 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1696                             const struct drm_connector_state *conn_state);
1697 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1698 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1699 void intel_edp_panel_on(struct intel_dp *intel_dp);
1700 void intel_edp_panel_off(struct intel_dp *intel_dp);
1701 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1702 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1703 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1704 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1705 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1706 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1707 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1708 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1709 void intel_plane_destroy(struct drm_plane *plane);
1710 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1711                            const struct intel_crtc_state *crtc_state);
1712 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1713                             const struct intel_crtc_state *crtc_state);
1714 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1715                                unsigned int frontbuffer_bits);
1716 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1717                           unsigned int frontbuffer_bits);
1718
1719 void
1720 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1721                                        uint8_t dp_train_pat);
1722 void
1723 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1724 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1725 uint8_t
1726 intel_dp_voltage_max(struct intel_dp *intel_dp);
1727 uint8_t
1728 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1729 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1730                            uint8_t *link_bw, uint8_t *rate_select);
1731 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1732 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1733 bool
1734 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1735
1736 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1737 {
1738         return ~((1 << lane_count) - 1) & 0xf;
1739 }
1740
1741 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1742 int intel_dp_link_required(int pixel_clock, int bpp);
1743 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1744 bool intel_digital_port_connected(struct intel_encoder *encoder);
1745
1746 /* intel_dp_aux_backlight.c */
1747 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1748
1749 /* intel_dp_mst.c */
1750 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1751 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1752 /* vlv_dsi.c */
1753 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1754
1755 /* intel_dsi_dcs_backlight.c */
1756 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1757
1758 /* intel_dvo.c */
1759 void intel_dvo_init(struct drm_i915_private *dev_priv);
1760 /* intel_hotplug.c */
1761 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1762 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1763                            struct intel_connector *connector);
1764
1765 /* legacy fbdev emulation in intel_fbdev.c */
1766 #ifdef CONFIG_DRM_FBDEV_EMULATION
1767 extern int intel_fbdev_init(struct drm_device *dev);
1768 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1769 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1770 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1771 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1772 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1773 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1774 #else
1775 static inline int intel_fbdev_init(struct drm_device *dev)
1776 {
1777         return 0;
1778 }
1779
1780 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1781 {
1782 }
1783
1784 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1785 {
1786 }
1787
1788 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1789 {
1790 }
1791
1792 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1793 {
1794 }
1795
1796 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1797 {
1798 }
1799
1800 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1801 {
1802 }
1803 #endif
1804
1805 /* intel_fbc.c */
1806 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1807                            struct intel_atomic_state *state);
1808 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1809 void intel_fbc_pre_update(struct intel_crtc *crtc,
1810                           struct intel_crtc_state *crtc_state,
1811                           struct intel_plane_state *plane_state);
1812 void intel_fbc_post_update(struct intel_crtc *crtc);
1813 void intel_fbc_init(struct drm_i915_private *dev_priv);
1814 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1815 void intel_fbc_enable(struct intel_crtc *crtc,
1816                       struct intel_crtc_state *crtc_state,
1817                       struct intel_plane_state *plane_state);
1818 void intel_fbc_disable(struct intel_crtc *crtc);
1819 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1820 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1821                           unsigned int frontbuffer_bits,
1822                           enum fb_op_origin origin);
1823 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1824                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1825 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1826 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1827 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1828
1829 /* intel_hdmi.c */
1830 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1831                      enum port port);
1832 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1833                                struct intel_connector *intel_connector);
1834 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1835 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1836                                struct intel_crtc_state *pipe_config,
1837                                struct drm_connector_state *conn_state);
1838 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1839                                        struct drm_connector *connector,
1840                                        bool high_tmds_clock_ratio,
1841                                        bool scrambling);
1842 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1843 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1844
1845
1846 /* intel_lvds.c */
1847 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1848                              i915_reg_t lvds_reg, enum pipe *pipe);
1849 void intel_lvds_init(struct drm_i915_private *dev_priv);
1850 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1851 bool intel_is_dual_link_lvds(struct drm_device *dev);
1852
1853
1854 /* intel_modes.c */
1855 int intel_connector_update_modes(struct drm_connector *connector,
1856                                  struct edid *edid);
1857 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1858 void intel_attach_force_audio_property(struct drm_connector *connector);
1859 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1860 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1861
1862
1863 /* intel_overlay.c */
1864 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1865 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1866 int intel_overlay_switch_off(struct intel_overlay *overlay);
1867 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1868                                   struct drm_file *file_priv);
1869 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1870                               struct drm_file *file_priv);
1871 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1872
1873
1874 /* intel_panel.c */
1875 int intel_panel_init(struct intel_panel *panel,
1876                      struct drm_display_mode *fixed_mode,
1877                      struct drm_display_mode *downclock_mode);
1878 void intel_panel_fini(struct intel_panel *panel);
1879 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1880                             struct drm_display_mode *adjusted_mode);
1881 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1882                              struct intel_crtc_state *pipe_config,
1883                              int fitting_mode);
1884 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1885                               struct intel_crtc_state *pipe_config,
1886                               int fitting_mode);
1887 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1888                                     u32 level, u32 max);
1889 int intel_panel_setup_backlight(struct drm_connector *connector,
1890                                 enum pipe pipe);
1891 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1892                                   const struct drm_connector_state *conn_state);
1893 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1894 void intel_panel_destroy_backlight(struct drm_connector *connector);
1895 extern struct drm_display_mode *intel_find_panel_downclock(
1896                                 struct drm_i915_private *dev_priv,
1897                                 struct drm_display_mode *fixed_mode,
1898                                 struct drm_connector *connector);
1899
1900 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1901 int intel_backlight_device_register(struct intel_connector *connector);
1902 void intel_backlight_device_unregister(struct intel_connector *connector);
1903 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1904 static inline int intel_backlight_device_register(struct intel_connector *connector)
1905 {
1906         return 0;
1907 }
1908 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1909 {
1910 }
1911 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1912
1913 /* intel_hdcp.c */
1914 void intel_hdcp_atomic_check(struct drm_connector *connector,
1915                              struct drm_connector_state *old_state,
1916                              struct drm_connector_state *new_state);
1917 int intel_hdcp_init(struct intel_connector *connector,
1918                     const struct intel_hdcp_shim *hdcp_shim);
1919 int intel_hdcp_enable(struct intel_connector *connector);
1920 int intel_hdcp_disable(struct intel_connector *connector);
1921 int intel_hdcp_check_link(struct intel_connector *connector);
1922 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1923
1924 /* intel_psr.c */
1925 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1926 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1927 void intel_psr_enable(struct intel_dp *intel_dp,
1928                       const struct intel_crtc_state *crtc_state);
1929 void intel_psr_disable(struct intel_dp *intel_dp,
1930                       const struct intel_crtc_state *old_crtc_state);
1931 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1932                           unsigned frontbuffer_bits,
1933                           enum fb_op_origin origin);
1934 void intel_psr_flush(struct drm_i915_private *dev_priv,
1935                      unsigned frontbuffer_bits,
1936                      enum fb_op_origin origin);
1937 void intel_psr_init(struct drm_i915_private *dev_priv);
1938 void intel_psr_compute_config(struct intel_dp *intel_dp,
1939                               struct intel_crtc_state *crtc_state);
1940 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1941 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1942 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1943 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
1944
1945 /* intel_runtime_pm.c */
1946 int intel_power_domains_init(struct drm_i915_private *);
1947 void intel_power_domains_fini(struct drm_i915_private *);
1948 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1949 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1950 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1951 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1952 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1953 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1954 const char *
1955 intel_display_power_domain_str(enum intel_display_power_domain domain);
1956
1957 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1958                                     enum intel_display_power_domain domain);
1959 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1960                                       enum intel_display_power_domain domain);
1961 void intel_display_power_get(struct drm_i915_private *dev_priv,
1962                              enum intel_display_power_domain domain);
1963 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1964                                         enum intel_display_power_domain domain);
1965 void intel_display_power_put(struct drm_i915_private *dev_priv,
1966                              enum intel_display_power_domain domain);
1967 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1968                             u8 req_slices);
1969
1970 static inline void
1971 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1972 {
1973         WARN_ONCE(dev_priv->runtime_pm.suspended,
1974                   "Device suspended during HW access\n");
1975 }
1976
1977 static inline void
1978 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1979 {
1980         assert_rpm_device_not_suspended(dev_priv);
1981         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1982                   "RPM wakelock ref not held during HW access");
1983 }
1984
1985 /**
1986  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1987  * @dev_priv: i915 device instance
1988  *
1989  * This function disable asserts that check if we hold an RPM wakelock
1990  * reference, while keeping the device-not-suspended checks still enabled.
1991  * It's meant to be used only in special circumstances where our rule about
1992  * the wakelock refcount wrt. the device power state doesn't hold. According
1993  * to this rule at any point where we access the HW or want to keep the HW in
1994  * an active state we must hold an RPM wakelock reference acquired via one of
1995  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1996  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1997  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1998  * users should avoid using this function.
1999  *
2000  * Any calls to this function must have a symmetric call to
2001  * enable_rpm_wakeref_asserts().
2002  */
2003 static inline void
2004 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2005 {
2006         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2007 }
2008
2009 /**
2010  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2011  * @dev_priv: i915 device instance
2012  *
2013  * This function re-enables the RPM assert checks after disabling them with
2014  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2015  * circumstances otherwise its use should be avoided.
2016  *
2017  * Any calls to this function must have a symmetric call to
2018  * disable_rpm_wakeref_asserts().
2019  */
2020 static inline void
2021 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2022 {
2023         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2024 }
2025
2026 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2027 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2028 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2029 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2030
2031 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2032
2033 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2034                              bool override, unsigned int mask);
2035 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2036                           enum dpio_channel ch, bool override);
2037
2038
2039 /* intel_pm.c */
2040 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2041 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2042 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2043 void intel_update_watermarks(struct intel_crtc *crtc);
2044 void intel_init_pm(struct drm_i915_private *dev_priv);
2045 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2046 void intel_pm_setup(struct drm_i915_private *dev_priv);
2047 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2048 void intel_gpu_ips_teardown(void);
2049 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2050 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2051 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2052 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2053 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2054 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2055 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2056 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2057 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2058 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2059 void g4x_wm_get_hw_state(struct drm_device *dev);
2060 void vlv_wm_get_hw_state(struct drm_device *dev);
2061 void ilk_wm_get_hw_state(struct drm_device *dev);
2062 void skl_wm_get_hw_state(struct drm_device *dev);
2063 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2064                           struct skl_ddb_allocation *ddb /* out */);
2065 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2066                               struct skl_pipe_wm *out);
2067 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2068 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2069 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2070 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2071 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2072 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2073                          const struct skl_wm_level *l2);
2074 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2075                                  const struct skl_ddb_entry **entries,
2076                                  const struct skl_ddb_entry *ddb,
2077                                  int ignore);
2078 bool ilk_disable_lp_wm(struct drm_device *dev);
2079 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2080                                   struct intel_crtc_state *cstate);
2081 void intel_init_ipc(struct drm_i915_private *dev_priv);
2082 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2083
2084 /* intel_sdvo.c */
2085 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2086                              i915_reg_t sdvo_reg, enum pipe *pipe);
2087 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2088                      i915_reg_t reg, enum port port);
2089
2090
2091 /* intel_sprite.c */
2092 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2093                              int usecs);
2094 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2095                                               enum pipe pipe, int plane);
2096 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2097                                     struct drm_file *file_priv);
2098 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2099 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2100 void skl_update_plane(struct intel_plane *plane,
2101                       const struct intel_crtc_state *crtc_state,
2102                       const struct intel_plane_state *plane_state);
2103 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2104 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2105 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2106                        enum pipe pipe, enum plane_id plane_id);
2107 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2108                           enum pipe pipe, enum plane_id plane_id);
2109
2110 /* intel_tv.c */
2111 void intel_tv_init(struct drm_i915_private *dev_priv);
2112
2113 /* intel_atomic.c */
2114 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2115                                                 const struct drm_connector_state *state,
2116                                                 struct drm_property *property,
2117                                                 uint64_t *val);
2118 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2119                                                 struct drm_connector_state *state,
2120                                                 struct drm_property *property,
2121                                                 uint64_t val);
2122 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2123                                          struct drm_connector_state *new_state);
2124 struct drm_connector_state *
2125 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2126
2127 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2128 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2129                                struct drm_crtc_state *state);
2130 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2131 void intel_atomic_state_clear(struct drm_atomic_state *);
2132
2133 static inline struct intel_crtc_state *
2134 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2135                             struct intel_crtc *crtc)
2136 {
2137         struct drm_crtc_state *crtc_state;
2138         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2139         if (IS_ERR(crtc_state))
2140                 return ERR_CAST(crtc_state);
2141
2142         return to_intel_crtc_state(crtc_state);
2143 }
2144
2145 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2146                                struct intel_crtc *intel_crtc,
2147                                struct intel_crtc_state *crtc_state);
2148
2149 /* intel_atomic_plane.c */
2150 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2151 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2152 void intel_plane_destroy_state(struct drm_plane *plane,
2153                                struct drm_plane_state *state);
2154 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2155 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2156                                         struct intel_crtc_state *crtc_state,
2157                                         const struct intel_plane_state *old_plane_state,
2158                                         struct intel_plane_state *intel_state);
2159
2160 /* intel_color.c */
2161 void intel_color_init(struct drm_crtc *crtc);
2162 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2163 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2164 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2165
2166 /* intel_lspcon.c */
2167 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2168 void lspcon_resume(struct intel_lspcon *lspcon);
2169 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2170
2171 /* intel_pipe_crc.c */
2172 #ifdef CONFIG_DEBUG_FS
2173 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2174                               size_t *values_cnt);
2175 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2176 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2177 #else
2178 #define intel_crtc_set_crc_source NULL
2179 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2180 {
2181 }
2182
2183 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2184 {
2185 }
2186 #endif
2187 #endif /* __INTEL_DRV_H__ */