drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133
 134         enum intel_output_type type;
 135         unsigned int cloneable;
 136         void (*hot_plug)(struct intel_encoder *);
 137         bool (*compute_config)(struct intel_encoder *,
 138                                struct intel_crtc_state *);
 139         void (*pre_pll_enable)(struct intel_encoder *);
 140         void (*pre_enable)(struct intel_encoder *);
 141         void (*enable)(struct intel_encoder *);
 142         void (*mode_set)(struct intel_encoder *intel_encoder);
 143         void (*disable)(struct intel_encoder *);
 144         void (*post_disable)(struct intel_encoder *);
 145         void (*post_pll_disable)(struct intel_encoder *);
 146         /* Read out the current hw state of this connector, returning true if
 147          * the encoder is active. If the encoder is enabled it also set the pipe
 148          * it is connected to in the pipe parameter. */
 149         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 150         /* Reconstructs the equivalent mode flags for the current hardware
 151          * state. This must be called _after_ display->get_pipe_config has
 152          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 153          * be set correctly before calling this function. */
 154         void (*get_config)(struct intel_encoder *,
 155                            struct intel_crtc_state *pipe_config);
 156         /*
 157          * Called during system suspend after all pending requests for the
 158          * encoder are flushed (for example for DP AUX transactions) and
 159          * device interrupts are disabled.
 160          */
 161         void (*suspend)(struct intel_encoder *);
 162         int crtc_mask;
 163         enum hpd_pin hpd_pin;
 164 };
 165
 166 struct intel_panel {
 167         struct drm_display_mode *fixed_mode;
 168         struct drm_display_mode *downclock_mode;
 169         int fitting_mode;
 170
 171         /* backlight */
 172         struct {
 173                 bool present;
 174                 u32 level;
 175                 u32 min;
 176                 u32 max;
 177                 bool enabled;
 178                 bool combination_mode;  /* gen 2/4 only */
 179                 bool active_low_pwm;
 180
 181                 /* PWM chip */
 182                 bool util_pin_active_low;       /* bxt+ */
 183                 u8 controller;          /* bxt+ only */
 184                 struct pwm_device *pwm;
 185
 186                 struct backlight_device *device;
 187
 188                 /* Connector and platform specific backlight functions */
 189                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 190                 uint32_t (*get)(struct intel_connector *connector);
 191                 void (*set)(struct intel_connector *connector, uint32_t level);
 192                 void (*disable)(struct intel_connector *connector);
 193                 void (*enable)(struct intel_connector *connector);
 194                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 195                                       uint32_t hz);
 196                 void (*power)(struct intel_connector *, bool enable);
 197         } backlight;
 198 };
 199
 200 struct intel_connector {
 201         struct drm_connector base;
 202         /*
 203          * The fixed encoder this connector is connected to.
 204          */
 205         struct intel_encoder *encoder;
 206
 207         /* Reads out the current hw, returning true if the connector is enabled
 208          * and active (i.e. dpms ON state). */
 209         bool (*get_hw_state)(struct intel_connector *);
 210
 211         /*
 212          * Removes all interfaces through which the connector is accessible
 213          * - like sysfs, debugfs entries -, so that no new operations can be
 214          * started on the connector. Also makes sure all currently pending
 215          * operations finish before returing.
 216          */
 217         void (*unregister)(struct intel_connector *);
 218
 219         /* Panel info for eDP and LVDS */
 220         struct intel_panel panel;
 221
 222         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 223         struct edid *edid;
 224         struct edid *detect_edid;
 225
 226         /* since POLL and HPD connectors may use the same HPD line keep the native
 227            state of connector->polled in case hotplug storm detection changes it */
 228         u8 polled;
 229
 230         void *port; /* store this opaque as its illegal to dereference it */
 231
 232         struct intel_dp *mst_port;
 233 };
 234
 235 typedef struct dpll {
 236         /* given values */
 237         int n;
 238         int m1, m2;
 239         int p1, p2;
 240         /* derived values */
 241         int     dot;
 242         int     vco;
 243         int     m;
 244         int     p;
 245 } intel_clock_t;
 246
 247 struct intel_atomic_state {
 248         struct drm_atomic_state base;
 249
 250         unsigned int cdclk;
 251         bool dpll_set;
 252         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 253         struct intel_wm_config wm_config;
 254 };
 255
 256 struct intel_plane_state {
 257         struct drm_plane_state base;
 258         struct drm_rect src;
 259         struct drm_rect dst;
 260         struct drm_rect clip;
 261         bool visible;
 262
 263         /*
 264          * scaler_id
 265          *    = -1 : not using a scaler
 266          *    >=  0 : using a scalers
 267          *
 268          * plane requiring a scaler:
 269          *   - During check_plane, its bit is set in
 270          *     crtc_state->scaler_state.scaler_users by calling helper function
 271          *     update_scaler_plane.
 272          *   - scaler_id indicates the scaler it got assigned.
 273          *
 274          * plane doesn't require a scaler:
 275          *   - this can happen when scaling is no more required or plane simply
 276          *     got disabled.
 277          *   - During check_plane, corresponding bit is reset in
 278          *     crtc_state->scaler_state.scaler_users by calling helper function
 279          *     update_scaler_plane.
 280          */
 281         int scaler_id;
 282
 283         struct drm_intel_sprite_colorkey ckey;
 284
 285         /* async flip related structures */
 286         struct drm_i915_gem_request *wait_req;
 287 };
 288
 289 struct intel_initial_plane_config {
 290         struct intel_framebuffer *fb;
 291         unsigned int tiling;
 292         int size;
 293         u32 base;
 294 };
 295
 296 #define SKL_MIN_SRC_W 8
 297 #define SKL_MAX_SRC_W 4096
 298 #define SKL_MIN_SRC_H 8
 299 #define SKL_MAX_SRC_H 4096
 300 #define SKL_MIN_DST_W 8
 301 #define SKL_MAX_DST_W 4096
 302 #define SKL_MIN_DST_H 8
 303 #define SKL_MAX_DST_H 4096
 304
 305 struct intel_scaler {
 306         int in_use;
 307         uint32_t mode;
 308 };
 309
 310 struct intel_crtc_scaler_state {
 311 #define SKL_NUM_SCALERS 2
 312         struct intel_scaler scalers[SKL_NUM_SCALERS];
 313
 314         /*
 315          * scaler_users: keeps track of users requesting scalers on this crtc.
 316          *
 317          *     If a bit is set, a user is using a scaler.
 318          *     Here user can be a plane or crtc as defined below:
 319          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 320          *       bit 31    - crtc
 321          *
 322          * Instead of creating a new index to cover planes and crtc, using
 323          * existing drm_plane_index for planes which is well less than 31
 324          * planes and bit 31 for crtc. This should be fine to cover all
 325          * our platforms.
 326          *
 327          * intel_atomic_setup_scalers will setup available scalers to users
 328          * requesting scalers. It will gracefully fail if request exceeds
 329          * avilability.
 330          */
 331 #define SKL_CRTC_INDEX 31
 332         unsigned scaler_users;
 333
 334         /* scaler used by crtc for panel fitting purpose */
 335         int scaler_id;
 336 };
 337
 338 /* drm_mode->private_flags */
 339 #define I915_MODE_FLAG_INHERITED 1
 340
 341 struct intel_pipe_wm {
 342         struct intel_wm_level wm[5];
 343         uint32_t linetime;
 344         bool fbc_wm_enabled;
 345         bool pipe_enabled;
 346         bool sprites_enabled;
 347         bool sprites_scaled;
 348 };
 349
 350 struct skl_pipe_wm {
 351         struct skl_wm_level wm[8];
 352         struct skl_wm_level trans_wm;
 353         uint32_t linetime;
 354 };
 355
 356 struct intel_crtc_state {
 357         struct drm_crtc_state base;
 358
 359         /**
 360          * quirks - bitfield with hw state readout quirks
 361          *
 362          * For various reasons the hw state readout code might not be able to
 363          * completely faithfully read out the current state. These cases are
 364          * tracked with quirk flags so that fastboot and state checker can act
 365          * accordingly.
 366          */
 367 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 368         unsigned long quirks;
 369
 370         bool update_pipe;
 371
 372         /* Pipe source size (ie. panel fitter input size)
 373          * All planes will be positioned inside this space,
 374          * and get clipped at the edges. */
 375         int pipe_src_w, pipe_src_h;
 376
 377         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 378          * between pch encoders and cpu encoders. */
 379         bool has_pch_encoder;
 380
 381         /* Are we sending infoframes on the attached port */
 382         bool has_infoframe;
 383
 384         /* CPU Transcoder for the pipe. Currently this can only differ from the
 385          * pipe on Haswell (where we have a special eDP transcoder). */
 386         enum transcoder cpu_transcoder;
 387
 388         /*
 389          * Use reduced/limited/broadcast rbg range, compressing from the full
 390          * range fed into the crtcs.
 391          */
 392         bool limited_color_range;
 393
 394         /* DP has a bunch of special case unfortunately, so mark the pipe
 395          * accordingly. */
 396         bool has_dp_encoder;
 397
 398         /* Whether we should send NULL infoframes. Required for audio. */
 399         bool has_hdmi_sink;
 400
 401         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 402          * has_dp_encoder is set. */
 403         bool has_audio;
 404
 405         /*
 406          * Enable dithering, used when the selected pipe bpp doesn't match the
 407          * plane bpp.
 408          */
 409         bool dither;
 410
 411         /* Controls for the clock computation, to override various stages. */
 412         bool clock_set;
 413
 414         /* SDVO TV has a bunch of special case. To make multifunction encoders
 415          * work correctly, we need to track this at runtime.*/
 416         bool sdvo_tv_clock;
 417
 418         /*
 419          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 420          * required. This is set in the 2nd loop of calling encoder's
 421          * ->compute_config if the first pick doesn't work out.
 422          */
 423         bool bw_constrained;
 424
 425         /* Settings for the intel dpll used on pretty much everything but
 426          * haswell. */
 427         struct dpll dpll;
 428
 429         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 430         enum intel_dpll_id shared_dpll;
 431
 432         /*
 433          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 434          * - enum skl_dpll on SKL
 435          */
 436         uint32_t ddi_pll_sel;
 437
 438         /* Actual register state of the dpll, for shared dpll cross-checking. */
 439         struct intel_dpll_hw_state dpll_hw_state;
 440
 441         int pipe_bpp;
 442         struct intel_link_m_n dp_m_n;
 443
 444         /* m2_n2 for eDP downclock */
 445         struct intel_link_m_n dp_m2_n2;
 446         bool has_drrs;
 447
 448         /*
 449          * Frequence the dpll for the port should run at. Differs from the
 450          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 451          * already multiplied by pixel_multiplier.
 452          */
 453         int port_clock;
 454
 455         /* Used by SDVO (and if we ever fix it, HDMI). */
 456         unsigned pixel_multiplier;
 457
 458         uint8_t lane_count;
 459
 460         /* Panel fitter controls for gen2-gen4 + VLV */
 461         struct {
 462                 u32 control;
 463                 u32 pgm_ratios;
 464                 u32 lvds_border_bits;
 465         } gmch_pfit;
 466
 467         /* Panel fitter placement and size for Ironlake+ */
 468         struct {
 469                 u32 pos;
 470                 u32 size;
 471                 bool enabled;
 472                 bool force_thru;
 473         } pch_pfit;
 474
 475         /* FDI configuration, only valid if has_pch_encoder is set. */
 476         int fdi_lanes;
 477         struct intel_link_m_n fdi_m_n;
 478
 479         bool ips_enabled;
 480
 481         bool double_wide;
 482
 483         bool dp_encoder_is_mst;
 484         int pbn;
 485
 486         struct intel_crtc_scaler_state scaler_state;
 487
 488         /* w/a for waiting 2 vblanks during crtc enable */
 489         enum pipe hsw_workaround_pipe;
 490
 491         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 492         bool disable_lp_wm;
 493
 494         struct {
 495                 /*
 496                  * optimal watermarks, programmed post-vblank when this state
 497                  * is committed
 498                  */
 499                 union {
 500                         struct intel_pipe_wm ilk;
 501                         struct skl_pipe_wm skl;
 502                 } optimal;
 503         } wm;
 504 };
 505
 506 struct vlv_wm_state {
 507         struct vlv_pipe_wm wm[3];
 508         struct vlv_sr_wm sr[3];
 509         uint8_t num_active_planes;
 510         uint8_t num_levels;
 511         uint8_t level;
 512         bool cxsr;
 513 };
 514
 515 struct intel_mmio_flip {
 516         struct work_struct work;
 517         struct drm_i915_private *i915;
 518         struct drm_i915_gem_request *req;
 519         struct intel_crtc *crtc;
 520         unsigned int rotation;
 521 };
 522
 523 /*
 524  * Tracking of operations that need to be performed at the beginning/end of an
 525  * atomic commit, outside the atomic section where interrupts are disabled.
 526  * These are generally operations that grab mutexes or might otherwise sleep
 527  * and thus can't be run with interrupts disabled.
 528  */
 529 struct intel_crtc_atomic_commit {
 530         /* Sleepable operations to perform before commit */
 531         bool disable_fbc;
 532         bool disable_ips;
 533         bool disable_cxsr;
 534         bool pre_disable_primary;
 535         bool update_wm_pre, update_wm_post;
 536
 537         /* Sleepable operations to perform after commit */
 538         unsigned fb_bits;
 539         bool wait_vblank;
 540         bool update_fbc;
 541         bool post_enable_primary;
 542         unsigned update_sprite_watermarks;
 543 };
 544
 545 struct intel_crtc {
 546         struct drm_crtc base;
 547         enum pipe pipe;
 548         enum plane plane;
 549         u8 lut_r[256], lut_g[256], lut_b[256];
 550         /*
 551          * Whether the crtc and the connected output pipeline is active. Implies
 552          * that crtc->enabled is set, i.e. the current mode configuration has
 553          * some outputs connected to this crtc.
 554          */
 555         bool active;
 556         unsigned long enabled_power_domains;
 557         bool lowfreq_avail;
 558         struct intel_overlay *overlay;
 559         struct intel_unpin_work *unpin_work;
 560
 561         atomic_t unpin_work_count;
 562
 563         /* Display surface base address adjustement for pageflips. Note that on
 564          * gen4+ this only adjusts up to a tile, offsets within a tile are
 565          * handled in the hw itself (with the TILEOFF register). */
 566         unsigned long dspaddr_offset;
 567         int adjusted_x;
 568         int adjusted_y;
 569
 570         struct drm_i915_gem_object *cursor_bo;
 571         uint32_t cursor_addr;
 572         uint32_t cursor_cntl;
 573         uint32_t cursor_size;
 574         uint32_t cursor_base;
 575
 576         struct intel_crtc_state *config;
 577
 578         /* reset counter value when the last flip was submitted */
 579         unsigned int reset_counter;
 580
 581         /* Access to these should be protected by dev_priv->irq_lock. */
 582         bool cpu_fifo_underrun_disabled;
 583         bool pch_fifo_underrun_disabled;
 584
 585         /* per-pipe watermark state */
 586         struct {
 587                 /* watermarks currently being used  */
 588                 union {
 589                         struct intel_pipe_wm ilk;
 590                         struct skl_pipe_wm skl;
 591                 } active;
 592                 /* allow CxSR on this pipe */
 593                 bool cxsr_allowed;
 594         } wm;
 595
 596         int scanline_offset;
 597
 598         struct {
 599                 unsigned start_vbl_count;
 600                 ktime_t start_vbl_time;
 601                 int min_vbl, max_vbl;
 602                 int scanline_start;
 603         } debug;
 604
 605         struct intel_crtc_atomic_commit atomic;
 606
 607         /* scalers available on this crtc */
 608         int num_scalers;
 609
 610         struct vlv_wm_state wm_state;
 611 };
 612
 613 struct intel_plane_wm_parameters {
 614         uint32_t horiz_pixels;
 615         uint32_t vert_pixels;
 616         /*
 617          *   For packed pixel formats:
 618          *     bytes_per_pixel - holds bytes per pixel
 619          *   For planar pixel formats:
 620          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 621          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 622          */
 623         uint8_t bytes_per_pixel;
 624         uint8_t y_bytes_per_pixel;
 625         bool enabled;
 626         bool scaled;
 627         u64 tiling;
 628         unsigned int rotation;
 629         uint16_t fifo_size;
 630 };
 631
 632 struct intel_plane {
 633         struct drm_plane base;
 634         int plane;
 635         enum pipe pipe;
 636         bool can_scale;
 637         int max_downscale;
 638         uint32_t frontbuffer_bit;
 639
 640         /* Since we need to change the watermarks before/after
 641          * enabling/disabling the planes, we need to store the parameters here
 642          * as the other pieces of the struct may not reflect the values we want
 643          * for the watermark calculations. Currently only Haswell uses this.
 644          */
 645         struct intel_plane_wm_parameters wm;
 646
 647         /*
 648          * NOTE: Do not place new plane state fields here (e.g., when adding
 649          * new plane properties).  New runtime state should now be placed in
 650          * the intel_plane_state structure and accessed via drm_plane->state.
 651          */
 652
 653         void (*update_plane)(struct drm_plane *plane,
 654                              struct drm_crtc *crtc,
 655                              struct drm_framebuffer *fb,
 656                              int crtc_x, int crtc_y,
 657                              unsigned int crtc_w, unsigned int crtc_h,
 658                              uint32_t x, uint32_t y,
 659                              uint32_t src_w, uint32_t src_h);
 660         void (*disable_plane)(struct drm_plane *plane,
 661                               struct drm_crtc *crtc);
 662         int (*check_plane)(struct drm_plane *plane,
 663                            struct intel_crtc_state *crtc_state,
 664                            struct intel_plane_state *state);
 665         void (*commit_plane)(struct drm_plane *plane,
 666                              struct intel_plane_state *state);
 667 };
 668
 669 struct intel_watermark_params {
 670         unsigned long fifo_size;
 671         unsigned long max_wm;
 672         unsigned long default_wm;
 673         unsigned long guard_size;
 674         unsigned long cacheline_size;
 675 };
 676
 677 struct cxsr_latency {
 678         int is_desktop;
 679         int is_ddr3;
 680         unsigned long fsb_freq;
 681         unsigned long mem_freq;
 682         unsigned long display_sr;
 683         unsigned long display_hpll_disable;
 684         unsigned long cursor_sr;
 685         unsigned long cursor_hpll_disable;
 686 };
 687
 688 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 689 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 690 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 691 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 692 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 693 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 694 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 695 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 696 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 697
 698 struct intel_hdmi {
 699         u32 hdmi_reg;
 700         int ddc_bus;
 701         bool limited_color_range;
 702         bool color_range_auto;
 703         bool has_hdmi_sink;
 704         bool has_audio;
 705         enum hdmi_force_audio force_audio;
 706         bool rgb_quant_range_selectable;
 707         enum hdmi_picture_aspect aspect_ratio;
 708         struct intel_connector *attached_connector;
 709         void (*write_infoframe)(struct drm_encoder *encoder,
 710                                 enum hdmi_infoframe_type type,
 711                                 const void *frame, ssize_t len);
 712         void (*set_infoframes)(struct drm_encoder *encoder,
 713                                bool enable,
 714                                const struct drm_display_mode *adjusted_mode);
 715         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 716 };
 717
 718 struct intel_dp_mst_encoder;
 719 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 720
 721 /*
 722  * enum link_m_n_set:
 723  *      When platform provides two set of M_N registers for dp, we can
 724  *      program them and switch between them incase of DRRS.
 725  *      But When only one such register is provided, we have to program the
 726  *      required divider value on that registers itself based on the DRRS state.
 727  *
 728  * M1_N1        : Program dp_m_n on M1_N1 registers
 729  *                        dp_m2_n2 on M2_N2 registers (If supported)
 730  *
 731  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 732  *                        M2_N2 registers are not supported
 733  */
 734
 735 enum link_m_n_set {
 736         /* Sets the m1_n1 and m2_n2 */
 737         M1_N1 = 0,
 738         M2_N2
 739 };
 740
 741 struct sink_crc {
 742         bool started;
 743 };
 744
 745 struct intel_dp {
 746         uint32_t output_reg;
 747         uint32_t aux_ch_ctl_reg;
 748         uint32_t aux_ch_data_reg[5];
 749         uint32_t DP;
 750         int link_rate;
 751         uint8_t lane_count;
 752         bool has_audio;
 753         enum hdmi_force_audio force_audio;
 754         bool limited_color_range;
 755         bool color_range_auto;
 756         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 757         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 758         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 759         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 760         uint8_t num_sink_rates;
 761         int sink_rates[DP_MAX_SUPPORTED_RATES];
 762         struct sink_crc sink_crc;
 763         struct drm_dp_aux aux;
 764         uint8_t train_set[4];
 765         int panel_power_up_delay;
 766         int panel_power_down_delay;
 767         int panel_power_cycle_delay;
 768         int backlight_on_delay;
 769         int backlight_off_delay;
 770         struct delayed_work panel_vdd_work;
 771         bool want_panel_vdd;
 772         unsigned long last_power_cycle;
 773         unsigned long last_power_on;
 774         unsigned long last_backlight_off;
 775
 776         struct notifier_block edp_notifier;
 777
 778         /*
 779          * Pipe whose power sequencer is currently locked into
 780          * this port. Only relevant on VLV/CHV.
 781          */
 782         enum pipe pps_pipe;
 783         struct edp_power_seq pps_delays;
 784
 785         bool can_mst; /* this port supports mst */
 786         bool is_mst;
 787         int active_mst_links;
 788         /* connector directly attached - won't be use for modeset in mst world */
 789         struct intel_connector *attached_connector;
 790
 791         /* mst connector list */
 792         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 793         struct drm_dp_mst_topology_mgr mst_mgr;
 794
 795         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 796         /*
 797          * This function returns the value we have to program the AUX_CTL
 798          * register with to kick off an AUX transaction.
 799          */
 800         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 801                                      bool has_aux_irq,
 802                                      int send_bytes,
 803                                      uint32_t aux_clock_divider);
 804
 805         /* This is called before a link training is starterd */
 806         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 807
 808         bool train_set_valid;
 809
 810         /* Displayport compliance testing */
 811         unsigned long compliance_test_type;
 812         unsigned long compliance_test_data;
 813         bool compliance_test_active;
 814 };
 815
 816 struct intel_digital_port {
 817         struct intel_encoder base;
 818         enum port port;
 819         u32 saved_port_bits;
 820         struct intel_dp dp;
 821         struct intel_hdmi hdmi;
 822         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 823         bool release_cl2_override;
 824 };
 825
 826 struct intel_dp_mst_encoder {
 827         struct intel_encoder base;
 828         enum pipe pipe;
 829         struct intel_digital_port *primary;
 830         void *port; /* store this opaque as its illegal to dereference it */
 831 };
 832
 833 static inline enum dpio_channel
 834 vlv_dport_to_channel(struct intel_digital_port *dport)
 835 {
 836         switch (dport->port) {
 837         case PORT_B:
 838         case PORT_D:
 839                 return DPIO_CH0;
 840         case PORT_C:
 841                 return DPIO_CH1;
 842         default:
 843                 BUG();
 844         }
 845 }
 846
 847 static inline enum dpio_phy
 848 vlv_dport_to_phy(struct intel_digital_port *dport)
 849 {
 850         switch (dport->port) {
 851         case PORT_B:
 852         case PORT_C:
 853                 return DPIO_PHY0;
 854         case PORT_D:
 855                 return DPIO_PHY1;
 856         default:
 857                 BUG();
 858         }
 859 }
 860
 861 static inline enum dpio_channel
 862 vlv_pipe_to_channel(enum pipe pipe)
 863 {
 864         switch (pipe) {
 865         case PIPE_A:
 866         case PIPE_C:
 867                 return DPIO_CH0;
 868         case PIPE_B:
 869                 return DPIO_CH1;
 870         default:
 871                 BUG();
 872         }
 873 }
 874
 875 static inline struct drm_crtc *
 876 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 877 {
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         return dev_priv->pipe_to_crtc_mapping[pipe];
 880 }
 881
 882 static inline struct drm_crtc *
 883 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 884 {
 885         struct drm_i915_private *dev_priv = dev->dev_private;
 886         return dev_priv->plane_to_crtc_mapping[plane];
 887 }
 888
 889 struct intel_unpin_work {
 890         struct work_struct work;
 891         struct drm_crtc *crtc;
 892         struct drm_framebuffer *old_fb;
 893         struct drm_i915_gem_object *pending_flip_obj;
 894         struct drm_pending_vblank_event *event;
 895         atomic_t pending;
 896 #define INTEL_FLIP_INACTIVE     0
 897 #define INTEL_FLIP_PENDING      1
 898 #define INTEL_FLIP_COMPLETE     2
 899         u32 flip_count;
 900         u32 gtt_offset;
 901         struct drm_i915_gem_request *flip_queued_req;
 902         u32 flip_queued_vblank;
 903         u32 flip_ready_vblank;
 904         bool enable_stall_check;
 905 };
 906
 907 struct intel_load_detect_pipe {
 908         struct drm_framebuffer *release_fb;
 909         bool load_detect_temp;
 910         int dpms_mode;
 911 };
 912
 913 static inline struct intel_encoder *
 914 intel_attached_encoder(struct drm_connector *connector)
 915 {
 916         return to_intel_connector(connector)->encoder;
 917 }
 918
 919 static inline struct intel_digital_port *
 920 enc_to_dig_port(struct drm_encoder *encoder)
 921 {
 922         return container_of(encoder, struct intel_digital_port, base.base);
 923 }
 924
 925 static inline struct intel_dp_mst_encoder *
 926 enc_to_mst(struct drm_encoder *encoder)
 927 {
 928         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 929 }
 930
 931 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 932 {
 933         return &enc_to_dig_port(encoder)->dp;
 934 }
 935
 936 static inline struct intel_digital_port *
 937 dp_to_dig_port(struct intel_dp *intel_dp)
 938 {
 939         return container_of(intel_dp, struct intel_digital_port, dp);
 940 }
 941
 942 static inline struct intel_digital_port *
 943 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 944 {
 945         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 946 }
 947
 948 /*
 949  * Returns the number of planes for this pipe, ie the number of sprites + 1
 950  * (primary plane). This doesn't count the cursor plane then.
 951  */
 952 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 953 {
 954         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 955 }
 956
 957 /* intel_fifo_underrun.c */
 958 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 959                                            enum pipe pipe, bool enable);
 960 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 961                                            enum transcoder pch_transcoder,
 962                                            bool enable);
 963 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 964                                          enum pipe pipe);
 965 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 966                                          enum transcoder pch_transcoder);
 967 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 968 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 969
 970 /* i915_irq.c */
 971 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 972 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 973 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 974 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 975 void gen6_reset_rps_interrupts(struct drm_device *dev);
 976 void gen6_enable_rps_interrupts(struct drm_device *dev);
 977 void gen6_disable_rps_interrupts(struct drm_device *dev);
 978 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 979 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 980 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 981 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 982 {
 983         /*
 984          * We only use drm_irq_uninstall() at unload and VT switch, so
 985          * this is the only thing we need to check.
 986          */
 987         return dev_priv->pm.irqs_enabled;
 988 }
 989
 990 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 991 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 992                                      unsigned int pipe_mask);
 993
 994 /* intel_crt.c */
 995 void intel_crt_init(struct drm_device *dev);
 996
 997
 998 /* intel_ddi.c */
 999 void intel_ddi_clk_select(struct intel_encoder *encoder,
1000                           const struct intel_crtc_state *pipe_config);
1001 void intel_prepare_ddi(struct drm_device *dev);
1002 void hsw_fdi_link_train(struct drm_crtc *crtc);
1003 void intel_ddi_init(struct drm_device *dev, enum port port);
1004 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1005 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1006 void intel_ddi_pll_init(struct drm_device *dev);
1007 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1008 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1009                                        enum transcoder cpu_transcoder);
1010 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1011 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1012 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1013                           struct intel_crtc_state *crtc_state);
1014 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1015 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1016 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1017 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1018 void intel_ddi_get_config(struct intel_encoder *encoder,
1019                           struct intel_crtc_state *pipe_config);
1020 struct intel_encoder *
1021 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1022
1023 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1024 void intel_ddi_clock_get(struct intel_encoder *encoder,
1025                          struct intel_crtc_state *pipe_config);
1026 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1027 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1028
1029 /* intel_frontbuffer.c */
1030 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1031                              enum fb_op_origin origin);
1032 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1033                                     unsigned frontbuffer_bits);
1034 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1035                                      unsigned frontbuffer_bits);
1036 void intel_frontbuffer_flip(struct drm_device *dev,
1037                             unsigned frontbuffer_bits);
1038 unsigned int intel_fb_align_height(struct drm_device *dev,
1039                                    unsigned int height,
1040                                    uint32_t pixel_format,
1041                                    uint64_t fb_format_modifier);
1042 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1043                         enum fb_op_origin origin);
1044 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1045                               uint32_t pixel_format);
1046
1047 /* intel_audio.c */
1048 void intel_init_audio(struct drm_device *dev);
1049 void intel_audio_codec_enable(struct intel_encoder *encoder);
1050 void intel_audio_codec_disable(struct intel_encoder *encoder);
1051 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1052 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1053
1054 /* intel_display.c */
1055 extern const struct drm_plane_funcs intel_plane_funcs;
1056 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1057 int intel_pch_rawclk(struct drm_device *dev);
1058 int intel_hrawclk(struct drm_device *dev);
1059 void intel_mark_busy(struct drm_device *dev);
1060 void intel_mark_idle(struct drm_device *dev);
1061 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1062 int intel_display_suspend(struct drm_device *dev);
1063 void intel_encoder_destroy(struct drm_encoder *encoder);
1064 int intel_connector_init(struct intel_connector *);
1065 struct intel_connector *intel_connector_alloc(void);
1066 bool intel_connector_get_hw_state(struct intel_connector *connector);
1067 void intel_connector_attach_encoder(struct intel_connector *connector,
1068                                     struct intel_encoder *encoder);
1069 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1070 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1071                                              struct drm_crtc *crtc);
1072 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1073 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1074                                 struct drm_file *file_priv);
1075 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1076                                              enum pipe pipe);
1077 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1078 static inline void
1079 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1080 {
1081         drm_wait_one_vblank(dev, pipe);
1082 }
1083 static inline void
1084 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1085 {
1086         const struct intel_crtc *crtc =
1087                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1088
1089         if (crtc->active)
1090                 intel_wait_for_vblank(dev, pipe);
1091 }
1092 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1093 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1094                          struct intel_digital_port *dport,
1095                          unsigned int expected_mask);
1096 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1097                                 struct drm_display_mode *mode,
1098                                 struct intel_load_detect_pipe *old,
1099                                 struct drm_modeset_acquire_ctx *ctx);
1100 void intel_release_load_detect_pipe(struct drm_connector *connector,
1101                                     struct intel_load_detect_pipe *old,
1102                                     struct drm_modeset_acquire_ctx *ctx);
1103 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1104                                struct drm_framebuffer *fb,
1105                                const struct drm_plane_state *plane_state);
1106 struct drm_framebuffer *
1107 __intel_framebuffer_create(struct drm_device *dev,
1108                            struct drm_mode_fb_cmd2 *mode_cmd,
1109                            struct drm_i915_gem_object *obj);
1110 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1111 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1112 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1113 void intel_check_page_flip(struct drm_device *dev, int pipe);
1114 int intel_prepare_plane_fb(struct drm_plane *plane,
1115                            const struct drm_plane_state *new_state);
1116 void intel_cleanup_plane_fb(struct drm_plane *plane,
1117                             const struct drm_plane_state *old_state);
1118 int intel_plane_atomic_get_property(struct drm_plane *plane,
1119                                     const struct drm_plane_state *state,
1120                                     struct drm_property *property,
1121                                     uint64_t *val);
1122 int intel_plane_atomic_set_property(struct drm_plane *plane,
1123                                     struct drm_plane_state *state,
1124                                     struct drm_property *property,
1125                                     uint64_t val);
1126 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1127                                     struct drm_plane_state *plane_state);
1128
1129 unsigned int
1130 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1131                   uint64_t fb_format_modifier, unsigned int plane);
1132
1133 static inline bool
1134 intel_rotation_90_or_270(unsigned int rotation)
1135 {
1136         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1137 }
1138
1139 void intel_create_rotation_property(struct drm_device *dev,
1140                                         struct intel_plane *plane);
1141
1142 /* shared dpll functions */
1143 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1144 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1145                         struct intel_shared_dpll *pll,
1146                         bool state);
1147 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1148 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1149 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1150                                                 struct intel_crtc_state *state);
1151
1152 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1153                       const struct dpll *dpll);
1154 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1155
1156 /* modesetting asserts */
1157 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1158                            enum pipe pipe);
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state);
1161 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1162 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1163 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1164                        enum pipe pipe, bool state);
1165 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1166 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1167 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1168 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1169 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1170 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1171                                              int *x, int *y,
1172                                              unsigned int tiling_mode,
1173                                              unsigned int bpp,
1174                                              unsigned int pitch);
1175 void intel_prepare_reset(struct drm_device *dev);
1176 void intel_finish_reset(struct drm_device *dev);
1177 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1178 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1179 void broxton_init_cdclk(struct drm_device *dev);
1180 void broxton_uninit_cdclk(struct drm_device *dev);
1181 void broxton_ddi_phy_init(struct drm_device *dev);
1182 void broxton_ddi_phy_uninit(struct drm_device *dev);
1183 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1184 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1185 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1186 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1187 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1188 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1189 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1190 void intel_dp_get_m_n(struct intel_crtc *crtc,
1191                       struct intel_crtc_state *pipe_config);
1192 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1193 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1194 void
1195 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1196                                 int dotclock);
1197 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1198                         intel_clock_t *best_clock);
1199 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1200
1201 bool intel_crtc_active(struct drm_crtc *crtc);
1202 void hsw_enable_ips(struct intel_crtc *crtc);
1203 void hsw_disable_ips(struct intel_crtc *crtc);
1204 enum intel_display_power_domain
1205 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1206 enum intel_display_power_domain
1207 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1208 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1209                                  struct intel_crtc_state *pipe_config);
1210 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1211
1212 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1213 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1214
1215 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1216                            struct drm_i915_gem_object *obj,
1217                            unsigned int plane);
1218
1219 u32 skl_plane_ctl_format(uint32_t pixel_format);
1220 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1221 u32 skl_plane_ctl_rotation(unsigned int rotation);
1222
1223 /* intel_csr.c */
1224 void intel_csr_ucode_init(struct drm_i915_private *);
1225 void intel_csr_load_program(struct drm_i915_private *);
1226 void intel_csr_ucode_fini(struct drm_i915_private *);
1227
1228 /* intel_dp.c */
1229 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1230 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1231                              struct intel_connector *intel_connector);
1232 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1233                               const struct intel_crtc_state *pipe_config);
1234 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1235 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1236 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1237 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1238 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1239 bool intel_dp_compute_config(struct intel_encoder *encoder,
1240                              struct intel_crtc_state *pipe_config);
1241 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1242 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1243                                   bool long_hpd);
1244 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1245 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1246 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1247 void intel_edp_panel_on(struct intel_dp *intel_dp);
1248 void intel_edp_panel_off(struct intel_dp *intel_dp);
1249 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1250 void intel_dp_mst_suspend(struct drm_device *dev);
1251 void intel_dp_mst_resume(struct drm_device *dev);
1252 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1253 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1254 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1255 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1256 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1257 void intel_plane_destroy(struct drm_plane *plane);
1258 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1259 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1260 void intel_edp_drrs_invalidate(struct drm_device *dev,
1261                 unsigned frontbuffer_bits);
1262 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1263 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1264                                          struct intel_digital_port *port);
1265 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1266
1267 void
1268 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1269                                        uint8_t dp_train_pat);
1270 void
1271 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1272 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1273 uint8_t
1274 intel_dp_voltage_max(struct intel_dp *intel_dp);
1275 uint8_t
1276 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1277 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1278                            uint8_t *link_bw, uint8_t *rate_select);
1279 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1280 bool
1281 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1282
1283 /* intel_dp_mst.c */
1284 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1285 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1286 /* intel_dsi.c */
1287 void intel_dsi_init(struct drm_device *dev);
1288
1289
1290 /* intel_dvo.c */
1291 void intel_dvo_init(struct drm_device *dev);
1292
1293
1294 /* legacy fbdev emulation in intel_fbdev.c */
1295 #ifdef CONFIG_DRM_FBDEV_EMULATION
1296 extern int intel_fbdev_init(struct drm_device *dev);
1297 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1298 extern void intel_fbdev_fini(struct drm_device *dev);
1299 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1300 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1301 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1302 #else
1303 static inline int intel_fbdev_init(struct drm_device *dev)
1304 {
1305         return 0;
1306 }
1307
1308 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1309 {
1310 }
1311
1312 static inline void intel_fbdev_fini(struct drm_device *dev)
1313 {
1314 }
1315
1316 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1317 {
1318 }
1319
1320 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1321 {
1322 }
1323 #endif
1324
1325 /* intel_fbc.c */
1326 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1327 void intel_fbc_update(struct drm_i915_private *dev_priv);
1328 void intel_fbc_init(struct drm_i915_private *dev_priv);
1329 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1330 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1331 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1332                           unsigned int frontbuffer_bits,
1333                           enum fb_op_origin origin);
1334 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1335                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1336 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1337
1338 /* intel_hdmi.c */
1339 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1340 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1341                                struct intel_connector *intel_connector);
1342 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1343 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1344                                struct intel_crtc_state *pipe_config);
1345
1346
1347 /* intel_lvds.c */
1348 void intel_lvds_init(struct drm_device *dev);
1349 bool intel_is_dual_link_lvds(struct drm_device *dev);
1350
1351
1352 /* intel_modes.c */
1353 int intel_connector_update_modes(struct drm_connector *connector,
1354                                  struct edid *edid);
1355 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1356 void intel_attach_force_audio_property(struct drm_connector *connector);
1357 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1358 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1359
1360
1361 /* intel_overlay.c */
1362 void intel_setup_overlay(struct drm_device *dev);
1363 void intel_cleanup_overlay(struct drm_device *dev);
1364 int intel_overlay_switch_off(struct intel_overlay *overlay);
1365 int intel_overlay_put_image(struct drm_device *dev, void *data,
1366                             struct drm_file *file_priv);
1367 int intel_overlay_attrs(struct drm_device *dev, void *data,
1368                         struct drm_file *file_priv);
1369 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1370
1371
1372 /* intel_panel.c */
1373 int intel_panel_init(struct intel_panel *panel,
1374                      struct drm_display_mode *fixed_mode,
1375                      struct drm_display_mode *downclock_mode);
1376 void intel_panel_fini(struct intel_panel *panel);
1377 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1378                             struct drm_display_mode *adjusted_mode);
1379 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1380                              struct intel_crtc_state *pipe_config,
1381                              int fitting_mode);
1382 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1383                               struct intel_crtc_state *pipe_config,
1384                               int fitting_mode);
1385 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1386                                     u32 level, u32 max);
1387 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1388 void intel_panel_enable_backlight(struct intel_connector *connector);
1389 void intel_panel_disable_backlight(struct intel_connector *connector);
1390 void intel_panel_destroy_backlight(struct drm_connector *connector);
1391 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1392 extern struct drm_display_mode *intel_find_panel_downclock(
1393                                 struct drm_device *dev,
1394                                 struct drm_display_mode *fixed_mode,
1395                                 struct drm_connector *connector);
1396 void intel_backlight_register(struct drm_device *dev);
1397 void intel_backlight_unregister(struct drm_device *dev);
1398
1399
1400 /* intel_psr.c */
1401 void intel_psr_enable(struct intel_dp *intel_dp);
1402 void intel_psr_disable(struct intel_dp *intel_dp);
1403 void intel_psr_invalidate(struct drm_device *dev,
1404                           unsigned frontbuffer_bits);
1405 void intel_psr_flush(struct drm_device *dev,
1406                      unsigned frontbuffer_bits,
1407                      enum fb_op_origin origin);
1408 void intel_psr_init(struct drm_device *dev);
1409 void intel_psr_single_frame_update(struct drm_device *dev,
1410                                    unsigned frontbuffer_bits);
1411
1412 /* intel_runtime_pm.c */
1413 int intel_power_domains_init(struct drm_i915_private *);
1414 void intel_power_domains_fini(struct drm_i915_private *);
1415 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1416 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1417 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1418 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1419 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1420
1421 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1422                                     enum intel_display_power_domain domain);
1423 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1424                                       enum intel_display_power_domain domain);
1425 void intel_display_power_get(struct drm_i915_private *dev_priv,
1426                              enum intel_display_power_domain domain);
1427 void intel_display_power_put(struct drm_i915_private *dev_priv,
1428                              enum intel_display_power_domain domain);
1429 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1430 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1431 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1432
1433 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1434
1435 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1436                              bool override, unsigned int mask);
1437 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1438                           enum dpio_channel ch, bool override);
1439
1440
1441 /* intel_pm.c */
1442 void intel_init_clock_gating(struct drm_device *dev);
1443 void intel_suspend_hw(struct drm_device *dev);
1444 int ilk_wm_max_level(const struct drm_device *dev);
1445 void intel_update_watermarks(struct drm_crtc *crtc);
1446 void intel_init_pm(struct drm_device *dev);
1447 void intel_pm_setup(struct drm_device *dev);
1448 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1449 void intel_gpu_ips_teardown(void);
1450 void intel_init_gt_powersave(struct drm_device *dev);
1451 void intel_cleanup_gt_powersave(struct drm_device *dev);
1452 void intel_enable_gt_powersave(struct drm_device *dev);
1453 void intel_disable_gt_powersave(struct drm_device *dev);
1454 void intel_suspend_gt_powersave(struct drm_device *dev);
1455 void intel_reset_gt_powersave(struct drm_device *dev);
1456 void gen6_update_ring_freq(struct drm_device *dev);
1457 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1458 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1459 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1460 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1461                     struct intel_rps_client *rps,
1462                     unsigned long submitted);
1463 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1464                                        struct drm_i915_gem_request *req);
1465 void vlv_wm_get_hw_state(struct drm_device *dev);
1466 void ilk_wm_get_hw_state(struct drm_device *dev);
1467 void skl_wm_get_hw_state(struct drm_device *dev);
1468 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1469                           struct skl_ddb_allocation *ddb /* out */);
1470 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1471
1472 /* intel_sdvo.c */
1473 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1474
1475
1476 /* intel_sprite.c */
1477 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1478 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1479                               struct drm_file *file_priv);
1480 void intel_pipe_update_start(struct intel_crtc *crtc);
1481 void intel_pipe_update_end(struct intel_crtc *crtc);
1482
1483 /* intel_tv.c */
1484 void intel_tv_init(struct drm_device *dev);
1485
1486 /* intel_atomic.c */
1487 int intel_connector_atomic_get_property(struct drm_connector *connector,
1488                                         const struct drm_connector_state *state,
1489                                         struct drm_property *property,
1490                                         uint64_t *val);
1491 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1492 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1493                                struct drm_crtc_state *state);
1494 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1495 void intel_atomic_state_clear(struct drm_atomic_state *);
1496 struct intel_shared_dpll_config *
1497 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1498
1499 static inline struct intel_crtc_state *
1500 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1501                             struct intel_crtc *crtc)
1502 {
1503         struct drm_crtc_state *crtc_state;
1504         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1505         if (IS_ERR(crtc_state))
1506                 return ERR_CAST(crtc_state);
1507
1508         return to_intel_crtc_state(crtc_state);
1509 }
1510 int intel_atomic_setup_scalers(struct drm_device *dev,
1511         struct intel_crtc *intel_crtc,
1512         struct intel_crtc_state *crtc_state);
1513
1514 /* intel_atomic_plane.c */
1515 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1516 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1517 void intel_plane_destroy_state(struct drm_plane *plane,
1518                                struct drm_plane_state *state);
1519 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1520
1521 #endif /* __INTEL_DRV_H__ */