drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  */
  51 #define _wait_for(COND, US, Wmin, Wmax) ({ \
  52         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 usleep_range(wait__, wait__ * 2);                       \
  67                 if (wait__ < (Wmax))                                    \
  68                         wait__ <<= 1;                                   \
  69         }                                                               \
  70         ret__;                                                          \
  71 })
  72
  73 #define wait_for(COND, MS)      _wait_for((COND), (MS) * 1000, 10, 1000)
  74
  75 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  76 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  78 #else
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  80 #endif
  81
  82 #define _wait_for_atomic(COND, US, ATOMIC) \
  83 ({ \
  84         int cpu, ret, timeout = (US) * 1000; \
  85         u64 base; \
  86         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  87         if (!(ATOMIC)) { \
  88                 preempt_disable(); \
  89                 cpu = smp_processor_id(); \
  90         } \
  91         base = local_clock(); \
  92         for (;;) { \
  93                 u64 now = local_clock(); \
  94                 if (!(ATOMIC)) \
  95                         preempt_enable(); \
  96                 if (COND) { \
  97                         ret = 0; \
  98                         break; \
  99                 } \
 100                 if (now - base >= timeout) { \
 101                         ret = -ETIMEDOUT; \
 102                         break; \
 103                 } \
 104                 cpu_relax(); \
 105                 if (!(ATOMIC)) { \
 106                         preempt_disable(); \
 107                         if (unlikely(cpu != smp_processor_id())) { \
 108                                 timeout -= now - base; \
 109                                 cpu = smp_processor_id(); \
 110                                 base = local_clock(); \
 111                         } \
 112                 } \
 113         } \
 114         ret; \
 115 })
 116
 117 #define wait_for_us(COND, US) \
 118 ({ \
 119         int ret__; \
 120         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 121         if ((US) > 10) \
 122                 ret__ = _wait_for((COND), (US), 10, 10); \
 123         else \
 124                 ret__ = _wait_for_atomic((COND), (US), 0); \
 125         ret__; \
 126 })
 127
 128 #define wait_for_atomic_us(COND, US) \
 129 ({ \
 130         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 131         BUILD_BUG_ON((US) > 50000); \
 132         _wait_for_atomic((COND), (US), 1); \
 133 })
 134
 135 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 136
 137 #define KHz(x) (1000 * (x))
 138 #define MHz(x) KHz(1000 * (x))
 139
 140 /*
 141  * Display related stuff
 142  */
 143
 144 /* store information about an Ixxx DVO */
 145 /* The i830->i865 use multiple DVOs with multiple i2cs */
 146 /* the i915, i945 have a single sDVO i2c bus - which is different */
 147 #define MAX_OUTPUTS 6
 148 /* maximum connectors per crtcs in the mode set */
 149
 150 /* Maximum cursor sizes */
 151 #define GEN2_CURSOR_WIDTH 64
 152 #define GEN2_CURSOR_HEIGHT 64
 153 #define MAX_CURSOR_WIDTH 256
 154 #define MAX_CURSOR_HEIGHT 256
 155
 156 #define INTEL_I2C_BUS_DVO 1
 157 #define INTEL_I2C_BUS_SDVO 2
 158
 159 /* these are outputs from the chip - integrated only
 160    external chips are via DVO or SDVO output */
 161 enum intel_output_type {
 162         INTEL_OUTPUT_UNUSED = 0,
 163         INTEL_OUTPUT_ANALOG = 1,
 164         INTEL_OUTPUT_DVO = 2,
 165         INTEL_OUTPUT_SDVO = 3,
 166         INTEL_OUTPUT_LVDS = 4,
 167         INTEL_OUTPUT_TVOUT = 5,
 168         INTEL_OUTPUT_HDMI = 6,
 169         INTEL_OUTPUT_DP = 7,
 170         INTEL_OUTPUT_EDP = 8,
 171         INTEL_OUTPUT_DSI = 9,
 172         INTEL_OUTPUT_DDI = 10,
 173         INTEL_OUTPUT_DP_MST = 11,
 174 };
 175
 176 #define INTEL_DVO_CHIP_NONE 0
 177 #define INTEL_DVO_CHIP_LVDS 1
 178 #define INTEL_DVO_CHIP_TMDS 2
 179 #define INTEL_DVO_CHIP_TVOUT 4
 180
 181 #define INTEL_DSI_VIDEO_MODE    0
 182 #define INTEL_DSI_COMMAND_MODE  1
 183
 184 struct intel_framebuffer {
 185         struct drm_framebuffer base;
 186         struct drm_i915_gem_object *obj;
 187         struct intel_rotation_info rot_info;
 188
 189         /* for each plane in the normal GTT view */
 190         struct {
 191                 unsigned int x, y;
 192         } normal[2];
 193         /* for each plane in the rotated GTT view */
 194         struct {
 195                 unsigned int x, y;
 196                 unsigned int pitch; /* pixels */
 197         } rotated[2];
 198 };
 199
 200 struct intel_fbdev {
 201         struct drm_fb_helper helper;
 202         struct intel_framebuffer *fb;
 203         struct i915_vma *vma;
 204         async_cookie_t cookie;
 205         int preferred_bpp;
 206 };
 207
 208 struct intel_encoder {
 209         struct drm_encoder base;
 210
 211         enum intel_output_type type;
 212         enum port port;
 213         unsigned int cloneable;
 214         void (*hot_plug)(struct intel_encoder *);
 215         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 216                                                       struct intel_crtc_state *,
 217                                                       struct drm_connector_state *);
 218         bool (*compute_config)(struct intel_encoder *,
 219                                struct intel_crtc_state *,
 220                                struct drm_connector_state *);
 221         void (*pre_pll_enable)(struct intel_encoder *,
 222                                const struct intel_crtc_state *,
 223                                const struct drm_connector_state *);
 224         void (*pre_enable)(struct intel_encoder *,
 225                            const struct intel_crtc_state *,
 226                            const struct drm_connector_state *);
 227         void (*enable)(struct intel_encoder *,
 228                        const struct intel_crtc_state *,
 229                        const struct drm_connector_state *);
 230         void (*disable)(struct intel_encoder *,
 231                         const struct intel_crtc_state *,
 232                         const struct drm_connector_state *);
 233         void (*post_disable)(struct intel_encoder *,
 234                              const struct intel_crtc_state *,
 235                              const struct drm_connector_state *);
 236         void (*post_pll_disable)(struct intel_encoder *,
 237                                  const struct intel_crtc_state *,
 238                                  const struct drm_connector_state *);
 239         /* Read out the current hw state of this connector, returning true if
 240          * the encoder is active. If the encoder is enabled it also set the pipe
 241          * it is connected to in the pipe parameter. */
 242         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 243         /* Reconstructs the equivalent mode flags for the current hardware
 244          * state. This must be called _after_ display->get_pipe_config has
 245          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 246          * be set correctly before calling this function. */
 247         void (*get_config)(struct intel_encoder *,
 248                            struct intel_crtc_state *pipe_config);
 249         /* Returns a mask of power domains that need to be referenced as part
 250          * of the hardware state readout code. */
 251         u64 (*get_power_domains)(struct intel_encoder *encoder);
 252         /*
 253          * Called during system suspend after all pending requests for the
 254          * encoder are flushed (for example for DP AUX transactions) and
 255          * device interrupts are disabled.
 256          */
 257         void (*suspend)(struct intel_encoder *);
 258         int crtc_mask;
 259         enum hpd_pin hpd_pin;
 260         enum intel_display_power_domain power_domain;
 261         /* for communication with audio component; protected by av_mutex */
 262         const struct drm_connector *audio_connector;
 263 };
 264
 265 struct intel_panel {
 266         struct drm_display_mode *fixed_mode;
 267         struct drm_display_mode *alt_fixed_mode;
 268         struct drm_display_mode *downclock_mode;
 269
 270         /* backlight */
 271         struct {
 272                 bool present;
 273                 u32 level;
 274                 u32 min;
 275                 u32 max;
 276                 bool enabled;
 277                 bool combination_mode;  /* gen 2/4 only */
 278                 bool active_low_pwm;
 279                 bool alternate_pwm_increment;   /* lpt+ */
 280
 281                 /* PWM chip */
 282                 bool util_pin_active_low;       /* bxt+ */
 283                 u8 controller;          /* bxt+ only */
 284                 struct pwm_device *pwm;
 285
 286                 struct backlight_device *device;
 287
 288                 /* Connector and platform specific backlight functions */
 289                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 290                 uint32_t (*get)(struct intel_connector *connector);
 291                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 292                 void (*disable)(const struct drm_connector_state *conn_state);
 293                 void (*enable)(const struct intel_crtc_state *crtc_state,
 294                                const struct drm_connector_state *conn_state);
 295                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 296                                       uint32_t hz);
 297                 void (*power)(struct intel_connector *, bool enable);
 298         } backlight;
 299 };
 300
 301 struct intel_connector {
 302         struct drm_connector base;
 303         /*
 304          * The fixed encoder this connector is connected to.
 305          */
 306         struct intel_encoder *encoder;
 307
 308         /* ACPI device id for ACPI and driver cooperation */
 309         u32 acpi_device_id;
 310
 311         /* Reads out the current hw, returning true if the connector is enabled
 312          * and active (i.e. dpms ON state). */
 313         bool (*get_hw_state)(struct intel_connector *);
 314
 315         /* Panel info for eDP and LVDS */
 316         struct intel_panel panel;
 317
 318         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 319         struct edid *edid;
 320         struct edid *detect_edid;
 321
 322         /* since POLL and HPD connectors may use the same HPD line keep the native
 323            state of connector->polled in case hotplug storm detection changes it */
 324         u8 polled;
 325
 326         void *port; /* store this opaque as its illegal to dereference it */
 327
 328         struct intel_dp *mst_port;
 329
 330         /* Work struct to schedule a uevent on link train failure */
 331         struct work_struct modeset_retry_work;
 332 };
 333
 334 struct intel_digital_connector_state {
 335         struct drm_connector_state base;
 336
 337         enum hdmi_force_audio force_audio;
 338         int broadcast_rgb;
 339 };
 340
 341 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 342
 343 struct dpll {
 344         /* given values */
 345         int n;
 346         int m1, m2;
 347         int p1, p2;
 348         /* derived values */
 349         int     dot;
 350         int     vco;
 351         int     m;
 352         int     p;
 353 };
 354
 355 struct intel_atomic_state {
 356         struct drm_atomic_state base;
 357
 358         struct {
 359                 /*
 360                  * Logical state of cdclk (used for all scaling, watermark,
 361                  * etc. calculations and checks). This is computed as if all
 362                  * enabled crtcs were active.
 363                  */
 364                 struct intel_cdclk_state logical;
 365
 366                 /*
 367                  * Actual state of cdclk, can be different from the logical
 368                  * state only when all crtc's are DPMS off.
 369                  */
 370                 struct intel_cdclk_state actual;
 371         } cdclk;
 372
 373         bool dpll_set, modeset;
 374
 375         /*
 376          * Does this transaction change the pipes that are active?  This mask
 377          * tracks which CRTC's have changed their active state at the end of
 378          * the transaction (not counting the temporary disable during modesets).
 379          * This mask should only be non-zero when intel_state->modeset is true,
 380          * but the converse is not necessarily true; simply changing a mode may
 381          * not flip the final active status of any CRTC's
 382          */
 383         unsigned int active_pipe_changes;
 384
 385         unsigned int active_crtcs;
 386         /* minimum acceptable cdclk for each pipe */
 387         int min_cdclk[I915_MAX_PIPES];
 388         /* minimum acceptable voltage level for each pipe */
 389         u8 min_voltage_level[I915_MAX_PIPES];
 390
 391         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 392
 393         /*
 394          * Current watermarks can't be trusted during hardware readout, so
 395          * don't bother calculating intermediate watermarks.
 396          */
 397         bool skip_intermediate_wm;
 398
 399         /* Gen9+ only */
 400         struct skl_wm_values wm_results;
 401
 402         struct i915_sw_fence commit_ready;
 403
 404         struct llist_node freed;
 405 };
 406
 407 struct intel_plane_state {
 408         struct drm_plane_state base;
 409         struct i915_vma *vma;
 410
 411         struct {
 412                 u32 offset;
 413                 int x, y;
 414         } main;
 415         struct {
 416                 u32 offset;
 417                 int x, y;
 418         } aux;
 419
 420         /* plane control register */
 421         u32 ctl;
 422
 423         /* plane color control register */
 424         u32 color_ctl;
 425
 426         /*
 427          * scaler_id
 428          *    = -1 : not using a scaler
 429          *    >=  0 : using a scalers
 430          *
 431          * plane requiring a scaler:
 432          *   - During check_plane, its bit is set in
 433          *     crtc_state->scaler_state.scaler_users by calling helper function
 434          *     update_scaler_plane.
 435          *   - scaler_id indicates the scaler it got assigned.
 436          *
 437          * plane doesn't require a scaler:
 438          *   - this can happen when scaling is no more required or plane simply
 439          *     got disabled.
 440          *   - During check_plane, corresponding bit is reset in
 441          *     crtc_state->scaler_state.scaler_users by calling helper function
 442          *     update_scaler_plane.
 443          */
 444         int scaler_id;
 445
 446         struct drm_intel_sprite_colorkey ckey;
 447 };
 448
 449 struct intel_initial_plane_config {
 450         struct intel_framebuffer *fb;
 451         unsigned int tiling;
 452         int size;
 453         u32 base;
 454 };
 455
 456 #define SKL_MIN_SRC_W 8
 457 #define SKL_MAX_SRC_W 4096
 458 #define SKL_MIN_SRC_H 8
 459 #define SKL_MAX_SRC_H 4096
 460 #define SKL_MIN_DST_W 8
 461 #define SKL_MAX_DST_W 4096
 462 #define SKL_MIN_DST_H 8
 463 #define SKL_MAX_DST_H 4096
 464
 465 struct intel_scaler {
 466         int in_use;
 467         uint32_t mode;
 468 };
 469
 470 struct intel_crtc_scaler_state {
 471 #define SKL_NUM_SCALERS 2
 472         struct intel_scaler scalers[SKL_NUM_SCALERS];
 473
 474         /*
 475          * scaler_users: keeps track of users requesting scalers on this crtc.
 476          *
 477          *     If a bit is set, a user is using a scaler.
 478          *     Here user can be a plane or crtc as defined below:
 479          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 480          *       bit 31    - crtc
 481          *
 482          * Instead of creating a new index to cover planes and crtc, using
 483          * existing drm_plane_index for planes which is well less than 31
 484          * planes and bit 31 for crtc. This should be fine to cover all
 485          * our platforms.
 486          *
 487          * intel_atomic_setup_scalers will setup available scalers to users
 488          * requesting scalers. It will gracefully fail if request exceeds
 489          * avilability.
 490          */
 491 #define SKL_CRTC_INDEX 31
 492         unsigned scaler_users;
 493
 494         /* scaler used by crtc for panel fitting purpose */
 495         int scaler_id;
 496 };
 497
 498 /* drm_mode->private_flags */
 499 #define I915_MODE_FLAG_INHERITED 1
 500 /* Flag to get scanline using frame time stamps */
 501 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 502
 503 struct intel_pipe_wm {
 504         struct intel_wm_level wm[5];
 505         uint32_t linetime;
 506         bool fbc_wm_enabled;
 507         bool pipe_enabled;
 508         bool sprites_enabled;
 509         bool sprites_scaled;
 510 };
 511
 512 struct skl_plane_wm {
 513         struct skl_wm_level wm[8];
 514         struct skl_wm_level trans_wm;
 515 };
 516
 517 struct skl_pipe_wm {
 518         struct skl_plane_wm planes[I915_MAX_PLANES];
 519         uint32_t linetime;
 520 };
 521
 522 enum vlv_wm_level {
 523         VLV_WM_LEVEL_PM2,
 524         VLV_WM_LEVEL_PM5,
 525         VLV_WM_LEVEL_DDR_DVFS,
 526         NUM_VLV_WM_LEVELS,
 527 };
 528
 529 struct vlv_wm_state {
 530         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 531         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 532         uint8_t num_levels;
 533         bool cxsr;
 534 };
 535
 536 struct vlv_fifo_state {
 537         u16 plane[I915_MAX_PLANES];
 538 };
 539
 540 enum g4x_wm_level {
 541         G4X_WM_LEVEL_NORMAL,
 542         G4X_WM_LEVEL_SR,
 543         G4X_WM_LEVEL_HPLL,
 544         NUM_G4X_WM_LEVELS,
 545 };
 546
 547 struct g4x_wm_state {
 548         struct g4x_pipe_wm wm;
 549         struct g4x_sr_wm sr;
 550         struct g4x_sr_wm hpll;
 551         bool cxsr;
 552         bool hpll_en;
 553         bool fbc_en;
 554 };
 555
 556 struct intel_crtc_wm_state {
 557         union {
 558                 struct {
 559                         /*
 560                          * Intermediate watermarks; these can be
 561                          * programmed immediately since they satisfy
 562                          * both the current configuration we're
 563                          * switching away from and the new
 564                          * configuration we're switching to.
 565                          */
 566                         struct intel_pipe_wm intermediate;
 567
 568                         /*
 569                          * Optimal watermarks, programmed post-vblank
 570                          * when this state is committed.
 571                          */
 572                         struct intel_pipe_wm optimal;
 573                 } ilk;
 574
 575                 struct {
 576                         /* gen9+ only needs 1-step wm programming */
 577                         struct skl_pipe_wm optimal;
 578                         struct skl_ddb_entry ddb;
 579                 } skl;
 580
 581                 struct {
 582                         /* "raw" watermarks (not inverted) */
 583                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 584                         /* intermediate watermarks (inverted) */
 585                         struct vlv_wm_state intermediate;
 586                         /* optimal watermarks (inverted) */
 587                         struct vlv_wm_state optimal;
 588                         /* display FIFO split */
 589                         struct vlv_fifo_state fifo_state;
 590                 } vlv;
 591
 592                 struct {
 593                         /* "raw" watermarks */
 594                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 595                         /* intermediate watermarks */
 596                         struct g4x_wm_state intermediate;
 597                         /* optimal watermarks */
 598                         struct g4x_wm_state optimal;
 599                 } g4x;
 600         };
 601
 602         /*
 603          * Platforms with two-step watermark programming will need to
 604          * update watermark programming post-vblank to switch from the
 605          * safe intermediate watermarks to the optimal final
 606          * watermarks.
 607          */
 608         bool need_postvbl_update;
 609 };
 610
 611 struct intel_crtc_state {
 612         struct drm_crtc_state base;
 613
 614         /**
 615          * quirks - bitfield with hw state readout quirks
 616          *
 617          * For various reasons the hw state readout code might not be able to
 618          * completely faithfully read out the current state. These cases are
 619          * tracked with quirk flags so that fastboot and state checker can act
 620          * accordingly.
 621          */
 622 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 623         unsigned long quirks;
 624
 625         unsigned fb_bits; /* framebuffers to flip */
 626         bool update_pipe; /* can a fast modeset be performed? */
 627         bool disable_cxsr;
 628         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 629         bool fb_changed; /* fb on any of the planes is changed */
 630         bool fifo_changed; /* FIFO split is changed */
 631
 632         /* Pipe source size (ie. panel fitter input size)
 633          * All planes will be positioned inside this space,
 634          * and get clipped at the edges. */
 635         int pipe_src_w, pipe_src_h;
 636
 637         /*
 638          * Pipe pixel rate, adjusted for
 639          * panel fitter/pipe scaler downscaling.
 640          */
 641         unsigned int pixel_rate;
 642
 643         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 644          * between pch encoders and cpu encoders. */
 645         bool has_pch_encoder;
 646
 647         /* Are we sending infoframes on the attached port */
 648         bool has_infoframe;
 649
 650         /* CPU Transcoder for the pipe. Currently this can only differ from the
 651          * pipe on Haswell and later (where we have a special eDP transcoder)
 652          * and Broxton (where we have special DSI transcoders). */
 653         enum transcoder cpu_transcoder;
 654
 655         /*
 656          * Use reduced/limited/broadcast rbg range, compressing from the full
 657          * range fed into the crtcs.
 658          */
 659         bool limited_color_range;
 660
 661         /* Bitmask of encoder types (enum intel_output_type)
 662          * driven by the pipe.
 663          */
 664         unsigned int output_types;
 665
 666         /* Whether we should send NULL infoframes. Required for audio. */
 667         bool has_hdmi_sink;
 668
 669         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 670          * has_dp_encoder is set. */
 671         bool has_audio;
 672
 673         /*
 674          * Enable dithering, used when the selected pipe bpp doesn't match the
 675          * plane bpp.
 676          */
 677         bool dither;
 678
 679         /*
 680          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 681          * compliance video pattern tests.
 682          * Disable dither only if it is a compliance test request for
 683          * 18bpp.
 684          */
 685         bool dither_force_disable;
 686
 687         /* Controls for the clock computation, to override various stages. */
 688         bool clock_set;
 689
 690         /* SDVO TV has a bunch of special case. To make multifunction encoders
 691          * work correctly, we need to track this at runtime.*/
 692         bool sdvo_tv_clock;
 693
 694         /*
 695          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 696          * required. This is set in the 2nd loop of calling encoder's
 697          * ->compute_config if the first pick doesn't work out.
 698          */
 699         bool bw_constrained;
 700
 701         /* Settings for the intel dpll used on pretty much everything but
 702          * haswell. */
 703         struct dpll dpll;
 704
 705         /* Selected dpll when shared or NULL. */
 706         struct intel_shared_dpll *shared_dpll;
 707
 708         /* Actual register state of the dpll, for shared dpll cross-checking. */
 709         struct intel_dpll_hw_state dpll_hw_state;
 710
 711         /* DSI PLL registers */
 712         struct {
 713                 u32 ctrl, div;
 714         } dsi_pll;
 715
 716         int pipe_bpp;
 717         struct intel_link_m_n dp_m_n;
 718
 719         /* m2_n2 for eDP downclock */
 720         struct intel_link_m_n dp_m2_n2;
 721         bool has_drrs;
 722
 723         bool has_psr;
 724         bool has_psr2;
 725
 726         /*
 727          * Frequence the dpll for the port should run at. Differs from the
 728          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 729          * already multiplied by pixel_multiplier.
 730          */
 731         int port_clock;
 732
 733         /* Used by SDVO (and if we ever fix it, HDMI). */
 734         unsigned pixel_multiplier;
 735
 736         uint8_t lane_count;
 737
 738         /*
 739          * Used by platforms having DP/HDMI PHY with programmable lane
 740          * latency optimization.
 741          */
 742         uint8_t lane_lat_optim_mask;
 743
 744         /* minimum acceptable voltage level */
 745         u8 min_voltage_level;
 746
 747         /* Panel fitter controls for gen2-gen4 + VLV */
 748         struct {
 749                 u32 control;
 750                 u32 pgm_ratios;
 751                 u32 lvds_border_bits;
 752         } gmch_pfit;
 753
 754         /* Panel fitter placement and size for Ironlake+ */
 755         struct {
 756                 u32 pos;
 757                 u32 size;
 758                 bool enabled;
 759                 bool force_thru;
 760         } pch_pfit;
 761
 762         /* FDI configuration, only valid if has_pch_encoder is set. */
 763         int fdi_lanes;
 764         struct intel_link_m_n fdi_m_n;
 765
 766         bool ips_enabled;
 767         bool ips_force_disable;
 768
 769         bool enable_fbc;
 770
 771         bool double_wide;
 772
 773         int pbn;
 774
 775         struct intel_crtc_scaler_state scaler_state;
 776
 777         /* w/a for waiting 2 vblanks during crtc enable */
 778         enum pipe hsw_workaround_pipe;
 779
 780         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 781         bool disable_lp_wm;
 782
 783         struct intel_crtc_wm_state wm;
 784
 785         /* Gamma mode programmed on the pipe */
 786         uint32_t gamma_mode;
 787
 788         /* bitmask of visible planes (enum plane_id) */
 789         u8 active_planes;
 790
 791         /* HDMI scrambling status */
 792         bool hdmi_scrambling;
 793
 794         /* HDMI High TMDS char rate ratio */
 795         bool hdmi_high_tmds_clock_ratio;
 796
 797         /* output format is YCBCR 4:2:0 */
 798         bool ycbcr420;
 799 };
 800
 801 struct intel_crtc {
 802         struct drm_crtc base;
 803         enum pipe pipe;
 804         /*
 805          * Whether the crtc and the connected output pipeline is active. Implies
 806          * that crtc->enabled is set, i.e. the current mode configuration has
 807          * some outputs connected to this crtc.
 808          */
 809         bool active;
 810         u8 plane_ids_mask;
 811         unsigned long long enabled_power_domains;
 812         struct intel_overlay *overlay;
 813
 814         struct intel_crtc_state *config;
 815
 816         /* global reset count when the last flip was submitted */
 817         unsigned int reset_count;
 818
 819         /* Access to these should be protected by dev_priv->irq_lock. */
 820         bool cpu_fifo_underrun_disabled;
 821         bool pch_fifo_underrun_disabled;
 822
 823         /* per-pipe watermark state */
 824         struct {
 825                 /* watermarks currently being used  */
 826                 union {
 827                         struct intel_pipe_wm ilk;
 828                         struct vlv_wm_state vlv;
 829                         struct g4x_wm_state g4x;
 830                 } active;
 831         } wm;
 832
 833         int scanline_offset;
 834
 835         struct {
 836                 unsigned start_vbl_count;
 837                 ktime_t start_vbl_time;
 838                 int min_vbl, max_vbl;
 839                 int scanline_start;
 840         } debug;
 841
 842         /* scalers available on this crtc */
 843         int num_scalers;
 844 };
 845
 846 struct intel_plane {
 847         struct drm_plane base;
 848         enum i9xx_plane_id i9xx_plane;
 849         enum plane_id id;
 850         enum pipe pipe;
 851         bool can_scale;
 852         int max_downscale;
 853         uint32_t frontbuffer_bit;
 854
 855         struct {
 856                 u32 base, cntl, size;
 857         } cursor;
 858
 859         /*
 860          * NOTE: Do not place new plane state fields here (e.g., when adding
 861          * new plane properties).  New runtime state should now be placed in
 862          * the intel_plane_state structure and accessed via plane_state.
 863          */
 864
 865         void (*update_plane)(struct intel_plane *plane,
 866                              const struct intel_crtc_state *crtc_state,
 867                              const struct intel_plane_state *plane_state);
 868         void (*disable_plane)(struct intel_plane *plane,
 869                               struct intel_crtc *crtc);
 870         bool (*get_hw_state)(struct intel_plane *plane);
 871         int (*check_plane)(struct intel_plane *plane,
 872                            struct intel_crtc_state *crtc_state,
 873                            struct intel_plane_state *state);
 874 };
 875
 876 struct intel_watermark_params {
 877         u16 fifo_size;
 878         u16 max_wm;
 879         u8 default_wm;
 880         u8 guard_size;
 881         u8 cacheline_size;
 882 };
 883
 884 struct cxsr_latency {
 885         bool is_desktop : 1;
 886         bool is_ddr3 : 1;
 887         u16 fsb_freq;
 888         u16 mem_freq;
 889         u16 display_sr;
 890         u16 display_hpll_disable;
 891         u16 cursor_sr;
 892         u16 cursor_hpll_disable;
 893 };
 894
 895 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 896 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 897 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 898 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 899 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 900 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 901 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 902 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 903 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 904
 905 struct intel_hdmi {
 906         i915_reg_t hdmi_reg;
 907         int ddc_bus;
 908         struct {
 909                 enum drm_dp_dual_mode_type type;
 910                 int max_tmds_clock;
 911         } dp_dual_mode;
 912         bool has_hdmi_sink;
 913         bool has_audio;
 914         bool rgb_quant_range_selectable;
 915         struct intel_connector *attached_connector;
 916 };
 917
 918 struct intel_dp_mst_encoder;
 919 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 920
 921 /*
 922  * enum link_m_n_set:
 923  *      When platform provides two set of M_N registers for dp, we can
 924  *      program them and switch between them incase of DRRS.
 925  *      But When only one such register is provided, we have to program the
 926  *      required divider value on that registers itself based on the DRRS state.
 927  *
 928  * M1_N1        : Program dp_m_n on M1_N1 registers
 929  *                        dp_m2_n2 on M2_N2 registers (If supported)
 930  *
 931  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 932  *                        M2_N2 registers are not supported
 933  */
 934
 935 enum link_m_n_set {
 936         /* Sets the m1_n1 and m2_n2 */
 937         M1_N1 = 0,
 938         M2_N2
 939 };
 940
 941 struct intel_dp_compliance_data {
 942         unsigned long edid;
 943         uint8_t video_pattern;
 944         uint16_t hdisplay, vdisplay;
 945         uint8_t bpc;
 946 };
 947
 948 struct intel_dp_compliance {
 949         unsigned long test_type;
 950         struct intel_dp_compliance_data test_data;
 951         bool test_active;
 952         int test_link_rate;
 953         u8 test_lane_count;
 954 };
 955
 956 struct intel_dp {
 957         i915_reg_t output_reg;
 958         i915_reg_t aux_ch_ctl_reg;
 959         i915_reg_t aux_ch_data_reg[5];
 960         uint32_t DP;
 961         int link_rate;
 962         uint8_t lane_count;
 963         uint8_t sink_count;
 964         bool link_mst;
 965         bool has_audio;
 966         bool detect_done;
 967         bool channel_eq_status;
 968         bool reset_link_params;
 969         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 970         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 971         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 972         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 973         /* source rates */
 974         int num_source_rates;
 975         const int *source_rates;
 976         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 977         int num_sink_rates;
 978         int sink_rates[DP_MAX_SUPPORTED_RATES];
 979         bool use_rate_select;
 980         /* intersection of source and sink rates */
 981         int num_common_rates;
 982         int common_rates[DP_MAX_SUPPORTED_RATES];
 983         /* Max lane count for the current link */
 984         int max_link_lane_count;
 985         /* Max rate for the current link */
 986         int max_link_rate;
 987         /* sink or branch descriptor */
 988         struct drm_dp_desc desc;
 989         struct drm_dp_aux aux;
 990         enum intel_display_power_domain aux_power_domain;
 991         uint8_t train_set[4];
 992         int panel_power_up_delay;
 993         int panel_power_down_delay;
 994         int panel_power_cycle_delay;
 995         int backlight_on_delay;
 996         int backlight_off_delay;
 997         struct delayed_work panel_vdd_work;
 998         bool want_panel_vdd;
 999         unsigned long last_power_on;
1000         unsigned long last_backlight_off;
1001         ktime_t panel_power_off_time;
1002
1003         struct notifier_block edp_notifier;
1004
1005         /*
1006          * Pipe whose power sequencer is currently locked into
1007          * this port. Only relevant on VLV/CHV.
1008          */
1009         enum pipe pps_pipe;
1010         /*
1011          * Pipe currently driving the port. Used for preventing
1012          * the use of the PPS for any pipe currentrly driving
1013          * external DP as that will mess things up on VLV.
1014          */
1015         enum pipe active_pipe;
1016         /*
1017          * Set if the sequencer may be reset due to a power transition,
1018          * requiring a reinitialization. Only relevant on BXT.
1019          */
1020         bool pps_reset;
1021         struct edp_power_seq pps_delays;
1022
1023         bool can_mst; /* this port supports mst */
1024         bool is_mst;
1025         int active_mst_links;
1026         /* connector directly attached - won't be use for modeset in mst world */
1027         struct intel_connector *attached_connector;
1028
1029         /* mst connector list */
1030         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1031         struct drm_dp_mst_topology_mgr mst_mgr;
1032
1033         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1034         /*
1035          * This function returns the value we have to program the AUX_CTL
1036          * register with to kick off an AUX transaction.
1037          */
1038         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1039                                      bool has_aux_irq,
1040                                      int send_bytes,
1041                                      uint32_t aux_clock_divider);
1042
1043         /* This is called before a link training is starterd */
1044         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1045
1046         /* Displayport compliance testing */
1047         struct intel_dp_compliance compliance;
1048 };
1049
1050 struct intel_lspcon {
1051         bool active;
1052         enum drm_lspcon_mode mode;
1053 };
1054
1055 struct intel_digital_port {
1056         struct intel_encoder base;
1057         u32 saved_port_bits;
1058         struct intel_dp dp;
1059         struct intel_hdmi hdmi;
1060         struct intel_lspcon lspcon;
1061         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1062         bool release_cl2_override;
1063         uint8_t max_lanes;
1064         enum intel_display_power_domain ddi_io_power_domain;
1065
1066         void (*write_infoframe)(struct drm_encoder *encoder,
1067                                 const struct intel_crtc_state *crtc_state,
1068                                 unsigned int type,
1069                                 const void *frame, ssize_t len);
1070         void (*set_infoframes)(struct drm_encoder *encoder,
1071                                bool enable,
1072                                const struct intel_crtc_state *crtc_state,
1073                                const struct drm_connector_state *conn_state);
1074         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1075                                   const struct intel_crtc_state *pipe_config);
1076 };
1077
1078 struct intel_dp_mst_encoder {
1079         struct intel_encoder base;
1080         enum pipe pipe;
1081         struct intel_digital_port *primary;
1082         struct intel_connector *connector;
1083 };
1084
1085 static inline enum dpio_channel
1086 vlv_dport_to_channel(struct intel_digital_port *dport)
1087 {
1088         switch (dport->base.port) {
1089         case PORT_B:
1090         case PORT_D:
1091                 return DPIO_CH0;
1092         case PORT_C:
1093                 return DPIO_CH1;
1094         default:
1095                 BUG();
1096         }
1097 }
1098
1099 static inline enum dpio_phy
1100 vlv_dport_to_phy(struct intel_digital_port *dport)
1101 {
1102         switch (dport->base.port) {
1103         case PORT_B:
1104         case PORT_C:
1105                 return DPIO_PHY0;
1106         case PORT_D:
1107                 return DPIO_PHY1;
1108         default:
1109                 BUG();
1110         }
1111 }
1112
1113 static inline enum dpio_channel
1114 vlv_pipe_to_channel(enum pipe pipe)
1115 {
1116         switch (pipe) {
1117         case PIPE_A:
1118         case PIPE_C:
1119                 return DPIO_CH0;
1120         case PIPE_B:
1121                 return DPIO_CH1;
1122         default:
1123                 BUG();
1124         }
1125 }
1126
1127 static inline struct intel_crtc *
1128 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1129 {
1130         return dev_priv->pipe_to_crtc_mapping[pipe];
1131 }
1132
1133 static inline struct intel_crtc *
1134 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1135 {
1136         return dev_priv->plane_to_crtc_mapping[plane];
1137 }
1138
1139 struct intel_load_detect_pipe {
1140         struct drm_atomic_state *restore_state;
1141 };
1142
1143 static inline struct intel_encoder *
1144 intel_attached_encoder(struct drm_connector *connector)
1145 {
1146         return to_intel_connector(connector)->encoder;
1147 }
1148
1149 static inline struct intel_digital_port *
1150 enc_to_dig_port(struct drm_encoder *encoder)
1151 {
1152         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1153
1154         switch (intel_encoder->type) {
1155         case INTEL_OUTPUT_DDI:
1156                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1157         case INTEL_OUTPUT_DP:
1158         case INTEL_OUTPUT_EDP:
1159         case INTEL_OUTPUT_HDMI:
1160                 return container_of(encoder, struct intel_digital_port,
1161                                     base.base);
1162         default:
1163                 return NULL;
1164         }
1165 }
1166
1167 static inline struct intel_dp_mst_encoder *
1168 enc_to_mst(struct drm_encoder *encoder)
1169 {
1170         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1171 }
1172
1173 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1174 {
1175         return &enc_to_dig_port(encoder)->dp;
1176 }
1177
1178 static inline struct intel_digital_port *
1179 dp_to_dig_port(struct intel_dp *intel_dp)
1180 {
1181         return container_of(intel_dp, struct intel_digital_port, dp);
1182 }
1183
1184 static inline struct intel_lspcon *
1185 dp_to_lspcon(struct intel_dp *intel_dp)
1186 {
1187         return &dp_to_dig_port(intel_dp)->lspcon;
1188 }
1189
1190 static inline struct intel_digital_port *
1191 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1192 {
1193         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1194 }
1195
1196 static inline struct intel_plane_state *
1197 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1198                                  struct intel_plane *plane)
1199 {
1200         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1201                                                                    &plane->base));
1202 }
1203
1204 static inline struct intel_crtc_state *
1205 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1206                                 struct intel_crtc *crtc)
1207 {
1208         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1209                                                                  &crtc->base));
1210 }
1211
1212 static inline struct intel_crtc_state *
1213 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1214                                 struct intel_crtc *crtc)
1215 {
1216         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1217                                                                  &crtc->base));
1218 }
1219
1220 /* intel_fifo_underrun.c */
1221 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1222                                            enum pipe pipe, bool enable);
1223 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1224                                            enum pipe pch_transcoder,
1225                                            bool enable);
1226 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1227                                          enum pipe pipe);
1228 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1229                                          enum pipe pch_transcoder);
1230 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1231 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1232
1233 /* i915_irq.c */
1234 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1235 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1236 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1237 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1238 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1239 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1240 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1241
1242 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1243                                             u32 mask)
1244 {
1245         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1246 }
1247
1248 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1249 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1250 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1251 {
1252         /*
1253          * We only use drm_irq_uninstall() at unload and VT switch, so
1254          * this is the only thing we need to check.
1255          */
1256         return dev_priv->runtime_pm.irqs_enabled;
1257 }
1258
1259 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1260 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1261                                      u8 pipe_mask);
1262 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1263                                      u8 pipe_mask);
1264 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1265 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1266 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1267
1268 /* intel_crt.c */
1269 void intel_crt_init(struct drm_i915_private *dev_priv);
1270 void intel_crt_reset(struct drm_encoder *encoder);
1271
1272 /* intel_ddi.c */
1273 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1274                                 const struct intel_crtc_state *old_crtc_state,
1275                                 const struct drm_connector_state *old_conn_state);
1276 void hsw_fdi_link_train(struct intel_crtc *crtc,
1277                         const struct intel_crtc_state *crtc_state);
1278 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1279 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1280 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1281 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1282                                        enum transcoder cpu_transcoder);
1283 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1284 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1285 struct intel_encoder *
1286 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1287 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1288 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1289 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1290 void intel_ddi_get_config(struct intel_encoder *encoder,
1291                           struct intel_crtc_state *pipe_config);
1292
1293 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1294                                     bool state);
1295 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1296                                          struct intel_crtc_state *crtc_state);
1297 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1298 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1299 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1300
1301 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1302                                    int plane, unsigned int height);
1303
1304 /* intel_audio.c */
1305 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1306 void intel_audio_codec_enable(struct intel_encoder *encoder,
1307                               const struct intel_crtc_state *crtc_state,
1308                               const struct drm_connector_state *conn_state);
1309 void intel_audio_codec_disable(struct intel_encoder *encoder,
1310                                const struct intel_crtc_state *old_crtc_state,
1311                                const struct drm_connector_state *old_conn_state);
1312 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1313 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1314 void intel_audio_init(struct drm_i915_private *dev_priv);
1315 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1316
1317 /* intel_cdclk.c */
1318 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1319 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1320 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1321 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1322 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1323 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1324 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1326 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1327 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1328 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1329 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1330                                const struct intel_cdclk_state *b);
1331 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1332                          const struct intel_cdclk_state *b);
1333 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1334                      const struct intel_cdclk_state *cdclk_state);
1335 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1336                             const char *context);
1337
1338 /* intel_display.c */
1339 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1340 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1341 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1342 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1343 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1344 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1345                       const char *name, u32 reg, int ref_freq);
1346 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1347                            const char *name, u32 reg);
1348 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1349 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1350 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1351 unsigned int intel_fb_xy_to_linear(int x, int y,
1352                                    const struct intel_plane_state *state,
1353                                    int plane);
1354 void intel_add_fb_offsets(int *x, int *y,
1355                           const struct intel_plane_state *state, int plane);
1356 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1357 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1358 void intel_mark_busy(struct drm_i915_private *dev_priv);
1359 void intel_mark_idle(struct drm_i915_private *dev_priv);
1360 int intel_display_suspend(struct drm_device *dev);
1361 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1362 void intel_encoder_destroy(struct drm_encoder *encoder);
1363 int intel_connector_init(struct intel_connector *);
1364 struct intel_connector *intel_connector_alloc(void);
1365 void intel_connector_free(struct intel_connector *connector);
1366 bool intel_connector_get_hw_state(struct intel_connector *connector);
1367 void intel_connector_attach_encoder(struct intel_connector *connector,
1368                                     struct intel_encoder *encoder);
1369 struct drm_display_mode *
1370 intel_encoder_current_mode(struct intel_encoder *encoder);
1371
1372 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1373 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1374                                 struct drm_file *file_priv);
1375 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1376                                              enum pipe pipe);
1377 static inline bool
1378 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1379                     enum intel_output_type type)
1380 {
1381         return crtc_state->output_types & (1 << type);
1382 }
1383 static inline bool
1384 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1385 {
1386         return crtc_state->output_types &
1387                 ((1 << INTEL_OUTPUT_DP) |
1388                  (1 << INTEL_OUTPUT_DP_MST) |
1389                  (1 << INTEL_OUTPUT_EDP));
1390 }
1391 static inline void
1392 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1393 {
1394         drm_wait_one_vblank(&dev_priv->drm, pipe);
1395 }
1396 static inline void
1397 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1398 {
1399         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1400
1401         if (crtc->active)
1402                 intel_wait_for_vblank(dev_priv, pipe);
1403 }
1404
1405 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1406
1407 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1408 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1409                          struct intel_digital_port *dport,
1410                          unsigned int expected_mask);
1411 int intel_get_load_detect_pipe(struct drm_connector *connector,
1412                                const struct drm_display_mode *mode,
1413                                struct intel_load_detect_pipe *old,
1414                                struct drm_modeset_acquire_ctx *ctx);
1415 void intel_release_load_detect_pipe(struct drm_connector *connector,
1416                                     struct intel_load_detect_pipe *old,
1417                                     struct drm_modeset_acquire_ctx *ctx);
1418 struct i915_vma *
1419 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1420 void intel_unpin_fb_vma(struct i915_vma *vma);
1421 struct drm_framebuffer *
1422 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1423                          struct drm_mode_fb_cmd2 *mode_cmd);
1424 int intel_prepare_plane_fb(struct drm_plane *plane,
1425                            struct drm_plane_state *new_state);
1426 void intel_cleanup_plane_fb(struct drm_plane *plane,
1427                             struct drm_plane_state *old_state);
1428 int intel_plane_atomic_get_property(struct drm_plane *plane,
1429                                     const struct drm_plane_state *state,
1430                                     struct drm_property *property,
1431                                     uint64_t *val);
1432 int intel_plane_atomic_set_property(struct drm_plane *plane,
1433                                     struct drm_plane_state *state,
1434                                     struct drm_property *property,
1435                                     uint64_t val);
1436 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1437                                     struct drm_crtc_state *crtc_state,
1438                                     const struct intel_plane_state *old_plane_state,
1439                                     struct drm_plane_state *plane_state);
1440
1441 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1442                                     enum pipe pipe);
1443
1444 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1445                      const struct dpll *dpll);
1446 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1447 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1448
1449 /* modesetting asserts */
1450 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1451                            enum pipe pipe);
1452 void assert_pll(struct drm_i915_private *dev_priv,
1453                 enum pipe pipe, bool state);
1454 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1455 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1456 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1457 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1458 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1459 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1460                        enum pipe pipe, bool state);
1461 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1462 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1463 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1464 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1465 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1466 u32 intel_compute_tile_offset(int *x, int *y,
1467                               const struct intel_plane_state *state, int plane);
1468 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1469 void intel_finish_reset(struct drm_i915_private *dev_priv);
1470 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1471 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1472 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1473 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1474 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1475 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1476 unsigned int skl_cdclk_get_vco(unsigned int freq);
1477 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1478 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1479 void intel_dp_get_m_n(struct intel_crtc *crtc,
1480                       struct intel_crtc_state *pipe_config);
1481 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1482 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1483 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1484                         struct dpll *best_clock);
1485 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1486
1487 bool intel_crtc_active(struct intel_crtc *crtc);
1488 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1489 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1490 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1491 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1492 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1493                                  struct intel_crtc_state *pipe_config);
1494
1495 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1496 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1497
1498 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1499 {
1500         return i915_ggtt_offset(state->vma);
1501 }
1502
1503 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1504                         const struct intel_plane_state *plane_state);
1505 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1506                   const struct intel_plane_state *plane_state);
1507 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1508                      unsigned int rotation);
1509 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1510                             struct intel_plane_state *plane_state);
1511 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1512
1513 /* intel_csr.c */
1514 void intel_csr_ucode_init(struct drm_i915_private *);
1515 void intel_csr_load_program(struct drm_i915_private *);
1516 void intel_csr_ucode_fini(struct drm_i915_private *);
1517 void intel_csr_ucode_suspend(struct drm_i915_private *);
1518 void intel_csr_ucode_resume(struct drm_i915_private *);
1519
1520 /* intel_dp.c */
1521 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1522                    enum port port);
1523 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1524                              struct intel_connector *intel_connector);
1525 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1526                               int link_rate, uint8_t lane_count,
1527                               bool link_mst);
1528 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1529                                             int link_rate, uint8_t lane_count);
1530 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1531 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1532 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1533 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1534 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1535 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1536 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1537                       struct intel_crtc_state *crtc_state, u8 *crc);
1538 bool intel_dp_compute_config(struct intel_encoder *encoder,
1539                              struct intel_crtc_state *pipe_config,
1540                              struct drm_connector_state *conn_state);
1541 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1542 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1543 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1544                                   bool long_hpd);
1545 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1546                             const struct drm_connector_state *conn_state);
1547 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1548 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1549 void intel_edp_panel_on(struct intel_dp *intel_dp);
1550 void intel_edp_panel_off(struct intel_dp *intel_dp);
1551 void intel_dp_mst_suspend(struct drm_device *dev);
1552 void intel_dp_mst_resume(struct drm_device *dev);
1553 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1554 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1555 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1556 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1557 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1558 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1559 void intel_plane_destroy(struct drm_plane *plane);
1560 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1561                            const struct intel_crtc_state *crtc_state);
1562 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1563                             const struct intel_crtc_state *crtc_state);
1564 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1565                                unsigned int frontbuffer_bits);
1566 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1567                           unsigned int frontbuffer_bits);
1568
1569 void
1570 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1571                                        uint8_t dp_train_pat);
1572 void
1573 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1574 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1575 uint8_t
1576 intel_dp_voltage_max(struct intel_dp *intel_dp);
1577 uint8_t
1578 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1579 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1580                            uint8_t *link_bw, uint8_t *rate_select);
1581 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1582 bool
1583 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1584
1585 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1586 {
1587         return ~((1 << lane_count) - 1) & 0xf;
1588 }
1589
1590 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1591 int intel_dp_link_required(int pixel_clock, int bpp);
1592 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1593 bool intel_digital_port_connected(struct intel_encoder *encoder);
1594
1595 /* intel_dp_aux_backlight.c */
1596 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1597
1598 /* intel_dp_mst.c */
1599 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1600 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1601 /* intel_dsi.c */
1602 void intel_dsi_init(struct drm_i915_private *dev_priv);
1603
1604 /* intel_dsi_dcs_backlight.c */
1605 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1606
1607 /* intel_dvo.c */
1608 void intel_dvo_init(struct drm_i915_private *dev_priv);
1609 /* intel_hotplug.c */
1610 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1611
1612
1613 /* legacy fbdev emulation in intel_fbdev.c */
1614 #ifdef CONFIG_DRM_FBDEV_EMULATION
1615 extern int intel_fbdev_init(struct drm_device *dev);
1616 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1617 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1618 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1619 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1620 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1621 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1622 #else
1623 static inline int intel_fbdev_init(struct drm_device *dev)
1624 {
1625         return 0;
1626 }
1627
1628 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1629 {
1630 }
1631
1632 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1633 {
1634 }
1635
1636 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1637 {
1638 }
1639
1640 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1641 {
1642 }
1643
1644 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1645 {
1646 }
1647
1648 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1649 {
1650 }
1651 #endif
1652
1653 /* intel_fbc.c */
1654 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1655                            struct intel_atomic_state *state);
1656 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1657 void intel_fbc_pre_update(struct intel_crtc *crtc,
1658                           struct intel_crtc_state *crtc_state,
1659                           struct intel_plane_state *plane_state);
1660 void intel_fbc_post_update(struct intel_crtc *crtc);
1661 void intel_fbc_init(struct drm_i915_private *dev_priv);
1662 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1663 void intel_fbc_enable(struct intel_crtc *crtc,
1664                       struct intel_crtc_state *crtc_state,
1665                       struct intel_plane_state *plane_state);
1666 void intel_fbc_disable(struct intel_crtc *crtc);
1667 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1668 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1669                           unsigned int frontbuffer_bits,
1670                           enum fb_op_origin origin);
1671 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1672                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1673 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1674 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1675
1676 /* intel_hdmi.c */
1677 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1678                      enum port port);
1679 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1680                                struct intel_connector *intel_connector);
1681 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1682 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1683                                struct intel_crtc_state *pipe_config,
1684                                struct drm_connector_state *conn_state);
1685 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1686                                        struct drm_connector *connector,
1687                                        bool high_tmds_clock_ratio,
1688                                        bool scrambling);
1689 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1690 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1691
1692
1693 /* intel_lvds.c */
1694 void intel_lvds_init(struct drm_i915_private *dev_priv);
1695 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1696 bool intel_is_dual_link_lvds(struct drm_device *dev);
1697
1698
1699 /* intel_modes.c */
1700 int intel_connector_update_modes(struct drm_connector *connector,
1701                                  struct edid *edid);
1702 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1703 void intel_attach_force_audio_property(struct drm_connector *connector);
1704 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1705 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1706
1707
1708 /* intel_overlay.c */
1709 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1710 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1711 int intel_overlay_switch_off(struct intel_overlay *overlay);
1712 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1713                                   struct drm_file *file_priv);
1714 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1715                               struct drm_file *file_priv);
1716 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1717
1718
1719 /* intel_panel.c */
1720 int intel_panel_init(struct intel_panel *panel,
1721                      struct drm_display_mode *fixed_mode,
1722                      struct drm_display_mode *alt_fixed_mode,
1723                      struct drm_display_mode *downclock_mode);
1724 void intel_panel_fini(struct intel_panel *panel);
1725 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1726                             struct drm_display_mode *adjusted_mode);
1727 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1728                              struct intel_crtc_state *pipe_config,
1729                              int fitting_mode);
1730 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1731                               struct intel_crtc_state *pipe_config,
1732                               int fitting_mode);
1733 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1734                                     u32 level, u32 max);
1735 int intel_panel_setup_backlight(struct drm_connector *connector,
1736                                 enum pipe pipe);
1737 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1738                                   const struct drm_connector_state *conn_state);
1739 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1740 void intel_panel_destroy_backlight(struct drm_connector *connector);
1741 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1742 extern struct drm_display_mode *intel_find_panel_downclock(
1743                                 struct drm_i915_private *dev_priv,
1744                                 struct drm_display_mode *fixed_mode,
1745                                 struct drm_connector *connector);
1746
1747 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1748 int intel_backlight_device_register(struct intel_connector *connector);
1749 void intel_backlight_device_unregister(struct intel_connector *connector);
1750 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1751 static inline int intel_backlight_device_register(struct intel_connector *connector)
1752 {
1753         return 0;
1754 }
1755 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1756 {
1757 }
1758 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1759
1760
1761 /* intel_psr.c */
1762 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1763 void intel_psr_enable(struct intel_dp *intel_dp,
1764                       const struct intel_crtc_state *crtc_state);
1765 void intel_psr_disable(struct intel_dp *intel_dp,
1766                       const struct intel_crtc_state *old_crtc_state);
1767 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1768                           unsigned frontbuffer_bits);
1769 void intel_psr_flush(struct drm_i915_private *dev_priv,
1770                      unsigned frontbuffer_bits,
1771                      enum fb_op_origin origin);
1772 void intel_psr_init(struct drm_i915_private *dev_priv);
1773 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1774                                    unsigned frontbuffer_bits);
1775 void intel_psr_compute_config(struct intel_dp *intel_dp,
1776                               struct intel_crtc_state *crtc_state);
1777
1778 /* intel_runtime_pm.c */
1779 int intel_power_domains_init(struct drm_i915_private *);
1780 void intel_power_domains_fini(struct drm_i915_private *);
1781 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1782 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1783 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1784 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1785 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1786 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1787 const char *
1788 intel_display_power_domain_str(enum intel_display_power_domain domain);
1789
1790 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1791                                     enum intel_display_power_domain domain);
1792 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1793                                       enum intel_display_power_domain domain);
1794 void intel_display_power_get(struct drm_i915_private *dev_priv,
1795                              enum intel_display_power_domain domain);
1796 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1797                                         enum intel_display_power_domain domain);
1798 void intel_display_power_put(struct drm_i915_private *dev_priv,
1799                              enum intel_display_power_domain domain);
1800
1801 static inline void
1802 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1803 {
1804         WARN_ONCE(dev_priv->runtime_pm.suspended,
1805                   "Device suspended during HW access\n");
1806 }
1807
1808 static inline void
1809 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1810 {
1811         assert_rpm_device_not_suspended(dev_priv);
1812         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1813                   "RPM wakelock ref not held during HW access");
1814 }
1815
1816 /**
1817  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1818  * @dev_priv: i915 device instance
1819  *
1820  * This function disable asserts that check if we hold an RPM wakelock
1821  * reference, while keeping the device-not-suspended checks still enabled.
1822  * It's meant to be used only in special circumstances where our rule about
1823  * the wakelock refcount wrt. the device power state doesn't hold. According
1824  * to this rule at any point where we access the HW or want to keep the HW in
1825  * an active state we must hold an RPM wakelock reference acquired via one of
1826  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1827  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1828  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1829  * users should avoid using this function.
1830  *
1831  * Any calls to this function must have a symmetric call to
1832  * enable_rpm_wakeref_asserts().
1833  */
1834 static inline void
1835 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1836 {
1837         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1838 }
1839
1840 /**
1841  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1842  * @dev_priv: i915 device instance
1843  *
1844  * This function re-enables the RPM assert checks after disabling them with
1845  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1846  * circumstances otherwise its use should be avoided.
1847  *
1848  * Any calls to this function must have a symmetric call to
1849  * disable_rpm_wakeref_asserts().
1850  */
1851 static inline void
1852 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1853 {
1854         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1855 }
1856
1857 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1858 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1859 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1860 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1861
1862 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1863
1864 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1865                              bool override, unsigned int mask);
1866 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1867                           enum dpio_channel ch, bool override);
1868
1869
1870 /* intel_pm.c */
1871 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1872 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1873 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1874 void intel_update_watermarks(struct intel_crtc *crtc);
1875 void intel_init_pm(struct drm_i915_private *dev_priv);
1876 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1877 void intel_pm_setup(struct drm_i915_private *dev_priv);
1878 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1879 void intel_gpu_ips_teardown(void);
1880 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1881 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1882 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1883 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1884 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1885 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1886 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1887 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1888 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1889 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1890                     struct intel_rps_client *rps);
1891 void g4x_wm_get_hw_state(struct drm_device *dev);
1892 void vlv_wm_get_hw_state(struct drm_device *dev);
1893 void ilk_wm_get_hw_state(struct drm_device *dev);
1894 void skl_wm_get_hw_state(struct drm_device *dev);
1895 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1896                           struct skl_ddb_allocation *ddb /* out */);
1897 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1898                               struct skl_pipe_wm *out);
1899 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1900 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1901 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1902 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1903 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1904 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1905                          const struct skl_wm_level *l2);
1906 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
1907                                  const struct skl_ddb_entry **entries,
1908                                  const struct skl_ddb_entry *ddb,
1909                                  int ignore);
1910 bool ilk_disable_lp_wm(struct drm_device *dev);
1911 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1912                                   struct intel_crtc_state *cstate);
1913 void intel_init_ipc(struct drm_i915_private *dev_priv);
1914 void intel_enable_ipc(struct drm_i915_private *dev_priv);
1915
1916 /* intel_sdvo.c */
1917 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1918                      i915_reg_t reg, enum port port);
1919
1920
1921 /* intel_sprite.c */
1922 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1923                              int usecs);
1924 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1925                                               enum pipe pipe, int plane);
1926 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1927                               struct drm_file *file_priv);
1928 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1929 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1930 void skl_update_plane(struct intel_plane *plane,
1931                       const struct intel_crtc_state *crtc_state,
1932                       const struct intel_plane_state *plane_state);
1933 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
1934 bool skl_plane_get_hw_state(struct intel_plane *plane);
1935 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1936                        enum pipe pipe, enum plane_id plane_id);
1937
1938 /* intel_tv.c */
1939 void intel_tv_init(struct drm_i915_private *dev_priv);
1940
1941 /* intel_atomic.c */
1942 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1943                                                 const struct drm_connector_state *state,
1944                                                 struct drm_property *property,
1945                                                 uint64_t *val);
1946 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1947                                                 struct drm_connector_state *state,
1948                                                 struct drm_property *property,
1949                                                 uint64_t val);
1950 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1951                                          struct drm_connector_state *new_state);
1952 struct drm_connector_state *
1953 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1954
1955 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1956 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1957                                struct drm_crtc_state *state);
1958 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1959 void intel_atomic_state_clear(struct drm_atomic_state *);
1960
1961 static inline struct intel_crtc_state *
1962 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1963                             struct intel_crtc *crtc)
1964 {
1965         struct drm_crtc_state *crtc_state;
1966         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1967         if (IS_ERR(crtc_state))
1968                 return ERR_CAST(crtc_state);
1969
1970         return to_intel_crtc_state(crtc_state);
1971 }
1972
1973 static inline struct intel_crtc_state *
1974 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1975                                      struct intel_crtc *crtc)
1976 {
1977         struct drm_crtc_state *crtc_state;
1978
1979         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1980
1981         if (crtc_state)
1982                 return to_intel_crtc_state(crtc_state);
1983         else
1984                 return NULL;
1985 }
1986
1987 static inline struct intel_plane_state *
1988 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1989                                       struct intel_plane *plane)
1990 {
1991         struct drm_plane_state *plane_state;
1992
1993         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1994
1995         return to_intel_plane_state(plane_state);
1996 }
1997
1998 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1999                                struct intel_crtc *intel_crtc,
2000                                struct intel_crtc_state *crtc_state);
2001
2002 /* intel_atomic_plane.c */
2003 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2004 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2005 void intel_plane_destroy_state(struct drm_plane *plane,
2006                                struct drm_plane_state *state);
2007 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2008 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2009                                         struct intel_crtc_state *crtc_state,
2010                                         const struct intel_plane_state *old_plane_state,
2011                                         struct intel_plane_state *intel_state);
2012
2013 /* intel_color.c */
2014 void intel_color_init(struct drm_crtc *crtc);
2015 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2016 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2017 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2018
2019 /* intel_lspcon.c */
2020 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2021 void lspcon_resume(struct intel_lspcon *lspcon);
2022 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2023
2024 /* intel_pipe_crc.c */
2025 int intel_pipe_crc_create(struct drm_minor *minor);
2026 #ifdef CONFIG_DEBUG_FS
2027 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2028                               size_t *values_cnt);
2029 #else
2030 #define intel_crtc_set_crc_source NULL
2031 #endif
2032 extern const struct file_operations i915_display_crc_ctl_fops;
2033 #endif /* __INTEL_DRV_H__ */