drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 /**
  41  * _wait_for - magic (register) wait macro
  42  *
  43  * Does the right thing for modeset paths when run under kdgb or similar atomic
  44  * contexts. Note that it's important that we check the condition again after
  45  * having timed out, since the timeout could be due to preemption or similar and
  46  * we've never had a chance to check the condition before the timeout.
  47  */
  48 #define _wait_for(COND, MS, W) ({ \
  49         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  50         int ret__ = 0;                                                  \
  51         while (!(COND)) {                                               \
  52                 if (time_after(jiffies, timeout__)) {                   \
  53                         if (!(COND))                                    \
  54                                 ret__ = -ETIMEDOUT;                     \
  55                         break;                                          \
  56                 }                                                       \
  57                 if ((W) && drm_can_sleep()) {                           \
  58                         usleep_range((W)*1000, (W)*2000);               \
  59                 } else {                                                \
  60                         cpu_relax();                                    \
  61                 }                                                       \
  62         }                                                               \
  63         ret__;                                                          \
  64 })
  65
  66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69                                                DIV_ROUND_UP((US), 1000), 0)
  70
  71 #define KHz(x) (1000 * (x))
  72 #define MHz(x) KHz(1000 * (x))
  73
  74 /*
  75  * Display related stuff
  76  */
  77
  78 /* store information about an Ixxx DVO */
  79 /* The i830->i865 use multiple DVOs with multiple i2cs */
  80 /* the i915, i945 have a single sDVO i2c bus - which is different */
  81 #define MAX_OUTPUTS 6
  82 /* maximum connectors per crtcs in the mode set */
  83
  84 /* Maximum cursor sizes */
  85 #define GEN2_CURSOR_WIDTH 64
  86 #define GEN2_CURSOR_HEIGHT 64
  87 #define MAX_CURSOR_WIDTH 256
  88 #define MAX_CURSOR_HEIGHT 256
  89
  90 #define INTEL_I2C_BUS_DVO 1
  91 #define INTEL_I2C_BUS_SDVO 2
  92
  93 /* these are outputs from the chip - integrated only
  94    external chips are via DVO or SDVO output */
  95 enum intel_output_type {
  96         INTEL_OUTPUT_UNUSED = 0,
  97         INTEL_OUTPUT_ANALOG = 1,
  98         INTEL_OUTPUT_DVO = 2,
  99         INTEL_OUTPUT_SDVO = 3,
 100         INTEL_OUTPUT_LVDS = 4,
 101         INTEL_OUTPUT_TVOUT = 5,
 102         INTEL_OUTPUT_HDMI = 6,
 103         INTEL_OUTPUT_DISPLAYPORT = 7,
 104         INTEL_OUTPUT_EDP = 8,
 105         INTEL_OUTPUT_DSI = 9,
 106         INTEL_OUTPUT_UNKNOWN = 10,
 107         INTEL_OUTPUT_DP_MST = 11,
 108 };
 109
 110 #define INTEL_DVO_CHIP_NONE 0
 111 #define INTEL_DVO_CHIP_LVDS 1
 112 #define INTEL_DVO_CHIP_TMDS 2
 113 #define INTEL_DVO_CHIP_TVOUT 4
 114
 115 #define INTEL_DSI_VIDEO_MODE    0
 116 #define INTEL_DSI_COMMAND_MODE  1
 117
 118 struct intel_framebuffer {
 119         struct drm_framebuffer base;
 120         struct drm_i915_gem_object *obj;
 121 };
 122
 123 struct intel_fbdev {
 124         struct drm_fb_helper helper;
 125         struct intel_framebuffer *fb;
 126         struct list_head fbdev_list;
 127         struct drm_display_mode *our_mode;
 128         int preferred_bpp;
 129 };
 130
 131 struct intel_encoder {
 132         struct drm_encoder base;
 133         /*
 134          * The new crtc this encoder will be driven from. Only differs from
 135          * base->crtc while a modeset is in progress.
 136          */
 137         struct intel_crtc *new_crtc;
 138
 139         enum intel_output_type type;
 140         unsigned int cloneable;
 141         bool connectors_active;
 142         void (*hot_plug)(struct intel_encoder *);
 143         bool (*compute_config)(struct intel_encoder *,
 144                                struct intel_crtc_state *);
 145         void (*pre_pll_enable)(struct intel_encoder *);
 146         void (*pre_enable)(struct intel_encoder *);
 147         void (*enable)(struct intel_encoder *);
 148         void (*mode_set)(struct intel_encoder *intel_encoder);
 149         void (*disable)(struct intel_encoder *);
 150         void (*post_disable)(struct intel_encoder *);
 151         /* Read out the current hw state of this connector, returning true if
 152          * the encoder is active. If the encoder is enabled it also set the pipe
 153          * it is connected to in the pipe parameter. */
 154         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 155         /* Reconstructs the equivalent mode flags for the current hardware
 156          * state. This must be called _after_ display->get_pipe_config has
 157          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 158          * be set correctly before calling this function. */
 159         void (*get_config)(struct intel_encoder *,
 160                            struct intel_crtc_state *pipe_config);
 161         /*
 162          * Called during system suspend after all pending requests for the
 163          * encoder are flushed (for example for DP AUX transactions) and
 164          * device interrupts are disabled.
 165          */
 166         void (*suspend)(struct intel_encoder *);
 167         int crtc_mask;
 168         enum hpd_pin hpd_pin;
 169 };
 170
 171 struct intel_panel {
 172         struct drm_display_mode *fixed_mode;
 173         struct drm_display_mode *downclock_mode;
 174         int fitting_mode;
 175
 176         /* backlight */
 177         struct {
 178                 bool present;
 179                 u32 level;
 180                 u32 min;
 181                 u32 max;
 182                 bool enabled;
 183                 bool combination_mode;  /* gen 2/4 only */
 184                 bool active_low_pwm;
 185                 struct backlight_device *device;
 186         } backlight;
 187
 188         void (*backlight_power)(struct intel_connector *, bool enable);
 189 };
 190
 191 struct intel_connector {
 192         struct drm_connector base;
 193         /*
 194          * The fixed encoder this connector is connected to.
 195          */
 196         struct intel_encoder *encoder;
 197
 198         /*
 199          * The new encoder this connector will be driven. Only differs from
 200          * encoder while a modeset is in progress.
 201          */
 202         struct intel_encoder *new_encoder;
 203
 204         /* Reads out the current hw, returning true if the connector is enabled
 205          * and active (i.e. dpms ON state). */
 206         bool (*get_hw_state)(struct intel_connector *);
 207
 208         /*
 209          * Removes all interfaces through which the connector is accessible
 210          * - like sysfs, debugfs entries -, so that no new operations can be
 211          * started on the connector. Also makes sure all currently pending
 212          * operations finish before returing.
 213          */
 214         void (*unregister)(struct intel_connector *);
 215
 216         /* Panel info for eDP and LVDS */
 217         struct intel_panel panel;
 218
 219         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 220         struct edid *edid;
 221         struct edid *detect_edid;
 222
 223         /* since POLL and HPD connectors may use the same HPD line keep the native
 224            state of connector->polled in case hotplug storm detection changes it */
 225         u8 polled;
 226
 227         void *port; /* store this opaque as its illegal to dereference it */
 228
 229         struct intel_dp *mst_port;
 230 };
 231
 232 typedef struct dpll {
 233         /* given values */
 234         int n;
 235         int m1, m2;
 236         int p1, p2;
 237         /* derived values */
 238         int     dot;
 239         int     vco;
 240         int     m;
 241         int     p;
 242 } intel_clock_t;
 243
 244 struct intel_atomic_state {
 245         struct drm_atomic_state base;
 246
 247         unsigned int cdclk;
 248         bool dpll_set;
 249         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 250 };
 251
 252 struct intel_plane_state {
 253         struct drm_plane_state base;
 254         struct drm_rect src;
 255         struct drm_rect dst;
 256         struct drm_rect clip;
 257         bool visible;
 258
 259         /*
 260          * scaler_id
 261          *    = -1 : not using a scaler
 262          *    >=  0 : using a scalers
 263          *
 264          * plane requiring a scaler:
 265          *   - During check_plane, its bit is set in
 266          *     crtc_state->scaler_state.scaler_users by calling helper function
 267          *     update_scaler_plane.
 268          *   - scaler_id indicates the scaler it got assigned.
 269          *
 270          * plane doesn't require a scaler:
 271          *   - this can happen when scaling is no more required or plane simply
 272          *     got disabled.
 273          *   - During check_plane, corresponding bit is reset in
 274          *     crtc_state->scaler_state.scaler_users by calling helper function
 275          *     update_scaler_plane.
 276          */
 277         int scaler_id;
 278
 279         struct drm_intel_sprite_colorkey ckey;
 280 };
 281
 282 struct intel_initial_plane_config {
 283         struct intel_framebuffer *fb;
 284         unsigned int tiling;
 285         int size;
 286         u32 base;
 287 };
 288
 289 #define SKL_MIN_SRC_W 8
 290 #define SKL_MAX_SRC_W 4096
 291 #define SKL_MIN_SRC_H 8
 292 #define SKL_MAX_SRC_H 4096
 293 #define SKL_MIN_DST_W 8
 294 #define SKL_MAX_DST_W 4096
 295 #define SKL_MIN_DST_H 8
 296 #define SKL_MAX_DST_H 4096
 297
 298 struct intel_scaler {
 299         int in_use;
 300         uint32_t mode;
 301 };
 302
 303 struct intel_crtc_scaler_state {
 304 #define SKL_NUM_SCALERS 2
 305         struct intel_scaler scalers[SKL_NUM_SCALERS];
 306
 307         /*
 308          * scaler_users: keeps track of users requesting scalers on this crtc.
 309          *
 310          *     If a bit is set, a user is using a scaler.
 311          *     Here user can be a plane or crtc as defined below:
 312          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 313          *       bit 31    - crtc
 314          *
 315          * Instead of creating a new index to cover planes and crtc, using
 316          * existing drm_plane_index for planes which is well less than 31
 317          * planes and bit 31 for crtc. This should be fine to cover all
 318          * our platforms.
 319          *
 320          * intel_atomic_setup_scalers will setup available scalers to users
 321          * requesting scalers. It will gracefully fail if request exceeds
 322          * avilability.
 323          */
 324 #define SKL_CRTC_INDEX 31
 325         unsigned scaler_users;
 326
 327         /* scaler used by crtc for panel fitting purpose */
 328         int scaler_id;
 329 };
 330
 331 struct intel_crtc_state {
 332         struct drm_crtc_state base;
 333
 334         /**
 335          * quirks - bitfield with hw state readout quirks
 336          *
 337          * For various reasons the hw state readout code might not be able to
 338          * completely faithfully read out the current state. These cases are
 339          * tracked with quirk flags so that fastboot and state checker can act
 340          * accordingly.
 341          */
 342 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 343 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 344 #define PIPE_CONFIG_QUIRK_INITIAL_PLANES        (1<<2) /* planes are in unknown state */
 345         unsigned long quirks;
 346
 347         /* Pipe source size (ie. panel fitter input size)
 348          * All planes will be positioned inside this space,
 349          * and get clipped at the edges. */
 350         int pipe_src_w, pipe_src_h;
 351
 352         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 353          * between pch encoders and cpu encoders. */
 354         bool has_pch_encoder;
 355
 356         /* Are we sending infoframes on the attached port */
 357         bool has_infoframe;
 358
 359         /* CPU Transcoder for the pipe. Currently this can only differ from the
 360          * pipe on Haswell (where we have a special eDP transcoder). */
 361         enum transcoder cpu_transcoder;
 362
 363         /*
 364          * Use reduced/limited/broadcast rbg range, compressing from the full
 365          * range fed into the crtcs.
 366          */
 367         bool limited_color_range;
 368
 369         /* DP has a bunch of special case unfortunately, so mark the pipe
 370          * accordingly. */
 371         bool has_dp_encoder;
 372
 373         /* Whether we should send NULL infoframes. Required for audio. */
 374         bool has_hdmi_sink;
 375
 376         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 377          * has_dp_encoder is set. */
 378         bool has_audio;
 379
 380         /*
 381          * Enable dithering, used when the selected pipe bpp doesn't match the
 382          * plane bpp.
 383          */
 384         bool dither;
 385
 386         /* Controls for the clock computation, to override various stages. */
 387         bool clock_set;
 388
 389         /* SDVO TV has a bunch of special case. To make multifunction encoders
 390          * work correctly, we need to track this at runtime.*/
 391         bool sdvo_tv_clock;
 392
 393         /*
 394          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 395          * required. This is set in the 2nd loop of calling encoder's
 396          * ->compute_config if the first pick doesn't work out.
 397          */
 398         bool bw_constrained;
 399
 400         /* Settings for the intel dpll used on pretty much everything but
 401          * haswell. */
 402         struct dpll dpll;
 403
 404         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 405         enum intel_dpll_id shared_dpll;
 406
 407         /*
 408          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 409          * - enum skl_dpll on SKL
 410          */
 411         uint32_t ddi_pll_sel;
 412
 413         /* Actual register state of the dpll, for shared dpll cross-checking. */
 414         struct intel_dpll_hw_state dpll_hw_state;
 415
 416         int pipe_bpp;
 417         struct intel_link_m_n dp_m_n;
 418
 419         /* m2_n2 for eDP downclock */
 420         struct intel_link_m_n dp_m2_n2;
 421         bool has_drrs;
 422
 423         /*
 424          * Frequence the dpll for the port should run at. Differs from the
 425          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 426          * already multiplied by pixel_multiplier.
 427          */
 428         int port_clock;
 429
 430         /* Used by SDVO (and if we ever fix it, HDMI). */
 431         unsigned pixel_multiplier;
 432
 433         /* Panel fitter controls for gen2-gen4 + VLV */
 434         struct {
 435                 u32 control;
 436                 u32 pgm_ratios;
 437                 u32 lvds_border_bits;
 438         } gmch_pfit;
 439
 440         /* Panel fitter placement and size for Ironlake+ */
 441         struct {
 442                 u32 pos;
 443                 u32 size;
 444                 bool enabled;
 445                 bool force_thru;
 446         } pch_pfit;
 447
 448         /* FDI configuration, only valid if has_pch_encoder is set. */
 449         int fdi_lanes;
 450         struct intel_link_m_n fdi_m_n;
 451
 452         bool ips_enabled;
 453
 454         bool double_wide;
 455
 456         bool dp_encoder_is_mst;
 457         int pbn;
 458
 459         struct intel_crtc_scaler_state scaler_state;
 460
 461         /* w/a for waiting 2 vblanks during crtc enable */
 462         enum pipe hsw_workaround_pipe;
 463 };
 464
 465 struct vlv_wm_state {
 466         struct vlv_pipe_wm wm[3];
 467         struct vlv_sr_wm sr[3];
 468         uint8_t num_active_planes;
 469         uint8_t num_levels;
 470         uint8_t level;
 471         bool cxsr;
 472 };
 473
 474 struct intel_pipe_wm {
 475         struct intel_wm_level wm[5];
 476         uint32_t linetime;
 477         bool fbc_wm_enabled;
 478         bool pipe_enabled;
 479         bool sprites_enabled;
 480         bool sprites_scaled;
 481 };
 482
 483 struct intel_mmio_flip {
 484         struct work_struct work;
 485         struct drm_i915_private *i915;
 486         struct drm_i915_gem_request *req;
 487         struct intel_crtc *crtc;
 488 };
 489
 490 struct skl_pipe_wm {
 491         struct skl_wm_level wm[8];
 492         struct skl_wm_level trans_wm;
 493         uint32_t linetime;
 494 };
 495
 496 /*
 497  * Tracking of operations that need to be performed at the beginning/end of an
 498  * atomic commit, outside the atomic section where interrupts are disabled.
 499  * These are generally operations that grab mutexes or might otherwise sleep
 500  * and thus can't be run with interrupts disabled.
 501  */
 502 struct intel_crtc_atomic_commit {
 503         /* vblank evasion */
 504         bool evade;
 505         unsigned start_vbl_count;
 506
 507         /* Sleepable operations to perform before commit */
 508         bool wait_for_flips;
 509         bool disable_fbc;
 510         bool disable_ips;
 511         bool disable_cxsr;
 512         bool pre_disable_primary;
 513         bool update_wm_pre, update_wm_post;
 514         unsigned disabled_planes;
 515
 516         /* Sleepable operations to perform after commit */
 517         unsigned fb_bits;
 518         bool wait_vblank;
 519         bool update_fbc;
 520         bool post_enable_primary;
 521         unsigned update_sprite_watermarks;
 522 };
 523
 524 struct intel_crtc {
 525         struct drm_crtc base;
 526         enum pipe pipe;
 527         enum plane plane;
 528         u8 lut_r[256], lut_g[256], lut_b[256];
 529         /*
 530          * Whether the crtc and the connected output pipeline is active. Implies
 531          * that crtc->enabled is set, i.e. the current mode configuration has
 532          * some outputs connected to this crtc.
 533          */
 534         bool active;
 535         unsigned long enabled_power_domains;
 536         bool lowfreq_avail;
 537         struct intel_overlay *overlay;
 538         struct intel_unpin_work *unpin_work;
 539
 540         atomic_t unpin_work_count;
 541
 542         /* Display surface base address adjustement for pageflips. Note that on
 543          * gen4+ this only adjusts up to a tile, offsets within a tile are
 544          * handled in the hw itself (with the TILEOFF register). */
 545         unsigned long dspaddr_offset;
 546
 547         struct drm_i915_gem_object *cursor_bo;
 548         uint32_t cursor_addr;
 549         uint32_t cursor_cntl;
 550         uint32_t cursor_size;
 551         uint32_t cursor_base;
 552
 553         struct intel_initial_plane_config plane_config;
 554         struct intel_crtc_state *config;
 555         bool new_enabled;
 556
 557         /* reset counter value when the last flip was submitted */
 558         unsigned int reset_counter;
 559
 560         /* Access to these should be protected by dev_priv->irq_lock. */
 561         bool cpu_fifo_underrun_disabled;
 562         bool pch_fifo_underrun_disabled;
 563
 564         /* per-pipe watermark state */
 565         struct {
 566                 /* watermarks currently being used  */
 567                 struct intel_pipe_wm active;
 568                 /* SKL wm values currently in use */
 569                 struct skl_pipe_wm skl_active;
 570                 /* allow CxSR on this pipe */
 571                 bool cxsr_allowed;
 572         } wm;
 573
 574         int scanline_offset;
 575
 576         struct intel_crtc_atomic_commit atomic;
 577
 578         /* scalers available on this crtc */
 579         int num_scalers;
 580
 581         struct vlv_wm_state wm_state;
 582 };
 583
 584 struct intel_plane_wm_parameters {
 585         uint32_t horiz_pixels;
 586         uint32_t vert_pixels;
 587         /*
 588          *   For packed pixel formats:
 589          *     bytes_per_pixel - holds bytes per pixel
 590          *   For planar pixel formats:
 591          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 592          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 593          */
 594         uint8_t bytes_per_pixel;
 595         uint8_t y_bytes_per_pixel;
 596         bool enabled;
 597         bool scaled;
 598         u64 tiling;
 599         unsigned int rotation;
 600         uint16_t fifo_size;
 601 };
 602
 603 struct intel_plane {
 604         struct drm_plane base;
 605         int plane;
 606         enum pipe pipe;
 607         bool can_scale;
 608         int max_downscale;
 609         uint32_t frontbuffer_bit;
 610
 611         /* Since we need to change the watermarks before/after
 612          * enabling/disabling the planes, we need to store the parameters here
 613          * as the other pieces of the struct may not reflect the values we want
 614          * for the watermark calculations. Currently only Haswell uses this.
 615          */
 616         struct intel_plane_wm_parameters wm;
 617
 618         /*
 619          * NOTE: Do not place new plane state fields here (e.g., when adding
 620          * new plane properties).  New runtime state should now be placed in
 621          * the intel_plane_state structure and accessed via drm_plane->state.
 622          */
 623
 624         void (*update_plane)(struct drm_plane *plane,
 625                              struct drm_crtc *crtc,
 626                              struct drm_framebuffer *fb,
 627                              int crtc_x, int crtc_y,
 628                              unsigned int crtc_w, unsigned int crtc_h,
 629                              uint32_t x, uint32_t y,
 630                              uint32_t src_w, uint32_t src_h);
 631         void (*disable_plane)(struct drm_plane *plane,
 632                               struct drm_crtc *crtc);
 633         int (*check_plane)(struct drm_plane *plane,
 634                            struct intel_crtc_state *crtc_state,
 635                            struct intel_plane_state *state);
 636         void (*commit_plane)(struct drm_plane *plane,
 637                              struct intel_plane_state *state);
 638 };
 639
 640 struct intel_watermark_params {
 641         unsigned long fifo_size;
 642         unsigned long max_wm;
 643         unsigned long default_wm;
 644         unsigned long guard_size;
 645         unsigned long cacheline_size;
 646 };
 647
 648 struct cxsr_latency {
 649         int is_desktop;
 650         int is_ddr3;
 651         unsigned long fsb_freq;
 652         unsigned long mem_freq;
 653         unsigned long display_sr;
 654         unsigned long display_hpll_disable;
 655         unsigned long cursor_sr;
 656         unsigned long cursor_hpll_disable;
 657 };
 658
 659 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 660 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 661 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 662 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 663 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 664 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 665 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 666 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 667 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 668
 669 struct intel_hdmi {
 670         u32 hdmi_reg;
 671         int ddc_bus;
 672         uint32_t color_range;
 673         bool color_range_auto;
 674         bool has_hdmi_sink;
 675         bool has_audio;
 676         enum hdmi_force_audio force_audio;
 677         bool rgb_quant_range_selectable;
 678         enum hdmi_picture_aspect aspect_ratio;
 679         void (*write_infoframe)(struct drm_encoder *encoder,
 680                                 enum hdmi_infoframe_type type,
 681                                 const void *frame, ssize_t len);
 682         void (*set_infoframes)(struct drm_encoder *encoder,
 683                                bool enable,
 684                                struct drm_display_mode *adjusted_mode);
 685         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 686 };
 687
 688 struct intel_dp_mst_encoder;
 689 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 690
 691 /*
 692  * enum link_m_n_set:
 693  *      When platform provides two set of M_N registers for dp, we can
 694  *      program them and switch between them incase of DRRS.
 695  *      But When only one such register is provided, we have to program the
 696  *      required divider value on that registers itself based on the DRRS state.
 697  *
 698  * M1_N1        : Program dp_m_n on M1_N1 registers
 699  *                        dp_m2_n2 on M2_N2 registers (If supported)
 700  *
 701  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 702  *                        M2_N2 registers are not supported
 703  */
 704
 705 enum link_m_n_set {
 706         /* Sets the m1_n1 and m2_n2 */
 707         M1_N1 = 0,
 708         M2_N2
 709 };
 710
 711 struct intel_dp {
 712         uint32_t output_reg;
 713         uint32_t aux_ch_ctl_reg;
 714         uint32_t DP;
 715         bool has_audio;
 716         enum hdmi_force_audio force_audio;
 717         uint32_t color_range;
 718         bool color_range_auto;
 719         uint8_t link_bw;
 720         uint8_t rate_select;
 721         uint8_t lane_count;
 722         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 723         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 724         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 725         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 726         uint8_t num_sink_rates;
 727         int sink_rates[DP_MAX_SUPPORTED_RATES];
 728         struct drm_dp_aux aux;
 729         uint8_t train_set[4];
 730         int panel_power_up_delay;
 731         int panel_power_down_delay;
 732         int panel_power_cycle_delay;
 733         int backlight_on_delay;
 734         int backlight_off_delay;
 735         struct delayed_work panel_vdd_work;
 736         bool want_panel_vdd;
 737         unsigned long last_power_cycle;
 738         unsigned long last_power_on;
 739         unsigned long last_backlight_off;
 740
 741         struct notifier_block edp_notifier;
 742
 743         /*
 744          * Pipe whose power sequencer is currently locked into
 745          * this port. Only relevant on VLV/CHV.
 746          */
 747         enum pipe pps_pipe;
 748         struct edp_power_seq pps_delays;
 749
 750         bool use_tps3;
 751         bool can_mst; /* this port supports mst */
 752         bool is_mst;
 753         int active_mst_links;
 754         /* connector directly attached - won't be use for modeset in mst world */
 755         struct intel_connector *attached_connector;
 756
 757         /* mst connector list */
 758         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 759         struct drm_dp_mst_topology_mgr mst_mgr;
 760
 761         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 762         /*
 763          * This function returns the value we have to program the AUX_CTL
 764          * register with to kick off an AUX transaction.
 765          */
 766         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 767                                      bool has_aux_irq,
 768                                      int send_bytes,
 769                                      uint32_t aux_clock_divider);
 770         bool train_set_valid;
 771
 772         /* Displayport compliance testing */
 773         unsigned long compliance_test_type;
 774         unsigned long compliance_test_data;
 775         bool compliance_test_active;
 776 };
 777
 778 struct intel_digital_port {
 779         struct intel_encoder base;
 780         enum port port;
 781         u32 saved_port_bits;
 782         struct intel_dp dp;
 783         struct intel_hdmi hdmi;
 784         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 785 };
 786
 787 struct intel_dp_mst_encoder {
 788         struct intel_encoder base;
 789         enum pipe pipe;
 790         struct intel_digital_port *primary;
 791         void *port; /* store this opaque as its illegal to dereference it */
 792 };
 793
 794 static inline int
 795 vlv_dport_to_channel(struct intel_digital_port *dport)
 796 {
 797         switch (dport->port) {
 798         case PORT_B:
 799         case PORT_D:
 800                 return DPIO_CH0;
 801         case PORT_C:
 802                 return DPIO_CH1;
 803         default:
 804                 BUG();
 805         }
 806 }
 807
 808 static inline int
 809 vlv_pipe_to_channel(enum pipe pipe)
 810 {
 811         switch (pipe) {
 812         case PIPE_A:
 813         case PIPE_C:
 814                 return DPIO_CH0;
 815         case PIPE_B:
 816                 return DPIO_CH1;
 817         default:
 818                 BUG();
 819         }
 820 }
 821
 822 static inline struct drm_crtc *
 823 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 824 {
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         return dev_priv->pipe_to_crtc_mapping[pipe];
 827 }
 828
 829 static inline struct drm_crtc *
 830 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         return dev_priv->plane_to_crtc_mapping[plane];
 834 }
 835
 836 struct intel_unpin_work {
 837         struct work_struct work;
 838         struct drm_crtc *crtc;
 839         struct drm_framebuffer *old_fb;
 840         struct drm_i915_gem_object *pending_flip_obj;
 841         struct drm_pending_vblank_event *event;
 842         atomic_t pending;
 843 #define INTEL_FLIP_INACTIVE     0
 844 #define INTEL_FLIP_PENDING      1
 845 #define INTEL_FLIP_COMPLETE     2
 846         u32 flip_count;
 847         u32 gtt_offset;
 848         struct drm_i915_gem_request *flip_queued_req;
 849         int flip_queued_vblank;
 850         int flip_ready_vblank;
 851         bool enable_stall_check;
 852 };
 853
 854 struct intel_load_detect_pipe {
 855         struct drm_framebuffer *release_fb;
 856         bool load_detect_temp;
 857         int dpms_mode;
 858 };
 859
 860 static inline struct intel_encoder *
 861 intel_attached_encoder(struct drm_connector *connector)
 862 {
 863         return to_intel_connector(connector)->encoder;
 864 }
 865
 866 static inline struct intel_digital_port *
 867 enc_to_dig_port(struct drm_encoder *encoder)
 868 {
 869         return container_of(encoder, struct intel_digital_port, base.base);
 870 }
 871
 872 static inline struct intel_dp_mst_encoder *
 873 enc_to_mst(struct drm_encoder *encoder)
 874 {
 875         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 876 }
 877
 878 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 879 {
 880         return &enc_to_dig_port(encoder)->dp;
 881 }
 882
 883 static inline struct intel_digital_port *
 884 dp_to_dig_port(struct intel_dp *intel_dp)
 885 {
 886         return container_of(intel_dp, struct intel_digital_port, dp);
 887 }
 888
 889 static inline struct intel_digital_port *
 890 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 891 {
 892         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 893 }
 894
 895 /*
 896  * Returns the number of planes for this pipe, ie the number of sprites + 1
 897  * (primary plane). This doesn't count the cursor plane then.
 898  */
 899 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 900 {
 901         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 902 }
 903
 904 /* intel_fifo_underrun.c */
 905 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 906                                            enum pipe pipe, bool enable);
 907 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 908                                            enum transcoder pch_transcoder,
 909                                            bool enable);
 910 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 911                                          enum pipe pipe);
 912 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 913                                          enum transcoder pch_transcoder);
 914 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 915
 916 /* i915_irq.c */
 917 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 918 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 919 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 920 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 921 void gen6_reset_rps_interrupts(struct drm_device *dev);
 922 void gen6_enable_rps_interrupts(struct drm_device *dev);
 923 void gen6_disable_rps_interrupts(struct drm_device *dev);
 924 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 925 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 926 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 927 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 928 {
 929         /*
 930          * We only use drm_irq_uninstall() at unload and VT switch, so
 931          * this is the only thing we need to check.
 932          */
 933         return dev_priv->pm.irqs_enabled;
 934 }
 935
 936 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 937 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 938                                      unsigned int pipe_mask);
 939
 940 /* intel_crt.c */
 941 void intel_crt_init(struct drm_device *dev);
 942
 943
 944 /* intel_ddi.c */
 945 void intel_prepare_ddi(struct drm_device *dev);
 946 void hsw_fdi_link_train(struct drm_crtc *crtc);
 947 void intel_ddi_init(struct drm_device *dev, enum port port);
 948 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 949 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 950 void intel_ddi_pll_init(struct drm_device *dev);
 951 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 952 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 953                                        enum transcoder cpu_transcoder);
 954 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 955 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 956 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 957                           struct intel_crtc_state *crtc_state);
 958 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 959 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 960 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 961 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 962 void intel_ddi_get_config(struct intel_encoder *encoder,
 963                           struct intel_crtc_state *pipe_config);
 964 struct intel_encoder *
 965 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
 966
 967 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 968 void intel_ddi_clock_get(struct intel_encoder *encoder,
 969                          struct intel_crtc_state *pipe_config);
 970 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 971 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 972
 973 /* intel_frontbuffer.c */
 974 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 975                              enum fb_op_origin origin);
 976 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 977                                     unsigned frontbuffer_bits);
 978 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 979                                      unsigned frontbuffer_bits);
 980 void intel_frontbuffer_flush(struct drm_device *dev,
 981                              unsigned frontbuffer_bits);
 982 void intel_frontbuffer_flip(struct drm_device *dev,
 983                             unsigned frontbuffer_bits);
 984
 985 unsigned int intel_fb_align_height(struct drm_device *dev,
 986                                    unsigned int height,
 987                                    uint32_t pixel_format,
 988                                    uint64_t fb_format_modifier);
 989 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 990
 991 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 992                               uint32_t pixel_format);
 993
 994 /* intel_audio.c */
 995 void intel_init_audio(struct drm_device *dev);
 996 void intel_audio_codec_enable(struct intel_encoder *encoder);
 997 void intel_audio_codec_disable(struct intel_encoder *encoder);
 998 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 999 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1000
1001 /* intel_display.c */
1002 extern const struct drm_plane_funcs intel_plane_funcs;
1003 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1004 int intel_pch_rawclk(struct drm_device *dev);
1005 void intel_mark_busy(struct drm_device *dev);
1006 void intel_mark_idle(struct drm_device *dev);
1007 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1008 void intel_display_suspend(struct drm_device *dev);
1009 int intel_crtc_control(struct drm_crtc *crtc, bool enable);
1010 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1011 void intel_encoder_destroy(struct drm_encoder *encoder);
1012 int intel_connector_init(struct intel_connector *);
1013 struct intel_connector *intel_connector_alloc(void);
1014 void intel_connector_dpms(struct drm_connector *, int mode);
1015 bool intel_connector_get_hw_state(struct intel_connector *connector);
1016 void intel_modeset_check_state(struct drm_device *dev);
1017 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1018                                 struct intel_digital_port *port);
1019 void intel_connector_attach_encoder(struct intel_connector *connector,
1020                                     struct intel_encoder *encoder);
1021 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1022 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1023                                              struct drm_crtc *crtc);
1024 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1025 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1026                                 struct drm_file *file_priv);
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1028                                              enum pipe pipe);
1029 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1030 static inline void
1031 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1032 {
1033         drm_wait_one_vblank(dev, pipe);
1034 }
1035 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1036 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1037                          struct intel_digital_port *dport,
1038                          unsigned int expected_mask);
1039 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1040                                 struct drm_display_mode *mode,
1041                                 struct intel_load_detect_pipe *old,
1042                                 struct drm_modeset_acquire_ctx *ctx);
1043 void intel_release_load_detect_pipe(struct drm_connector *connector,
1044                                     struct intel_load_detect_pipe *old,
1045                                     struct drm_modeset_acquire_ctx *ctx);
1046 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1047                                struct drm_framebuffer *fb,
1048                                const struct drm_plane_state *plane_state,
1049                                struct intel_engine_cs *pipelined,
1050                                struct drm_i915_gem_request **pipelined_request);
1051 struct drm_framebuffer *
1052 __intel_framebuffer_create(struct drm_device *dev,
1053                            struct drm_mode_fb_cmd2 *mode_cmd,
1054                            struct drm_i915_gem_object *obj);
1055 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1056 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1057 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1058 void intel_check_page_flip(struct drm_device *dev, int pipe);
1059 int intel_prepare_plane_fb(struct drm_plane *plane,
1060                            struct drm_framebuffer *fb,
1061                            const struct drm_plane_state *new_state);
1062 void intel_cleanup_plane_fb(struct drm_plane *plane,
1063                             struct drm_framebuffer *fb,
1064                             const struct drm_plane_state *old_state);
1065 int intel_plane_atomic_get_property(struct drm_plane *plane,
1066                                     const struct drm_plane_state *state,
1067                                     struct drm_property *property,
1068                                     uint64_t *val);
1069 int intel_plane_atomic_set_property(struct drm_plane *plane,
1070                                     struct drm_plane_state *state,
1071                                     struct drm_property *property,
1072                                     uint64_t val);
1073 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1074                                     struct drm_plane_state *plane_state);
1075
1076 unsigned int
1077 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1078                   uint64_t fb_format_modifier);
1079
1080 static inline bool
1081 intel_rotation_90_or_270(unsigned int rotation)
1082 {
1083         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1084 }
1085
1086 void intel_create_rotation_property(struct drm_device *dev,
1087                                         struct intel_plane *plane);
1088
1089 /* shared dpll functions */
1090 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1091 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1092                         struct intel_shared_dpll *pll,
1093                         bool state);
1094 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1095 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1096 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1097                                                 struct intel_crtc_state *state);
1098
1099 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1100                       const struct dpll *dpll);
1101 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1102
1103 /* modesetting asserts */
1104 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1105                            enum pipe pipe);
1106 void assert_pll(struct drm_i915_private *dev_priv,
1107                 enum pipe pipe, bool state);
1108 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1109 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1110 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1111                        enum pipe pipe, bool state);
1112 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1113 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1114 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1115 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1116 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1117 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1118                                              int *x, int *y,
1119                                              unsigned int tiling_mode,
1120                                              unsigned int bpp,
1121                                              unsigned int pitch);
1122 void intel_prepare_reset(struct drm_device *dev);
1123 void intel_finish_reset(struct drm_device *dev);
1124 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1125 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1126 void broxton_init_cdclk(struct drm_device *dev);
1127 void broxton_uninit_cdclk(struct drm_device *dev);
1128 void broxton_ddi_phy_init(struct drm_device *dev);
1129 void broxton_ddi_phy_uninit(struct drm_device *dev);
1130 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1131 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1132 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1133 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1134 void intel_dp_get_m_n(struct intel_crtc *crtc,
1135                       struct intel_crtc_state *pipe_config);
1136 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1137 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1138 void
1139 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1140                                 int dotclock);
1141 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1142                         intel_clock_t *best_clock);
1143 bool intel_crtc_active(struct drm_crtc *crtc);
1144 void hsw_enable_ips(struct intel_crtc *crtc);
1145 void hsw_disable_ips(struct intel_crtc *crtc);
1146 enum intel_display_power_domain
1147 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1148 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1149                                  struct intel_crtc_state *pipe_config);
1150 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1151 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1152
1153 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state, int force_detach);
1154 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1155
1156 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1157                                      struct drm_i915_gem_object *obj);
1158 u32 skl_plane_ctl_format(uint32_t pixel_format);
1159 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1160 u32 skl_plane_ctl_rotation(unsigned int rotation);
1161
1162 /* intel_csr.c */
1163 void intel_csr_ucode_init(struct drm_device *dev);
1164 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1165 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1166                                         enum csr_state state);
1167 void intel_csr_load_program(struct drm_device *dev);
1168 void intel_csr_ucode_fini(struct drm_device *dev);
1169 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1170
1171 /* intel_dp.c */
1172 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1173 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1174                              struct intel_connector *intel_connector);
1175 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1176 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1177 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1178 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1179 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1180 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1181 bool intel_dp_compute_config(struct intel_encoder *encoder,
1182                              struct intel_crtc_state *pipe_config);
1183 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1184 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1185                                   bool long_hpd);
1186 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1187 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1188 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1189 void intel_edp_panel_on(struct intel_dp *intel_dp);
1190 void intel_edp_panel_off(struct intel_dp *intel_dp);
1191 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1192 void intel_dp_mst_suspend(struct drm_device *dev);
1193 void intel_dp_mst_resume(struct drm_device *dev);
1194 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1195 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1196 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1197 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1198 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1199 void intel_plane_destroy(struct drm_plane *plane);
1200 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1201 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1202 void intel_edp_drrs_invalidate(struct drm_device *dev,
1203                 unsigned frontbuffer_bits);
1204 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1205
1206 /* intel_dp_mst.c */
1207 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1208 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1209 /* intel_dsi.c */
1210 void intel_dsi_init(struct drm_device *dev);
1211
1212
1213 /* intel_dvo.c */
1214 void intel_dvo_init(struct drm_device *dev);
1215
1216
1217 /* legacy fbdev emulation in intel_fbdev.c */
1218 #ifdef CONFIG_DRM_I915_FBDEV
1219 extern int intel_fbdev_init(struct drm_device *dev);
1220 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1221 extern void intel_fbdev_fini(struct drm_device *dev);
1222 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1223 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1224 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1225 #else
1226 static inline int intel_fbdev_init(struct drm_device *dev)
1227 {
1228         return 0;
1229 }
1230
1231 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1232 {
1233 }
1234
1235 static inline void intel_fbdev_fini(struct drm_device *dev)
1236 {
1237 }
1238
1239 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1240 {
1241 }
1242
1243 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1244 {
1245 }
1246 #endif
1247
1248 /* intel_fbc.c */
1249 bool intel_fbc_enabled(struct drm_device *dev);
1250 void intel_fbc_update(struct drm_device *dev);
1251 void intel_fbc_init(struct drm_i915_private *dev_priv);
1252 void intel_fbc_disable(struct drm_device *dev);
1253 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1254                           unsigned int frontbuffer_bits,
1255                           enum fb_op_origin origin);
1256 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1257                      unsigned int frontbuffer_bits);
1258 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1259
1260 /* intel_hdmi.c */
1261 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1262 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1263                                struct intel_connector *intel_connector);
1264 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1265 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1266                                struct intel_crtc_state *pipe_config);
1267
1268
1269 /* intel_lvds.c */
1270 void intel_lvds_init(struct drm_device *dev);
1271 bool intel_is_dual_link_lvds(struct drm_device *dev);
1272
1273
1274 /* intel_modes.c */
1275 int intel_connector_update_modes(struct drm_connector *connector,
1276                                  struct edid *edid);
1277 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1278 void intel_attach_force_audio_property(struct drm_connector *connector);
1279 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1280
1281
1282 /* intel_overlay.c */
1283 void intel_setup_overlay(struct drm_device *dev);
1284 void intel_cleanup_overlay(struct drm_device *dev);
1285 int intel_overlay_switch_off(struct intel_overlay *overlay);
1286 int intel_overlay_put_image(struct drm_device *dev, void *data,
1287                             struct drm_file *file_priv);
1288 int intel_overlay_attrs(struct drm_device *dev, void *data,
1289                         struct drm_file *file_priv);
1290 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1291
1292
1293 /* intel_panel.c */
1294 int intel_panel_init(struct intel_panel *panel,
1295                      struct drm_display_mode *fixed_mode,
1296                      struct drm_display_mode *downclock_mode);
1297 void intel_panel_fini(struct intel_panel *panel);
1298 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1299                             struct drm_display_mode *adjusted_mode);
1300 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1301                              struct intel_crtc_state *pipe_config,
1302                              int fitting_mode);
1303 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1304                               struct intel_crtc_state *pipe_config,
1305                               int fitting_mode);
1306 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1307                                     u32 level, u32 max);
1308 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1309 void intel_panel_enable_backlight(struct intel_connector *connector);
1310 void intel_panel_disable_backlight(struct intel_connector *connector);
1311 void intel_panel_destroy_backlight(struct drm_connector *connector);
1312 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1313 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1314 extern struct drm_display_mode *intel_find_panel_downclock(
1315                                 struct drm_device *dev,
1316                                 struct drm_display_mode *fixed_mode,
1317                                 struct drm_connector *connector);
1318 void intel_backlight_register(struct drm_device *dev);
1319 void intel_backlight_unregister(struct drm_device *dev);
1320
1321
1322 /* intel_psr.c */
1323 void intel_psr_enable(struct intel_dp *intel_dp);
1324 void intel_psr_disable(struct intel_dp *intel_dp);
1325 void intel_psr_invalidate(struct drm_device *dev,
1326                           unsigned frontbuffer_bits);
1327 void intel_psr_flush(struct drm_device *dev,
1328                      unsigned frontbuffer_bits);
1329 void intel_psr_init(struct drm_device *dev);
1330 void intel_psr_single_frame_update(struct drm_device *dev,
1331                                    unsigned frontbuffer_bits);
1332
1333 /* intel_runtime_pm.c */
1334 int intel_power_domains_init(struct drm_i915_private *);
1335 void intel_power_domains_fini(struct drm_i915_private *);
1336 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1337 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1338
1339 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1340                                     enum intel_display_power_domain domain);
1341 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1342                                       enum intel_display_power_domain domain);
1343 void intel_display_power_get(struct drm_i915_private *dev_priv,
1344                              enum intel_display_power_domain domain);
1345 void intel_display_power_put(struct drm_i915_private *dev_priv,
1346                              enum intel_display_power_domain domain);
1347 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1348 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1349 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1350 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1351 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1352
1353 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1354
1355 /* intel_pm.c */
1356 void intel_init_clock_gating(struct drm_device *dev);
1357 void intel_suspend_hw(struct drm_device *dev);
1358 int ilk_wm_max_level(const struct drm_device *dev);
1359 void intel_update_watermarks(struct drm_crtc *crtc);
1360 void intel_update_sprite_watermarks(struct drm_plane *plane,
1361                                     struct drm_crtc *crtc,
1362                                     uint32_t sprite_width,
1363                                     uint32_t sprite_height,
1364                                     int pixel_size,
1365                                     bool enabled, bool scaled);
1366 void intel_init_pm(struct drm_device *dev);
1367 void intel_pm_setup(struct drm_device *dev);
1368 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1369 void intel_gpu_ips_teardown(void);
1370 void intel_init_gt_powersave(struct drm_device *dev);
1371 void intel_cleanup_gt_powersave(struct drm_device *dev);
1372 void intel_enable_gt_powersave(struct drm_device *dev);
1373 void intel_disable_gt_powersave(struct drm_device *dev);
1374 void intel_suspend_gt_powersave(struct drm_device *dev);
1375 void intel_reset_gt_powersave(struct drm_device *dev);
1376 void gen6_update_ring_freq(struct drm_device *dev);
1377 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1378 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1379 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1380 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1381                     struct intel_rps_client *rps,
1382                     unsigned long submitted);
1383 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1384                                        struct drm_i915_gem_request *req);
1385 void vlv_wm_get_hw_state(struct drm_device *dev);
1386 void ilk_wm_get_hw_state(struct drm_device *dev);
1387 void skl_wm_get_hw_state(struct drm_device *dev);
1388 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1389                           struct skl_ddb_allocation *ddb /* out */);
1390 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1391
1392 /* intel_sdvo.c */
1393 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1394
1395
1396 /* intel_sprite.c */
1397 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1398 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1399                               struct drm_file *file_priv);
1400 bool intel_pipe_update_start(struct intel_crtc *crtc,
1401                              uint32_t *start_vbl_count);
1402 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1403
1404 /* intel_tv.c */
1405 void intel_tv_init(struct drm_device *dev);
1406
1407 /* intel_atomic.c */
1408 int intel_atomic_check(struct drm_device *dev,
1409                        struct drm_atomic_state *state);
1410 int intel_atomic_commit(struct drm_device *dev,
1411                         struct drm_atomic_state *state,
1412                         bool async);
1413 int intel_connector_atomic_get_property(struct drm_connector *connector,
1414                                         const struct drm_connector_state *state,
1415                                         struct drm_property *property,
1416                                         uint64_t *val);
1417 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1418 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1419                                struct drm_crtc_state *state);
1420 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1421 void intel_atomic_state_clear(struct drm_atomic_state *);
1422 struct intel_shared_dpll_config *
1423 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1424
1425 static inline struct intel_crtc_state *
1426 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1427                             struct intel_crtc *crtc)
1428 {
1429         struct drm_crtc_state *crtc_state;
1430         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1431         if (IS_ERR(crtc_state))
1432                 return ERR_CAST(crtc_state);
1433
1434         return to_intel_crtc_state(crtc_state);
1435 }
1436 int intel_atomic_setup_scalers(struct drm_device *dev,
1437         struct intel_crtc *intel_crtc,
1438         struct intel_crtc_state *crtc_state);
1439
1440 /* intel_atomic_plane.c */
1441 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1442 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1443 void intel_plane_destroy_state(struct drm_plane *plane,
1444                                struct drm_plane_state *state);
1445 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1446
1447 #endif /* __INTEL_DRV_H__ */