drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42 #include <media/cec-notifier.h>
  43
  44 /**
  45  * __wait_for - magic wait macro
  46  *
  47  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  48  * important that we check the condition again after having timed out, since the
  49  * timeout could be due to preemption or similar and we've never had a chance to
  50  * check the condition before the timeout.
  51  */
  52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  53         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  54         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  55         int ret__;                                                      \
  56         might_sleep();                                                  \
  57         for (;;) {                                                      \
  58                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  59                 OP;                                                     \
  60                 /* Guarantee COND check prior to timeout */             \
  61                 barrier();                                              \
  62                 if (COND) {                                             \
  63                         ret__ = 0;                                      \
  64                         break;                                          \
  65                 }                                                       \
  66                 if (expired__) {                                        \
  67                         ret__ = -ETIMEDOUT;                             \
  68                         break;                                          \
  69                 }                                                       \
  70                 usleep_range(wait__, wait__ * 2);                       \
  71                 if (wait__ < (Wmax))                                    \
  72                         wait__ <<= 1;                                   \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  78                                                    (Wmax))
  79 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  80
  81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  84 #else
  85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  86 #endif
  87
  88 #define _wait_for_atomic(COND, US, ATOMIC) \
  89 ({ \
  90         int cpu, ret, timeout = (US) * 1000; \
  91         u64 base; \
  92         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  93         if (!(ATOMIC)) { \
  94                 preempt_disable(); \
  95                 cpu = smp_processor_id(); \
  96         } \
  97         base = local_clock(); \
  98         for (;;) { \
  99                 u64 now = local_clock(); \
 100                 if (!(ATOMIC)) \
 101                         preempt_enable(); \
 102                 /* Guarantee COND check prior to timeout */ \
 103                 barrier(); \
 104                 if (COND) { \
 105                         ret = 0; \
 106                         break; \
 107                 } \
 108                 if (now - base >= timeout) { \
 109                         ret = -ETIMEDOUT; \
 110                         break; \
 111                 } \
 112                 cpu_relax(); \
 113                 if (!(ATOMIC)) { \
 114                         preempt_disable(); \
 115                         if (unlikely(cpu != smp_processor_id())) { \
 116                                 timeout -= now - base; \
 117                                 cpu = smp_processor_id(); \
 118                                 base = local_clock(); \
 119                         } \
 120                 } \
 121         } \
 122         ret; \
 123 })
 124
 125 #define wait_for_us(COND, US) \
 126 ({ \
 127         int ret__; \
 128         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 129         if ((US) > 10) \
 130                 ret__ = _wait_for((COND), (US), 10, 10); \
 131         else \
 132                 ret__ = _wait_for_atomic((COND), (US), 0); \
 133         ret__; \
 134 })
 135
 136 #define wait_for_atomic_us(COND, US) \
 137 ({ \
 138         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 139         BUILD_BUG_ON((US) > 50000); \
 140         _wait_for_atomic((COND), (US), 1); \
 141 })
 142
 143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 144
 145 #define KHz(x) (1000 * (x))
 146 #define MHz(x) KHz(1000 * (x))
 147
 148 #define KBps(x) (1000 * (x))
 149 #define MBps(x) KBps(1000 * (x))
 150 #define GBps(x) ((u64)1000 * MBps((x)))
 151
 152 /*
 153  * Display related stuff
 154  */
 155
 156 /* store information about an Ixxx DVO */
 157 /* The i830->i865 use multiple DVOs with multiple i2cs */
 158 /* the i915, i945 have a single sDVO i2c bus - which is different */
 159 #define MAX_OUTPUTS 6
 160 /* maximum connectors per crtcs in the mode set */
 161
 162 #define INTEL_I2C_BUS_DVO 1
 163 #define INTEL_I2C_BUS_SDVO 2
 164
 165 /* these are outputs from the chip - integrated only
 166    external chips are via DVO or SDVO output */
 167 enum intel_output_type {
 168         INTEL_OUTPUT_UNUSED = 0,
 169         INTEL_OUTPUT_ANALOG = 1,
 170         INTEL_OUTPUT_DVO = 2,
 171         INTEL_OUTPUT_SDVO = 3,
 172         INTEL_OUTPUT_LVDS = 4,
 173         INTEL_OUTPUT_TVOUT = 5,
 174         INTEL_OUTPUT_HDMI = 6,
 175         INTEL_OUTPUT_DP = 7,
 176         INTEL_OUTPUT_EDP = 8,
 177         INTEL_OUTPUT_DSI = 9,
 178         INTEL_OUTPUT_DDI = 10,
 179         INTEL_OUTPUT_DP_MST = 11,
 180 };
 181
 182 #define INTEL_DVO_CHIP_NONE 0
 183 #define INTEL_DVO_CHIP_LVDS 1
 184 #define INTEL_DVO_CHIP_TMDS 2
 185 #define INTEL_DVO_CHIP_TVOUT 4
 186
 187 #define INTEL_DSI_VIDEO_MODE    0
 188 #define INTEL_DSI_COMMAND_MODE  1
 189
 190 struct intel_framebuffer {
 191         struct drm_framebuffer base;
 192         struct intel_rotation_info rot_info;
 193
 194         /* for each plane in the normal GTT view */
 195         struct {
 196                 unsigned int x, y;
 197         } normal[2];
 198         /* for each plane in the rotated GTT view */
 199         struct {
 200                 unsigned int x, y;
 201                 unsigned int pitch; /* pixels */
 202         } rotated[2];
 203 };
 204
 205 struct intel_fbdev {
 206         struct drm_fb_helper helper;
 207         struct intel_framebuffer *fb;
 208         struct i915_vma *vma;
 209         unsigned long vma_flags;
 210         async_cookie_t cookie;
 211         int preferred_bpp;
 212 };
 213
 214 struct intel_encoder {
 215         struct drm_encoder base;
 216
 217         enum intel_output_type type;
 218         enum port port;
 219         unsigned int cloneable;
 220         bool (*hotplug)(struct intel_encoder *encoder,
 221                         struct intel_connector *connector);
 222         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 223                                                       struct intel_crtc_state *,
 224                                                       struct drm_connector_state *);
 225         bool (*compute_config)(struct intel_encoder *,
 226                                struct intel_crtc_state *,
 227                                struct drm_connector_state *);
 228         void (*pre_pll_enable)(struct intel_encoder *,
 229                                const struct intel_crtc_state *,
 230                                const struct drm_connector_state *);
 231         void (*pre_enable)(struct intel_encoder *,
 232                            const struct intel_crtc_state *,
 233                            const struct drm_connector_state *);
 234         void (*enable)(struct intel_encoder *,
 235                        const struct intel_crtc_state *,
 236                        const struct drm_connector_state *);
 237         void (*disable)(struct intel_encoder *,
 238                         const struct intel_crtc_state *,
 239                         const struct drm_connector_state *);
 240         void (*post_disable)(struct intel_encoder *,
 241                              const struct intel_crtc_state *,
 242                              const struct drm_connector_state *);
 243         void (*post_pll_disable)(struct intel_encoder *,
 244                                  const struct intel_crtc_state *,
 245                                  const struct drm_connector_state *);
 246         /* Read out the current hw state of this connector, returning true if
 247          * the encoder is active. If the encoder is enabled it also set the pipe
 248          * it is connected to in the pipe parameter. */
 249         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 250         /* Reconstructs the equivalent mode flags for the current hardware
 251          * state. This must be called _after_ display->get_pipe_config has
 252          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 253          * be set correctly before calling this function. */
 254         void (*get_config)(struct intel_encoder *,
 255                            struct intel_crtc_state *pipe_config);
 256         /* Returns a mask of power domains that need to be referenced as part
 257          * of the hardware state readout code. */
 258         u64 (*get_power_domains)(struct intel_encoder *encoder,
 259                                  struct intel_crtc_state *crtc_state);
 260         /*
 261          * Called during system suspend after all pending requests for the
 262          * encoder are flushed (for example for DP AUX transactions) and
 263          * device interrupts are disabled.
 264          */
 265         void (*suspend)(struct intel_encoder *);
 266         int crtc_mask;
 267         enum hpd_pin hpd_pin;
 268         enum intel_display_power_domain power_domain;
 269         /* for communication with audio component; protected by av_mutex */
 270         const struct drm_connector *audio_connector;
 271 };
 272
 273 struct intel_panel {
 274         struct drm_display_mode *fixed_mode;
 275         struct drm_display_mode *downclock_mode;
 276
 277         /* backlight */
 278         struct {
 279                 bool present;
 280                 u32 level;
 281                 u32 min;
 282                 u32 max;
 283                 bool enabled;
 284                 bool combination_mode;  /* gen 2/4 only */
 285                 bool active_low_pwm;
 286                 bool alternate_pwm_increment;   /* lpt+ */
 287
 288                 /* PWM chip */
 289                 bool util_pin_active_low;       /* bxt+ */
 290                 u8 controller;          /* bxt+ only */
 291                 struct pwm_device *pwm;
 292
 293                 struct backlight_device *device;
 294
 295                 /* Connector and platform specific backlight functions */
 296                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 297                 uint32_t (*get)(struct intel_connector *connector);
 298                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 299                 void (*disable)(const struct drm_connector_state *conn_state);
 300                 void (*enable)(const struct intel_crtc_state *crtc_state,
 301                                const struct drm_connector_state *conn_state);
 302                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 303                                       uint32_t hz);
 304                 void (*power)(struct intel_connector *, bool enable);
 305         } backlight;
 306 };
 307
 308 struct intel_digital_port;
 309
 310 /*
 311  * This structure serves as a translation layer between the generic HDCP code
 312  * and the bus-specific code. What that means is that HDCP over HDMI differs
 313  * from HDCP over DP, so to account for these differences, we need to
 314  * communicate with the receiver through this shim.
 315  *
 316  * For completeness, the 2 buses differ in the following ways:
 317  *      - DP AUX vs. DDC
 318  *              HDCP registers on the receiver are set via DP AUX for DP, and
 319  *              they are set via DDC for HDMI.
 320  *      - Receiver register offsets
 321  *              The offsets of the registers are different for DP vs. HDMI
 322  *      - Receiver register masks/offsets
 323  *              For instance, the ready bit for the KSV fifo is in a different
 324  *              place on DP vs HDMI
 325  *      - Receiver register names
 326  *              Seriously. In the DP spec, the 16-bit register containing
 327  *              downstream information is called BINFO, on HDMI it's called
 328  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 329  *              with a completely different definition.
 330  *      - KSV FIFO
 331  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 332  *              be read 3 keys at a time
 333  *      - Aksv output
 334  *              Since Aksv is hidden in hardware, there's different procedures
 335  *              to send it over DP AUX vs DDC
 336  */
 337 struct intel_hdcp_shim {
 338         /* Outputs the transmitter's An and Aksv values to the receiver. */
 339         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 340
 341         /* Reads the receiver's key selection vector */
 342         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 343
 344         /*
 345          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 346          * definitions are the same in the respective specs, but the names are
 347          * different. Call it BSTATUS since that's the name the HDMI spec
 348          * uses and it was there first.
 349          */
 350         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 351                             u8 *bstatus);
 352
 353         /* Determines whether a repeater is present downstream */
 354         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 355                                 bool *repeater_present);
 356
 357         /* Reads the receiver's Ri' value */
 358         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 359
 360         /* Determines if the receiver's KSV FIFO is ready for consumption */
 361         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 362                               bool *ksv_ready);
 363
 364         /* Reads the ksv fifo for num_downstream devices */
 365         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 366                              int num_downstream, u8 *ksv_fifo);
 367
 368         /* Reads a 32-bit part of V' from the receiver */
 369         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 370                                  int i, u32 *part);
 371
 372         /* Enables HDCP signalling on the port */
 373         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 374                                  bool enable);
 375
 376         /* Ensures the link is still protected */
 377         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 378
 379         /* Detects panel's hdcp capability. This is optional for HDMI. */
 380         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 381                             bool *hdcp_capable);
 382 };
 383
 384 struct intel_hdcp {
 385         const struct intel_hdcp_shim *shim;
 386         /* Mutex for hdcp state of the connector */
 387         struct mutex mutex;
 388         u64 value;
 389         struct delayed_work check_work;
 390         struct work_struct prop_work;
 391 };
 392
 393 struct intel_connector {
 394         struct drm_connector base;
 395         /*
 396          * The fixed encoder this connector is connected to.
 397          */
 398         struct intel_encoder *encoder;
 399
 400         /* ACPI device id for ACPI and driver cooperation */
 401         u32 acpi_device_id;
 402
 403         /* Reads out the current hw, returning true if the connector is enabled
 404          * and active (i.e. dpms ON state). */
 405         bool (*get_hw_state)(struct intel_connector *);
 406
 407         /* Panel info for eDP and LVDS */
 408         struct intel_panel panel;
 409
 410         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 411         struct edid *edid;
 412         struct edid *detect_edid;
 413
 414         /* since POLL and HPD connectors may use the same HPD line keep the native
 415            state of connector->polled in case hotplug storm detection changes it */
 416         u8 polled;
 417
 418         void *port; /* store this opaque as its illegal to dereference it */
 419
 420         struct intel_dp *mst_port;
 421
 422         /* Work struct to schedule a uevent on link train failure */
 423         struct work_struct modeset_retry_work;
 424
 425         struct intel_hdcp hdcp;
 426 };
 427
 428 struct intel_digital_connector_state {
 429         struct drm_connector_state base;
 430
 431         enum hdmi_force_audio force_audio;
 432         int broadcast_rgb;
 433 };
 434
 435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 436
 437 struct dpll {
 438         /* given values */
 439         int n;
 440         int m1, m2;
 441         int p1, p2;
 442         /* derived values */
 443         int     dot;
 444         int     vco;
 445         int     m;
 446         int     p;
 447 };
 448
 449 struct intel_atomic_state {
 450         struct drm_atomic_state base;
 451
 452         struct {
 453                 /*
 454                  * Logical state of cdclk (used for all scaling, watermark,
 455                  * etc. calculations and checks). This is computed as if all
 456                  * enabled crtcs were active.
 457                  */
 458                 struct intel_cdclk_state logical;
 459
 460                 /*
 461                  * Actual state of cdclk, can be different from the logical
 462                  * state only when all crtc's are DPMS off.
 463                  */
 464                 struct intel_cdclk_state actual;
 465         } cdclk;
 466
 467         bool dpll_set, modeset;
 468
 469         /*
 470          * Does this transaction change the pipes that are active?  This mask
 471          * tracks which CRTC's have changed their active state at the end of
 472          * the transaction (not counting the temporary disable during modesets).
 473          * This mask should only be non-zero when intel_state->modeset is true,
 474          * but the converse is not necessarily true; simply changing a mode may
 475          * not flip the final active status of any CRTC's
 476          */
 477         unsigned int active_pipe_changes;
 478
 479         unsigned int active_crtcs;
 480         /* minimum acceptable cdclk for each pipe */
 481         int min_cdclk[I915_MAX_PIPES];
 482         /* minimum acceptable voltage level for each pipe */
 483         u8 min_voltage_level[I915_MAX_PIPES];
 484
 485         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 486
 487         /*
 488          * Current watermarks can't be trusted during hardware readout, so
 489          * don't bother calculating intermediate watermarks.
 490          */
 491         bool skip_intermediate_wm;
 492
 493         bool rps_interactive;
 494
 495         /* Gen9+ only */
 496         struct skl_ddb_values wm_results;
 497
 498         struct i915_sw_fence commit_ready;
 499
 500         struct llist_node freed;
 501 };
 502
 503 struct intel_plane_state {
 504         struct drm_plane_state base;
 505         struct i915_ggtt_view view;
 506         struct i915_vma *vma;
 507         unsigned long flags;
 508 #define PLANE_HAS_FENCE BIT(0)
 509
 510         struct {
 511                 u32 offset;
 512                 /*
 513                  * Plane stride in:
 514                  * bytes for 0/180 degree rotation
 515                  * pixels for 90/270 degree rotation
 516                  */
 517                 u32 stride;
 518                 int x, y;
 519         } color_plane[2];
 520
 521         /* plane control register */
 522         u32 ctl;
 523
 524         /* plane color control register */
 525         u32 color_ctl;
 526
 527         /*
 528          * scaler_id
 529          *    = -1 : not using a scaler
 530          *    >=  0 : using a scalers
 531          *
 532          * plane requiring a scaler:
 533          *   - During check_plane, its bit is set in
 534          *     crtc_state->scaler_state.scaler_users by calling helper function
 535          *     update_scaler_plane.
 536          *   - scaler_id indicates the scaler it got assigned.
 537          *
 538          * plane doesn't require a scaler:
 539          *   - this can happen when scaling is no more required or plane simply
 540          *     got disabled.
 541          *   - During check_plane, corresponding bit is reset in
 542          *     crtc_state->scaler_state.scaler_users by calling helper function
 543          *     update_scaler_plane.
 544          */
 545         int scaler_id;
 546
 547         /*
 548          * linked_plane:
 549          *
 550          * ICL planar formats require 2 planes that are updated as pairs.
 551          * This member is used to make sure the other plane is also updated
 552          * when required, and for update_slave() to find the correct
 553          * plane_state to pass as argument.
 554          */
 555         struct intel_plane *linked_plane;
 556
 557         /*
 558          * slave:
 559          * If set don't update use the linked plane's state for updating
 560          * this plane during atomic commit with the update_slave() callback.
 561          *
 562          * It's also used by the watermark code to ignore wm calculations on
 563          * this plane. They're calculated by the linked plane's wm code.
 564          */
 565         u32 slave;
 566
 567         struct drm_intel_sprite_colorkey ckey;
 568 };
 569
 570 struct intel_initial_plane_config {
 571         struct intel_framebuffer *fb;
 572         unsigned int tiling;
 573         int size;
 574         u32 base;
 575         u8 rotation;
 576 };
 577
 578 #define SKL_MIN_SRC_W 8
 579 #define SKL_MAX_SRC_W 4096
 580 #define SKL_MIN_SRC_H 8
 581 #define SKL_MAX_SRC_H 4096
 582 #define SKL_MIN_DST_W 8
 583 #define SKL_MAX_DST_W 4096
 584 #define SKL_MIN_DST_H 8
 585 #define SKL_MAX_DST_H 4096
 586 #define ICL_MAX_SRC_W 5120
 587 #define ICL_MAX_SRC_H 4096
 588 #define ICL_MAX_DST_W 5120
 589 #define ICL_MAX_DST_H 4096
 590 #define SKL_MIN_YUV_420_SRC_W 16
 591 #define SKL_MIN_YUV_420_SRC_H 16
 592
 593 struct intel_scaler {
 594         int in_use;
 595         uint32_t mode;
 596 };
 597
 598 struct intel_crtc_scaler_state {
 599 #define SKL_NUM_SCALERS 2
 600         struct intel_scaler scalers[SKL_NUM_SCALERS];
 601
 602         /*
 603          * scaler_users: keeps track of users requesting scalers on this crtc.
 604          *
 605          *     If a bit is set, a user is using a scaler.
 606          *     Here user can be a plane or crtc as defined below:
 607          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 608          *       bit 31    - crtc
 609          *
 610          * Instead of creating a new index to cover planes and crtc, using
 611          * existing drm_plane_index for planes which is well less than 31
 612          * planes and bit 31 for crtc. This should be fine to cover all
 613          * our platforms.
 614          *
 615          * intel_atomic_setup_scalers will setup available scalers to users
 616          * requesting scalers. It will gracefully fail if request exceeds
 617          * avilability.
 618          */
 619 #define SKL_CRTC_INDEX 31
 620         unsigned scaler_users;
 621
 622         /* scaler used by crtc for panel fitting purpose */
 623         int scaler_id;
 624 };
 625
 626 /* drm_mode->private_flags */
 627 #define I915_MODE_FLAG_INHERITED 1
 628 /* Flag to get scanline using frame time stamps */
 629 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 630
 631 struct intel_pipe_wm {
 632         struct intel_wm_level wm[5];
 633         uint32_t linetime;
 634         bool fbc_wm_enabled;
 635         bool pipe_enabled;
 636         bool sprites_enabled;
 637         bool sprites_scaled;
 638 };
 639
 640 struct skl_plane_wm {
 641         struct skl_wm_level wm[8];
 642         struct skl_wm_level uv_wm[8];
 643         struct skl_wm_level trans_wm;
 644         bool is_planar;
 645 };
 646
 647 struct skl_pipe_wm {
 648         struct skl_plane_wm planes[I915_MAX_PLANES];
 649         uint32_t linetime;
 650 };
 651
 652 enum vlv_wm_level {
 653         VLV_WM_LEVEL_PM2,
 654         VLV_WM_LEVEL_PM5,
 655         VLV_WM_LEVEL_DDR_DVFS,
 656         NUM_VLV_WM_LEVELS,
 657 };
 658
 659 struct vlv_wm_state {
 660         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 661         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 662         uint8_t num_levels;
 663         bool cxsr;
 664 };
 665
 666 struct vlv_fifo_state {
 667         u16 plane[I915_MAX_PLANES];
 668 };
 669
 670 enum g4x_wm_level {
 671         G4X_WM_LEVEL_NORMAL,
 672         G4X_WM_LEVEL_SR,
 673         G4X_WM_LEVEL_HPLL,
 674         NUM_G4X_WM_LEVELS,
 675 };
 676
 677 struct g4x_wm_state {
 678         struct g4x_pipe_wm wm;
 679         struct g4x_sr_wm sr;
 680         struct g4x_sr_wm hpll;
 681         bool cxsr;
 682         bool hpll_en;
 683         bool fbc_en;
 684 };
 685
 686 struct intel_crtc_wm_state {
 687         union {
 688                 struct {
 689                         /*
 690                          * Intermediate watermarks; these can be
 691                          * programmed immediately since they satisfy
 692                          * both the current configuration we're
 693                          * switching away from and the new
 694                          * configuration we're switching to.
 695                          */
 696                         struct intel_pipe_wm intermediate;
 697
 698                         /*
 699                          * Optimal watermarks, programmed post-vblank
 700                          * when this state is committed.
 701                          */
 702                         struct intel_pipe_wm optimal;
 703                 } ilk;
 704
 705                 struct {
 706                         /* gen9+ only needs 1-step wm programming */
 707                         struct skl_pipe_wm optimal;
 708                         struct skl_ddb_entry ddb;
 709                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 710                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 711                 } skl;
 712
 713                 struct {
 714                         /* "raw" watermarks (not inverted) */
 715                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 716                         /* intermediate watermarks (inverted) */
 717                         struct vlv_wm_state intermediate;
 718                         /* optimal watermarks (inverted) */
 719                         struct vlv_wm_state optimal;
 720                         /* display FIFO split */
 721                         struct vlv_fifo_state fifo_state;
 722                 } vlv;
 723
 724                 struct {
 725                         /* "raw" watermarks */
 726                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 727                         /* intermediate watermarks */
 728                         struct g4x_wm_state intermediate;
 729                         /* optimal watermarks */
 730                         struct g4x_wm_state optimal;
 731                 } g4x;
 732         };
 733
 734         /*
 735          * Platforms with two-step watermark programming will need to
 736          * update watermark programming post-vblank to switch from the
 737          * safe intermediate watermarks to the optimal final
 738          * watermarks.
 739          */
 740         bool need_postvbl_update;
 741 };
 742
 743 enum intel_output_format {
 744         INTEL_OUTPUT_FORMAT_INVALID,
 745         INTEL_OUTPUT_FORMAT_RGB,
 746         INTEL_OUTPUT_FORMAT_YCBCR420,
 747         INTEL_OUTPUT_FORMAT_YCBCR444,
 748 };
 749
 750 struct intel_crtc_state {
 751         struct drm_crtc_state base;
 752
 753         /**
 754          * quirks - bitfield with hw state readout quirks
 755          *
 756          * For various reasons the hw state readout code might not be able to
 757          * completely faithfully read out the current state. These cases are
 758          * tracked with quirk flags so that fastboot and state checker can act
 759          * accordingly.
 760          */
 761 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 762         unsigned long quirks;
 763
 764         unsigned fb_bits; /* framebuffers to flip */
 765         bool update_pipe; /* can a fast modeset be performed? */
 766         bool disable_cxsr;
 767         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 768         bool fb_changed; /* fb on any of the planes is changed */
 769         bool fifo_changed; /* FIFO split is changed */
 770
 771         /* Pipe source size (ie. panel fitter input size)
 772          * All planes will be positioned inside this space,
 773          * and get clipped at the edges. */
 774         int pipe_src_w, pipe_src_h;
 775
 776         /*
 777          * Pipe pixel rate, adjusted for
 778          * panel fitter/pipe scaler downscaling.
 779          */
 780         unsigned int pixel_rate;
 781
 782         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 783          * between pch encoders and cpu encoders. */
 784         bool has_pch_encoder;
 785
 786         /* Are we sending infoframes on the attached port */
 787         bool has_infoframe;
 788
 789         /* CPU Transcoder for the pipe. Currently this can only differ from the
 790          * pipe on Haswell and later (where we have a special eDP transcoder)
 791          * and Broxton (where we have special DSI transcoders). */
 792         enum transcoder cpu_transcoder;
 793
 794         /*
 795          * Use reduced/limited/broadcast rbg range, compressing from the full
 796          * range fed into the crtcs.
 797          */
 798         bool limited_color_range;
 799
 800         /* Bitmask of encoder types (enum intel_output_type)
 801          * driven by the pipe.
 802          */
 803         unsigned int output_types;
 804
 805         /* Whether we should send NULL infoframes. Required for audio. */
 806         bool has_hdmi_sink;
 807
 808         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 809          * has_dp_encoder is set. */
 810         bool has_audio;
 811
 812         /*
 813          * Enable dithering, used when the selected pipe bpp doesn't match the
 814          * plane bpp.
 815          */
 816         bool dither;
 817
 818         /*
 819          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 820          * compliance video pattern tests.
 821          * Disable dither only if it is a compliance test request for
 822          * 18bpp.
 823          */
 824         bool dither_force_disable;
 825
 826         /* Controls for the clock computation, to override various stages. */
 827         bool clock_set;
 828
 829         /* SDVO TV has a bunch of special case. To make multifunction encoders
 830          * work correctly, we need to track this at runtime.*/
 831         bool sdvo_tv_clock;
 832
 833         /*
 834          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 835          * required. This is set in the 2nd loop of calling encoder's
 836          * ->compute_config if the first pick doesn't work out.
 837          */
 838         bool bw_constrained;
 839
 840         /* Settings for the intel dpll used on pretty much everything but
 841          * haswell. */
 842         struct dpll dpll;
 843
 844         /* Selected dpll when shared or NULL. */
 845         struct intel_shared_dpll *shared_dpll;
 846
 847         /* Actual register state of the dpll, for shared dpll cross-checking. */
 848         struct intel_dpll_hw_state dpll_hw_state;
 849
 850         /* DSI PLL registers */
 851         struct {
 852                 u32 ctrl, div;
 853         } dsi_pll;
 854
 855         int pipe_bpp;
 856         struct intel_link_m_n dp_m_n;
 857
 858         /* m2_n2 for eDP downclock */
 859         struct intel_link_m_n dp_m2_n2;
 860         bool has_drrs;
 861
 862         bool has_psr;
 863         bool has_psr2;
 864
 865         /*
 866          * Frequence the dpll for the port should run at. Differs from the
 867          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 868          * already multiplied by pixel_multiplier.
 869          */
 870         int port_clock;
 871
 872         /* Used by SDVO (and if we ever fix it, HDMI). */
 873         unsigned pixel_multiplier;
 874
 875         uint8_t lane_count;
 876
 877         /*
 878          * Used by platforms having DP/HDMI PHY with programmable lane
 879          * latency optimization.
 880          */
 881         uint8_t lane_lat_optim_mask;
 882
 883         /* minimum acceptable voltage level */
 884         u8 min_voltage_level;
 885
 886         /* Panel fitter controls for gen2-gen4 + VLV */
 887         struct {
 888                 u32 control;
 889                 u32 pgm_ratios;
 890                 u32 lvds_border_bits;
 891         } gmch_pfit;
 892
 893         /* Panel fitter placement and size for Ironlake+ */
 894         struct {
 895                 u32 pos;
 896                 u32 size;
 897                 bool enabled;
 898                 bool force_thru;
 899         } pch_pfit;
 900
 901         /* FDI configuration, only valid if has_pch_encoder is set. */
 902         int fdi_lanes;
 903         struct intel_link_m_n fdi_m_n;
 904
 905         bool ips_enabled;
 906         bool ips_force_disable;
 907
 908         bool enable_fbc;
 909
 910         bool double_wide;
 911
 912         int pbn;
 913
 914         struct intel_crtc_scaler_state scaler_state;
 915
 916         /* w/a for waiting 2 vblanks during crtc enable */
 917         enum pipe hsw_workaround_pipe;
 918
 919         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 920         bool disable_lp_wm;
 921
 922         struct intel_crtc_wm_state wm;
 923
 924         /* Gamma mode programmed on the pipe */
 925         uint32_t gamma_mode;
 926
 927         /* bitmask of visible planes (enum plane_id) */
 928         u8 active_planes;
 929         u8 nv12_planes;
 930
 931         /* bitmask of planes that will be updated during the commit */
 932         u8 update_planes;
 933
 934         /* HDMI scrambling status */
 935         bool hdmi_scrambling;
 936
 937         /* HDMI High TMDS char rate ratio */
 938         bool hdmi_high_tmds_clock_ratio;
 939
 940         /* Output format RGB/YCBCR etc */
 941         enum intel_output_format output_format;
 942
 943         /* Output down scaling is done in LSPCON device */
 944         bool lspcon_downsampling;
 945
 946         /* Display Stream compression state */
 947         struct {
 948                 bool compression_enable;
 949                 bool dsc_split;
 950                 u16 compressed_bpp;
 951                 u8 slice_count;
 952         } dsc_params;
 953         struct drm_dsc_config dp_dsc_cfg;
 954
 955         /* Forward Error correction State */
 956         bool fec_enable;
 957 };
 958
 959 struct intel_crtc {
 960         struct drm_crtc base;
 961         enum pipe pipe;
 962         /*
 963          * Whether the crtc and the connected output pipeline is active. Implies
 964          * that crtc->enabled is set, i.e. the current mode configuration has
 965          * some outputs connected to this crtc.
 966          */
 967         bool active;
 968         u8 plane_ids_mask;
 969         unsigned long long enabled_power_domains;
 970         struct intel_overlay *overlay;
 971
 972         struct intel_crtc_state *config;
 973
 974         /* global reset count when the last flip was submitted */
 975         unsigned int reset_count;
 976
 977         /* Access to these should be protected by dev_priv->irq_lock. */
 978         bool cpu_fifo_underrun_disabled;
 979         bool pch_fifo_underrun_disabled;
 980
 981         /* per-pipe watermark state */
 982         struct {
 983                 /* watermarks currently being used  */
 984                 union {
 985                         struct intel_pipe_wm ilk;
 986                         struct vlv_wm_state vlv;
 987                         struct g4x_wm_state g4x;
 988                 } active;
 989         } wm;
 990
 991         int scanline_offset;
 992
 993         struct {
 994                 unsigned start_vbl_count;
 995                 ktime_t start_vbl_time;
 996                 int min_vbl, max_vbl;
 997                 int scanline_start;
 998         } debug;
 999
1000         /* scalers available on this crtc */
1001         int num_scalers;
1002 };
1003
1004 struct intel_plane {
1005         struct drm_plane base;
1006         enum i9xx_plane_id i9xx_plane;
1007         enum plane_id id;
1008         enum pipe pipe;
1009         bool has_fbc;
1010         bool has_ccs;
1011         uint32_t frontbuffer_bit;
1012
1013         struct {
1014                 u32 base, cntl, size;
1015         } cursor;
1016
1017         /*
1018          * NOTE: Do not place new plane state fields here (e.g., when adding
1019          * new plane properties).  New runtime state should now be placed in
1020          * the intel_plane_state structure and accessed via plane_state.
1021          */
1022
1023         unsigned int (*max_stride)(struct intel_plane *plane,
1024                                    u32 pixel_format, u64 modifier,
1025                                    unsigned int rotation);
1026         void (*update_plane)(struct intel_plane *plane,
1027                              const struct intel_crtc_state *crtc_state,
1028                              const struct intel_plane_state *plane_state);
1029         void (*update_slave)(struct intel_plane *plane,
1030                              const struct intel_crtc_state *crtc_state,
1031                              const struct intel_plane_state *plane_state);
1032         void (*disable_plane)(struct intel_plane *plane,
1033                               const struct intel_crtc_state *crtc_state);
1034         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1035         int (*check_plane)(struct intel_crtc_state *crtc_state,
1036                            struct intel_plane_state *plane_state);
1037 };
1038
1039 struct intel_watermark_params {
1040         u16 fifo_size;
1041         u16 max_wm;
1042         u8 default_wm;
1043         u8 guard_size;
1044         u8 cacheline_size;
1045 };
1046
1047 struct cxsr_latency {
1048         bool is_desktop : 1;
1049         bool is_ddr3 : 1;
1050         u16 fsb_freq;
1051         u16 mem_freq;
1052         u16 display_sr;
1053         u16 display_hpll_disable;
1054         u16 cursor_sr;
1055         u16 cursor_hpll_disable;
1056 };
1057
1058 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1059 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1060 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1061 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1062 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1063 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1064 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1065 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1066 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1067
1068 struct intel_hdmi {
1069         i915_reg_t hdmi_reg;
1070         int ddc_bus;
1071         struct {
1072                 enum drm_dp_dual_mode_type type;
1073                 int max_tmds_clock;
1074         } dp_dual_mode;
1075         bool has_hdmi_sink;
1076         bool has_audio;
1077         struct intel_connector *attached_connector;
1078         struct cec_notifier *cec_notifier;
1079 };
1080
1081 struct intel_dp_mst_encoder;
1082 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1083
1084 /*
1085  * enum link_m_n_set:
1086  *      When platform provides two set of M_N registers for dp, we can
1087  *      program them and switch between them incase of DRRS.
1088  *      But When only one such register is provided, we have to program the
1089  *      required divider value on that registers itself based on the DRRS state.
1090  *
1091  * M1_N1        : Program dp_m_n on M1_N1 registers
1092  *                        dp_m2_n2 on M2_N2 registers (If supported)
1093  *
1094  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1095  *                        M2_N2 registers are not supported
1096  */
1097
1098 enum link_m_n_set {
1099         /* Sets the m1_n1 and m2_n2 */
1100         M1_N1 = 0,
1101         M2_N2
1102 };
1103
1104 struct intel_dp_compliance_data {
1105         unsigned long edid;
1106         uint8_t video_pattern;
1107         uint16_t hdisplay, vdisplay;
1108         uint8_t bpc;
1109 };
1110
1111 struct intel_dp_compliance {
1112         unsigned long test_type;
1113         struct intel_dp_compliance_data test_data;
1114         bool test_active;
1115         int test_link_rate;
1116         u8 test_lane_count;
1117 };
1118
1119 struct intel_dp {
1120         i915_reg_t output_reg;
1121         uint32_t DP;
1122         int link_rate;
1123         uint8_t lane_count;
1124         uint8_t sink_count;
1125         bool link_mst;
1126         bool link_trained;
1127         bool has_audio;
1128         bool reset_link_params;
1129         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1130         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1131         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1132         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1133         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1134         u8 fec_capable;
1135         /* source rates */
1136         int num_source_rates;
1137         const int *source_rates;
1138         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1139         int num_sink_rates;
1140         int sink_rates[DP_MAX_SUPPORTED_RATES];
1141         bool use_rate_select;
1142         /* intersection of source and sink rates */
1143         int num_common_rates;
1144         int common_rates[DP_MAX_SUPPORTED_RATES];
1145         /* Max lane count for the current link */
1146         int max_link_lane_count;
1147         /* Max rate for the current link */
1148         int max_link_rate;
1149         /* sink or branch descriptor */
1150         struct drm_dp_desc desc;
1151         struct drm_dp_aux aux;
1152         uint8_t train_set[4];
1153         int panel_power_up_delay;
1154         int panel_power_down_delay;
1155         int panel_power_cycle_delay;
1156         int backlight_on_delay;
1157         int backlight_off_delay;
1158         struct delayed_work panel_vdd_work;
1159         bool want_panel_vdd;
1160         unsigned long last_power_on;
1161         unsigned long last_backlight_off;
1162         ktime_t panel_power_off_time;
1163
1164         struct notifier_block edp_notifier;
1165
1166         /*
1167          * Pipe whose power sequencer is currently locked into
1168          * this port. Only relevant on VLV/CHV.
1169          */
1170         enum pipe pps_pipe;
1171         /*
1172          * Pipe currently driving the port. Used for preventing
1173          * the use of the PPS for any pipe currentrly driving
1174          * external DP as that will mess things up on VLV.
1175          */
1176         enum pipe active_pipe;
1177         /*
1178          * Set if the sequencer may be reset due to a power transition,
1179          * requiring a reinitialization. Only relevant on BXT.
1180          */
1181         bool pps_reset;
1182         struct edp_power_seq pps_delays;
1183
1184         bool can_mst; /* this port supports mst */
1185         bool is_mst;
1186         int active_mst_links;
1187         /* connector directly attached - won't be use for modeset in mst world */
1188         struct intel_connector *attached_connector;
1189
1190         /* mst connector list */
1191         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1192         struct drm_dp_mst_topology_mgr mst_mgr;
1193
1194         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1195         /*
1196          * This function returns the value we have to program the AUX_CTL
1197          * register with to kick off an AUX transaction.
1198          */
1199         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1200                                      int send_bytes,
1201                                      uint32_t aux_clock_divider);
1202
1203         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1204         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1205
1206         /* This is called before a link training is starterd */
1207         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1208
1209         /* Displayport compliance testing */
1210         struct intel_dp_compliance compliance;
1211 };
1212
1213 enum lspcon_vendor {
1214         LSPCON_VENDOR_MCA,
1215         LSPCON_VENDOR_PARADE
1216 };
1217
1218 struct intel_lspcon {
1219         bool active;
1220         enum drm_lspcon_mode mode;
1221         enum lspcon_vendor vendor;
1222 };
1223
1224 struct intel_digital_port {
1225         struct intel_encoder base;
1226         u32 saved_port_bits;
1227         struct intel_dp dp;
1228         struct intel_hdmi hdmi;
1229         struct intel_lspcon lspcon;
1230         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1231         bool release_cl2_override;
1232         uint8_t max_lanes;
1233         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1234         enum aux_ch aux_ch;
1235         enum intel_display_power_domain ddi_io_power_domain;
1236         enum tc_port_type tc_type;
1237
1238         void (*write_infoframe)(struct intel_encoder *encoder,
1239                                 const struct intel_crtc_state *crtc_state,
1240                                 unsigned int type,
1241                                 const void *frame, ssize_t len);
1242         void (*set_infoframes)(struct intel_encoder *encoder,
1243                                bool enable,
1244                                const struct intel_crtc_state *crtc_state,
1245                                const struct drm_connector_state *conn_state);
1246         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1247                                   const struct intel_crtc_state *pipe_config);
1248 };
1249
1250 struct intel_dp_mst_encoder {
1251         struct intel_encoder base;
1252         enum pipe pipe;
1253         struct intel_digital_port *primary;
1254         struct intel_connector *connector;
1255 };
1256
1257 static inline enum dpio_channel
1258 vlv_dport_to_channel(struct intel_digital_port *dport)
1259 {
1260         switch (dport->base.port) {
1261         case PORT_B:
1262         case PORT_D:
1263                 return DPIO_CH0;
1264         case PORT_C:
1265                 return DPIO_CH1;
1266         default:
1267                 BUG();
1268         }
1269 }
1270
1271 static inline enum dpio_phy
1272 vlv_dport_to_phy(struct intel_digital_port *dport)
1273 {
1274         switch (dport->base.port) {
1275         case PORT_B:
1276         case PORT_C:
1277                 return DPIO_PHY0;
1278         case PORT_D:
1279                 return DPIO_PHY1;
1280         default:
1281                 BUG();
1282         }
1283 }
1284
1285 static inline enum dpio_channel
1286 vlv_pipe_to_channel(enum pipe pipe)
1287 {
1288         switch (pipe) {
1289         case PIPE_A:
1290         case PIPE_C:
1291                 return DPIO_CH0;
1292         case PIPE_B:
1293                 return DPIO_CH1;
1294         default:
1295                 BUG();
1296         }
1297 }
1298
1299 static inline struct intel_crtc *
1300 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1301 {
1302         return dev_priv->pipe_to_crtc_mapping[pipe];
1303 }
1304
1305 static inline struct intel_crtc *
1306 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1307 {
1308         return dev_priv->plane_to_crtc_mapping[plane];
1309 }
1310
1311 struct intel_load_detect_pipe {
1312         struct drm_atomic_state *restore_state;
1313 };
1314
1315 static inline struct intel_encoder *
1316 intel_attached_encoder(struct drm_connector *connector)
1317 {
1318         return to_intel_connector(connector)->encoder;
1319 }
1320
1321 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1322 {
1323         switch (encoder->type) {
1324         case INTEL_OUTPUT_DDI:
1325         case INTEL_OUTPUT_DP:
1326         case INTEL_OUTPUT_EDP:
1327         case INTEL_OUTPUT_HDMI:
1328                 return true;
1329         default:
1330                 return false;
1331         }
1332 }
1333
1334 static inline struct intel_digital_port *
1335 enc_to_dig_port(struct drm_encoder *encoder)
1336 {
1337         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1338
1339         if (intel_encoder_is_dig_port(intel_encoder))
1340                 return container_of(encoder, struct intel_digital_port,
1341                                     base.base);
1342         else
1343                 return NULL;
1344 }
1345
1346 static inline struct intel_digital_port *
1347 conn_to_dig_port(struct intel_connector *connector)
1348 {
1349         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1350 }
1351
1352 static inline struct intel_dp_mst_encoder *
1353 enc_to_mst(struct drm_encoder *encoder)
1354 {
1355         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1356 }
1357
1358 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1359 {
1360         return &enc_to_dig_port(encoder)->dp;
1361 }
1362
1363 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1364 {
1365         switch (encoder->type) {
1366         case INTEL_OUTPUT_DP:
1367         case INTEL_OUTPUT_EDP:
1368                 return true;
1369         case INTEL_OUTPUT_DDI:
1370                 /* Skip pure HDMI/DVI DDI encoders */
1371                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1372         default:
1373                 return false;
1374         }
1375 }
1376
1377 static inline struct intel_lspcon *
1378 enc_to_intel_lspcon(struct drm_encoder *encoder)
1379 {
1380         return &enc_to_dig_port(encoder)->lspcon;
1381 }
1382
1383 static inline struct intel_digital_port *
1384 dp_to_dig_port(struct intel_dp *intel_dp)
1385 {
1386         return container_of(intel_dp, struct intel_digital_port, dp);
1387 }
1388
1389 static inline struct intel_lspcon *
1390 dp_to_lspcon(struct intel_dp *intel_dp)
1391 {
1392         return &dp_to_dig_port(intel_dp)->lspcon;
1393 }
1394
1395 static inline struct drm_i915_private *
1396 dp_to_i915(struct intel_dp *intel_dp)
1397 {
1398         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1399 }
1400
1401 static inline struct intel_digital_port *
1402 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1403 {
1404         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1405 }
1406
1407 static inline struct intel_plane_state *
1408 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1409                                  struct intel_plane *plane)
1410 {
1411         struct drm_plane_state *ret =
1412                 drm_atomic_get_plane_state(&state->base, &plane->base);
1413
1414         if (IS_ERR(ret))
1415                 return ERR_CAST(ret);
1416
1417         return to_intel_plane_state(ret);
1418 }
1419
1420 static inline struct intel_plane_state *
1421 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1422                                  struct intel_plane *plane)
1423 {
1424         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1425                                                                    &plane->base));
1426 }
1427
1428 static inline struct intel_plane_state *
1429 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1430                                  struct intel_plane *plane)
1431 {
1432         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1433                                                                    &plane->base));
1434 }
1435
1436 static inline struct intel_crtc_state *
1437 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1438                                 struct intel_crtc *crtc)
1439 {
1440         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1441                                                                  &crtc->base));
1442 }
1443
1444 static inline struct intel_crtc_state *
1445 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1446                                 struct intel_crtc *crtc)
1447 {
1448         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1449                                                                  &crtc->base));
1450 }
1451
1452 /* intel_fifo_underrun.c */
1453 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1454                                            enum pipe pipe, bool enable);
1455 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1456                                            enum pipe pch_transcoder,
1457                                            bool enable);
1458 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1459                                          enum pipe pipe);
1460 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1461                                          enum pipe pch_transcoder);
1462 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1463 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1464
1465 /* i915_irq.c */
1466 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1467 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1468 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1469 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1470 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1471 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1472 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1473 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1474
1475 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1476                                             u32 mask)
1477 {
1478         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1479 }
1480
1481 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1482 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1483 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1484 {
1485         /*
1486          * We only use drm_irq_uninstall() at unload and VT switch, so
1487          * this is the only thing we need to check.
1488          */
1489         return dev_priv->runtime_pm.irqs_enabled;
1490 }
1491
1492 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1493 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1494                                      u8 pipe_mask);
1495 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1496                                      u8 pipe_mask);
1497 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1498 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1499 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1500
1501 /* intel_crt.c */
1502 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1503                             i915_reg_t adpa_reg, enum pipe *pipe);
1504 void intel_crt_init(struct drm_i915_private *dev_priv);
1505 void intel_crt_reset(struct drm_encoder *encoder);
1506
1507 /* intel_ddi.c */
1508 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1509                                 const struct intel_crtc_state *old_crtc_state,
1510                                 const struct drm_connector_state *old_conn_state);
1511 void hsw_fdi_link_train(struct intel_crtc *crtc,
1512                         const struct intel_crtc_state *crtc_state);
1513 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1514 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1515 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1516 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1517 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1518 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1519 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1520 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1521 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1522 void intel_ddi_get_config(struct intel_encoder *encoder,
1523                           struct intel_crtc_state *pipe_config);
1524
1525 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1526                                     bool state);
1527 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1528                                          struct intel_crtc_state *crtc_state);
1529 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1530 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1531 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1532 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1533                                  u8 voltage_swing);
1534 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1535                                      bool enable);
1536 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1537 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1538                         enum intel_dpll_id pll_id);
1539
1540 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1541                                    int color_plane, unsigned int height);
1542
1543 /* intel_audio.c */
1544 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1545 void intel_audio_codec_enable(struct intel_encoder *encoder,
1546                               const struct intel_crtc_state *crtc_state,
1547                               const struct drm_connector_state *conn_state);
1548 void intel_audio_codec_disable(struct intel_encoder *encoder,
1549                                const struct intel_crtc_state *old_crtc_state,
1550                                const struct drm_connector_state *old_conn_state);
1551 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1552 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1553 void intel_audio_init(struct drm_i915_private *dev_priv);
1554 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1555
1556 /* intel_cdclk.c */
1557 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1558 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1559 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1560 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1561 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1562 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1563 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1564 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1565 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1566 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1567 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1568 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1569 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1570 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1571                                const struct intel_cdclk_state *b);
1572 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1573                          const struct intel_cdclk_state *b);
1574 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1575                      const struct intel_cdclk_state *cdclk_state);
1576 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1577                             const char *context);
1578
1579 /* intel_display.c */
1580 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1581 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1582 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1583 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1584 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1585                       const char *name, u32 reg, int ref_freq);
1586 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1587                            const char *name, u32 reg);
1588 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1589 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1590 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1591 unsigned int intel_fb_xy_to_linear(int x, int y,
1592                                    const struct intel_plane_state *state,
1593                                    int plane);
1594 void intel_add_fb_offsets(int *x, int *y,
1595                           const struct intel_plane_state *state, int plane);
1596 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1597 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1598 void intel_mark_busy(struct drm_i915_private *dev_priv);
1599 void intel_mark_idle(struct drm_i915_private *dev_priv);
1600 int intel_display_suspend(struct drm_device *dev);
1601 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1602 void intel_encoder_destroy(struct drm_encoder *encoder);
1603 struct drm_display_mode *
1604 intel_encoder_current_mode(struct intel_encoder *encoder);
1605 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1606 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1607 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1608                               enum port port);
1609 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1610                                       struct drm_file *file_priv);
1611 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1612                                              enum pipe pipe);
1613 static inline bool
1614 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1615                     enum intel_output_type type)
1616 {
1617         return crtc_state->output_types & (1 << type);
1618 }
1619 static inline bool
1620 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1621 {
1622         return crtc_state->output_types &
1623                 ((1 << INTEL_OUTPUT_DP) |
1624                  (1 << INTEL_OUTPUT_DP_MST) |
1625                  (1 << INTEL_OUTPUT_EDP));
1626 }
1627 static inline void
1628 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1629 {
1630         drm_wait_one_vblank(&dev_priv->drm, pipe);
1631 }
1632 static inline void
1633 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1634 {
1635         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1636
1637         if (crtc->active)
1638                 intel_wait_for_vblank(dev_priv, pipe);
1639 }
1640
1641 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1642
1643 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1644 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1645                          struct intel_digital_port *dport,
1646                          unsigned int expected_mask);
1647 int intel_get_load_detect_pipe(struct drm_connector *connector,
1648                                const struct drm_display_mode *mode,
1649                                struct intel_load_detect_pipe *old,
1650                                struct drm_modeset_acquire_ctx *ctx);
1651 void intel_release_load_detect_pipe(struct drm_connector *connector,
1652                                     struct intel_load_detect_pipe *old,
1653                                     struct drm_modeset_acquire_ctx *ctx);
1654 struct i915_vma *
1655 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1656                            const struct i915_ggtt_view *view,
1657                            bool uses_fence,
1658                            unsigned long *out_flags);
1659 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1660 struct drm_framebuffer *
1661 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1662                          struct drm_mode_fb_cmd2 *mode_cmd);
1663 int intel_prepare_plane_fb(struct drm_plane *plane,
1664                            struct drm_plane_state *new_state);
1665 void intel_cleanup_plane_fb(struct drm_plane *plane,
1666                             struct drm_plane_state *old_state);
1667 int intel_plane_atomic_get_property(struct drm_plane *plane,
1668                                     const struct drm_plane_state *state,
1669                                     struct drm_property *property,
1670                                     uint64_t *val);
1671 int intel_plane_atomic_set_property(struct drm_plane *plane,
1672                                     struct drm_plane_state *state,
1673                                     struct drm_property *property,
1674                                     uint64_t val);
1675 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1676                                     struct drm_crtc_state *crtc_state,
1677                                     const struct intel_plane_state *old_plane_state,
1678                                     struct drm_plane_state *plane_state);
1679
1680 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1681                                     enum pipe pipe);
1682
1683 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1684                      const struct dpll *dpll);
1685 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1686 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1687
1688 /* modesetting asserts */
1689 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1690                            enum pipe pipe);
1691 void assert_pll(struct drm_i915_private *dev_priv,
1692                 enum pipe pipe, bool state);
1693 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1694 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1695 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1696 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1697 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1698 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1699                        enum pipe pipe, bool state);
1700 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1701 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1702 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1703 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1704 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1705 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1706 void intel_finish_reset(struct drm_i915_private *dev_priv);
1707 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1708 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1709 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1710 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1711 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1712 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1713 unsigned int skl_cdclk_get_vco(unsigned int freq);
1714 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1715 void intel_dp_get_m_n(struct intel_crtc *crtc,
1716                       struct intel_crtc_state *pipe_config);
1717 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1718                       enum link_m_n_set m_n);
1719 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1720 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1721                         struct dpll *best_clock);
1722 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1723
1724 bool intel_crtc_active(struct intel_crtc *crtc);
1725 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1726 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1727 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1728 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1729 enum intel_display_power_domain
1730 intel_aux_power_domain(struct intel_digital_port *dig_port);
1731 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1732                                  struct intel_crtc_state *pipe_config);
1733 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1734                                   struct intel_crtc_state *crtc_state);
1735
1736 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1737 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1738 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1739                   u32 pixel_format);
1740
1741 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1742 {
1743         return i915_ggtt_offset(state->vma);
1744 }
1745
1746 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1747                         const struct intel_plane_state *plane_state);
1748 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1749                   const struct intel_plane_state *plane_state);
1750 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1751 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1752                      int plane);
1753 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1754 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1755 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1756 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1757                                    u32 pixel_format, u64 modifier,
1758                                    unsigned int rotation);
1759
1760 /* intel_connector.c */
1761 int intel_connector_init(struct intel_connector *connector);
1762 struct intel_connector *intel_connector_alloc(void);
1763 void intel_connector_free(struct intel_connector *connector);
1764 void intel_connector_destroy(struct drm_connector *connector);
1765 int intel_connector_register(struct drm_connector *connector);
1766 void intel_connector_unregister(struct drm_connector *connector);
1767 void intel_connector_attach_encoder(struct intel_connector *connector,
1768                                     struct intel_encoder *encoder);
1769 bool intel_connector_get_hw_state(struct intel_connector *connector);
1770 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1771 int intel_connector_update_modes(struct drm_connector *connector,
1772                                  struct edid *edid);
1773 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1774 void intel_attach_force_audio_property(struct drm_connector *connector);
1775 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1776 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1777
1778 /* intel_csr.c */
1779 void intel_csr_ucode_init(struct drm_i915_private *);
1780 void intel_csr_load_program(struct drm_i915_private *);
1781 void intel_csr_ucode_fini(struct drm_i915_private *);
1782 void intel_csr_ucode_suspend(struct drm_i915_private *);
1783 void intel_csr_ucode_resume(struct drm_i915_private *);
1784
1785 /* intel_dp.c */
1786 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1787                            i915_reg_t dp_reg, enum port port,
1788                            enum pipe *pipe);
1789 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1790                    enum port port);
1791 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1792                              struct intel_connector *intel_connector);
1793 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1794                               int link_rate, uint8_t lane_count,
1795                               bool link_mst);
1796 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1797                                             int link_rate, uint8_t lane_count);
1798 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1799 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1800 int intel_dp_retrain_link(struct intel_encoder *encoder,
1801                           struct drm_modeset_acquire_ctx *ctx);
1802 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1803 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1804                                            const struct intel_crtc_state *crtc_state,
1805                                            bool enable);
1806 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1807 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1808 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1809 bool intel_dp_compute_config(struct intel_encoder *encoder,
1810                              struct intel_crtc_state *pipe_config,
1811                              struct drm_connector_state *conn_state);
1812 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1813 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1814 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1815                                   bool long_hpd);
1816 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1817                             const struct drm_connector_state *conn_state);
1818 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1819 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1820 void intel_edp_panel_on(struct intel_dp *intel_dp);
1821 void intel_edp_panel_off(struct intel_dp *intel_dp);
1822 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1823 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1824 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1825 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1826 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1827 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1828 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1829 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1830 void intel_plane_destroy(struct drm_plane *plane);
1831 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1832                            const struct intel_crtc_state *crtc_state);
1833 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1834                             const struct intel_crtc_state *crtc_state);
1835 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1836                                unsigned int frontbuffer_bits);
1837 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1838                           unsigned int frontbuffer_bits);
1839
1840 void
1841 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1842                                        uint8_t dp_train_pat);
1843 void
1844 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1845 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1846 uint8_t
1847 intel_dp_voltage_max(struct intel_dp *intel_dp);
1848 uint8_t
1849 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1850 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1851                            uint8_t *link_bw, uint8_t *rate_select);
1852 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1853 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1854 bool
1855 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1856 uint16_t intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
1857                                      int mode_clock, int mode_hdisplay);
1858 uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1859                                      int mode_hdisplay);
1860
1861 /* intel_vdsc.c */
1862 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1863                                 struct intel_crtc_state *pipe_config);
1864 enum intel_display_power_domain
1865 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1866
1867 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1868 {
1869         return ~((1 << lane_count) - 1) & 0xf;
1870 }
1871
1872 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1873 int intel_dp_link_required(int pixel_clock, int bpp);
1874 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1875 bool intel_digital_port_connected(struct intel_encoder *encoder);
1876
1877 /* intel_dp_aux_backlight.c */
1878 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1879
1880 /* intel_dp_mst.c */
1881 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1882 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1883 /* vlv_dsi.c */
1884 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1885
1886 /* icl_dsi.c */
1887 void icl_dsi_init(struct drm_i915_private *dev_priv);
1888
1889 /* intel_dsi_dcs_backlight.c */
1890 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1891
1892 /* intel_dvo.c */
1893 void intel_dvo_init(struct drm_i915_private *dev_priv);
1894 /* intel_hotplug.c */
1895 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1896 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1897                            struct intel_connector *connector);
1898
1899 /* legacy fbdev emulation in intel_fbdev.c */
1900 #ifdef CONFIG_DRM_FBDEV_EMULATION
1901 extern int intel_fbdev_init(struct drm_device *dev);
1902 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1903 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1904 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1905 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1906 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1907 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1908 #else
1909 static inline int intel_fbdev_init(struct drm_device *dev)
1910 {
1911         return 0;
1912 }
1913
1914 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1915 {
1916 }
1917
1918 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1919 {
1920 }
1921
1922 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1923 {
1924 }
1925
1926 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1927 {
1928 }
1929
1930 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1931 {
1932 }
1933
1934 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1935 {
1936 }
1937 #endif
1938
1939 /* intel_fbc.c */
1940 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1941                            struct intel_atomic_state *state);
1942 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1943 void intel_fbc_pre_update(struct intel_crtc *crtc,
1944                           struct intel_crtc_state *crtc_state,
1945                           struct intel_plane_state *plane_state);
1946 void intel_fbc_post_update(struct intel_crtc *crtc);
1947 void intel_fbc_init(struct drm_i915_private *dev_priv);
1948 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1949 void intel_fbc_enable(struct intel_crtc *crtc,
1950                       struct intel_crtc_state *crtc_state,
1951                       struct intel_plane_state *plane_state);
1952 void intel_fbc_disable(struct intel_crtc *crtc);
1953 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1954 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1955                           unsigned int frontbuffer_bits,
1956                           enum fb_op_origin origin);
1957 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1958                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1959 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1960 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1961 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1962
1963 /* intel_hdmi.c */
1964 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1965                      enum port port);
1966 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1967                                struct intel_connector *intel_connector);
1968 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1969 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1970                                struct intel_crtc_state *pipe_config,
1971                                struct drm_connector_state *conn_state);
1972 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1973                                        struct drm_connector *connector,
1974                                        bool high_tmds_clock_ratio,
1975                                        bool scrambling);
1976 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1977 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1978
1979 /* intel_lvds.c */
1980 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1981                              i915_reg_t lvds_reg, enum pipe *pipe);
1982 void intel_lvds_init(struct drm_i915_private *dev_priv);
1983 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1984 bool intel_is_dual_link_lvds(struct drm_device *dev);
1985
1986 /* intel_overlay.c */
1987 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1988 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
1989 int intel_overlay_switch_off(struct intel_overlay *overlay);
1990 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1991                                   struct drm_file *file_priv);
1992 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1993                               struct drm_file *file_priv);
1994 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1995
1996
1997 /* intel_panel.c */
1998 int intel_panel_init(struct intel_panel *panel,
1999                      struct drm_display_mode *fixed_mode,
2000                      struct drm_display_mode *downclock_mode);
2001 void intel_panel_fini(struct intel_panel *panel);
2002 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2003                             struct drm_display_mode *adjusted_mode);
2004 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2005                              struct intel_crtc_state *pipe_config,
2006                              int fitting_mode);
2007 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2008                               struct intel_crtc_state *pipe_config,
2009                               int fitting_mode);
2010 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2011                                     u32 level, u32 max);
2012 int intel_panel_setup_backlight(struct drm_connector *connector,
2013                                 enum pipe pipe);
2014 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2015                                   const struct drm_connector_state *conn_state);
2016 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2017 extern struct drm_display_mode *intel_find_panel_downclock(
2018                                 struct drm_i915_private *dev_priv,
2019                                 struct drm_display_mode *fixed_mode,
2020                                 struct drm_connector *connector);
2021
2022 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2023 int intel_backlight_device_register(struct intel_connector *connector);
2024 void intel_backlight_device_unregister(struct intel_connector *connector);
2025 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2026 static inline int intel_backlight_device_register(struct intel_connector *connector)
2027 {
2028         return 0;
2029 }
2030 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2031 {
2032 }
2033 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2034
2035 /* intel_hdcp.c */
2036 void intel_hdcp_atomic_check(struct drm_connector *connector,
2037                              struct drm_connector_state *old_state,
2038                              struct drm_connector_state *new_state);
2039 int intel_hdcp_init(struct intel_connector *connector,
2040                     const struct intel_hdcp_shim *hdcp_shim);
2041 int intel_hdcp_enable(struct intel_connector *connector);
2042 int intel_hdcp_disable(struct intel_connector *connector);
2043 int intel_hdcp_check_link(struct intel_connector *connector);
2044 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2045 bool intel_hdcp_capable(struct intel_connector *connector);
2046
2047 /* intel_psr.c */
2048 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2049 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2050 void intel_psr_enable(struct intel_dp *intel_dp,
2051                       const struct intel_crtc_state *crtc_state);
2052 void intel_psr_disable(struct intel_dp *intel_dp,
2053                       const struct intel_crtc_state *old_crtc_state);
2054 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2055                                struct drm_modeset_acquire_ctx *ctx,
2056                                u64 value);
2057 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2058                           unsigned frontbuffer_bits,
2059                           enum fb_op_origin origin);
2060 void intel_psr_flush(struct drm_i915_private *dev_priv,
2061                      unsigned frontbuffer_bits,
2062                      enum fb_op_origin origin);
2063 void intel_psr_init(struct drm_i915_private *dev_priv);
2064 void intel_psr_compute_config(struct intel_dp *intel_dp,
2065                               struct intel_crtc_state *crtc_state);
2066 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2067 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2068 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2069 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2070                             u32 *out_value);
2071 bool intel_psr_enabled(struct intel_dp *intel_dp);
2072
2073 /* intel_quirks.c */
2074 void intel_init_quirks(struct drm_i915_private *dev_priv);
2075
2076 /* intel_runtime_pm.c */
2077 int intel_power_domains_init(struct drm_i915_private *);
2078 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2079 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2080 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2081 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2082 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2083 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2084 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2085
2086 enum i915_drm_suspend_mode {
2087         I915_DRM_SUSPEND_IDLE,
2088         I915_DRM_SUSPEND_MEM,
2089         I915_DRM_SUSPEND_HIBERNATE,
2090 };
2091
2092 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2093                                  enum i915_drm_suspend_mode);
2094 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2095 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2096 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2097 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2098 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2099 const char *
2100 intel_display_power_domain_str(enum intel_display_power_domain domain);
2101
2102 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2103                                     enum intel_display_power_domain domain);
2104 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2105                                       enum intel_display_power_domain domain);
2106 void intel_display_power_get(struct drm_i915_private *dev_priv,
2107                              enum intel_display_power_domain domain);
2108 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2109                                         enum intel_display_power_domain domain);
2110 void intel_display_power_put(struct drm_i915_private *dev_priv,
2111                              enum intel_display_power_domain domain);
2112 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2113                             u8 req_slices);
2114
2115 static inline void
2116 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
2117 {
2118         WARN_ONCE(dev_priv->runtime_pm.suspended,
2119                   "Device suspended during HW access\n");
2120 }
2121
2122 static inline void
2123 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
2124 {
2125         assert_rpm_device_not_suspended(dev_priv);
2126         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
2127                   "RPM wakelock ref not held during HW access");
2128 }
2129
2130 /**
2131  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2132  * @dev_priv: i915 device instance
2133  *
2134  * This function disable asserts that check if we hold an RPM wakelock
2135  * reference, while keeping the device-not-suspended checks still enabled.
2136  * It's meant to be used only in special circumstances where our rule about
2137  * the wakelock refcount wrt. the device power state doesn't hold. According
2138  * to this rule at any point where we access the HW or want to keep the HW in
2139  * an active state we must hold an RPM wakelock reference acquired via one of
2140  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2141  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2142  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2143  * users should avoid using this function.
2144  *
2145  * Any calls to this function must have a symmetric call to
2146  * enable_rpm_wakeref_asserts().
2147  */
2148 static inline void
2149 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2150 {
2151         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2152 }
2153
2154 /**
2155  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2156  * @dev_priv: i915 device instance
2157  *
2158  * This function re-enables the RPM assert checks after disabling them with
2159  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2160  * circumstances otherwise its use should be avoided.
2161  *
2162  * Any calls to this function must have a symmetric call to
2163  * disable_rpm_wakeref_asserts().
2164  */
2165 static inline void
2166 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2167 {
2168         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2169 }
2170
2171 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2172 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2173 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2174 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2175
2176 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2177                              bool override, unsigned int mask);
2178 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2179                           enum dpio_channel ch, bool override);
2180
2181
2182 /* intel_pm.c */
2183 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2184 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2185 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2186 void intel_update_watermarks(struct intel_crtc *crtc);
2187 void intel_init_pm(struct drm_i915_private *dev_priv);
2188 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2189 void intel_pm_setup(struct drm_i915_private *dev_priv);
2190 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2191 void intel_gpu_ips_teardown(void);
2192 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2193 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2194 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2195 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2196 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2197 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2198 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2199 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2200 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2201 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2202 void g4x_wm_get_hw_state(struct drm_device *dev);
2203 void vlv_wm_get_hw_state(struct drm_device *dev);
2204 void ilk_wm_get_hw_state(struct drm_device *dev);
2205 void skl_wm_get_hw_state(struct drm_device *dev);
2206 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2207                                struct skl_ddb_entry *ddb_y,
2208                                struct skl_ddb_entry *ddb_uv);
2209 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2210                           struct skl_ddb_allocation *ddb /* out */);
2211 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2212                               struct skl_pipe_wm *out);
2213 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2214 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2215 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2216 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2217 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2218 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2219                          const struct skl_wm_level *l2);
2220 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2221                                  const struct skl_ddb_entry entries[],
2222                                  int num_entries, int ignore_idx);
2223 void skl_write_plane_wm(struct intel_plane *plane,
2224                         const struct intel_crtc_state *crtc_state);
2225 void skl_write_cursor_wm(struct intel_plane *plane,
2226                          const struct intel_crtc_state *crtc_state);
2227 bool ilk_disable_lp_wm(struct drm_device *dev);
2228 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2229                                   struct intel_crtc_state *cstate);
2230 void intel_init_ipc(struct drm_i915_private *dev_priv);
2231 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2232
2233 /* intel_sdvo.c */
2234 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2235                              i915_reg_t sdvo_reg, enum pipe *pipe);
2236 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2237                      i915_reg_t reg, enum port port);
2238
2239
2240 /* intel_sprite.c */
2241 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2242                              int usecs);
2243 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2244                                               enum pipe pipe, int plane);
2245 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2246                                     struct drm_file *file_priv);
2247 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2248 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2249 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2250 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2251 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2252 struct intel_plane *
2253 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2254                            enum pipe pipe, enum plane_id plane_id);
2255
2256 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2257 {
2258         /* Don't need to do a gen check, these planes are only available on gen11 */
2259         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2260                 return true;
2261
2262         return false;
2263 }
2264
2265 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2266 {
2267         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2268                 return false;
2269
2270         return plane->id < PLANE_SPRITE2;
2271 }
2272
2273 /* intel_tv.c */
2274 void intel_tv_init(struct drm_i915_private *dev_priv);
2275
2276 /* intel_atomic.c */
2277 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2278                                                 const struct drm_connector_state *state,
2279                                                 struct drm_property *property,
2280                                                 uint64_t *val);
2281 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2282                                                 struct drm_connector_state *state,
2283                                                 struct drm_property *property,
2284                                                 uint64_t val);
2285 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2286                                          struct drm_connector_state *new_state);
2287 struct drm_connector_state *
2288 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2289
2290 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2291 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2292                                struct drm_crtc_state *state);
2293 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2294 void intel_atomic_state_clear(struct drm_atomic_state *);
2295
2296 static inline struct intel_crtc_state *
2297 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2298                             struct intel_crtc *crtc)
2299 {
2300         struct drm_crtc_state *crtc_state;
2301         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2302         if (IS_ERR(crtc_state))
2303                 return ERR_CAST(crtc_state);
2304
2305         return to_intel_crtc_state(crtc_state);
2306 }
2307
2308 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2309                                struct intel_crtc *intel_crtc,
2310                                struct intel_crtc_state *crtc_state);
2311
2312 /* intel_atomic_plane.c */
2313 struct intel_plane *intel_plane_alloc(void);
2314 void intel_plane_free(struct intel_plane *plane);
2315 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2316 void intel_plane_destroy_state(struct drm_plane *plane,
2317                                struct drm_plane_state *state);
2318 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2319 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2320                                struct intel_crtc *crtc);
2321 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2322                                 struct intel_crtc *crtc);
2323 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2324                                         struct intel_crtc_state *crtc_state,
2325                                         const struct intel_plane_state *old_plane_state,
2326                                         struct intel_plane_state *intel_state);
2327
2328 /* intel_color.c */
2329 void intel_color_init(struct drm_crtc *crtc);
2330 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2331 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2332 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2333
2334 /* intel_lspcon.c */
2335 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2336 void lspcon_resume(struct intel_lspcon *lspcon);
2337 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2338 void lspcon_write_infoframe(struct intel_encoder *encoder,
2339                             const struct intel_crtc_state *crtc_state,
2340                             unsigned int type,
2341                             const void *buf, ssize_t len);
2342 void lspcon_set_infoframes(struct intel_encoder *encoder,
2343                            bool enable,
2344                            const struct intel_crtc_state *crtc_state,
2345                            const struct drm_connector_state *conn_state);
2346 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2347                               const struct intel_crtc_state *pipe_config);
2348 void lspcon_ycbcr420_config(struct drm_connector *connector,
2349                             struct intel_crtc_state *crtc_state);
2350
2351 /* intel_pipe_crc.c */
2352 #ifdef CONFIG_DEBUG_FS
2353 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2354 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2355                                  const char *source_name, size_t *values_cnt);
2356 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2357                                               size_t *count);
2358 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2359 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2360 #else
2361 #define intel_crtc_set_crc_source NULL
2362 #define intel_crtc_verify_crc_source NULL
2363 #define intel_crtc_get_crc_sources NULL
2364 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2365 {
2366 }
2367
2368 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2369 {
2370 }
2371 #endif
2372 #endif /* __INTEL_DRV_H__ */