drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181
 182         /* for each plane in the normal GTT view */
 183         struct {
 184                 unsigned int x, y;
 185         } normal[2];
 186         /* for each plane in the rotated GTT view */
 187         struct {
 188                 unsigned int x, y;
 189                 unsigned int pitch; /* pixels */
 190         } rotated[2];
 191 };
 192
 193 struct intel_fbdev {
 194         struct drm_fb_helper helper;
 195         struct intel_framebuffer *fb;
 196         async_cookie_t cookie;
 197         int preferred_bpp;
 198 };
 199
 200 struct intel_encoder {
 201         struct drm_encoder base;
 202
 203         enum intel_output_type type;
 204         unsigned int cloneable;
 205         void (*hot_plug)(struct intel_encoder *);
 206         bool (*compute_config)(struct intel_encoder *,
 207                                struct intel_crtc_state *);
 208         void (*pre_pll_enable)(struct intel_encoder *);
 209         void (*pre_enable)(struct intel_encoder *);
 210         void (*enable)(struct intel_encoder *);
 211         void (*mode_set)(struct intel_encoder *intel_encoder);
 212         void (*disable)(struct intel_encoder *);
 213         void (*post_disable)(struct intel_encoder *);
 214         void (*post_pll_disable)(struct intel_encoder *);
 215         /* Read out the current hw state of this connector, returning true if
 216          * the encoder is active. If the encoder is enabled it also set the pipe
 217          * it is connected to in the pipe parameter. */
 218         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 219         /* Reconstructs the equivalent mode flags for the current hardware
 220          * state. This must be called _after_ display->get_pipe_config has
 221          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 222          * be set correctly before calling this function. */
 223         void (*get_config)(struct intel_encoder *,
 224                            struct intel_crtc_state *pipe_config);
 225         /*
 226          * Called during system suspend after all pending requests for the
 227          * encoder are flushed (for example for DP AUX transactions) and
 228          * device interrupts are disabled.
 229          */
 230         void (*suspend)(struct intel_encoder *);
 231         int crtc_mask;
 232         enum hpd_pin hpd_pin;
 233 };
 234
 235 struct intel_panel {
 236         struct drm_display_mode *fixed_mode;
 237         struct drm_display_mode *downclock_mode;
 238         int fitting_mode;
 239
 240         /* backlight */
 241         struct {
 242                 bool present;
 243                 u32 level;
 244                 u32 min;
 245                 u32 max;
 246                 bool enabled;
 247                 bool combination_mode;  /* gen 2/4 only */
 248                 bool active_low_pwm;
 249
 250                 /* PWM chip */
 251                 bool util_pin_active_low;       /* bxt+ */
 252                 u8 controller;          /* bxt+ only */
 253                 struct pwm_device *pwm;
 254
 255                 struct backlight_device *device;
 256
 257                 /* Connector and platform specific backlight functions */
 258                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 259                 uint32_t (*get)(struct intel_connector *connector);
 260                 void (*set)(struct intel_connector *connector, uint32_t level);
 261                 void (*disable)(struct intel_connector *connector);
 262                 void (*enable)(struct intel_connector *connector);
 263                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 264                                       uint32_t hz);
 265                 void (*power)(struct intel_connector *, bool enable);
 266         } backlight;
 267 };
 268
 269 struct intel_connector {
 270         struct drm_connector base;
 271         /*
 272          * The fixed encoder this connector is connected to.
 273          */
 274         struct intel_encoder *encoder;
 275
 276         /* Reads out the current hw, returning true if the connector is enabled
 277          * and active (i.e. dpms ON state). */
 278         bool (*get_hw_state)(struct intel_connector *);
 279
 280         /* Panel info for eDP and LVDS */
 281         struct intel_panel panel;
 282
 283         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 284         struct edid *edid;
 285         struct edid *detect_edid;
 286
 287         /* since POLL and HPD connectors may use the same HPD line keep the native
 288            state of connector->polled in case hotplug storm detection changes it */
 289         u8 polled;
 290
 291         void *port; /* store this opaque as its illegal to dereference it */
 292
 293         struct intel_dp *mst_port;
 294 };
 295
 296 struct dpll {
 297         /* given values */
 298         int n;
 299         int m1, m2;
 300         int p1, p2;
 301         /* derived values */
 302         int     dot;
 303         int     vco;
 304         int     m;
 305         int     p;
 306 };
 307
 308 struct intel_atomic_state {
 309         struct drm_atomic_state base;
 310
 311         unsigned int cdclk;
 312
 313         /*
 314          * Calculated device cdclk, can be different from cdclk
 315          * only when all crtc's are DPMS off.
 316          */
 317         unsigned int dev_cdclk;
 318
 319         bool dpll_set, modeset;
 320
 321         /*
 322          * Does this transaction change the pipes that are active?  This mask
 323          * tracks which CRTC's have changed their active state at the end of
 324          * the transaction (not counting the temporary disable during modesets).
 325          * This mask should only be non-zero when intel_state->modeset is true,
 326          * but the converse is not necessarily true; simply changing a mode may
 327          * not flip the final active status of any CRTC's
 328          */
 329         unsigned int active_pipe_changes;
 330
 331         unsigned int active_crtcs;
 332         unsigned int min_pixclk[I915_MAX_PIPES];
 333
 334         /* SKL/KBL Only */
 335         unsigned int cdclk_pll_vco;
 336
 337         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 338
 339         /*
 340          * Current watermarks can't be trusted during hardware readout, so
 341          * don't bother calculating intermediate watermarks.
 342          */
 343         bool skip_intermediate_wm;
 344
 345         /* Gen9+ only */
 346         struct skl_wm_values wm_results;
 347 };
 348
 349 struct intel_plane_state {
 350         struct drm_plane_state base;
 351         struct drm_rect clip;
 352
 353         struct {
 354                 u32 offset;
 355                 int x, y;
 356         } main;
 357         struct {
 358                 u32 offset;
 359                 int x, y;
 360         } aux;
 361
 362         /*
 363          * scaler_id
 364          *    = -1 : not using a scaler
 365          *    >=  0 : using a scalers
 366          *
 367          * plane requiring a scaler:
 368          *   - During check_plane, its bit is set in
 369          *     crtc_state->scaler_state.scaler_users by calling helper function
 370          *     update_scaler_plane.
 371          *   - scaler_id indicates the scaler it got assigned.
 372          *
 373          * plane doesn't require a scaler:
 374          *   - this can happen when scaling is no more required or plane simply
 375          *     got disabled.
 376          *   - During check_plane, corresponding bit is reset in
 377          *     crtc_state->scaler_state.scaler_users by calling helper function
 378          *     update_scaler_plane.
 379          */
 380         int scaler_id;
 381
 382         struct drm_intel_sprite_colorkey ckey;
 383
 384         /* async flip related structures */
 385         struct drm_i915_gem_request *wait_req;
 386 };
 387
 388 struct intel_initial_plane_config {
 389         struct intel_framebuffer *fb;
 390         unsigned int tiling;
 391         int size;
 392         u32 base;
 393 };
 394
 395 #define SKL_MIN_SRC_W 8
 396 #define SKL_MAX_SRC_W 4096
 397 #define SKL_MIN_SRC_H 8
 398 #define SKL_MAX_SRC_H 4096
 399 #define SKL_MIN_DST_W 8
 400 #define SKL_MAX_DST_W 4096
 401 #define SKL_MIN_DST_H 8
 402 #define SKL_MAX_DST_H 4096
 403
 404 struct intel_scaler {
 405         int in_use;
 406         uint32_t mode;
 407 };
 408
 409 struct intel_crtc_scaler_state {
 410 #define SKL_NUM_SCALERS 2
 411         struct intel_scaler scalers[SKL_NUM_SCALERS];
 412
 413         /*
 414          * scaler_users: keeps track of users requesting scalers on this crtc.
 415          *
 416          *     If a bit is set, a user is using a scaler.
 417          *     Here user can be a plane or crtc as defined below:
 418          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 419          *       bit 31    - crtc
 420          *
 421          * Instead of creating a new index to cover planes and crtc, using
 422          * existing drm_plane_index for planes which is well less than 31
 423          * planes and bit 31 for crtc. This should be fine to cover all
 424          * our platforms.
 425          *
 426          * intel_atomic_setup_scalers will setup available scalers to users
 427          * requesting scalers. It will gracefully fail if request exceeds
 428          * avilability.
 429          */
 430 #define SKL_CRTC_INDEX 31
 431         unsigned scaler_users;
 432
 433         /* scaler used by crtc for panel fitting purpose */
 434         int scaler_id;
 435 };
 436
 437 /* drm_mode->private_flags */
 438 #define I915_MODE_FLAG_INHERITED 1
 439
 440 struct intel_pipe_wm {
 441         struct intel_wm_level wm[5];
 442         struct intel_wm_level raw_wm[5];
 443         uint32_t linetime;
 444         bool fbc_wm_enabled;
 445         bool pipe_enabled;
 446         bool sprites_enabled;
 447         bool sprites_scaled;
 448 };
 449
 450 struct skl_pipe_wm {
 451         struct skl_wm_level wm[8];
 452         struct skl_wm_level trans_wm;
 453         uint32_t linetime;
 454 };
 455
 456 struct intel_crtc_wm_state {
 457         union {
 458                 struct {
 459                         /*
 460                          * Intermediate watermarks; these can be
 461                          * programmed immediately since they satisfy
 462                          * both the current configuration we're
 463                          * switching away from and the new
 464                          * configuration we're switching to.
 465                          */
 466                         struct intel_pipe_wm intermediate;
 467
 468                         /*
 469                          * Optimal watermarks, programmed post-vblank
 470                          * when this state is committed.
 471                          */
 472                         struct intel_pipe_wm optimal;
 473                 } ilk;
 474
 475                 struct {
 476                         /* gen9+ only needs 1-step wm programming */
 477                         struct skl_pipe_wm optimal;
 478
 479                         /* cached plane data rate */
 480                         unsigned plane_data_rate[I915_MAX_PLANES];
 481                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 482
 483                         /* minimum block allocation */
 484                         uint16_t minimum_blocks[I915_MAX_PLANES];
 485                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 486                 } skl;
 487         };
 488
 489         /*
 490          * Platforms with two-step watermark programming will need to
 491          * update watermark programming post-vblank to switch from the
 492          * safe intermediate watermarks to the optimal final
 493          * watermarks.
 494          */
 495         bool need_postvbl_update;
 496 };
 497
 498 struct intel_crtc_state {
 499         struct drm_crtc_state base;
 500
 501         /**
 502          * quirks - bitfield with hw state readout quirks
 503          *
 504          * For various reasons the hw state readout code might not be able to
 505          * completely faithfully read out the current state. These cases are
 506          * tracked with quirk flags so that fastboot and state checker can act
 507          * accordingly.
 508          */
 509 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 510         unsigned long quirks;
 511
 512         unsigned fb_bits; /* framebuffers to flip */
 513         bool update_pipe; /* can a fast modeset be performed? */
 514         bool disable_cxsr;
 515         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 516         bool fb_changed; /* fb on any of the planes is changed */
 517
 518         /* Pipe source size (ie. panel fitter input size)
 519          * All planes will be positioned inside this space,
 520          * and get clipped at the edges. */
 521         int pipe_src_w, pipe_src_h;
 522
 523         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 524          * between pch encoders and cpu encoders. */
 525         bool has_pch_encoder;
 526
 527         /* Are we sending infoframes on the attached port */
 528         bool has_infoframe;
 529
 530         /* CPU Transcoder for the pipe. Currently this can only differ from the
 531          * pipe on Haswell and later (where we have a special eDP transcoder)
 532          * and Broxton (where we have special DSI transcoders). */
 533         enum transcoder cpu_transcoder;
 534
 535         /*
 536          * Use reduced/limited/broadcast rbg range, compressing from the full
 537          * range fed into the crtcs.
 538          */
 539         bool limited_color_range;
 540
 541         /* Bitmask of encoder types (enum intel_output_type)
 542          * driven by the pipe.
 543          */
 544         unsigned int output_types;
 545
 546         /* Whether we should send NULL infoframes. Required for audio. */
 547         bool has_hdmi_sink;
 548
 549         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 550          * has_dp_encoder is set. */
 551         bool has_audio;
 552
 553         /*
 554          * Enable dithering, used when the selected pipe bpp doesn't match the
 555          * plane bpp.
 556          */
 557         bool dither;
 558
 559         /* Controls for the clock computation, to override various stages. */
 560         bool clock_set;
 561
 562         /* SDVO TV has a bunch of special case. To make multifunction encoders
 563          * work correctly, we need to track this at runtime.*/
 564         bool sdvo_tv_clock;
 565
 566         /*
 567          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 568          * required. This is set in the 2nd loop of calling encoder's
 569          * ->compute_config if the first pick doesn't work out.
 570          */
 571         bool bw_constrained;
 572
 573         /* Settings for the intel dpll used on pretty much everything but
 574          * haswell. */
 575         struct dpll dpll;
 576
 577         /* Selected dpll when shared or NULL. */
 578         struct intel_shared_dpll *shared_dpll;
 579
 580         /*
 581          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 582          * - enum skl_dpll on SKL
 583          */
 584         uint32_t ddi_pll_sel;
 585
 586         /* Actual register state of the dpll, for shared dpll cross-checking. */
 587         struct intel_dpll_hw_state dpll_hw_state;
 588
 589         /* DSI PLL registers */
 590         struct {
 591                 u32 ctrl, div;
 592         } dsi_pll;
 593
 594         int pipe_bpp;
 595         struct intel_link_m_n dp_m_n;
 596
 597         /* m2_n2 for eDP downclock */
 598         struct intel_link_m_n dp_m2_n2;
 599         bool has_drrs;
 600
 601         /*
 602          * Frequence the dpll for the port should run at. Differs from the
 603          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 604          * already multiplied by pixel_multiplier.
 605          */
 606         int port_clock;
 607
 608         /* Used by SDVO (and if we ever fix it, HDMI). */
 609         unsigned pixel_multiplier;
 610
 611         uint8_t lane_count;
 612
 613         /*
 614          * Used by platforms having DP/HDMI PHY with programmable lane
 615          * latency optimization.
 616          */
 617         uint8_t lane_lat_optim_mask;
 618
 619         /* Panel fitter controls for gen2-gen4 + VLV */
 620         struct {
 621                 u32 control;
 622                 u32 pgm_ratios;
 623                 u32 lvds_border_bits;
 624         } gmch_pfit;
 625
 626         /* Panel fitter placement and size for Ironlake+ */
 627         struct {
 628                 u32 pos;
 629                 u32 size;
 630                 bool enabled;
 631                 bool force_thru;
 632         } pch_pfit;
 633
 634         /* FDI configuration, only valid if has_pch_encoder is set. */
 635         int fdi_lanes;
 636         struct intel_link_m_n fdi_m_n;
 637
 638         bool ips_enabled;
 639
 640         bool enable_fbc;
 641
 642         bool double_wide;
 643
 644         bool dp_encoder_is_mst;
 645         int pbn;
 646
 647         struct intel_crtc_scaler_state scaler_state;
 648
 649         /* w/a for waiting 2 vblanks during crtc enable */
 650         enum pipe hsw_workaround_pipe;
 651
 652         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 653         bool disable_lp_wm;
 654
 655         struct intel_crtc_wm_state wm;
 656
 657         /* Gamma mode programmed on the pipe */
 658         uint32_t gamma_mode;
 659 };
 660
 661 struct vlv_wm_state {
 662         struct vlv_pipe_wm wm[3];
 663         struct vlv_sr_wm sr[3];
 664         uint8_t num_active_planes;
 665         uint8_t num_levels;
 666         uint8_t level;
 667         bool cxsr;
 668 };
 669
 670 struct intel_crtc {
 671         struct drm_crtc base;
 672         enum pipe pipe;
 673         enum plane plane;
 674         u8 lut_r[256], lut_g[256], lut_b[256];
 675         /*
 676          * Whether the crtc and the connected output pipeline is active. Implies
 677          * that crtc->enabled is set, i.e. the current mode configuration has
 678          * some outputs connected to this crtc.
 679          */
 680         bool active;
 681         unsigned long enabled_power_domains;
 682         bool lowfreq_avail;
 683         struct intel_overlay *overlay;
 684         struct intel_flip_work *flip_work;
 685
 686         atomic_t unpin_work_count;
 687
 688         /* Display surface base address adjustement for pageflips. Note that on
 689          * gen4+ this only adjusts up to a tile, offsets within a tile are
 690          * handled in the hw itself (with the TILEOFF register). */
 691         u32 dspaddr_offset;
 692         int adjusted_x;
 693         int adjusted_y;
 694
 695         uint32_t cursor_addr;
 696         uint32_t cursor_cntl;
 697         uint32_t cursor_size;
 698         uint32_t cursor_base;
 699
 700         struct intel_crtc_state *config;
 701
 702         /* reset counter value when the last flip was submitted */
 703         unsigned int reset_counter;
 704
 705         /* Access to these should be protected by dev_priv->irq_lock. */
 706         bool cpu_fifo_underrun_disabled;
 707         bool pch_fifo_underrun_disabled;
 708
 709         /* per-pipe watermark state */
 710         struct {
 711                 /* watermarks currently being used  */
 712                 union {
 713                         struct intel_pipe_wm ilk;
 714                         struct skl_pipe_wm skl;
 715                 } active;
 716
 717                 /* allow CxSR on this pipe */
 718                 bool cxsr_allowed;
 719         } wm;
 720
 721         int scanline_offset;
 722
 723         struct {
 724                 unsigned start_vbl_count;
 725                 ktime_t start_vbl_time;
 726                 int min_vbl, max_vbl;
 727                 int scanline_start;
 728         } debug;
 729
 730         /* scalers available on this crtc */
 731         int num_scalers;
 732
 733         struct vlv_wm_state wm_state;
 734 };
 735
 736 struct intel_plane_wm_parameters {
 737         uint32_t horiz_pixels;
 738         uint32_t vert_pixels;
 739         /*
 740          *   For packed pixel formats:
 741          *     bytes_per_pixel - holds bytes per pixel
 742          *   For planar pixel formats:
 743          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 744          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 745          */
 746         uint8_t bytes_per_pixel;
 747         uint8_t y_bytes_per_pixel;
 748         bool enabled;
 749         bool scaled;
 750         u64 tiling;
 751         unsigned int rotation;
 752         uint16_t fifo_size;
 753 };
 754
 755 struct intel_plane {
 756         struct drm_plane base;
 757         int plane;
 758         enum pipe pipe;
 759         bool can_scale;
 760         int max_downscale;
 761         uint32_t frontbuffer_bit;
 762
 763         /* Since we need to change the watermarks before/after
 764          * enabling/disabling the planes, we need to store the parameters here
 765          * as the other pieces of the struct may not reflect the values we want
 766          * for the watermark calculations. Currently only Haswell uses this.
 767          */
 768         struct intel_plane_wm_parameters wm;
 769
 770         /*
 771          * NOTE: Do not place new plane state fields here (e.g., when adding
 772          * new plane properties).  New runtime state should now be placed in
 773          * the intel_plane_state structure and accessed via plane_state.
 774          */
 775
 776         void (*update_plane)(struct drm_plane *plane,
 777                              const struct intel_crtc_state *crtc_state,
 778                              const struct intel_plane_state *plane_state);
 779         void (*disable_plane)(struct drm_plane *plane,
 780                               struct drm_crtc *crtc);
 781         int (*check_plane)(struct drm_plane *plane,
 782                            struct intel_crtc_state *crtc_state,
 783                            struct intel_plane_state *state);
 784 };
 785
 786 struct intel_watermark_params {
 787         unsigned long fifo_size;
 788         unsigned long max_wm;
 789         unsigned long default_wm;
 790         unsigned long guard_size;
 791         unsigned long cacheline_size;
 792 };
 793
 794 struct cxsr_latency {
 795         int is_desktop;
 796         int is_ddr3;
 797         unsigned long fsb_freq;
 798         unsigned long mem_freq;
 799         unsigned long display_sr;
 800         unsigned long display_hpll_disable;
 801         unsigned long cursor_sr;
 802         unsigned long cursor_hpll_disable;
 803 };
 804
 805 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 806 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 807 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 808 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 809 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 810 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 811 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 812 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 813 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 814
 815 struct intel_hdmi {
 816         i915_reg_t hdmi_reg;
 817         int ddc_bus;
 818         struct {
 819                 enum drm_dp_dual_mode_type type;
 820                 int max_tmds_clock;
 821         } dp_dual_mode;
 822         bool limited_color_range;
 823         bool color_range_auto;
 824         bool has_hdmi_sink;
 825         bool has_audio;
 826         enum hdmi_force_audio force_audio;
 827         bool rgb_quant_range_selectable;
 828         enum hdmi_picture_aspect aspect_ratio;
 829         struct intel_connector *attached_connector;
 830         void (*write_infoframe)(struct drm_encoder *encoder,
 831                                 enum hdmi_infoframe_type type,
 832                                 const void *frame, ssize_t len);
 833         void (*set_infoframes)(struct drm_encoder *encoder,
 834                                bool enable,
 835                                const struct drm_display_mode *adjusted_mode);
 836         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 837                                   const struct intel_crtc_state *pipe_config);
 838 };
 839
 840 struct intel_dp_mst_encoder;
 841 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 842
 843 /*
 844  * enum link_m_n_set:
 845  *      When platform provides two set of M_N registers for dp, we can
 846  *      program them and switch between them incase of DRRS.
 847  *      But When only one such register is provided, we have to program the
 848  *      required divider value on that registers itself based on the DRRS state.
 849  *
 850  * M1_N1        : Program dp_m_n on M1_N1 registers
 851  *                        dp_m2_n2 on M2_N2 registers (If supported)
 852  *
 853  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 854  *                        M2_N2 registers are not supported
 855  */
 856
 857 enum link_m_n_set {
 858         /* Sets the m1_n1 and m2_n2 */
 859         M1_N1 = 0,
 860         M2_N2
 861 };
 862
 863 struct intel_dp {
 864         i915_reg_t output_reg;
 865         i915_reg_t aux_ch_ctl_reg;
 866         i915_reg_t aux_ch_data_reg[5];
 867         uint32_t DP;
 868         int link_rate;
 869         uint8_t lane_count;
 870         uint8_t sink_count;
 871         bool link_mst;
 872         bool has_audio;
 873         bool detect_done;
 874         enum hdmi_force_audio force_audio;
 875         bool limited_color_range;
 876         bool color_range_auto;
 877         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 878         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 879         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 880         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 881         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 882         uint8_t num_sink_rates;
 883         int sink_rates[DP_MAX_SUPPORTED_RATES];
 884         struct drm_dp_aux aux;
 885         uint8_t train_set[4];
 886         int panel_power_up_delay;
 887         int panel_power_down_delay;
 888         int panel_power_cycle_delay;
 889         int backlight_on_delay;
 890         int backlight_off_delay;
 891         struct delayed_work panel_vdd_work;
 892         bool want_panel_vdd;
 893         unsigned long last_power_on;
 894         unsigned long last_backlight_off;
 895         ktime_t panel_power_off_time;
 896
 897         struct notifier_block edp_notifier;
 898
 899         /*
 900          * Pipe whose power sequencer is currently locked into
 901          * this port. Only relevant on VLV/CHV.
 902          */
 903         enum pipe pps_pipe;
 904         /*
 905          * Set if the sequencer may be reset due to a power transition,
 906          * requiring a reinitialization. Only relevant on BXT.
 907          */
 908         bool pps_reset;
 909         struct edp_power_seq pps_delays;
 910
 911         bool can_mst; /* this port supports mst */
 912         bool is_mst;
 913         int active_mst_links;
 914         /* connector directly attached - won't be use for modeset in mst world */
 915         struct intel_connector *attached_connector;
 916
 917         /* mst connector list */
 918         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 919         struct drm_dp_mst_topology_mgr mst_mgr;
 920
 921         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 922         /*
 923          * This function returns the value we have to program the AUX_CTL
 924          * register with to kick off an AUX transaction.
 925          */
 926         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 927                                      bool has_aux_irq,
 928                                      int send_bytes,
 929                                      uint32_t aux_clock_divider);
 930
 931         /* This is called before a link training is starterd */
 932         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 933
 934         /* Displayport compliance testing */
 935         unsigned long compliance_test_type;
 936         unsigned long compliance_test_data;
 937         bool compliance_test_active;
 938 };
 939
 940 struct intel_digital_port {
 941         struct intel_encoder base;
 942         enum port port;
 943         u32 saved_port_bits;
 944         struct intel_dp dp;
 945         struct intel_hdmi hdmi;
 946         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 947         bool release_cl2_override;
 948         uint8_t max_lanes;
 949         /* for communication with audio component; protected by av_mutex */
 950         const struct drm_connector *audio_connector;
 951 };
 952
 953 struct intel_dp_mst_encoder {
 954         struct intel_encoder base;
 955         enum pipe pipe;
 956         struct intel_digital_port *primary;
 957         struct intel_connector *connector;
 958 };
 959
 960 static inline enum dpio_channel
 961 vlv_dport_to_channel(struct intel_digital_port *dport)
 962 {
 963         switch (dport->port) {
 964         case PORT_B:
 965         case PORT_D:
 966                 return DPIO_CH0;
 967         case PORT_C:
 968                 return DPIO_CH1;
 969         default:
 970                 BUG();
 971         }
 972 }
 973
 974 static inline enum dpio_phy
 975 vlv_dport_to_phy(struct intel_digital_port *dport)
 976 {
 977         switch (dport->port) {
 978         case PORT_B:
 979         case PORT_C:
 980                 return DPIO_PHY0;
 981         case PORT_D:
 982                 return DPIO_PHY1;
 983         default:
 984                 BUG();
 985         }
 986 }
 987
 988 static inline enum dpio_channel
 989 vlv_pipe_to_channel(enum pipe pipe)
 990 {
 991         switch (pipe) {
 992         case PIPE_A:
 993         case PIPE_C:
 994                 return DPIO_CH0;
 995         case PIPE_B:
 996                 return DPIO_CH1;
 997         default:
 998                 BUG();
 999         }
1000 }
1001
1002 static inline struct drm_crtc *
1003 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1004 {
1005         struct drm_i915_private *dev_priv = to_i915(dev);
1006         return dev_priv->pipe_to_crtc_mapping[pipe];
1007 }
1008
1009 static inline struct drm_crtc *
1010 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1011 {
1012         struct drm_i915_private *dev_priv = to_i915(dev);
1013         return dev_priv->plane_to_crtc_mapping[plane];
1014 }
1015
1016 struct intel_flip_work {
1017         struct work_struct unpin_work;
1018         struct work_struct mmio_work;
1019
1020         struct drm_crtc *crtc;
1021         struct drm_framebuffer *old_fb;
1022         struct drm_i915_gem_object *pending_flip_obj;
1023         struct drm_pending_vblank_event *event;
1024         atomic_t pending;
1025         u32 flip_count;
1026         u32 gtt_offset;
1027         struct drm_i915_gem_request *flip_queued_req;
1028         u32 flip_queued_vblank;
1029         u32 flip_ready_vblank;
1030         unsigned int rotation;
1031 };
1032
1033 struct intel_load_detect_pipe {
1034         struct drm_atomic_state *restore_state;
1035 };
1036
1037 static inline struct intel_encoder *
1038 intel_attached_encoder(struct drm_connector *connector)
1039 {
1040         return to_intel_connector(connector)->encoder;
1041 }
1042
1043 static inline struct intel_digital_port *
1044 enc_to_dig_port(struct drm_encoder *encoder)
1045 {
1046         return container_of(encoder, struct intel_digital_port, base.base);
1047 }
1048
1049 static inline struct intel_dp_mst_encoder *
1050 enc_to_mst(struct drm_encoder *encoder)
1051 {
1052         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1053 }
1054
1055 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1056 {
1057         return &enc_to_dig_port(encoder)->dp;
1058 }
1059
1060 static inline struct intel_digital_port *
1061 dp_to_dig_port(struct intel_dp *intel_dp)
1062 {
1063         return container_of(intel_dp, struct intel_digital_port, dp);
1064 }
1065
1066 static inline struct intel_digital_port *
1067 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1068 {
1069         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1070 }
1071
1072 /*
1073  * Returns the number of planes for this pipe, ie the number of sprites + 1
1074  * (primary plane). This doesn't count the cursor plane then.
1075  */
1076 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1077 {
1078         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1079 }
1080
1081 /* intel_fifo_underrun.c */
1082 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1083                                            enum pipe pipe, bool enable);
1084 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1085                                            enum transcoder pch_transcoder,
1086                                            bool enable);
1087 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1088                                          enum pipe pipe);
1089 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1090                                          enum transcoder pch_transcoder);
1091 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1092 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1093
1094 /* i915_irq.c */
1095 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1096 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1097 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1098 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1099 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1100 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1101 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1102 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1103 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1104 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1105 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1106 {
1107         /*
1108          * We only use drm_irq_uninstall() at unload and VT switch, so
1109          * this is the only thing we need to check.
1110          */
1111         return dev_priv->pm.irqs_enabled;
1112 }
1113
1114 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1115 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1116                                      unsigned int pipe_mask);
1117 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1118                                      unsigned int pipe_mask);
1119
1120 /* intel_crt.c */
1121 void intel_crt_init(struct drm_device *dev);
1122 void intel_crt_reset(struct drm_encoder *encoder);
1123
1124 /* intel_ddi.c */
1125 void intel_ddi_clk_select(struct intel_encoder *encoder,
1126                           const struct intel_crtc_state *pipe_config);
1127 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1128 void hsw_fdi_link_train(struct drm_crtc *crtc);
1129 void intel_ddi_init(struct drm_device *dev, enum port port);
1130 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1131 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1132 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1133 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1134                                        enum transcoder cpu_transcoder);
1135 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1136 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1137 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1138                           struct intel_crtc_state *crtc_state);
1139 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1140 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1141 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1142 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1143 void intel_ddi_get_config(struct intel_encoder *encoder,
1144                           struct intel_crtc_state *pipe_config);
1145 struct intel_encoder *
1146 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1147
1148 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1149 void intel_ddi_clock_get(struct intel_encoder *encoder,
1150                          struct intel_crtc_state *pipe_config);
1151 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1152 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1153
1154 unsigned int intel_fb_align_height(struct drm_device *dev,
1155                                    unsigned int height,
1156                                    uint32_t pixel_format,
1157                                    uint64_t fb_format_modifier);
1158 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1159                               uint64_t fb_modifier, uint32_t pixel_format);
1160
1161 /* intel_audio.c */
1162 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1163 void intel_audio_codec_enable(struct intel_encoder *encoder);
1164 void intel_audio_codec_disable(struct intel_encoder *encoder);
1165 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1166 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1167
1168 /* intel_display.c */
1169 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1170 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1171 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1172                       const char *name, u32 reg, int ref_freq);
1173 extern const struct drm_plane_funcs intel_plane_funcs;
1174 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1175 unsigned int intel_fb_xy_to_linear(int x, int y,
1176                                    const struct intel_plane_state *state,
1177                                    int plane);
1178 void intel_add_fb_offsets(int *x, int *y,
1179                           const struct intel_plane_state *state, int plane);
1180 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1181 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1182 void intel_mark_busy(struct drm_i915_private *dev_priv);
1183 void intel_mark_idle(struct drm_i915_private *dev_priv);
1184 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1185 int intel_display_suspend(struct drm_device *dev);
1186 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1187 void intel_encoder_destroy(struct drm_encoder *encoder);
1188 int intel_connector_init(struct intel_connector *);
1189 struct intel_connector *intel_connector_alloc(void);
1190 bool intel_connector_get_hw_state(struct intel_connector *connector);
1191 void intel_connector_attach_encoder(struct intel_connector *connector,
1192                                     struct intel_encoder *encoder);
1193 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1194                                              struct drm_crtc *crtc);
1195 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1196 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1197                                 struct drm_file *file_priv);
1198 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1199                                              enum pipe pipe);
1200 static inline bool
1201 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1202                     enum intel_output_type type)
1203 {
1204         return crtc_state->output_types & (1 << type);
1205 }
1206 static inline bool
1207 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1208 {
1209         return crtc_state->output_types &
1210                 ((1 << INTEL_OUTPUT_DP) |
1211                  (1 << INTEL_OUTPUT_DP_MST) |
1212                  (1 << INTEL_OUTPUT_EDP));
1213 }
1214 static inline void
1215 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1216 {
1217         drm_wait_one_vblank(dev, pipe);
1218 }
1219 static inline void
1220 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1221 {
1222         const struct intel_crtc *crtc =
1223                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1224
1225         if (crtc->active)
1226                 intel_wait_for_vblank(dev, pipe);
1227 }
1228
1229 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1230
1231 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1232 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1233                          struct intel_digital_port *dport,
1234                          unsigned int expected_mask);
1235 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1236                                 struct drm_display_mode *mode,
1237                                 struct intel_load_detect_pipe *old,
1238                                 struct drm_modeset_acquire_ctx *ctx);
1239 void intel_release_load_detect_pipe(struct drm_connector *connector,
1240                                     struct intel_load_detect_pipe *old,
1241                                     struct drm_modeset_acquire_ctx *ctx);
1242 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1243                                unsigned int rotation);
1244 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1245 struct drm_framebuffer *
1246 __intel_framebuffer_create(struct drm_device *dev,
1247                            struct drm_mode_fb_cmd2 *mode_cmd,
1248                            struct drm_i915_gem_object *obj);
1249 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1250 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1251 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1252 int intel_prepare_plane_fb(struct drm_plane *plane,
1253                            const struct drm_plane_state *new_state);
1254 void intel_cleanup_plane_fb(struct drm_plane *plane,
1255                             const struct drm_plane_state *old_state);
1256 int intel_plane_atomic_get_property(struct drm_plane *plane,
1257                                     const struct drm_plane_state *state,
1258                                     struct drm_property *property,
1259                                     uint64_t *val);
1260 int intel_plane_atomic_set_property(struct drm_plane *plane,
1261                                     struct drm_plane_state *state,
1262                                     struct drm_property *property,
1263                                     uint64_t val);
1264 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1265                                     struct drm_plane_state *plane_state);
1266
1267 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1268                                uint64_t fb_modifier, unsigned int cpp);
1269
1270 static inline bool
1271 intel_rotation_90_or_270(unsigned int rotation)
1272 {
1273         return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1274 }
1275
1276 void intel_create_rotation_property(struct drm_device *dev,
1277                                         struct intel_plane *plane);
1278
1279 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1280                                     enum pipe pipe);
1281
1282 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1283                      const struct dpll *dpll);
1284 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1285 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1286
1287 /* modesetting asserts */
1288 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1289                            enum pipe pipe);
1290 void assert_pll(struct drm_i915_private *dev_priv,
1291                 enum pipe pipe, bool state);
1292 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1293 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1294 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1295 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1296 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1297 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1298                        enum pipe pipe, bool state);
1299 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1300 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1301 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1302 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1303 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1304 u32 intel_compute_tile_offset(int *x, int *y,
1305                               const struct intel_plane_state *state, int plane);
1306 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1307 void intel_finish_reset(struct drm_i915_private *dev_priv);
1308 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1309 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1310 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1311 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1312 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1313 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1314 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1315                             enum dpio_phy phy);
1316 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1317                               enum dpio_phy phy);
1318 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1319 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1320 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1321 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1322 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1323 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1324 unsigned int skl_cdclk_get_vco(unsigned int freq);
1325 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1326 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1327 void intel_dp_get_m_n(struct intel_crtc *crtc,
1328                       struct intel_crtc_state *pipe_config);
1329 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1330 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1331 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1332                         struct dpll *best_clock);
1333 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1334
1335 bool intel_crtc_active(struct drm_crtc *crtc);
1336 void hsw_enable_ips(struct intel_crtc *crtc);
1337 void hsw_disable_ips(struct intel_crtc *crtc);
1338 enum intel_display_power_domain
1339 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1340 enum intel_display_power_domain
1341 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1342 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1343                                  struct intel_crtc_state *pipe_config);
1344
1345 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1346 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1347
1348 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
1349
1350 u32 skl_plane_ctl_format(uint32_t pixel_format);
1351 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1352 u32 skl_plane_ctl_rotation(unsigned int rotation);
1353 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1354                      unsigned int rotation);
1355 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1356
1357 /* intel_csr.c */
1358 void intel_csr_ucode_init(struct drm_i915_private *);
1359 void intel_csr_load_program(struct drm_i915_private *);
1360 void intel_csr_ucode_fini(struct drm_i915_private *);
1361 void intel_csr_ucode_suspend(struct drm_i915_private *);
1362 void intel_csr_ucode_resume(struct drm_i915_private *);
1363
1364 /* intel_dp.c */
1365 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1366 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1367                              struct intel_connector *intel_connector);
1368 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1369                               const struct intel_crtc_state *pipe_config);
1370 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1371 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1372 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1373 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1374 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1375 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1376 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1377 bool intel_dp_compute_config(struct intel_encoder *encoder,
1378                              struct intel_crtc_state *pipe_config);
1379 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1380 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1381                                   bool long_hpd);
1382 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1383 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1384 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1385 void intel_edp_panel_on(struct intel_dp *intel_dp);
1386 void intel_edp_panel_off(struct intel_dp *intel_dp);
1387 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1388 void intel_dp_mst_suspend(struct drm_device *dev);
1389 void intel_dp_mst_resume(struct drm_device *dev);
1390 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1391 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1392 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1393 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1394 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1395 void intel_plane_destroy(struct drm_plane *plane);
1396 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1397 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1398 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1399                                unsigned int frontbuffer_bits);
1400 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1401                           unsigned int frontbuffer_bits);
1402 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1403                                   struct intel_digital_port *port);
1404
1405 void
1406 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1407                                        uint8_t dp_train_pat);
1408 void
1409 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1410 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1411 uint8_t
1412 intel_dp_voltage_max(struct intel_dp *intel_dp);
1413 uint8_t
1414 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1415 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1416                            uint8_t *link_bw, uint8_t *rate_select);
1417 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1418 bool
1419 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1420
1421 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1422 {
1423         return ~((1 << lane_count) - 1) & 0xf;
1424 }
1425
1426 /* intel_dp_aux_backlight.c */
1427 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1428
1429 /* intel_dp_mst.c */
1430 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1431 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1432 /* intel_dsi.c */
1433 void intel_dsi_init(struct drm_device *dev);
1434
1435 /* intel_dsi_dcs_backlight.c */
1436 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1437
1438 /* intel_dvo.c */
1439 void intel_dvo_init(struct drm_device *dev);
1440 /* intel_hotplug.c */
1441 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1442
1443
1444 /* legacy fbdev emulation in intel_fbdev.c */
1445 #ifdef CONFIG_DRM_FBDEV_EMULATION
1446 extern int intel_fbdev_init(struct drm_device *dev);
1447 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1448 extern void intel_fbdev_fini(struct drm_device *dev);
1449 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1450 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1451 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1452 #else
1453 static inline int intel_fbdev_init(struct drm_device *dev)
1454 {
1455         return 0;
1456 }
1457
1458 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1459 {
1460 }
1461
1462 static inline void intel_fbdev_fini(struct drm_device *dev)
1463 {
1464 }
1465
1466 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1467 {
1468 }
1469
1470 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1471 {
1472 }
1473 #endif
1474
1475 /* intel_fbc.c */
1476 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1477                            struct drm_atomic_state *state);
1478 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1479 void intel_fbc_pre_update(struct intel_crtc *crtc,
1480                           struct intel_crtc_state *crtc_state,
1481                           struct intel_plane_state *plane_state);
1482 void intel_fbc_post_update(struct intel_crtc *crtc);
1483 void intel_fbc_init(struct drm_i915_private *dev_priv);
1484 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1485 void intel_fbc_enable(struct intel_crtc *crtc,
1486                       struct intel_crtc_state *crtc_state,
1487                       struct intel_plane_state *plane_state);
1488 void intel_fbc_disable(struct intel_crtc *crtc);
1489 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1490 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1491                           unsigned int frontbuffer_bits,
1492                           enum fb_op_origin origin);
1493 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1494                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1495 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1496
1497 /* intel_hdmi.c */
1498 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1499 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1500                                struct intel_connector *intel_connector);
1501 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1502 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1503                                struct intel_crtc_state *pipe_config);
1504 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1505
1506
1507 /* intel_lvds.c */
1508 void intel_lvds_init(struct drm_device *dev);
1509 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1510 bool intel_is_dual_link_lvds(struct drm_device *dev);
1511
1512
1513 /* intel_modes.c */
1514 int intel_connector_update_modes(struct drm_connector *connector,
1515                                  struct edid *edid);
1516 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1517 void intel_attach_force_audio_property(struct drm_connector *connector);
1518 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1519 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1520
1521
1522 /* intel_overlay.c */
1523 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1524 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1525 int intel_overlay_switch_off(struct intel_overlay *overlay);
1526 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1527                                   struct drm_file *file_priv);
1528 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1529                               struct drm_file *file_priv);
1530 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1531
1532
1533 /* intel_panel.c */
1534 int intel_panel_init(struct intel_panel *panel,
1535                      struct drm_display_mode *fixed_mode,
1536                      struct drm_display_mode *downclock_mode);
1537 void intel_panel_fini(struct intel_panel *panel);
1538 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1539                             struct drm_display_mode *adjusted_mode);
1540 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1541                              struct intel_crtc_state *pipe_config,
1542                              int fitting_mode);
1543 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1544                               struct intel_crtc_state *pipe_config,
1545                               int fitting_mode);
1546 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1547                                     u32 level, u32 max);
1548 int intel_panel_setup_backlight(struct drm_connector *connector,
1549                                 enum pipe pipe);
1550 void intel_panel_enable_backlight(struct intel_connector *connector);
1551 void intel_panel_disable_backlight(struct intel_connector *connector);
1552 void intel_panel_destroy_backlight(struct drm_connector *connector);
1553 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1554 extern struct drm_display_mode *intel_find_panel_downclock(
1555                                 struct drm_device *dev,
1556                                 struct drm_display_mode *fixed_mode,
1557                                 struct drm_connector *connector);
1558
1559 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1560 int intel_backlight_device_register(struct intel_connector *connector);
1561 void intel_backlight_device_unregister(struct intel_connector *connector);
1562 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1563 static int intel_backlight_device_register(struct intel_connector *connector)
1564 {
1565         return 0;
1566 }
1567 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1568 {
1569 }
1570 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1571
1572
1573 /* intel_psr.c */
1574 void intel_psr_enable(struct intel_dp *intel_dp);
1575 void intel_psr_disable(struct intel_dp *intel_dp);
1576 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1577                           unsigned frontbuffer_bits);
1578 void intel_psr_flush(struct drm_i915_private *dev_priv,
1579                      unsigned frontbuffer_bits,
1580                      enum fb_op_origin origin);
1581 void intel_psr_init(struct drm_device *dev);
1582 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1583                                    unsigned frontbuffer_bits);
1584
1585 /* intel_runtime_pm.c */
1586 int intel_power_domains_init(struct drm_i915_private *);
1587 void intel_power_domains_fini(struct drm_i915_private *);
1588 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1589 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1590 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1591 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1592 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1593 const char *
1594 intel_display_power_domain_str(enum intel_display_power_domain domain);
1595
1596 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1597                                     enum intel_display_power_domain domain);
1598 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1599                                       enum intel_display_power_domain domain);
1600 void intel_display_power_get(struct drm_i915_private *dev_priv,
1601                              enum intel_display_power_domain domain);
1602 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1603                                         enum intel_display_power_domain domain);
1604 void intel_display_power_put(struct drm_i915_private *dev_priv,
1605                              enum intel_display_power_domain domain);
1606
1607 static inline void
1608 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1609 {
1610         WARN_ONCE(dev_priv->pm.suspended,
1611                   "Device suspended during HW access\n");
1612 }
1613
1614 static inline void
1615 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1616 {
1617         assert_rpm_device_not_suspended(dev_priv);
1618         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1619          * too much noise. */
1620         if (!atomic_read(&dev_priv->pm.wakeref_count))
1621                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1622 }
1623
1624 static inline int
1625 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1626 {
1627         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1628
1629         assert_rpm_wakelock_held(dev_priv);
1630
1631         return seq;
1632 }
1633
1634 static inline void
1635 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1636 {
1637         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1638                   "HW access outside of RPM atomic section\n");
1639 }
1640
1641 /**
1642  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1643  * @dev_priv: i915 device instance
1644  *
1645  * This function disable asserts that check if we hold an RPM wakelock
1646  * reference, while keeping the device-not-suspended checks still enabled.
1647  * It's meant to be used only in special circumstances where our rule about
1648  * the wakelock refcount wrt. the device power state doesn't hold. According
1649  * to this rule at any point where we access the HW or want to keep the HW in
1650  * an active state we must hold an RPM wakelock reference acquired via one of
1651  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1652  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1653  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1654  * users should avoid using this function.
1655  *
1656  * Any calls to this function must have a symmetric call to
1657  * enable_rpm_wakeref_asserts().
1658  */
1659 static inline void
1660 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1661 {
1662         atomic_inc(&dev_priv->pm.wakeref_count);
1663 }
1664
1665 /**
1666  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1667  * @dev_priv: i915 device instance
1668  *
1669  * This function re-enables the RPM assert checks after disabling them with
1670  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1671  * circumstances otherwise its use should be avoided.
1672  *
1673  * Any calls to this function must have a symmetric call to
1674  * disable_rpm_wakeref_asserts().
1675  */
1676 static inline void
1677 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1678 {
1679         atomic_dec(&dev_priv->pm.wakeref_count);
1680 }
1681
1682 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1683 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1684 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1685 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1686
1687 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1688
1689 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1690                              bool override, unsigned int mask);
1691 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1692                           enum dpio_channel ch, bool override);
1693
1694
1695 /* intel_pm.c */
1696 void intel_init_clock_gating(struct drm_device *dev);
1697 void intel_suspend_hw(struct drm_device *dev);
1698 int ilk_wm_max_level(const struct drm_device *dev);
1699 void intel_update_watermarks(struct drm_crtc *crtc);
1700 void intel_init_pm(struct drm_device *dev);
1701 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1702 void intel_pm_setup(struct drm_device *dev);
1703 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1704 void intel_gpu_ips_teardown(void);
1705 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1706 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1707 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1708 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1709 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1710 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1711 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1712 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1713 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1714 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1715 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1716                     struct intel_rps_client *rps,
1717                     unsigned long submitted);
1718 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1719 void vlv_wm_get_hw_state(struct drm_device *dev);
1720 void ilk_wm_get_hw_state(struct drm_device *dev);
1721 void skl_wm_get_hw_state(struct drm_device *dev);
1722 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1723                           struct skl_ddb_allocation *ddb /* out */);
1724 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1725 bool ilk_disable_lp_wm(struct drm_device *dev);
1726 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1727 static inline int intel_enable_rc6(void)
1728 {
1729         return i915.enable_rc6;
1730 }
1731
1732 /* intel_sdvo.c */
1733 bool intel_sdvo_init(struct drm_device *dev,
1734                      i915_reg_t reg, enum port port);
1735
1736
1737 /* intel_sprite.c */
1738 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1739                              int usecs);
1740 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1741 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1742                               struct drm_file *file_priv);
1743 void intel_pipe_update_start(struct intel_crtc *crtc);
1744 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1745
1746 /* intel_tv.c */
1747 void intel_tv_init(struct drm_device *dev);
1748
1749 /* intel_atomic.c */
1750 int intel_connector_atomic_get_property(struct drm_connector *connector,
1751                                         const struct drm_connector_state *state,
1752                                         struct drm_property *property,
1753                                         uint64_t *val);
1754 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1755 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1756                                struct drm_crtc_state *state);
1757 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1758 void intel_atomic_state_clear(struct drm_atomic_state *);
1759 struct intel_shared_dpll_config *
1760 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1761
1762 static inline struct intel_crtc_state *
1763 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1764                             struct intel_crtc *crtc)
1765 {
1766         struct drm_crtc_state *crtc_state;
1767         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1768         if (IS_ERR(crtc_state))
1769                 return ERR_CAST(crtc_state);
1770
1771         return to_intel_crtc_state(crtc_state);
1772 }
1773
1774 static inline struct intel_plane_state *
1775 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1776                                       struct intel_plane *plane)
1777 {
1778         struct drm_plane_state *plane_state;
1779
1780         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1781
1782         return to_intel_plane_state(plane_state);
1783 }
1784
1785 int intel_atomic_setup_scalers(struct drm_device *dev,
1786         struct intel_crtc *intel_crtc,
1787         struct intel_crtc_state *crtc_state);
1788
1789 /* intel_atomic_plane.c */
1790 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1791 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1792 void intel_plane_destroy_state(struct drm_plane *plane,
1793                                struct drm_plane_state *state);
1794 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1795
1796 /* intel_color.c */
1797 void intel_color_init(struct drm_crtc *crtc);
1798 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1799 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1800 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1801
1802 #endif /* __INTEL_DRV_H__ */