2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <linux/hdmi.h>
30 #include <drm/i915_drm.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_dp_mst_helper.h>
38 * _wait_for - magic (register) wait macro
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
45 #define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
49 if (time_after(jiffies, timeout__)) { \
54 if (W && drm_can_sleep()) { \
63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
68 #define KHz(x) (1000 * (x))
69 #define MHz(x) KHz(1000 * (x))
72 * Display related stuff
75 /* store information about an Ixxx DVO */
76 /* The i830->i865 use multiple DVOs with multiple i2cs */
77 /* the i915, i945 have a single sDVO i2c bus - which is different */
79 /* maximum connectors per crtcs in the mode set */
81 /* Maximum cursor sizes */
82 #define GEN2_CURSOR_WIDTH 64
83 #define GEN2_CURSOR_HEIGHT 64
84 #define MAX_CURSOR_WIDTH 256
85 #define MAX_CURSOR_HEIGHT 256
87 #define INTEL_I2C_BUS_DVO 1
88 #define INTEL_I2C_BUS_SDVO 2
90 /* these are outputs from the chip - integrated only
91 external chips are via DVO or SDVO output */
92 #define INTEL_OUTPUT_UNUSED 0
93 #define INTEL_OUTPUT_ANALOG 1
94 #define INTEL_OUTPUT_DVO 2
95 #define INTEL_OUTPUT_SDVO 3
96 #define INTEL_OUTPUT_LVDS 4
97 #define INTEL_OUTPUT_TVOUT 5
98 #define INTEL_OUTPUT_HDMI 6
99 #define INTEL_OUTPUT_DISPLAYPORT 7
100 #define INTEL_OUTPUT_EDP 8
101 #define INTEL_OUTPUT_DSI 9
102 #define INTEL_OUTPUT_UNKNOWN 10
103 #define INTEL_OUTPUT_DP_MST 11
105 #define INTEL_DVO_CHIP_NONE 0
106 #define INTEL_DVO_CHIP_LVDS 1
107 #define INTEL_DVO_CHIP_TMDS 2
108 #define INTEL_DVO_CHIP_TVOUT 4
110 #define INTEL_DSI_VIDEO_MODE 0
111 #define INTEL_DSI_COMMAND_MODE 1
113 struct intel_framebuffer {
114 struct drm_framebuffer base;
115 struct drm_i915_gem_object *obj;
119 struct drm_fb_helper helper;
120 struct intel_framebuffer *fb;
121 struct list_head fbdev_list;
122 struct drm_display_mode *our_mode;
126 struct intel_encoder {
127 struct drm_encoder base;
129 * The new crtc this encoder will be driven from. Only differs from
130 * base->crtc while a modeset is in progress.
132 struct intel_crtc *new_crtc;
135 unsigned int cloneable;
136 bool connectors_active;
137 void (*hot_plug)(struct intel_encoder *);
138 bool (*compute_config)(struct intel_encoder *,
139 struct intel_crtc_config *);
140 void (*pre_pll_enable)(struct intel_encoder *);
141 void (*pre_enable)(struct intel_encoder *);
142 void (*enable)(struct intel_encoder *);
143 void (*mode_set)(struct intel_encoder *intel_encoder);
144 void (*disable)(struct intel_encoder *);
145 void (*post_disable)(struct intel_encoder *);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_config *pipe_config);
157 enum hpd_pin hpd_pin;
161 struct drm_display_mode *fixed_mode;
162 struct drm_display_mode *downclock_mode;
172 bool combination_mode; /* gen 2/4 only */
174 struct backlight_device *device;
178 struct intel_connector {
179 struct drm_connector base;
181 * The fixed encoder this connector is connected to.
183 struct intel_encoder *encoder;
186 * The new encoder this connector will be driven. Only differs from
187 * encoder while a modeset is in progress.
189 struct intel_encoder *new_encoder;
191 /* Reads out the current hw, returning true if the connector is enabled
192 * and active (i.e. dpms ON state). */
193 bool (*get_hw_state)(struct intel_connector *);
196 * Removes all interfaces through which the connector is accessible
197 * - like sysfs, debugfs entries -, so that no new operations can be
198 * started on the connector. Also makes sure all currently pending
199 * operations finish before returing.
201 void (*unregister)(struct intel_connector *);
203 /* Panel info for eDP and LVDS */
204 struct intel_panel panel;
206 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
209 /* since POLL and HPD connectors may use the same HPD line keep the native
210 state of connector->polled in case hotplug storm detection changes it */
213 void *port; /* store this opaque as its illegal to dereference it */
215 struct intel_dp *mst_port;
218 typedef struct dpll {
230 struct intel_plane_config {
236 struct intel_crtc_config {
238 * quirks - bitfield with hw state readout quirks
240 * For various reasons the hw state readout code might not be able to
241 * completely faithfully read out the current state. These cases are
242 * tracked with quirk flags so that fastboot and state checker can act
245 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
246 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
247 unsigned long quirks;
249 /* User requested mode, only valid as a starting point to
250 * compute adjusted_mode, except in the case of (S)DVO where
251 * it's also for the output timings of the (S)DVO chip.
252 * adjusted_mode will then correspond to the S(DVO) chip's
253 * preferred input timings. */
254 struct drm_display_mode requested_mode;
255 /* Actual pipe timings ie. what we program into the pipe timing
256 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
257 struct drm_display_mode adjusted_mode;
259 /* Pipe source size (ie. panel fitter input size)
260 * All planes will be positioned inside this space,
261 * and get clipped at the edges. */
262 int pipe_src_w, pipe_src_h;
264 /* Whether to set up the PCH/FDI. Note that we never allow sharing
265 * between pch encoders and cpu encoders. */
266 bool has_pch_encoder;
268 /* CPU Transcoder for the pipe. Currently this can only differ from the
269 * pipe on Haswell (where we have a special eDP transcoder). */
270 enum transcoder cpu_transcoder;
273 * Use reduced/limited/broadcast rbg range, compressing from the full
274 * range fed into the crtcs.
276 bool limited_color_range;
278 /* DP has a bunch of special case unfortunately, so mark the pipe
282 /* Whether we should send NULL infoframes. Required for audio. */
285 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
286 * has_dp_encoder is set. */
290 * Enable dithering, used when the selected pipe bpp doesn't match the
295 /* Controls for the clock computation, to override various stages. */
298 /* SDVO TV has a bunch of special case. To make multifunction encoders
299 * work correctly, we need to track this at runtime.*/
303 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
304 * required. This is set in the 2nd loop of calling encoder's
305 * ->compute_config if the first pick doesn't work out.
309 /* Settings for the intel dpll used on pretty much everything but
313 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
314 enum intel_dpll_id shared_dpll;
316 /* PORT_CLK_SEL for DDI ports. */
317 uint32_t ddi_pll_sel;
319 /* Actual register state of the dpll, for shared dpll cross-checking. */
320 struct intel_dpll_hw_state dpll_hw_state;
323 struct intel_link_m_n dp_m_n;
325 /* m2_n2 for eDP downclock */
326 struct intel_link_m_n dp_m2_n2;
330 * Frequence the dpll for the port should run at. Differs from the
331 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
332 * already multiplied by pixel_multiplier.
336 /* Used by SDVO (and if we ever fix it, HDMI). */
337 unsigned pixel_multiplier;
339 /* Panel fitter controls for gen2-gen4 + VLV */
343 u32 lvds_border_bits;
346 /* Panel fitter placement and size for Ironlake+ */
354 /* FDI configuration, only valid if has_pch_encoder is set. */
356 struct intel_link_m_n fdi_m_n;
362 bool dp_encoder_is_mst;
366 struct intel_pipe_wm {
367 struct intel_wm_level wm[5];
371 bool sprites_enabled;
375 struct intel_mmio_flip {
381 struct drm_crtc base;
384 u8 lut_r[256], lut_g[256], lut_b[256];
386 * Whether the crtc and the connected output pipeline is active. Implies
387 * that crtc->enabled is set, i.e. the current mode configuration has
388 * some outputs connected to this crtc.
391 unsigned long enabled_power_domains;
392 bool primary_enabled; /* is the primary plane (partially) visible? */
394 struct intel_overlay *overlay;
395 struct intel_unpin_work *unpin_work;
397 atomic_t unpin_work_count;
399 /* Display surface base address adjustement for pageflips. Note that on
400 * gen4+ this only adjusts up to a tile, offsets within a tile are
401 * handled in the hw itself (with the TILEOFF register). */
402 unsigned long dspaddr_offset;
404 struct drm_i915_gem_object *cursor_bo;
405 uint32_t cursor_addr;
406 int16_t cursor_width, cursor_height;
407 uint32_t cursor_cntl;
408 uint32_t cursor_size;
409 uint32_t cursor_base;
411 struct intel_plane_config plane_config;
412 struct intel_crtc_config config;
413 struct intel_crtc_config *new_config;
416 /* reset counter value when the last flip was submitted */
417 unsigned int reset_counter;
419 /* Access to these should be protected by dev_priv->irq_lock. */
420 bool cpu_fifo_underrun_disabled;
421 bool pch_fifo_underrun_disabled;
423 /* per-pipe watermark state */
425 /* watermarks currently being used */
426 struct intel_pipe_wm active;
430 struct intel_mmio_flip mmio_flip;
433 struct intel_plane_wm_parameters {
434 uint32_t horiz_pixels;
435 uint32_t vert_pixels;
436 uint8_t bytes_per_pixel;
442 struct drm_plane base;
445 struct drm_i915_gem_object *obj;
449 unsigned int crtc_w, crtc_h;
450 uint32_t src_x, src_y;
451 uint32_t src_w, src_h;
452 unsigned int rotation;
454 /* Since we need to change the watermarks before/after
455 * enabling/disabling the planes, we need to store the parameters here
456 * as the other pieces of the struct may not reflect the values we want
457 * for the watermark calculations. Currently only Haswell uses this.
459 struct intel_plane_wm_parameters wm;
461 void (*update_plane)(struct drm_plane *plane,
462 struct drm_crtc *crtc,
463 struct drm_framebuffer *fb,
464 struct drm_i915_gem_object *obj,
465 int crtc_x, int crtc_y,
466 unsigned int crtc_w, unsigned int crtc_h,
467 uint32_t x, uint32_t y,
468 uint32_t src_w, uint32_t src_h);
469 void (*disable_plane)(struct drm_plane *plane,
470 struct drm_crtc *crtc);
471 int (*update_colorkey)(struct drm_plane *plane,
472 struct drm_intel_sprite_colorkey *key);
473 void (*get_colorkey)(struct drm_plane *plane,
474 struct drm_intel_sprite_colorkey *key);
477 struct intel_watermark_params {
478 unsigned long fifo_size;
479 unsigned long max_wm;
480 unsigned long default_wm;
481 unsigned long guard_size;
482 unsigned long cacheline_size;
485 struct cxsr_latency {
488 unsigned long fsb_freq;
489 unsigned long mem_freq;
490 unsigned long display_sr;
491 unsigned long display_hpll_disable;
492 unsigned long cursor_sr;
493 unsigned long cursor_hpll_disable;
496 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
497 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
498 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
499 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
500 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
501 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
506 uint32_t color_range;
507 bool color_range_auto;
510 enum hdmi_force_audio force_audio;
511 bool rgb_quant_range_selectable;
512 enum hdmi_picture_aspect aspect_ratio;
513 void (*write_infoframe)(struct drm_encoder *encoder,
514 enum hdmi_infoframe_type type,
515 const void *frame, ssize_t len);
516 void (*set_infoframes)(struct drm_encoder *encoder,
518 struct drm_display_mode *adjusted_mode);
521 struct intel_dp_mst_encoder;
522 #define DP_MAX_DOWNSTREAM_PORTS 0x10
525 * HIGH_RR is the highest eDP panel refresh rate read from EDID
526 * LOW_RR is the lowest eDP panel refresh rate found from EDID
527 * parsing for same resolution.
529 enum edp_drrs_refresh_rate_type {
532 DRRS_MAX_RR, /* RR count */
537 uint32_t aux_ch_ctl_reg;
540 enum hdmi_force_audio force_audio;
541 uint32_t color_range;
542 bool color_range_auto;
545 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
546 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
547 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
548 struct drm_dp_aux aux;
549 uint8_t train_set[4];
550 int panel_power_up_delay;
551 int panel_power_down_delay;
552 int panel_power_cycle_delay;
553 int backlight_on_delay;
554 int backlight_off_delay;
555 struct delayed_work panel_vdd_work;
557 unsigned long last_power_cycle;
558 unsigned long last_power_on;
559 unsigned long last_backlight_off;
561 struct notifier_block edp_notifier;
564 bool can_mst; /* this port supports mst */
566 int active_mst_links;
567 /* connector directly attached - won't be use for modeset in mst world */
568 struct intel_connector *attached_connector;
570 /* mst connector list */
571 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
572 struct drm_dp_mst_topology_mgr mst_mgr;
574 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
576 * This function returns the value we have to program the AUX_CTL
577 * register with to kick off an AUX transaction.
579 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
582 uint32_t aux_clock_divider);
584 enum drrs_support_type type;
585 enum edp_drrs_refresh_rate_type refresh_rate_type;
591 struct intel_digital_port {
592 struct intel_encoder base;
596 struct intel_hdmi hdmi;
597 bool (*hpd_pulse)(struct intel_digital_port *, bool);
600 struct intel_dp_mst_encoder {
601 struct intel_encoder base;
603 struct intel_digital_port *primary;
604 void *port; /* store this opaque as its illegal to dereference it */
608 vlv_dport_to_channel(struct intel_digital_port *dport)
610 switch (dport->port) {
622 vlv_pipe_to_channel(enum pipe pipe)
635 static inline struct drm_crtc *
636 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 return dev_priv->pipe_to_crtc_mapping[pipe];
642 static inline struct drm_crtc *
643 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
645 struct drm_i915_private *dev_priv = dev->dev_private;
646 return dev_priv->plane_to_crtc_mapping[plane];
649 struct intel_unpin_work {
650 struct work_struct work;
651 struct drm_crtc *crtc;
652 struct drm_i915_gem_object *old_fb_obj;
653 struct drm_i915_gem_object *pending_flip_obj;
654 struct drm_pending_vblank_event *event;
656 #define INTEL_FLIP_INACTIVE 0
657 #define INTEL_FLIP_PENDING 1
658 #define INTEL_FLIP_COMPLETE 2
661 bool enable_stall_check;
664 struct intel_set_config {
665 struct drm_encoder **save_connector_encoders;
666 struct drm_crtc **save_encoder_crtcs;
667 bool *save_crtc_enabled;
673 struct intel_load_detect_pipe {
674 struct drm_framebuffer *release_fb;
675 bool load_detect_temp;
679 static inline struct intel_encoder *
680 intel_attached_encoder(struct drm_connector *connector)
682 return to_intel_connector(connector)->encoder;
685 static inline struct intel_digital_port *
686 enc_to_dig_port(struct drm_encoder *encoder)
688 return container_of(encoder, struct intel_digital_port, base.base);
691 static inline struct intel_dp_mst_encoder *
692 enc_to_mst(struct drm_encoder *encoder)
694 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
697 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
699 return &enc_to_dig_port(encoder)->dp;
702 static inline struct intel_digital_port *
703 dp_to_dig_port(struct intel_dp *intel_dp)
705 return container_of(intel_dp, struct intel_digital_port, dp);
708 static inline struct intel_digital_port *
709 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
711 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
716 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
717 enum pipe pipe, bool enable);
718 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
719 enum transcoder pch_transcoder,
721 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
722 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
723 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
724 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
725 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
726 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
727 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
728 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
729 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
732 * We only use drm_irq_uninstall() at unload and VT switch, so
733 * this is the only thing we need to check.
735 return !dev_priv->pm._irqs_disabled;
738 int intel_get_crtc_scanline(struct intel_crtc *crtc);
739 void i9xx_check_fifo_underruns(struct drm_device *dev);
740 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
743 void intel_crt_init(struct drm_device *dev);
747 void intel_prepare_ddi(struct drm_device *dev);
748 void hsw_fdi_link_train(struct drm_crtc *crtc);
749 void intel_ddi_init(struct drm_device *dev, enum port port);
750 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
751 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
752 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
753 void intel_ddi_pll_init(struct drm_device *dev);
754 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
755 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
756 enum transcoder cpu_transcoder);
757 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
758 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
759 bool intel_ddi_pll_select(struct intel_crtc *crtc);
760 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
761 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
762 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
763 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
764 void intel_ddi_get_config(struct intel_encoder *encoder,
765 struct intel_crtc_config *pipe_config);
767 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
768 void intel_ddi_clock_get(struct intel_encoder *encoder,
769 struct intel_crtc_config *pipe_config);
770 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
772 /* intel_display.c */
773 const char *intel_output_name(int output);
774 bool intel_has_pending_fb_unpin(struct drm_device *dev);
775 int intel_pch_rawclk(struct drm_device *dev);
776 void intel_mark_busy(struct drm_device *dev);
777 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
778 struct intel_engine_cs *ring);
779 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
780 unsigned frontbuffer_bits);
781 void intel_frontbuffer_flip_complete(struct drm_device *dev,
782 unsigned frontbuffer_bits);
783 void intel_frontbuffer_flush(struct drm_device *dev,
784 unsigned frontbuffer_bits);
786 * intel_frontbuffer_flip - prepare frontbuffer flip
788 * @frontbuffer_bits: frontbuffer plane tracking bits
790 * This function gets called after scheduling a flip on @obj. This is for
791 * synchronous plane updates which will happen on the next vblank and which will
792 * not get delayed by pending gpu rendering.
794 * Can be called without any locks held.
797 void intel_frontbuffer_flip(struct drm_device *dev,
798 unsigned frontbuffer_bits)
800 intel_frontbuffer_flush(dev, frontbuffer_bits);
803 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
804 void intel_mark_idle(struct drm_device *dev);
805 void intel_crtc_restore_mode(struct drm_crtc *crtc);
806 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
807 void intel_crtc_update_dpms(struct drm_crtc *crtc);
808 void intel_encoder_destroy(struct drm_encoder *encoder);
809 void intel_connector_dpms(struct drm_connector *, int mode);
810 bool intel_connector_get_hw_state(struct intel_connector *connector);
811 void intel_modeset_check_state(struct drm_device *dev);
812 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
813 struct intel_digital_port *port);
814 void intel_connector_attach_encoder(struct intel_connector *connector,
815 struct intel_encoder *encoder);
816 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
817 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
818 struct drm_crtc *crtc);
819 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
820 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
821 struct drm_file *file_priv);
822 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
824 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
825 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
826 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
827 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
828 struct intel_digital_port *dport);
829 bool intel_get_load_detect_pipe(struct drm_connector *connector,
830 struct drm_display_mode *mode,
831 struct intel_load_detect_pipe *old,
832 struct drm_modeset_acquire_ctx *ctx);
833 void intel_release_load_detect_pipe(struct drm_connector *connector,
834 struct intel_load_detect_pipe *old,
835 struct drm_modeset_acquire_ctx *ctx);
836 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
838 struct intel_engine_cs *pipelined);
839 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
840 struct drm_framebuffer *
841 __intel_framebuffer_create(struct drm_device *dev,
842 struct drm_mode_fb_cmd2 *mode_cmd,
843 struct drm_i915_gem_object *obj);
844 void intel_prepare_page_flip(struct drm_device *dev, int plane);
845 void intel_finish_page_flip(struct drm_device *dev, int pipe);
846 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
848 /* shared dpll functions */
849 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
850 void assert_shared_dpll(struct drm_i915_private *dev_priv,
851 struct intel_shared_dpll *pll,
853 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
854 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
855 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
856 void intel_put_shared_dpll(struct intel_crtc *crtc);
858 /* modesetting asserts */
859 void assert_pll(struct drm_i915_private *dev_priv,
860 enum pipe pipe, bool state);
861 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
862 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
863 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
864 enum pipe pipe, bool state);
865 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
866 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
867 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
868 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
869 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
870 void intel_write_eld(struct drm_encoder *encoder,
871 struct drm_display_mode *mode);
872 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
873 unsigned int tiling_mode,
876 void intel_display_handle_reset(struct drm_device *dev);
877 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
878 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
879 void intel_dp_get_m_n(struct intel_crtc *crtc,
880 struct intel_crtc_config *pipe_config);
881 void intel_dp_set_m_n(struct intel_crtc *crtc);
882 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
884 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
886 bool intel_crtc_active(struct drm_crtc *crtc);
887 void hsw_enable_ips(struct intel_crtc *crtc);
888 void hsw_disable_ips(struct intel_crtc *crtc);
889 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
890 enum intel_display_power_domain
891 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
892 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
893 struct intel_crtc_config *pipe_config);
894 int intel_format_to_fourcc(int format);
895 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
896 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
899 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
900 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
901 struct intel_connector *intel_connector);
902 void intel_dp_start_link_train(struct intel_dp *intel_dp);
903 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
904 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
905 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
906 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
907 void intel_dp_check_link_status(struct intel_dp *intel_dp);
908 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
909 bool intel_dp_compute_config(struct intel_encoder *encoder,
910 struct intel_crtc_config *pipe_config);
911 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
912 bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
914 void intel_edp_backlight_on(struct intel_dp *intel_dp);
915 void intel_edp_backlight_off(struct intel_dp *intel_dp);
916 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
917 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
918 void intel_edp_panel_on(struct intel_dp *intel_dp);
919 void intel_edp_panel_off(struct intel_dp *intel_dp);
920 void intel_edp_psr_enable(struct intel_dp *intel_dp);
921 void intel_edp_psr_disable(struct intel_dp *intel_dp);
922 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
923 void intel_edp_psr_invalidate(struct drm_device *dev,
924 unsigned frontbuffer_bits);
925 void intel_edp_psr_flush(struct drm_device *dev,
926 unsigned frontbuffer_bits);
927 void intel_edp_psr_init(struct drm_device *dev);
929 int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
930 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
931 void intel_dp_mst_suspend(struct drm_device *dev);
932 void intel_dp_mst_resume(struct drm_device *dev);
933 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
934 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
936 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
937 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
939 void intel_dsi_init(struct drm_device *dev);
943 void intel_dvo_init(struct drm_device *dev);
946 /* legacy fbdev emulation in intel_fbdev.c */
947 #ifdef CONFIG_DRM_I915_FBDEV
948 extern int intel_fbdev_init(struct drm_device *dev);
949 extern void intel_fbdev_initial_config(struct drm_device *dev);
950 extern void intel_fbdev_fini(struct drm_device *dev);
951 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
952 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
953 extern void intel_fbdev_restore_mode(struct drm_device *dev);
955 static inline int intel_fbdev_init(struct drm_device *dev)
960 static inline void intel_fbdev_initial_config(struct drm_device *dev)
964 static inline void intel_fbdev_fini(struct drm_device *dev)
968 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
972 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
978 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
979 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
980 struct intel_connector *intel_connector);
981 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
982 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config);
987 void intel_lvds_init(struct drm_device *dev);
988 bool intel_is_dual_link_lvds(struct drm_device *dev);
992 int intel_connector_update_modes(struct drm_connector *connector,
994 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
995 void intel_attach_force_audio_property(struct drm_connector *connector);
996 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
999 /* intel_overlay.c */
1000 void intel_setup_overlay(struct drm_device *dev);
1001 void intel_cleanup_overlay(struct drm_device *dev);
1002 int intel_overlay_switch_off(struct intel_overlay *overlay);
1003 int intel_overlay_put_image(struct drm_device *dev, void *data,
1004 struct drm_file *file_priv);
1005 int intel_overlay_attrs(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv);
1010 int intel_panel_init(struct intel_panel *panel,
1011 struct drm_display_mode *fixed_mode,
1012 struct drm_display_mode *downclock_mode);
1013 void intel_panel_fini(struct intel_panel *panel);
1014 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1015 struct drm_display_mode *adjusted_mode);
1016 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1017 struct intel_crtc_config *pipe_config,
1019 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1020 struct intel_crtc_config *pipe_config,
1022 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1023 u32 level, u32 max);
1024 int intel_panel_setup_backlight(struct drm_connector *connector);
1025 void intel_panel_enable_backlight(struct intel_connector *connector);
1026 void intel_panel_disable_backlight(struct intel_connector *connector);
1027 void intel_panel_destroy_backlight(struct drm_connector *connector);
1028 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1029 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1030 extern struct drm_display_mode *intel_find_panel_downclock(
1031 struct drm_device *dev,
1032 struct drm_display_mode *fixed_mode,
1033 struct drm_connector *connector);
1036 void intel_init_clock_gating(struct drm_device *dev);
1037 void intel_suspend_hw(struct drm_device *dev);
1038 int ilk_wm_max_level(const struct drm_device *dev);
1039 void intel_update_watermarks(struct drm_crtc *crtc);
1040 void intel_update_sprite_watermarks(struct drm_plane *plane,
1041 struct drm_crtc *crtc,
1042 uint32_t sprite_width,
1043 uint32_t sprite_height,
1045 bool enabled, bool scaled);
1046 void intel_init_pm(struct drm_device *dev);
1047 void intel_pm_setup(struct drm_device *dev);
1048 bool intel_fbc_enabled(struct drm_device *dev);
1049 void intel_update_fbc(struct drm_device *dev);
1050 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1051 void intel_gpu_ips_teardown(void);
1052 int intel_power_domains_init(struct drm_i915_private *);
1053 void intel_power_domains_remove(struct drm_i915_private *);
1054 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1055 enum intel_display_power_domain domain);
1056 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1057 enum intel_display_power_domain domain);
1058 void intel_display_power_get(struct drm_i915_private *dev_priv,
1059 enum intel_display_power_domain domain);
1060 void intel_display_power_put(struct drm_i915_private *dev_priv,
1061 enum intel_display_power_domain domain);
1062 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1063 void intel_init_gt_powersave(struct drm_device *dev);
1064 void intel_cleanup_gt_powersave(struct drm_device *dev);
1065 void intel_enable_gt_powersave(struct drm_device *dev);
1066 void intel_disable_gt_powersave(struct drm_device *dev);
1067 void intel_suspend_gt_powersave(struct drm_device *dev);
1068 void intel_reset_gt_powersave(struct drm_device *dev);
1069 void ironlake_teardown_rc6(struct drm_device *dev);
1070 void gen6_update_ring_freq(struct drm_device *dev);
1071 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1072 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1073 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1074 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1075 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1076 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1077 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1078 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1079 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1080 void ilk_wm_get_hw_state(struct drm_device *dev);
1084 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1087 /* intel_sprite.c */
1088 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1089 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1091 int intel_plane_restore(struct drm_plane *plane);
1092 void intel_plane_disable(struct drm_plane *plane);
1093 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv);
1095 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1096 struct drm_file *file_priv);
1100 void intel_tv_init(struct drm_device *dev);
1102 #endif /* __INTEL_DRV_H__ */