2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * __wait_for - magic wait macro
46 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
47 * important that we check the condition again after having timed out, since the
48 * timeout could be due to preemption or similar and we've never had a chance to
49 * check the condition before the timeout.
51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
52 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
53 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
57 bool expired__ = time_after(jiffies, timeout__); \
67 usleep_range(wait__, wait__ * 2); \
68 if (wait__ < (Wmax)) \
74 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
76 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
78 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
79 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
80 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
85 #define _wait_for_atomic(COND, US, ATOMIC) \
87 int cpu, ret, timeout = (US) * 1000; \
89 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
92 cpu = smp_processor_id(); \
94 base = local_clock(); \
96 u64 now = local_clock(); \
103 if (now - base >= timeout) { \
110 if (unlikely(cpu != smp_processor_id())) { \
111 timeout -= now - base; \
112 cpu = smp_processor_id(); \
113 base = local_clock(); \
120 #define wait_for_us(COND, US) \
123 BUILD_BUG_ON(!__builtin_constant_p(US)); \
125 ret__ = _wait_for((COND), (US), 10, 10); \
127 ret__ = _wait_for_atomic((COND), (US), 0); \
131 #define wait_for_atomic_us(COND, US) \
133 BUILD_BUG_ON(!__builtin_constant_p(US)); \
134 BUILD_BUG_ON((US) > 50000); \
135 _wait_for_atomic((COND), (US), 1); \
138 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
140 #define KHz(x) (1000 * (x))
141 #define MHz(x) KHz(1000 * (x))
144 * Display related stuff
147 /* store information about an Ixxx DVO */
148 /* The i830->i865 use multiple DVOs with multiple i2cs */
149 /* the i915, i945 have a single sDVO i2c bus - which is different */
150 #define MAX_OUTPUTS 6
151 /* maximum connectors per crtcs in the mode set */
153 /* Maximum cursor sizes */
154 #define GEN2_CURSOR_WIDTH 64
155 #define GEN2_CURSOR_HEIGHT 64
156 #define MAX_CURSOR_WIDTH 256
157 #define MAX_CURSOR_HEIGHT 256
159 #define INTEL_I2C_BUS_DVO 1
160 #define INTEL_I2C_BUS_SDVO 2
162 /* these are outputs from the chip - integrated only
163 external chips are via DVO or SDVO output */
164 enum intel_output_type {
165 INTEL_OUTPUT_UNUSED = 0,
166 INTEL_OUTPUT_ANALOG = 1,
167 INTEL_OUTPUT_DVO = 2,
168 INTEL_OUTPUT_SDVO = 3,
169 INTEL_OUTPUT_LVDS = 4,
170 INTEL_OUTPUT_TVOUT = 5,
171 INTEL_OUTPUT_HDMI = 6,
173 INTEL_OUTPUT_EDP = 8,
174 INTEL_OUTPUT_DSI = 9,
175 INTEL_OUTPUT_DDI = 10,
176 INTEL_OUTPUT_DP_MST = 11,
179 #define INTEL_DVO_CHIP_NONE 0
180 #define INTEL_DVO_CHIP_LVDS 1
181 #define INTEL_DVO_CHIP_TMDS 2
182 #define INTEL_DVO_CHIP_TVOUT 4
184 #define INTEL_DSI_VIDEO_MODE 0
185 #define INTEL_DSI_COMMAND_MODE 1
187 struct intel_framebuffer {
188 struct drm_framebuffer base;
189 struct drm_i915_gem_object *obj;
190 struct intel_rotation_info rot_info;
192 /* for each plane in the normal GTT view */
196 /* for each plane in the rotated GTT view */
199 unsigned int pitch; /* pixels */
204 struct drm_fb_helper helper;
205 struct intel_framebuffer *fb;
206 struct i915_vma *vma;
207 async_cookie_t cookie;
211 struct intel_encoder {
212 struct drm_encoder base;
214 enum intel_output_type type;
216 unsigned int cloneable;
217 void (*hot_plug)(struct intel_encoder *);
218 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
219 struct intel_crtc_state *,
220 struct drm_connector_state *);
221 bool (*compute_config)(struct intel_encoder *,
222 struct intel_crtc_state *,
223 struct drm_connector_state *);
224 void (*pre_pll_enable)(struct intel_encoder *,
225 const struct intel_crtc_state *,
226 const struct drm_connector_state *);
227 void (*pre_enable)(struct intel_encoder *,
228 const struct intel_crtc_state *,
229 const struct drm_connector_state *);
230 void (*enable)(struct intel_encoder *,
231 const struct intel_crtc_state *,
232 const struct drm_connector_state *);
233 void (*disable)(struct intel_encoder *,
234 const struct intel_crtc_state *,
235 const struct drm_connector_state *);
236 void (*post_disable)(struct intel_encoder *,
237 const struct intel_crtc_state *,
238 const struct drm_connector_state *);
239 void (*post_pll_disable)(struct intel_encoder *,
240 const struct intel_crtc_state *,
241 const struct drm_connector_state *);
242 /* Read out the current hw state of this connector, returning true if
243 * the encoder is active. If the encoder is enabled it also set the pipe
244 * it is connected to in the pipe parameter. */
245 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
246 /* Reconstructs the equivalent mode flags for the current hardware
247 * state. This must be called _after_ display->get_pipe_config has
248 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
249 * be set correctly before calling this function. */
250 void (*get_config)(struct intel_encoder *,
251 struct intel_crtc_state *pipe_config);
252 /* Returns a mask of power domains that need to be referenced as part
253 * of the hardware state readout code. */
254 u64 (*get_power_domains)(struct intel_encoder *encoder);
256 * Called during system suspend after all pending requests for the
257 * encoder are flushed (for example for DP AUX transactions) and
258 * device interrupts are disabled.
260 void (*suspend)(struct intel_encoder *);
262 enum hpd_pin hpd_pin;
263 enum intel_display_power_domain power_domain;
264 /* for communication with audio component; protected by av_mutex */
265 const struct drm_connector *audio_connector;
269 struct drm_display_mode *fixed_mode;
270 struct drm_display_mode *alt_fixed_mode;
271 struct drm_display_mode *downclock_mode;
280 bool combination_mode; /* gen 2/4 only */
282 bool alternate_pwm_increment; /* lpt+ */
285 bool util_pin_active_low; /* bxt+ */
286 u8 controller; /* bxt+ only */
287 struct pwm_device *pwm;
289 struct backlight_device *device;
291 /* Connector and platform specific backlight functions */
292 int (*setup)(struct intel_connector *connector, enum pipe pipe);
293 uint32_t (*get)(struct intel_connector *connector);
294 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
295 void (*disable)(const struct drm_connector_state *conn_state);
296 void (*enable)(const struct intel_crtc_state *crtc_state,
297 const struct drm_connector_state *conn_state);
298 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
300 void (*power)(struct intel_connector *, bool enable);
305 * This structure serves as a translation layer between the generic HDCP code
306 * and the bus-specific code. What that means is that HDCP over HDMI differs
307 * from HDCP over DP, so to account for these differences, we need to
308 * communicate with the receiver through this shim.
310 * For completeness, the 2 buses differ in the following ways:
312 * HDCP registers on the receiver are set via DP AUX for DP, and
313 * they are set via DDC for HDMI.
314 * - Receiver register offsets
315 * The offsets of the registers are different for DP vs. HDMI
316 * - Receiver register masks/offsets
317 * For instance, the ready bit for the KSV fifo is in a different
318 * place on DP vs HDMI
319 * - Receiver register names
320 * Seriously. In the DP spec, the 16-bit register containing
321 * downstream information is called BINFO, on HDMI it's called
322 * BSTATUS. To confuse matters further, DP has a BSTATUS register
323 * with a completely different definition.
325 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
326 * be read 3 keys at a time
328 * Since Aksv is hidden in hardware, there's different procedures
329 * to send it over DP AUX vs DDC
331 struct intel_hdcp_shim {
332 /* Outputs the transmitter's An and Aksv values to the receiver. */
333 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
335 /* Reads the receiver's key selection vector */
336 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
339 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
340 * definitions are the same in the respective specs, but the names are
341 * different. Call it BSTATUS since that's the name the HDMI spec
342 * uses and it was there first.
344 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
347 /* Determines whether a repeater is present downstream */
348 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
349 bool *repeater_present);
351 /* Reads the receiver's Ri' value */
352 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
354 /* Determines if the receiver's KSV FIFO is ready for consumption */
355 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
358 /* Reads the ksv fifo for num_downstream devices */
359 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
360 int num_downstream, u8 *ksv_fifo);
362 /* Reads a 32-bit part of V' from the receiver */
363 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
366 /* Enables HDCP signalling on the port */
367 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
370 /* Ensures the link is still protected */
371 bool (*check_link)(struct intel_digital_port *intel_dig_port);
373 /* Detects panel's hdcp capability. This is optional for HDMI. */
374 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
378 struct intel_connector {
379 struct drm_connector base;
381 * The fixed encoder this connector is connected to.
383 struct intel_encoder *encoder;
385 /* ACPI device id for ACPI and driver cooperation */
388 /* Reads out the current hw, returning true if the connector is enabled
389 * and active (i.e. dpms ON state). */
390 bool (*get_hw_state)(struct intel_connector *);
392 /* Panel info for eDP and LVDS */
393 struct intel_panel panel;
395 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
397 struct edid *detect_edid;
399 /* since POLL and HPD connectors may use the same HPD line keep the native
400 state of connector->polled in case hotplug storm detection changes it */
403 void *port; /* store this opaque as its illegal to dereference it */
405 struct intel_dp *mst_port;
407 /* Work struct to schedule a uevent on link train failure */
408 struct work_struct modeset_retry_work;
410 const struct intel_hdcp_shim *hdcp_shim;
411 struct mutex hdcp_mutex;
412 uint64_t hdcp_value; /* protected by hdcp_mutex */
413 struct delayed_work hdcp_check_work;
414 struct work_struct hdcp_prop_work;
417 struct intel_digital_connector_state {
418 struct drm_connector_state base;
420 enum hdmi_force_audio force_audio;
424 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
438 struct intel_atomic_state {
439 struct drm_atomic_state base;
443 * Logical state of cdclk (used for all scaling, watermark,
444 * etc. calculations and checks). This is computed as if all
445 * enabled crtcs were active.
447 struct intel_cdclk_state logical;
450 * Actual state of cdclk, can be different from the logical
451 * state only when all crtc's are DPMS off.
453 struct intel_cdclk_state actual;
456 bool dpll_set, modeset;
459 * Does this transaction change the pipes that are active? This mask
460 * tracks which CRTC's have changed their active state at the end of
461 * the transaction (not counting the temporary disable during modesets).
462 * This mask should only be non-zero when intel_state->modeset is true,
463 * but the converse is not necessarily true; simply changing a mode may
464 * not flip the final active status of any CRTC's
466 unsigned int active_pipe_changes;
468 unsigned int active_crtcs;
469 /* minimum acceptable cdclk for each pipe */
470 int min_cdclk[I915_MAX_PIPES];
471 /* minimum acceptable voltage level for each pipe */
472 u8 min_voltage_level[I915_MAX_PIPES];
474 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
477 * Current watermarks can't be trusted during hardware readout, so
478 * don't bother calculating intermediate watermarks.
480 bool skip_intermediate_wm;
483 struct skl_wm_values wm_results;
485 struct i915_sw_fence commit_ready;
487 struct llist_node freed;
490 struct intel_plane_state {
491 struct drm_plane_state base;
492 struct i915_vma *vma;
503 /* plane control register */
506 /* plane color control register */
511 * = -1 : not using a scaler
512 * >= 0 : using a scalers
514 * plane requiring a scaler:
515 * - During check_plane, its bit is set in
516 * crtc_state->scaler_state.scaler_users by calling helper function
517 * update_scaler_plane.
518 * - scaler_id indicates the scaler it got assigned.
520 * plane doesn't require a scaler:
521 * - this can happen when scaling is no more required or plane simply
523 * - During check_plane, corresponding bit is reset in
524 * crtc_state->scaler_state.scaler_users by calling helper function
525 * update_scaler_plane.
529 struct drm_intel_sprite_colorkey ckey;
532 struct intel_initial_plane_config {
533 struct intel_framebuffer *fb;
539 #define SKL_MIN_SRC_W 8
540 #define SKL_MAX_SRC_W 4096
541 #define SKL_MIN_SRC_H 8
542 #define SKL_MAX_SRC_H 4096
543 #define SKL_MIN_DST_W 8
544 #define SKL_MAX_DST_W 4096
545 #define SKL_MIN_DST_H 8
546 #define SKL_MAX_DST_H 4096
548 struct intel_scaler {
553 struct intel_crtc_scaler_state {
554 #define SKL_NUM_SCALERS 2
555 struct intel_scaler scalers[SKL_NUM_SCALERS];
558 * scaler_users: keeps track of users requesting scalers on this crtc.
560 * If a bit is set, a user is using a scaler.
561 * Here user can be a plane or crtc as defined below:
562 * bits 0-30 - plane (bit position is index from drm_plane_index)
565 * Instead of creating a new index to cover planes and crtc, using
566 * existing drm_plane_index for planes which is well less than 31
567 * planes and bit 31 for crtc. This should be fine to cover all
570 * intel_atomic_setup_scalers will setup available scalers to users
571 * requesting scalers. It will gracefully fail if request exceeds
574 #define SKL_CRTC_INDEX 31
575 unsigned scaler_users;
577 /* scaler used by crtc for panel fitting purpose */
581 /* drm_mode->private_flags */
582 #define I915_MODE_FLAG_INHERITED 1
583 /* Flag to get scanline using frame time stamps */
584 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
586 struct intel_pipe_wm {
587 struct intel_wm_level wm[5];
591 bool sprites_enabled;
595 struct skl_plane_wm {
596 struct skl_wm_level wm[8];
597 struct skl_wm_level trans_wm;
601 struct skl_plane_wm planes[I915_MAX_PLANES];
608 VLV_WM_LEVEL_DDR_DVFS,
612 struct vlv_wm_state {
613 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
614 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
619 struct vlv_fifo_state {
620 u16 plane[I915_MAX_PLANES];
630 struct g4x_wm_state {
631 struct g4x_pipe_wm wm;
633 struct g4x_sr_wm hpll;
639 struct intel_crtc_wm_state {
643 * Intermediate watermarks; these can be
644 * programmed immediately since they satisfy
645 * both the current configuration we're
646 * switching away from and the new
647 * configuration we're switching to.
649 struct intel_pipe_wm intermediate;
652 * Optimal watermarks, programmed post-vblank
653 * when this state is committed.
655 struct intel_pipe_wm optimal;
659 /* gen9+ only needs 1-step wm programming */
660 struct skl_pipe_wm optimal;
661 struct skl_ddb_entry ddb;
665 /* "raw" watermarks (not inverted) */
666 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
667 /* intermediate watermarks (inverted) */
668 struct vlv_wm_state intermediate;
669 /* optimal watermarks (inverted) */
670 struct vlv_wm_state optimal;
671 /* display FIFO split */
672 struct vlv_fifo_state fifo_state;
676 /* "raw" watermarks */
677 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
678 /* intermediate watermarks */
679 struct g4x_wm_state intermediate;
680 /* optimal watermarks */
681 struct g4x_wm_state optimal;
686 * Platforms with two-step watermark programming will need to
687 * update watermark programming post-vblank to switch from the
688 * safe intermediate watermarks to the optimal final
691 bool need_postvbl_update;
694 struct intel_crtc_state {
695 struct drm_crtc_state base;
698 * quirks - bitfield with hw state readout quirks
700 * For various reasons the hw state readout code might not be able to
701 * completely faithfully read out the current state. These cases are
702 * tracked with quirk flags so that fastboot and state checker can act
705 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
706 unsigned long quirks;
708 unsigned fb_bits; /* framebuffers to flip */
709 bool update_pipe; /* can a fast modeset be performed? */
711 bool update_wm_pre, update_wm_post; /* watermarks are updated */
712 bool fb_changed; /* fb on any of the planes is changed */
713 bool fifo_changed; /* FIFO split is changed */
715 /* Pipe source size (ie. panel fitter input size)
716 * All planes will be positioned inside this space,
717 * and get clipped at the edges. */
718 int pipe_src_w, pipe_src_h;
721 * Pipe pixel rate, adjusted for
722 * panel fitter/pipe scaler downscaling.
724 unsigned int pixel_rate;
726 /* Whether to set up the PCH/FDI. Note that we never allow sharing
727 * between pch encoders and cpu encoders. */
728 bool has_pch_encoder;
730 /* Are we sending infoframes on the attached port */
733 /* CPU Transcoder for the pipe. Currently this can only differ from the
734 * pipe on Haswell and later (where we have a special eDP transcoder)
735 * and Broxton (where we have special DSI transcoders). */
736 enum transcoder cpu_transcoder;
739 * Use reduced/limited/broadcast rbg range, compressing from the full
740 * range fed into the crtcs.
742 bool limited_color_range;
744 /* Bitmask of encoder types (enum intel_output_type)
745 * driven by the pipe.
747 unsigned int output_types;
749 /* Whether we should send NULL infoframes. Required for audio. */
752 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
753 * has_dp_encoder is set. */
757 * Enable dithering, used when the selected pipe bpp doesn't match the
763 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
764 * compliance video pattern tests.
765 * Disable dither only if it is a compliance test request for
768 bool dither_force_disable;
770 /* Controls for the clock computation, to override various stages. */
773 /* SDVO TV has a bunch of special case. To make multifunction encoders
774 * work correctly, we need to track this at runtime.*/
778 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
779 * required. This is set in the 2nd loop of calling encoder's
780 * ->compute_config if the first pick doesn't work out.
784 /* Settings for the intel dpll used on pretty much everything but
788 /* Selected dpll when shared or NULL. */
789 struct intel_shared_dpll *shared_dpll;
791 /* Actual register state of the dpll, for shared dpll cross-checking. */
792 struct intel_dpll_hw_state dpll_hw_state;
794 /* DSI PLL registers */
800 struct intel_link_m_n dp_m_n;
802 /* m2_n2 for eDP downclock */
803 struct intel_link_m_n dp_m2_n2;
810 * Frequence the dpll for the port should run at. Differs from the
811 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
812 * already multiplied by pixel_multiplier.
816 /* Used by SDVO (and if we ever fix it, HDMI). */
817 unsigned pixel_multiplier;
822 * Used by platforms having DP/HDMI PHY with programmable lane
823 * latency optimization.
825 uint8_t lane_lat_optim_mask;
827 /* minimum acceptable voltage level */
828 u8 min_voltage_level;
830 /* Panel fitter controls for gen2-gen4 + VLV */
834 u32 lvds_border_bits;
837 /* Panel fitter placement and size for Ironlake+ */
845 /* FDI configuration, only valid if has_pch_encoder is set. */
847 struct intel_link_m_n fdi_m_n;
850 bool ips_force_disable;
858 struct intel_crtc_scaler_state scaler_state;
860 /* w/a for waiting 2 vblanks during crtc enable */
861 enum pipe hsw_workaround_pipe;
863 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
866 struct intel_crtc_wm_state wm;
868 /* Gamma mode programmed on the pipe */
871 /* bitmask of visible planes (enum plane_id) */
874 /* HDMI scrambling status */
875 bool hdmi_scrambling;
877 /* HDMI High TMDS char rate ratio */
878 bool hdmi_high_tmds_clock_ratio;
880 /* output format is YCBCR 4:2:0 */
885 struct drm_crtc base;
888 * Whether the crtc and the connected output pipeline is active. Implies
889 * that crtc->enabled is set, i.e. the current mode configuration has
890 * some outputs connected to this crtc.
894 unsigned long long enabled_power_domains;
895 struct intel_overlay *overlay;
897 struct intel_crtc_state *config;
899 /* global reset count when the last flip was submitted */
900 unsigned int reset_count;
902 /* Access to these should be protected by dev_priv->irq_lock. */
903 bool cpu_fifo_underrun_disabled;
904 bool pch_fifo_underrun_disabled;
906 /* per-pipe watermark state */
908 /* watermarks currently being used */
910 struct intel_pipe_wm ilk;
911 struct vlv_wm_state vlv;
912 struct g4x_wm_state g4x;
919 unsigned start_vbl_count;
920 ktime_t start_vbl_time;
921 int min_vbl, max_vbl;
925 /* scalers available on this crtc */
930 struct drm_plane base;
931 enum i9xx_plane_id i9xx_plane;
936 uint32_t frontbuffer_bit;
939 u32 base, cntl, size;
943 * NOTE: Do not place new plane state fields here (e.g., when adding
944 * new plane properties). New runtime state should now be placed in
945 * the intel_plane_state structure and accessed via plane_state.
948 void (*update_plane)(struct intel_plane *plane,
949 const struct intel_crtc_state *crtc_state,
950 const struct intel_plane_state *plane_state);
951 void (*disable_plane)(struct intel_plane *plane,
952 struct intel_crtc *crtc);
953 bool (*get_hw_state)(struct intel_plane *plane);
954 int (*check_plane)(struct intel_plane *plane,
955 struct intel_crtc_state *crtc_state,
956 struct intel_plane_state *state);
959 struct intel_watermark_params {
967 struct cxsr_latency {
973 u16 display_hpll_disable;
975 u16 cursor_hpll_disable;
978 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
979 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
980 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
981 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
982 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
983 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
984 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
985 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
986 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
992 enum drm_dp_dual_mode_type type;
997 bool rgb_quant_range_selectable;
998 struct intel_connector *attached_connector;
1001 struct intel_dp_mst_encoder;
1002 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1005 * enum link_m_n_set:
1006 * When platform provides two set of M_N registers for dp, we can
1007 * program them and switch between them incase of DRRS.
1008 * But When only one such register is provided, we have to program the
1009 * required divider value on that registers itself based on the DRRS state.
1011 * M1_N1 : Program dp_m_n on M1_N1 registers
1012 * dp_m2_n2 on M2_N2 registers (If supported)
1014 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1015 * M2_N2 registers are not supported
1019 /* Sets the m1_n1 and m2_n2 */
1024 struct intel_dp_compliance_data {
1026 uint8_t video_pattern;
1027 uint16_t hdisplay, vdisplay;
1031 struct intel_dp_compliance {
1032 unsigned long test_type;
1033 struct intel_dp_compliance_data test_data;
1040 i915_reg_t output_reg;
1041 i915_reg_t aux_ch_ctl_reg;
1042 i915_reg_t aux_ch_data_reg[5];
1050 bool channel_eq_status;
1051 bool reset_link_params;
1052 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1053 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1054 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1055 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1057 int num_source_rates;
1058 const int *source_rates;
1059 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1061 int sink_rates[DP_MAX_SUPPORTED_RATES];
1062 bool use_rate_select;
1063 /* intersection of source and sink rates */
1064 int num_common_rates;
1065 int common_rates[DP_MAX_SUPPORTED_RATES];
1066 /* Max lane count for the current link */
1067 int max_link_lane_count;
1068 /* Max rate for the current link */
1070 /* sink or branch descriptor */
1071 struct drm_dp_desc desc;
1072 struct drm_dp_aux aux;
1073 enum intel_display_power_domain aux_power_domain;
1074 uint8_t train_set[4];
1075 int panel_power_up_delay;
1076 int panel_power_down_delay;
1077 int panel_power_cycle_delay;
1078 int backlight_on_delay;
1079 int backlight_off_delay;
1080 struct delayed_work panel_vdd_work;
1081 bool want_panel_vdd;
1082 unsigned long last_power_on;
1083 unsigned long last_backlight_off;
1084 ktime_t panel_power_off_time;
1086 struct notifier_block edp_notifier;
1089 * Pipe whose power sequencer is currently locked into
1090 * this port. Only relevant on VLV/CHV.
1094 * Pipe currently driving the port. Used for preventing
1095 * the use of the PPS for any pipe currentrly driving
1096 * external DP as that will mess things up on VLV.
1098 enum pipe active_pipe;
1100 * Set if the sequencer may be reset due to a power transition,
1101 * requiring a reinitialization. Only relevant on BXT.
1104 struct edp_power_seq pps_delays;
1106 bool can_mst; /* this port supports mst */
1108 int active_mst_links;
1109 /* connector directly attached - won't be use for modeset in mst world */
1110 struct intel_connector *attached_connector;
1112 /* mst connector list */
1113 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1114 struct drm_dp_mst_topology_mgr mst_mgr;
1116 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1118 * This function returns the value we have to program the AUX_CTL
1119 * register with to kick off an AUX transaction.
1121 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1124 uint32_t aux_clock_divider);
1126 /* This is called before a link training is starterd */
1127 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1129 /* Displayport compliance testing */
1130 struct intel_dp_compliance compliance;
1133 struct intel_lspcon {
1135 enum drm_lspcon_mode mode;
1138 struct intel_digital_port {
1139 struct intel_encoder base;
1140 u32 saved_port_bits;
1142 struct intel_hdmi hdmi;
1143 struct intel_lspcon lspcon;
1144 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1145 bool release_cl2_override;
1147 enum intel_display_power_domain ddi_io_power_domain;
1149 void (*write_infoframe)(struct drm_encoder *encoder,
1150 const struct intel_crtc_state *crtc_state,
1152 const void *frame, ssize_t len);
1153 void (*set_infoframes)(struct drm_encoder *encoder,
1155 const struct intel_crtc_state *crtc_state,
1156 const struct drm_connector_state *conn_state);
1157 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1158 const struct intel_crtc_state *pipe_config);
1161 struct intel_dp_mst_encoder {
1162 struct intel_encoder base;
1164 struct intel_digital_port *primary;
1165 struct intel_connector *connector;
1168 static inline enum dpio_channel
1169 vlv_dport_to_channel(struct intel_digital_port *dport)
1171 switch (dport->base.port) {
1182 static inline enum dpio_phy
1183 vlv_dport_to_phy(struct intel_digital_port *dport)
1185 switch (dport->base.port) {
1196 static inline enum dpio_channel
1197 vlv_pipe_to_channel(enum pipe pipe)
1210 static inline struct intel_crtc *
1211 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1213 return dev_priv->pipe_to_crtc_mapping[pipe];
1216 static inline struct intel_crtc *
1217 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1219 return dev_priv->plane_to_crtc_mapping[plane];
1222 struct intel_load_detect_pipe {
1223 struct drm_atomic_state *restore_state;
1226 static inline struct intel_encoder *
1227 intel_attached_encoder(struct drm_connector *connector)
1229 return to_intel_connector(connector)->encoder;
1232 static inline struct intel_digital_port *
1233 enc_to_dig_port(struct drm_encoder *encoder)
1235 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1237 switch (intel_encoder->type) {
1238 case INTEL_OUTPUT_DDI:
1239 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1240 case INTEL_OUTPUT_DP:
1241 case INTEL_OUTPUT_EDP:
1242 case INTEL_OUTPUT_HDMI:
1243 return container_of(encoder, struct intel_digital_port,
1250 static inline struct intel_dp_mst_encoder *
1251 enc_to_mst(struct drm_encoder *encoder)
1253 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1256 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1258 return &enc_to_dig_port(encoder)->dp;
1261 static inline struct intel_digital_port *
1262 dp_to_dig_port(struct intel_dp *intel_dp)
1264 return container_of(intel_dp, struct intel_digital_port, dp);
1267 static inline struct intel_lspcon *
1268 dp_to_lspcon(struct intel_dp *intel_dp)
1270 return &dp_to_dig_port(intel_dp)->lspcon;
1273 static inline struct intel_digital_port *
1274 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1276 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1279 static inline struct intel_plane_state *
1280 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1281 struct intel_plane *plane)
1283 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1287 static inline struct intel_crtc_state *
1288 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1289 struct intel_crtc *crtc)
1291 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1295 static inline struct intel_crtc_state *
1296 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1297 struct intel_crtc *crtc)
1299 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1303 /* intel_fifo_underrun.c */
1304 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool enable);
1306 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1307 enum pipe pch_transcoder,
1309 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1311 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1312 enum pipe pch_transcoder);
1313 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1314 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1317 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1318 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1319 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1320 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1321 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1322 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1323 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1325 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1328 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1331 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1332 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1333 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1336 * We only use drm_irq_uninstall() at unload and VT switch, so
1337 * this is the only thing we need to check.
1339 return dev_priv->runtime_pm.irqs_enabled;
1342 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1343 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1345 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1347 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1348 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1349 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1352 void intel_crt_init(struct drm_i915_private *dev_priv);
1353 void intel_crt_reset(struct drm_encoder *encoder);
1356 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1357 const struct intel_crtc_state *old_crtc_state,
1358 const struct drm_connector_state *old_conn_state);
1359 void hsw_fdi_link_train(struct intel_crtc *crtc,
1360 const struct intel_crtc_state *crtc_state);
1361 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1362 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1363 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1364 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1365 enum transcoder cpu_transcoder);
1366 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1367 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1368 struct intel_encoder *
1369 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1370 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1371 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1372 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1373 void intel_ddi_get_config(struct intel_encoder *encoder,
1374 struct intel_crtc_state *pipe_config);
1376 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1378 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1379 struct intel_crtc_state *crtc_state);
1380 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1381 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1382 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1383 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1386 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1387 int plane, unsigned int height);
1390 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1391 void intel_audio_codec_enable(struct intel_encoder *encoder,
1392 const struct intel_crtc_state *crtc_state,
1393 const struct drm_connector_state *conn_state);
1394 void intel_audio_codec_disable(struct intel_encoder *encoder,
1395 const struct intel_crtc_state *old_crtc_state,
1396 const struct drm_connector_state *old_conn_state);
1397 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1398 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1399 void intel_audio_init(struct drm_i915_private *dev_priv);
1400 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1403 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1404 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1405 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1406 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1407 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1408 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1409 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1410 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1411 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1412 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1413 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1414 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1415 const struct intel_cdclk_state *b);
1416 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1417 const struct intel_cdclk_state *b);
1418 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1419 const struct intel_cdclk_state *cdclk_state);
1420 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1421 const char *context);
1423 /* intel_display.c */
1424 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1425 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1426 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1427 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1428 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1429 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1430 const char *name, u32 reg, int ref_freq);
1431 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1432 const char *name, u32 reg);
1433 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1434 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1435 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1436 unsigned int intel_fb_xy_to_linear(int x, int y,
1437 const struct intel_plane_state *state,
1439 void intel_add_fb_offsets(int *x, int *y,
1440 const struct intel_plane_state *state, int plane);
1441 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1442 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1443 void intel_mark_busy(struct drm_i915_private *dev_priv);
1444 void intel_mark_idle(struct drm_i915_private *dev_priv);
1445 int intel_display_suspend(struct drm_device *dev);
1446 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1447 void intel_encoder_destroy(struct drm_encoder *encoder);
1448 int intel_connector_init(struct intel_connector *);
1449 struct intel_connector *intel_connector_alloc(void);
1450 void intel_connector_free(struct intel_connector *connector);
1451 bool intel_connector_get_hw_state(struct intel_connector *connector);
1452 void intel_connector_attach_encoder(struct intel_connector *connector,
1453 struct intel_encoder *encoder);
1454 struct drm_display_mode *
1455 intel_encoder_current_mode(struct intel_encoder *encoder);
1457 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1458 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1459 struct drm_file *file_priv);
1460 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1463 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1464 enum intel_output_type type)
1466 return crtc_state->output_types & (1 << type);
1469 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1471 return crtc_state->output_types &
1472 ((1 << INTEL_OUTPUT_DP) |
1473 (1 << INTEL_OUTPUT_DP_MST) |
1474 (1 << INTEL_OUTPUT_EDP));
1477 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 drm_wait_one_vblank(&dev_priv->drm, pipe);
1482 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1484 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1487 intel_wait_for_vblank(dev_priv, pipe);
1490 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1492 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1494 struct intel_digital_port *dport,
1495 unsigned int expected_mask);
1496 int intel_get_load_detect_pipe(struct drm_connector *connector,
1497 const struct drm_display_mode *mode,
1498 struct intel_load_detect_pipe *old,
1499 struct drm_modeset_acquire_ctx *ctx);
1500 void intel_release_load_detect_pipe(struct drm_connector *connector,
1501 struct intel_load_detect_pipe *old,
1502 struct drm_modeset_acquire_ctx *ctx);
1504 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1505 void intel_unpin_fb_vma(struct i915_vma *vma);
1506 struct drm_framebuffer *
1507 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1508 struct drm_mode_fb_cmd2 *mode_cmd);
1509 int intel_prepare_plane_fb(struct drm_plane *plane,
1510 struct drm_plane_state *new_state);
1511 void intel_cleanup_plane_fb(struct drm_plane *plane,
1512 struct drm_plane_state *old_state);
1513 int intel_plane_atomic_get_property(struct drm_plane *plane,
1514 const struct drm_plane_state *state,
1515 struct drm_property *property,
1517 int intel_plane_atomic_set_property(struct drm_plane *plane,
1518 struct drm_plane_state *state,
1519 struct drm_property *property,
1521 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1522 struct drm_crtc_state *crtc_state,
1523 const struct intel_plane_state *old_plane_state,
1524 struct drm_plane_state *plane_state);
1526 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1529 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1530 const struct dpll *dpll);
1531 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1532 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1534 /* modesetting asserts */
1535 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1537 void assert_pll(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, bool state);
1539 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1540 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1541 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1542 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1543 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1544 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, bool state);
1546 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1547 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1548 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1549 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1550 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1551 u32 intel_compute_tile_offset(int *x, int *y,
1552 const struct intel_plane_state *state, int plane);
1553 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1554 void intel_finish_reset(struct drm_i915_private *dev_priv);
1555 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1556 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1557 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1558 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1559 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1560 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1561 unsigned int skl_cdclk_get_vco(unsigned int freq);
1562 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1563 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1564 void intel_dp_get_m_n(struct intel_crtc *crtc,
1565 struct intel_crtc_state *pipe_config);
1566 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1567 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1568 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1569 struct dpll *best_clock);
1570 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1572 bool intel_crtc_active(struct intel_crtc *crtc);
1573 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1574 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1575 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1576 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1577 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1578 struct intel_crtc_state *pipe_config);
1580 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1581 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1583 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1585 return i915_ggtt_offset(state->vma);
1588 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1589 const struct intel_plane_state *plane_state);
1590 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1591 const struct intel_plane_state *plane_state);
1592 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1593 unsigned int rotation);
1594 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1595 struct intel_plane_state *plane_state);
1596 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1599 void intel_csr_ucode_init(struct drm_i915_private *);
1600 void intel_csr_load_program(struct drm_i915_private *);
1601 void intel_csr_ucode_fini(struct drm_i915_private *);
1602 void intel_csr_ucode_suspend(struct drm_i915_private *);
1603 void intel_csr_ucode_resume(struct drm_i915_private *);
1606 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1608 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1609 struct intel_connector *intel_connector);
1610 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1611 int link_rate, uint8_t lane_count,
1613 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1614 int link_rate, uint8_t lane_count);
1615 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1616 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1617 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1618 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1619 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1620 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1621 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1622 struct intel_crtc_state *crtc_state, u8 *crc);
1623 bool intel_dp_compute_config(struct intel_encoder *encoder,
1624 struct intel_crtc_state *pipe_config,
1625 struct drm_connector_state *conn_state);
1626 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1627 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1628 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1630 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1631 const struct drm_connector_state *conn_state);
1632 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1633 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1634 void intel_edp_panel_on(struct intel_dp *intel_dp);
1635 void intel_edp_panel_off(struct intel_dp *intel_dp);
1636 void intel_dp_mst_suspend(struct drm_device *dev);
1637 void intel_dp_mst_resume(struct drm_device *dev);
1638 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1639 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1640 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1641 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1642 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1643 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1644 void intel_plane_destroy(struct drm_plane *plane);
1645 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1646 const struct intel_crtc_state *crtc_state);
1647 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1648 const struct intel_crtc_state *crtc_state);
1649 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1650 unsigned int frontbuffer_bits);
1651 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1652 unsigned int frontbuffer_bits);
1655 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1656 uint8_t dp_train_pat);
1658 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1659 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1661 intel_dp_voltage_max(struct intel_dp *intel_dp);
1663 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1664 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1665 uint8_t *link_bw, uint8_t *rate_select);
1666 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1668 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1670 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1672 return ~((1 << lane_count) - 1) & 0xf;
1675 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1676 int intel_dp_link_required(int pixel_clock, int bpp);
1677 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1678 bool intel_digital_port_connected(struct intel_encoder *encoder);
1680 /* intel_dp_aux_backlight.c */
1681 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1683 /* intel_dp_mst.c */
1684 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1685 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1687 void intel_dsi_init(struct drm_i915_private *dev_priv);
1689 /* intel_dsi_dcs_backlight.c */
1690 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1693 void intel_dvo_init(struct drm_i915_private *dev_priv);
1694 /* intel_hotplug.c */
1695 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1698 /* legacy fbdev emulation in intel_fbdev.c */
1699 #ifdef CONFIG_DRM_FBDEV_EMULATION
1700 extern int intel_fbdev_init(struct drm_device *dev);
1701 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1702 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1703 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1704 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1705 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1706 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1708 static inline int intel_fbdev_init(struct drm_device *dev)
1713 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1717 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1721 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1725 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1729 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1733 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1739 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1740 struct intel_atomic_state *state);
1741 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1742 void intel_fbc_pre_update(struct intel_crtc *crtc,
1743 struct intel_crtc_state *crtc_state,
1744 struct intel_plane_state *plane_state);
1745 void intel_fbc_post_update(struct intel_crtc *crtc);
1746 void intel_fbc_init(struct drm_i915_private *dev_priv);
1747 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1748 void intel_fbc_enable(struct intel_crtc *crtc,
1749 struct intel_crtc_state *crtc_state,
1750 struct intel_plane_state *plane_state);
1751 void intel_fbc_disable(struct intel_crtc *crtc);
1752 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1753 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1754 unsigned int frontbuffer_bits,
1755 enum fb_op_origin origin);
1756 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1757 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1758 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1759 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1762 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1764 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1765 struct intel_connector *intel_connector);
1766 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1767 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1768 struct intel_crtc_state *pipe_config,
1769 struct drm_connector_state *conn_state);
1770 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1771 struct drm_connector *connector,
1772 bool high_tmds_clock_ratio,
1774 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1775 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1779 void intel_lvds_init(struct drm_i915_private *dev_priv);
1780 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1781 bool intel_is_dual_link_lvds(struct drm_device *dev);
1785 int intel_connector_update_modes(struct drm_connector *connector,
1787 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1788 void intel_attach_force_audio_property(struct drm_connector *connector);
1789 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1790 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1793 /* intel_overlay.c */
1794 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1795 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1796 int intel_overlay_switch_off(struct intel_overlay *overlay);
1797 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1798 struct drm_file *file_priv);
1799 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1800 struct drm_file *file_priv);
1801 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1805 int intel_panel_init(struct intel_panel *panel,
1806 struct drm_display_mode *fixed_mode,
1807 struct drm_display_mode *alt_fixed_mode,
1808 struct drm_display_mode *downclock_mode);
1809 void intel_panel_fini(struct intel_panel *panel);
1810 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1811 struct drm_display_mode *adjusted_mode);
1812 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1813 struct intel_crtc_state *pipe_config,
1815 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1816 struct intel_crtc_state *pipe_config,
1818 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1819 u32 level, u32 max);
1820 int intel_panel_setup_backlight(struct drm_connector *connector,
1822 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1823 const struct drm_connector_state *conn_state);
1824 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1825 void intel_panel_destroy_backlight(struct drm_connector *connector);
1826 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1827 extern struct drm_display_mode *intel_find_panel_downclock(
1828 struct drm_i915_private *dev_priv,
1829 struct drm_display_mode *fixed_mode,
1830 struct drm_connector *connector);
1832 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1833 int intel_backlight_device_register(struct intel_connector *connector);
1834 void intel_backlight_device_unregister(struct intel_connector *connector);
1835 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1836 static inline int intel_backlight_device_register(struct intel_connector *connector)
1840 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1843 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1846 void intel_hdcp_atomic_check(struct drm_connector *connector,
1847 struct drm_connector_state *old_state,
1848 struct drm_connector_state *new_state);
1849 int intel_hdcp_init(struct intel_connector *connector,
1850 const struct intel_hdcp_shim *hdcp_shim);
1851 int intel_hdcp_enable(struct intel_connector *connector);
1852 int intel_hdcp_disable(struct intel_connector *connector);
1853 int intel_hdcp_check_link(struct intel_connector *connector);
1854 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1857 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1858 void intel_psr_enable(struct intel_dp *intel_dp,
1859 const struct intel_crtc_state *crtc_state);
1860 void intel_psr_disable(struct intel_dp *intel_dp,
1861 const struct intel_crtc_state *old_crtc_state);
1862 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1863 unsigned frontbuffer_bits);
1864 void intel_psr_flush(struct drm_i915_private *dev_priv,
1865 unsigned frontbuffer_bits,
1866 enum fb_op_origin origin);
1867 void intel_psr_init(struct drm_i915_private *dev_priv);
1868 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1869 unsigned frontbuffer_bits);
1870 void intel_psr_compute_config(struct intel_dp *intel_dp,
1871 struct intel_crtc_state *crtc_state);
1873 /* intel_runtime_pm.c */
1874 int intel_power_domains_init(struct drm_i915_private *);
1875 void intel_power_domains_fini(struct drm_i915_private *);
1876 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1877 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1878 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1879 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1880 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1881 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1883 intel_display_power_domain_str(enum intel_display_power_domain domain);
1885 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1886 enum intel_display_power_domain domain);
1887 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1888 enum intel_display_power_domain domain);
1889 void intel_display_power_get(struct drm_i915_private *dev_priv,
1890 enum intel_display_power_domain domain);
1891 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1892 enum intel_display_power_domain domain);
1893 void intel_display_power_put(struct drm_i915_private *dev_priv,
1894 enum intel_display_power_domain domain);
1897 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1899 WARN_ONCE(dev_priv->runtime_pm.suspended,
1900 "Device suspended during HW access\n");
1904 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1906 assert_rpm_device_not_suspended(dev_priv);
1907 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1908 "RPM wakelock ref not held during HW access");
1912 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1913 * @dev_priv: i915 device instance
1915 * This function disable asserts that check if we hold an RPM wakelock
1916 * reference, while keeping the device-not-suspended checks still enabled.
1917 * It's meant to be used only in special circumstances where our rule about
1918 * the wakelock refcount wrt. the device power state doesn't hold. According
1919 * to this rule at any point where we access the HW or want to keep the HW in
1920 * an active state we must hold an RPM wakelock reference acquired via one of
1921 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1922 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1923 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1924 * users should avoid using this function.
1926 * Any calls to this function must have a symmetric call to
1927 * enable_rpm_wakeref_asserts().
1930 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1932 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1936 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1937 * @dev_priv: i915 device instance
1939 * This function re-enables the RPM assert checks after disabling them with
1940 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1941 * circumstances otherwise its use should be avoided.
1943 * Any calls to this function must have a symmetric call to
1944 * disable_rpm_wakeref_asserts().
1947 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1949 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1952 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1953 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1954 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1955 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1957 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1959 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1960 bool override, unsigned int mask);
1961 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1962 enum dpio_channel ch, bool override);
1966 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1967 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1968 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1969 void intel_update_watermarks(struct intel_crtc *crtc);
1970 void intel_init_pm(struct drm_i915_private *dev_priv);
1971 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1972 void intel_pm_setup(struct drm_i915_private *dev_priv);
1973 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1974 void intel_gpu_ips_teardown(void);
1975 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1976 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1977 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1978 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1979 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1980 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1981 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1982 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1983 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1984 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1985 struct intel_rps_client *rps);
1986 void g4x_wm_get_hw_state(struct drm_device *dev);
1987 void vlv_wm_get_hw_state(struct drm_device *dev);
1988 void ilk_wm_get_hw_state(struct drm_device *dev);
1989 void skl_wm_get_hw_state(struct drm_device *dev);
1990 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1991 struct skl_ddb_allocation *ddb /* out */);
1992 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1993 struct skl_pipe_wm *out);
1994 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1995 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1996 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1997 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1998 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1999 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2000 const struct skl_wm_level *l2);
2001 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2002 const struct skl_ddb_entry **entries,
2003 const struct skl_ddb_entry *ddb,
2005 bool ilk_disable_lp_wm(struct drm_device *dev);
2006 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2007 struct intel_crtc_state *cstate);
2008 void intel_init_ipc(struct drm_i915_private *dev_priv);
2009 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2012 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2013 i915_reg_t reg, enum port port);
2016 /* intel_sprite.c */
2017 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2019 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2020 enum pipe pipe, int plane);
2021 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
2022 struct drm_file *file_priv);
2023 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2024 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2025 void skl_update_plane(struct intel_plane *plane,
2026 const struct intel_crtc_state *crtc_state,
2027 const struct intel_plane_state *plane_state);
2028 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2029 bool skl_plane_get_hw_state(struct intel_plane *plane);
2030 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2031 enum pipe pipe, enum plane_id plane_id);
2034 void intel_tv_init(struct drm_i915_private *dev_priv);
2036 /* intel_atomic.c */
2037 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2038 const struct drm_connector_state *state,
2039 struct drm_property *property,
2041 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2042 struct drm_connector_state *state,
2043 struct drm_property *property,
2045 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2046 struct drm_connector_state *new_state);
2047 struct drm_connector_state *
2048 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2050 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2051 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2052 struct drm_crtc_state *state);
2053 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2054 void intel_atomic_state_clear(struct drm_atomic_state *);
2056 static inline struct intel_crtc_state *
2057 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2058 struct intel_crtc *crtc)
2060 struct drm_crtc_state *crtc_state;
2061 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2062 if (IS_ERR(crtc_state))
2063 return ERR_CAST(crtc_state);
2065 return to_intel_crtc_state(crtc_state);
2068 static inline struct intel_crtc_state *
2069 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
2070 struct intel_crtc *crtc)
2072 struct drm_crtc_state *crtc_state;
2074 crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
2077 return to_intel_crtc_state(crtc_state);
2082 static inline struct intel_plane_state *
2083 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
2084 struct intel_plane *plane)
2086 struct drm_plane_state *plane_state;
2088 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
2090 return to_intel_plane_state(plane_state);
2093 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2094 struct intel_crtc *intel_crtc,
2095 struct intel_crtc_state *crtc_state);
2097 /* intel_atomic_plane.c */
2098 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2099 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2100 void intel_plane_destroy_state(struct drm_plane *plane,
2101 struct drm_plane_state *state);
2102 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2103 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2104 struct intel_crtc_state *crtc_state,
2105 const struct intel_plane_state *old_plane_state,
2106 struct intel_plane_state *intel_state);
2109 void intel_color_init(struct drm_crtc *crtc);
2110 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2111 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2112 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2114 /* intel_lspcon.c */
2115 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2116 void lspcon_resume(struct intel_lspcon *lspcon);
2117 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2119 /* intel_pipe_crc.c */
2120 int intel_pipe_crc_create(struct drm_minor *minor);
2121 #ifdef CONFIG_DEBUG_FS
2122 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2123 size_t *values_cnt);
2125 #define intel_crtc_set_crc_source NULL
2127 extern const struct file_operations i915_display_crc_ctl_fops;
2128 #endif /* __INTEL_DRV_H__ */