2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
41 * _wait_for - magic (register) wait macro
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
52 if (time_after(jiffies, timeout__)) { \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
75 * Display related stuff
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
82 /* maximum connectors per crtcs in the mode set */
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
131 struct intel_encoder {
132 struct drm_encoder base;
134 enum intel_output_type type;
135 unsigned int cloneable;
136 void (*hot_plug)(struct intel_encoder *);
137 bool (*compute_config)(struct intel_encoder *,
138 struct intel_crtc_state *);
139 void (*pre_pll_enable)(struct intel_encoder *);
140 void (*pre_enable)(struct intel_encoder *);
141 void (*enable)(struct intel_encoder *);
142 void (*mode_set)(struct intel_encoder *intel_encoder);
143 void (*disable)(struct intel_encoder *);
144 void (*post_disable)(struct intel_encoder *);
145 void (*post_pll_disable)(struct intel_encoder *);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_state *pipe_config);
157 * Called during system suspend after all pending requests for the
158 * encoder are flushed (for example for DP AUX transactions) and
159 * device interrupts are disabled.
161 void (*suspend)(struct intel_encoder *);
163 enum hpd_pin hpd_pin;
167 struct drm_display_mode *fixed_mode;
168 struct drm_display_mode *downclock_mode;
178 bool combination_mode; /* gen 2/4 only */
182 struct pwm_device *pwm;
184 struct backlight_device *device;
187 void (*backlight_power)(struct intel_connector *, bool enable);
190 struct intel_connector {
191 struct drm_connector base;
193 * The fixed encoder this connector is connected to.
195 struct intel_encoder *encoder;
197 /* Reads out the current hw, returning true if the connector is enabled
198 * and active (i.e. dpms ON state). */
199 bool (*get_hw_state)(struct intel_connector *);
202 * Removes all interfaces through which the connector is accessible
203 * - like sysfs, debugfs entries -, so that no new operations can be
204 * started on the connector. Also makes sure all currently pending
205 * operations finish before returing.
207 void (*unregister)(struct intel_connector *);
209 /* Panel info for eDP and LVDS */
210 struct intel_panel panel;
212 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
214 struct edid *detect_edid;
216 /* since POLL and HPD connectors may use the same HPD line keep the native
217 state of connector->polled in case hotplug storm detection changes it */
220 void *port; /* store this opaque as its illegal to dereference it */
222 struct intel_dp *mst_port;
225 typedef struct dpll {
237 struct intel_atomic_state {
238 struct drm_atomic_state base;
242 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
245 struct intel_plane_state {
246 struct drm_plane_state base;
249 struct drm_rect clip;
254 * = -1 : not using a scaler
255 * >= 0 : using a scalers
257 * plane requiring a scaler:
258 * - During check_plane, its bit is set in
259 * crtc_state->scaler_state.scaler_users by calling helper function
260 * update_scaler_plane.
261 * - scaler_id indicates the scaler it got assigned.
263 * plane doesn't require a scaler:
264 * - this can happen when scaling is no more required or plane simply
266 * - During check_plane, corresponding bit is reset in
267 * crtc_state->scaler_state.scaler_users by calling helper function
268 * update_scaler_plane.
272 struct drm_intel_sprite_colorkey ckey;
275 struct intel_initial_plane_config {
276 struct intel_framebuffer *fb;
282 #define SKL_MIN_SRC_W 8
283 #define SKL_MAX_SRC_W 4096
284 #define SKL_MIN_SRC_H 8
285 #define SKL_MAX_SRC_H 4096
286 #define SKL_MIN_DST_W 8
287 #define SKL_MAX_DST_W 4096
288 #define SKL_MIN_DST_H 8
289 #define SKL_MAX_DST_H 4096
291 struct intel_scaler {
296 struct intel_crtc_scaler_state {
297 #define SKL_NUM_SCALERS 2
298 struct intel_scaler scalers[SKL_NUM_SCALERS];
301 * scaler_users: keeps track of users requesting scalers on this crtc.
303 * If a bit is set, a user is using a scaler.
304 * Here user can be a plane or crtc as defined below:
305 * bits 0-30 - plane (bit position is index from drm_plane_index)
308 * Instead of creating a new index to cover planes and crtc, using
309 * existing drm_plane_index for planes which is well less than 31
310 * planes and bit 31 for crtc. This should be fine to cover all
313 * intel_atomic_setup_scalers will setup available scalers to users
314 * requesting scalers. It will gracefully fail if request exceeds
317 #define SKL_CRTC_INDEX 31
318 unsigned scaler_users;
320 /* scaler used by crtc for panel fitting purpose */
324 /* drm_mode->private_flags */
325 #define I915_MODE_FLAG_INHERITED 1
327 struct intel_crtc_state {
328 struct drm_crtc_state base;
331 * quirks - bitfield with hw state readout quirks
333 * For various reasons the hw state readout code might not be able to
334 * completely faithfully read out the current state. These cases are
335 * tracked with quirk flags so that fastboot and state checker can act
338 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
339 unsigned long quirks;
341 /* Pipe source size (ie. panel fitter input size)
342 * All planes will be positioned inside this space,
343 * and get clipped at the edges. */
344 int pipe_src_w, pipe_src_h;
346 /* Whether to set up the PCH/FDI. Note that we never allow sharing
347 * between pch encoders and cpu encoders. */
348 bool has_pch_encoder;
350 /* Are we sending infoframes on the attached port */
353 /* CPU Transcoder for the pipe. Currently this can only differ from the
354 * pipe on Haswell (where we have a special eDP transcoder). */
355 enum transcoder cpu_transcoder;
358 * Use reduced/limited/broadcast rbg range, compressing from the full
359 * range fed into the crtcs.
361 bool limited_color_range;
363 /* DP has a bunch of special case unfortunately, so mark the pipe
367 /* Whether we should send NULL infoframes. Required for audio. */
370 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
371 * has_dp_encoder is set. */
375 * Enable dithering, used when the selected pipe bpp doesn't match the
380 /* Controls for the clock computation, to override various stages. */
383 /* SDVO TV has a bunch of special case. To make multifunction encoders
384 * work correctly, we need to track this at runtime.*/
388 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
389 * required. This is set in the 2nd loop of calling encoder's
390 * ->compute_config if the first pick doesn't work out.
394 /* Settings for the intel dpll used on pretty much everything but
398 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
399 enum intel_dpll_id shared_dpll;
402 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
403 * - enum skl_dpll on SKL
405 uint32_t ddi_pll_sel;
407 /* Actual register state of the dpll, for shared dpll cross-checking. */
408 struct intel_dpll_hw_state dpll_hw_state;
411 struct intel_link_m_n dp_m_n;
413 /* m2_n2 for eDP downclock */
414 struct intel_link_m_n dp_m2_n2;
418 * Frequence the dpll for the port should run at. Differs from the
419 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
420 * already multiplied by pixel_multiplier.
424 /* Used by SDVO (and if we ever fix it, HDMI). */
425 unsigned pixel_multiplier;
429 /* Panel fitter controls for gen2-gen4 + VLV */
433 u32 lvds_border_bits;
436 /* Panel fitter placement and size for Ironlake+ */
444 /* FDI configuration, only valid if has_pch_encoder is set. */
446 struct intel_link_m_n fdi_m_n;
452 bool dp_encoder_is_mst;
455 struct intel_crtc_scaler_state scaler_state;
457 /* w/a for waiting 2 vblanks during crtc enable */
458 enum pipe hsw_workaround_pipe;
461 struct vlv_wm_state {
462 struct vlv_pipe_wm wm[3];
463 struct vlv_sr_wm sr[3];
464 uint8_t num_active_planes;
470 struct intel_pipe_wm {
471 struct intel_wm_level wm[5];
475 bool sprites_enabled;
479 struct intel_mmio_flip {
480 struct work_struct work;
481 struct drm_i915_private *i915;
482 struct drm_i915_gem_request *req;
483 struct intel_crtc *crtc;
487 struct skl_wm_level wm[8];
488 struct skl_wm_level trans_wm;
493 * Tracking of operations that need to be performed at the beginning/end of an
494 * atomic commit, outside the atomic section where interrupts are disabled.
495 * These are generally operations that grab mutexes or might otherwise sleep
496 * and thus can't be run with interrupts disabled.
498 struct intel_crtc_atomic_commit {
499 /* Sleepable operations to perform before commit */
504 bool pre_disable_primary;
505 bool update_wm_pre, update_wm_post;
506 unsigned disabled_planes;
508 /* Sleepable operations to perform after commit */
512 bool post_enable_primary;
513 unsigned update_sprite_watermarks;
517 struct drm_crtc base;
520 u8 lut_r[256], lut_g[256], lut_b[256];
522 * Whether the crtc and the connected output pipeline is active. Implies
523 * that crtc->enabled is set, i.e. the current mode configuration has
524 * some outputs connected to this crtc.
527 unsigned long enabled_power_domains;
529 struct intel_overlay *overlay;
530 struct intel_unpin_work *unpin_work;
532 atomic_t unpin_work_count;
534 /* Display surface base address adjustement for pageflips. Note that on
535 * gen4+ this only adjusts up to a tile, offsets within a tile are
536 * handled in the hw itself (with the TILEOFF register). */
537 unsigned long dspaddr_offset;
539 struct drm_i915_gem_object *cursor_bo;
540 uint32_t cursor_addr;
541 uint32_t cursor_cntl;
542 uint32_t cursor_size;
543 uint32_t cursor_base;
545 struct intel_crtc_state *config;
547 /* reset counter value when the last flip was submitted */
548 unsigned int reset_counter;
550 /* Access to these should be protected by dev_priv->irq_lock. */
551 bool cpu_fifo_underrun_disabled;
552 bool pch_fifo_underrun_disabled;
554 /* per-pipe watermark state */
556 /* watermarks currently being used */
557 struct intel_pipe_wm active;
558 /* SKL wm values currently in use */
559 struct skl_pipe_wm skl_active;
560 /* allow CxSR on this pipe */
566 unsigned start_vbl_count;
567 ktime_t start_vbl_time;
569 struct intel_crtc_atomic_commit atomic;
571 /* scalers available on this crtc */
574 struct vlv_wm_state wm_state;
577 struct intel_plane_wm_parameters {
578 uint32_t horiz_pixels;
579 uint32_t vert_pixels;
581 * For packed pixel formats:
582 * bytes_per_pixel - holds bytes per pixel
583 * For planar pixel formats:
584 * bytes_per_pixel - holds bytes per pixel for uv-plane
585 * y_bytes_per_pixel - holds bytes per pixel for y-plane
587 uint8_t bytes_per_pixel;
588 uint8_t y_bytes_per_pixel;
592 unsigned int rotation;
597 struct drm_plane base;
602 uint32_t frontbuffer_bit;
604 /* Since we need to change the watermarks before/after
605 * enabling/disabling the planes, we need to store the parameters here
606 * as the other pieces of the struct may not reflect the values we want
607 * for the watermark calculations. Currently only Haswell uses this.
609 struct intel_plane_wm_parameters wm;
612 * NOTE: Do not place new plane state fields here (e.g., when adding
613 * new plane properties). New runtime state should now be placed in
614 * the intel_plane_state structure and accessed via drm_plane->state.
617 void (*update_plane)(struct drm_plane *plane,
618 struct drm_crtc *crtc,
619 struct drm_framebuffer *fb,
620 int crtc_x, int crtc_y,
621 unsigned int crtc_w, unsigned int crtc_h,
622 uint32_t x, uint32_t y,
623 uint32_t src_w, uint32_t src_h);
624 void (*disable_plane)(struct drm_plane *plane,
625 struct drm_crtc *crtc);
626 int (*check_plane)(struct drm_plane *plane,
627 struct intel_crtc_state *crtc_state,
628 struct intel_plane_state *state);
629 void (*commit_plane)(struct drm_plane *plane,
630 struct intel_plane_state *state);
633 struct intel_watermark_params {
634 unsigned long fifo_size;
635 unsigned long max_wm;
636 unsigned long default_wm;
637 unsigned long guard_size;
638 unsigned long cacheline_size;
641 struct cxsr_latency {
644 unsigned long fsb_freq;
645 unsigned long mem_freq;
646 unsigned long display_sr;
647 unsigned long display_hpll_disable;
648 unsigned long cursor_sr;
649 unsigned long cursor_hpll_disable;
652 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
653 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
654 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
655 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
656 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
657 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
658 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
659 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
660 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
665 bool limited_color_range;
666 bool color_range_auto;
669 enum hdmi_force_audio force_audio;
670 bool rgb_quant_range_selectable;
671 enum hdmi_picture_aspect aspect_ratio;
672 void (*write_infoframe)(struct drm_encoder *encoder,
673 enum hdmi_infoframe_type type,
674 const void *frame, ssize_t len);
675 void (*set_infoframes)(struct drm_encoder *encoder,
677 struct drm_display_mode *adjusted_mode);
678 bool (*infoframe_enabled)(struct drm_encoder *encoder);
681 struct intel_dp_mst_encoder;
682 #define DP_MAX_DOWNSTREAM_PORTS 0x10
686 * When platform provides two set of M_N registers for dp, we can
687 * program them and switch between them incase of DRRS.
688 * But When only one such register is provided, we have to program the
689 * required divider value on that registers itself based on the DRRS state.
691 * M1_N1 : Program dp_m_n on M1_N1 registers
692 * dp_m2_n2 on M2_N2 registers (If supported)
694 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
695 * M2_N2 registers are not supported
699 /* Sets the m1_n1 and m2_n2 */
712 uint32_t aux_ch_ctl_reg;
717 enum hdmi_force_audio force_audio;
718 bool limited_color_range;
719 bool color_range_auto;
720 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
721 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
722 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
723 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
724 uint8_t num_sink_rates;
725 int sink_rates[DP_MAX_SUPPORTED_RATES];
726 struct sink_crc sink_crc;
727 struct drm_dp_aux aux;
728 uint8_t train_set[4];
729 int panel_power_up_delay;
730 int panel_power_down_delay;
731 int panel_power_cycle_delay;
732 int backlight_on_delay;
733 int backlight_off_delay;
734 struct delayed_work panel_vdd_work;
736 unsigned long last_power_cycle;
737 unsigned long last_power_on;
738 unsigned long last_backlight_off;
740 struct notifier_block edp_notifier;
743 * Pipe whose power sequencer is currently locked into
744 * this port. Only relevant on VLV/CHV.
747 struct edp_power_seq pps_delays;
750 bool can_mst; /* this port supports mst */
752 int active_mst_links;
753 /* connector directly attached - won't be use for modeset in mst world */
754 struct intel_connector *attached_connector;
756 /* mst connector list */
757 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
758 struct drm_dp_mst_topology_mgr mst_mgr;
760 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
762 * This function returns the value we have to program the AUX_CTL
763 * register with to kick off an AUX transaction.
765 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
768 uint32_t aux_clock_divider);
769 bool train_set_valid;
771 /* Displayport compliance testing */
772 unsigned long compliance_test_type;
773 unsigned long compliance_test_data;
774 bool compliance_test_active;
777 struct intel_digital_port {
778 struct intel_encoder base;
782 struct intel_hdmi hdmi;
783 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
784 bool release_cl2_override;
787 struct intel_dp_mst_encoder {
788 struct intel_encoder base;
790 struct intel_digital_port *primary;
791 void *port; /* store this opaque as its illegal to dereference it */
794 static inline enum dpio_channel
795 vlv_dport_to_channel(struct intel_digital_port *dport)
797 switch (dport->port) {
808 static inline enum dpio_phy
809 vlv_dport_to_phy(struct intel_digital_port *dport)
811 switch (dport->port) {
822 static inline enum dpio_channel
823 vlv_pipe_to_channel(enum pipe pipe)
836 static inline struct drm_crtc *
837 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 return dev_priv->pipe_to_crtc_mapping[pipe];
843 static inline struct drm_crtc *
844 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 return dev_priv->plane_to_crtc_mapping[plane];
850 struct intel_unpin_work {
851 struct work_struct work;
852 struct drm_crtc *crtc;
853 struct drm_framebuffer *old_fb;
854 struct drm_i915_gem_object *pending_flip_obj;
855 struct drm_pending_vblank_event *event;
857 #define INTEL_FLIP_INACTIVE 0
858 #define INTEL_FLIP_PENDING 1
859 #define INTEL_FLIP_COMPLETE 2
862 struct drm_i915_gem_request *flip_queued_req;
863 int flip_queued_vblank;
864 int flip_ready_vblank;
865 bool enable_stall_check;
868 struct intel_load_detect_pipe {
869 struct drm_framebuffer *release_fb;
870 bool load_detect_temp;
874 static inline struct intel_encoder *
875 intel_attached_encoder(struct drm_connector *connector)
877 return to_intel_connector(connector)->encoder;
880 static inline struct intel_digital_port *
881 enc_to_dig_port(struct drm_encoder *encoder)
883 return container_of(encoder, struct intel_digital_port, base.base);
886 static inline struct intel_dp_mst_encoder *
887 enc_to_mst(struct drm_encoder *encoder)
889 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
892 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
894 return &enc_to_dig_port(encoder)->dp;
897 static inline struct intel_digital_port *
898 dp_to_dig_port(struct intel_dp *intel_dp)
900 return container_of(intel_dp, struct intel_digital_port, dp);
903 static inline struct intel_digital_port *
904 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
906 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
910 * Returns the number of planes for this pipe, ie the number of sprites + 1
911 * (primary plane). This doesn't count the cursor plane then.
913 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
915 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
918 /* intel_fifo_underrun.c */
919 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool enable);
921 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
922 enum transcoder pch_transcoder,
924 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
926 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
927 enum transcoder pch_transcoder);
928 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
931 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
932 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
933 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
934 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
935 void gen6_reset_rps_interrupts(struct drm_device *dev);
936 void gen6_enable_rps_interrupts(struct drm_device *dev);
937 void gen6_disable_rps_interrupts(struct drm_device *dev);
938 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
939 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
940 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
941 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
944 * We only use drm_irq_uninstall() at unload and VT switch, so
945 * this is the only thing we need to check.
947 return dev_priv->pm.irqs_enabled;
950 int intel_get_crtc_scanline(struct intel_crtc *crtc);
951 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
952 unsigned int pipe_mask);
955 void intel_crt_init(struct drm_device *dev);
959 void intel_prepare_ddi(struct drm_device *dev);
960 void hsw_fdi_link_train(struct drm_crtc *crtc);
961 void intel_ddi_init(struct drm_device *dev, enum port port);
962 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
963 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
964 void intel_ddi_pll_init(struct drm_device *dev);
965 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
966 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
967 enum transcoder cpu_transcoder);
968 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
969 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
970 bool intel_ddi_pll_select(struct intel_crtc *crtc,
971 struct intel_crtc_state *crtc_state);
972 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
973 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
974 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
975 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
976 void intel_ddi_get_config(struct intel_encoder *encoder,
977 struct intel_crtc_state *pipe_config);
978 struct intel_encoder *
979 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
981 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
982 void intel_ddi_clock_get(struct intel_encoder *encoder,
983 struct intel_crtc_state *pipe_config);
984 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
985 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
987 /* intel_frontbuffer.c */
988 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
989 enum fb_op_origin origin);
990 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
991 unsigned frontbuffer_bits);
992 void intel_frontbuffer_flip_complete(struct drm_device *dev,
993 unsigned frontbuffer_bits);
994 void intel_frontbuffer_flip(struct drm_device *dev,
995 unsigned frontbuffer_bits);
996 unsigned int intel_fb_align_height(struct drm_device *dev,
998 uint32_t pixel_format,
999 uint64_t fb_format_modifier);
1000 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1001 enum fb_op_origin origin);
1002 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1003 uint32_t pixel_format);
1006 void intel_init_audio(struct drm_device *dev);
1007 void intel_audio_codec_enable(struct intel_encoder *encoder);
1008 void intel_audio_codec_disable(struct intel_encoder *encoder);
1009 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1010 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1012 /* intel_display.c */
1013 extern const struct drm_plane_funcs intel_plane_funcs;
1014 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1015 int intel_pch_rawclk(struct drm_device *dev);
1016 int intel_hrawclk(struct drm_device *dev);
1017 void intel_mark_busy(struct drm_device *dev);
1018 void intel_mark_idle(struct drm_device *dev);
1019 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1020 int intel_display_suspend(struct drm_device *dev);
1021 void intel_encoder_destroy(struct drm_encoder *encoder);
1022 int intel_connector_init(struct intel_connector *);
1023 struct intel_connector *intel_connector_alloc(void);
1024 bool intel_connector_get_hw_state(struct intel_connector *connector);
1025 void intel_connector_attach_encoder(struct intel_connector *connector,
1026 struct intel_encoder *encoder);
1027 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1028 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1029 struct drm_crtc *crtc);
1030 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1031 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1032 struct drm_file *file_priv);
1033 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1035 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1037 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1039 drm_wait_one_vblank(dev, pipe);
1041 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1042 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1043 struct intel_digital_port *dport,
1044 unsigned int expected_mask);
1045 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1046 struct drm_display_mode *mode,
1047 struct intel_load_detect_pipe *old,
1048 struct drm_modeset_acquire_ctx *ctx);
1049 void intel_release_load_detect_pipe(struct drm_connector *connector,
1050 struct intel_load_detect_pipe *old,
1051 struct drm_modeset_acquire_ctx *ctx);
1052 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1053 struct drm_framebuffer *fb,
1054 const struct drm_plane_state *plane_state,
1055 struct intel_engine_cs *pipelined,
1056 struct drm_i915_gem_request **pipelined_request);
1057 struct drm_framebuffer *
1058 __intel_framebuffer_create(struct drm_device *dev,
1059 struct drm_mode_fb_cmd2 *mode_cmd,
1060 struct drm_i915_gem_object *obj);
1061 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1062 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1063 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1064 void intel_check_page_flip(struct drm_device *dev, int pipe);
1065 int intel_prepare_plane_fb(struct drm_plane *plane,
1066 struct drm_framebuffer *fb,
1067 const struct drm_plane_state *new_state);
1068 void intel_cleanup_plane_fb(struct drm_plane *plane,
1069 struct drm_framebuffer *fb,
1070 const struct drm_plane_state *old_state);
1071 int intel_plane_atomic_get_property(struct drm_plane *plane,
1072 const struct drm_plane_state *state,
1073 struct drm_property *property,
1075 int intel_plane_atomic_set_property(struct drm_plane *plane,
1076 struct drm_plane_state *state,
1077 struct drm_property *property,
1079 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1080 struct drm_plane_state *plane_state);
1083 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1084 uint64_t fb_format_modifier);
1087 intel_rotation_90_or_270(unsigned int rotation)
1089 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1092 void intel_create_rotation_property(struct drm_device *dev,
1093 struct intel_plane *plane);
1095 /* shared dpll functions */
1096 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1097 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1098 struct intel_shared_dpll *pll,
1100 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1101 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1102 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1103 struct intel_crtc_state *state);
1105 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1106 const struct dpll *dpll);
1107 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1109 /* modesetting asserts */
1110 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1112 void assert_pll(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state);
1114 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1115 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1116 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state);
1118 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1119 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1120 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1121 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1122 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1123 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1125 unsigned int tiling_mode,
1127 unsigned int pitch);
1128 void intel_prepare_reset(struct drm_device *dev);
1129 void intel_finish_reset(struct drm_device *dev);
1130 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1131 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1132 void broxton_init_cdclk(struct drm_device *dev);
1133 void broxton_uninit_cdclk(struct drm_device *dev);
1134 void broxton_ddi_phy_init(struct drm_device *dev);
1135 void broxton_ddi_phy_uninit(struct drm_device *dev);
1136 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1137 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1138 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1139 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1140 void intel_dp_get_m_n(struct intel_crtc *crtc,
1141 struct intel_crtc_state *pipe_config);
1142 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1143 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1145 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1147 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1148 intel_clock_t *best_clock);
1149 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1151 bool intel_crtc_active(struct drm_crtc *crtc);
1152 void hsw_enable_ips(struct intel_crtc *crtc);
1153 void hsw_disable_ips(struct intel_crtc *crtc);
1154 enum intel_display_power_domain
1155 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1156 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1157 struct intel_crtc_state *pipe_config);
1158 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1159 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1161 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1162 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1164 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1165 struct drm_i915_gem_object *obj);
1166 u32 skl_plane_ctl_format(uint32_t pixel_format);
1167 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1168 u32 skl_plane_ctl_rotation(unsigned int rotation);
1171 void intel_csr_ucode_init(struct drm_device *dev);
1172 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1173 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1174 enum csr_state state);
1175 void intel_csr_load_program(struct drm_device *dev);
1176 void intel_csr_ucode_fini(struct drm_device *dev);
1177 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1180 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1181 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1182 struct intel_connector *intel_connector);
1183 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1184 const struct intel_crtc_state *pipe_config);
1185 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1186 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1187 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1188 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1189 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1190 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1191 bool intel_dp_compute_config(struct intel_encoder *encoder,
1192 struct intel_crtc_state *pipe_config);
1193 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1194 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1196 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1197 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1198 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1199 void intel_edp_panel_on(struct intel_dp *intel_dp);
1200 void intel_edp_panel_off(struct intel_dp *intel_dp);
1201 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1202 void intel_dp_mst_suspend(struct drm_device *dev);
1203 void intel_dp_mst_resume(struct drm_device *dev);
1204 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1205 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1206 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1207 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1208 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1209 void intel_plane_destroy(struct drm_plane *plane);
1210 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1211 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1212 void intel_edp_drrs_invalidate(struct drm_device *dev,
1213 unsigned frontbuffer_bits);
1214 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1215 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1217 /* intel_dp_mst.c */
1218 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1219 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1221 void intel_dsi_init(struct drm_device *dev);
1225 void intel_dvo_init(struct drm_device *dev);
1228 /* legacy fbdev emulation in intel_fbdev.c */
1229 #ifdef CONFIG_DRM_FBDEV_EMULATION
1230 extern int intel_fbdev_init(struct drm_device *dev);
1231 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1232 extern void intel_fbdev_fini(struct drm_device *dev);
1233 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1234 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1235 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1237 static inline int intel_fbdev_init(struct drm_device *dev)
1242 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1246 static inline void intel_fbdev_fini(struct drm_device *dev)
1250 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1254 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1260 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1261 void intel_fbc_update(struct drm_i915_private *dev_priv);
1262 void intel_fbc_init(struct drm_i915_private *dev_priv);
1263 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1264 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1265 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1266 unsigned int frontbuffer_bits,
1267 enum fb_op_origin origin);
1268 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1269 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1270 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1271 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1274 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1275 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1276 struct intel_connector *intel_connector);
1277 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1278 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1279 struct intel_crtc_state *pipe_config);
1283 void intel_lvds_init(struct drm_device *dev);
1284 bool intel_is_dual_link_lvds(struct drm_device *dev);
1288 int intel_connector_update_modes(struct drm_connector *connector,
1290 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1291 void intel_attach_force_audio_property(struct drm_connector *connector);
1292 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1295 /* intel_overlay.c */
1296 void intel_setup_overlay(struct drm_device *dev);
1297 void intel_cleanup_overlay(struct drm_device *dev);
1298 int intel_overlay_switch_off(struct intel_overlay *overlay);
1299 int intel_overlay_put_image(struct drm_device *dev, void *data,
1300 struct drm_file *file_priv);
1301 int intel_overlay_attrs(struct drm_device *dev, void *data,
1302 struct drm_file *file_priv);
1303 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1307 int intel_panel_init(struct intel_panel *panel,
1308 struct drm_display_mode *fixed_mode,
1309 struct drm_display_mode *downclock_mode);
1310 void intel_panel_fini(struct intel_panel *panel);
1311 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1312 struct drm_display_mode *adjusted_mode);
1313 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1314 struct intel_crtc_state *pipe_config,
1316 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1317 struct intel_crtc_state *pipe_config,
1319 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1320 u32 level, u32 max);
1321 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1322 void intel_panel_enable_backlight(struct intel_connector *connector);
1323 void intel_panel_disable_backlight(struct intel_connector *connector);
1324 void intel_panel_destroy_backlight(struct drm_connector *connector);
1325 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1326 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1327 extern struct drm_display_mode *intel_find_panel_downclock(
1328 struct drm_device *dev,
1329 struct drm_display_mode *fixed_mode,
1330 struct drm_connector *connector);
1331 void intel_backlight_register(struct drm_device *dev);
1332 void intel_backlight_unregister(struct drm_device *dev);
1336 void intel_psr_enable(struct intel_dp *intel_dp);
1337 void intel_psr_disable(struct intel_dp *intel_dp);
1338 void intel_psr_invalidate(struct drm_device *dev,
1339 unsigned frontbuffer_bits);
1340 void intel_psr_flush(struct drm_device *dev,
1341 unsigned frontbuffer_bits,
1342 enum fb_op_origin origin);
1343 void intel_psr_init(struct drm_device *dev);
1344 void intel_psr_single_frame_update(struct drm_device *dev,
1345 unsigned frontbuffer_bits);
1347 /* intel_runtime_pm.c */
1348 int intel_power_domains_init(struct drm_i915_private *);
1349 void intel_power_domains_fini(struct drm_i915_private *);
1350 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1351 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1353 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1354 enum intel_display_power_domain domain);
1355 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1356 enum intel_display_power_domain domain);
1357 void intel_display_power_get(struct drm_i915_private *dev_priv,
1358 enum intel_display_power_domain domain);
1359 void intel_display_power_put(struct drm_i915_private *dev_priv,
1360 enum intel_display_power_domain domain);
1361 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1362 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1363 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1364 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1365 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1367 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1369 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1370 bool override, unsigned int mask);
1371 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1372 enum dpio_channel ch, bool override);
1376 void intel_init_clock_gating(struct drm_device *dev);
1377 void intel_suspend_hw(struct drm_device *dev);
1378 int ilk_wm_max_level(const struct drm_device *dev);
1379 void intel_update_watermarks(struct drm_crtc *crtc);
1380 void intel_update_sprite_watermarks(struct drm_plane *plane,
1381 struct drm_crtc *crtc,
1382 uint32_t sprite_width,
1383 uint32_t sprite_height,
1385 bool enabled, bool scaled);
1386 void intel_init_pm(struct drm_device *dev);
1387 void intel_pm_setup(struct drm_device *dev);
1388 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1389 void intel_gpu_ips_teardown(void);
1390 void intel_init_gt_powersave(struct drm_device *dev);
1391 void intel_cleanup_gt_powersave(struct drm_device *dev);
1392 void intel_enable_gt_powersave(struct drm_device *dev);
1393 void intel_disable_gt_powersave(struct drm_device *dev);
1394 void intel_suspend_gt_powersave(struct drm_device *dev);
1395 void intel_reset_gt_powersave(struct drm_device *dev);
1396 void gen6_update_ring_freq(struct drm_device *dev);
1397 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1398 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1399 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1400 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1401 struct intel_rps_client *rps,
1402 unsigned long submitted);
1403 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1404 struct drm_i915_gem_request *req);
1405 void vlv_wm_get_hw_state(struct drm_device *dev);
1406 void ilk_wm_get_hw_state(struct drm_device *dev);
1407 void skl_wm_get_hw_state(struct drm_device *dev);
1408 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1409 struct skl_ddb_allocation *ddb /* out */);
1410 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1413 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1416 /* intel_sprite.c */
1417 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1418 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1419 struct drm_file *file_priv);
1420 void intel_pipe_update_start(struct intel_crtc *crtc);
1421 void intel_pipe_update_end(struct intel_crtc *crtc);
1424 void intel_tv_init(struct drm_device *dev);
1426 /* intel_atomic.c */
1427 int intel_connector_atomic_get_property(struct drm_connector *connector,
1428 const struct drm_connector_state *state,
1429 struct drm_property *property,
1431 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1432 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1433 struct drm_crtc_state *state);
1434 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1435 void intel_atomic_state_clear(struct drm_atomic_state *);
1436 struct intel_shared_dpll_config *
1437 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1439 static inline struct intel_crtc_state *
1440 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1441 struct intel_crtc *crtc)
1443 struct drm_crtc_state *crtc_state;
1444 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1445 if (IS_ERR(crtc_state))
1446 return ERR_CAST(crtc_state);
1448 return to_intel_crtc_state(crtc_state);
1450 int intel_atomic_setup_scalers(struct drm_device *dev,
1451 struct intel_crtc *intel_crtc,
1452 struct intel_crtc_state *crtc_state);
1454 /* intel_atomic_plane.c */
1455 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1456 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1457 void intel_plane_destroy_state(struct drm_plane *plane,
1458 struct drm_plane_state *state);
1459 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1461 #endif /* __INTEL_DRV_H__ */