2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/sched/clock.h>
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_dp_dual_mode_helper.h>
35 #include <drm/drm_dp_mst_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_rect.h>
40 #include <drm/drm_vblank.h>
41 #include <drm/i915_drm.h>
42 #include <drm/i915_mei_hdcp_interface.h>
43 #include <media/cec-notifier.h>
50 * Display related stuff
53 /* these are outputs from the chip - integrated only
54 external chips are via DVO or SDVO output */
55 enum intel_output_type {
56 INTEL_OUTPUT_UNUSED = 0,
57 INTEL_OUTPUT_ANALOG = 1,
59 INTEL_OUTPUT_SDVO = 3,
60 INTEL_OUTPUT_LVDS = 4,
61 INTEL_OUTPUT_TVOUT = 5,
62 INTEL_OUTPUT_HDMI = 6,
66 INTEL_OUTPUT_DDI = 10,
67 INTEL_OUTPUT_DP_MST = 11,
70 struct intel_framebuffer {
71 struct drm_framebuffer base;
72 struct intel_rotation_info rot_info;
74 /* for each plane in the normal GTT view */
78 /* for each plane in the rotated GTT view */
81 unsigned int pitch; /* pixels */
86 struct drm_fb_helper helper;
87 struct intel_framebuffer *fb;
89 unsigned long vma_flags;
90 async_cookie_t cookie;
93 /* Whether or not fbdev hpd processing is temporarily suspended */
94 bool hpd_suspended : 1;
95 /* Set when a hotplug was received while HPD processing was
100 /* Protects hpd_suspended */
101 struct mutex hpd_lock;
104 struct intel_encoder {
105 struct drm_encoder base;
107 enum intel_output_type type;
109 unsigned int cloneable;
110 bool (*hotplug)(struct intel_encoder *encoder,
111 struct intel_connector *connector);
112 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
113 struct intel_crtc_state *,
114 struct drm_connector_state *);
115 int (*compute_config)(struct intel_encoder *,
116 struct intel_crtc_state *,
117 struct drm_connector_state *);
118 void (*pre_pll_enable)(struct intel_encoder *,
119 const struct intel_crtc_state *,
120 const struct drm_connector_state *);
121 void (*pre_enable)(struct intel_encoder *,
122 const struct intel_crtc_state *,
123 const struct drm_connector_state *);
124 void (*enable)(struct intel_encoder *,
125 const struct intel_crtc_state *,
126 const struct drm_connector_state *);
127 void (*disable)(struct intel_encoder *,
128 const struct intel_crtc_state *,
129 const struct drm_connector_state *);
130 void (*post_disable)(struct intel_encoder *,
131 const struct intel_crtc_state *,
132 const struct drm_connector_state *);
133 void (*post_pll_disable)(struct intel_encoder *,
134 const struct intel_crtc_state *,
135 const struct drm_connector_state *);
136 void (*update_pipe)(struct intel_encoder *,
137 const struct intel_crtc_state *,
138 const struct drm_connector_state *);
139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
143 /* Reconstructs the equivalent mode flags for the current hardware
144 * state. This must be called _after_ display->get_pipe_config has
145 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
146 * be set correctly before calling this function. */
147 void (*get_config)(struct intel_encoder *,
148 struct intel_crtc_state *pipe_config);
150 * Acquires the power domains needed for an active encoder during
151 * hardware state readout.
153 void (*get_power_domains)(struct intel_encoder *encoder,
154 struct intel_crtc_state *crtc_state);
156 * Called during system suspend after all pending requests for the
157 * encoder are flushed (for example for DP AUX transactions) and
158 * device interrupts are disabled.
160 void (*suspend)(struct intel_encoder *);
162 enum hpd_pin hpd_pin;
163 enum intel_display_power_domain power_domain;
164 /* for communication with audio component; protected by av_mutex */
165 const struct drm_connector *audio_connector;
169 struct drm_display_mode *fixed_mode;
170 struct drm_display_mode *downclock_mode;
179 bool combination_mode; /* gen 2/4 only */
181 bool alternate_pwm_increment; /* lpt+ */
184 bool util_pin_active_low; /* bxt+ */
185 u8 controller; /* bxt+ only */
186 struct pwm_device *pwm;
188 struct backlight_device *device;
190 /* Connector and platform specific backlight functions */
191 int (*setup)(struct intel_connector *connector, enum pipe pipe);
192 u32 (*get)(struct intel_connector *connector);
193 void (*set)(const struct drm_connector_state *conn_state, u32 level);
194 void (*disable)(const struct drm_connector_state *conn_state);
195 void (*enable)(const struct intel_crtc_state *crtc_state,
196 const struct drm_connector_state *conn_state);
197 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
198 void (*power)(struct intel_connector *, bool enable);
202 struct intel_digital_port;
204 enum check_link_response {
205 HDCP_LINK_PROTECTED = 0,
206 HDCP_TOPOLOGY_CHANGE,
207 HDCP_LINK_INTEGRITY_FAILURE,
212 * This structure serves as a translation layer between the generic HDCP code
213 * and the bus-specific code. What that means is that HDCP over HDMI differs
214 * from HDCP over DP, so to account for these differences, we need to
215 * communicate with the receiver through this shim.
217 * For completeness, the 2 buses differ in the following ways:
219 * HDCP registers on the receiver are set via DP AUX for DP, and
220 * they are set via DDC for HDMI.
221 * - Receiver register offsets
222 * The offsets of the registers are different for DP vs. HDMI
223 * - Receiver register masks/offsets
224 * For instance, the ready bit for the KSV fifo is in a different
225 * place on DP vs HDMI
226 * - Receiver register names
227 * Seriously. In the DP spec, the 16-bit register containing
228 * downstream information is called BINFO, on HDMI it's called
229 * BSTATUS. To confuse matters further, DP has a BSTATUS register
230 * with a completely different definition.
232 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
233 * be read 3 keys at a time
235 * Since Aksv is hidden in hardware, there's different procedures
236 * to send it over DP AUX vs DDC
238 struct intel_hdcp_shim {
239 /* Outputs the transmitter's An and Aksv values to the receiver. */
240 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
242 /* Reads the receiver's key selection vector */
243 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
246 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
247 * definitions are the same in the respective specs, but the names are
248 * different. Call it BSTATUS since that's the name the HDMI spec
249 * uses and it was there first.
251 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
254 /* Determines whether a repeater is present downstream */
255 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
256 bool *repeater_present);
258 /* Reads the receiver's Ri' value */
259 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
261 /* Determines if the receiver's KSV FIFO is ready for consumption */
262 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
265 /* Reads the ksv fifo for num_downstream devices */
266 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
267 int num_downstream, u8 *ksv_fifo);
269 /* Reads a 32-bit part of V' from the receiver */
270 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
273 /* Enables HDCP signalling on the port */
274 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
277 /* Ensures the link is still protected */
278 bool (*check_link)(struct intel_digital_port *intel_dig_port);
280 /* Detects panel's hdcp capability. This is optional for HDMI. */
281 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
284 /* HDCP adaptation(DP/HDMI) required on the port */
285 enum hdcp_wired_protocol protocol;
287 /* Detects whether sink is HDCP2.2 capable */
288 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
291 /* Write HDCP2.2 messages */
292 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
293 void *buf, size_t size);
295 /* Read HDCP2.2 messages */
296 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
297 u8 msg_id, void *buf, size_t size);
300 * Implementation of DP HDCP2.2 Errata for the communication of stream
301 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
302 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
304 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
305 bool is_repeater, u8 type);
307 /* HDCP2.2 Link Integrity Check */
308 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
312 const struct intel_hdcp_shim *shim;
313 /* Mutex for hdcp state of the connector */
316 struct delayed_work check_work;
317 struct work_struct prop_work;
319 /* HDCP1.4 Encryption status */
322 /* HDCP2.2 related definitions */
323 /* Flag indicates whether this connector supports HDCP2.2 or not. */
324 bool hdcp2_supported;
326 /* HDCP2.2 Encryption status */
327 bool hdcp2_encrypted;
330 * Content Stream Type defined by content owner. TYPE0(0x0) content can
331 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
332 * content can flow only through a link protected by HDCP2.2.
335 struct hdcp_port_data port_data;
341 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
342 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
343 * When it rolls over re-auth has to be triggered.
348 * Count of RepeaterAuth_Stream_Manage msg propagated.
349 * Initialized to 0 on AKE_INIT. Incremented after every successful
350 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
351 * over re-Auth has to be triggered.
356 * Work queue to signal the CP_IRQ. Used for the waiters to read the
357 * available information from HDCP DP sink.
359 wait_queue_head_t cp_irq_queue;
360 atomic_t cp_irq_count;
361 int cp_irq_count_cached;
364 struct intel_connector {
365 struct drm_connector base;
367 * The fixed encoder this connector is connected to.
369 struct intel_encoder *encoder;
371 /* ACPI device id for ACPI and driver cooperation */
374 /* Reads out the current hw, returning true if the connector is enabled
375 * and active (i.e. dpms ON state). */
376 bool (*get_hw_state)(struct intel_connector *);
378 /* Panel info for eDP and LVDS */
379 struct intel_panel panel;
381 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
383 struct edid *detect_edid;
385 /* since POLL and HPD connectors may use the same HPD line keep the native
386 state of connector->polled in case hotplug storm detection changes it */
389 void *port; /* store this opaque as its illegal to dereference it */
391 struct intel_dp *mst_port;
393 /* Work struct to schedule a uevent on link train failure */
394 struct work_struct modeset_retry_work;
396 struct intel_hdcp hdcp;
399 struct intel_digital_connector_state {
400 struct drm_connector_state base;
402 enum hdmi_force_audio force_audio;
406 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
420 struct intel_atomic_state {
421 struct drm_atomic_state base;
423 intel_wakeref_t wakeref;
427 * Logical state of cdclk (used for all scaling, watermark,
428 * etc. calculations and checks). This is computed as if all
429 * enabled crtcs were active.
431 struct intel_cdclk_state logical;
434 * Actual state of cdclk, can be different from the logical
435 * state only when all crtc's are DPMS off.
437 struct intel_cdclk_state actual;
440 bool force_min_cdclk_changed;
441 /* pipe to which cd2x update is synchronized */
445 bool dpll_set, modeset;
448 * Does this transaction change the pipes that are active? This mask
449 * tracks which CRTC's have changed their active state at the end of
450 * the transaction (not counting the temporary disable during modesets).
451 * This mask should only be non-zero when intel_state->modeset is true,
452 * but the converse is not necessarily true; simply changing a mode may
453 * not flip the final active status of any CRTC's
455 unsigned int active_pipe_changes;
457 unsigned int active_crtcs;
458 /* minimum acceptable cdclk for each pipe */
459 int min_cdclk[I915_MAX_PIPES];
460 /* minimum acceptable voltage level for each pipe */
461 u8 min_voltage_level[I915_MAX_PIPES];
463 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
466 * Current watermarks can't be trusted during hardware readout, so
467 * don't bother calculating intermediate watermarks.
469 bool skip_intermediate_wm;
471 bool rps_interactive;
474 struct skl_ddb_values wm_results;
476 struct i915_sw_fence commit_ready;
478 struct llist_node freed;
481 struct intel_plane_state {
482 struct drm_plane_state base;
483 struct i915_ggtt_view view;
484 struct i915_vma *vma;
486 #define PLANE_HAS_FENCE BIT(0)
492 * bytes for 0/180 degree rotation
493 * pixels for 90/270 degree rotation
499 /* plane control register */
502 /* plane color control register */
507 * = -1 : not using a scaler
508 * >= 0 : using a scalers
510 * plane requiring a scaler:
511 * - During check_plane, its bit is set in
512 * crtc_state->scaler_state.scaler_users by calling helper function
513 * update_scaler_plane.
514 * - scaler_id indicates the scaler it got assigned.
516 * plane doesn't require a scaler:
517 * - this can happen when scaling is no more required or plane simply
519 * - During check_plane, corresponding bit is reset in
520 * crtc_state->scaler_state.scaler_users by calling helper function
521 * update_scaler_plane.
528 * ICL planar formats require 2 planes that are updated as pairs.
529 * This member is used to make sure the other plane is also updated
530 * when required, and for update_slave() to find the correct
531 * plane_state to pass as argument.
533 struct intel_plane *linked_plane;
537 * If set don't update use the linked plane's state for updating
538 * this plane during atomic commit with the update_slave() callback.
540 * It's also used by the watermark code to ignore wm calculations on
541 * this plane. They're calculated by the linked plane's wm code.
545 struct drm_intel_sprite_colorkey ckey;
548 struct intel_initial_plane_config {
549 struct intel_framebuffer *fb;
556 struct intel_scaler {
561 struct intel_crtc_scaler_state {
562 #define SKL_NUM_SCALERS 2
563 struct intel_scaler scalers[SKL_NUM_SCALERS];
566 * scaler_users: keeps track of users requesting scalers on this crtc.
568 * If a bit is set, a user is using a scaler.
569 * Here user can be a plane or crtc as defined below:
570 * bits 0-30 - plane (bit position is index from drm_plane_index)
573 * Instead of creating a new index to cover planes and crtc, using
574 * existing drm_plane_index for planes which is well less than 31
575 * planes and bit 31 for crtc. This should be fine to cover all
578 * intel_atomic_setup_scalers will setup available scalers to users
579 * requesting scalers. It will gracefully fail if request exceeds
582 #define SKL_CRTC_INDEX 31
583 unsigned scaler_users;
585 /* scaler used by crtc for panel fitting purpose */
589 /* drm_mode->private_flags */
590 #define I915_MODE_FLAG_INHERITED (1<<0)
591 /* Flag to get scanline using frame time stamps */
592 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
593 /* Flag to use the scanline counter instead of the pixel counter */
594 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
596 struct intel_pipe_wm {
597 struct intel_wm_level wm[5];
601 bool sprites_enabled;
605 struct skl_plane_wm {
606 struct skl_wm_level wm[8];
607 struct skl_wm_level uv_wm[8];
608 struct skl_wm_level trans_wm;
613 struct skl_plane_wm planes[I915_MAX_PLANES];
620 VLV_WM_LEVEL_DDR_DVFS,
624 struct vlv_wm_state {
625 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
626 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
631 struct vlv_fifo_state {
632 u16 plane[I915_MAX_PLANES];
642 struct g4x_wm_state {
643 struct g4x_pipe_wm wm;
645 struct g4x_sr_wm hpll;
651 struct intel_crtc_wm_state {
655 * Intermediate watermarks; these can be
656 * programmed immediately since they satisfy
657 * both the current configuration we're
658 * switching away from and the new
659 * configuration we're switching to.
661 struct intel_pipe_wm intermediate;
664 * Optimal watermarks, programmed post-vblank
665 * when this state is committed.
667 struct intel_pipe_wm optimal;
671 /* gen9+ only needs 1-step wm programming */
672 struct skl_pipe_wm optimal;
673 struct skl_ddb_entry ddb;
674 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
675 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
679 /* "raw" watermarks (not inverted) */
680 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
681 /* intermediate watermarks (inverted) */
682 struct vlv_wm_state intermediate;
683 /* optimal watermarks (inverted) */
684 struct vlv_wm_state optimal;
685 /* display FIFO split */
686 struct vlv_fifo_state fifo_state;
690 /* "raw" watermarks */
691 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
692 /* intermediate watermarks */
693 struct g4x_wm_state intermediate;
694 /* optimal watermarks */
695 struct g4x_wm_state optimal;
700 * Platforms with two-step watermark programming will need to
701 * update watermark programming post-vblank to switch from the
702 * safe intermediate watermarks to the optimal final
705 bool need_postvbl_update;
708 enum intel_output_format {
709 INTEL_OUTPUT_FORMAT_INVALID,
710 INTEL_OUTPUT_FORMAT_RGB,
711 INTEL_OUTPUT_FORMAT_YCBCR420,
712 INTEL_OUTPUT_FORMAT_YCBCR444,
715 struct intel_crtc_state {
716 struct drm_crtc_state base;
719 * quirks - bitfield with hw state readout quirks
721 * For various reasons the hw state readout code might not be able to
722 * completely faithfully read out the current state. These cases are
723 * tracked with quirk flags so that fastboot and state checker can act
726 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
727 unsigned long quirks;
729 unsigned fb_bits; /* framebuffers to flip */
730 bool update_pipe; /* can a fast modeset be performed? */
732 bool update_wm_pre, update_wm_post; /* watermarks are updated */
733 bool fb_changed; /* fb on any of the planes is changed */
734 bool fifo_changed; /* FIFO split is changed */
736 /* Pipe source size (ie. panel fitter input size)
737 * All planes will be positioned inside this space,
738 * and get clipped at the edges. */
739 int pipe_src_w, pipe_src_h;
742 * Pipe pixel rate, adjusted for
743 * panel fitter/pipe scaler downscaling.
745 unsigned int pixel_rate;
747 /* Whether to set up the PCH/FDI. Note that we never allow sharing
748 * between pch encoders and cpu encoders. */
749 bool has_pch_encoder;
751 /* Are we sending infoframes on the attached port */
754 /* CPU Transcoder for the pipe. Currently this can only differ from the
755 * pipe on Haswell and later (where we have a special eDP transcoder)
756 * and Broxton (where we have special DSI transcoders). */
757 enum transcoder cpu_transcoder;
760 * Use reduced/limited/broadcast rbg range, compressing from the full
761 * range fed into the crtcs.
763 bool limited_color_range;
765 /* Bitmask of encoder types (enum intel_output_type)
766 * driven by the pipe.
768 unsigned int output_types;
770 /* Whether we should send NULL infoframes. Required for audio. */
773 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
774 * has_dp_encoder is set. */
778 * Enable dithering, used when the selected pipe bpp doesn't match the
784 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
785 * compliance video pattern tests.
786 * Disable dither only if it is a compliance test request for
789 bool dither_force_disable;
791 /* Controls for the clock computation, to override various stages. */
794 /* SDVO TV has a bunch of special case. To make multifunction encoders
795 * work correctly, we need to track this at runtime.*/
799 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
800 * required. This is set in the 2nd loop of calling encoder's
801 * ->compute_config if the first pick doesn't work out.
805 /* Settings for the intel dpll used on pretty much everything but
809 /* Selected dpll when shared or NULL. */
810 struct intel_shared_dpll *shared_dpll;
812 /* Actual register state of the dpll, for shared dpll cross-checking. */
813 struct intel_dpll_hw_state dpll_hw_state;
815 /* DSI PLL registers */
821 struct intel_link_m_n dp_m_n;
823 /* m2_n2 for eDP downclock */
824 struct intel_link_m_n dp_m2_n2;
831 * Frequence the dpll for the port should run at. Differs from the
832 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
833 * already multiplied by pixel_multiplier.
837 /* Used by SDVO (and if we ever fix it, HDMI). */
838 unsigned pixel_multiplier;
843 * Used by platforms having DP/HDMI PHY with programmable lane
844 * latency optimization.
846 u8 lane_lat_optim_mask;
848 /* minimum acceptable voltage level */
849 u8 min_voltage_level;
851 /* Panel fitter controls for gen2-gen4 + VLV */
855 u32 lvds_border_bits;
858 /* Panel fitter placement and size for Ironlake+ */
866 /* FDI configuration, only valid if has_pch_encoder is set. */
868 struct intel_link_m_n fdi_m_n;
880 struct intel_crtc_scaler_state scaler_state;
882 /* w/a for waiting 2 vblanks during crtc enable */
883 enum pipe hsw_workaround_pipe;
885 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
888 struct intel_crtc_wm_state wm;
890 u32 data_rate[I915_MAX_PLANES];
892 /* Gamma mode programmed on the pipe */
896 /* CSC mode programmed on the pipe */
903 /* bitmask of visible planes (enum plane_id) */
908 /* bitmask of planes that will be updated during the commit */
914 union hdmi_infoframe avi;
915 union hdmi_infoframe spd;
916 union hdmi_infoframe hdmi;
917 union hdmi_infoframe drm;
920 /* HDMI scrambling status */
921 bool hdmi_scrambling;
923 /* HDMI High TMDS char rate ratio */
924 bool hdmi_high_tmds_clock_ratio;
926 /* Output format RGB/YCBCR etc */
927 enum intel_output_format output_format;
929 /* Output down scaling is done in LSPCON device */
930 bool lspcon_downsampling;
932 /* enable pipe gamma? */
935 /* enable pipe csc? */
938 /* Display Stream compression state */
940 bool compression_enable;
945 struct drm_dsc_config dp_dsc_cfg;
947 /* Forward Error correction State */
952 struct drm_crtc base;
955 * Whether the crtc and the connected output pipeline is active. Implies
956 * that crtc->enabled is set, i.e. the current mode configuration has
957 * some outputs connected to this crtc.
961 unsigned long long enabled_power_domains;
962 struct intel_overlay *overlay;
964 struct intel_crtc_state *config;
966 /* Access to these should be protected by dev_priv->irq_lock. */
967 bool cpu_fifo_underrun_disabled;
968 bool pch_fifo_underrun_disabled;
970 /* per-pipe watermark state */
972 /* watermarks currently being used */
974 struct intel_pipe_wm ilk;
975 struct vlv_wm_state vlv;
976 struct g4x_wm_state g4x;
983 unsigned start_vbl_count;
984 ktime_t start_vbl_time;
985 int min_vbl, max_vbl;
989 /* scalers available on this crtc */
994 struct drm_plane base;
995 enum i9xx_plane_id i9xx_plane;
1000 u32 frontbuffer_bit;
1003 u32 base, cntl, size;
1007 * NOTE: Do not place new plane state fields here (e.g., when adding
1008 * new plane properties). New runtime state should now be placed in
1009 * the intel_plane_state structure and accessed via plane_state.
1012 unsigned int (*max_stride)(struct intel_plane *plane,
1013 u32 pixel_format, u64 modifier,
1014 unsigned int rotation);
1015 void (*update_plane)(struct intel_plane *plane,
1016 const struct intel_crtc_state *crtc_state,
1017 const struct intel_plane_state *plane_state);
1018 void (*update_slave)(struct intel_plane *plane,
1019 const struct intel_crtc_state *crtc_state,
1020 const struct intel_plane_state *plane_state);
1021 void (*disable_plane)(struct intel_plane *plane,
1022 const struct intel_crtc_state *crtc_state);
1023 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1024 int (*check_plane)(struct intel_crtc_state *crtc_state,
1025 struct intel_plane_state *plane_state);
1028 struct intel_watermark_params {
1036 struct cxsr_latency {
1037 bool is_desktop : 1;
1042 u16 display_hpll_disable;
1044 u16 cursor_hpll_disable;
1047 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1048 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1049 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1050 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1051 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1052 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1053 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1054 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1055 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1058 i915_reg_t hdmi_reg;
1061 enum drm_dp_dual_mode_type type;
1066 struct intel_connector *attached_connector;
1067 struct cec_notifier *cec_notifier;
1070 struct intel_dp_mst_encoder;
1071 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1074 * enum link_m_n_set:
1075 * When platform provides two set of M_N registers for dp, we can
1076 * program them and switch between them incase of DRRS.
1077 * But When only one such register is provided, we have to program the
1078 * required divider value on that registers itself based on the DRRS state.
1080 * M1_N1 : Program dp_m_n on M1_N1 registers
1081 * dp_m2_n2 on M2_N2 registers (If supported)
1083 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1084 * M2_N2 registers are not supported
1088 /* Sets the m1_n1 and m2_n2 */
1093 struct intel_dp_compliance_data {
1096 u16 hdisplay, vdisplay;
1100 struct intel_dp_compliance {
1101 unsigned long test_type;
1102 struct intel_dp_compliance_data test_data;
1109 i915_reg_t output_reg;
1117 bool reset_link_params;
1118 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1119 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1120 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1121 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1122 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1125 int num_source_rates;
1126 const int *source_rates;
1127 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1129 int sink_rates[DP_MAX_SUPPORTED_RATES];
1130 bool use_rate_select;
1131 /* intersection of source and sink rates */
1132 int num_common_rates;
1133 int common_rates[DP_MAX_SUPPORTED_RATES];
1134 /* Max lane count for the current link */
1135 int max_link_lane_count;
1136 /* Max rate for the current link */
1138 /* sink or branch descriptor */
1139 struct drm_dp_desc desc;
1140 struct drm_dp_aux aux;
1142 int panel_power_up_delay;
1143 int panel_power_down_delay;
1144 int panel_power_cycle_delay;
1145 int backlight_on_delay;
1146 int backlight_off_delay;
1147 struct delayed_work panel_vdd_work;
1148 bool want_panel_vdd;
1149 unsigned long last_power_on;
1150 unsigned long last_backlight_off;
1151 ktime_t panel_power_off_time;
1153 struct notifier_block edp_notifier;
1156 * Pipe whose power sequencer is currently locked into
1157 * this port. Only relevant on VLV/CHV.
1161 * Pipe currently driving the port. Used for preventing
1162 * the use of the PPS for any pipe currentrly driving
1163 * external DP as that will mess things up on VLV.
1165 enum pipe active_pipe;
1167 * Set if the sequencer may be reset due to a power transition,
1168 * requiring a reinitialization. Only relevant on BXT.
1171 struct edp_power_seq pps_delays;
1173 bool can_mst; /* this port supports mst */
1175 int active_mst_links;
1176 /* connector directly attached - won't be use for modeset in mst world */
1177 struct intel_connector *attached_connector;
1179 /* mst connector list */
1180 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1181 struct drm_dp_mst_topology_mgr mst_mgr;
1183 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1185 * This function returns the value we have to program the AUX_CTL
1186 * register with to kick off an AUX transaction.
1188 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1189 u32 aux_clock_divider);
1191 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1192 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1194 /* This is called before a link training is starterd */
1195 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1197 /* Displayport compliance testing */
1198 struct intel_dp_compliance compliance;
1200 /* Display stream compression testing */
1204 enum lspcon_vendor {
1206 LSPCON_VENDOR_PARADE
1209 struct intel_lspcon {
1211 enum drm_lspcon_mode mode;
1212 enum lspcon_vendor vendor;
1215 struct intel_digital_port {
1216 struct intel_encoder base;
1217 u32 saved_port_bits;
1219 struct intel_hdmi hdmi;
1220 struct intel_lspcon lspcon;
1221 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1222 bool release_cl2_override;
1224 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1226 enum intel_display_power_domain ddi_io_power_domain;
1227 bool tc_legacy_port:1;
1228 enum tc_port_type tc_type;
1230 void (*write_infoframe)(struct intel_encoder *encoder,
1231 const struct intel_crtc_state *crtc_state,
1233 const void *frame, ssize_t len);
1234 void (*read_infoframe)(struct intel_encoder *encoder,
1235 const struct intel_crtc_state *crtc_state,
1237 void *frame, ssize_t len);
1238 void (*set_infoframes)(struct intel_encoder *encoder,
1240 const struct intel_crtc_state *crtc_state,
1241 const struct drm_connector_state *conn_state);
1242 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1243 const struct intel_crtc_state *pipe_config);
1246 struct intel_dp_mst_encoder {
1247 struct intel_encoder base;
1249 struct intel_digital_port *primary;
1250 struct intel_connector *connector;
1253 static inline enum dpio_channel
1254 vlv_dport_to_channel(struct intel_digital_port *dport)
1256 switch (dport->base.port) {
1267 static inline enum dpio_phy
1268 vlv_dport_to_phy(struct intel_digital_port *dport)
1270 switch (dport->base.port) {
1281 static inline enum dpio_channel
1282 vlv_pipe_to_channel(enum pipe pipe)
1295 static inline struct intel_crtc *
1296 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1298 return dev_priv->pipe_to_crtc_mapping[pipe];
1301 static inline struct intel_crtc *
1302 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1304 return dev_priv->plane_to_crtc_mapping[plane];
1307 struct intel_load_detect_pipe {
1308 struct drm_atomic_state *restore_state;
1311 static inline struct intel_encoder *
1312 intel_attached_encoder(struct drm_connector *connector)
1314 return to_intel_connector(connector)->encoder;
1317 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1319 switch (encoder->type) {
1320 case INTEL_OUTPUT_DDI:
1321 case INTEL_OUTPUT_DP:
1322 case INTEL_OUTPUT_EDP:
1323 case INTEL_OUTPUT_HDMI:
1330 static inline struct intel_digital_port *
1331 enc_to_dig_port(struct drm_encoder *encoder)
1333 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1335 if (intel_encoder_is_dig_port(intel_encoder))
1336 return container_of(encoder, struct intel_digital_port,
1342 static inline struct intel_digital_port *
1343 conn_to_dig_port(struct intel_connector *connector)
1345 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1348 static inline struct intel_dp_mst_encoder *
1349 enc_to_mst(struct drm_encoder *encoder)
1351 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1354 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1356 return &enc_to_dig_port(encoder)->dp;
1359 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1361 switch (encoder->type) {
1362 case INTEL_OUTPUT_DP:
1363 case INTEL_OUTPUT_EDP:
1365 case INTEL_OUTPUT_DDI:
1366 /* Skip pure HDMI/DVI DDI encoders */
1367 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1373 static inline struct intel_lspcon *
1374 enc_to_intel_lspcon(struct drm_encoder *encoder)
1376 return &enc_to_dig_port(encoder)->lspcon;
1379 static inline struct intel_digital_port *
1380 dp_to_dig_port(struct intel_dp *intel_dp)
1382 return container_of(intel_dp, struct intel_digital_port, dp);
1385 static inline struct intel_lspcon *
1386 dp_to_lspcon(struct intel_dp *intel_dp)
1388 return &dp_to_dig_port(intel_dp)->lspcon;
1391 static inline struct drm_i915_private *
1392 dp_to_i915(struct intel_dp *intel_dp)
1394 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1397 static inline struct intel_digital_port *
1398 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1400 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1403 static inline struct intel_plane_state *
1404 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1405 struct intel_plane *plane)
1407 struct drm_plane_state *ret =
1408 drm_atomic_get_plane_state(&state->base, &plane->base);
1411 return ERR_CAST(ret);
1413 return to_intel_plane_state(ret);
1416 static inline struct intel_plane_state *
1417 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1418 struct intel_plane *plane)
1420 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1424 static inline struct intel_plane_state *
1425 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1426 struct intel_plane *plane)
1428 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1432 static inline struct intel_crtc_state *
1433 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1434 struct intel_crtc *crtc)
1436 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1440 static inline struct intel_crtc_state *
1441 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1442 struct intel_crtc *crtc)
1444 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1448 /* intel_display.c */
1449 void intel_plane_destroy(struct drm_plane *plane);
1450 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1451 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1452 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1453 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1454 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1455 const char *name, u32 reg, int ref_freq);
1456 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1457 const char *name, u32 reg);
1458 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1459 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1460 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1461 unsigned int intel_fb_xy_to_linear(int x, int y,
1462 const struct intel_plane_state *state,
1464 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1465 int color_plane, unsigned int height);
1466 void intel_add_fb_offsets(int *x, int *y,
1467 const struct intel_plane_state *state, int plane);
1468 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1469 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
1470 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1471 int intel_display_suspend(struct drm_device *dev);
1472 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1473 void intel_encoder_destroy(struct drm_encoder *encoder);
1474 struct drm_display_mode *
1475 intel_encoder_current_mode(struct intel_encoder *encoder);
1476 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1477 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1478 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1480 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *file_priv);
1482 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1485 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1486 enum intel_output_type type)
1488 return crtc_state->output_types & (1 << type);
1491 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1493 return crtc_state->output_types &
1494 ((1 << INTEL_OUTPUT_DP) |
1495 (1 << INTEL_OUTPUT_DP_MST) |
1496 (1 << INTEL_OUTPUT_EDP));
1499 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1501 drm_wait_one_vblank(&dev_priv->drm, pipe);
1504 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1506 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1509 intel_wait_for_vblank(dev_priv, pipe);
1512 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1514 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1515 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1516 struct intel_digital_port *dport,
1517 unsigned int expected_mask);
1518 int intel_get_load_detect_pipe(struct drm_connector *connector,
1519 const struct drm_display_mode *mode,
1520 struct intel_load_detect_pipe *old,
1521 struct drm_modeset_acquire_ctx *ctx);
1522 void intel_release_load_detect_pipe(struct drm_connector *connector,
1523 struct intel_load_detect_pipe *old,
1524 struct drm_modeset_acquire_ctx *ctx);
1526 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1527 const struct i915_ggtt_view *view,
1529 unsigned long *out_flags);
1530 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1531 struct drm_framebuffer *
1532 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1533 struct drm_mode_fb_cmd2 *mode_cmd);
1534 int intel_prepare_plane_fb(struct drm_plane *plane,
1535 struct drm_plane_state *new_state);
1536 void intel_cleanup_plane_fb(struct drm_plane *plane,
1537 struct drm_plane_state *old_state);
1539 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1542 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1543 const struct dpll *dpll);
1544 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1545 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1546 bool intel_fuzzy_clock_check(int clock1, int clock2);
1548 /* modesetting asserts */
1549 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1551 void assert_pll(struct drm_i915_private *dev_priv,
1552 enum pipe pipe, bool state);
1553 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1554 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1555 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1556 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1557 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1558 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1559 enum pipe pipe, bool state);
1560 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1561 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1562 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1563 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1564 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1565 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1566 void intel_finish_reset(struct drm_i915_private *dev_priv);
1567 void intel_dp_get_m_n(struct intel_crtc *crtc,
1568 struct intel_crtc_state *pipe_config);
1569 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1570 enum link_m_n_set m_n);
1571 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
1572 const struct intel_crtc_state *crtc_state);
1573 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1574 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1575 struct dpll *best_clock);
1576 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1578 bool intel_crtc_active(struct intel_crtc *crtc);
1579 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1580 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1581 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1582 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1583 enum intel_display_power_domain
1584 intel_aux_power_domain(struct intel_digital_port *dig_port);
1585 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1586 struct intel_crtc_state *pipe_config);
1587 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1588 struct intel_crtc_state *crtc_state);
1590 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1591 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1592 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1595 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1597 return i915_ggtt_offset(state->vma);
1600 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1601 const struct intel_plane_state *plane_state);
1602 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1603 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1604 const struct intel_plane_state *plane_state);
1605 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1606 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1608 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1609 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1610 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1611 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1612 u32 pixel_format, u64 modifier,
1613 unsigned int rotation);
1614 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
1616 #endif /* __INTEL_DRV_H__ */