2 * Copyright © 2008-2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "intel_drv.h"
27 intel_get_adjust_train(struct intel_dp *intel_dp,
28 const uint8_t link_status[DP_LINK_STATUS_SIZE])
36 for (lane = 0; lane < intel_dp->lane_count; lane++) {
37 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
38 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
46 voltage_max = intel_dp_voltage_max(intel_dp);
48 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
50 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
52 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
54 for (lane = 0; lane < 4; lane++)
55 intel_dp->train_set[lane] = v | p;
59 intel_dp_set_link_train(struct intel_dp *intel_dp,
62 uint8_t buf[sizeof(intel_dp->train_set) + 1];
65 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
67 buf[0] = dp_train_pat;
68 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
69 DP_TRAINING_PATTERN_DISABLE) {
70 /* don't write DP_TRAINING_LANEx_SET on disable */
73 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
74 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
75 len = intel_dp->lane_count + 1;
78 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
85 intel_dp_reset_link_train(struct intel_dp *intel_dp,
88 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
89 intel_dp_set_signal_levels(intel_dp);
90 return intel_dp_set_link_train(intel_dp, dp_train_pat);
94 intel_dp_update_link_train(struct intel_dp *intel_dp)
98 intel_dp_set_signal_levels(intel_dp);
100 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
101 intel_dp->train_set, intel_dp->lane_count);
103 return ret == intel_dp->lane_count;
106 /* Enable corresponding port and start training pattern 1 */
108 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
112 int voltage_tries, loop_tries;
113 uint8_t link_config[2];
114 uint8_t link_bw, rate_select;
116 if (intel_dp->prepare_link_retrain)
117 intel_dp->prepare_link_retrain(intel_dp);
119 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
120 &link_bw, &rate_select);
122 /* Write the link configuration data */
123 link_config[0] = link_bw;
124 link_config[1] = intel_dp->lane_count;
125 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
126 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
127 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
128 if (intel_dp->num_sink_rates)
129 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
133 link_config[1] = DP_SET_ANSI_8B10B;
134 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
136 intel_dp->DP |= DP_PORT_EN;
139 if (!intel_dp_reset_link_train(intel_dp,
140 DP_TRAINING_PATTERN_1 |
141 DP_LINK_SCRAMBLING_DISABLE)) {
142 DRM_ERROR("failed to enable link training\n");
150 uint8_t link_status[DP_LINK_STATUS_SIZE];
152 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
153 if (!intel_dp_get_link_status(intel_dp, link_status)) {
154 DRM_ERROR("failed to get link status\n");
158 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
159 DRM_DEBUG_KMS("clock recovery OK\n");
163 /* Check to see if we've tried the max voltage */
164 for (i = 0; i < intel_dp->lane_count; i++)
165 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
167 if (i == intel_dp->lane_count) {
169 if (loop_tries == 5) {
170 DRM_ERROR("too many full retries, give up\n");
173 intel_dp_reset_link_train(intel_dp,
174 DP_TRAINING_PATTERN_1 |
175 DP_LINK_SCRAMBLING_DISABLE);
180 /* Check to see if we've tried the same voltage 5 times */
181 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
183 if (voltage_tries == 5) {
184 DRM_ERROR("too many voltage retries, give up\n");
189 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
191 /* Update training set as requested by target */
192 intel_get_adjust_train(intel_dp, link_status);
193 if (!intel_dp_update_link_train(intel_dp)) {
194 DRM_ERROR("failed to update link training\n");
201 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
202 * or 1.2 devices that support it, Training Pattern 2 otherwise.
204 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
206 u32 training_pattern = DP_TRAINING_PATTERN_2;
207 bool source_tps3, sink_tps3;
210 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
211 * also mandatory for downstream devices that support HBR2. However, not
212 * all sinks follow the spec.
214 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
215 * supported in source but still not enabled.
217 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
218 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
220 if (source_tps3 && sink_tps3) {
221 training_pattern = DP_TRAINING_PATTERN_3;
222 } else if (intel_dp->link_rate == 540000) {
224 DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
226 DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
229 return training_pattern;
233 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
235 bool channel_eq = false;
237 u32 training_pattern;
239 training_pattern = intel_dp_training_pattern(intel_dp);
241 /* channel equalization */
242 if (!intel_dp_set_link_train(intel_dp,
244 DP_LINK_SCRAMBLING_DISABLE)) {
245 DRM_ERROR("failed to start channel equalization\n");
253 uint8_t link_status[DP_LINK_STATUS_SIZE];
256 DRM_ERROR("failed to train DP, aborting\n");
260 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
261 if (!intel_dp_get_link_status(intel_dp, link_status)) {
262 DRM_ERROR("failed to get link status\n");
266 /* Make sure clock is still ok */
267 if (!drm_dp_clock_recovery_ok(link_status,
268 intel_dp->lane_count)) {
269 intel_dp_link_training_clock_recovery(intel_dp);
270 intel_dp_set_link_train(intel_dp,
272 DP_LINK_SCRAMBLING_DISABLE);
277 if (drm_dp_channel_eq_ok(link_status,
278 intel_dp->lane_count)) {
283 /* Try 5 times, then try clock recovery if that fails */
285 intel_dp_link_training_clock_recovery(intel_dp);
286 intel_dp_set_link_train(intel_dp,
288 DP_LINK_SCRAMBLING_DISABLE);
294 /* Update training set as requested by target */
295 intel_get_adjust_train(intel_dp, link_status);
296 if (!intel_dp_update_link_train(intel_dp)) {
297 DRM_ERROR("failed to update link training\n");
303 intel_dp_set_idle_link_train(intel_dp);
306 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
309 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
311 intel_dp_set_link_train(intel_dp,
312 DP_TRAINING_PATTERN_DISABLE);
316 intel_dp_start_link_train(struct intel_dp *intel_dp)
318 intel_dp_link_training_clock_recovery(intel_dp);
319 intel_dp_link_training_channel_equalization(intel_dp);