2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
71 static const struct dp_link_dpll chv_dpll[] = {
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
92 static bool is_edp(struct intel_dp *intel_dp)
94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
103 return intel_dig_port->base.base.dev;
106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 static void intel_dp_link_down(struct intel_dp *intel_dp);
112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
130 max_link_bw = DP_LINK_BW_2_7;
133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw = DP_LINK_BW_1_62;
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
147 * 270000 * 1 * 8 / 10 == 216000
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
159 intel_dp_link_required(int pixel_clock, int bpp)
161 return (pixel_clock * bpp + 9) / 10;
165 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
167 return (max_link_clock * max_lanes * 8) / 10;
170 static enum drm_mode_status
171 intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
174 struct intel_dp *intel_dp = intel_attached_dp(connector);
175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
184 if (mode->vdisplay > fixed_mode->vdisplay)
187 target_clock = fixed_mode->clock;
190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
196 if (mode_rate > max_rate)
197 return MODE_CLOCK_HIGH;
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
209 pack_aux(uint8_t *src, int src_bytes)
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
222 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
231 /* hrawclock is 1/4 the FSB frequency */
233 intel_hrawclk(struct drm_device *dev)
235 struct drm_i915_private *dev_priv = dev->dev_private;
238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
252 case CLKCFG_FSB_1067:
254 case CLKCFG_FSB_1333:
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
266 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
270 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
275 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
284 /* modeset should have pipe */
286 return to_intel_crtc(crtc)->pipe;
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
302 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
312 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
322 static bool edp_have_panel_power(struct intel_dp *intel_dp)
324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
330 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
333 struct drm_i915_private *dev_priv = dev->dev_private;
334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
344 intel_dp_check_edp(struct intel_dp *intel_dp)
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
349 if (!is_edp(intel_dp))
352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
361 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
370 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
373 msecs_to_jiffies_timeout(10));
375 done = wait_for_atomic(C, 10) == 0;
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
384 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
393 return index ? 0 : intel_hrawclk(dev) / 2;
396 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
408 return 225; /* eDP input clock at 450Mhz */
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
414 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
420 if (intel_dig_port->port == PORT_A) {
423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
436 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
438 return index ? 0 : 100;
441 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
444 uint32_t aux_clock_divider)
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
460 return DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
465 DP_AUX_CH_CTL_RECEIVE_ERROR |
466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
472 intel_dp_aux_ch(struct intel_dp *intel_dp,
473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
480 uint32_t ch_data = ch_ctl + 4;
481 uint32_t aux_clock_divider;
482 int i, ret, recv_bytes;
485 bool has_aux_irq = HAS_AUX_IRQ(dev);
488 vdd = _edp_panel_vdd_on(intel_dp);
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
496 intel_dp_check_edp(intel_dp);
498 intel_aux_display_runtime_get(dev_priv);
500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
502 status = I915_READ_NOTRACE(ch_ctl);
503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
534 /* Send the command and wait for it to complete */
535 I915_WRITE(ch_ctl, send_ctl);
537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
539 /* Clear done status and any errors */
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
549 if (status & DP_AUX_CH_CTL_DONE)
552 if (status & DP_AUX_CH_CTL_DONE)
556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
592 intel_aux_display_runtime_put(dev_priv);
595 edp_panel_vdd_off(intel_dp, false);
600 #define BARE_ADDRESS_SIZE 3
601 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
603 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
621 if (WARN_ON(txsize > 20))
624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
628 msg->reply = rxbuf[0] >> 4;
630 /* Return payload size. */
635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
638 rxsize = msg->size + 1;
640 if (WARN_ON(rxsize > 20))
643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
645 msg->reply = rxbuf[0] >> 4;
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
650 * Return payload size.
653 memcpy(msg->buffer, rxbuf + 1, ret);
666 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
671 const char *name = NULL;
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
698 intel_dp->aux.name = name;
699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
722 intel_dp_connector_unregister(struct intel_connector *intel_connector)
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
727 intel_dp->aux.ddc.dev.kobj.name);
728 intel_connector_unregister(intel_connector);
732 intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
735 struct drm_device *dev = encoder->base.dev;
736 const struct dp_link_dpll *divisor = NULL;
741 count = ARRAY_SIZE(gen4_dpll);
742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
746 count = ARRAY_SIZE(pch_dpll);
747 } else if (IS_CHERRYVIEW(dev)) {
749 count = ARRAY_SIZE(chv_dpll);
750 } else if (IS_VALLEYVIEW(dev)) {
752 count = ARRAY_SIZE(vlv_dpll);
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
767 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
781 intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
784 struct drm_device *dev = encoder->base.dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
788 enum port port = dp_to_dig_port(intel_dp)->port;
789 struct intel_crtc *intel_crtc = encoder->new_crtc;
790 struct intel_connector *intel_connector = intel_dp->attached_connector;
791 int lane_count, clock;
792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
797 int link_avail, link_clock;
799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
800 pipe_config->has_pch_encoder = true;
802 pipe_config->has_dp_encoder = true;
804 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
805 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
807 if (!HAS_PCH_SPLIT(dev))
808 intel_gmch_panel_fitting(intel_crtc, pipe_config,
809 intel_connector->panel.fitting_mode);
811 intel_pch_panel_fitting(intel_crtc, pipe_config,
812 intel_connector->panel.fitting_mode);
815 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
818 DRM_DEBUG_KMS("DP link computation with max lane count %i "
819 "max bw %02x pixel clock %iKHz\n",
820 max_lane_count, bws[max_clock],
821 adjusted_mode->crtc_clock);
823 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
825 bpp = pipe_config->pipe_bpp;
826 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
827 dev_priv->vbt.edp_bpp < bpp) {
828 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
829 dev_priv->vbt.edp_bpp);
830 bpp = dev_priv->vbt.edp_bpp;
833 for (; bpp >= 6*3; bpp -= 2*3) {
834 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
837 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
838 for (clock = 0; clock <= max_clock; clock++) {
839 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
840 link_avail = intel_dp_max_data_rate(link_clock,
843 if (mode_rate <= link_avail) {
853 if (intel_dp->color_range_auto) {
856 * CEA-861-E - 5.1 Default Encoding Parameters
857 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
859 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
860 intel_dp->color_range = DP_COLOR_RANGE_16_235;
862 intel_dp->color_range = 0;
865 if (intel_dp->color_range)
866 pipe_config->limited_color_range = true;
868 intel_dp->link_bw = bws[clock];
869 intel_dp->lane_count = lane_count;
870 pipe_config->pipe_bpp = bpp;
871 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
873 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
874 intel_dp->link_bw, intel_dp->lane_count,
875 pipe_config->port_clock, bpp);
876 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
877 mode_rate, link_avail);
879 intel_link_compute_m_n(bpp, lane_count,
880 adjusted_mode->crtc_clock,
881 pipe_config->port_clock,
882 &pipe_config->dp_m_n);
884 if (intel_connector->panel.downclock_mode != NULL &&
885 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
886 intel_link_compute_m_n(bpp, lane_count,
887 intel_connector->panel.downclock_mode->clock,
888 pipe_config->port_clock,
889 &pipe_config->dp_m2_n2);
892 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
897 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
899 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
900 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
901 struct drm_device *dev = crtc->base.dev;
902 struct drm_i915_private *dev_priv = dev->dev_private;
905 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
906 dpa_ctl = I915_READ(DP_A);
907 dpa_ctl &= ~DP_PLL_FREQ_MASK;
909 if (crtc->config.port_clock == 162000) {
910 /* For a long time we've carried around a ILK-DevA w/a for the
911 * 160MHz clock. If we're really unlucky, it's still required.
913 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
914 dpa_ctl |= DP_PLL_FREQ_160MHZ;
915 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
917 dpa_ctl |= DP_PLL_FREQ_270MHZ;
918 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
921 I915_WRITE(DP_A, dpa_ctl);
927 static void intel_dp_mode_set(struct intel_encoder *encoder)
929 struct drm_device *dev = encoder->base.dev;
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
932 enum port port = dp_to_dig_port(intel_dp)->port;
933 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
934 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
937 * There are four kinds of DP registers:
944 * IBX PCH and CPU are the same for almost everything,
945 * except that the CPU DP PLL is configured in this
948 * CPT PCH is quite different, having many bits moved
949 * to the TRANS_DP_CTL register instead. That
950 * configuration happens (oddly) in ironlake_pch_enable
953 /* Preserve the BIOS-computed detected bit. This is
954 * supposed to be read-only.
956 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
958 /* Handle DP bits in common between all three register formats */
959 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
960 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
962 if (intel_dp->has_audio) {
963 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
964 pipe_name(crtc->pipe));
965 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
966 intel_write_eld(&encoder->base, adjusted_mode);
969 /* Split out the IBX/CPU vs CPT settings */
971 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
978 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
979 intel_dp->DP |= DP_ENHANCED_FRAMING;
981 intel_dp->DP |= crtc->pipe << 29;
982 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
983 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
984 intel_dp->DP |= intel_dp->color_range;
986 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
987 intel_dp->DP |= DP_SYNC_HS_HIGH;
988 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
989 intel_dp->DP |= DP_SYNC_VS_HIGH;
990 intel_dp->DP |= DP_LINK_TRAIN_OFF;
992 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
993 intel_dp->DP |= DP_ENHANCED_FRAMING;
996 intel_dp->DP |= DP_PIPEB_SELECT;
998 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1001 if (port == PORT_A && !IS_VALLEYVIEW(dev))
1002 ironlake_set_pll_cpu_edp(intel_dp);
1005 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1006 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1008 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1009 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1011 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1014 static void wait_panel_status(struct intel_dp *intel_dp,
1018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020 u32 pp_stat_reg, pp_ctrl_reg;
1022 pp_stat_reg = _pp_stat_reg(intel_dp);
1023 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1025 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1027 I915_READ(pp_stat_reg),
1028 I915_READ(pp_ctrl_reg));
1030 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1031 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1032 I915_READ(pp_stat_reg),
1033 I915_READ(pp_ctrl_reg));
1036 DRM_DEBUG_KMS("Wait complete\n");
1039 static void wait_panel_on(struct intel_dp *intel_dp)
1041 DRM_DEBUG_KMS("Wait for panel power on\n");
1042 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1045 static void wait_panel_off(struct intel_dp *intel_dp)
1047 DRM_DEBUG_KMS("Wait for panel power off time\n");
1048 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1051 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1053 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1055 /* When we disable the VDD override bit last we have to do the manual
1057 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1058 intel_dp->panel_power_cycle_delay);
1060 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1063 static void wait_backlight_on(struct intel_dp *intel_dp)
1065 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1066 intel_dp->backlight_on_delay);
1069 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1071 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1072 intel_dp->backlight_off_delay);
1075 /* Read the current pp_control value, unlocking the register if it
1079 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1081 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1085 control = I915_READ(_pp_ctrl_reg(intel_dp));
1086 control &= ~PANEL_UNLOCK_MASK;
1087 control |= PANEL_UNLOCK_REGS;
1091 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1093 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1095 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 enum intel_display_power_domain power_domain;
1099 u32 pp_stat_reg, pp_ctrl_reg;
1100 bool need_to_disable = !intel_dp->want_panel_vdd;
1102 if (!is_edp(intel_dp))
1105 intel_dp->want_panel_vdd = true;
1107 if (edp_have_panel_vdd(intel_dp))
1108 return need_to_disable;
1110 power_domain = intel_display_port_power_domain(intel_encoder);
1111 intel_display_power_get(dev_priv, power_domain);
1113 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1115 if (!edp_have_panel_power(intel_dp))
1116 wait_panel_power_cycle(intel_dp);
1118 pp = ironlake_get_pp_control(intel_dp);
1119 pp |= EDP_FORCE_VDD;
1121 pp_stat_reg = _pp_stat_reg(intel_dp);
1122 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1124 I915_WRITE(pp_ctrl_reg, pp);
1125 POSTING_READ(pp_ctrl_reg);
1126 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1127 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1129 * If the panel wasn't on, delay before accessing aux channel
1131 if (!edp_have_panel_power(intel_dp)) {
1132 DRM_DEBUG_KMS("eDP was not running\n");
1133 msleep(intel_dp->panel_power_up_delay);
1136 return need_to_disable;
1139 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1141 if (is_edp(intel_dp)) {
1142 bool vdd = _edp_panel_vdd_on(intel_dp);
1144 WARN(!vdd, "eDP VDD already requested on\n");
1148 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1153 u32 pp_stat_reg, pp_ctrl_reg;
1155 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1157 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1158 struct intel_digital_port *intel_dig_port =
1159 dp_to_dig_port(intel_dp);
1160 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1161 enum intel_display_power_domain power_domain;
1163 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1165 pp = ironlake_get_pp_control(intel_dp);
1166 pp &= ~EDP_FORCE_VDD;
1168 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1169 pp_stat_reg = _pp_stat_reg(intel_dp);
1171 I915_WRITE(pp_ctrl_reg, pp);
1172 POSTING_READ(pp_ctrl_reg);
1174 /* Make sure sequencer is idle before allowing subsequent activity */
1175 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1176 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1178 if ((pp & POWER_TARGET_ON) == 0)
1179 intel_dp->last_power_cycle = jiffies;
1181 power_domain = intel_display_port_power_domain(intel_encoder);
1182 intel_display_power_put(dev_priv, power_domain);
1186 static void edp_panel_vdd_work(struct work_struct *__work)
1188 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1189 struct intel_dp, panel_vdd_work);
1190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192 mutex_lock(&dev->mode_config.mutex);
1193 edp_panel_vdd_off_sync(intel_dp);
1194 mutex_unlock(&dev->mode_config.mutex);
1197 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1199 if (!is_edp(intel_dp))
1202 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1204 intel_dp->want_panel_vdd = false;
1207 edp_panel_vdd_off_sync(intel_dp);
1210 * Queue the timer to fire a long
1211 * time from now (relative to the power down delay)
1212 * to keep the panel power up across a sequence of operations
1214 schedule_delayed_work(&intel_dp->panel_vdd_work,
1215 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1219 void intel_edp_panel_on(struct intel_dp *intel_dp)
1221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1226 if (!is_edp(intel_dp))
1229 DRM_DEBUG_KMS("Turn eDP power on\n");
1231 if (edp_have_panel_power(intel_dp)) {
1232 DRM_DEBUG_KMS("eDP power already on\n");
1236 wait_panel_power_cycle(intel_dp);
1238 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1239 pp = ironlake_get_pp_control(intel_dp);
1241 /* ILK workaround: disable reset around power sequence */
1242 pp &= ~PANEL_POWER_RESET;
1243 I915_WRITE(pp_ctrl_reg, pp);
1244 POSTING_READ(pp_ctrl_reg);
1247 pp |= POWER_TARGET_ON;
1249 pp |= PANEL_POWER_RESET;
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
1254 wait_panel_on(intel_dp);
1255 intel_dp->last_power_on = jiffies;
1258 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1259 I915_WRITE(pp_ctrl_reg, pp);
1260 POSTING_READ(pp_ctrl_reg);
1264 void intel_edp_panel_off(struct intel_dp *intel_dp)
1266 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1267 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 enum intel_display_power_domain power_domain;
1274 if (!is_edp(intel_dp))
1277 DRM_DEBUG_KMS("Turn eDP power off\n");
1279 edp_wait_backlight_off(intel_dp);
1281 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1283 pp = ironlake_get_pp_control(intel_dp);
1284 /* We need to switch off panel power _and_ force vdd, for otherwise some
1285 * panels get very unhappy and cease to work. */
1286 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1291 intel_dp->want_panel_vdd = false;
1293 I915_WRITE(pp_ctrl_reg, pp);
1294 POSTING_READ(pp_ctrl_reg);
1296 intel_dp->last_power_cycle = jiffies;
1297 wait_panel_off(intel_dp);
1299 /* We got a reference when we enabled the VDD. */
1300 power_domain = intel_display_port_power_domain(intel_encoder);
1301 intel_display_power_put(dev_priv, power_domain);
1304 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct drm_device *dev = intel_dig_port->base.base.dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1312 if (!is_edp(intel_dp))
1315 DRM_DEBUG_KMS("\n");
1317 * If we enable the backlight right away following a panel power
1318 * on, we may see slight flicker as the panel syncs with the eDP
1319 * link. So delay a bit to make sure the image is solid before
1320 * allowing it to appear.
1322 wait_backlight_on(intel_dp);
1323 pp = ironlake_get_pp_control(intel_dp);
1324 pp |= EDP_BLC_ENABLE;
1326 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1328 I915_WRITE(pp_ctrl_reg, pp);
1329 POSTING_READ(pp_ctrl_reg);
1331 intel_panel_enable_backlight(intel_dp->attached_connector);
1334 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1336 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1341 if (!is_edp(intel_dp))
1344 intel_panel_disable_backlight(intel_dp->attached_connector);
1346 DRM_DEBUG_KMS("\n");
1347 pp = ironlake_get_pp_control(intel_dp);
1348 pp &= ~EDP_BLC_ENABLE;
1350 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1352 I915_WRITE(pp_ctrl_reg, pp);
1353 POSTING_READ(pp_ctrl_reg);
1354 intel_dp->last_backlight_off = jiffies;
1357 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1359 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1360 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1361 struct drm_device *dev = crtc->dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1365 assert_pipe_disabled(dev_priv,
1366 to_intel_crtc(crtc)->pipe);
1368 DRM_DEBUG_KMS("\n");
1369 dpa_ctl = I915_READ(DP_A);
1370 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1371 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1373 /* We don't adjust intel_dp->DP while tearing down the link, to
1374 * facilitate link retraining (e.g. after hotplug). Hence clear all
1375 * enable bits here to ensure that we don't enable too much. */
1376 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1377 intel_dp->DP |= DP_PLL_ENABLE;
1378 I915_WRITE(DP_A, intel_dp->DP);
1383 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1386 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1387 struct drm_device *dev = crtc->dev;
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1391 assert_pipe_disabled(dev_priv,
1392 to_intel_crtc(crtc)->pipe);
1394 dpa_ctl = I915_READ(DP_A);
1395 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1396 "dp pll off, should be on\n");
1397 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1399 /* We can't rely on the value tracked for the DP register in
1400 * intel_dp->DP because link_down must not change that (otherwise link
1401 * re-training will fail. */
1402 dpa_ctl &= ~DP_PLL_ENABLE;
1403 I915_WRITE(DP_A, dpa_ctl);
1408 /* If the sink supports it, try to set the power state appropriately */
1409 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1413 /* Should have a valid DPCD by this point */
1414 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417 if (mode != DRM_MODE_DPMS_ON) {
1418 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424 * When turning on, we need to retry for 1ms to give the sink
1427 for (i = 0; i < 3; i++) {
1428 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1437 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1441 enum port port = dp_to_dig_port(intel_dp)->port;
1442 struct drm_device *dev = encoder->base.dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 enum intel_display_power_domain power_domain;
1447 power_domain = intel_display_port_power_domain(encoder);
1448 if (!intel_display_power_enabled(dev_priv, power_domain))
1451 tmp = I915_READ(intel_dp->output_reg);
1453 if (!(tmp & DP_PORT_EN))
1456 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1457 *pipe = PORT_TO_PIPE_CPT(tmp);
1458 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1459 *pipe = PORT_TO_PIPE(tmp);
1465 switch (intel_dp->output_reg) {
1467 trans_sel = TRANS_DP_PORT_SEL_B;
1470 trans_sel = TRANS_DP_PORT_SEL_C;
1473 trans_sel = TRANS_DP_PORT_SEL_D;
1480 trans_dp = I915_READ(TRANS_DP_CTL(i));
1481 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1487 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1488 intel_dp->output_reg);
1494 static void intel_dp_get_config(struct intel_encoder *encoder,
1495 struct intel_crtc_config *pipe_config)
1497 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1499 struct drm_device *dev = encoder->base.dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 enum port port = dp_to_dig_port(intel_dp)->port;
1502 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1505 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1506 tmp = I915_READ(intel_dp->output_reg);
1507 if (tmp & DP_SYNC_HS_HIGH)
1508 flags |= DRM_MODE_FLAG_PHSYNC;
1510 flags |= DRM_MODE_FLAG_NHSYNC;
1512 if (tmp & DP_SYNC_VS_HIGH)
1513 flags |= DRM_MODE_FLAG_PVSYNC;
1515 flags |= DRM_MODE_FLAG_NVSYNC;
1517 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1518 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1519 flags |= DRM_MODE_FLAG_PHSYNC;
1521 flags |= DRM_MODE_FLAG_NHSYNC;
1523 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1524 flags |= DRM_MODE_FLAG_PVSYNC;
1526 flags |= DRM_MODE_FLAG_NVSYNC;
1529 pipe_config->adjusted_mode.flags |= flags;
1531 pipe_config->has_dp_encoder = true;
1533 intel_dp_get_m_n(crtc, pipe_config);
1535 if (port == PORT_A) {
1536 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1537 pipe_config->port_clock = 162000;
1539 pipe_config->port_clock = 270000;
1542 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1543 &pipe_config->dp_m_n);
1545 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1546 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1548 pipe_config->adjusted_mode.crtc_clock = dotclock;
1550 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1551 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1553 * This is a big fat ugly hack.
1555 * Some machines in UEFI boot mode provide us a VBT that has 18
1556 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1557 * unknown we fail to light up. Yet the same BIOS boots up with
1558 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1559 * max, not what it tells us to use.
1561 * Note: This will still be broken if the eDP panel is not lit
1562 * up by the BIOS, and thus we can't get the mode at module
1565 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1566 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1567 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1571 static bool is_edp_psr(struct drm_device *dev)
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1575 return dev_priv->psr.sink_support;
1578 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1585 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1588 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1589 struct edp_vsc_psr *vsc_psr)
1591 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1592 struct drm_device *dev = dig_port->base.base.dev;
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1595 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1596 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1597 uint32_t *data = (uint32_t *) vsc_psr;
1600 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1601 the video DIP being updated before program video DIP data buffer
1602 registers for DIP being updated. */
1603 I915_WRITE(ctl_reg, 0);
1604 POSTING_READ(ctl_reg);
1606 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1607 if (i < sizeof(struct edp_vsc_psr))
1608 I915_WRITE(data_reg + i, *data++);
1610 I915_WRITE(data_reg + i, 0);
1613 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1614 POSTING_READ(ctl_reg);
1617 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1619 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 struct edp_vsc_psr psr_vsc;
1623 if (intel_dp->psr_setup_done)
1626 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1627 memset(&psr_vsc, 0, sizeof(psr_vsc));
1628 psr_vsc.sdp_header.HB0 = 0;
1629 psr_vsc.sdp_header.HB1 = 0x7;
1630 psr_vsc.sdp_header.HB2 = 0x2;
1631 psr_vsc.sdp_header.HB3 = 0x8;
1632 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1634 /* Avoid continuous PSR exit by masking memup and hpd */
1635 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1636 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1638 intel_dp->psr_setup_done = true;
1641 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1643 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 uint32_t aux_clock_divider;
1646 int precharge = 0x3;
1647 int msg_size = 5; /* Header(4) + Message(1) */
1649 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1651 /* Enable PSR in sink */
1652 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1653 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1654 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1656 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1657 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1659 /* Setup AUX registers */
1660 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1661 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1662 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1663 DP_AUX_CH_CTL_TIME_OUT_400us |
1664 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1665 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1666 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1669 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1671 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 uint32_t max_sleep_time = 0x1f;
1674 uint32_t idle_frames = 1;
1676 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1678 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1679 val |= EDP_PSR_LINK_STANDBY;
1680 val |= EDP_PSR_TP2_TP3_TIME_0us;
1681 val |= EDP_PSR_TP1_TIME_0us;
1682 val |= EDP_PSR_SKIP_AUX_EXIT;
1684 val |= EDP_PSR_LINK_DISABLE;
1686 I915_WRITE(EDP_PSR_CTL(dev), val |
1687 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1688 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1689 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1693 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1695 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1696 struct drm_device *dev = dig_port->base.base.dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct drm_crtc *crtc = dig_port->base.base.crtc;
1699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1701 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1703 dev_priv->psr.source_ok = false;
1705 if (!HAS_PSR(dev)) {
1706 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1710 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1711 (dig_port->port != PORT_A)) {
1712 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1716 if (!i915.enable_psr) {
1717 DRM_DEBUG_KMS("PSR disable by flag\n");
1721 crtc = dig_port->base.base.crtc;
1723 DRM_DEBUG_KMS("crtc not active for PSR\n");
1727 intel_crtc = to_intel_crtc(crtc);
1728 if (!intel_crtc_active(crtc)) {
1729 DRM_DEBUG_KMS("crtc not active for PSR\n");
1733 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1734 if (obj->tiling_mode != I915_TILING_X ||
1735 obj->fence_reg == I915_FENCE_REG_NONE) {
1736 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1740 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1741 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1745 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1747 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1751 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1752 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1756 dev_priv->psr.source_ok = true;
1760 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1764 if (!intel_edp_psr_match_conditions(intel_dp) ||
1765 intel_edp_is_psr_enabled(dev))
1768 /* Setup PSR once */
1769 intel_edp_psr_setup(intel_dp);
1771 /* Enable PSR on the panel */
1772 intel_edp_psr_enable_sink(intel_dp);
1774 /* Enable PSR on the host */
1775 intel_edp_psr_enable_source(intel_dp);
1778 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1780 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1782 if (intel_edp_psr_match_conditions(intel_dp) &&
1783 !intel_edp_is_psr_enabled(dev))
1784 intel_edp_psr_do_enable(intel_dp);
1787 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1789 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1792 if (!intel_edp_is_psr_enabled(dev))
1795 I915_WRITE(EDP_PSR_CTL(dev),
1796 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1798 /* Wait till PSR is idle */
1799 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1800 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1801 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1804 void intel_edp_psr_update(struct drm_device *dev)
1806 struct intel_encoder *encoder;
1807 struct intel_dp *intel_dp = NULL;
1809 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1810 if (encoder->type == INTEL_OUTPUT_EDP) {
1811 intel_dp = enc_to_intel_dp(&encoder->base);
1813 if (!is_edp_psr(dev))
1816 if (!intel_edp_psr_match_conditions(intel_dp))
1817 intel_edp_psr_disable(intel_dp);
1819 if (!intel_edp_is_psr_enabled(dev))
1820 intel_edp_psr_do_enable(intel_dp);
1824 static void intel_disable_dp(struct intel_encoder *encoder)
1826 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1827 enum port port = dp_to_dig_port(intel_dp)->port;
1828 struct drm_device *dev = encoder->base.dev;
1830 /* Make sure the panel is off before trying to change the mode. But also
1831 * ensure that we have vdd while we switch off the panel. */
1832 intel_edp_panel_vdd_on(intel_dp);
1833 intel_edp_backlight_off(intel_dp);
1834 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1835 intel_edp_panel_off(intel_dp);
1837 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1838 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1839 intel_dp_link_down(intel_dp);
1842 static void g4x_post_disable_dp(struct intel_encoder *encoder)
1844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1845 enum port port = dp_to_dig_port(intel_dp)->port;
1850 intel_dp_link_down(intel_dp);
1851 ironlake_edp_pll_off(intel_dp);
1854 static void vlv_post_disable_dp(struct intel_encoder *encoder)
1856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1858 intel_dp_link_down(intel_dp);
1861 static void intel_enable_dp(struct intel_encoder *encoder)
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864 struct drm_device *dev = encoder->base.dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1868 if (WARN_ON(dp_reg & DP_PORT_EN))
1871 intel_edp_panel_vdd_on(intel_dp);
1872 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1873 intel_dp_start_link_train(intel_dp);
1874 intel_edp_panel_on(intel_dp);
1875 edp_panel_vdd_off(intel_dp, true);
1876 intel_dp_complete_link_train(intel_dp);
1877 intel_dp_stop_link_train(intel_dp);
1880 static void g4x_enable_dp(struct intel_encoder *encoder)
1882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1884 intel_enable_dp(encoder);
1885 intel_edp_backlight_on(intel_dp);
1888 static void vlv_enable_dp(struct intel_encoder *encoder)
1890 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1892 intel_edp_backlight_on(intel_dp);
1895 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1897 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1898 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1900 if (dport->port == PORT_A)
1901 ironlake_edp_pll_on(intel_dp);
1904 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1906 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1908 struct drm_device *dev = encoder->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1911 enum dpio_channel port = vlv_dport_to_channel(dport);
1912 int pipe = intel_crtc->pipe;
1913 struct edp_power_seq power_seq;
1916 mutex_lock(&dev_priv->dpio_lock);
1918 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1925 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1926 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1927 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1929 mutex_unlock(&dev_priv->dpio_lock);
1931 if (is_edp(intel_dp)) {
1932 /* init power sequencer on this pipe and port */
1933 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1934 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1938 intel_enable_dp(encoder);
1940 vlv_wait_port_ready(dev_priv, dport);
1943 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1945 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1946 struct drm_device *dev = encoder->base.dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc =
1949 to_intel_crtc(encoder->base.crtc);
1950 enum dpio_channel port = vlv_dport_to_channel(dport);
1951 int pipe = intel_crtc->pipe;
1953 /* Program Tx lane resets to default */
1954 mutex_lock(&dev_priv->dpio_lock);
1955 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1956 DPIO_PCS_TX_LANE2_RESET |
1957 DPIO_PCS_TX_LANE1_RESET);
1958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1959 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1960 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1961 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1962 DPIO_PCS_CLK_SOFT_RESET);
1964 /* Fix up inter-pair skew failure */
1965 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1966 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1967 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1968 mutex_unlock(&dev_priv->dpio_lock);
1972 * Native read with retry for link status and receiver capability reads for
1973 * cases where the sink may still be asleep.
1975 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1976 * supposed to retry 3 times per the spec.
1979 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1980 void *buffer, size_t size)
1985 for (i = 0; i < 3; i++) {
1986 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1996 * Fetch AUX CH registers 0x202 - 0x207 which contain
1997 * link status information
2000 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2002 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2005 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2009 * These are source-specific values; current Intel hardware supports
2010 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2014 intel_dp_voltage_max(struct intel_dp *intel_dp)
2016 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2017 enum port port = dp_to_dig_port(intel_dp)->port;
2019 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2020 return DP_TRAIN_VOLTAGE_SWING_1200;
2021 else if (IS_GEN7(dev) && port == PORT_A)
2022 return DP_TRAIN_VOLTAGE_SWING_800;
2023 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2024 return DP_TRAIN_VOLTAGE_SWING_1200;
2026 return DP_TRAIN_VOLTAGE_SWING_800;
2030 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2033 enum port port = dp_to_dig_port(intel_dp)->port;
2035 if (IS_BROADWELL(dev)) {
2036 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2037 case DP_TRAIN_VOLTAGE_SWING_400:
2038 case DP_TRAIN_VOLTAGE_SWING_600:
2039 return DP_TRAIN_PRE_EMPHASIS_6;
2040 case DP_TRAIN_VOLTAGE_SWING_800:
2041 return DP_TRAIN_PRE_EMPHASIS_3_5;
2042 case DP_TRAIN_VOLTAGE_SWING_1200:
2044 return DP_TRAIN_PRE_EMPHASIS_0;
2046 } else if (IS_HASWELL(dev)) {
2047 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2048 case DP_TRAIN_VOLTAGE_SWING_400:
2049 return DP_TRAIN_PRE_EMPHASIS_9_5;
2050 case DP_TRAIN_VOLTAGE_SWING_600:
2051 return DP_TRAIN_PRE_EMPHASIS_6;
2052 case DP_TRAIN_VOLTAGE_SWING_800:
2053 return DP_TRAIN_PRE_EMPHASIS_3_5;
2054 case DP_TRAIN_VOLTAGE_SWING_1200:
2056 return DP_TRAIN_PRE_EMPHASIS_0;
2058 } else if (IS_VALLEYVIEW(dev)) {
2059 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2060 case DP_TRAIN_VOLTAGE_SWING_400:
2061 return DP_TRAIN_PRE_EMPHASIS_9_5;
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 return DP_TRAIN_PRE_EMPHASIS_6;
2064 case DP_TRAIN_VOLTAGE_SWING_800:
2065 return DP_TRAIN_PRE_EMPHASIS_3_5;
2066 case DP_TRAIN_VOLTAGE_SWING_1200:
2068 return DP_TRAIN_PRE_EMPHASIS_0;
2070 } else if (IS_GEN7(dev) && port == PORT_A) {
2071 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2072 case DP_TRAIN_VOLTAGE_SWING_400:
2073 return DP_TRAIN_PRE_EMPHASIS_6;
2074 case DP_TRAIN_VOLTAGE_SWING_600:
2075 case DP_TRAIN_VOLTAGE_SWING_800:
2076 return DP_TRAIN_PRE_EMPHASIS_3_5;
2078 return DP_TRAIN_PRE_EMPHASIS_0;
2081 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2082 case DP_TRAIN_VOLTAGE_SWING_400:
2083 return DP_TRAIN_PRE_EMPHASIS_6;
2084 case DP_TRAIN_VOLTAGE_SWING_600:
2085 return DP_TRAIN_PRE_EMPHASIS_6;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 return DP_TRAIN_PRE_EMPHASIS_3_5;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2090 return DP_TRAIN_PRE_EMPHASIS_0;
2095 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2100 struct intel_crtc *intel_crtc =
2101 to_intel_crtc(dport->base.base.crtc);
2102 unsigned long demph_reg_value, preemph_reg_value,
2103 uniqtranscale_reg_value;
2104 uint8_t train_set = intel_dp->train_set[0];
2105 enum dpio_channel port = vlv_dport_to_channel(dport);
2106 int pipe = intel_crtc->pipe;
2108 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2109 case DP_TRAIN_PRE_EMPHASIS_0:
2110 preemph_reg_value = 0x0004000;
2111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2112 case DP_TRAIN_VOLTAGE_SWING_400:
2113 demph_reg_value = 0x2B405555;
2114 uniqtranscale_reg_value = 0x552AB83A;
2116 case DP_TRAIN_VOLTAGE_SWING_600:
2117 demph_reg_value = 0x2B404040;
2118 uniqtranscale_reg_value = 0x5548B83A;
2120 case DP_TRAIN_VOLTAGE_SWING_800:
2121 demph_reg_value = 0x2B245555;
2122 uniqtranscale_reg_value = 0x5560B83A;
2124 case DP_TRAIN_VOLTAGE_SWING_1200:
2125 demph_reg_value = 0x2B405555;
2126 uniqtranscale_reg_value = 0x5598DA3A;
2132 case DP_TRAIN_PRE_EMPHASIS_3_5:
2133 preemph_reg_value = 0x0002000;
2134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 case DP_TRAIN_VOLTAGE_SWING_400:
2136 demph_reg_value = 0x2B404040;
2137 uniqtranscale_reg_value = 0x5552B83A;
2139 case DP_TRAIN_VOLTAGE_SWING_600:
2140 demph_reg_value = 0x2B404848;
2141 uniqtranscale_reg_value = 0x5580B83A;
2143 case DP_TRAIN_VOLTAGE_SWING_800:
2144 demph_reg_value = 0x2B404040;
2145 uniqtranscale_reg_value = 0x55ADDA3A;
2151 case DP_TRAIN_PRE_EMPHASIS_6:
2152 preemph_reg_value = 0x0000000;
2153 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2154 case DP_TRAIN_VOLTAGE_SWING_400:
2155 demph_reg_value = 0x2B305555;
2156 uniqtranscale_reg_value = 0x5570B83A;
2158 case DP_TRAIN_VOLTAGE_SWING_600:
2159 demph_reg_value = 0x2B2B4040;
2160 uniqtranscale_reg_value = 0x55ADDA3A;
2166 case DP_TRAIN_PRE_EMPHASIS_9_5:
2167 preemph_reg_value = 0x0006000;
2168 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2169 case DP_TRAIN_VOLTAGE_SWING_400:
2170 demph_reg_value = 0x1B405555;
2171 uniqtranscale_reg_value = 0x55ADDA3A;
2181 mutex_lock(&dev_priv->dpio_lock);
2182 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2183 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2184 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2185 uniqtranscale_reg_value);
2186 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2187 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2188 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2189 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2190 mutex_unlock(&dev_priv->dpio_lock);
2196 intel_get_adjust_train(struct intel_dp *intel_dp,
2197 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2202 uint8_t voltage_max;
2203 uint8_t preemph_max;
2205 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2206 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2207 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2215 voltage_max = intel_dp_voltage_max(intel_dp);
2216 if (v >= voltage_max)
2217 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2219 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2220 if (p >= preemph_max)
2221 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2223 for (lane = 0; lane < 4; lane++)
2224 intel_dp->train_set[lane] = v | p;
2228 intel_gen4_signal_levels(uint8_t train_set)
2230 uint32_t signal_levels = 0;
2232 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2233 case DP_TRAIN_VOLTAGE_SWING_400:
2235 signal_levels |= DP_VOLTAGE_0_4;
2237 case DP_TRAIN_VOLTAGE_SWING_600:
2238 signal_levels |= DP_VOLTAGE_0_6;
2240 case DP_TRAIN_VOLTAGE_SWING_800:
2241 signal_levels |= DP_VOLTAGE_0_8;
2243 case DP_TRAIN_VOLTAGE_SWING_1200:
2244 signal_levels |= DP_VOLTAGE_1_2;
2247 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2248 case DP_TRAIN_PRE_EMPHASIS_0:
2250 signal_levels |= DP_PRE_EMPHASIS_0;
2252 case DP_TRAIN_PRE_EMPHASIS_3_5:
2253 signal_levels |= DP_PRE_EMPHASIS_3_5;
2255 case DP_TRAIN_PRE_EMPHASIS_6:
2256 signal_levels |= DP_PRE_EMPHASIS_6;
2258 case DP_TRAIN_PRE_EMPHASIS_9_5:
2259 signal_levels |= DP_PRE_EMPHASIS_9_5;
2262 return signal_levels;
2265 /* Gen6's DP voltage swing and pre-emphasis control */
2267 intel_gen6_edp_signal_levels(uint8_t train_set)
2269 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2270 DP_TRAIN_PRE_EMPHASIS_MASK);
2271 switch (signal_levels) {
2272 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2274 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2278 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2279 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2283 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2284 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2285 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2287 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2288 "0x%x\n", signal_levels);
2289 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2293 /* Gen7's DP voltage swing and pre-emphasis control */
2295 intel_gen7_edp_signal_levels(uint8_t train_set)
2297 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2298 DP_TRAIN_PRE_EMPHASIS_MASK);
2299 switch (signal_levels) {
2300 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2301 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2303 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2305 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2308 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2309 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2310 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2312 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2313 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2314 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2315 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels);
2320 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2324 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2326 intel_hsw_signal_levels(uint8_t train_set)
2328 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2329 DP_TRAIN_PRE_EMPHASIS_MASK);
2330 switch (signal_levels) {
2331 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2332 return DDI_BUF_EMP_400MV_0DB_HSW;
2333 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2334 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2335 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2336 return DDI_BUF_EMP_400MV_6DB_HSW;
2337 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2338 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2340 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2341 return DDI_BUF_EMP_600MV_0DB_HSW;
2342 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2343 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2344 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2345 return DDI_BUF_EMP_600MV_6DB_HSW;
2347 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2348 return DDI_BUF_EMP_800MV_0DB_HSW;
2349 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2350 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2352 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2353 "0x%x\n", signal_levels);
2354 return DDI_BUF_EMP_400MV_0DB_HSW;
2359 intel_bdw_signal_levels(uint8_t train_set)
2361 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2362 DP_TRAIN_PRE_EMPHASIS_MASK);
2363 switch (signal_levels) {
2364 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2365 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2366 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2367 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2368 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2369 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2371 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2372 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2373 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2374 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2375 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2376 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2378 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2379 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2380 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2381 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2383 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2384 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2387 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2388 "0x%x\n", signal_levels);
2389 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2393 /* Properly updates "DP" with the correct signal levels. */
2395 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2397 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2398 enum port port = intel_dig_port->port;
2399 struct drm_device *dev = intel_dig_port->base.base.dev;
2400 uint32_t signal_levels, mask;
2401 uint8_t train_set = intel_dp->train_set[0];
2403 if (IS_BROADWELL(dev)) {
2404 signal_levels = intel_bdw_signal_levels(train_set);
2405 mask = DDI_BUF_EMP_MASK;
2406 } else if (IS_HASWELL(dev)) {
2407 signal_levels = intel_hsw_signal_levels(train_set);
2408 mask = DDI_BUF_EMP_MASK;
2409 } else if (IS_VALLEYVIEW(dev)) {
2410 signal_levels = intel_vlv_signal_levels(intel_dp);
2412 } else if (IS_GEN7(dev) && port == PORT_A) {
2413 signal_levels = intel_gen7_edp_signal_levels(train_set);
2414 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2415 } else if (IS_GEN6(dev) && port == PORT_A) {
2416 signal_levels = intel_gen6_edp_signal_levels(train_set);
2417 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2419 signal_levels = intel_gen4_signal_levels(train_set);
2420 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2423 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2425 *DP = (*DP & ~mask) | signal_levels;
2429 intel_dp_set_link_train(struct intel_dp *intel_dp,
2431 uint8_t dp_train_pat)
2433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2434 struct drm_device *dev = intel_dig_port->base.base.dev;
2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 enum port port = intel_dig_port->port;
2437 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2441 uint32_t temp = I915_READ(DP_TP_CTL(port));
2443 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2444 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2446 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2448 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2449 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2450 case DP_TRAINING_PATTERN_DISABLE:
2451 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2454 case DP_TRAINING_PATTERN_1:
2455 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2457 case DP_TRAINING_PATTERN_2:
2458 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2460 case DP_TRAINING_PATTERN_3:
2461 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2464 I915_WRITE(DP_TP_CTL(port), temp);
2466 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2467 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2469 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2470 case DP_TRAINING_PATTERN_DISABLE:
2471 *DP |= DP_LINK_TRAIN_OFF_CPT;
2473 case DP_TRAINING_PATTERN_1:
2474 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2476 case DP_TRAINING_PATTERN_2:
2477 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2479 case DP_TRAINING_PATTERN_3:
2480 DRM_ERROR("DP training pattern 3 not supported\n");
2481 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2486 *DP &= ~DP_LINK_TRAIN_MASK;
2488 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2489 case DP_TRAINING_PATTERN_DISABLE:
2490 *DP |= DP_LINK_TRAIN_OFF;
2492 case DP_TRAINING_PATTERN_1:
2493 *DP |= DP_LINK_TRAIN_PAT_1;
2495 case DP_TRAINING_PATTERN_2:
2496 *DP |= DP_LINK_TRAIN_PAT_2;
2498 case DP_TRAINING_PATTERN_3:
2499 DRM_ERROR("DP training pattern 3 not supported\n");
2500 *DP |= DP_LINK_TRAIN_PAT_2;
2505 I915_WRITE(intel_dp->output_reg, *DP);
2506 POSTING_READ(intel_dp->output_reg);
2508 buf[0] = dp_train_pat;
2509 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2510 DP_TRAINING_PATTERN_DISABLE) {
2511 /* don't write DP_TRAINING_LANEx_SET on disable */
2514 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2515 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2516 len = intel_dp->lane_count + 1;
2519 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2526 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2527 uint8_t dp_train_pat)
2529 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2530 intel_dp_set_signal_levels(intel_dp, DP);
2531 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2535 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2536 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2538 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2539 struct drm_device *dev = intel_dig_port->base.base.dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
2543 intel_get_adjust_train(intel_dp, link_status);
2544 intel_dp_set_signal_levels(intel_dp, DP);
2546 I915_WRITE(intel_dp->output_reg, *DP);
2547 POSTING_READ(intel_dp->output_reg);
2549 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2550 intel_dp->train_set, intel_dp->lane_count);
2552 return ret == intel_dp->lane_count;
2555 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2558 struct drm_device *dev = intel_dig_port->base.base.dev;
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560 enum port port = intel_dig_port->port;
2566 val = I915_READ(DP_TP_CTL(port));
2567 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2568 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2569 I915_WRITE(DP_TP_CTL(port), val);
2572 * On PORT_A we can have only eDP in SST mode. There the only reason
2573 * we need to set idle transmission mode is to work around a HW issue
2574 * where we enable the pipe while not in idle link-training mode.
2575 * In this case there is requirement to wait for a minimum number of
2576 * idle patterns to be sent.
2581 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2583 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2586 /* Enable corresponding port and start training pattern 1 */
2588 intel_dp_start_link_train(struct intel_dp *intel_dp)
2590 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2591 struct drm_device *dev = encoder->dev;
2594 int voltage_tries, loop_tries;
2595 uint32_t DP = intel_dp->DP;
2596 uint8_t link_config[2];
2599 intel_ddi_prepare_link_retrain(encoder);
2601 /* Write the link configuration data */
2602 link_config[0] = intel_dp->link_bw;
2603 link_config[1] = intel_dp->lane_count;
2604 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2605 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2606 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2609 link_config[1] = DP_SET_ANSI_8B10B;
2610 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2614 /* clock recovery */
2615 if (!intel_dp_reset_link_train(intel_dp, &DP,
2616 DP_TRAINING_PATTERN_1 |
2617 DP_LINK_SCRAMBLING_DISABLE)) {
2618 DRM_ERROR("failed to enable link training\n");
2626 uint8_t link_status[DP_LINK_STATUS_SIZE];
2628 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2629 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2630 DRM_ERROR("failed to get link status\n");
2634 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2635 DRM_DEBUG_KMS("clock recovery OK\n");
2639 /* Check to see if we've tried the max voltage */
2640 for (i = 0; i < intel_dp->lane_count; i++)
2641 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2643 if (i == intel_dp->lane_count) {
2645 if (loop_tries == 5) {
2646 DRM_ERROR("too many full retries, give up\n");
2649 intel_dp_reset_link_train(intel_dp, &DP,
2650 DP_TRAINING_PATTERN_1 |
2651 DP_LINK_SCRAMBLING_DISABLE);
2656 /* Check to see if we've tried the same voltage 5 times */
2657 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2659 if (voltage_tries == 5) {
2660 DRM_ERROR("too many voltage retries, give up\n");
2665 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2667 /* Update training set as requested by target */
2668 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2669 DRM_ERROR("failed to update link training\n");
2678 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2680 bool channel_eq = false;
2681 int tries, cr_tries;
2682 uint32_t DP = intel_dp->DP;
2683 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2685 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2686 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2687 training_pattern = DP_TRAINING_PATTERN_3;
2689 /* channel equalization */
2690 if (!intel_dp_set_link_train(intel_dp, &DP,
2692 DP_LINK_SCRAMBLING_DISABLE)) {
2693 DRM_ERROR("failed to start channel equalization\n");
2701 uint8_t link_status[DP_LINK_STATUS_SIZE];
2704 DRM_ERROR("failed to train DP, aborting\n");
2708 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2709 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2710 DRM_ERROR("failed to get link status\n");
2714 /* Make sure clock is still ok */
2715 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2716 intel_dp_start_link_train(intel_dp);
2717 intel_dp_set_link_train(intel_dp, &DP,
2719 DP_LINK_SCRAMBLING_DISABLE);
2724 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2729 /* Try 5 times, then try clock recovery if that fails */
2731 intel_dp_link_down(intel_dp);
2732 intel_dp_start_link_train(intel_dp);
2733 intel_dp_set_link_train(intel_dp, &DP,
2735 DP_LINK_SCRAMBLING_DISABLE);
2741 /* Update training set as requested by target */
2742 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2743 DRM_ERROR("failed to update link training\n");
2749 intel_dp_set_idle_link_train(intel_dp);
2754 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2758 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2760 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2761 DP_TRAINING_PATTERN_DISABLE);
2765 intel_dp_link_down(struct intel_dp *intel_dp)
2767 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2768 enum port port = intel_dig_port->port;
2769 struct drm_device *dev = intel_dig_port->base.base.dev;
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_crtc *intel_crtc =
2772 to_intel_crtc(intel_dig_port->base.base.crtc);
2773 uint32_t DP = intel_dp->DP;
2776 * DDI code has a strict mode set sequence and we should try to respect
2777 * it, otherwise we might hang the machine in many different ways. So we
2778 * really should be disabling the port only on a complete crtc_disable
2779 * sequence. This function is just called under two conditions on DDI
2781 * - Link train failed while doing crtc_enable, and on this case we
2782 * really should respect the mode set sequence and wait for a
2784 * - Someone turned the monitor off and intel_dp_check_link_status
2785 * called us. We don't need to disable the whole port on this case, so
2786 * when someone turns the monitor on again,
2787 * intel_ddi_prepare_link_retrain will take care of redoing the link
2793 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2796 DRM_DEBUG_KMS("\n");
2798 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2799 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2800 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2802 DP &= ~DP_LINK_TRAIN_MASK;
2803 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2805 POSTING_READ(intel_dp->output_reg);
2807 if (HAS_PCH_IBX(dev) &&
2808 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2809 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2811 /* Hardware workaround: leaving our transcoder select
2812 * set to transcoder B while it's off will prevent the
2813 * corresponding HDMI output on transcoder A.
2815 * Combine this with another hardware workaround:
2816 * transcoder select bit can only be cleared while the
2819 DP &= ~DP_PIPEB_SELECT;
2820 I915_WRITE(intel_dp->output_reg, DP);
2822 /* Changes to enable or select take place the vblank
2823 * after being written.
2825 if (WARN_ON(crtc == NULL)) {
2826 /* We should never try to disable a port without a crtc
2827 * attached. For paranoia keep the code around for a
2829 POSTING_READ(intel_dp->output_reg);
2832 intel_wait_for_vblank(dev, intel_crtc->pipe);
2835 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2836 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2837 POSTING_READ(intel_dp->output_reg);
2838 msleep(intel_dp->panel_power_down_delay);
2842 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2844 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2845 struct drm_device *dev = dig_port->base.base.dev;
2846 struct drm_i915_private *dev_priv = dev->dev_private;
2848 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2850 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2851 sizeof(intel_dp->dpcd)) < 0)
2852 return false; /* aux transfer failed */
2854 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2855 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2856 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2858 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2859 return false; /* DPCD not present */
2861 /* Check if the panel supports PSR */
2862 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2863 if (is_edp(intel_dp)) {
2864 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2866 sizeof(intel_dp->psr_dpcd));
2867 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2868 dev_priv->psr.sink_support = true;
2869 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2873 /* Training Pattern 3 support */
2874 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2875 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2876 intel_dp->use_tps3 = true;
2877 DRM_DEBUG_KMS("Displayport TPS3 supported");
2879 intel_dp->use_tps3 = false;
2881 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2882 DP_DWN_STRM_PORT_PRESENT))
2883 return true; /* native DP sink */
2885 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2886 return true; /* no per-port downstream info */
2888 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2889 intel_dp->downstream_ports,
2890 DP_MAX_DOWNSTREAM_PORTS) < 0)
2891 return false; /* downstream port status fetch failed */
2897 intel_dp_probe_oui(struct intel_dp *intel_dp)
2901 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2904 intel_edp_panel_vdd_on(intel_dp);
2906 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2907 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2908 buf[0], buf[1], buf[2]);
2910 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2911 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2912 buf[0], buf[1], buf[2]);
2914 edp_panel_vdd_off(intel_dp, false);
2917 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2919 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2920 struct drm_device *dev = intel_dig_port->base.base.dev;
2921 struct intel_crtc *intel_crtc =
2922 to_intel_crtc(intel_dig_port->base.base.crtc);
2925 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2928 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2931 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2932 DP_TEST_SINK_START) < 0)
2935 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2936 intel_wait_for_vblank(dev, intel_crtc->pipe);
2937 intel_wait_for_vblank(dev, intel_crtc->pipe);
2939 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2942 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2947 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2949 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2950 DP_DEVICE_SERVICE_IRQ_VECTOR,
2951 sink_irq_vector, 1) == 1;
2955 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2957 /* NAK by default */
2958 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2962 * According to DP spec
2965 * 2. Configure link according to Receiver Capabilities
2966 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2967 * 4. Check link status on receipt of hot-plug interrupt
2971 intel_dp_check_link_status(struct intel_dp *intel_dp)
2973 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2975 u8 link_status[DP_LINK_STATUS_SIZE];
2977 if (!intel_encoder->connectors_active)
2980 if (WARN_ON(!intel_encoder->base.crtc))
2983 /* Try to read receiver status if the link appears to be up */
2984 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2988 /* Now read the DPCD to see if it's actually running */
2989 if (!intel_dp_get_dpcd(intel_dp)) {
2993 /* Try to read the source of the interrupt */
2994 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2995 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2996 /* Clear interrupt source */
2997 drm_dp_dpcd_writeb(&intel_dp->aux,
2998 DP_DEVICE_SERVICE_IRQ_VECTOR,
3001 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3002 intel_dp_handle_test_request(intel_dp);
3003 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3004 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3007 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3008 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3009 drm_get_encoder_name(&intel_encoder->base));
3010 intel_dp_start_link_train(intel_dp);
3011 intel_dp_complete_link_train(intel_dp);
3012 intel_dp_stop_link_train(intel_dp);
3016 /* XXX this is probably wrong for multiple downstream ports */
3017 static enum drm_connector_status
3018 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3020 uint8_t *dpcd = intel_dp->dpcd;
3023 if (!intel_dp_get_dpcd(intel_dp))
3024 return connector_status_disconnected;
3026 /* if there's no downstream port, we're done */
3027 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3028 return connector_status_connected;
3030 /* If we're HPD-aware, SINK_COUNT changes dynamically */
3031 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3032 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3035 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3037 return connector_status_unknown;
3039 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3040 : connector_status_disconnected;
3043 /* If no HPD, poke DDC gently */
3044 if (drm_probe_ddc(&intel_dp->aux.ddc))
3045 return connector_status_connected;
3047 /* Well we tried, say unknown for unreliable port types */
3048 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3049 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3050 if (type == DP_DS_PORT_TYPE_VGA ||
3051 type == DP_DS_PORT_TYPE_NON_EDID)
3052 return connector_status_unknown;
3054 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3055 DP_DWN_STRM_PORT_TYPE_MASK;
3056 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3057 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3058 return connector_status_unknown;
3061 /* Anything else is out of spec, warn and ignore */
3062 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3063 return connector_status_disconnected;
3066 static enum drm_connector_status
3067 ironlake_dp_detect(struct intel_dp *intel_dp)
3069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3070 struct drm_i915_private *dev_priv = dev->dev_private;
3071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3072 enum drm_connector_status status;
3074 /* Can't disconnect eDP, but you can close the lid... */
3075 if (is_edp(intel_dp)) {
3076 status = intel_panel_detect(dev);
3077 if (status == connector_status_unknown)
3078 status = connector_status_connected;
3082 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3083 return connector_status_disconnected;
3085 return intel_dp_detect_dpcd(intel_dp);
3088 static enum drm_connector_status
3089 g4x_dp_detect(struct intel_dp *intel_dp)
3091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3096 /* Can't disconnect eDP, but you can close the lid... */
3097 if (is_edp(intel_dp)) {
3098 enum drm_connector_status status;
3100 status = intel_panel_detect(dev);
3101 if (status == connector_status_unknown)
3102 status = connector_status_connected;
3106 if (IS_VALLEYVIEW(dev)) {
3107 switch (intel_dig_port->port) {
3109 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3112 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3115 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3118 return connector_status_unknown;
3121 switch (intel_dig_port->port) {
3123 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3126 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3129 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3132 return connector_status_unknown;
3136 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3137 return connector_status_disconnected;
3139 return intel_dp_detect_dpcd(intel_dp);
3142 static struct edid *
3143 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3145 struct intel_connector *intel_connector = to_intel_connector(connector);
3147 /* use cached edid if we have one */
3148 if (intel_connector->edid) {
3150 if (IS_ERR(intel_connector->edid))
3153 return drm_edid_duplicate(intel_connector->edid);
3156 return drm_get_edid(connector, adapter);
3160 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3162 struct intel_connector *intel_connector = to_intel_connector(connector);
3164 /* use cached edid if we have one */
3165 if (intel_connector->edid) {
3167 if (IS_ERR(intel_connector->edid))
3170 return intel_connector_update_modes(connector,
3171 intel_connector->edid);
3174 return intel_ddc_get_modes(connector, adapter);
3177 static enum drm_connector_status
3178 intel_dp_detect(struct drm_connector *connector, bool force)
3180 struct intel_dp *intel_dp = intel_attached_dp(connector);
3181 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3182 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3183 struct drm_device *dev = connector->dev;
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 enum drm_connector_status status;
3186 enum intel_display_power_domain power_domain;
3187 struct edid *edid = NULL;
3189 intel_runtime_pm_get(dev_priv);
3191 power_domain = intel_display_port_power_domain(intel_encoder);
3192 intel_display_power_get(dev_priv, power_domain);
3194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3195 connector->base.id, drm_get_connector_name(connector));
3197 intel_dp->has_audio = false;
3199 if (HAS_PCH_SPLIT(dev))
3200 status = ironlake_dp_detect(intel_dp);
3202 status = g4x_dp_detect(intel_dp);
3204 if (status != connector_status_connected)
3207 intel_dp_probe_oui(intel_dp);
3209 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3210 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3212 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3214 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3219 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3220 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3221 status = connector_status_connected;
3224 intel_display_power_put(dev_priv, power_domain);
3226 intel_runtime_pm_put(dev_priv);
3231 static int intel_dp_get_modes(struct drm_connector *connector)
3233 struct intel_dp *intel_dp = intel_attached_dp(connector);
3234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3235 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3236 struct intel_connector *intel_connector = to_intel_connector(connector);
3237 struct drm_device *dev = connector->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 enum intel_display_power_domain power_domain;
3242 /* We should parse the EDID data and find out if it has an audio sink
3245 power_domain = intel_display_port_power_domain(intel_encoder);
3246 intel_display_power_get(dev_priv, power_domain);
3248 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3249 intel_display_power_put(dev_priv, power_domain);
3253 /* if eDP has no EDID, fall back to fixed mode */
3254 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3255 struct drm_display_mode *mode;
3256 mode = drm_mode_duplicate(dev,
3257 intel_connector->panel.fixed_mode);
3259 drm_mode_probed_add(connector, mode);
3267 intel_dp_detect_audio(struct drm_connector *connector)
3269 struct intel_dp *intel_dp = intel_attached_dp(connector);
3270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3271 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3272 struct drm_device *dev = connector->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 enum intel_display_power_domain power_domain;
3276 bool has_audio = false;
3278 power_domain = intel_display_port_power_domain(intel_encoder);
3279 intel_display_power_get(dev_priv, power_domain);
3281 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3283 has_audio = drm_detect_monitor_audio(edid);
3287 intel_display_power_put(dev_priv, power_domain);
3293 intel_dp_set_property(struct drm_connector *connector,
3294 struct drm_property *property,
3297 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3298 struct intel_connector *intel_connector = to_intel_connector(connector);
3299 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3300 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3303 ret = drm_object_property_set_value(&connector->base, property, val);
3307 if (property == dev_priv->force_audio_property) {
3311 if (i == intel_dp->force_audio)
3314 intel_dp->force_audio = i;
3316 if (i == HDMI_AUDIO_AUTO)
3317 has_audio = intel_dp_detect_audio(connector);
3319 has_audio = (i == HDMI_AUDIO_ON);
3321 if (has_audio == intel_dp->has_audio)
3324 intel_dp->has_audio = has_audio;
3328 if (property == dev_priv->broadcast_rgb_property) {
3329 bool old_auto = intel_dp->color_range_auto;
3330 uint32_t old_range = intel_dp->color_range;
3333 case INTEL_BROADCAST_RGB_AUTO:
3334 intel_dp->color_range_auto = true;
3336 case INTEL_BROADCAST_RGB_FULL:
3337 intel_dp->color_range_auto = false;
3338 intel_dp->color_range = 0;
3340 case INTEL_BROADCAST_RGB_LIMITED:
3341 intel_dp->color_range_auto = false;
3342 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3348 if (old_auto == intel_dp->color_range_auto &&
3349 old_range == intel_dp->color_range)
3355 if (is_edp(intel_dp) &&
3356 property == connector->dev->mode_config.scaling_mode_property) {
3357 if (val == DRM_MODE_SCALE_NONE) {
3358 DRM_DEBUG_KMS("no scaling not supported\n");
3362 if (intel_connector->panel.fitting_mode == val) {
3363 /* the eDP scaling property is not changed */
3366 intel_connector->panel.fitting_mode = val;
3374 if (intel_encoder->base.crtc)
3375 intel_crtc_restore_mode(intel_encoder->base.crtc);
3381 intel_dp_connector_destroy(struct drm_connector *connector)
3383 struct intel_connector *intel_connector = to_intel_connector(connector);
3385 if (!IS_ERR_OR_NULL(intel_connector->edid))
3386 kfree(intel_connector->edid);
3388 /* Can't call is_edp() since the encoder may have been destroyed
3390 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3391 intel_panel_fini(&intel_connector->panel);
3393 drm_connector_cleanup(connector);
3397 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3399 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3400 struct intel_dp *intel_dp = &intel_dig_port->dp;
3401 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3403 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3404 drm_encoder_cleanup(encoder);
3405 if (is_edp(intel_dp)) {
3406 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3407 mutex_lock(&dev->mode_config.mutex);
3408 edp_panel_vdd_off_sync(intel_dp);
3409 mutex_unlock(&dev->mode_config.mutex);
3411 kfree(intel_dig_port);
3414 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3415 .dpms = intel_connector_dpms,
3416 .detect = intel_dp_detect,
3417 .fill_modes = drm_helper_probe_single_connector_modes,
3418 .set_property = intel_dp_set_property,
3419 .destroy = intel_dp_connector_destroy,
3422 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3423 .get_modes = intel_dp_get_modes,
3424 .mode_valid = intel_dp_mode_valid,
3425 .best_encoder = intel_best_encoder,
3428 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3429 .destroy = intel_dp_encoder_destroy,
3433 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3435 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3437 intel_dp_check_link_status(intel_dp);
3440 /* Return which DP Port should be selected for Transcoder DP control */
3442 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3444 struct drm_device *dev = crtc->dev;
3445 struct intel_encoder *intel_encoder;
3446 struct intel_dp *intel_dp;
3448 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3449 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3451 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3452 intel_encoder->type == INTEL_OUTPUT_EDP)
3453 return intel_dp->output_reg;
3459 /* check the VBT to see whether the eDP is on DP-D port */
3460 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3462 struct drm_i915_private *dev_priv = dev->dev_private;
3463 union child_device_config *p_child;
3465 static const short port_mapping[] = {
3466 [PORT_B] = PORT_IDPB,
3467 [PORT_C] = PORT_IDPC,
3468 [PORT_D] = PORT_IDPD,
3474 if (!dev_priv->vbt.child_dev_num)
3477 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3478 p_child = dev_priv->vbt.child_dev + i;
3480 if (p_child->common.dvo_port == port_mapping[port] &&
3481 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3482 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3489 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3491 struct intel_connector *intel_connector = to_intel_connector(connector);
3493 intel_attach_force_audio_property(connector);
3494 intel_attach_broadcast_rgb_property(connector);
3495 intel_dp->color_range_auto = true;
3497 if (is_edp(intel_dp)) {
3498 drm_mode_create_scaling_mode_property(connector->dev);
3499 drm_object_attach_property(
3501 connector->dev->mode_config.scaling_mode_property,
3502 DRM_MODE_SCALE_ASPECT);
3503 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3507 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3509 intel_dp->last_power_cycle = jiffies;
3510 intel_dp->last_power_on = jiffies;
3511 intel_dp->last_backlight_off = jiffies;
3515 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3516 struct intel_dp *intel_dp,
3517 struct edp_power_seq *out)
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 struct edp_power_seq cur, vbt, spec, final;
3521 u32 pp_on, pp_off, pp_div, pp;
3522 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3524 if (HAS_PCH_SPLIT(dev)) {
3525 pp_ctrl_reg = PCH_PP_CONTROL;
3526 pp_on_reg = PCH_PP_ON_DELAYS;
3527 pp_off_reg = PCH_PP_OFF_DELAYS;
3528 pp_div_reg = PCH_PP_DIVISOR;
3530 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3532 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3533 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3534 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3535 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3538 /* Workaround: Need to write PP_CONTROL with the unlock key as
3539 * the very first thing. */
3540 pp = ironlake_get_pp_control(intel_dp);
3541 I915_WRITE(pp_ctrl_reg, pp);
3543 pp_on = I915_READ(pp_on_reg);
3544 pp_off = I915_READ(pp_off_reg);
3545 pp_div = I915_READ(pp_div_reg);
3547 /* Pull timing values out of registers */
3548 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3549 PANEL_POWER_UP_DELAY_SHIFT;
3551 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3552 PANEL_LIGHT_ON_DELAY_SHIFT;
3554 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3555 PANEL_LIGHT_OFF_DELAY_SHIFT;
3557 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3558 PANEL_POWER_DOWN_DELAY_SHIFT;
3560 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3561 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3563 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3564 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3566 vbt = dev_priv->vbt.edp_pps;
3568 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3569 * our hw here, which are all in 100usec. */
3570 spec.t1_t3 = 210 * 10;
3571 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3572 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3573 spec.t10 = 500 * 10;
3574 /* This one is special and actually in units of 100ms, but zero
3575 * based in the hw (so we need to add 100 ms). But the sw vbt
3576 * table multiplies it with 1000 to make it in units of 100usec,
3578 spec.t11_t12 = (510 + 100) * 10;
3580 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3581 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3583 /* Use the max of the register settings and vbt. If both are
3584 * unset, fall back to the spec limits. */
3585 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3587 max(cur.field, vbt.field))
3588 assign_final(t1_t3);
3592 assign_final(t11_t12);
3595 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3596 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3597 intel_dp->backlight_on_delay = get_delay(t8);
3598 intel_dp->backlight_off_delay = get_delay(t9);
3599 intel_dp->panel_power_down_delay = get_delay(t10);
3600 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3603 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3604 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3605 intel_dp->panel_power_cycle_delay);
3607 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3608 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3615 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3616 struct intel_dp *intel_dp,
3617 struct edp_power_seq *seq)
3619 struct drm_i915_private *dev_priv = dev->dev_private;
3620 u32 pp_on, pp_off, pp_div, port_sel = 0;
3621 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3622 int pp_on_reg, pp_off_reg, pp_div_reg;
3624 if (HAS_PCH_SPLIT(dev)) {
3625 pp_on_reg = PCH_PP_ON_DELAYS;
3626 pp_off_reg = PCH_PP_OFF_DELAYS;
3627 pp_div_reg = PCH_PP_DIVISOR;
3629 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3631 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3632 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3633 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3637 * And finally store the new values in the power sequencer. The
3638 * backlight delays are set to 1 because we do manual waits on them. For
3639 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3640 * we'll end up waiting for the backlight off delay twice: once when we
3641 * do the manual sleep, and once when we disable the panel and wait for
3642 * the PP_STATUS bit to become zero.
3644 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3645 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3646 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3647 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3648 /* Compute the divisor for the pp clock, simply match the Bspec
3650 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3651 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3652 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3654 /* Haswell doesn't have any port selection bits for the panel
3655 * power sequencer any more. */
3656 if (IS_VALLEYVIEW(dev)) {
3657 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3658 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3660 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3661 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3662 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3663 port_sel = PANEL_PORT_SELECT_DPA;
3665 port_sel = PANEL_PORT_SELECT_DPD;
3670 I915_WRITE(pp_on_reg, pp_on);
3671 I915_WRITE(pp_off_reg, pp_off);
3672 I915_WRITE(pp_div_reg, pp_div);
3674 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3675 I915_READ(pp_on_reg),
3676 I915_READ(pp_off_reg),
3677 I915_READ(pp_div_reg));
3680 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_encoder *encoder;
3684 struct intel_dp *intel_dp = NULL;
3685 struct intel_crtc_config *config = NULL;
3686 struct intel_crtc *intel_crtc = NULL;
3687 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3689 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3691 if (refresh_rate <= 0) {
3692 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3696 if (intel_connector == NULL) {
3697 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3701 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3702 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3706 encoder = intel_attached_encoder(&intel_connector->base);
3707 intel_dp = enc_to_intel_dp(&encoder->base);
3708 intel_crtc = encoder->new_crtc;
3711 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3715 config = &intel_crtc->config;
3717 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3718 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3722 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3723 index = DRRS_LOW_RR;
3725 if (index == intel_dp->drrs_state.refresh_rate_type) {
3727 "DRRS requested for previously set RR...ignoring\n");
3731 if (!intel_crtc->active) {
3732 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3736 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3737 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3738 val = I915_READ(reg);
3739 if (index > DRRS_HIGH_RR) {
3740 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3741 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3743 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3745 I915_WRITE(reg, val);
3749 * mutex taken to ensure that there is no race between differnt
3750 * drrs calls trying to update refresh rate. This scenario may occur
3751 * in future when idleness detection based DRRS in kernel and
3752 * possible calls from user space to set differnt RR are made.
3755 mutex_lock(&intel_dp->drrs_state.mutex);
3757 intel_dp->drrs_state.refresh_rate_type = index;
3759 mutex_unlock(&intel_dp->drrs_state.mutex);
3761 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3764 static struct drm_display_mode *
3765 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3766 struct intel_connector *intel_connector,
3767 struct drm_display_mode *fixed_mode)
3769 struct drm_connector *connector = &intel_connector->base;
3770 struct intel_dp *intel_dp = &intel_dig_port->dp;
3771 struct drm_device *dev = intel_dig_port->base.base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773 struct drm_display_mode *downclock_mode = NULL;
3775 if (INTEL_INFO(dev)->gen <= 6) {
3776 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3780 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3781 DRM_INFO("VBT doesn't support DRRS\n");
3785 downclock_mode = intel_find_panel_downclock
3786 (dev, fixed_mode, connector);
3788 if (!downclock_mode) {
3789 DRM_INFO("DRRS not supported\n");
3793 dev_priv->drrs.connector = intel_connector;
3795 mutex_init(&intel_dp->drrs_state.mutex);
3797 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3799 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3800 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3801 return downclock_mode;
3804 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3805 struct intel_connector *intel_connector,
3806 struct edp_power_seq *power_seq)
3808 struct drm_connector *connector = &intel_connector->base;
3809 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3810 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3811 struct drm_device *dev = intel_encoder->base.dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 struct drm_display_mode *fixed_mode = NULL;
3814 struct drm_display_mode *downclock_mode = NULL;
3816 struct drm_display_mode *scan;
3819 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
3821 if (!is_edp(intel_dp))
3824 /* The VDD bit needs a power domain reference, so if the bit is already
3825 * enabled when we boot, grab this reference. */
3826 if (edp_have_panel_vdd(intel_dp)) {
3827 enum intel_display_power_domain power_domain;
3828 power_domain = intel_display_port_power_domain(intel_encoder);
3829 intel_display_power_get(dev_priv, power_domain);
3832 /* Cache DPCD and EDID for edp. */
3833 intel_edp_panel_vdd_on(intel_dp);
3834 has_dpcd = intel_dp_get_dpcd(intel_dp);
3835 edp_panel_vdd_off(intel_dp, false);
3838 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3839 dev_priv->no_aux_handshake =
3840 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3841 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3843 /* if this fails, presume the device is a ghost */
3844 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3848 /* We now know it's not a ghost, init power sequence regs. */
3849 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3851 mutex_lock(&dev->mode_config.mutex);
3852 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3854 if (drm_add_edid_modes(connector, edid)) {
3855 drm_mode_connector_update_edid_property(connector,
3857 drm_edid_to_eld(connector, edid);
3860 edid = ERR_PTR(-EINVAL);
3863 edid = ERR_PTR(-ENOENT);
3865 intel_connector->edid = edid;
3867 /* prefer fixed mode from EDID if available */
3868 list_for_each_entry(scan, &connector->probed_modes, head) {
3869 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3870 fixed_mode = drm_mode_duplicate(dev, scan);
3871 downclock_mode = intel_dp_drrs_init(
3873 intel_connector, fixed_mode);
3878 /* fallback to VBT if available for eDP */
3879 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3880 fixed_mode = drm_mode_duplicate(dev,
3881 dev_priv->vbt.lfp_lvds_vbt_mode);
3883 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3885 mutex_unlock(&dev->mode_config.mutex);
3887 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
3888 intel_panel_setup_backlight(connector);
3894 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3895 struct intel_connector *intel_connector)
3897 struct drm_connector *connector = &intel_connector->base;
3898 struct intel_dp *intel_dp = &intel_dig_port->dp;
3899 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3900 struct drm_device *dev = intel_encoder->base.dev;
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 enum port port = intel_dig_port->port;
3903 struct edp_power_seq power_seq = { 0 };
3906 /* intel_dp vfuncs */
3907 if (IS_VALLEYVIEW(dev))
3908 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3909 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3910 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3911 else if (HAS_PCH_SPLIT(dev))
3912 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3914 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3916 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3918 /* Preserve the current hw state. */
3919 intel_dp->DP = I915_READ(intel_dp->output_reg);
3920 intel_dp->attached_connector = intel_connector;
3922 if (intel_dp_is_edp(dev, port))
3923 type = DRM_MODE_CONNECTOR_eDP;
3925 type = DRM_MODE_CONNECTOR_DisplayPort;
3928 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3929 * for DP the encoder type can be set by the caller to
3930 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3932 if (type == DRM_MODE_CONNECTOR_eDP)
3933 intel_encoder->type = INTEL_OUTPUT_EDP;
3935 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3936 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3939 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3940 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3942 connector->interlace_allowed = true;
3943 connector->doublescan_allowed = 0;
3945 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3946 edp_panel_vdd_work);
3948 intel_connector_attach_encoder(intel_connector, intel_encoder);
3949 drm_sysfs_connector_add(connector);
3952 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3954 intel_connector->get_hw_state = intel_connector_get_hw_state;
3955 intel_connector->unregister = intel_dp_connector_unregister;
3957 /* Set up the hotplug pin. */
3960 intel_encoder->hpd_pin = HPD_PORT_A;
3963 intel_encoder->hpd_pin = HPD_PORT_B;
3966 intel_encoder->hpd_pin = HPD_PORT_C;
3969 intel_encoder->hpd_pin = HPD_PORT_D;
3975 if (is_edp(intel_dp)) {
3976 intel_dp_init_panel_power_timestamps(intel_dp);
3977 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3980 intel_dp_aux_init(intel_dp, intel_connector);
3982 intel_dp->psr_setup_done = false;
3984 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3985 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3986 if (is_edp(intel_dp)) {
3987 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3988 mutex_lock(&dev->mode_config.mutex);
3989 edp_panel_vdd_off_sync(intel_dp);
3990 mutex_unlock(&dev->mode_config.mutex);
3992 drm_sysfs_connector_remove(connector);
3993 drm_connector_cleanup(connector);
3997 intel_dp_add_properties(intel_dp, connector);
3999 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4000 * 0xd. Failure to do so will result in spurious interrupts being
4001 * generated on the port when a cable is not attached.
4003 if (IS_G4X(dev) && !IS_GM45(dev)) {
4004 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4005 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4012 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4014 struct intel_digital_port *intel_dig_port;
4015 struct intel_encoder *intel_encoder;
4016 struct drm_encoder *encoder;
4017 struct intel_connector *intel_connector;
4019 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4020 if (!intel_dig_port)
4023 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4024 if (!intel_connector) {
4025 kfree(intel_dig_port);
4029 intel_encoder = &intel_dig_port->base;
4030 encoder = &intel_encoder->base;
4032 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4033 DRM_MODE_ENCODER_TMDS);
4035 intel_encoder->compute_config = intel_dp_compute_config;
4036 intel_encoder->mode_set = intel_dp_mode_set;
4037 intel_encoder->disable = intel_disable_dp;
4038 intel_encoder->get_hw_state = intel_dp_get_hw_state;
4039 intel_encoder->get_config = intel_dp_get_config;
4040 if (IS_VALLEYVIEW(dev)) {
4041 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4042 intel_encoder->pre_enable = vlv_pre_enable_dp;
4043 intel_encoder->enable = vlv_enable_dp;
4044 intel_encoder->post_disable = vlv_post_disable_dp;
4046 intel_encoder->pre_enable = g4x_pre_enable_dp;
4047 intel_encoder->enable = g4x_enable_dp;
4048 intel_encoder->post_disable = g4x_post_disable_dp;
4051 intel_dig_port->port = port;
4052 intel_dig_port->dp.output_reg = output_reg;
4054 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4055 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4056 intel_encoder->cloneable = 0;
4057 intel_encoder->hot_plug = intel_dp_hot_plug;
4059 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4060 drm_encoder_cleanup(encoder);
4061 kfree(intel_dig_port);
4062 kfree(intel_connector);