drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /*
  68  * CHV supports eDP 1.4 that have  more link rates.
  69  * Below only provides the fixed rate but exclude variable rate.
  70  */
  71 static const struct dp_link_dpll chv_dpll[] = {
  72         /*
  73          * CHV requires to program fractional division for m2.
  74          * m2 is stored in fixed point format using formula below
  75          * (m2_int << 22) | m2_fraction
  76          */
  77         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  78                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  79         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  80                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  81         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  83 };
  84
  85 /**
  86  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  87  * @intel_dp: DP struct
  88  *
  89  * If a CPU or PCH DP output is attached to an eDP panel, this function
  90  * will return true, and false otherwise.
  91  */
  92 static bool is_edp(struct intel_dp *intel_dp)
  93 {
  94         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  95
  96         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  97 }
  98
  99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 100 {
 101         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 102
 103         return intel_dig_port->base.base.dev;
 104 }
 105
 106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 107 {
 108         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 109 }
 110
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
 113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 114
 115 static int
 116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 117 {
 118         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 119         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 120
 121         switch (max_link_bw) {
 122         case DP_LINK_BW_1_62:
 123         case DP_LINK_BW_2_7:
 124                 break;
 125         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 126                 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
 127                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 128                         max_link_bw = DP_LINK_BW_5_4;
 129                 else
 130                         max_link_bw = DP_LINK_BW_2_7;
 131                 break;
 132         default:
 133                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 134                      max_link_bw);
 135                 max_link_bw = DP_LINK_BW_1_62;
 136                 break;
 137         }
 138         return max_link_bw;
 139 }
 140
 141 /*
 142  * The units on the numbers in the next two are... bizarre.  Examples will
 143  * make it clearer; this one parallels an example in the eDP spec.
 144  *
 145  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 146  *
 147  *     270000 * 1 * 8 / 10 == 216000
 148  *
 149  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 150  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 151  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 152  * 119000.  At 18bpp that's 2142000 kilobits per second.
 153  *
 154  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 155  * get the result in decakilobits instead of kilobits.
 156  */
 157
 158 static int
 159 intel_dp_link_required(int pixel_clock, int bpp)
 160 {
 161         return (pixel_clock * bpp + 9) / 10;
 162 }
 163
 164 static int
 165 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 166 {
 167         return (max_link_clock * max_lanes * 8) / 10;
 168 }
 169
 170 static enum drm_mode_status
 171 intel_dp_mode_valid(struct drm_connector *connector,
 172                     struct drm_display_mode *mode)
 173 {
 174         struct intel_dp *intel_dp = intel_attached_dp(connector);
 175         struct intel_connector *intel_connector = to_intel_connector(connector);
 176         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 177         int target_clock = mode->clock;
 178         int max_rate, mode_rate, max_lanes, max_link_clock;
 179
 180         if (is_edp(intel_dp) && fixed_mode) {
 181                 if (mode->hdisplay > fixed_mode->hdisplay)
 182                         return MODE_PANEL;
 183
 184                 if (mode->vdisplay > fixed_mode->vdisplay)
 185                         return MODE_PANEL;
 186
 187                 target_clock = fixed_mode->clock;
 188         }
 189
 190         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 191         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 192
 193         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 194         mode_rate = intel_dp_link_required(target_clock, 18);
 195
 196         if (mode_rate > max_rate)
 197                 return MODE_CLOCK_HIGH;
 198
 199         if (mode->clock < 10000)
 200                 return MODE_CLOCK_LOW;
 201
 202         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 203                 return MODE_H_ILLEGAL;
 204
 205         return MODE_OK;
 206 }
 207
 208 static uint32_t
 209 pack_aux(uint8_t *src, int src_bytes)
 210 {
 211         int     i;
 212         uint32_t v = 0;
 213
 214         if (src_bytes > 4)
 215                 src_bytes = 4;
 216         for (i = 0; i < src_bytes; i++)
 217                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 218         return v;
 219 }
 220
 221 static void
 222 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 223 {
 224         int i;
 225         if (dst_bytes > 4)
 226                 dst_bytes = 4;
 227         for (i = 0; i < dst_bytes; i++)
 228                 dst[i] = src >> ((3-i) * 8);
 229 }
 230
 231 /* hrawclock is 1/4 the FSB frequency */
 232 static int
 233 intel_hrawclk(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         uint32_t clkcfg;
 237
 238         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 239         if (IS_VALLEYVIEW(dev))
 240                 return 200;
 241
 242         clkcfg = I915_READ(CLKCFG);
 243         switch (clkcfg & CLKCFG_FSB_MASK) {
 244         case CLKCFG_FSB_400:
 245                 return 100;
 246         case CLKCFG_FSB_533:
 247                 return 133;
 248         case CLKCFG_FSB_667:
 249                 return 166;
 250         case CLKCFG_FSB_800:
 251                 return 200;
 252         case CLKCFG_FSB_1067:
 253                 return 266;
 254         case CLKCFG_FSB_1333:
 255                 return 333;
 256         /* these two are just a guess; one of them might be right */
 257         case CLKCFG_FSB_1600:
 258         case CLKCFG_FSB_1600_ALT:
 259                 return 400;
 260         default:
 261                 return 133;
 262         }
 263 }
 264
 265 static void
 266 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 267                                     struct intel_dp *intel_dp,
 268                                     struct edp_power_seq *out);
 269 static void
 270 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 271                                               struct intel_dp *intel_dp,
 272                                               struct edp_power_seq *out);
 273
 274 static enum pipe
 275 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 276 {
 277         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 278         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 279         struct drm_device *dev = intel_dig_port->base.base.dev;
 280         struct drm_i915_private *dev_priv = dev->dev_private;
 281         enum port port = intel_dig_port->port;
 282         enum pipe pipe;
 283
 284         /* modeset should have pipe */
 285         if (crtc)
 286                 return to_intel_crtc(crtc)->pipe;
 287
 288         /* init time, try to find a pipe with this port selected */
 289         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 290                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 291                         PANEL_PORT_SELECT_MASK;
 292                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 293                         return pipe;
 294                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 295                         return pipe;
 296         }
 297
 298         /* shrug */
 299         return PIPE_A;
 300 }
 301
 302 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 303 {
 304         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 305
 306         if (HAS_PCH_SPLIT(dev))
 307                 return PCH_PP_CONTROL;
 308         else
 309                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 310 }
 311
 312 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 313 {
 314         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 315
 316         if (HAS_PCH_SPLIT(dev))
 317                 return PCH_PP_STATUS;
 318         else
 319                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 320 }
 321
 322 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 323 {
 324         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 328 }
 329
 330 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 331 {
 332         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 333         struct drm_i915_private *dev_priv = dev->dev_private;
 334         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 335         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 336         enum intel_display_power_domain power_domain;
 337
 338         power_domain = intel_display_port_power_domain(intel_encoder);
 339         return intel_display_power_enabled(dev_priv, power_domain) &&
 340                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 341 }
 342
 343 static void
 344 intel_dp_check_edp(struct intel_dp *intel_dp)
 345 {
 346         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348
 349         if (!is_edp(intel_dp))
 350                 return;
 351
 352         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 353                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 354                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 355                               I915_READ(_pp_stat_reg(intel_dp)),
 356                               I915_READ(_pp_ctrl_reg(intel_dp)));
 357         }
 358 }
 359
 360 static uint32_t
 361 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 362 {
 363         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 364         struct drm_device *dev = intel_dig_port->base.base.dev;
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 367         uint32_t status;
 368         bool done;
 369
 370 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 371         if (has_aux_irq)
 372                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 373                                           msecs_to_jiffies_timeout(10));
 374         else
 375                 done = wait_for_atomic(C, 10) == 0;
 376         if (!done)
 377                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 378                           has_aux_irq);
 379 #undef C
 380
 381         return status;
 382 }
 383
 384 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 385 {
 386         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 387         struct drm_device *dev = intel_dig_port->base.base.dev;
 388
 389         /*
 390          * The clock divider is based off the hrawclk, and would like to run at
 391          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 392          */
 393         return index ? 0 : intel_hrawclk(dev) / 2;
 394 }
 395
 396 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 397 {
 398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 399         struct drm_device *dev = intel_dig_port->base.base.dev;
 400
 401         if (index)
 402                 return 0;
 403
 404         if (intel_dig_port->port == PORT_A) {
 405                 if (IS_GEN6(dev) || IS_GEN7(dev))
 406                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 407                 else
 408                         return 225; /* eDP input clock at 450Mhz */
 409         } else {
 410                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 411         }
 412 }
 413
 414 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 415 {
 416         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 417         struct drm_device *dev = intel_dig_port->base.base.dev;
 418         struct drm_i915_private *dev_priv = dev->dev_private;
 419
 420         if (intel_dig_port->port == PORT_A) {
 421                 if (index)
 422                         return 0;
 423                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 424         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 425                 /* Workaround for non-ULT HSW */
 426                 switch (index) {
 427                 case 0: return 63;
 428                 case 1: return 72;
 429                 default: return 0;
 430                 }
 431         } else  {
 432                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 433         }
 434 }
 435
 436 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 437 {
 438         return index ? 0 : 100;
 439 }
 440
 441 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 442                                       bool has_aux_irq,
 443                                       int send_bytes,
 444                                       uint32_t aux_clock_divider)
 445 {
 446         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 447         struct drm_device *dev = intel_dig_port->base.base.dev;
 448         uint32_t precharge, timeout;
 449
 450         if (IS_GEN6(dev))
 451                 precharge = 3;
 452         else
 453                 precharge = 5;
 454
 455         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 456                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 457         else
 458                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 459
 460         return DP_AUX_CH_CTL_SEND_BUSY |
 461                DP_AUX_CH_CTL_DONE |
 462                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 463                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 464                timeout |
 465                DP_AUX_CH_CTL_RECEIVE_ERROR |
 466                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 467                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 468                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 469 }
 470
 471 static int
 472 intel_dp_aux_ch(struct intel_dp *intel_dp,
 473                 uint8_t *send, int send_bytes,
 474                 uint8_t *recv, int recv_size)
 475 {
 476         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 477         struct drm_device *dev = intel_dig_port->base.base.dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 480         uint32_t ch_data = ch_ctl + 4;
 481         uint32_t aux_clock_divider;
 482         int i, ret, recv_bytes;
 483         uint32_t status;
 484         int try, clock = 0;
 485         bool has_aux_irq = HAS_AUX_IRQ(dev);
 486         bool vdd;
 487
 488         vdd = _edp_panel_vdd_on(intel_dp);
 489
 490         /* dp aux is extremely sensitive to irq latency, hence request the
 491          * lowest possible wakeup latency and so prevent the cpu from going into
 492          * deep sleep states.
 493          */
 494         pm_qos_update_request(&dev_priv->pm_qos, 0);
 495
 496         intel_dp_check_edp(intel_dp);
 497
 498         intel_aux_display_runtime_get(dev_priv);
 499
 500         /* Try to wait for any previous AUX channel activity */
 501         for (try = 0; try < 3; try++) {
 502                 status = I915_READ_NOTRACE(ch_ctl);
 503                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 504                         break;
 505                 msleep(1);
 506         }
 507
 508         if (try == 3) {
 509                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 510                      I915_READ(ch_ctl));
 511                 ret = -EBUSY;
 512                 goto out;
 513         }
 514
 515         /* Only 5 data registers! */
 516         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 517                 ret = -E2BIG;
 518                 goto out;
 519         }
 520
 521         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 522                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 523                                                           has_aux_irq,
 524                                                           send_bytes,
 525                                                           aux_clock_divider);
 526
 527                 /* Must try at least 3 times according to DP spec */
 528                 for (try = 0; try < 5; try++) {
 529                         /* Load the send data into the aux channel data registers */
 530                         for (i = 0; i < send_bytes; i += 4)
 531                                 I915_WRITE(ch_data + i,
 532                                            pack_aux(send + i, send_bytes - i));
 533
 534                         /* Send the command and wait for it to complete */
 535                         I915_WRITE(ch_ctl, send_ctl);
 536
 537                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 538
 539                         /* Clear done status and any errors */
 540                         I915_WRITE(ch_ctl,
 541                                    status |
 542                                    DP_AUX_CH_CTL_DONE |
 543                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 544                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 545
 546                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 547                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 548                                 continue;
 549                         if (status & DP_AUX_CH_CTL_DONE)
 550                                 break;
 551                 }
 552                 if (status & DP_AUX_CH_CTL_DONE)
 553                         break;
 554         }
 555
 556         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 557                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 558                 ret = -EBUSY;
 559                 goto out;
 560         }
 561
 562         /* Check for timeout or receive error.
 563          * Timeouts occur when the sink is not connected
 564          */
 565         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 566                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 567                 ret = -EIO;
 568                 goto out;
 569         }
 570
 571         /* Timeouts occur when the device isn't connected, so they're
 572          * "normal" -- don't fill the kernel log with these */
 573         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 574                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 575                 ret = -ETIMEDOUT;
 576                 goto out;
 577         }
 578
 579         /* Unload any bytes sent back from the other side */
 580         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 581                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 582         if (recv_bytes > recv_size)
 583                 recv_bytes = recv_size;
 584
 585         for (i = 0; i < recv_bytes; i += 4)
 586                 unpack_aux(I915_READ(ch_data + i),
 587                            recv + i, recv_bytes - i);
 588
 589         ret = recv_bytes;
 590 out:
 591         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 592         intel_aux_display_runtime_put(dev_priv);
 593
 594         if (vdd)
 595                 edp_panel_vdd_off(intel_dp, false);
 596
 597         return ret;
 598 }
 599
 600 #define BARE_ADDRESS_SIZE       3
 601 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 602 static ssize_t
 603 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 604 {
 605         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 606         uint8_t txbuf[20], rxbuf[20];
 607         size_t txsize, rxsize;
 608         int ret;
 609
 610         txbuf[0] = msg->request << 4;
 611         txbuf[1] = msg->address >> 8;
 612         txbuf[2] = msg->address & 0xff;
 613         txbuf[3] = msg->size - 1;
 614
 615         switch (msg->request & ~DP_AUX_I2C_MOT) {
 616         case DP_AUX_NATIVE_WRITE:
 617         case DP_AUX_I2C_WRITE:
 618                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 619                 rxsize = 1;
 620
 621                 if (WARN_ON(txsize > 20))
 622                         return -E2BIG;
 623
 624                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 625
 626                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 627                 if (ret > 0) {
 628                         msg->reply = rxbuf[0] >> 4;
 629
 630                         /* Return payload size. */
 631                         ret = msg->size;
 632                 }
 633                 break;
 634
 635         case DP_AUX_NATIVE_READ:
 636         case DP_AUX_I2C_READ:
 637                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 638                 rxsize = msg->size + 1;
 639
 640                 if (WARN_ON(rxsize > 20))
 641                         return -E2BIG;
 642
 643                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 644                 if (ret > 0) {
 645                         msg->reply = rxbuf[0] >> 4;
 646                         /*
 647                          * Assume happy day, and copy the data. The caller is
 648                          * expected to check msg->reply before touching it.
 649                          *
 650                          * Return payload size.
 651                          */
 652                         ret--;
 653                         memcpy(msg->buffer, rxbuf + 1, ret);
 654                 }
 655                 break;
 656
 657         default:
 658                 ret = -EINVAL;
 659                 break;
 660         }
 661
 662         return ret;
 663 }
 664
 665 static void
 666 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 667 {
 668         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 670         enum port port = intel_dig_port->port;
 671         const char *name = NULL;
 672         int ret;
 673
 674         switch (port) {
 675         case PORT_A:
 676                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 677                 name = "DPDDC-A";
 678                 break;
 679         case PORT_B:
 680                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 681                 name = "DPDDC-B";
 682                 break;
 683         case PORT_C:
 684                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 685                 name = "DPDDC-C";
 686                 break;
 687         case PORT_D:
 688                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 689                 name = "DPDDC-D";
 690                 break;
 691         default:
 692                 BUG();
 693         }
 694
 695         if (!HAS_DDI(dev))
 696                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 697
 698         intel_dp->aux.name = name;
 699         intel_dp->aux.dev = dev->dev;
 700         intel_dp->aux.transfer = intel_dp_aux_transfer;
 701
 702         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 703                       connector->base.kdev->kobj.name);
 704
 705         ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
 706         if (ret < 0) {
 707                 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
 708                           name, ret);
 709                 return;
 710         }
 711
 712         ret = sysfs_create_link(&connector->base.kdev->kobj,
 713                                 &intel_dp->aux.ddc.dev.kobj,
 714                                 intel_dp->aux.ddc.dev.kobj.name);
 715         if (ret < 0) {
 716                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 717                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
 718         }
 719 }
 720
 721 static void
 722 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 723 {
 724         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 725
 726         sysfs_remove_link(&intel_connector->base.kdev->kobj,
 727                           intel_dp->aux.ddc.dev.kobj.name);
 728         intel_connector_unregister(intel_connector);
 729 }
 730
 731 static void
 732 intel_dp_set_clock(struct intel_encoder *encoder,
 733                    struct intel_crtc_config *pipe_config, int link_bw)
 734 {
 735         struct drm_device *dev = encoder->base.dev;
 736         const struct dp_link_dpll *divisor = NULL;
 737         int i, count = 0;
 738
 739         if (IS_G4X(dev)) {
 740                 divisor = gen4_dpll;
 741                 count = ARRAY_SIZE(gen4_dpll);
 742         } else if (IS_HASWELL(dev)) {
 743                 /* Haswell has special-purpose DP DDI clocks. */
 744         } else if (HAS_PCH_SPLIT(dev)) {
 745                 divisor = pch_dpll;
 746                 count = ARRAY_SIZE(pch_dpll);
 747         } else if (IS_CHERRYVIEW(dev)) {
 748                 divisor = chv_dpll;
 749                 count = ARRAY_SIZE(chv_dpll);
 750         } else if (IS_VALLEYVIEW(dev)) {
 751                 divisor = vlv_dpll;
 752                 count = ARRAY_SIZE(vlv_dpll);
 753         }
 754
 755         if (divisor && count) {
 756                 for (i = 0; i < count; i++) {
 757                         if (link_bw == divisor[i].link_bw) {
 758                                 pipe_config->dpll = divisor[i].dpll;
 759                                 pipe_config->clock_set = true;
 760                                 break;
 761                         }
 762                 }
 763         }
 764 }
 765
 766 static void
 767 intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
 768 {
 769         struct drm_device *dev = crtc->base.dev;
 770         struct drm_i915_private *dev_priv = dev->dev_private;
 771         enum transcoder transcoder = crtc->config.cpu_transcoder;
 772
 773         I915_WRITE(PIPE_DATA_M2(transcoder),
 774                 TU_SIZE(m_n->tu) | m_n->gmch_m);
 775         I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
 776         I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
 777         I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
 778 }
 779
 780 bool
 781 intel_dp_compute_config(struct intel_encoder *encoder,
 782                         struct intel_crtc_config *pipe_config)
 783 {
 784         struct drm_device *dev = encoder->base.dev;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 787         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 788         enum port port = dp_to_dig_port(intel_dp)->port;
 789         struct intel_crtc *intel_crtc = encoder->new_crtc;
 790         struct intel_connector *intel_connector = intel_dp->attached_connector;
 791         int lane_count, clock;
 792         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 793         /* Conveniently, the link BW constants become indices with a shift...*/
 794         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 795         int bpp, mode_rate;
 796         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 797         int link_avail, link_clock;
 798
 799         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 800                 pipe_config->has_pch_encoder = true;
 801
 802         pipe_config->has_dp_encoder = true;
 803
 804         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 805                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 806                                        adjusted_mode);
 807                 if (!HAS_PCH_SPLIT(dev))
 808                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 809                                                  intel_connector->panel.fitting_mode);
 810                 else
 811                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 812                                                 intel_connector->panel.fitting_mode);
 813         }
 814
 815         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 816                 return false;
 817
 818         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 819                       "max bw %02x pixel clock %iKHz\n",
 820                       max_lane_count, bws[max_clock],
 821                       adjusted_mode->crtc_clock);
 822
 823         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 824          * bpc in between. */
 825         bpp = pipe_config->pipe_bpp;
 826         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 827             dev_priv->vbt.edp_bpp < bpp) {
 828                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 829                               dev_priv->vbt.edp_bpp);
 830                 bpp = dev_priv->vbt.edp_bpp;
 831         }
 832
 833         for (; bpp >= 6*3; bpp -= 2*3) {
 834                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 835                                                    bpp);
 836
 837                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 838                         for (clock = 0; clock <= max_clock; clock++) {
 839                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 840                                 link_avail = intel_dp_max_data_rate(link_clock,
 841                                                                     lane_count);
 842
 843                                 if (mode_rate <= link_avail) {
 844                                         goto found;
 845                                 }
 846                         }
 847                 }
 848         }
 849
 850         return false;
 851
 852 found:
 853         if (intel_dp->color_range_auto) {
 854                 /*
 855                  * See:
 856                  * CEA-861-E - 5.1 Default Encoding Parameters
 857                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 858                  */
 859                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 860                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 861                 else
 862                         intel_dp->color_range = 0;
 863         }
 864
 865         if (intel_dp->color_range)
 866                 pipe_config->limited_color_range = true;
 867
 868         intel_dp->link_bw = bws[clock];
 869         intel_dp->lane_count = lane_count;
 870         pipe_config->pipe_bpp = bpp;
 871         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 872
 873         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 874                       intel_dp->link_bw, intel_dp->lane_count,
 875                       pipe_config->port_clock, bpp);
 876         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 877                       mode_rate, link_avail);
 878
 879         intel_link_compute_m_n(bpp, lane_count,
 880                                adjusted_mode->crtc_clock,
 881                                pipe_config->port_clock,
 882                                &pipe_config->dp_m_n);
 883
 884         if (intel_connector->panel.downclock_mode != NULL &&
 885                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 886                         intel_link_compute_m_n(bpp, lane_count,
 887                                 intel_connector->panel.downclock_mode->clock,
 888                                 pipe_config->port_clock,
 889                                 &pipe_config->dp_m2_n2);
 890         }
 891
 892         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 893
 894         return true;
 895 }
 896
 897 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 898 {
 899         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 900         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 901         struct drm_device *dev = crtc->base.dev;
 902         struct drm_i915_private *dev_priv = dev->dev_private;
 903         u32 dpa_ctl;
 904
 905         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 906         dpa_ctl = I915_READ(DP_A);
 907         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 908
 909         if (crtc->config.port_clock == 162000) {
 910                 /* For a long time we've carried around a ILK-DevA w/a for the
 911                  * 160MHz clock. If we're really unlucky, it's still required.
 912                  */
 913                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 914                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 915                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 916         } else {
 917                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 918                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 919         }
 920
 921         I915_WRITE(DP_A, dpa_ctl);
 922
 923         POSTING_READ(DP_A);
 924         udelay(500);
 925 }
 926
 927 static void intel_dp_mode_set(struct intel_encoder *encoder)
 928 {
 929         struct drm_device *dev = encoder->base.dev;
 930         struct drm_i915_private *dev_priv = dev->dev_private;
 931         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 932         enum port port = dp_to_dig_port(intel_dp)->port;
 933         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 934         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 935
 936         /*
 937          * There are four kinds of DP registers:
 938          *
 939          *      IBX PCH
 940          *      SNB CPU
 941          *      IVB CPU
 942          *      CPT PCH
 943          *
 944          * IBX PCH and CPU are the same for almost everything,
 945          * except that the CPU DP PLL is configured in this
 946          * register
 947          *
 948          * CPT PCH is quite different, having many bits moved
 949          * to the TRANS_DP_CTL register instead. That
 950          * configuration happens (oddly) in ironlake_pch_enable
 951          */
 952
 953         /* Preserve the BIOS-computed detected bit. This is
 954          * supposed to be read-only.
 955          */
 956         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 957
 958         /* Handle DP bits in common between all three register formats */
 959         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 960         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 961
 962         if (intel_dp->has_audio) {
 963                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 964                                  pipe_name(crtc->pipe));
 965                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 966                 intel_write_eld(&encoder->base, adjusted_mode);
 967         }
 968
 969         /* Split out the IBX/CPU vs CPT settings */
 970
 971         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 972                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 973                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 974                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 975                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 976                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 977
 978                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 979                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 980
 981                 intel_dp->DP |= crtc->pipe << 29;
 982         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 983                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 984                         intel_dp->DP |= intel_dp->color_range;
 985
 986                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 987                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 988                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 989                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 990                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 991
 992                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 993                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 994
 995                 if (crtc->pipe == 1)
 996                         intel_dp->DP |= DP_PIPEB_SELECT;
 997         } else {
 998                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 999         }
1000
1001         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1002                 ironlake_set_pll_cpu_edp(intel_dp);
1003 }
1004
1005 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1006 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1007
1008 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1009 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1010
1011 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1013
1014 static void wait_panel_status(struct intel_dp *intel_dp,
1015                                        u32 mask,
1016                                        u32 value)
1017 {
1018         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1019         struct drm_i915_private *dev_priv = dev->dev_private;
1020         u32 pp_stat_reg, pp_ctrl_reg;
1021
1022         pp_stat_reg = _pp_stat_reg(intel_dp);
1023         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1024
1025         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1026                         mask, value,
1027                         I915_READ(pp_stat_reg),
1028                         I915_READ(pp_ctrl_reg));
1029
1030         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1031                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1032                                 I915_READ(pp_stat_reg),
1033                                 I915_READ(pp_ctrl_reg));
1034         }
1035
1036         DRM_DEBUG_KMS("Wait complete\n");
1037 }
1038
1039 static void wait_panel_on(struct intel_dp *intel_dp)
1040 {
1041         DRM_DEBUG_KMS("Wait for panel power on\n");
1042         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1043 }
1044
1045 static void wait_panel_off(struct intel_dp *intel_dp)
1046 {
1047         DRM_DEBUG_KMS("Wait for panel power off time\n");
1048         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1049 }
1050
1051 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1052 {
1053         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1054
1055         /* When we disable the VDD override bit last we have to do the manual
1056          * wait. */
1057         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1058                                        intel_dp->panel_power_cycle_delay);
1059
1060         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 }
1062
1063 static void wait_backlight_on(struct intel_dp *intel_dp)
1064 {
1065         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1066                                        intel_dp->backlight_on_delay);
1067 }
1068
1069 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1070 {
1071         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1072                                        intel_dp->backlight_off_delay);
1073 }
1074
1075 /* Read the current pp_control value, unlocking the register if it
1076  * is locked
1077  */
1078
1079 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1080 {
1081         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1082         struct drm_i915_private *dev_priv = dev->dev_private;
1083         u32 control;
1084
1085         control = I915_READ(_pp_ctrl_reg(intel_dp));
1086         control &= ~PANEL_UNLOCK_MASK;
1087         control |= PANEL_UNLOCK_REGS;
1088         return control;
1089 }
1090
1091 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1092 {
1093         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1094         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1095         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097         enum intel_display_power_domain power_domain;
1098         u32 pp;
1099         u32 pp_stat_reg, pp_ctrl_reg;
1100         bool need_to_disable = !intel_dp->want_panel_vdd;
1101
1102         if (!is_edp(intel_dp))
1103                 return false;
1104
1105         intel_dp->want_panel_vdd = true;
1106
1107         if (edp_have_panel_vdd(intel_dp))
1108                 return need_to_disable;
1109
1110         power_domain = intel_display_port_power_domain(intel_encoder);
1111         intel_display_power_get(dev_priv, power_domain);
1112
1113         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1114
1115         if (!edp_have_panel_power(intel_dp))
1116                 wait_panel_power_cycle(intel_dp);
1117
1118         pp = ironlake_get_pp_control(intel_dp);
1119         pp |= EDP_FORCE_VDD;
1120
1121         pp_stat_reg = _pp_stat_reg(intel_dp);
1122         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1123
1124         I915_WRITE(pp_ctrl_reg, pp);
1125         POSTING_READ(pp_ctrl_reg);
1126         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1127                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1128         /*
1129          * If the panel wasn't on, delay before accessing aux channel
1130          */
1131         if (!edp_have_panel_power(intel_dp)) {
1132                 DRM_DEBUG_KMS("eDP was not running\n");
1133                 msleep(intel_dp->panel_power_up_delay);
1134         }
1135
1136         return need_to_disable;
1137 }
1138
1139 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1140 {
1141         if (is_edp(intel_dp)) {
1142                 bool vdd = _edp_panel_vdd_on(intel_dp);
1143
1144                 WARN(!vdd, "eDP VDD already requested on\n");
1145         }
1146 }
1147
1148 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1149 {
1150         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151         struct drm_i915_private *dev_priv = dev->dev_private;
1152         u32 pp;
1153         u32 pp_stat_reg, pp_ctrl_reg;
1154
1155         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1156
1157         if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1158                 struct intel_digital_port *intel_dig_port =
1159                                                 dp_to_dig_port(intel_dp);
1160                 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1161                 enum intel_display_power_domain power_domain;
1162
1163                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1164
1165                 pp = ironlake_get_pp_control(intel_dp);
1166                 pp &= ~EDP_FORCE_VDD;
1167
1168                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1169                 pp_stat_reg = _pp_stat_reg(intel_dp);
1170
1171                 I915_WRITE(pp_ctrl_reg, pp);
1172                 POSTING_READ(pp_ctrl_reg);
1173
1174                 /* Make sure sequencer is idle before allowing subsequent activity */
1175                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1176                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1177
1178                 if ((pp & POWER_TARGET_ON) == 0)
1179                         intel_dp->last_power_cycle = jiffies;
1180
1181                 power_domain = intel_display_port_power_domain(intel_encoder);
1182                 intel_display_power_put(dev_priv, power_domain);
1183         }
1184 }
1185
1186 static void edp_panel_vdd_work(struct work_struct *__work)
1187 {
1188         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1189                                                  struct intel_dp, panel_vdd_work);
1190         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1191
1192         mutex_lock(&dev->mode_config.mutex);
1193         edp_panel_vdd_off_sync(intel_dp);
1194         mutex_unlock(&dev->mode_config.mutex);
1195 }
1196
1197 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1198 {
1199         if (!is_edp(intel_dp))
1200                 return;
1201
1202         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1203
1204         intel_dp->want_panel_vdd = false;
1205
1206         if (sync) {
1207                 edp_panel_vdd_off_sync(intel_dp);
1208         } else {
1209                 /*
1210                  * Queue the timer to fire a long
1211                  * time from now (relative to the power down delay)
1212                  * to keep the panel power up across a sequence of operations
1213                  */
1214                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1215                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1216         }
1217 }
1218
1219 void intel_edp_panel_on(struct intel_dp *intel_dp)
1220 {
1221         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         u32 pp;
1224         u32 pp_ctrl_reg;
1225
1226         if (!is_edp(intel_dp))
1227                 return;
1228
1229         DRM_DEBUG_KMS("Turn eDP power on\n");
1230
1231         if (edp_have_panel_power(intel_dp)) {
1232                 DRM_DEBUG_KMS("eDP power already on\n");
1233                 return;
1234         }
1235
1236         wait_panel_power_cycle(intel_dp);
1237
1238         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1239         pp = ironlake_get_pp_control(intel_dp);
1240         if (IS_GEN5(dev)) {
1241                 /* ILK workaround: disable reset around power sequence */
1242                 pp &= ~PANEL_POWER_RESET;
1243                 I915_WRITE(pp_ctrl_reg, pp);
1244                 POSTING_READ(pp_ctrl_reg);
1245         }
1246
1247         pp |= POWER_TARGET_ON;
1248         if (!IS_GEN5(dev))
1249                 pp |= PANEL_POWER_RESET;
1250
1251         I915_WRITE(pp_ctrl_reg, pp);
1252         POSTING_READ(pp_ctrl_reg);
1253
1254         wait_panel_on(intel_dp);
1255         intel_dp->last_power_on = jiffies;
1256
1257         if (IS_GEN5(dev)) {
1258                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1259                 I915_WRITE(pp_ctrl_reg, pp);
1260                 POSTING_READ(pp_ctrl_reg);
1261         }
1262 }
1263
1264 void intel_edp_panel_off(struct intel_dp *intel_dp)
1265 {
1266         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1267         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1268         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1269         struct drm_i915_private *dev_priv = dev->dev_private;
1270         enum intel_display_power_domain power_domain;
1271         u32 pp;
1272         u32 pp_ctrl_reg;
1273
1274         if (!is_edp(intel_dp))
1275                 return;
1276
1277         DRM_DEBUG_KMS("Turn eDP power off\n");
1278
1279         edp_wait_backlight_off(intel_dp);
1280
1281         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1282
1283         pp = ironlake_get_pp_control(intel_dp);
1284         /* We need to switch off panel power _and_ force vdd, for otherwise some
1285          * panels get very unhappy and cease to work. */
1286         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1287                 EDP_BLC_ENABLE);
1288
1289         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1290
1291         intel_dp->want_panel_vdd = false;
1292
1293         I915_WRITE(pp_ctrl_reg, pp);
1294         POSTING_READ(pp_ctrl_reg);
1295
1296         intel_dp->last_power_cycle = jiffies;
1297         wait_panel_off(intel_dp);
1298
1299         /* We got a reference when we enabled the VDD. */
1300         power_domain = intel_display_port_power_domain(intel_encoder);
1301         intel_display_power_put(dev_priv, power_domain);
1302 }
1303
1304 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1305 {
1306         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307         struct drm_device *dev = intel_dig_port->base.base.dev;
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         u32 pp;
1310         u32 pp_ctrl_reg;
1311
1312         if (!is_edp(intel_dp))
1313                 return;
1314
1315         DRM_DEBUG_KMS("\n");
1316         /*
1317          * If we enable the backlight right away following a panel power
1318          * on, we may see slight flicker as the panel syncs with the eDP
1319          * link.  So delay a bit to make sure the image is solid before
1320          * allowing it to appear.
1321          */
1322         wait_backlight_on(intel_dp);
1323         pp = ironlake_get_pp_control(intel_dp);
1324         pp |= EDP_BLC_ENABLE;
1325
1326         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1327
1328         I915_WRITE(pp_ctrl_reg, pp);
1329         POSTING_READ(pp_ctrl_reg);
1330
1331         intel_panel_enable_backlight(intel_dp->attached_connector);
1332 }
1333
1334 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1335 {
1336         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1337         struct drm_i915_private *dev_priv = dev->dev_private;
1338         u32 pp;
1339         u32 pp_ctrl_reg;
1340
1341         if (!is_edp(intel_dp))
1342                 return;
1343
1344         intel_panel_disable_backlight(intel_dp->attached_connector);
1345
1346         DRM_DEBUG_KMS("\n");
1347         pp = ironlake_get_pp_control(intel_dp);
1348         pp &= ~EDP_BLC_ENABLE;
1349
1350         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1351
1352         I915_WRITE(pp_ctrl_reg, pp);
1353         POSTING_READ(pp_ctrl_reg);
1354         intel_dp->last_backlight_off = jiffies;
1355 }
1356
1357 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1358 {
1359         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1360         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1361         struct drm_device *dev = crtc->dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         u32 dpa_ctl;
1364
1365         assert_pipe_disabled(dev_priv,
1366                              to_intel_crtc(crtc)->pipe);
1367
1368         DRM_DEBUG_KMS("\n");
1369         dpa_ctl = I915_READ(DP_A);
1370         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1371         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1372
1373         /* We don't adjust intel_dp->DP while tearing down the link, to
1374          * facilitate link retraining (e.g. after hotplug). Hence clear all
1375          * enable bits here to ensure that we don't enable too much. */
1376         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1377         intel_dp->DP |= DP_PLL_ENABLE;
1378         I915_WRITE(DP_A, intel_dp->DP);
1379         POSTING_READ(DP_A);
1380         udelay(200);
1381 }
1382
1383 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1384 {
1385         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1386         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1387         struct drm_device *dev = crtc->dev;
1388         struct drm_i915_private *dev_priv = dev->dev_private;
1389         u32 dpa_ctl;
1390
1391         assert_pipe_disabled(dev_priv,
1392                              to_intel_crtc(crtc)->pipe);
1393
1394         dpa_ctl = I915_READ(DP_A);
1395         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1396              "dp pll off, should be on\n");
1397         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1398
1399         /* We can't rely on the value tracked for the DP register in
1400          * intel_dp->DP because link_down must not change that (otherwise link
1401          * re-training will fail. */
1402         dpa_ctl &= ~DP_PLL_ENABLE;
1403         I915_WRITE(DP_A, dpa_ctl);
1404         POSTING_READ(DP_A);
1405         udelay(200);
1406 }
1407
1408 /* If the sink supports it, try to set the power state appropriately */
1409 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1410 {
1411         int ret, i;
1412
1413         /* Should have a valid DPCD by this point */
1414         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1415                 return;
1416
1417         if (mode != DRM_MODE_DPMS_ON) {
1418                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1419                                          DP_SET_POWER_D3);
1420                 if (ret != 1)
1421                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1422         } else {
1423                 /*
1424                  * When turning on, we need to retry for 1ms to give the sink
1425                  * time to wake up.
1426                  */
1427                 for (i = 0; i < 3; i++) {
1428                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1429                                                  DP_SET_POWER_D0);
1430                         if (ret == 1)
1431                                 break;
1432                         msleep(1);
1433                 }
1434         }
1435 }
1436
1437 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1438                                   enum pipe *pipe)
1439 {
1440         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1441         enum port port = dp_to_dig_port(intel_dp)->port;
1442         struct drm_device *dev = encoder->base.dev;
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         enum intel_display_power_domain power_domain;
1445         u32 tmp;
1446
1447         power_domain = intel_display_port_power_domain(encoder);
1448         if (!intel_display_power_enabled(dev_priv, power_domain))
1449                 return false;
1450
1451         tmp = I915_READ(intel_dp->output_reg);
1452
1453         if (!(tmp & DP_PORT_EN))
1454                 return false;
1455
1456         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1457                 *pipe = PORT_TO_PIPE_CPT(tmp);
1458         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1459                 *pipe = PORT_TO_PIPE(tmp);
1460         } else {
1461                 u32 trans_sel;
1462                 u32 trans_dp;
1463                 int i;
1464
1465                 switch (intel_dp->output_reg) {
1466                 case PCH_DP_B:
1467                         trans_sel = TRANS_DP_PORT_SEL_B;
1468                         break;
1469                 case PCH_DP_C:
1470                         trans_sel = TRANS_DP_PORT_SEL_C;
1471                         break;
1472                 case PCH_DP_D:
1473                         trans_sel = TRANS_DP_PORT_SEL_D;
1474                         break;
1475                 default:
1476                         return true;
1477                 }
1478
1479                 for_each_pipe(i) {
1480                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1481                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1482                                 *pipe = i;
1483                                 return true;
1484                         }
1485                 }
1486
1487                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1488                               intel_dp->output_reg);
1489         }
1490
1491         return true;
1492 }
1493
1494 static void intel_dp_get_config(struct intel_encoder *encoder,
1495                                 struct intel_crtc_config *pipe_config)
1496 {
1497         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1498         u32 tmp, flags = 0;
1499         struct drm_device *dev = encoder->base.dev;
1500         struct drm_i915_private *dev_priv = dev->dev_private;
1501         enum port port = dp_to_dig_port(intel_dp)->port;
1502         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1503         int dotclock;
1504
1505         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1506                 tmp = I915_READ(intel_dp->output_reg);
1507                 if (tmp & DP_SYNC_HS_HIGH)
1508                         flags |= DRM_MODE_FLAG_PHSYNC;
1509                 else
1510                         flags |= DRM_MODE_FLAG_NHSYNC;
1511
1512                 if (tmp & DP_SYNC_VS_HIGH)
1513                         flags |= DRM_MODE_FLAG_PVSYNC;
1514                 else
1515                         flags |= DRM_MODE_FLAG_NVSYNC;
1516         } else {
1517                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1518                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1519                         flags |= DRM_MODE_FLAG_PHSYNC;
1520                 else
1521                         flags |= DRM_MODE_FLAG_NHSYNC;
1522
1523                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1524                         flags |= DRM_MODE_FLAG_PVSYNC;
1525                 else
1526                         flags |= DRM_MODE_FLAG_NVSYNC;
1527         }
1528
1529         pipe_config->adjusted_mode.flags |= flags;
1530
1531         pipe_config->has_dp_encoder = true;
1532
1533         intel_dp_get_m_n(crtc, pipe_config);
1534
1535         if (port == PORT_A) {
1536                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1537                         pipe_config->port_clock = 162000;
1538                 else
1539                         pipe_config->port_clock = 270000;
1540         }
1541
1542         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1543                                             &pipe_config->dp_m_n);
1544
1545         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1546                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1547
1548         pipe_config->adjusted_mode.crtc_clock = dotclock;
1549
1550         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1551             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1552                 /*
1553                  * This is a big fat ugly hack.
1554                  *
1555                  * Some machines in UEFI boot mode provide us a VBT that has 18
1556                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1557                  * unknown we fail to light up. Yet the same BIOS boots up with
1558                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1559                  * max, not what it tells us to use.
1560                  *
1561                  * Note: This will still be broken if the eDP panel is not lit
1562                  * up by the BIOS, and thus we can't get the mode at module
1563                  * load.
1564                  */
1565                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1566                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1567                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1568         }
1569 }
1570
1571 static bool is_edp_psr(struct drm_device *dev)
1572 {
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574
1575         return dev_priv->psr.sink_support;
1576 }
1577
1578 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582         if (!HAS_PSR(dev))
1583                 return false;
1584
1585         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1586 }
1587
1588 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1589                                     struct edp_vsc_psr *vsc_psr)
1590 {
1591         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1592         struct drm_device *dev = dig_port->base.base.dev;
1593         struct drm_i915_private *dev_priv = dev->dev_private;
1594         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1595         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1596         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1597         uint32_t *data = (uint32_t *) vsc_psr;
1598         unsigned int i;
1599
1600         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1601            the video DIP being updated before program video DIP data buffer
1602            registers for DIP being updated. */
1603         I915_WRITE(ctl_reg, 0);
1604         POSTING_READ(ctl_reg);
1605
1606         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1607                 if (i < sizeof(struct edp_vsc_psr))
1608                         I915_WRITE(data_reg + i, *data++);
1609                 else
1610                         I915_WRITE(data_reg + i, 0);
1611         }
1612
1613         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1614         POSTING_READ(ctl_reg);
1615 }
1616
1617 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1618 {
1619         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         struct edp_vsc_psr psr_vsc;
1622
1623         if (intel_dp->psr_setup_done)
1624                 return;
1625
1626         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1627         memset(&psr_vsc, 0, sizeof(psr_vsc));
1628         psr_vsc.sdp_header.HB0 = 0;
1629         psr_vsc.sdp_header.HB1 = 0x7;
1630         psr_vsc.sdp_header.HB2 = 0x2;
1631         psr_vsc.sdp_header.HB3 = 0x8;
1632         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1633
1634         /* Avoid continuous PSR exit by masking memup and hpd */
1635         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1636                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1637
1638         intel_dp->psr_setup_done = true;
1639 }
1640
1641 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1642 {
1643         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         uint32_t aux_clock_divider;
1646         int precharge = 0x3;
1647         int msg_size = 5;       /* Header(4) + Message(1) */
1648
1649         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1650
1651         /* Enable PSR in sink */
1652         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1653                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1654                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1655         else
1656                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1657                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1658
1659         /* Setup AUX registers */
1660         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1661         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1662         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1663                    DP_AUX_CH_CTL_TIME_OUT_400us |
1664                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1665                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1666                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1667 }
1668
1669 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1670 {
1671         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672         struct drm_i915_private *dev_priv = dev->dev_private;
1673         uint32_t max_sleep_time = 0x1f;
1674         uint32_t idle_frames = 1;
1675         uint32_t val = 0x0;
1676         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1677
1678         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1679                 val |= EDP_PSR_LINK_STANDBY;
1680                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1681                 val |= EDP_PSR_TP1_TIME_0us;
1682                 val |= EDP_PSR_SKIP_AUX_EXIT;
1683         } else
1684                 val |= EDP_PSR_LINK_DISABLE;
1685
1686         I915_WRITE(EDP_PSR_CTL(dev), val |
1687                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1688                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1689                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1690                    EDP_PSR_ENABLE);
1691 }
1692
1693 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1694 {
1695         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1696         struct drm_device *dev = dig_port->base.base.dev;
1697         struct drm_i915_private *dev_priv = dev->dev_private;
1698         struct drm_crtc *crtc = dig_port->base.base.crtc;
1699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1700         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1701         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1702
1703         dev_priv->psr.source_ok = false;
1704
1705         if (!HAS_PSR(dev)) {
1706                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1707                 return false;
1708         }
1709
1710         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1711             (dig_port->port != PORT_A)) {
1712                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1713                 return false;
1714         }
1715
1716         if (!i915.enable_psr) {
1717                 DRM_DEBUG_KMS("PSR disable by flag\n");
1718                 return false;
1719         }
1720
1721         crtc = dig_port->base.base.crtc;
1722         if (crtc == NULL) {
1723                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1724                 return false;
1725         }
1726
1727         intel_crtc = to_intel_crtc(crtc);
1728         if (!intel_crtc_active(crtc)) {
1729                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1730                 return false;
1731         }
1732
1733         obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1734         if (obj->tiling_mode != I915_TILING_X ||
1735             obj->fence_reg == I915_FENCE_REG_NONE) {
1736                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1737                 return false;
1738         }
1739
1740         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1741                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1742                 return false;
1743         }
1744
1745         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1746             S3D_ENABLE) {
1747                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1748                 return false;
1749         }
1750
1751         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1752                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1753                 return false;
1754         }
1755
1756         dev_priv->psr.source_ok = true;
1757         return true;
1758 }
1759
1760 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1761 {
1762         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1763
1764         if (!intel_edp_psr_match_conditions(intel_dp) ||
1765             intel_edp_is_psr_enabled(dev))
1766                 return;
1767
1768         /* Setup PSR once */
1769         intel_edp_psr_setup(intel_dp);
1770
1771         /* Enable PSR on the panel */
1772         intel_edp_psr_enable_sink(intel_dp);
1773
1774         /* Enable PSR on the host */
1775         intel_edp_psr_enable_source(intel_dp);
1776 }
1777
1778 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1779 {
1780         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1781
1782         if (intel_edp_psr_match_conditions(intel_dp) &&
1783             !intel_edp_is_psr_enabled(dev))
1784                 intel_edp_psr_do_enable(intel_dp);
1785 }
1786
1787 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1788 {
1789         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791
1792         if (!intel_edp_is_psr_enabled(dev))
1793                 return;
1794
1795         I915_WRITE(EDP_PSR_CTL(dev),
1796                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1797
1798         /* Wait till PSR is idle */
1799         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1800                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1801                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1802 }
1803
1804 void intel_edp_psr_update(struct drm_device *dev)
1805 {
1806         struct intel_encoder *encoder;
1807         struct intel_dp *intel_dp = NULL;
1808
1809         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1810                 if (encoder->type == INTEL_OUTPUT_EDP) {
1811                         intel_dp = enc_to_intel_dp(&encoder->base);
1812
1813                         if (!is_edp_psr(dev))
1814                                 return;
1815
1816                         if (!intel_edp_psr_match_conditions(intel_dp))
1817                                 intel_edp_psr_disable(intel_dp);
1818                         else
1819                                 if (!intel_edp_is_psr_enabled(dev))
1820                                         intel_edp_psr_do_enable(intel_dp);
1821                 }
1822 }
1823
1824 static void intel_disable_dp(struct intel_encoder *encoder)
1825 {
1826         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1827         enum port port = dp_to_dig_port(intel_dp)->port;
1828         struct drm_device *dev = encoder->base.dev;
1829
1830         /* Make sure the panel is off before trying to change the mode. But also
1831          * ensure that we have vdd while we switch off the panel. */
1832         intel_edp_panel_vdd_on(intel_dp);
1833         intel_edp_backlight_off(intel_dp);
1834         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1835         intel_edp_panel_off(intel_dp);
1836
1837         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1838         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1839                 intel_dp_link_down(intel_dp);
1840 }
1841
1842 static void g4x_post_disable_dp(struct intel_encoder *encoder)
1843 {
1844         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1845         enum port port = dp_to_dig_port(intel_dp)->port;
1846
1847         if (port != PORT_A)
1848                 return;
1849
1850         intel_dp_link_down(intel_dp);
1851         ironlake_edp_pll_off(intel_dp);
1852 }
1853
1854 static void vlv_post_disable_dp(struct intel_encoder *encoder)
1855 {
1856         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1857
1858         intel_dp_link_down(intel_dp);
1859 }
1860
1861 static void intel_enable_dp(struct intel_encoder *encoder)
1862 {
1863         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864         struct drm_device *dev = encoder->base.dev;
1865         struct drm_i915_private *dev_priv = dev->dev_private;
1866         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1867
1868         if (WARN_ON(dp_reg & DP_PORT_EN))
1869                 return;
1870
1871         intel_edp_panel_vdd_on(intel_dp);
1872         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1873         intel_dp_start_link_train(intel_dp);
1874         intel_edp_panel_on(intel_dp);
1875         edp_panel_vdd_off(intel_dp, true);
1876         intel_dp_complete_link_train(intel_dp);
1877         intel_dp_stop_link_train(intel_dp);
1878 }
1879
1880 static void g4x_enable_dp(struct intel_encoder *encoder)
1881 {
1882         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1883
1884         intel_enable_dp(encoder);
1885         intel_edp_backlight_on(intel_dp);
1886 }
1887
1888 static void vlv_enable_dp(struct intel_encoder *encoder)
1889 {
1890         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1891
1892         intel_edp_backlight_on(intel_dp);
1893 }
1894
1895 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1896 {
1897         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1898         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1899
1900         if (dport->port == PORT_A)
1901                 ironlake_edp_pll_on(intel_dp);
1902 }
1903
1904 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1905 {
1906         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1908         struct drm_device *dev = encoder->base.dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1911         enum dpio_channel port = vlv_dport_to_channel(dport);
1912         int pipe = intel_crtc->pipe;
1913         struct edp_power_seq power_seq;
1914         u32 val;
1915
1916         mutex_lock(&dev_priv->dpio_lock);
1917
1918         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1919         val = 0;
1920         if (pipe)
1921                 val |= (1<<21);
1922         else
1923                 val &= ~(1<<21);
1924         val |= 0x001000c4;
1925         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1926         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1927         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1928
1929         mutex_unlock(&dev_priv->dpio_lock);
1930
1931         if (is_edp(intel_dp)) {
1932                 /* init power sequencer on this pipe and port */
1933                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1934                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1935                                                               &power_seq);
1936         }
1937
1938         intel_enable_dp(encoder);
1939
1940         vlv_wait_port_ready(dev_priv, dport);
1941 }
1942
1943 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1944 {
1945         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1946         struct drm_device *dev = encoder->base.dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc =
1949                 to_intel_crtc(encoder->base.crtc);
1950         enum dpio_channel port = vlv_dport_to_channel(dport);
1951         int pipe = intel_crtc->pipe;
1952
1953         /* Program Tx lane resets to default */
1954         mutex_lock(&dev_priv->dpio_lock);
1955         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1956                          DPIO_PCS_TX_LANE2_RESET |
1957                          DPIO_PCS_TX_LANE1_RESET);
1958         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1959                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1960                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1961                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1962                                  DPIO_PCS_CLK_SOFT_RESET);
1963
1964         /* Fix up inter-pair skew failure */
1965         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1966         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1967         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1968         mutex_unlock(&dev_priv->dpio_lock);
1969 }
1970
1971 static void chv_pre_enable_dp(struct intel_encoder *encoder)
1972 {
1973         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1974         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1975         struct drm_device *dev = encoder->base.dev;
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         struct edp_power_seq power_seq;
1978         struct intel_crtc *intel_crtc =
1979                 to_intel_crtc(encoder->base.crtc);
1980         enum dpio_channel ch = vlv_dport_to_channel(dport);
1981         int pipe = intel_crtc->pipe;
1982         int data, i;
1983
1984         /* Program Tx lane latency optimal setting*/
1985         mutex_lock(&dev_priv->dpio_lock);
1986         for (i = 0; i < 4; i++) {
1987                 /* Set the latency optimal bit */
1988                 data = (i == 1) ? 0x0 : 0x6;
1989                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1990                                 data << DPIO_FRC_LATENCY_SHFIT);
1991
1992                 /* Set the upar bit */
1993                 data = (i == 1) ? 0x0 : 0x1;
1994                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1995                                 data << DPIO_UPAR_SHIFT);
1996         }
1997
1998         /* Data lane stagger programming */
1999         /* FIXME: Fix up value only after power analysis */
2000
2001         mutex_unlock(&dev_priv->dpio_lock);
2002
2003         if (is_edp(intel_dp)) {
2004                 /* init power sequencer on this pipe and port */
2005                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2006                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2007                                                               &power_seq);
2008         }
2009
2010         intel_enable_dp(encoder);
2011
2012         vlv_wait_port_ready(dev_priv, dport);
2013 }
2014
2015 /*
2016  * Native read with retry for link status and receiver capability reads for
2017  * cases where the sink may still be asleep.
2018  *
2019  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2020  * supposed to retry 3 times per the spec.
2021  */
2022 static ssize_t
2023 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2024                         void *buffer, size_t size)
2025 {
2026         ssize_t ret;
2027         int i;
2028
2029         for (i = 0; i < 3; i++) {
2030                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2031                 if (ret == size)
2032                         return ret;
2033                 msleep(1);
2034         }
2035
2036         return ret;
2037 }
2038
2039 /*
2040  * Fetch AUX CH registers 0x202 - 0x207 which contain
2041  * link status information
2042  */
2043 static bool
2044 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2045 {
2046         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2047                                        DP_LANE0_1_STATUS,
2048                                        link_status,
2049                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2050 }
2051
2052 /*
2053  * These are source-specific values; current Intel hardware supports
2054  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2055  */
2056
2057 static uint8_t
2058 intel_dp_voltage_max(struct intel_dp *intel_dp)
2059 {
2060         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2061         enum port port = dp_to_dig_port(intel_dp)->port;
2062
2063         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
2064                 return DP_TRAIN_VOLTAGE_SWING_1200;
2065         else if (IS_GEN7(dev) && port == PORT_A)
2066                 return DP_TRAIN_VOLTAGE_SWING_800;
2067         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2068                 return DP_TRAIN_VOLTAGE_SWING_1200;
2069         else
2070                 return DP_TRAIN_VOLTAGE_SWING_800;
2071 }
2072
2073 static uint8_t
2074 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2075 {
2076         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2077         enum port port = dp_to_dig_port(intel_dp)->port;
2078
2079         if (IS_BROADWELL(dev)) {
2080                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2081                 case DP_TRAIN_VOLTAGE_SWING_400:
2082                 case DP_TRAIN_VOLTAGE_SWING_600:
2083                         return DP_TRAIN_PRE_EMPHASIS_6;
2084                 case DP_TRAIN_VOLTAGE_SWING_800:
2085                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2086                 case DP_TRAIN_VOLTAGE_SWING_1200:
2087                 default:
2088                         return DP_TRAIN_PRE_EMPHASIS_0;
2089                 }
2090         } else if (IS_HASWELL(dev)) {
2091                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2092                 case DP_TRAIN_VOLTAGE_SWING_400:
2093                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2094                 case DP_TRAIN_VOLTAGE_SWING_600:
2095                         return DP_TRAIN_PRE_EMPHASIS_6;
2096                 case DP_TRAIN_VOLTAGE_SWING_800:
2097                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2098                 case DP_TRAIN_VOLTAGE_SWING_1200:
2099                 default:
2100                         return DP_TRAIN_PRE_EMPHASIS_0;
2101                 }
2102         } else if (IS_VALLEYVIEW(dev)) {
2103                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2104                 case DP_TRAIN_VOLTAGE_SWING_400:
2105                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2106                 case DP_TRAIN_VOLTAGE_SWING_600:
2107                         return DP_TRAIN_PRE_EMPHASIS_6;
2108                 case DP_TRAIN_VOLTAGE_SWING_800:
2109                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2110                 case DP_TRAIN_VOLTAGE_SWING_1200:
2111                 default:
2112                         return DP_TRAIN_PRE_EMPHASIS_0;
2113                 }
2114         } else if (IS_GEN7(dev) && port == PORT_A) {
2115                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2116                 case DP_TRAIN_VOLTAGE_SWING_400:
2117                         return DP_TRAIN_PRE_EMPHASIS_6;
2118                 case DP_TRAIN_VOLTAGE_SWING_600:
2119                 case DP_TRAIN_VOLTAGE_SWING_800:
2120                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2121                 default:
2122                         return DP_TRAIN_PRE_EMPHASIS_0;
2123                 }
2124         } else {
2125                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2126                 case DP_TRAIN_VOLTAGE_SWING_400:
2127                         return DP_TRAIN_PRE_EMPHASIS_6;
2128                 case DP_TRAIN_VOLTAGE_SWING_600:
2129                         return DP_TRAIN_PRE_EMPHASIS_6;
2130                 case DP_TRAIN_VOLTAGE_SWING_800:
2131                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2132                 case DP_TRAIN_VOLTAGE_SWING_1200:
2133                 default:
2134                         return DP_TRAIN_PRE_EMPHASIS_0;
2135                 }
2136         }
2137 }
2138
2139 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2140 {
2141         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2142         struct drm_i915_private *dev_priv = dev->dev_private;
2143         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2144         struct intel_crtc *intel_crtc =
2145                 to_intel_crtc(dport->base.base.crtc);
2146         unsigned long demph_reg_value, preemph_reg_value,
2147                 uniqtranscale_reg_value;
2148         uint8_t train_set = intel_dp->train_set[0];
2149         enum dpio_channel port = vlv_dport_to_channel(dport);
2150         int pipe = intel_crtc->pipe;
2151
2152         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2153         case DP_TRAIN_PRE_EMPHASIS_0:
2154                 preemph_reg_value = 0x0004000;
2155                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2156                 case DP_TRAIN_VOLTAGE_SWING_400:
2157                         demph_reg_value = 0x2B405555;
2158                         uniqtranscale_reg_value = 0x552AB83A;
2159                         break;
2160                 case DP_TRAIN_VOLTAGE_SWING_600:
2161                         demph_reg_value = 0x2B404040;
2162                         uniqtranscale_reg_value = 0x5548B83A;
2163                         break;
2164                 case DP_TRAIN_VOLTAGE_SWING_800:
2165                         demph_reg_value = 0x2B245555;
2166                         uniqtranscale_reg_value = 0x5560B83A;
2167                         break;
2168                 case DP_TRAIN_VOLTAGE_SWING_1200:
2169                         demph_reg_value = 0x2B405555;
2170                         uniqtranscale_reg_value = 0x5598DA3A;
2171                         break;
2172                 default:
2173                         return 0;
2174                 }
2175                 break;
2176         case DP_TRAIN_PRE_EMPHASIS_3_5:
2177                 preemph_reg_value = 0x0002000;
2178                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2179                 case DP_TRAIN_VOLTAGE_SWING_400:
2180                         demph_reg_value = 0x2B404040;
2181                         uniqtranscale_reg_value = 0x5552B83A;
2182                         break;
2183                 case DP_TRAIN_VOLTAGE_SWING_600:
2184                         demph_reg_value = 0x2B404848;
2185                         uniqtranscale_reg_value = 0x5580B83A;
2186                         break;
2187                 case DP_TRAIN_VOLTAGE_SWING_800:
2188                         demph_reg_value = 0x2B404040;
2189                         uniqtranscale_reg_value = 0x55ADDA3A;
2190                         break;
2191                 default:
2192                         return 0;
2193                 }
2194                 break;
2195         case DP_TRAIN_PRE_EMPHASIS_6:
2196                 preemph_reg_value = 0x0000000;
2197                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2198                 case DP_TRAIN_VOLTAGE_SWING_400:
2199                         demph_reg_value = 0x2B305555;
2200                         uniqtranscale_reg_value = 0x5570B83A;
2201                         break;
2202                 case DP_TRAIN_VOLTAGE_SWING_600:
2203                         demph_reg_value = 0x2B2B4040;
2204                         uniqtranscale_reg_value = 0x55ADDA3A;
2205                         break;
2206                 default:
2207                         return 0;
2208                 }
2209                 break;
2210         case DP_TRAIN_PRE_EMPHASIS_9_5:
2211                 preemph_reg_value = 0x0006000;
2212                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2213                 case DP_TRAIN_VOLTAGE_SWING_400:
2214                         demph_reg_value = 0x1B405555;
2215                         uniqtranscale_reg_value = 0x55ADDA3A;
2216                         break;
2217                 default:
2218                         return 0;
2219                 }
2220                 break;
2221         default:
2222                 return 0;
2223         }
2224
2225         mutex_lock(&dev_priv->dpio_lock);
2226         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2227         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2228         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2229                          uniqtranscale_reg_value);
2230         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2231         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2232         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2233         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2234         mutex_unlock(&dev_priv->dpio_lock);
2235
2236         return 0;
2237 }
2238
2239 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2240 {
2241         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2244         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2245         u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
2246         uint8_t train_set = intel_dp->train_set[0];
2247         enum dpio_channel ch = vlv_dport_to_channel(dport);
2248         int pipe = intel_crtc->pipe;
2249
2250         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2251         case DP_TRAIN_PRE_EMPHASIS_0:
2252                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2253                 case DP_TRAIN_VOLTAGE_SWING_400:
2254                         deemph_reg_value = 128;
2255                         margin_reg_value = 52;
2256                         break;
2257                 case DP_TRAIN_VOLTAGE_SWING_600:
2258                         deemph_reg_value = 128;
2259                         margin_reg_value = 77;
2260                         break;
2261                 case DP_TRAIN_VOLTAGE_SWING_800:
2262                         deemph_reg_value = 128;
2263                         margin_reg_value = 102;
2264                         break;
2265                 case DP_TRAIN_VOLTAGE_SWING_1200:
2266                         deemph_reg_value = 128;
2267                         margin_reg_value = 154;
2268                         /* FIXME extra to set for 1200 */
2269                         break;
2270                 default:
2271                         return 0;
2272                 }
2273                 break;
2274         case DP_TRAIN_PRE_EMPHASIS_3_5:
2275                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2276                 case DP_TRAIN_VOLTAGE_SWING_400:
2277                         deemph_reg_value = 85;
2278                         margin_reg_value = 78;
2279                         break;
2280                 case DP_TRAIN_VOLTAGE_SWING_600:
2281                         deemph_reg_value = 85;
2282                         margin_reg_value = 116;
2283                         break;
2284                 case DP_TRAIN_VOLTAGE_SWING_800:
2285                         deemph_reg_value = 85;
2286                         margin_reg_value = 154;
2287                         break;
2288                 default:
2289                         return 0;
2290                 }
2291                 break;
2292         case DP_TRAIN_PRE_EMPHASIS_6:
2293                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2294                 case DP_TRAIN_VOLTAGE_SWING_400:
2295                         deemph_reg_value = 64;
2296                         margin_reg_value = 104;
2297                         break;
2298                 case DP_TRAIN_VOLTAGE_SWING_600:
2299                         deemph_reg_value = 64;
2300                         margin_reg_value = 154;
2301                         break;
2302                 default:
2303                         return 0;
2304                 }
2305                 break;
2306         case DP_TRAIN_PRE_EMPHASIS_9_5:
2307                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2308                 case DP_TRAIN_VOLTAGE_SWING_400:
2309                         deemph_reg_value = 43;
2310                         margin_reg_value = 154;
2311                         break;
2312                 default:
2313                         return 0;
2314                 }
2315                 break;
2316         default:
2317                 return 0;
2318         }
2319
2320         mutex_lock(&dev_priv->dpio_lock);
2321
2322         /* Clear calc init */
2323         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
2324
2325         /* Program swing deemph */
2326         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
2327         val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2328         val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2329         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
2330
2331         /* Program swing margin */
2332         tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
2333         tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
2334         tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2335         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2336
2337         /* Disable unique transition scale */
2338         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2339         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2340         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2341
2342         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2343                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2344                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2345                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2346
2347                 /*
2348                  * The document said it needs to set bit 27 for ch0 and bit 26
2349                  * for ch1. Might be a typo in the doc.
2350                  * For now, for this unique transition scale selection, set bit
2351                  * 27 for ch0 and ch1.
2352                  */
2353                 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2354                 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2355                 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2356
2357                 tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2358                 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2359         }
2360
2361         /* Start swing calculation */
2362         vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
2363                 (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
2364
2365         /* LRC Bypass */
2366         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2367         val |= DPIO_LRC_BYPASS;
2368         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2369
2370         mutex_unlock(&dev_priv->dpio_lock);
2371
2372         return 0;
2373 }
2374
2375 static void
2376 intel_get_adjust_train(struct intel_dp *intel_dp,
2377                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2378 {
2379         uint8_t v = 0;
2380         uint8_t p = 0;
2381         int lane;
2382         uint8_t voltage_max;
2383         uint8_t preemph_max;
2384
2385         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2386                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2387                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2388
2389                 if (this_v > v)
2390                         v = this_v;
2391                 if (this_p > p)
2392                         p = this_p;
2393         }
2394
2395         voltage_max = intel_dp_voltage_max(intel_dp);
2396         if (v >= voltage_max)
2397                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2398
2399         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2400         if (p >= preemph_max)
2401                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2402
2403         for (lane = 0; lane < 4; lane++)
2404                 intel_dp->train_set[lane] = v | p;
2405 }
2406
2407 static uint32_t
2408 intel_gen4_signal_levels(uint8_t train_set)
2409 {
2410         uint32_t        signal_levels = 0;
2411
2412         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2413         case DP_TRAIN_VOLTAGE_SWING_400:
2414         default:
2415                 signal_levels |= DP_VOLTAGE_0_4;
2416                 break;
2417         case DP_TRAIN_VOLTAGE_SWING_600:
2418                 signal_levels |= DP_VOLTAGE_0_6;
2419                 break;
2420         case DP_TRAIN_VOLTAGE_SWING_800:
2421                 signal_levels |= DP_VOLTAGE_0_8;
2422                 break;
2423         case DP_TRAIN_VOLTAGE_SWING_1200:
2424                 signal_levels |= DP_VOLTAGE_1_2;
2425                 break;
2426         }
2427         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2428         case DP_TRAIN_PRE_EMPHASIS_0:
2429         default:
2430                 signal_levels |= DP_PRE_EMPHASIS_0;
2431                 break;
2432         case DP_TRAIN_PRE_EMPHASIS_3_5:
2433                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2434                 break;
2435         case DP_TRAIN_PRE_EMPHASIS_6:
2436                 signal_levels |= DP_PRE_EMPHASIS_6;
2437                 break;
2438         case DP_TRAIN_PRE_EMPHASIS_9_5:
2439                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2440                 break;
2441         }
2442         return signal_levels;
2443 }
2444
2445 /* Gen6's DP voltage swing and pre-emphasis control */
2446 static uint32_t
2447 intel_gen6_edp_signal_levels(uint8_t train_set)
2448 {
2449         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2450                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2451         switch (signal_levels) {
2452         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2453         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2454                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2455         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2456                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2457         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2458         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2459                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2460         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2461         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2462                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2463         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2464         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2465                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2466         default:
2467                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2468                               "0x%x\n", signal_levels);
2469                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2470         }
2471 }
2472
2473 /* Gen7's DP voltage swing and pre-emphasis control */
2474 static uint32_t
2475 intel_gen7_edp_signal_levels(uint8_t train_set)
2476 {
2477         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2478                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2479         switch (signal_levels) {
2480         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2481                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2482         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2483                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2484         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2485                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2486
2487         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2488                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2489         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2490                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2491
2492         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2493                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2494         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2495                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2496
2497         default:
2498                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2499                               "0x%x\n", signal_levels);
2500                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2501         }
2502 }
2503
2504 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2505 static uint32_t
2506 intel_hsw_signal_levels(uint8_t train_set)
2507 {
2508         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2509                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2510         switch (signal_levels) {
2511         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2512                 return DDI_BUF_EMP_400MV_0DB_HSW;
2513         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2514                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2515         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2516                 return DDI_BUF_EMP_400MV_6DB_HSW;
2517         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2518                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2519
2520         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2521                 return DDI_BUF_EMP_600MV_0DB_HSW;
2522         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2523                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2524         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2525                 return DDI_BUF_EMP_600MV_6DB_HSW;
2526
2527         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2528                 return DDI_BUF_EMP_800MV_0DB_HSW;
2529         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2530                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2531         default:
2532                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2533                               "0x%x\n", signal_levels);
2534                 return DDI_BUF_EMP_400MV_0DB_HSW;
2535         }
2536 }
2537
2538 static uint32_t
2539 intel_bdw_signal_levels(uint8_t train_set)
2540 {
2541         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2542                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2543         switch (signal_levels) {
2544         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2545                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2546         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2547                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2548         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2549                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2550
2551         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2552                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2553         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2554                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2555         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2556                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2557
2558         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2559                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2560         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2561                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2562
2563         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2564                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2565
2566         default:
2567                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2568                               "0x%x\n", signal_levels);
2569                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2570         }
2571 }
2572
2573 /* Properly updates "DP" with the correct signal levels. */
2574 static void
2575 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2576 {
2577         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2578         enum port port = intel_dig_port->port;
2579         struct drm_device *dev = intel_dig_port->base.base.dev;
2580         uint32_t signal_levels, mask;
2581         uint8_t train_set = intel_dp->train_set[0];
2582
2583         if (IS_BROADWELL(dev)) {
2584                 signal_levels = intel_bdw_signal_levels(train_set);
2585                 mask = DDI_BUF_EMP_MASK;
2586         } else if (IS_HASWELL(dev)) {
2587                 signal_levels = intel_hsw_signal_levels(train_set);
2588                 mask = DDI_BUF_EMP_MASK;
2589         } else if (IS_CHERRYVIEW(dev)) {
2590                 signal_levels = intel_chv_signal_levels(intel_dp);
2591                 mask = 0;
2592         } else if (IS_VALLEYVIEW(dev)) {
2593                 signal_levels = intel_vlv_signal_levels(intel_dp);
2594                 mask = 0;
2595         } else if (IS_GEN7(dev) && port == PORT_A) {
2596                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2597                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2598         } else if (IS_GEN6(dev) && port == PORT_A) {
2599                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2600                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2601         } else {
2602                 signal_levels = intel_gen4_signal_levels(train_set);
2603                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2604         }
2605
2606         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2607
2608         *DP = (*DP & ~mask) | signal_levels;
2609 }
2610
2611 static bool
2612 intel_dp_set_link_train(struct intel_dp *intel_dp,
2613                         uint32_t *DP,
2614                         uint8_t dp_train_pat)
2615 {
2616         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2617         struct drm_device *dev = intel_dig_port->base.base.dev;
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         enum port port = intel_dig_port->port;
2620         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2621         int ret, len;
2622
2623         if (HAS_DDI(dev)) {
2624                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2625
2626                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2627                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2628                 else
2629                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2630
2631                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2632                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2633                 case DP_TRAINING_PATTERN_DISABLE:
2634                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2635
2636                         break;
2637                 case DP_TRAINING_PATTERN_1:
2638                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2639                         break;
2640                 case DP_TRAINING_PATTERN_2:
2641                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2642                         break;
2643                 case DP_TRAINING_PATTERN_3:
2644                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2645                         break;
2646                 }
2647                 I915_WRITE(DP_TP_CTL(port), temp);
2648
2649         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2650                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2651
2652                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2653                 case DP_TRAINING_PATTERN_DISABLE:
2654                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2655                         break;
2656                 case DP_TRAINING_PATTERN_1:
2657                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2658                         break;
2659                 case DP_TRAINING_PATTERN_2:
2660                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2661                         break;
2662                 case DP_TRAINING_PATTERN_3:
2663                         DRM_ERROR("DP training pattern 3 not supported\n");
2664                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2665                         break;
2666                 }
2667
2668         } else {
2669                 *DP &= ~DP_LINK_TRAIN_MASK;
2670
2671                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2672                 case DP_TRAINING_PATTERN_DISABLE:
2673                         *DP |= DP_LINK_TRAIN_OFF;
2674                         break;
2675                 case DP_TRAINING_PATTERN_1:
2676                         *DP |= DP_LINK_TRAIN_PAT_1;
2677                         break;
2678                 case DP_TRAINING_PATTERN_2:
2679                         *DP |= DP_LINK_TRAIN_PAT_2;
2680                         break;
2681                 case DP_TRAINING_PATTERN_3:
2682                         DRM_ERROR("DP training pattern 3 not supported\n");
2683                         *DP |= DP_LINK_TRAIN_PAT_2;
2684                         break;
2685                 }
2686         }
2687
2688         I915_WRITE(intel_dp->output_reg, *DP);
2689         POSTING_READ(intel_dp->output_reg);
2690
2691         buf[0] = dp_train_pat;
2692         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2693             DP_TRAINING_PATTERN_DISABLE) {
2694                 /* don't write DP_TRAINING_LANEx_SET on disable */
2695                 len = 1;
2696         } else {
2697                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2698                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2699                 len = intel_dp->lane_count + 1;
2700         }
2701
2702         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2703                                 buf, len);
2704
2705         return ret == len;
2706 }
2707
2708 static bool
2709 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2710                         uint8_t dp_train_pat)
2711 {
2712         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2713         intel_dp_set_signal_levels(intel_dp, DP);
2714         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2715 }
2716
2717 static bool
2718 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2719                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2720 {
2721         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2722         struct drm_device *dev = intel_dig_port->base.base.dev;
2723         struct drm_i915_private *dev_priv = dev->dev_private;
2724         int ret;
2725
2726         intel_get_adjust_train(intel_dp, link_status);
2727         intel_dp_set_signal_levels(intel_dp, DP);
2728
2729         I915_WRITE(intel_dp->output_reg, *DP);
2730         POSTING_READ(intel_dp->output_reg);
2731
2732         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2733                                 intel_dp->train_set, intel_dp->lane_count);
2734
2735         return ret == intel_dp->lane_count;
2736 }
2737
2738 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2739 {
2740         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2741         struct drm_device *dev = intel_dig_port->base.base.dev;
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         enum port port = intel_dig_port->port;
2744         uint32_t val;
2745
2746         if (!HAS_DDI(dev))
2747                 return;
2748
2749         val = I915_READ(DP_TP_CTL(port));
2750         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2751         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2752         I915_WRITE(DP_TP_CTL(port), val);
2753
2754         /*
2755          * On PORT_A we can have only eDP in SST mode. There the only reason
2756          * we need to set idle transmission mode is to work around a HW issue
2757          * where we enable the pipe while not in idle link-training mode.
2758          * In this case there is requirement to wait for a minimum number of
2759          * idle patterns to be sent.
2760          */
2761         if (port == PORT_A)
2762                 return;
2763
2764         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2765                      1))
2766                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2767 }
2768
2769 /* Enable corresponding port and start training pattern 1 */
2770 void
2771 intel_dp_start_link_train(struct intel_dp *intel_dp)
2772 {
2773         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2774         struct drm_device *dev = encoder->dev;
2775         int i;
2776         uint8_t voltage;
2777         int voltage_tries, loop_tries;
2778         uint32_t DP = intel_dp->DP;
2779         uint8_t link_config[2];
2780
2781         if (HAS_DDI(dev))
2782                 intel_ddi_prepare_link_retrain(encoder);
2783
2784         /* Write the link configuration data */
2785         link_config[0] = intel_dp->link_bw;
2786         link_config[1] = intel_dp->lane_count;
2787         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2788                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2789         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2790
2791         link_config[0] = 0;
2792         link_config[1] = DP_SET_ANSI_8B10B;
2793         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2794
2795         DP |= DP_PORT_EN;
2796
2797         /* clock recovery */
2798         if (!intel_dp_reset_link_train(intel_dp, &DP,
2799                                        DP_TRAINING_PATTERN_1 |
2800                                        DP_LINK_SCRAMBLING_DISABLE)) {
2801                 DRM_ERROR("failed to enable link training\n");
2802                 return;
2803         }
2804
2805         voltage = 0xff;
2806         voltage_tries = 0;
2807         loop_tries = 0;
2808         for (;;) {
2809                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2810
2811                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2812                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2813                         DRM_ERROR("failed to get link status\n");
2814                         break;
2815                 }
2816
2817                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2818                         DRM_DEBUG_KMS("clock recovery OK\n");
2819                         break;
2820                 }
2821
2822                 /* Check to see if we've tried the max voltage */
2823                 for (i = 0; i < intel_dp->lane_count; i++)
2824                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2825                                 break;
2826                 if (i == intel_dp->lane_count) {
2827                         ++loop_tries;
2828                         if (loop_tries == 5) {
2829                                 DRM_ERROR("too many full retries, give up\n");
2830                                 break;
2831                         }
2832                         intel_dp_reset_link_train(intel_dp, &DP,
2833                                                   DP_TRAINING_PATTERN_1 |
2834                                                   DP_LINK_SCRAMBLING_DISABLE);
2835                         voltage_tries = 0;
2836                         continue;
2837                 }
2838
2839                 /* Check to see if we've tried the same voltage 5 times */
2840                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2841                         ++voltage_tries;
2842                         if (voltage_tries == 5) {
2843                                 DRM_ERROR("too many voltage retries, give up\n");
2844                                 break;
2845                         }
2846                 } else
2847                         voltage_tries = 0;
2848                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2849
2850                 /* Update training set as requested by target */
2851                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2852                         DRM_ERROR("failed to update link training\n");
2853                         break;
2854                 }
2855         }
2856
2857         intel_dp->DP = DP;
2858 }
2859
2860 void
2861 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2862 {
2863         bool channel_eq = false;
2864         int tries, cr_tries;
2865         uint32_t DP = intel_dp->DP;
2866         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2867
2868         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2869         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2870                 training_pattern = DP_TRAINING_PATTERN_3;
2871
2872         /* channel equalization */
2873         if (!intel_dp_set_link_train(intel_dp, &DP,
2874                                      training_pattern |
2875                                      DP_LINK_SCRAMBLING_DISABLE)) {
2876                 DRM_ERROR("failed to start channel equalization\n");
2877                 return;
2878         }
2879
2880         tries = 0;
2881         cr_tries = 0;
2882         channel_eq = false;
2883         for (;;) {
2884                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2885
2886                 if (cr_tries > 5) {
2887                         DRM_ERROR("failed to train DP, aborting\n");
2888                         break;
2889                 }
2890
2891                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2892                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2893                         DRM_ERROR("failed to get link status\n");
2894                         break;
2895                 }
2896
2897                 /* Make sure clock is still ok */
2898                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2899                         intel_dp_start_link_train(intel_dp);
2900                         intel_dp_set_link_train(intel_dp, &DP,
2901                                                 training_pattern |
2902                                                 DP_LINK_SCRAMBLING_DISABLE);
2903                         cr_tries++;
2904                         continue;
2905                 }
2906
2907                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2908                         channel_eq = true;
2909                         break;
2910                 }
2911
2912                 /* Try 5 times, then try clock recovery if that fails */
2913                 if (tries > 5) {
2914                         intel_dp_link_down(intel_dp);
2915                         intel_dp_start_link_train(intel_dp);
2916                         intel_dp_set_link_train(intel_dp, &DP,
2917                                                 training_pattern |
2918                                                 DP_LINK_SCRAMBLING_DISABLE);
2919                         tries = 0;
2920                         cr_tries++;
2921                         continue;
2922                 }
2923
2924                 /* Update training set as requested by target */
2925                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2926                         DRM_ERROR("failed to update link training\n");
2927                         break;
2928                 }
2929                 ++tries;
2930         }
2931
2932         intel_dp_set_idle_link_train(intel_dp);
2933
2934         intel_dp->DP = DP;
2935
2936         if (channel_eq)
2937                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2938
2939 }
2940
2941 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2942 {
2943         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2944                                 DP_TRAINING_PATTERN_DISABLE);
2945 }
2946
2947 static void
2948 intel_dp_link_down(struct intel_dp *intel_dp)
2949 {
2950         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2951         enum port port = intel_dig_port->port;
2952         struct drm_device *dev = intel_dig_port->base.base.dev;
2953         struct drm_i915_private *dev_priv = dev->dev_private;
2954         struct intel_crtc *intel_crtc =
2955                 to_intel_crtc(intel_dig_port->base.base.crtc);
2956         uint32_t DP = intel_dp->DP;
2957
2958         /*
2959          * DDI code has a strict mode set sequence and we should try to respect
2960          * it, otherwise we might hang the machine in many different ways. So we
2961          * really should be disabling the port only on a complete crtc_disable
2962          * sequence. This function is just called under two conditions on DDI
2963          * code:
2964          * - Link train failed while doing crtc_enable, and on this case we
2965          *   really should respect the mode set sequence and wait for a
2966          *   crtc_disable.
2967          * - Someone turned the monitor off and intel_dp_check_link_status
2968          *   called us. We don't need to disable the whole port on this case, so
2969          *   when someone turns the monitor on again,
2970          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2971          *   train.
2972          */
2973         if (HAS_DDI(dev))
2974                 return;
2975
2976         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2977                 return;
2978
2979         DRM_DEBUG_KMS("\n");
2980
2981         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2982                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2983                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2984         } else {
2985                 DP &= ~DP_LINK_TRAIN_MASK;
2986                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2987         }
2988         POSTING_READ(intel_dp->output_reg);
2989
2990         if (HAS_PCH_IBX(dev) &&
2991             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2992                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2993
2994                 /* Hardware workaround: leaving our transcoder select
2995                  * set to transcoder B while it's off will prevent the
2996                  * corresponding HDMI output on transcoder A.
2997                  *
2998                  * Combine this with another hardware workaround:
2999                  * transcoder select bit can only be cleared while the
3000                  * port is enabled.
3001                  */
3002                 DP &= ~DP_PIPEB_SELECT;
3003                 I915_WRITE(intel_dp->output_reg, DP);
3004
3005                 /* Changes to enable or select take place the vblank
3006                  * after being written.
3007                  */
3008                 if (WARN_ON(crtc == NULL)) {
3009                         /* We should never try to disable a port without a crtc
3010                          * attached. For paranoia keep the code around for a
3011                          * bit. */
3012                         POSTING_READ(intel_dp->output_reg);
3013                         msleep(50);
3014                 } else
3015                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3016         }
3017
3018         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3019         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3020         POSTING_READ(intel_dp->output_reg);
3021         msleep(intel_dp->panel_power_down_delay);
3022 }
3023
3024 static bool
3025 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3026 {
3027         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3028         struct drm_device *dev = dig_port->base.base.dev;
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030
3031         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3032
3033         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3034                                     sizeof(intel_dp->dpcd)) < 0)
3035                 return false; /* aux transfer failed */
3036
3037         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3038                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3039         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3040
3041         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3042                 return false; /* DPCD not present */
3043
3044         /* Check if the panel supports PSR */
3045         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3046         if (is_edp(intel_dp)) {
3047                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3048                                         intel_dp->psr_dpcd,
3049                                         sizeof(intel_dp->psr_dpcd));
3050                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3051                         dev_priv->psr.sink_support = true;
3052                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3053                 }
3054         }
3055
3056         /* Training Pattern 3 support */
3057         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3058             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3059                 intel_dp->use_tps3 = true;
3060                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3061         } else
3062                 intel_dp->use_tps3 = false;
3063
3064         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3065               DP_DWN_STRM_PORT_PRESENT))
3066                 return true; /* native DP sink */
3067
3068         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3069                 return true; /* no per-port downstream info */
3070
3071         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3072                                     intel_dp->downstream_ports,
3073                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3074                 return false; /* downstream port status fetch failed */
3075
3076         return true;
3077 }
3078
3079 static void
3080 intel_dp_probe_oui(struct intel_dp *intel_dp)
3081 {
3082         u8 buf[3];
3083
3084         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3085                 return;
3086
3087         intel_edp_panel_vdd_on(intel_dp);
3088
3089         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3090                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3091                               buf[0], buf[1], buf[2]);
3092
3093         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3094                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3095                               buf[0], buf[1], buf[2]);
3096
3097         edp_panel_vdd_off(intel_dp, false);
3098 }
3099
3100 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3101 {
3102         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3103         struct drm_device *dev = intel_dig_port->base.base.dev;
3104         struct intel_crtc *intel_crtc =
3105                 to_intel_crtc(intel_dig_port->base.base.crtc);
3106         u8 buf[1];
3107
3108         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3109                 return -EAGAIN;
3110
3111         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3112                 return -ENOTTY;
3113
3114         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3115                                DP_TEST_SINK_START) < 0)
3116                 return -EAGAIN;
3117
3118         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3119         intel_wait_for_vblank(dev, intel_crtc->pipe);
3120         intel_wait_for_vblank(dev, intel_crtc->pipe);
3121
3122         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3123                 return -EAGAIN;
3124
3125         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3126         return 0;
3127 }
3128
3129 static bool
3130 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3131 {
3132         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3133                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3134                                        sink_irq_vector, 1) == 1;
3135 }
3136
3137 static void
3138 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3139 {
3140         /* NAK by default */
3141         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3142 }
3143
3144 /*
3145  * According to DP spec
3146  * 5.1.2:
3147  *  1. Read DPCD
3148  *  2. Configure link according to Receiver Capabilities
3149  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3150  *  4. Check link status on receipt of hot-plug interrupt
3151  */
3152
3153 void
3154 intel_dp_check_link_status(struct intel_dp *intel_dp)
3155 {
3156         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3157         u8 sink_irq_vector;
3158         u8 link_status[DP_LINK_STATUS_SIZE];
3159
3160         if (!intel_encoder->connectors_active)
3161                 return;
3162
3163         if (WARN_ON(!intel_encoder->base.crtc))
3164                 return;
3165
3166         /* Try to read receiver status if the link appears to be up */
3167         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3168                 return;
3169         }
3170
3171         /* Now read the DPCD to see if it's actually running */
3172         if (!intel_dp_get_dpcd(intel_dp)) {
3173                 return;
3174         }
3175
3176         /* Try to read the source of the interrupt */
3177         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3178             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3179                 /* Clear interrupt source */
3180                 drm_dp_dpcd_writeb(&intel_dp->aux,
3181                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3182                                    sink_irq_vector);
3183
3184                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3185                         intel_dp_handle_test_request(intel_dp);
3186                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3187                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3188         }
3189
3190         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3191                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3192                               drm_get_encoder_name(&intel_encoder->base));
3193                 intel_dp_start_link_train(intel_dp);
3194                 intel_dp_complete_link_train(intel_dp);
3195                 intel_dp_stop_link_train(intel_dp);
3196         }
3197 }
3198
3199 /* XXX this is probably wrong for multiple downstream ports */
3200 static enum drm_connector_status
3201 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3202 {
3203         uint8_t *dpcd = intel_dp->dpcd;
3204         uint8_t type;
3205
3206         if (!intel_dp_get_dpcd(intel_dp))
3207                 return connector_status_disconnected;
3208
3209         /* if there's no downstream port, we're done */
3210         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3211                 return connector_status_connected;
3212
3213         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3214         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3215             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3216                 uint8_t reg;
3217
3218                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3219                                             &reg, 1) < 0)
3220                         return connector_status_unknown;
3221
3222                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3223                                               : connector_status_disconnected;
3224         }
3225
3226         /* If no HPD, poke DDC gently */
3227         if (drm_probe_ddc(&intel_dp->aux.ddc))
3228                 return connector_status_connected;
3229
3230         /* Well we tried, say unknown for unreliable port types */
3231         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3232                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3233                 if (type == DP_DS_PORT_TYPE_VGA ||
3234                     type == DP_DS_PORT_TYPE_NON_EDID)
3235                         return connector_status_unknown;
3236         } else {
3237                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3238                         DP_DWN_STRM_PORT_TYPE_MASK;
3239                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3240                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3241                         return connector_status_unknown;
3242         }
3243
3244         /* Anything else is out of spec, warn and ignore */
3245         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3246         return connector_status_disconnected;
3247 }
3248
3249 static enum drm_connector_status
3250 ironlake_dp_detect(struct intel_dp *intel_dp)
3251 {
3252         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3253         struct drm_i915_private *dev_priv = dev->dev_private;
3254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3255         enum drm_connector_status status;
3256
3257         /* Can't disconnect eDP, but you can close the lid... */
3258         if (is_edp(intel_dp)) {
3259                 status = intel_panel_detect(dev);
3260                 if (status == connector_status_unknown)
3261                         status = connector_status_connected;
3262                 return status;
3263         }
3264
3265         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3266                 return connector_status_disconnected;
3267
3268         return intel_dp_detect_dpcd(intel_dp);
3269 }
3270
3271 static enum drm_connector_status
3272 g4x_dp_detect(struct intel_dp *intel_dp)
3273 {
3274         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3275         struct drm_i915_private *dev_priv = dev->dev_private;
3276         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3277         uint32_t bit;
3278
3279         /* Can't disconnect eDP, but you can close the lid... */
3280         if (is_edp(intel_dp)) {
3281                 enum drm_connector_status status;
3282
3283                 status = intel_panel_detect(dev);
3284                 if (status == connector_status_unknown)
3285                         status = connector_status_connected;
3286                 return status;
3287         }
3288
3289         if (IS_VALLEYVIEW(dev)) {
3290                 switch (intel_dig_port->port) {
3291                 case PORT_B:
3292                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3293                         break;
3294                 case PORT_C:
3295                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3296                         break;
3297                 case PORT_D:
3298                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3299                         break;
3300                 default:
3301                         return connector_status_unknown;
3302                 }
3303         } else {
3304                 switch (intel_dig_port->port) {
3305                 case PORT_B:
3306                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3307                         break;
3308                 case PORT_C:
3309                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3310                         break;
3311                 case PORT_D:
3312                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3313                         break;
3314                 default:
3315                         return connector_status_unknown;
3316                 }
3317         }
3318
3319         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3320                 return connector_status_disconnected;
3321
3322         return intel_dp_detect_dpcd(intel_dp);
3323 }
3324
3325 static struct edid *
3326 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3327 {
3328         struct intel_connector *intel_connector = to_intel_connector(connector);
3329
3330         /* use cached edid if we have one */
3331         if (intel_connector->edid) {
3332                 /* invalid edid */
3333                 if (IS_ERR(intel_connector->edid))
3334                         return NULL;
3335
3336                 return drm_edid_duplicate(intel_connector->edid);
3337         }
3338
3339         return drm_get_edid(connector, adapter);
3340 }
3341
3342 static int
3343 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3344 {
3345         struct intel_connector *intel_connector = to_intel_connector(connector);
3346
3347         /* use cached edid if we have one */
3348         if (intel_connector->edid) {
3349                 /* invalid edid */
3350                 if (IS_ERR(intel_connector->edid))
3351                         return 0;
3352
3353                 return intel_connector_update_modes(connector,
3354                                                     intel_connector->edid);
3355         }
3356
3357         return intel_ddc_get_modes(connector, adapter);
3358 }
3359
3360 static enum drm_connector_status
3361 intel_dp_detect(struct drm_connector *connector, bool force)
3362 {
3363         struct intel_dp *intel_dp = intel_attached_dp(connector);
3364         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3365         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3366         struct drm_device *dev = connector->dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         enum drm_connector_status status;
3369         enum intel_display_power_domain power_domain;
3370         struct edid *edid = NULL;
3371
3372         intel_runtime_pm_get(dev_priv);
3373
3374         power_domain = intel_display_port_power_domain(intel_encoder);
3375         intel_display_power_get(dev_priv, power_domain);
3376
3377         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3378                       connector->base.id, drm_get_connector_name(connector));
3379
3380         intel_dp->has_audio = false;
3381
3382         if (HAS_PCH_SPLIT(dev))
3383                 status = ironlake_dp_detect(intel_dp);
3384         else
3385                 status = g4x_dp_detect(intel_dp);
3386
3387         if (status != connector_status_connected)
3388                 goto out;
3389
3390         intel_dp_probe_oui(intel_dp);
3391
3392         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3393                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3394         } else {
3395                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3396                 if (edid) {
3397                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3398                         kfree(edid);
3399                 }
3400         }
3401
3402         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3403                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3404         status = connector_status_connected;
3405
3406 out:
3407         intel_display_power_put(dev_priv, power_domain);
3408
3409         intel_runtime_pm_put(dev_priv);
3410
3411         return status;
3412 }
3413
3414 static int intel_dp_get_modes(struct drm_connector *connector)
3415 {
3416         struct intel_dp *intel_dp = intel_attached_dp(connector);
3417         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3418         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3419         struct intel_connector *intel_connector = to_intel_connector(connector);
3420         struct drm_device *dev = connector->dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         enum intel_display_power_domain power_domain;
3423         int ret;
3424
3425         /* We should parse the EDID data and find out if it has an audio sink
3426          */
3427
3428         power_domain = intel_display_port_power_domain(intel_encoder);
3429         intel_display_power_get(dev_priv, power_domain);
3430
3431         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3432         intel_display_power_put(dev_priv, power_domain);
3433         if (ret)
3434                 return ret;
3435
3436         /* if eDP has no EDID, fall back to fixed mode */
3437         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3438                 struct drm_display_mode *mode;
3439                 mode = drm_mode_duplicate(dev,
3440                                           intel_connector->panel.fixed_mode);
3441                 if (mode) {
3442                         drm_mode_probed_add(connector, mode);
3443                         return 1;
3444                 }
3445         }
3446         return 0;
3447 }
3448
3449 static bool
3450 intel_dp_detect_audio(struct drm_connector *connector)
3451 {
3452         struct intel_dp *intel_dp = intel_attached_dp(connector);
3453         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3454         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3455         struct drm_device *dev = connector->dev;
3456         struct drm_i915_private *dev_priv = dev->dev_private;
3457         enum intel_display_power_domain power_domain;
3458         struct edid *edid;
3459         bool has_audio = false;
3460
3461         power_domain = intel_display_port_power_domain(intel_encoder);
3462         intel_display_power_get(dev_priv, power_domain);
3463
3464         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3465         if (edid) {
3466                 has_audio = drm_detect_monitor_audio(edid);
3467                 kfree(edid);
3468         }
3469
3470         intel_display_power_put(dev_priv, power_domain);
3471
3472         return has_audio;
3473 }
3474
3475 static int
3476 intel_dp_set_property(struct drm_connector *connector,
3477                       struct drm_property *property,
3478                       uint64_t val)
3479 {
3480         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3481         struct intel_connector *intel_connector = to_intel_connector(connector);
3482         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3483         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3484         int ret;
3485
3486         ret = drm_object_property_set_value(&connector->base, property, val);
3487         if (ret)
3488                 return ret;
3489
3490         if (property == dev_priv->force_audio_property) {
3491                 int i = val;
3492                 bool has_audio;
3493
3494                 if (i == intel_dp->force_audio)
3495                         return 0;
3496
3497                 intel_dp->force_audio = i;
3498
3499                 if (i == HDMI_AUDIO_AUTO)
3500                         has_audio = intel_dp_detect_audio(connector);
3501                 else
3502                         has_audio = (i == HDMI_AUDIO_ON);
3503
3504                 if (has_audio == intel_dp->has_audio)
3505                         return 0;
3506
3507                 intel_dp->has_audio = has_audio;
3508                 goto done;
3509         }
3510
3511         if (property == dev_priv->broadcast_rgb_property) {
3512                 bool old_auto = intel_dp->color_range_auto;
3513                 uint32_t old_range = intel_dp->color_range;
3514
3515                 switch (val) {
3516                 case INTEL_BROADCAST_RGB_AUTO:
3517                         intel_dp->color_range_auto = true;
3518                         break;
3519                 case INTEL_BROADCAST_RGB_FULL:
3520                         intel_dp->color_range_auto = false;
3521                         intel_dp->color_range = 0;
3522                         break;
3523                 case INTEL_BROADCAST_RGB_LIMITED:
3524                         intel_dp->color_range_auto = false;
3525                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3526                         break;
3527                 default:
3528                         return -EINVAL;
3529                 }
3530
3531                 if (old_auto == intel_dp->color_range_auto &&
3532                     old_range == intel_dp->color_range)
3533                         return 0;
3534
3535                 goto done;
3536         }
3537
3538         if (is_edp(intel_dp) &&
3539             property == connector->dev->mode_config.scaling_mode_property) {
3540                 if (val == DRM_MODE_SCALE_NONE) {
3541                         DRM_DEBUG_KMS("no scaling not supported\n");
3542                         return -EINVAL;
3543                 }
3544
3545                 if (intel_connector->panel.fitting_mode == val) {
3546                         /* the eDP scaling property is not changed */
3547                         return 0;
3548                 }
3549                 intel_connector->panel.fitting_mode = val;
3550
3551                 goto done;
3552         }
3553
3554         return -EINVAL;
3555
3556 done:
3557         if (intel_encoder->base.crtc)
3558                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3559
3560         return 0;
3561 }
3562
3563 static void
3564 intel_dp_connector_destroy(struct drm_connector *connector)
3565 {
3566         struct intel_connector *intel_connector = to_intel_connector(connector);
3567
3568         if (!IS_ERR_OR_NULL(intel_connector->edid))
3569                 kfree(intel_connector->edid);
3570
3571         /* Can't call is_edp() since the encoder may have been destroyed
3572          * already. */
3573         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3574                 intel_panel_fini(&intel_connector->panel);
3575
3576         drm_connector_cleanup(connector);
3577         kfree(connector);
3578 }
3579
3580 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3581 {
3582         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3583         struct intel_dp *intel_dp = &intel_dig_port->dp;
3584         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3585
3586         drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3587         drm_encoder_cleanup(encoder);
3588         if (is_edp(intel_dp)) {
3589                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3590                 mutex_lock(&dev->mode_config.mutex);
3591                 edp_panel_vdd_off_sync(intel_dp);
3592                 mutex_unlock(&dev->mode_config.mutex);
3593         }
3594         kfree(intel_dig_port);
3595 }
3596
3597 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3598         .dpms = intel_connector_dpms,
3599         .detect = intel_dp_detect,
3600         .fill_modes = drm_helper_probe_single_connector_modes,
3601         .set_property = intel_dp_set_property,
3602         .destroy = intel_dp_connector_destroy,
3603 };
3604
3605 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3606         .get_modes = intel_dp_get_modes,
3607         .mode_valid = intel_dp_mode_valid,
3608         .best_encoder = intel_best_encoder,
3609 };
3610
3611 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3612         .destroy = intel_dp_encoder_destroy,
3613 };
3614
3615 static void
3616 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3617 {
3618         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3619
3620         intel_dp_check_link_status(intel_dp);
3621 }
3622
3623 /* Return which DP Port should be selected for Transcoder DP control */
3624 int
3625 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3626 {
3627         struct drm_device *dev = crtc->dev;
3628         struct intel_encoder *intel_encoder;
3629         struct intel_dp *intel_dp;
3630
3631         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3632                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3633
3634                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3635                     intel_encoder->type == INTEL_OUTPUT_EDP)
3636                         return intel_dp->output_reg;
3637         }
3638
3639         return -1;
3640 }
3641
3642 /* check the VBT to see whether the eDP is on DP-D port */
3643 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3644 {
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         union child_device_config *p_child;
3647         int i;
3648         static const short port_mapping[] = {
3649                 [PORT_B] = PORT_IDPB,
3650                 [PORT_C] = PORT_IDPC,
3651                 [PORT_D] = PORT_IDPD,
3652         };
3653
3654         if (port == PORT_A)
3655                 return true;
3656
3657         if (!dev_priv->vbt.child_dev_num)
3658                 return false;
3659
3660         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3661                 p_child = dev_priv->vbt.child_dev + i;
3662
3663                 if (p_child->common.dvo_port == port_mapping[port] &&
3664                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3665                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3666                         return true;
3667         }
3668         return false;
3669 }
3670
3671 static void
3672 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3673 {
3674         struct intel_connector *intel_connector = to_intel_connector(connector);
3675
3676         intel_attach_force_audio_property(connector);
3677         intel_attach_broadcast_rgb_property(connector);
3678         intel_dp->color_range_auto = true;
3679
3680         if (is_edp(intel_dp)) {
3681                 drm_mode_create_scaling_mode_property(connector->dev);
3682                 drm_object_attach_property(
3683                         &connector->base,
3684                         connector->dev->mode_config.scaling_mode_property,
3685                         DRM_MODE_SCALE_ASPECT);
3686                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3687         }
3688 }
3689
3690 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3691 {
3692         intel_dp->last_power_cycle = jiffies;
3693         intel_dp->last_power_on = jiffies;
3694         intel_dp->last_backlight_off = jiffies;
3695 }
3696
3697 static void
3698 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3699                                     struct intel_dp *intel_dp,
3700                                     struct edp_power_seq *out)
3701 {
3702         struct drm_i915_private *dev_priv = dev->dev_private;
3703         struct edp_power_seq cur, vbt, spec, final;
3704         u32 pp_on, pp_off, pp_div, pp;
3705         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3706
3707         if (HAS_PCH_SPLIT(dev)) {
3708                 pp_ctrl_reg = PCH_PP_CONTROL;
3709                 pp_on_reg = PCH_PP_ON_DELAYS;
3710                 pp_off_reg = PCH_PP_OFF_DELAYS;
3711                 pp_div_reg = PCH_PP_DIVISOR;
3712         } else {
3713                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3714
3715                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3716                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3717                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3718                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3719         }
3720
3721         /* Workaround: Need to write PP_CONTROL with the unlock key as
3722          * the very first thing. */
3723         pp = ironlake_get_pp_control(intel_dp);
3724         I915_WRITE(pp_ctrl_reg, pp);
3725
3726         pp_on = I915_READ(pp_on_reg);
3727         pp_off = I915_READ(pp_off_reg);
3728         pp_div = I915_READ(pp_div_reg);
3729
3730         /* Pull timing values out of registers */
3731         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3732                 PANEL_POWER_UP_DELAY_SHIFT;
3733
3734         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3735                 PANEL_LIGHT_ON_DELAY_SHIFT;
3736
3737         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3738                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3739
3740         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3741                 PANEL_POWER_DOWN_DELAY_SHIFT;
3742
3743         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3744                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3745
3746         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3747                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3748
3749         vbt = dev_priv->vbt.edp_pps;
3750
3751         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3752          * our hw here, which are all in 100usec. */
3753         spec.t1_t3 = 210 * 10;
3754         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3755         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3756         spec.t10 = 500 * 10;
3757         /* This one is special and actually in units of 100ms, but zero
3758          * based in the hw (so we need to add 100 ms). But the sw vbt
3759          * table multiplies it with 1000 to make it in units of 100usec,
3760          * too. */
3761         spec.t11_t12 = (510 + 100) * 10;
3762
3763         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3764                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3765
3766         /* Use the max of the register settings and vbt. If both are
3767          * unset, fall back to the spec limits. */
3768 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3769                                        spec.field : \
3770                                        max(cur.field, vbt.field))
3771         assign_final(t1_t3);
3772         assign_final(t8);
3773         assign_final(t9);
3774         assign_final(t10);
3775         assign_final(t11_t12);
3776 #undef assign_final
3777
3778 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3779         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3780         intel_dp->backlight_on_delay = get_delay(t8);
3781         intel_dp->backlight_off_delay = get_delay(t9);
3782         intel_dp->panel_power_down_delay = get_delay(t10);
3783         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3784 #undef get_delay
3785
3786         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3787                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3788                       intel_dp->panel_power_cycle_delay);
3789
3790         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3791                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3792
3793         if (out)
3794                 *out = final;
3795 }
3796
3797 static void
3798 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3799                                               struct intel_dp *intel_dp,
3800                                               struct edp_power_seq *seq)
3801 {
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         u32 pp_on, pp_off, pp_div, port_sel = 0;
3804         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3805         int pp_on_reg, pp_off_reg, pp_div_reg;
3806
3807         if (HAS_PCH_SPLIT(dev)) {
3808                 pp_on_reg = PCH_PP_ON_DELAYS;
3809                 pp_off_reg = PCH_PP_OFF_DELAYS;
3810                 pp_div_reg = PCH_PP_DIVISOR;
3811         } else {
3812                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3813
3814                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3815                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3816                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3817         }
3818
3819         /*
3820          * And finally store the new values in the power sequencer. The
3821          * backlight delays are set to 1 because we do manual waits on them. For
3822          * T8, even BSpec recommends doing it. For T9, if we don't do this,
3823          * we'll end up waiting for the backlight off delay twice: once when we
3824          * do the manual sleep, and once when we disable the panel and wait for
3825          * the PP_STATUS bit to become zero.
3826          */
3827         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3828                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3829         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3830                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3831         /* Compute the divisor for the pp clock, simply match the Bspec
3832          * formula. */
3833         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3834         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3835                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3836
3837         /* Haswell doesn't have any port selection bits for the panel
3838          * power sequencer any more. */
3839         if (IS_VALLEYVIEW(dev)) {
3840                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3841                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3842                 else
3843                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3844         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3845                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3846                         port_sel = PANEL_PORT_SELECT_DPA;
3847                 else
3848                         port_sel = PANEL_PORT_SELECT_DPD;
3849         }
3850
3851         pp_on |= port_sel;
3852
3853         I915_WRITE(pp_on_reg, pp_on);
3854         I915_WRITE(pp_off_reg, pp_off);
3855         I915_WRITE(pp_div_reg, pp_div);
3856
3857         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3858                       I915_READ(pp_on_reg),
3859                       I915_READ(pp_off_reg),
3860                       I915_READ(pp_div_reg));
3861 }
3862
3863 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3864 {
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         struct intel_encoder *encoder;
3867         struct intel_dp *intel_dp = NULL;
3868         struct intel_crtc_config *config = NULL;
3869         struct intel_crtc *intel_crtc = NULL;
3870         struct intel_connector *intel_connector = dev_priv->drrs.connector;
3871         u32 reg, val;
3872         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3873
3874         if (refresh_rate <= 0) {
3875                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3876                 return;
3877         }
3878
3879         if (intel_connector == NULL) {
3880                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3881                 return;
3882         }
3883
3884         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3885                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3886                 return;
3887         }
3888
3889         encoder = intel_attached_encoder(&intel_connector->base);
3890         intel_dp = enc_to_intel_dp(&encoder->base);
3891         intel_crtc = encoder->new_crtc;
3892
3893         if (!intel_crtc) {
3894                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3895                 return;
3896         }
3897
3898         config = &intel_crtc->config;
3899
3900         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3901                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3902                 return;
3903         }
3904
3905         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3906                 index = DRRS_LOW_RR;
3907
3908         if (index == intel_dp->drrs_state.refresh_rate_type) {
3909                 DRM_DEBUG_KMS(
3910                         "DRRS requested for previously set RR...ignoring\n");
3911                 return;
3912         }
3913
3914         if (!intel_crtc->active) {
3915                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3916                 return;
3917         }
3918
3919         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3920                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3921                 val = I915_READ(reg);
3922                 if (index > DRRS_HIGH_RR) {
3923                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
3924                         intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3925                 } else {
3926                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3927                 }
3928                 I915_WRITE(reg, val);
3929         }
3930
3931         /*
3932          * mutex taken to ensure that there is no race between differnt
3933          * drrs calls trying to update refresh rate. This scenario may occur
3934          * in future when idleness detection based DRRS in kernel and
3935          * possible calls from user space to set differnt RR are made.
3936          */
3937
3938         mutex_lock(&intel_dp->drrs_state.mutex);
3939
3940         intel_dp->drrs_state.refresh_rate_type = index;
3941
3942         mutex_unlock(&intel_dp->drrs_state.mutex);
3943
3944         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3945 }
3946
3947 static struct drm_display_mode *
3948 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3949                         struct intel_connector *intel_connector,
3950                         struct drm_display_mode *fixed_mode)
3951 {
3952         struct drm_connector *connector = &intel_connector->base;
3953         struct intel_dp *intel_dp = &intel_dig_port->dp;
3954         struct drm_device *dev = intel_dig_port->base.base.dev;
3955         struct drm_i915_private *dev_priv = dev->dev_private;
3956         struct drm_display_mode *downclock_mode = NULL;
3957
3958         if (INTEL_INFO(dev)->gen <= 6) {
3959                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3960                 return NULL;
3961         }
3962
3963         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3964                 DRM_INFO("VBT doesn't support DRRS\n");
3965                 return NULL;
3966         }
3967
3968         downclock_mode = intel_find_panel_downclock
3969                                         (dev, fixed_mode, connector);
3970
3971         if (!downclock_mode) {
3972                 DRM_INFO("DRRS not supported\n");
3973                 return NULL;
3974         }
3975
3976         dev_priv->drrs.connector = intel_connector;
3977
3978         mutex_init(&intel_dp->drrs_state.mutex);
3979
3980         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3981
3982         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3983         DRM_INFO("seamless DRRS supported for eDP panel.\n");
3984         return downclock_mode;
3985 }
3986
3987 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3988                                      struct intel_connector *intel_connector,
3989                                      struct edp_power_seq *power_seq)
3990 {
3991         struct drm_connector *connector = &intel_connector->base;
3992         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3993         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3994         struct drm_device *dev = intel_encoder->base.dev;
3995         struct drm_i915_private *dev_priv = dev->dev_private;
3996         struct drm_display_mode *fixed_mode = NULL;
3997         struct drm_display_mode *downclock_mode = NULL;
3998         bool has_dpcd;
3999         struct drm_display_mode *scan;
4000         struct edid *edid;
4001
4002         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4003
4004         if (!is_edp(intel_dp))
4005                 return true;
4006
4007         /* The VDD bit needs a power domain reference, so if the bit is already
4008          * enabled when we boot, grab this reference. */
4009         if (edp_have_panel_vdd(intel_dp)) {
4010                 enum intel_display_power_domain power_domain;
4011                 power_domain = intel_display_port_power_domain(intel_encoder);
4012                 intel_display_power_get(dev_priv, power_domain);
4013         }
4014
4015         /* Cache DPCD and EDID for edp. */
4016         intel_edp_panel_vdd_on(intel_dp);
4017         has_dpcd = intel_dp_get_dpcd(intel_dp);
4018         edp_panel_vdd_off(intel_dp, false);
4019
4020         if (has_dpcd) {
4021                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4022                         dev_priv->no_aux_handshake =
4023                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4024                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4025         } else {
4026                 /* if this fails, presume the device is a ghost */
4027                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4028                 return false;
4029         }
4030
4031         /* We now know it's not a ghost, init power sequence regs. */
4032         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4033
4034         mutex_lock(&dev->mode_config.mutex);
4035         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4036         if (edid) {
4037                 if (drm_add_edid_modes(connector, edid)) {
4038                         drm_mode_connector_update_edid_property(connector,
4039                                                                 edid);
4040                         drm_edid_to_eld(connector, edid);
4041                 } else {
4042                         kfree(edid);
4043                         edid = ERR_PTR(-EINVAL);
4044                 }
4045         } else {
4046                 edid = ERR_PTR(-ENOENT);
4047         }
4048         intel_connector->edid = edid;
4049
4050         /* prefer fixed mode from EDID if available */
4051         list_for_each_entry(scan, &connector->probed_modes, head) {
4052                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4053                         fixed_mode = drm_mode_duplicate(dev, scan);
4054                         downclock_mode = intel_dp_drrs_init(
4055                                                 intel_dig_port,
4056                                                 intel_connector, fixed_mode);
4057                         break;
4058                 }
4059         }
4060
4061         /* fallback to VBT if available for eDP */
4062         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4063                 fixed_mode = drm_mode_duplicate(dev,
4064                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4065                 if (fixed_mode)
4066                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4067         }
4068         mutex_unlock(&dev->mode_config.mutex);
4069
4070         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4071         intel_panel_setup_backlight(connector);
4072
4073         return true;
4074 }
4075
4076 bool
4077 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4078                         struct intel_connector *intel_connector)
4079 {
4080         struct drm_connector *connector = &intel_connector->base;
4081         struct intel_dp *intel_dp = &intel_dig_port->dp;
4082         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4083         struct drm_device *dev = intel_encoder->base.dev;
4084         struct drm_i915_private *dev_priv = dev->dev_private;
4085         enum port port = intel_dig_port->port;
4086         struct edp_power_seq power_seq = { 0 };
4087         int type;
4088
4089         /* intel_dp vfuncs */
4090         if (IS_VALLEYVIEW(dev))
4091                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4092         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4093                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4094         else if (HAS_PCH_SPLIT(dev))
4095                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4096         else
4097                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4098
4099         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4100
4101         /* Preserve the current hw state. */
4102         intel_dp->DP = I915_READ(intel_dp->output_reg);
4103         intel_dp->attached_connector = intel_connector;
4104
4105         if (intel_dp_is_edp(dev, port))
4106                 type = DRM_MODE_CONNECTOR_eDP;
4107         else
4108                 type = DRM_MODE_CONNECTOR_DisplayPort;
4109
4110         /*
4111          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4112          * for DP the encoder type can be set by the caller to
4113          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4114          */
4115         if (type == DRM_MODE_CONNECTOR_eDP)
4116                 intel_encoder->type = INTEL_OUTPUT_EDP;
4117
4118         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4119                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4120                         port_name(port));
4121
4122         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4123         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4124
4125         connector->interlace_allowed = true;
4126         connector->doublescan_allowed = 0;
4127
4128         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4129                           edp_panel_vdd_work);
4130
4131         intel_connector_attach_encoder(intel_connector, intel_encoder);
4132         drm_sysfs_connector_add(connector);
4133
4134         if (HAS_DDI(dev))
4135                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4136         else
4137                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4138         intel_connector->unregister = intel_dp_connector_unregister;
4139
4140         /* Set up the hotplug pin. */
4141         switch (port) {
4142         case PORT_A:
4143                 intel_encoder->hpd_pin = HPD_PORT_A;
4144                 break;
4145         case PORT_B:
4146                 intel_encoder->hpd_pin = HPD_PORT_B;
4147                 break;
4148         case PORT_C:
4149                 intel_encoder->hpd_pin = HPD_PORT_C;
4150                 break;
4151         case PORT_D:
4152                 intel_encoder->hpd_pin = HPD_PORT_D;
4153                 break;
4154         default:
4155                 BUG();
4156         }
4157
4158         if (is_edp(intel_dp)) {
4159                 intel_dp_init_panel_power_timestamps(intel_dp);
4160                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4161         }
4162
4163         intel_dp_aux_init(intel_dp, intel_connector);
4164
4165         intel_dp->psr_setup_done = false;
4166
4167         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4168                 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
4169                 if (is_edp(intel_dp)) {
4170                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4171                         mutex_lock(&dev->mode_config.mutex);
4172                         edp_panel_vdd_off_sync(intel_dp);
4173                         mutex_unlock(&dev->mode_config.mutex);
4174                 }
4175                 drm_sysfs_connector_remove(connector);
4176                 drm_connector_cleanup(connector);
4177                 return false;
4178         }
4179
4180         intel_dp_add_properties(intel_dp, connector);
4181
4182         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4183          * 0xd.  Failure to do so will result in spurious interrupts being
4184          * generated on the port when a cable is not attached.
4185          */
4186         if (IS_G4X(dev) && !IS_GM45(dev)) {
4187                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4188                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4189         }
4190
4191         return true;
4192 }
4193
4194 void
4195 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4196 {
4197         struct intel_digital_port *intel_dig_port;
4198         struct intel_encoder *intel_encoder;
4199         struct drm_encoder *encoder;
4200         struct intel_connector *intel_connector;
4201
4202         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4203         if (!intel_dig_port)
4204                 return;
4205
4206         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4207         if (!intel_connector) {
4208                 kfree(intel_dig_port);
4209                 return;
4210         }
4211
4212         intel_encoder = &intel_dig_port->base;
4213         encoder = &intel_encoder->base;
4214
4215         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4216                          DRM_MODE_ENCODER_TMDS);
4217
4218         intel_encoder->compute_config = intel_dp_compute_config;
4219         intel_encoder->mode_set = intel_dp_mode_set;
4220         intel_encoder->disable = intel_disable_dp;
4221         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4222         intel_encoder->get_config = intel_dp_get_config;
4223         if (IS_CHERRYVIEW(dev)) {
4224                 intel_encoder->pre_enable = chv_pre_enable_dp;
4225                 intel_encoder->enable = vlv_enable_dp;
4226         } else if (IS_VALLEYVIEW(dev)) {
4227                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4228                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4229                 intel_encoder->enable = vlv_enable_dp;
4230                 intel_encoder->post_disable = vlv_post_disable_dp;
4231         } else {
4232                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4233                 intel_encoder->enable = g4x_enable_dp;
4234                 intel_encoder->post_disable = g4x_post_disable_dp;
4235         }
4236
4237         intel_dig_port->port = port;
4238         intel_dig_port->dp.output_reg = output_reg;
4239
4240         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4241         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4242         intel_encoder->cloneable = 0;
4243         intel_encoder->hot_plug = intel_dp_hot_plug;
4244
4245         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4246                 drm_encoder_cleanup(encoder);
4247                 kfree(intel_dig_port);
4248                 kfree(intel_connector);
4249         }
4250 }