drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  47 #define DP_DPRX_ESI_LEN 14
  48
  49 /* Compliance test status bits  */
  50 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  51 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  54
  55 struct dp_link_dpll {
  56         int clock;
  57         struct dpll dpll;
  58 };
  59
  60 static const struct dp_link_dpll gen4_dpll[] = {
  61         { 162000,
  62                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  63         { 270000,
  64                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  65 };
  66
  67 static const struct dp_link_dpll pch_dpll[] = {
  68         { 162000,
  69                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  70         { 270000,
  71                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  72 };
  73
  74 static const struct dp_link_dpll vlv_dpll[] = {
  75         { 162000,
  76                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  77         { 270000,
  78                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  79 };
  80
  81 /*
  82  * CHV supports eDP 1.4 that have  more link rates.
  83  * Below only provides the fixed rate but exclude variable rate.
  84  */
  85 static const struct dp_link_dpll chv_dpll[] = {
  86         /*
  87          * CHV requires to program fractional division for m2.
  88          * m2 is stored in fixed point format using formula below
  89          * (m2_int << 22) | m2_fraction
  90          */
  91         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  92                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  93         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  95         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  96                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  97 };
  98
  99 /**
 100  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 101  * @intel_dp: DP struct
 102  *
 103  * If a CPU or PCH DP output is attached to an eDP panel, this function
 104  * will return true, and false otherwise.
 105  */
 106 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 107 {
 108         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 109
 110         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 111 }
 112
 113 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.base.dev;
 118 }
 119
 120 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 121 {
 122         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 123 }
 124
 125 static void intel_dp_link_down(struct intel_encoder *encoder,
 126                                const struct intel_crtc_state *old_crtc_state);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 130                                            const struct intel_crtc_state *crtc_state);
 131 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 132                                       enum pipe pipe);
 133 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 134
 135 /* update sink rates from dpcd */
 136 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 137 {
 138         static const int dp_rates[] = {
 139                 162000, 270000, 540000, 810000
 140         };
 141         int i, max_rate;
 142
 143         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 144
 145         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 146                 if (dp_rates[i] > max_rate)
 147                         break;
 148                 intel_dp->sink_rates[i] = dp_rates[i];
 149         }
 150
 151         intel_dp->num_sink_rates = i;
 152 }
 153
 154 /* Get length of rates array potentially limited by max_rate. */
 155 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 156 {
 157         int i;
 158
 159         /* Limit results by potentially reduced max rate */
 160         for (i = 0; i < len; i++) {
 161                 if (rates[len - i - 1] <= max_rate)
 162                         return len - i;
 163         }
 164
 165         return 0;
 166 }
 167
 168 /* Get length of common rates array potentially limited by max_rate. */
 169 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 170                                           int max_rate)
 171 {
 172         return intel_dp_rate_limit_len(intel_dp->common_rates,
 173                                        intel_dp->num_common_rates, max_rate);
 174 }
 175
 176 /* Theoretical max between source and sink */
 177 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 178 {
 179         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 180 }
 181
 182 /* Theoretical max between source and sink */
 183 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 184 {
 185         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 186         int source_max = intel_dig_port->max_lanes;
 187         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 188
 189         return min(source_max, sink_max);
 190 }
 191
 192 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 193 {
 194         return intel_dp->max_link_lane_count;
 195 }
 196
 197 int
 198 intel_dp_link_required(int pixel_clock, int bpp)
 199 {
 200         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 201         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 202 }
 203
 204 int
 205 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 206 {
 207         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 208          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 209          * is transmitted every LS_Clk per lane, there is no need to account for
 210          * the channel encoding that is done in the PHY layer here.
 211          */
 212
 213         return max_link_clock * max_lanes;
 214 }
 215
 216 static int
 217 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 218 {
 219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 220         struct intel_encoder *encoder = &intel_dig_port->base;
 221         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 222         int max_dotclk = dev_priv->max_dotclk_freq;
 223         int ds_max_dotclk;
 224
 225         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 226
 227         if (type != DP_DS_PORT_TYPE_VGA)
 228                 return max_dotclk;
 229
 230         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 231                                                     intel_dp->downstream_ports);
 232
 233         if (ds_max_dotclk != 0)
 234                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 235
 236         return max_dotclk;
 237 }
 238
 239 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 240 {
 241         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 242         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 243         enum port port = dig_port->base.port;
 244
 245         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 246
 247         /* Low voltage SKUs are limited to max of 5.4G */
 248         if (voltage == VOLTAGE_INFO_0_85V)
 249                 return 540000;
 250
 251         /* For this SKU 8.1G is supported in all ports */
 252         if (IS_CNL_WITH_PORT_F(dev_priv))
 253                 return 810000;
 254
 255         /* For other SKUs, max rate on ports A and D is 5.4G */
 256         if (port == PORT_A || port == PORT_D)
 257                 return 540000;
 258
 259         return 810000;
 260 }
 261
 262 static void
 263 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 264 {
 265         /* The values must be in increasing order */
 266         static const int cnl_rates[] = {
 267                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 268         };
 269         static const int bxt_rates[] = {
 270                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 271         };
 272         static const int skl_rates[] = {
 273                 162000, 216000, 270000, 324000, 432000, 540000
 274         };
 275         static const int hsw_rates[] = {
 276                 162000, 270000, 540000
 277         };
 278         static const int g4x_rates[] = {
 279                 162000, 270000
 280         };
 281         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 282         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 283         const struct ddi_vbt_port_info *info =
 284                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 285         const int *source_rates;
 286         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 287
 288         /* This should only be done once */
 289         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 290
 291         if (IS_CANNONLAKE(dev_priv)) {
 292                 source_rates = cnl_rates;
 293                 size = ARRAY_SIZE(cnl_rates);
 294                 max_rate = cnl_max_source_rate(intel_dp);
 295         } else if (IS_GEN9_LP(dev_priv)) {
 296                 source_rates = bxt_rates;
 297                 size = ARRAY_SIZE(bxt_rates);
 298         } else if (IS_GEN9_BC(dev_priv)) {
 299                 source_rates = skl_rates;
 300                 size = ARRAY_SIZE(skl_rates);
 301         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 302                    IS_BROADWELL(dev_priv)) {
 303                 source_rates = hsw_rates;
 304                 size = ARRAY_SIZE(hsw_rates);
 305         } else {
 306                 source_rates = g4x_rates;
 307                 size = ARRAY_SIZE(g4x_rates);
 308         }
 309
 310         if (max_rate && vbt_max_rate)
 311                 max_rate = min(max_rate, vbt_max_rate);
 312         else if (vbt_max_rate)
 313                 max_rate = vbt_max_rate;
 314
 315         if (max_rate)
 316                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 317
 318         intel_dp->source_rates = source_rates;
 319         intel_dp->num_source_rates = size;
 320 }
 321
 322 static int intersect_rates(const int *source_rates, int source_len,
 323                            const int *sink_rates, int sink_len,
 324                            int *common_rates)
 325 {
 326         int i = 0, j = 0, k = 0;
 327
 328         while (i < source_len && j < sink_len) {
 329                 if (source_rates[i] == sink_rates[j]) {
 330                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 331                                 return k;
 332                         common_rates[k] = source_rates[i];
 333                         ++k;
 334                         ++i;
 335                         ++j;
 336                 } else if (source_rates[i] < sink_rates[j]) {
 337                         ++i;
 338                 } else {
 339                         ++j;
 340                 }
 341         }
 342         return k;
 343 }
 344
 345 /* return index of rate in rates array, or -1 if not found */
 346 static int intel_dp_rate_index(const int *rates, int len, int rate)
 347 {
 348         int i;
 349
 350         for (i = 0; i < len; i++)
 351                 if (rate == rates[i])
 352                         return i;
 353
 354         return -1;
 355 }
 356
 357 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 358 {
 359         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 360
 361         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 362                                                      intel_dp->num_source_rates,
 363                                                      intel_dp->sink_rates,
 364                                                      intel_dp->num_sink_rates,
 365                                                      intel_dp->common_rates);
 366
 367         /* Paranoia, there should always be something in common. */
 368         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 369                 intel_dp->common_rates[0] = 162000;
 370                 intel_dp->num_common_rates = 1;
 371         }
 372 }
 373
 374 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 375                                        uint8_t lane_count)
 376 {
 377         /*
 378          * FIXME: we need to synchronize the current link parameters with
 379          * hardware readout. Currently fast link training doesn't work on
 380          * boot-up.
 381          */
 382         if (link_rate == 0 ||
 383             link_rate > intel_dp->max_link_rate)
 384                 return false;
 385
 386         if (lane_count == 0 ||
 387             lane_count > intel_dp_max_lane_count(intel_dp))
 388                 return false;
 389
 390         return true;
 391 }
 392
 393 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 394                                             int link_rate, uint8_t lane_count)
 395 {
 396         int index;
 397
 398         index = intel_dp_rate_index(intel_dp->common_rates,
 399                                     intel_dp->num_common_rates,
 400                                     link_rate);
 401         if (index > 0) {
 402                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 403                 intel_dp->max_link_lane_count = lane_count;
 404         } else if (lane_count > 1) {
 405                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 406                 intel_dp->max_link_lane_count = lane_count >> 1;
 407         } else {
 408                 DRM_ERROR("Link Training Unsuccessful\n");
 409                 return -1;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static enum drm_mode_status
 416 intel_dp_mode_valid(struct drm_connector *connector,
 417                     struct drm_display_mode *mode)
 418 {
 419         struct intel_dp *intel_dp = intel_attached_dp(connector);
 420         struct intel_connector *intel_connector = to_intel_connector(connector);
 421         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 422         int target_clock = mode->clock;
 423         int max_rate, mode_rate, max_lanes, max_link_clock;
 424         int max_dotclk;
 425
 426         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 427
 428         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 429                 if (mode->hdisplay > fixed_mode->hdisplay)
 430                         return MODE_PANEL;
 431
 432                 if (mode->vdisplay > fixed_mode->vdisplay)
 433                         return MODE_PANEL;
 434
 435                 target_clock = fixed_mode->clock;
 436         }
 437
 438         max_link_clock = intel_dp_max_link_rate(intel_dp);
 439         max_lanes = intel_dp_max_lane_count(intel_dp);
 440
 441         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 442         mode_rate = intel_dp_link_required(target_clock, 18);
 443
 444         if (mode_rate > max_rate || target_clock > max_dotclk)
 445                 return MODE_CLOCK_HIGH;
 446
 447         if (mode->clock < 10000)
 448                 return MODE_CLOCK_LOW;
 449
 450         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 451                 return MODE_H_ILLEGAL;
 452
 453         return MODE_OK;
 454 }
 455
 456 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 457 {
 458         int     i;
 459         uint32_t v = 0;
 460
 461         if (src_bytes > 4)
 462                 src_bytes = 4;
 463         for (i = 0; i < src_bytes; i++)
 464                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 465         return v;
 466 }
 467
 468 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 469 {
 470         int i;
 471         if (dst_bytes > 4)
 472                 dst_bytes = 4;
 473         for (i = 0; i < dst_bytes; i++)
 474                 dst[i] = src >> ((3-i) * 8);
 475 }
 476
 477 static void
 478 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 479 static void
 480 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 481                                               bool force_disable_vdd);
 482 static void
 483 intel_dp_pps_init(struct intel_dp *intel_dp);
 484
 485 static void pps_lock(struct intel_dp *intel_dp)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 488
 489         /*
 490          * See intel_power_sequencer_reset() why we need
 491          * a power domain reference here.
 492          */
 493         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 494
 495         mutex_lock(&dev_priv->pps_mutex);
 496 }
 497
 498 static void pps_unlock(struct intel_dp *intel_dp)
 499 {
 500         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 501
 502         mutex_unlock(&dev_priv->pps_mutex);
 503
 504         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 505 }
 506
 507 static void
 508 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 509 {
 510         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 511         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 512         enum pipe pipe = intel_dp->pps_pipe;
 513         bool pll_enabled, release_cl_override = false;
 514         enum dpio_phy phy = DPIO_PHY(pipe);
 515         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 516         uint32_t DP;
 517
 518         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 519                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 520                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 521                 return;
 522
 523         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 524                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 525
 526         /* Preserve the BIOS-computed detected bit. This is
 527          * supposed to be read-only.
 528          */
 529         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 530         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 531         DP |= DP_PORT_WIDTH(1);
 532         DP |= DP_LINK_TRAIN_PAT_1;
 533
 534         if (IS_CHERRYVIEW(dev_priv))
 535                 DP |= DP_PIPE_SELECT_CHV(pipe);
 536         else if (pipe == PIPE_B)
 537                 DP |= DP_PIPEB_SELECT;
 538
 539         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 540
 541         /*
 542          * The DPLL for the pipe must be enabled for this to work.
 543          * So enable temporarily it if it's not already enabled.
 544          */
 545         if (!pll_enabled) {
 546                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 547                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 548
 549                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 550                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 551                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 552                                   pipe_name(pipe));
 553                         return;
 554                 }
 555         }
 556
 557         /*
 558          * Similar magic as in intel_dp_enable_port().
 559          * We _must_ do this port enable + disable trick
 560          * to make this power seqeuencer lock onto the port.
 561          * Otherwise even VDD force bit won't work.
 562          */
 563         I915_WRITE(intel_dp->output_reg, DP);
 564         POSTING_READ(intel_dp->output_reg);
 565
 566         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 567         POSTING_READ(intel_dp->output_reg);
 568
 569         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 570         POSTING_READ(intel_dp->output_reg);
 571
 572         if (!pll_enabled) {
 573                 vlv_force_pll_off(dev_priv, pipe);
 574
 575                 if (release_cl_override)
 576                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 577         }
 578 }
 579
 580 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 581 {
 582         struct intel_encoder *encoder;
 583         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 584
 585         /*
 586          * We don't have power sequencer currently.
 587          * Pick one that's not used by other ports.
 588          */
 589         for_each_intel_encoder(&dev_priv->drm, encoder) {
 590                 struct intel_dp *intel_dp;
 591
 592                 if (encoder->type != INTEL_OUTPUT_DP &&
 593                     encoder->type != INTEL_OUTPUT_EDP)
 594                         continue;
 595
 596                 intel_dp = enc_to_intel_dp(&encoder->base);
 597
 598                 if (encoder->type == INTEL_OUTPUT_EDP) {
 599                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 600                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 601
 602                         if (intel_dp->pps_pipe != INVALID_PIPE)
 603                                 pipes &= ~(1 << intel_dp->pps_pipe);
 604                 } else {
 605                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 606
 607                         if (intel_dp->active_pipe != INVALID_PIPE)
 608                                 pipes &= ~(1 << intel_dp->active_pipe);
 609                 }
 610         }
 611
 612         if (pipes == 0)
 613                 return INVALID_PIPE;
 614
 615         return ffs(pipes) - 1;
 616 }
 617
 618 static enum pipe
 619 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 620 {
 621         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 622         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 623         enum pipe pipe;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         /* We should never land here with regular DP ports */
 628         WARN_ON(!intel_dp_is_edp(intel_dp));
 629
 630         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 631                 intel_dp->active_pipe != intel_dp->pps_pipe);
 632
 633         if (intel_dp->pps_pipe != INVALID_PIPE)
 634                 return intel_dp->pps_pipe;
 635
 636         pipe = vlv_find_free_pps(dev_priv);
 637
 638         /*
 639          * Didn't find one. This should not happen since there
 640          * are two power sequencers and up to two eDP ports.
 641          */
 642         if (WARN_ON(pipe == INVALID_PIPE))
 643                 pipe = PIPE_A;
 644
 645         vlv_steal_power_sequencer(dev_priv, pipe);
 646         intel_dp->pps_pipe = pipe;
 647
 648         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 649                       pipe_name(intel_dp->pps_pipe),
 650                       port_name(intel_dig_port->base.port));
 651
 652         /* init power sequencer on this pipe and port */
 653         intel_dp_init_panel_power_sequencer(intel_dp);
 654         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 655
 656         /*
 657          * Even vdd force doesn't work until we've made
 658          * the power sequencer lock in on the port.
 659          */
 660         vlv_power_sequencer_kick(intel_dp);
 661
 662         return intel_dp->pps_pipe;
 663 }
 664
 665 static int
 666 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 667 {
 668         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 669         int backlight_controller = dev_priv->vbt.backlight.controller;
 670
 671         lockdep_assert_held(&dev_priv->pps_mutex);
 672
 673         /* We should never land here with regular DP ports */
 674         WARN_ON(!intel_dp_is_edp(intel_dp));
 675
 676         if (!intel_dp->pps_reset)
 677                 return backlight_controller;
 678
 679         intel_dp->pps_reset = false;
 680
 681         /*
 682          * Only the HW needs to be reprogrammed, the SW state is fixed and
 683          * has been setup during connector init.
 684          */
 685         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 686
 687         return backlight_controller;
 688 }
 689
 690 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 691                                enum pipe pipe);
 692
 693 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 694                                enum pipe pipe)
 695 {
 696         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 697 }
 698
 699 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 700                                 enum pipe pipe)
 701 {
 702         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 703 }
 704
 705 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 706                          enum pipe pipe)
 707 {
 708         return true;
 709 }
 710
 711 static enum pipe
 712 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 713                      enum port port,
 714                      vlv_pipe_check pipe_check)
 715 {
 716         enum pipe pipe;
 717
 718         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 719                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 720                         PANEL_PORT_SELECT_MASK;
 721
 722                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 723                         continue;
 724
 725                 if (!pipe_check(dev_priv, pipe))
 726                         continue;
 727
 728                 return pipe;
 729         }
 730
 731         return INVALID_PIPE;
 732 }
 733
 734 static void
 735 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 736 {
 737         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 738         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 739         enum port port = intel_dig_port->base.port;
 740
 741         lockdep_assert_held(&dev_priv->pps_mutex);
 742
 743         /* try to find a pipe with this port selected */
 744         /* first pick one where the panel is on */
 745         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 746                                                   vlv_pipe_has_pp_on);
 747         /* didn't find one? pick one where vdd is on */
 748         if (intel_dp->pps_pipe == INVALID_PIPE)
 749                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 750                                                           vlv_pipe_has_vdd_on);
 751         /* didn't find one? pick one with just the correct port */
 752         if (intel_dp->pps_pipe == INVALID_PIPE)
 753                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 754                                                           vlv_pipe_any);
 755
 756         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 757         if (intel_dp->pps_pipe == INVALID_PIPE) {
 758                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 759                               port_name(port));
 760                 return;
 761         }
 762
 763         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 764                       port_name(port), pipe_name(intel_dp->pps_pipe));
 765
 766         intel_dp_init_panel_power_sequencer(intel_dp);
 767         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 768 }
 769
 770 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 771 {
 772         struct intel_encoder *encoder;
 773
 774         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 775                     !IS_GEN9_LP(dev_priv)))
 776                 return;
 777
 778         /*
 779          * We can't grab pps_mutex here due to deadlock with power_domain
 780          * mutex when power_domain functions are called while holding pps_mutex.
 781          * That also means that in order to use pps_pipe the code needs to
 782          * hold both a power domain reference and pps_mutex, and the power domain
 783          * reference get/put must be done while _not_ holding pps_mutex.
 784          * pps_{lock,unlock}() do these steps in the correct order, so one
 785          * should use them always.
 786          */
 787
 788         for_each_intel_encoder(&dev_priv->drm, encoder) {
 789                 struct intel_dp *intel_dp;
 790
 791                 if (encoder->type != INTEL_OUTPUT_DP &&
 792                     encoder->type != INTEL_OUTPUT_EDP &&
 793                     encoder->type != INTEL_OUTPUT_DDI)
 794                         continue;
 795
 796                 intel_dp = enc_to_intel_dp(&encoder->base);
 797
 798                 /* Skip pure DVI/HDMI DDI encoders */
 799                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 800                         continue;
 801
 802                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 803
 804                 if (encoder->type != INTEL_OUTPUT_EDP)
 805                         continue;
 806
 807                 if (IS_GEN9_LP(dev_priv))
 808                         intel_dp->pps_reset = true;
 809                 else
 810                         intel_dp->pps_pipe = INVALID_PIPE;
 811         }
 812 }
 813
 814 struct pps_registers {
 815         i915_reg_t pp_ctrl;
 816         i915_reg_t pp_stat;
 817         i915_reg_t pp_on;
 818         i915_reg_t pp_off;
 819         i915_reg_t pp_div;
 820 };
 821
 822 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 823                                     struct pps_registers *regs)
 824 {
 825         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 826         int pps_idx = 0;
 827
 828         memset(regs, 0, sizeof(*regs));
 829
 830         if (IS_GEN9_LP(dev_priv))
 831                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 832         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 833                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 834
 835         regs->pp_ctrl = PP_CONTROL(pps_idx);
 836         regs->pp_stat = PP_STATUS(pps_idx);
 837         regs->pp_on = PP_ON_DELAYS(pps_idx);
 838         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 839         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 840             !HAS_PCH_ICP(dev_priv))
 841                 regs->pp_div = PP_DIVISOR(pps_idx);
 842 }
 843
 844 static i915_reg_t
 845 _pp_ctrl_reg(struct intel_dp *intel_dp)
 846 {
 847         struct pps_registers regs;
 848
 849         intel_pps_get_registers(intel_dp, &regs);
 850
 851         return regs.pp_ctrl;
 852 }
 853
 854 static i915_reg_t
 855 _pp_stat_reg(struct intel_dp *intel_dp)
 856 {
 857         struct pps_registers regs;
 858
 859         intel_pps_get_registers(intel_dp, &regs);
 860
 861         return regs.pp_stat;
 862 }
 863
 864 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 865    This function only applicable when panel PM state is not to be tracked */
 866 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 867                               void *unused)
 868 {
 869         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 870                                                  edp_notifier);
 871         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 872
 873         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 874                 return 0;
 875
 876         pps_lock(intel_dp);
 877
 878         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 879                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 880                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 881                 u32 pp_div;
 882
 883                 pp_ctrl_reg = PP_CONTROL(pipe);
 884                 pp_div_reg  = PP_DIVISOR(pipe);
 885                 pp_div = I915_READ(pp_div_reg);
 886                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 887
 888                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 889                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 890                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 891                 msleep(intel_dp->panel_power_cycle_delay);
 892         }
 893
 894         pps_unlock(intel_dp);
 895
 896         return 0;
 897 }
 898
 899 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 902
 903         lockdep_assert_held(&dev_priv->pps_mutex);
 904
 905         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 906             intel_dp->pps_pipe == INVALID_PIPE)
 907                 return false;
 908
 909         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 910 }
 911
 912 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 913 {
 914         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 915
 916         lockdep_assert_held(&dev_priv->pps_mutex);
 917
 918         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 919             intel_dp->pps_pipe == INVALID_PIPE)
 920                 return false;
 921
 922         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 923 }
 924
 925 static void
 926 intel_dp_check_edp(struct intel_dp *intel_dp)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 929
 930         if (!intel_dp_is_edp(intel_dp))
 931                 return;
 932
 933         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 934                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 935                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 936                               I915_READ(_pp_stat_reg(intel_dp)),
 937                               I915_READ(_pp_ctrl_reg(intel_dp)));
 938         }
 939 }
 940
 941 static uint32_t
 942 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 945         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 946         uint32_t status;
 947         bool done;
 948
 949 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 950         if (has_aux_irq)
 951                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 952                                           msecs_to_jiffies_timeout(10));
 953         else
 954                 done = wait_for(C, 10) == 0;
 955         if (!done)
 956                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 957                           has_aux_irq);
 958 #undef C
 959
 960         return status;
 961 }
 962
 963 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 966
 967         if (index)
 968                 return 0;
 969
 970         /*
 971          * The clock divider is based off the hrawclk, and would like to run at
 972          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 973          */
 974         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 975 }
 976
 977 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 978 {
 979         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 980
 981         if (index)
 982                 return 0;
 983
 984         /*
 985          * The clock divider is based off the cdclk or PCH rawclk, and would
 986          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 987          * divide by 2000 and use that
 988          */
 989         if (intel_dp->aux_ch == AUX_CH_A)
 990                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 991         else
 992                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 993 }
 994
 995 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 996 {
 997         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 998
 999         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1000                 /* Workaround for non-ULT HSW */
1001                 switch (index) {
1002                 case 0: return 63;
1003                 case 1: return 72;
1004                 default: return 0;
1005                 }
1006         }
1007
1008         return ilk_get_aux_clock_divider(intel_dp, index);
1009 }
1010
1011 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1012 {
1013         /*
1014          * SKL doesn't need us to program the AUX clock divider (Hardware will
1015          * derive the clock from CDCLK automatically). We still implement the
1016          * get_aux_clock_divider vfunc to plug-in into the existing code.
1017          */
1018         return index ? 0 : 1;
1019 }
1020
1021 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1022                                      bool has_aux_irq,
1023                                      int send_bytes,
1024                                      uint32_t aux_clock_divider)
1025 {
1026         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1027         struct drm_i915_private *dev_priv =
1028                         to_i915(intel_dig_port->base.base.dev);
1029         uint32_t precharge, timeout;
1030
1031         if (IS_GEN6(dev_priv))
1032                 precharge = 3;
1033         else
1034                 precharge = 5;
1035
1036         if (IS_BROADWELL(dev_priv))
1037                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1038         else
1039                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1040
1041         return DP_AUX_CH_CTL_SEND_BUSY |
1042                DP_AUX_CH_CTL_DONE |
1043                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1044                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1045                timeout |
1046                DP_AUX_CH_CTL_RECEIVE_ERROR |
1047                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1048                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1049                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1050 }
1051
1052 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1053                                       bool has_aux_irq,
1054                                       int send_bytes,
1055                                       uint32_t unused)
1056 {
1057         return DP_AUX_CH_CTL_SEND_BUSY |
1058                DP_AUX_CH_CTL_DONE |
1059                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1060                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1061                DP_AUX_CH_CTL_TIME_OUT_MAX |
1062                DP_AUX_CH_CTL_RECEIVE_ERROR |
1063                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1064                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1065                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1066 }
1067
1068 static int
1069 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1070                   const uint8_t *send, int send_bytes,
1071                   uint8_t *recv, int recv_size,
1072                   u32 aux_send_ctl_flags)
1073 {
1074         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1075         struct drm_i915_private *dev_priv =
1076                         to_i915(intel_dig_port->base.base.dev);
1077         i915_reg_t ch_ctl, ch_data[5];
1078         uint32_t aux_clock_divider;
1079         int i, ret, recv_bytes;
1080         uint32_t status;
1081         int try, clock = 0;
1082         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1083         bool vdd;
1084
1085         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1086         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1087                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1088
1089         pps_lock(intel_dp);
1090
1091         /*
1092          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1093          * In such cases we want to leave VDD enabled and it's up to upper layers
1094          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1095          * ourselves.
1096          */
1097         vdd = edp_panel_vdd_on(intel_dp);
1098
1099         /* dp aux is extremely sensitive to irq latency, hence request the
1100          * lowest possible wakeup latency and so prevent the cpu from going into
1101          * deep sleep states.
1102          */
1103         pm_qos_update_request(&dev_priv->pm_qos, 0);
1104
1105         intel_dp_check_edp(intel_dp);
1106
1107         /* Try to wait for any previous AUX channel activity */
1108         for (try = 0; try < 3; try++) {
1109                 status = I915_READ_NOTRACE(ch_ctl);
1110                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1111                         break;
1112                 msleep(1);
1113         }
1114
1115         if (try == 3) {
1116                 static u32 last_status = -1;
1117                 const u32 status = I915_READ(ch_ctl);
1118
1119                 if (status != last_status) {
1120                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1121                              status);
1122                         last_status = status;
1123                 }
1124
1125                 ret = -EBUSY;
1126                 goto out;
1127         }
1128
1129         /* Only 5 data registers! */
1130         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1131                 ret = -E2BIG;
1132                 goto out;
1133         }
1134
1135         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1136                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1137                                                           has_aux_irq,
1138                                                           send_bytes,
1139                                                           aux_clock_divider);
1140
1141                 send_ctl |= aux_send_ctl_flags;
1142
1143                 /* Must try at least 3 times according to DP spec */
1144                 for (try = 0; try < 5; try++) {
1145                         /* Load the send data into the aux channel data registers */
1146                         for (i = 0; i < send_bytes; i += 4)
1147                                 I915_WRITE(ch_data[i >> 2],
1148                                            intel_dp_pack_aux(send + i,
1149                                                              send_bytes - i));
1150
1151                         /* Send the command and wait for it to complete */
1152                         I915_WRITE(ch_ctl, send_ctl);
1153
1154                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1155
1156                         /* Clear done status and any errors */
1157                         I915_WRITE(ch_ctl,
1158                                    status |
1159                                    DP_AUX_CH_CTL_DONE |
1160                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1161                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1162
1163                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1164                          *   400us delay required for errors and timeouts
1165                          *   Timeout errors from the HW already meet this
1166                          *   requirement so skip to next iteration
1167                          */
1168                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1169                                 continue;
1170
1171                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1172                                 usleep_range(400, 500);
1173                                 continue;
1174                         }
1175                         if (status & DP_AUX_CH_CTL_DONE)
1176                                 goto done;
1177                 }
1178         }
1179
1180         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1181                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1182                 ret = -EBUSY;
1183                 goto out;
1184         }
1185
1186 done:
1187         /* Check for timeout or receive error.
1188          * Timeouts occur when the sink is not connected
1189          */
1190         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1191                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1192                 ret = -EIO;
1193                 goto out;
1194         }
1195
1196         /* Timeouts occur when the device isn't connected, so they're
1197          * "normal" -- don't fill the kernel log with these */
1198         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1199                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1200                 ret = -ETIMEDOUT;
1201                 goto out;
1202         }
1203
1204         /* Unload any bytes sent back from the other side */
1205         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1206                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1207
1208         /*
1209          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1210          * We have no idea of what happened so we return -EBUSY so
1211          * drm layer takes care for the necessary retries.
1212          */
1213         if (recv_bytes == 0 || recv_bytes > 20) {
1214                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1215                               recv_bytes);
1216                 ret = -EBUSY;
1217                 goto out;
1218         }
1219
1220         if (recv_bytes > recv_size)
1221                 recv_bytes = recv_size;
1222
1223         for (i = 0; i < recv_bytes; i += 4)
1224                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1225                                     recv + i, recv_bytes - i);
1226
1227         ret = recv_bytes;
1228 out:
1229         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1230
1231         if (vdd)
1232                 edp_panel_vdd_off(intel_dp, false);
1233
1234         pps_unlock(intel_dp);
1235
1236         return ret;
1237 }
1238
1239 #define BARE_ADDRESS_SIZE       3
1240 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1241
1242 static void
1243 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1244                     const struct drm_dp_aux_msg *msg)
1245 {
1246         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1247         txbuf[1] = (msg->address >> 8) & 0xff;
1248         txbuf[2] = msg->address & 0xff;
1249         txbuf[3] = msg->size - 1;
1250 }
1251
1252 static ssize_t
1253 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1254 {
1255         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1256         uint8_t txbuf[20], rxbuf[20];
1257         size_t txsize, rxsize;
1258         int ret;
1259
1260         intel_dp_aux_header(txbuf, msg);
1261
1262         switch (msg->request & ~DP_AUX_I2C_MOT) {
1263         case DP_AUX_NATIVE_WRITE:
1264         case DP_AUX_I2C_WRITE:
1265         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1266                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1267                 rxsize = 2; /* 0 or 1 data bytes */
1268
1269                 if (WARN_ON(txsize > 20))
1270                         return -E2BIG;
1271
1272                 WARN_ON(!msg->buffer != !msg->size);
1273
1274                 if (msg->buffer)
1275                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1276
1277                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1278                                         rxbuf, rxsize, 0);
1279                 if (ret > 0) {
1280                         msg->reply = rxbuf[0] >> 4;
1281
1282                         if (ret > 1) {
1283                                 /* Number of bytes written in a short write. */
1284                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1285                         } else {
1286                                 /* Return payload size. */
1287                                 ret = msg->size;
1288                         }
1289                 }
1290                 break;
1291
1292         case DP_AUX_NATIVE_READ:
1293         case DP_AUX_I2C_READ:
1294                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1295                 rxsize = msg->size + 1;
1296
1297                 if (WARN_ON(rxsize > 20))
1298                         return -E2BIG;
1299
1300                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1301                                         rxbuf, rxsize, 0);
1302                 if (ret > 0) {
1303                         msg->reply = rxbuf[0] >> 4;
1304                         /*
1305                          * Assume happy day, and copy the data. The caller is
1306                          * expected to check msg->reply before touching it.
1307                          *
1308                          * Return payload size.
1309                          */
1310                         ret--;
1311                         memcpy(msg->buffer, rxbuf + 1, ret);
1312                 }
1313                 break;
1314
1315         default:
1316                 ret = -EINVAL;
1317                 break;
1318         }
1319
1320         return ret;
1321 }
1322
1323 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1324 {
1325         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1326         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1327         enum port port = encoder->port;
1328         const struct ddi_vbt_port_info *info =
1329                 &dev_priv->vbt.ddi_port_info[port];
1330         enum aux_ch aux_ch;
1331
1332         if (!info->alternate_aux_channel) {
1333                 aux_ch = (enum aux_ch) port;
1334
1335                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1336                               aux_ch_name(aux_ch), port_name(port));
1337                 return aux_ch;
1338         }
1339
1340         switch (info->alternate_aux_channel) {
1341         case DP_AUX_A:
1342                 aux_ch = AUX_CH_A;
1343                 break;
1344         case DP_AUX_B:
1345                 aux_ch = AUX_CH_B;
1346                 break;
1347         case DP_AUX_C:
1348                 aux_ch = AUX_CH_C;
1349                 break;
1350         case DP_AUX_D:
1351                 aux_ch = AUX_CH_D;
1352                 break;
1353         case DP_AUX_F:
1354                 aux_ch = AUX_CH_F;
1355                 break;
1356         default:
1357                 MISSING_CASE(info->alternate_aux_channel);
1358                 aux_ch = AUX_CH_A;
1359                 break;
1360         }
1361
1362         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1363                       aux_ch_name(aux_ch), port_name(port));
1364
1365         return aux_ch;
1366 }
1367
1368 static enum intel_display_power_domain
1369 intel_aux_power_domain(struct intel_dp *intel_dp)
1370 {
1371         switch (intel_dp->aux_ch) {
1372         case AUX_CH_A:
1373                 return POWER_DOMAIN_AUX_A;
1374         case AUX_CH_B:
1375                 return POWER_DOMAIN_AUX_B;
1376         case AUX_CH_C:
1377                 return POWER_DOMAIN_AUX_C;
1378         case AUX_CH_D:
1379                 return POWER_DOMAIN_AUX_D;
1380         case AUX_CH_F:
1381                 return POWER_DOMAIN_AUX_F;
1382         default:
1383                 MISSING_CASE(intel_dp->aux_ch);
1384                 return POWER_DOMAIN_AUX_A;
1385         }
1386 }
1387
1388 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1391         enum aux_ch aux_ch = intel_dp->aux_ch;
1392
1393         switch (aux_ch) {
1394         case AUX_CH_B:
1395         case AUX_CH_C:
1396         case AUX_CH_D:
1397                 return DP_AUX_CH_CTL(aux_ch);
1398         default:
1399                 MISSING_CASE(aux_ch);
1400                 return DP_AUX_CH_CTL(AUX_CH_B);
1401         }
1402 }
1403
1404 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1405 {
1406         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1407         enum aux_ch aux_ch = intel_dp->aux_ch;
1408
1409         switch (aux_ch) {
1410         case AUX_CH_B:
1411         case AUX_CH_C:
1412         case AUX_CH_D:
1413                 return DP_AUX_CH_DATA(aux_ch, index);
1414         default:
1415                 MISSING_CASE(aux_ch);
1416                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1417         }
1418 }
1419
1420 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1421 {
1422         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1423         enum aux_ch aux_ch = intel_dp->aux_ch;
1424
1425         switch (aux_ch) {
1426         case AUX_CH_A:
1427                 return DP_AUX_CH_CTL(aux_ch);
1428         case AUX_CH_B:
1429         case AUX_CH_C:
1430         case AUX_CH_D:
1431                 return PCH_DP_AUX_CH_CTL(aux_ch);
1432         default:
1433                 MISSING_CASE(aux_ch);
1434                 return DP_AUX_CH_CTL(AUX_CH_A);
1435         }
1436 }
1437
1438 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1441         enum aux_ch aux_ch = intel_dp->aux_ch;
1442
1443         switch (aux_ch) {
1444         case AUX_CH_A:
1445                 return DP_AUX_CH_DATA(aux_ch, index);
1446         case AUX_CH_B:
1447         case AUX_CH_C:
1448         case AUX_CH_D:
1449                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1450         default:
1451                 MISSING_CASE(aux_ch);
1452                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1453         }
1454 }
1455
1456 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1457 {
1458         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1459         enum aux_ch aux_ch = intel_dp->aux_ch;
1460
1461         switch (aux_ch) {
1462         case AUX_CH_A:
1463         case AUX_CH_B:
1464         case AUX_CH_C:
1465         case AUX_CH_D:
1466         case AUX_CH_F:
1467                 return DP_AUX_CH_CTL(aux_ch);
1468         default:
1469                 MISSING_CASE(aux_ch);
1470                 return DP_AUX_CH_CTL(AUX_CH_A);
1471         }
1472 }
1473
1474 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1475 {
1476         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1477         enum aux_ch aux_ch = intel_dp->aux_ch;
1478
1479         switch (aux_ch) {
1480         case AUX_CH_A:
1481         case AUX_CH_B:
1482         case AUX_CH_C:
1483         case AUX_CH_D:
1484         case AUX_CH_F:
1485                 return DP_AUX_CH_DATA(aux_ch, index);
1486         default:
1487                 MISSING_CASE(aux_ch);
1488                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1489         }
1490 }
1491
1492 static void
1493 intel_dp_aux_fini(struct intel_dp *intel_dp)
1494 {
1495         kfree(intel_dp->aux.name);
1496 }
1497
1498 static void
1499 intel_dp_aux_init(struct intel_dp *intel_dp)
1500 {
1501         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1502         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1503
1504         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1505         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1506
1507         if (INTEL_GEN(dev_priv) >= 9) {
1508                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1509                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1510         } else if (HAS_PCH_SPLIT(dev_priv)) {
1511                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1512                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1513         } else {
1514                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1515                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1516         }
1517
1518         if (INTEL_GEN(dev_priv) >= 9)
1519                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1520         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1521                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1522         else if (HAS_PCH_SPLIT(dev_priv))
1523                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1524         else
1525                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1526
1527         if (INTEL_GEN(dev_priv) >= 9)
1528                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1529         else
1530                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1531
1532         drm_dp_aux_init(&intel_dp->aux);
1533
1534         /* Failure to allocate our preferred name is not critical */
1535         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1536                                        port_name(encoder->port));
1537         intel_dp->aux.transfer = intel_dp_aux_transfer;
1538 }
1539
1540 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1541 {
1542         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1543
1544         return max_rate >= 540000;
1545 }
1546
1547 static void
1548 intel_dp_set_clock(struct intel_encoder *encoder,
1549                    struct intel_crtc_state *pipe_config)
1550 {
1551         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1552         const struct dp_link_dpll *divisor = NULL;
1553         int i, count = 0;
1554
1555         if (IS_G4X(dev_priv)) {
1556                 divisor = gen4_dpll;
1557                 count = ARRAY_SIZE(gen4_dpll);
1558         } else if (HAS_PCH_SPLIT(dev_priv)) {
1559                 divisor = pch_dpll;
1560                 count = ARRAY_SIZE(pch_dpll);
1561         } else if (IS_CHERRYVIEW(dev_priv)) {
1562                 divisor = chv_dpll;
1563                 count = ARRAY_SIZE(chv_dpll);
1564         } else if (IS_VALLEYVIEW(dev_priv)) {
1565                 divisor = vlv_dpll;
1566                 count = ARRAY_SIZE(vlv_dpll);
1567         }
1568
1569         if (divisor && count) {
1570                 for (i = 0; i < count; i++) {
1571                         if (pipe_config->port_clock == divisor[i].clock) {
1572                                 pipe_config->dpll = divisor[i].dpll;
1573                                 pipe_config->clock_set = true;
1574                                 break;
1575                         }
1576                 }
1577         }
1578 }
1579
1580 static void snprintf_int_array(char *str, size_t len,
1581                                const int *array, int nelem)
1582 {
1583         int i;
1584
1585         str[0] = '\0';
1586
1587         for (i = 0; i < nelem; i++) {
1588                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1589                 if (r >= len)
1590                         return;
1591                 str += r;
1592                 len -= r;
1593         }
1594 }
1595
1596 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1597 {
1598         char str[128]; /* FIXME: too big for stack? */
1599
1600         if ((drm_debug & DRM_UT_KMS) == 0)
1601                 return;
1602
1603         snprintf_int_array(str, sizeof(str),
1604                            intel_dp->source_rates, intel_dp->num_source_rates);
1605         DRM_DEBUG_KMS("source rates: %s\n", str);
1606
1607         snprintf_int_array(str, sizeof(str),
1608                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1609         DRM_DEBUG_KMS("sink rates: %s\n", str);
1610
1611         snprintf_int_array(str, sizeof(str),
1612                            intel_dp->common_rates, intel_dp->num_common_rates);
1613         DRM_DEBUG_KMS("common rates: %s\n", str);
1614 }
1615
1616 int
1617 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1618 {
1619         int len;
1620
1621         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1622         if (WARN_ON(len <= 0))
1623                 return 162000;
1624
1625         return intel_dp->common_rates[len - 1];
1626 }
1627
1628 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1629 {
1630         int i = intel_dp_rate_index(intel_dp->sink_rates,
1631                                     intel_dp->num_sink_rates, rate);
1632
1633         if (WARN_ON(i < 0))
1634                 i = 0;
1635
1636         return i;
1637 }
1638
1639 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1640                            uint8_t *link_bw, uint8_t *rate_select)
1641 {
1642         /* eDP 1.4 rate select method. */
1643         if (intel_dp->use_rate_select) {
1644                 *link_bw = 0;
1645                 *rate_select =
1646                         intel_dp_rate_select(intel_dp, port_clock);
1647         } else {
1648                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1649                 *rate_select = 0;
1650         }
1651 }
1652
1653 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1654                                 struct intel_crtc_state *pipe_config)
1655 {
1656         int bpp, bpc;
1657
1658         bpp = pipe_config->pipe_bpp;
1659         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1660
1661         if (bpc > 0)
1662                 bpp = min(bpp, 3*bpc);
1663
1664         /* For DP Compliance we override the computed bpp for the pipe */
1665         if (intel_dp->compliance.test_data.bpc != 0) {
1666                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1667                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1668                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1669                               pipe_config->pipe_bpp);
1670         }
1671         return bpp;
1672 }
1673
1674 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1675                                        struct drm_display_mode *m2)
1676 {
1677         bool bres = false;
1678
1679         if (m1 && m2)
1680                 bres = (m1->hdisplay == m2->hdisplay &&
1681                         m1->hsync_start == m2->hsync_start &&
1682                         m1->hsync_end == m2->hsync_end &&
1683                         m1->htotal == m2->htotal &&
1684                         m1->vdisplay == m2->vdisplay &&
1685                         m1->vsync_start == m2->vsync_start &&
1686                         m1->vsync_end == m2->vsync_end &&
1687                         m1->vtotal == m2->vtotal);
1688         return bres;
1689 }
1690
1691 bool
1692 intel_dp_compute_config(struct intel_encoder *encoder,
1693                         struct intel_crtc_state *pipe_config,
1694                         struct drm_connector_state *conn_state)
1695 {
1696         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1697         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1698         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1699         enum port port = encoder->port;
1700         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1701         struct intel_connector *intel_connector = intel_dp->attached_connector;
1702         struct intel_digital_connector_state *intel_conn_state =
1703                 to_intel_digital_connector_state(conn_state);
1704         int lane_count, clock;
1705         int min_lane_count = 1;
1706         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1707         /* Conveniently, the link BW constants become indices with a shift...*/
1708         int min_clock = 0;
1709         int max_clock;
1710         int bpp, mode_rate;
1711         int link_avail, link_clock;
1712         int common_len;
1713         uint8_t link_bw, rate_select;
1714         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1715                                            DP_DPCD_QUIRK_LIMITED_M_N);
1716
1717         common_len = intel_dp_common_len_rate_limit(intel_dp,
1718                                                     intel_dp->max_link_rate);
1719
1720         /* No common link rates between source and sink */
1721         WARN_ON(common_len <= 0);
1722
1723         max_clock = common_len - 1;
1724
1725         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1726                 pipe_config->has_pch_encoder = true;
1727
1728         pipe_config->has_drrs = false;
1729         if (IS_G4X(dev_priv) || port == PORT_A)
1730                 pipe_config->has_audio = false;
1731         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1732                 pipe_config->has_audio = intel_dp->has_audio;
1733         else
1734                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1735
1736         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1737                 struct drm_display_mode *panel_mode =
1738                         intel_connector->panel.alt_fixed_mode;
1739                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1740
1741                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1742                         panel_mode = intel_connector->panel.fixed_mode;
1743
1744                 drm_mode_debug_printmodeline(panel_mode);
1745
1746                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1747
1748                 if (INTEL_GEN(dev_priv) >= 9) {
1749                         int ret;
1750                         ret = skl_update_scaler_crtc(pipe_config);
1751                         if (ret)
1752                                 return ret;
1753                 }
1754
1755                 if (HAS_GMCH_DISPLAY(dev_priv))
1756                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1757                                                  conn_state->scaling_mode);
1758                 else
1759                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1760                                                 conn_state->scaling_mode);
1761         }
1762
1763         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1764             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1765                 return false;
1766
1767         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1768                 return false;
1769
1770         /* Use values requested by Compliance Test Request */
1771         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1772                 int index;
1773
1774                 /* Validate the compliance test data since max values
1775                  * might have changed due to link train fallback.
1776                  */
1777                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1778                                                intel_dp->compliance.test_lane_count)) {
1779                         index = intel_dp_rate_index(intel_dp->common_rates,
1780                                                     intel_dp->num_common_rates,
1781                                                     intel_dp->compliance.test_link_rate);
1782                         if (index >= 0)
1783                                 min_clock = max_clock = index;
1784                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1785                 }
1786         }
1787         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1788                       "max bw %d pixel clock %iKHz\n",
1789                       max_lane_count, intel_dp->common_rates[max_clock],
1790                       adjusted_mode->crtc_clock);
1791
1792         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1793          * bpc in between. */
1794         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1795         if (intel_dp_is_edp(intel_dp)) {
1796
1797                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1798                 if (intel_connector->base.display_info.bpc == 0 &&
1799                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1800                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1801                                       dev_priv->vbt.edp.bpp);
1802                         bpp = dev_priv->vbt.edp.bpp;
1803                 }
1804
1805                 /*
1806                  * Use the maximum clock and number of lanes the eDP panel
1807                  * advertizes being capable of. The panels are generally
1808                  * designed to support only a single clock and lane
1809                  * configuration, and typically these values correspond to the
1810                  * native resolution of the panel.
1811                  */
1812                 min_lane_count = max_lane_count;
1813                 min_clock = max_clock;
1814         }
1815
1816         for (; bpp >= 6*3; bpp -= 2*3) {
1817                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1818                                                    bpp);
1819
1820                 for (clock = min_clock; clock <= max_clock; clock++) {
1821                         for (lane_count = min_lane_count;
1822                                 lane_count <= max_lane_count;
1823                                 lane_count <<= 1) {
1824
1825                                 link_clock = intel_dp->common_rates[clock];
1826                                 link_avail = intel_dp_max_data_rate(link_clock,
1827                                                                     lane_count);
1828
1829                                 if (mode_rate <= link_avail) {
1830                                         goto found;
1831                                 }
1832                         }
1833                 }
1834         }
1835
1836         return false;
1837
1838 found:
1839         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1840                 /*
1841                  * See:
1842                  * CEA-861-E - 5.1 Default Encoding Parameters
1843                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1844                  */
1845                 pipe_config->limited_color_range =
1846                         bpp != 18 &&
1847                         drm_default_rgb_quant_range(adjusted_mode) ==
1848                         HDMI_QUANTIZATION_RANGE_LIMITED;
1849         } else {
1850                 pipe_config->limited_color_range =
1851                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1852         }
1853
1854         pipe_config->lane_count = lane_count;
1855
1856         pipe_config->pipe_bpp = bpp;
1857         pipe_config->port_clock = intel_dp->common_rates[clock];
1858
1859         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1860                               &link_bw, &rate_select);
1861
1862         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1863                       link_bw, rate_select, pipe_config->lane_count,
1864                       pipe_config->port_clock, bpp);
1865         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1866                       mode_rate, link_avail);
1867
1868         intel_link_compute_m_n(bpp, lane_count,
1869                                adjusted_mode->crtc_clock,
1870                                pipe_config->port_clock,
1871                                &pipe_config->dp_m_n,
1872                                reduce_m_n);
1873
1874         if (intel_connector->panel.downclock_mode != NULL &&
1875                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1876                         pipe_config->has_drrs = true;
1877                         intel_link_compute_m_n(bpp, lane_count,
1878                                 intel_connector->panel.downclock_mode->clock,
1879                                 pipe_config->port_clock,
1880                                 &pipe_config->dp_m2_n2,
1881                                 reduce_m_n);
1882         }
1883
1884         /*
1885          * DPLL0 VCO may need to be adjusted to get the correct
1886          * clock for eDP. This will affect cdclk as well.
1887          */
1888         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1889                 int vco;
1890
1891                 switch (pipe_config->port_clock / 2) {
1892                 case 108000:
1893                 case 216000:
1894                         vco = 8640000;
1895                         break;
1896                 default:
1897                         vco = 8100000;
1898                         break;
1899                 }
1900
1901                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1902         }
1903
1904         if (!HAS_DDI(dev_priv))
1905                 intel_dp_set_clock(encoder, pipe_config);
1906
1907         intel_psr_compute_config(intel_dp, pipe_config);
1908
1909         return true;
1910 }
1911
1912 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1913                               int link_rate, uint8_t lane_count,
1914                               bool link_mst)
1915 {
1916         intel_dp->link_trained = false;
1917         intel_dp->link_rate = link_rate;
1918         intel_dp->lane_count = lane_count;
1919         intel_dp->link_mst = link_mst;
1920 }
1921
1922 static void intel_dp_prepare(struct intel_encoder *encoder,
1923                              const struct intel_crtc_state *pipe_config)
1924 {
1925         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1926         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1927         enum port port = encoder->port;
1928         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1929         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1930
1931         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1932                                  pipe_config->lane_count,
1933                                  intel_crtc_has_type(pipe_config,
1934                                                      INTEL_OUTPUT_DP_MST));
1935
1936         /*
1937          * There are four kinds of DP registers:
1938          *
1939          *      IBX PCH
1940          *      SNB CPU
1941          *      IVB CPU
1942          *      CPT PCH
1943          *
1944          * IBX PCH and CPU are the same for almost everything,
1945          * except that the CPU DP PLL is configured in this
1946          * register
1947          *
1948          * CPT PCH is quite different, having many bits moved
1949          * to the TRANS_DP_CTL register instead. That
1950          * configuration happens (oddly) in ironlake_pch_enable
1951          */
1952
1953         /* Preserve the BIOS-computed detected bit. This is
1954          * supposed to be read-only.
1955          */
1956         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1957
1958         /* Handle DP bits in common between all three register formats */
1959         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1960         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1961
1962         /* Split out the IBX/CPU vs CPT settings */
1963
1964         if (IS_GEN7(dev_priv) && port == PORT_A) {
1965                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1966                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1967                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1968                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1969                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1970
1971                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1972                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1973
1974                 intel_dp->DP |= crtc->pipe << 29;
1975         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1976                 u32 trans_dp;
1977
1978                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1979
1980                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1981                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1982                         trans_dp |= TRANS_DP_ENH_FRAMING;
1983                 else
1984                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1985                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1986         } else {
1987                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1988                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1989
1990                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1991                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1992                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1993                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1994                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1995
1996                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1997                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1998
1999                 if (IS_CHERRYVIEW(dev_priv))
2000                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
2001                 else if (crtc->pipe == PIPE_B)
2002                         intel_dp->DP |= DP_PIPEB_SELECT;
2003         }
2004 }
2005
2006 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2007 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2008
2009 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2010 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2011
2012 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2013 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2014
2015 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2016
2017 static void wait_panel_status(struct intel_dp *intel_dp,
2018                                        u32 mask,
2019                                        u32 value)
2020 {
2021         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2022         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2023
2024         lockdep_assert_held(&dev_priv->pps_mutex);
2025
2026         intel_pps_verify_state(intel_dp);
2027
2028         pp_stat_reg = _pp_stat_reg(intel_dp);
2029         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2030
2031         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2032                         mask, value,
2033                         I915_READ(pp_stat_reg),
2034                         I915_READ(pp_ctrl_reg));
2035
2036         if (intel_wait_for_register(dev_priv,
2037                                     pp_stat_reg, mask, value,
2038                                     5000))
2039                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2040                                 I915_READ(pp_stat_reg),
2041                                 I915_READ(pp_ctrl_reg));
2042
2043         DRM_DEBUG_KMS("Wait complete\n");
2044 }
2045
2046 static void wait_panel_on(struct intel_dp *intel_dp)
2047 {
2048         DRM_DEBUG_KMS("Wait for panel power on\n");
2049         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2050 }
2051
2052 static void wait_panel_off(struct intel_dp *intel_dp)
2053 {
2054         DRM_DEBUG_KMS("Wait for panel power off time\n");
2055         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2056 }
2057
2058 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2059 {
2060         ktime_t panel_power_on_time;
2061         s64 panel_power_off_duration;
2062
2063         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2064
2065         /* take the difference of currrent time and panel power off time
2066          * and then make panel wait for t11_t12 if needed. */
2067         panel_power_on_time = ktime_get_boottime();
2068         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2069
2070         /* When we disable the VDD override bit last we have to do the manual
2071          * wait. */
2072         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2073                 wait_remaining_ms_from_jiffies(jiffies,
2074                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2075
2076         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2077 }
2078
2079 static void wait_backlight_on(struct intel_dp *intel_dp)
2080 {
2081         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2082                                        intel_dp->backlight_on_delay);
2083 }
2084
2085 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2086 {
2087         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2088                                        intel_dp->backlight_off_delay);
2089 }
2090
2091 /* Read the current pp_control value, unlocking the register if it
2092  * is locked
2093  */
2094
2095 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2096 {
2097         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2098         u32 control;
2099
2100         lockdep_assert_held(&dev_priv->pps_mutex);
2101
2102         control = I915_READ(_pp_ctrl_reg(intel_dp));
2103         if (WARN_ON(!HAS_DDI(dev_priv) &&
2104                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2105                 control &= ~PANEL_UNLOCK_MASK;
2106                 control |= PANEL_UNLOCK_REGS;
2107         }
2108         return control;
2109 }
2110
2111 /*
2112  * Must be paired with edp_panel_vdd_off().
2113  * Must hold pps_mutex around the whole on/off sequence.
2114  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2115  */
2116 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2117 {
2118         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2119         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2120         u32 pp;
2121         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2122         bool need_to_disable = !intel_dp->want_panel_vdd;
2123
2124         lockdep_assert_held(&dev_priv->pps_mutex);
2125
2126         if (!intel_dp_is_edp(intel_dp))
2127                 return false;
2128
2129         cancel_delayed_work(&intel_dp->panel_vdd_work);
2130         intel_dp->want_panel_vdd = true;
2131
2132         if (edp_have_panel_vdd(intel_dp))
2133                 return need_to_disable;
2134
2135         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2136
2137         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2138                       port_name(intel_dig_port->base.port));
2139
2140         if (!edp_have_panel_power(intel_dp))
2141                 wait_panel_power_cycle(intel_dp);
2142
2143         pp = ironlake_get_pp_control(intel_dp);
2144         pp |= EDP_FORCE_VDD;
2145
2146         pp_stat_reg = _pp_stat_reg(intel_dp);
2147         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2148
2149         I915_WRITE(pp_ctrl_reg, pp);
2150         POSTING_READ(pp_ctrl_reg);
2151         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2152                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2153         /*
2154          * If the panel wasn't on, delay before accessing aux channel
2155          */
2156         if (!edp_have_panel_power(intel_dp)) {
2157                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2158                               port_name(intel_dig_port->base.port));
2159                 msleep(intel_dp->panel_power_up_delay);
2160         }
2161
2162         return need_to_disable;
2163 }
2164
2165 /*
2166  * Must be paired with intel_edp_panel_vdd_off() or
2167  * intel_edp_panel_off().
2168  * Nested calls to these functions are not allowed since
2169  * we drop the lock. Caller must use some higher level
2170  * locking to prevent nested calls from other threads.
2171  */
2172 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2173 {
2174         bool vdd;
2175
2176         if (!intel_dp_is_edp(intel_dp))
2177                 return;
2178
2179         pps_lock(intel_dp);
2180         vdd = edp_panel_vdd_on(intel_dp);
2181         pps_unlock(intel_dp);
2182
2183         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2184              port_name(dp_to_dig_port(intel_dp)->base.port));
2185 }
2186
2187 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2188 {
2189         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2190         struct intel_digital_port *intel_dig_port =
2191                 dp_to_dig_port(intel_dp);
2192         u32 pp;
2193         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2194
2195         lockdep_assert_held(&dev_priv->pps_mutex);
2196
2197         WARN_ON(intel_dp->want_panel_vdd);
2198
2199         if (!edp_have_panel_vdd(intel_dp))
2200                 return;
2201
2202         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2203                       port_name(intel_dig_port->base.port));
2204
2205         pp = ironlake_get_pp_control(intel_dp);
2206         pp &= ~EDP_FORCE_VDD;
2207
2208         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2209         pp_stat_reg = _pp_stat_reg(intel_dp);
2210
2211         I915_WRITE(pp_ctrl_reg, pp);
2212         POSTING_READ(pp_ctrl_reg);
2213
2214         /* Make sure sequencer is idle before allowing subsequent activity */
2215         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2216         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2217
2218         if ((pp & PANEL_POWER_ON) == 0)
2219                 intel_dp->panel_power_off_time = ktime_get_boottime();
2220
2221         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2222 }
2223
2224 static void edp_panel_vdd_work(struct work_struct *__work)
2225 {
2226         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2227                                                  struct intel_dp, panel_vdd_work);
2228
2229         pps_lock(intel_dp);
2230         if (!intel_dp->want_panel_vdd)
2231                 edp_panel_vdd_off_sync(intel_dp);
2232         pps_unlock(intel_dp);
2233 }
2234
2235 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2236 {
2237         unsigned long delay;
2238
2239         /*
2240          * Queue the timer to fire a long time from now (relative to the power
2241          * down delay) to keep the panel power up across a sequence of
2242          * operations.
2243          */
2244         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2245         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2246 }
2247
2248 /*
2249  * Must be paired with edp_panel_vdd_on().
2250  * Must hold pps_mutex around the whole on/off sequence.
2251  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2252  */
2253 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2254 {
2255         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2256
2257         lockdep_assert_held(&dev_priv->pps_mutex);
2258
2259         if (!intel_dp_is_edp(intel_dp))
2260                 return;
2261
2262         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2263              port_name(dp_to_dig_port(intel_dp)->base.port));
2264
2265         intel_dp->want_panel_vdd = false;
2266
2267         if (sync)
2268                 edp_panel_vdd_off_sync(intel_dp);
2269         else
2270                 edp_panel_vdd_schedule_off(intel_dp);
2271 }
2272
2273 static void edp_panel_on(struct intel_dp *intel_dp)
2274 {
2275         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2276         u32 pp;
2277         i915_reg_t pp_ctrl_reg;
2278
2279         lockdep_assert_held(&dev_priv->pps_mutex);
2280
2281         if (!intel_dp_is_edp(intel_dp))
2282                 return;
2283
2284         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2285                       port_name(dp_to_dig_port(intel_dp)->base.port));
2286
2287         if (WARN(edp_have_panel_power(intel_dp),
2288                  "eDP port %c panel power already on\n",
2289                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2290                 return;
2291
2292         wait_panel_power_cycle(intel_dp);
2293
2294         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2295         pp = ironlake_get_pp_control(intel_dp);
2296         if (IS_GEN5(dev_priv)) {
2297                 /* ILK workaround: disable reset around power sequence */
2298                 pp &= ~PANEL_POWER_RESET;
2299                 I915_WRITE(pp_ctrl_reg, pp);
2300                 POSTING_READ(pp_ctrl_reg);
2301         }
2302
2303         pp |= PANEL_POWER_ON;
2304         if (!IS_GEN5(dev_priv))
2305                 pp |= PANEL_POWER_RESET;
2306
2307         I915_WRITE(pp_ctrl_reg, pp);
2308         POSTING_READ(pp_ctrl_reg);
2309
2310         wait_panel_on(intel_dp);
2311         intel_dp->last_power_on = jiffies;
2312
2313         if (IS_GEN5(dev_priv)) {
2314                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2315                 I915_WRITE(pp_ctrl_reg, pp);
2316                 POSTING_READ(pp_ctrl_reg);
2317         }
2318 }
2319
2320 void intel_edp_panel_on(struct intel_dp *intel_dp)
2321 {
2322         if (!intel_dp_is_edp(intel_dp))
2323                 return;
2324
2325         pps_lock(intel_dp);
2326         edp_panel_on(intel_dp);
2327         pps_unlock(intel_dp);
2328 }
2329
2330
2331 static void edp_panel_off(struct intel_dp *intel_dp)
2332 {
2333         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2334         u32 pp;
2335         i915_reg_t pp_ctrl_reg;
2336
2337         lockdep_assert_held(&dev_priv->pps_mutex);
2338
2339         if (!intel_dp_is_edp(intel_dp))
2340                 return;
2341
2342         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2343                       port_name(dp_to_dig_port(intel_dp)->base.port));
2344
2345         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2346              port_name(dp_to_dig_port(intel_dp)->base.port));
2347
2348         pp = ironlake_get_pp_control(intel_dp);
2349         /* We need to switch off panel power _and_ force vdd, for otherwise some
2350          * panels get very unhappy and cease to work. */
2351         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2352                 EDP_BLC_ENABLE);
2353
2354         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2355
2356         intel_dp->want_panel_vdd = false;
2357
2358         I915_WRITE(pp_ctrl_reg, pp);
2359         POSTING_READ(pp_ctrl_reg);
2360
2361         wait_panel_off(intel_dp);
2362         intel_dp->panel_power_off_time = ktime_get_boottime();
2363
2364         /* We got a reference when we enabled the VDD. */
2365         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2366 }
2367
2368 void intel_edp_panel_off(struct intel_dp *intel_dp)
2369 {
2370         if (!intel_dp_is_edp(intel_dp))
2371                 return;
2372
2373         pps_lock(intel_dp);
2374         edp_panel_off(intel_dp);
2375         pps_unlock(intel_dp);
2376 }
2377
2378 /* Enable backlight in the panel power control. */
2379 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2380 {
2381         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2382         u32 pp;
2383         i915_reg_t pp_ctrl_reg;
2384
2385         /*
2386          * If we enable the backlight right away following a panel power
2387          * on, we may see slight flicker as the panel syncs with the eDP
2388          * link.  So delay a bit to make sure the image is solid before
2389          * allowing it to appear.
2390          */
2391         wait_backlight_on(intel_dp);
2392
2393         pps_lock(intel_dp);
2394
2395         pp = ironlake_get_pp_control(intel_dp);
2396         pp |= EDP_BLC_ENABLE;
2397
2398         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2399
2400         I915_WRITE(pp_ctrl_reg, pp);
2401         POSTING_READ(pp_ctrl_reg);
2402
2403         pps_unlock(intel_dp);
2404 }
2405
2406 /* Enable backlight PWM and backlight PP control. */
2407 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2408                             const struct drm_connector_state *conn_state)
2409 {
2410         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2411
2412         if (!intel_dp_is_edp(intel_dp))
2413                 return;
2414
2415         DRM_DEBUG_KMS("\n");
2416
2417         intel_panel_enable_backlight(crtc_state, conn_state);
2418         _intel_edp_backlight_on(intel_dp);
2419 }
2420
2421 /* Disable backlight in the panel power control. */
2422 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2423 {
2424         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2425         u32 pp;
2426         i915_reg_t pp_ctrl_reg;
2427
2428         if (!intel_dp_is_edp(intel_dp))
2429                 return;
2430
2431         pps_lock(intel_dp);
2432
2433         pp = ironlake_get_pp_control(intel_dp);
2434         pp &= ~EDP_BLC_ENABLE;
2435
2436         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2437
2438         I915_WRITE(pp_ctrl_reg, pp);
2439         POSTING_READ(pp_ctrl_reg);
2440
2441         pps_unlock(intel_dp);
2442
2443         intel_dp->last_backlight_off = jiffies;
2444         edp_wait_backlight_off(intel_dp);
2445 }
2446
2447 /* Disable backlight PP control and backlight PWM. */
2448 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2449 {
2450         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2451
2452         if (!intel_dp_is_edp(intel_dp))
2453                 return;
2454
2455         DRM_DEBUG_KMS("\n");
2456
2457         _intel_edp_backlight_off(intel_dp);
2458         intel_panel_disable_backlight(old_conn_state);
2459 }
2460
2461 /*
2462  * Hook for controlling the panel power control backlight through the bl_power
2463  * sysfs attribute. Take care to handle multiple calls.
2464  */
2465 static void intel_edp_backlight_power(struct intel_connector *connector,
2466                                       bool enable)
2467 {
2468         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2469         bool is_enabled;
2470
2471         pps_lock(intel_dp);
2472         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2473         pps_unlock(intel_dp);
2474
2475         if (is_enabled == enable)
2476                 return;
2477
2478         DRM_DEBUG_KMS("panel power control backlight %s\n",
2479                       enable ? "enable" : "disable");
2480
2481         if (enable)
2482                 _intel_edp_backlight_on(intel_dp);
2483         else
2484                 _intel_edp_backlight_off(intel_dp);
2485 }
2486
2487 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2488 {
2489         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2490         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2491         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2492
2493         I915_STATE_WARN(cur_state != state,
2494                         "DP port %c state assertion failure (expected %s, current %s)\n",
2495                         port_name(dig_port->base.port),
2496                         onoff(state), onoff(cur_state));
2497 }
2498 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2499
2500 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2501 {
2502         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2503
2504         I915_STATE_WARN(cur_state != state,
2505                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2506                         onoff(state), onoff(cur_state));
2507 }
2508 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2509 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2510
2511 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2512                                 const struct intel_crtc_state *pipe_config)
2513 {
2514         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2515         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2516
2517         assert_pipe_disabled(dev_priv, crtc->pipe);
2518         assert_dp_port_disabled(intel_dp);
2519         assert_edp_pll_disabled(dev_priv);
2520
2521         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2522                       pipe_config->port_clock);
2523
2524         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2525
2526         if (pipe_config->port_clock == 162000)
2527                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2528         else
2529                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2530
2531         I915_WRITE(DP_A, intel_dp->DP);
2532         POSTING_READ(DP_A);
2533         udelay(500);
2534
2535         /*
2536          * [DevILK] Work around required when enabling DP PLL
2537          * while a pipe is enabled going to FDI:
2538          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2539          * 2. Program DP PLL enable
2540          */
2541         if (IS_GEN5(dev_priv))
2542                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2543
2544         intel_dp->DP |= DP_PLL_ENABLE;
2545
2546         I915_WRITE(DP_A, intel_dp->DP);
2547         POSTING_READ(DP_A);
2548         udelay(200);
2549 }
2550
2551 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2552                                  const struct intel_crtc_state *old_crtc_state)
2553 {
2554         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2556
2557         assert_pipe_disabled(dev_priv, crtc->pipe);
2558         assert_dp_port_disabled(intel_dp);
2559         assert_edp_pll_enabled(dev_priv);
2560
2561         DRM_DEBUG_KMS("disabling eDP PLL\n");
2562
2563         intel_dp->DP &= ~DP_PLL_ENABLE;
2564
2565         I915_WRITE(DP_A, intel_dp->DP);
2566         POSTING_READ(DP_A);
2567         udelay(200);
2568 }
2569
2570 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2571 {
2572         /*
2573          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2574          * be capable of signalling downstream hpd with a long pulse.
2575          * Whether or not that means D3 is safe to use is not clear,
2576          * but let's assume so until proven otherwise.
2577          *
2578          * FIXME should really check all downstream ports...
2579          */
2580         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2581                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2582                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2583 }
2584
2585 /* If the sink supports it, try to set the power state appropriately */
2586 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2587 {
2588         int ret, i;
2589
2590         /* Should have a valid DPCD by this point */
2591         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2592                 return;
2593
2594         if (mode != DRM_MODE_DPMS_ON) {
2595                 if (downstream_hpd_needs_d0(intel_dp))
2596                         return;
2597
2598                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2599                                          DP_SET_POWER_D3);
2600         } else {
2601                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2602
2603                 /*
2604                  * When turning on, we need to retry for 1ms to give the sink
2605                  * time to wake up.
2606                  */
2607                 for (i = 0; i < 3; i++) {
2608                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2609                                                  DP_SET_POWER_D0);
2610                         if (ret == 1)
2611                                 break;
2612                         msleep(1);
2613                 }
2614
2615                 if (ret == 1 && lspcon->active)
2616                         lspcon_wait_pcon_mode(lspcon);
2617         }
2618
2619         if (ret != 1)
2620                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2621                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2622 }
2623
2624 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2625                                   enum pipe *pipe)
2626 {
2627         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2628         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2629         enum port port = encoder->port;
2630         u32 tmp;
2631         bool ret;
2632
2633         if (!intel_display_power_get_if_enabled(dev_priv,
2634                                                 encoder->power_domain))
2635                 return false;
2636
2637         ret = false;
2638
2639         tmp = I915_READ(intel_dp->output_reg);
2640
2641         if (!(tmp & DP_PORT_EN))
2642                 goto out;
2643
2644         if (IS_GEN7(dev_priv) && port == PORT_A) {
2645                 *pipe = PORT_TO_PIPE_CPT(tmp);
2646         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2647                 enum pipe p;
2648
2649                 for_each_pipe(dev_priv, p) {
2650                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2651                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2652                                 *pipe = p;
2653                                 ret = true;
2654
2655                                 goto out;
2656                         }
2657                 }
2658
2659                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2660                               i915_mmio_reg_offset(intel_dp->output_reg));
2661         } else if (IS_CHERRYVIEW(dev_priv)) {
2662                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2663         } else {
2664                 *pipe = PORT_TO_PIPE(tmp);
2665         }
2666
2667         ret = true;
2668
2669 out:
2670         intel_display_power_put(dev_priv, encoder->power_domain);
2671
2672         return ret;
2673 }
2674
2675 static void intel_dp_get_config(struct intel_encoder *encoder,
2676                                 struct intel_crtc_state *pipe_config)
2677 {
2678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2679         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680         u32 tmp, flags = 0;
2681         enum port port = encoder->port;
2682         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2683
2684         if (encoder->type == INTEL_OUTPUT_EDP)
2685                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2686         else
2687                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2688
2689         tmp = I915_READ(intel_dp->output_reg);
2690
2691         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2692
2693         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2694                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2695
2696                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2697                         flags |= DRM_MODE_FLAG_PHSYNC;
2698                 else
2699                         flags |= DRM_MODE_FLAG_NHSYNC;
2700
2701                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2702                         flags |= DRM_MODE_FLAG_PVSYNC;
2703                 else
2704                         flags |= DRM_MODE_FLAG_NVSYNC;
2705         } else {
2706                 if (tmp & DP_SYNC_HS_HIGH)
2707                         flags |= DRM_MODE_FLAG_PHSYNC;
2708                 else
2709                         flags |= DRM_MODE_FLAG_NHSYNC;
2710
2711                 if (tmp & DP_SYNC_VS_HIGH)
2712                         flags |= DRM_MODE_FLAG_PVSYNC;
2713                 else
2714                         flags |= DRM_MODE_FLAG_NVSYNC;
2715         }
2716
2717         pipe_config->base.adjusted_mode.flags |= flags;
2718
2719         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2720                 pipe_config->limited_color_range = true;
2721
2722         pipe_config->lane_count =
2723                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2724
2725         intel_dp_get_m_n(crtc, pipe_config);
2726
2727         if (port == PORT_A) {
2728                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2729                         pipe_config->port_clock = 162000;
2730                 else
2731                         pipe_config->port_clock = 270000;
2732         }
2733
2734         pipe_config->base.adjusted_mode.crtc_clock =
2735                 intel_dotclock_calculate(pipe_config->port_clock,
2736                                          &pipe_config->dp_m_n);
2737
2738         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2739             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2740                 /*
2741                  * This is a big fat ugly hack.
2742                  *
2743                  * Some machines in UEFI boot mode provide us a VBT that has 18
2744                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2745                  * unknown we fail to light up. Yet the same BIOS boots up with
2746                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2747                  * max, not what it tells us to use.
2748                  *
2749                  * Note: This will still be broken if the eDP panel is not lit
2750                  * up by the BIOS, and thus we can't get the mode at module
2751                  * load.
2752                  */
2753                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2754                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2755                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2756         }
2757 }
2758
2759 static void intel_disable_dp(struct intel_encoder *encoder,
2760                              const struct intel_crtc_state *old_crtc_state,
2761                              const struct drm_connector_state *old_conn_state)
2762 {
2763         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2764
2765         intel_dp->link_trained = false;
2766
2767         if (old_crtc_state->has_audio)
2768                 intel_audio_codec_disable(encoder,
2769                                           old_crtc_state, old_conn_state);
2770
2771         /* Make sure the panel is off before trying to change the mode. But also
2772          * ensure that we have vdd while we switch off the panel. */
2773         intel_edp_panel_vdd_on(intel_dp);
2774         intel_edp_backlight_off(old_conn_state);
2775         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2776         intel_edp_panel_off(intel_dp);
2777 }
2778
2779 static void g4x_disable_dp(struct intel_encoder *encoder,
2780                            const struct intel_crtc_state *old_crtc_state,
2781                            const struct drm_connector_state *old_conn_state)
2782 {
2783         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2784
2785         /* disable the port before the pipe on g4x */
2786         intel_dp_link_down(encoder, old_crtc_state);
2787 }
2788
2789 static void ilk_disable_dp(struct intel_encoder *encoder,
2790                            const struct intel_crtc_state *old_crtc_state,
2791                            const struct drm_connector_state *old_conn_state)
2792 {
2793         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2794 }
2795
2796 static void vlv_disable_dp(struct intel_encoder *encoder,
2797                            const struct intel_crtc_state *old_crtc_state,
2798                            const struct drm_connector_state *old_conn_state)
2799 {
2800         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2801
2802         intel_psr_disable(intel_dp, old_crtc_state);
2803
2804         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2805 }
2806
2807 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2808                                 const struct intel_crtc_state *old_crtc_state,
2809                                 const struct drm_connector_state *old_conn_state)
2810 {
2811         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2812         enum port port = encoder->port;
2813
2814         intel_dp_link_down(encoder, old_crtc_state);
2815
2816         /* Only ilk+ has port A */
2817         if (port == PORT_A)
2818                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2819 }
2820
2821 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2822                                 const struct intel_crtc_state *old_crtc_state,
2823                                 const struct drm_connector_state *old_conn_state)
2824 {
2825         intel_dp_link_down(encoder, old_crtc_state);
2826 }
2827
2828 static void chv_post_disable_dp(struct intel_encoder *encoder,
2829                                 const struct intel_crtc_state *old_crtc_state,
2830                                 const struct drm_connector_state *old_conn_state)
2831 {
2832         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2833
2834         intel_dp_link_down(encoder, old_crtc_state);
2835
2836         mutex_lock(&dev_priv->sb_lock);
2837
2838         /* Assert data lane reset */
2839         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2840
2841         mutex_unlock(&dev_priv->sb_lock);
2842 }
2843
2844 static void
2845 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2846                          uint32_t *DP,
2847                          uint8_t dp_train_pat)
2848 {
2849         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2850         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2851         enum port port = intel_dig_port->base.port;
2852
2853         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2854                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2855                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2856
2857         if (HAS_DDI(dev_priv)) {
2858                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2859
2860                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2861                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2862                 else
2863                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2864
2865                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2866                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2867                 case DP_TRAINING_PATTERN_DISABLE:
2868                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2869
2870                         break;
2871                 case DP_TRAINING_PATTERN_1:
2872                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2873                         break;
2874                 case DP_TRAINING_PATTERN_2:
2875                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2876                         break;
2877                 case DP_TRAINING_PATTERN_3:
2878                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2879                         break;
2880                 }
2881                 I915_WRITE(DP_TP_CTL(port), temp);
2882
2883         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2884                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2885                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2886
2887                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2888                 case DP_TRAINING_PATTERN_DISABLE:
2889                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2890                         break;
2891                 case DP_TRAINING_PATTERN_1:
2892                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2893                         break;
2894                 case DP_TRAINING_PATTERN_2:
2895                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2896                         break;
2897                 case DP_TRAINING_PATTERN_3:
2898                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2899                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2900                         break;
2901                 }
2902
2903         } else {
2904                 if (IS_CHERRYVIEW(dev_priv))
2905                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2906                 else
2907                         *DP &= ~DP_LINK_TRAIN_MASK;
2908
2909                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2910                 case DP_TRAINING_PATTERN_DISABLE:
2911                         *DP |= DP_LINK_TRAIN_OFF;
2912                         break;
2913                 case DP_TRAINING_PATTERN_1:
2914                         *DP |= DP_LINK_TRAIN_PAT_1;
2915                         break;
2916                 case DP_TRAINING_PATTERN_2:
2917                         *DP |= DP_LINK_TRAIN_PAT_2;
2918                         break;
2919                 case DP_TRAINING_PATTERN_3:
2920                         if (IS_CHERRYVIEW(dev_priv)) {
2921                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2922                         } else {
2923                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2924                                 *DP |= DP_LINK_TRAIN_PAT_2;
2925                         }
2926                         break;
2927                 }
2928         }
2929 }
2930
2931 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2932                                  const struct intel_crtc_state *old_crtc_state)
2933 {
2934         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2935
2936         /* enable with pattern 1 (as per spec) */
2937
2938         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2939
2940         /*
2941          * Magic for VLV/CHV. We _must_ first set up the register
2942          * without actually enabling the port, and then do another
2943          * write to enable the port. Otherwise link training will
2944          * fail when the power sequencer is freshly used for this port.
2945          */
2946         intel_dp->DP |= DP_PORT_EN;
2947         if (old_crtc_state->has_audio)
2948                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2949
2950         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2951         POSTING_READ(intel_dp->output_reg);
2952 }
2953
2954 static void intel_enable_dp(struct intel_encoder *encoder,
2955                             const struct intel_crtc_state *pipe_config,
2956                             const struct drm_connector_state *conn_state)
2957 {
2958         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2959         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2960         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2961         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2962         enum pipe pipe = crtc->pipe;
2963
2964         if (WARN_ON(dp_reg & DP_PORT_EN))
2965                 return;
2966
2967         pps_lock(intel_dp);
2968
2969         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2970                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2971
2972         intel_dp_enable_port(intel_dp, pipe_config);
2973
2974         edp_panel_vdd_on(intel_dp);
2975         edp_panel_on(intel_dp);
2976         edp_panel_vdd_off(intel_dp, true);
2977
2978         pps_unlock(intel_dp);
2979
2980         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2981                 unsigned int lane_mask = 0x0;
2982
2983                 if (IS_CHERRYVIEW(dev_priv))
2984                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2985
2986                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2987                                     lane_mask);
2988         }
2989
2990         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2991         intel_dp_start_link_train(intel_dp);
2992         intel_dp_stop_link_train(intel_dp);
2993
2994         if (pipe_config->has_audio) {
2995                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2996                                  pipe_name(pipe));
2997                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2998         }
2999 }
3000
3001 static void g4x_enable_dp(struct intel_encoder *encoder,
3002                           const struct intel_crtc_state *pipe_config,
3003                           const struct drm_connector_state *conn_state)
3004 {
3005         intel_enable_dp(encoder, pipe_config, conn_state);
3006         intel_edp_backlight_on(pipe_config, conn_state);
3007 }
3008
3009 static void vlv_enable_dp(struct intel_encoder *encoder,
3010                           const struct intel_crtc_state *pipe_config,
3011                           const struct drm_connector_state *conn_state)
3012 {
3013         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3014
3015         intel_edp_backlight_on(pipe_config, conn_state);
3016         intel_psr_enable(intel_dp, pipe_config);
3017 }
3018
3019 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3020                               const struct intel_crtc_state *pipe_config,
3021                               const struct drm_connector_state *conn_state)
3022 {
3023         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3024         enum port port = encoder->port;
3025
3026         intel_dp_prepare(encoder, pipe_config);
3027
3028         /* Only ilk+ has port A */
3029         if (port == PORT_A)
3030                 ironlake_edp_pll_on(intel_dp, pipe_config);
3031 }
3032
3033 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3034 {
3035         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3036         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3037         enum pipe pipe = intel_dp->pps_pipe;
3038         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3039
3040         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3041
3042         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3043                 return;
3044
3045         edp_panel_vdd_off_sync(intel_dp);
3046
3047         /*
3048          * VLV seems to get confused when multiple power seqeuencers
3049          * have the same port selected (even if only one has power/vdd
3050          * enabled). The failure manifests as vlv_wait_port_ready() failing
3051          * CHV on the other hand doesn't seem to mind having the same port
3052          * selected in multiple power seqeuencers, but let's clear the
3053          * port select always when logically disconnecting a power sequencer
3054          * from a port.
3055          */
3056         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3057                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3058         I915_WRITE(pp_on_reg, 0);
3059         POSTING_READ(pp_on_reg);
3060
3061         intel_dp->pps_pipe = INVALID_PIPE;
3062 }
3063
3064 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3065                                       enum pipe pipe)
3066 {
3067         struct intel_encoder *encoder;
3068
3069         lockdep_assert_held(&dev_priv->pps_mutex);
3070
3071         for_each_intel_encoder(&dev_priv->drm, encoder) {
3072                 struct intel_dp *intel_dp;
3073                 enum port port;
3074
3075                 if (encoder->type != INTEL_OUTPUT_DP &&
3076                     encoder->type != INTEL_OUTPUT_EDP)
3077                         continue;
3078
3079                 intel_dp = enc_to_intel_dp(&encoder->base);
3080                 port = dp_to_dig_port(intel_dp)->base.port;
3081
3082                 WARN(intel_dp->active_pipe == pipe,
3083                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3084                      pipe_name(pipe), port_name(port));
3085
3086                 if (intel_dp->pps_pipe != pipe)
3087                         continue;
3088
3089                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3090                               pipe_name(pipe), port_name(port));
3091
3092                 /* make sure vdd is off before we steal it */
3093                 vlv_detach_power_sequencer(intel_dp);
3094         }
3095 }
3096
3097 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3098                                            const struct intel_crtc_state *crtc_state)
3099 {
3100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3101         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3102         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3103
3104         lockdep_assert_held(&dev_priv->pps_mutex);
3105
3106         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3107
3108         if (intel_dp->pps_pipe != INVALID_PIPE &&
3109             intel_dp->pps_pipe != crtc->pipe) {
3110                 /*
3111                  * If another power sequencer was being used on this
3112                  * port previously make sure to turn off vdd there while
3113                  * we still have control of it.
3114                  */
3115                 vlv_detach_power_sequencer(intel_dp);
3116         }
3117
3118         /*
3119          * We may be stealing the power
3120          * sequencer from another port.
3121          */
3122         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3123
3124         intel_dp->active_pipe = crtc->pipe;
3125
3126         if (!intel_dp_is_edp(intel_dp))
3127                 return;
3128
3129         /* now it's all ours */
3130         intel_dp->pps_pipe = crtc->pipe;
3131
3132         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3133                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3134
3135         /* init power sequencer on this pipe and port */
3136         intel_dp_init_panel_power_sequencer(intel_dp);
3137         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3138 }
3139
3140 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3141                               const struct intel_crtc_state *pipe_config,
3142                               const struct drm_connector_state *conn_state)
3143 {
3144         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3145
3146         intel_enable_dp(encoder, pipe_config, conn_state);
3147 }
3148
3149 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3150                                   const struct intel_crtc_state *pipe_config,
3151                                   const struct drm_connector_state *conn_state)
3152 {
3153         intel_dp_prepare(encoder, pipe_config);
3154
3155         vlv_phy_pre_pll_enable(encoder, pipe_config);
3156 }
3157
3158 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3159                               const struct intel_crtc_state *pipe_config,
3160                               const struct drm_connector_state *conn_state)
3161 {
3162         chv_phy_pre_encoder_enable(encoder, pipe_config);
3163
3164         intel_enable_dp(encoder, pipe_config, conn_state);
3165
3166         /* Second common lane will stay alive on its own now */
3167         chv_phy_release_cl2_override(encoder);
3168 }
3169
3170 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3171                                   const struct intel_crtc_state *pipe_config,
3172                                   const struct drm_connector_state *conn_state)
3173 {
3174         intel_dp_prepare(encoder, pipe_config);
3175
3176         chv_phy_pre_pll_enable(encoder, pipe_config);
3177 }
3178
3179 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3180                                     const struct intel_crtc_state *old_crtc_state,
3181                                     const struct drm_connector_state *old_conn_state)
3182 {
3183         chv_phy_post_pll_disable(encoder, old_crtc_state);
3184 }
3185
3186 /*
3187  * Fetch AUX CH registers 0x202 - 0x207 which contain
3188  * link status information
3189  */
3190 bool
3191 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3192 {
3193         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3194                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3195 }
3196
3197 /* These are source-specific values. */
3198 uint8_t
3199 intel_dp_voltage_max(struct intel_dp *intel_dp)
3200 {
3201         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3202         enum port port = dp_to_dig_port(intel_dp)->base.port;
3203
3204         if (INTEL_GEN(dev_priv) >= 9) {
3205                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3206                 return intel_ddi_dp_voltage_max(encoder);
3207         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3208                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3209         else if (IS_GEN7(dev_priv) && port == PORT_A)
3210                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3211         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3212                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3213         else
3214                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3215 }
3216
3217 uint8_t
3218 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3219 {
3220         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3221         enum port port = dp_to_dig_port(intel_dp)->base.port;
3222
3223         if (INTEL_GEN(dev_priv) >= 9) {
3224                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3225                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3226                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3227                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3228                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3229                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3230                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3231                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3232                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3233                 default:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3235                 }
3236         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3237                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3240                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3241                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3242                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3243                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3244                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3245                 default:
3246                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3247                 }
3248         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3249                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3250                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3251                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3252                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3253                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3254                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3255                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3256                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3257                 default:
3258                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3259                 }
3260         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3261                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3264                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3265                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3266                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3267                 default:
3268                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3269                 }
3270         } else {
3271                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3273                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3274                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3275                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3276                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3277                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3278                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3279                 default:
3280                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3281                 }
3282         }
3283 }
3284
3285 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3286 {
3287         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3288         unsigned long demph_reg_value, preemph_reg_value,
3289                 uniqtranscale_reg_value;
3290         uint8_t train_set = intel_dp->train_set[0];
3291
3292         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3293         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3294                 preemph_reg_value = 0x0004000;
3295                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3296                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3297                         demph_reg_value = 0x2B405555;
3298                         uniqtranscale_reg_value = 0x552AB83A;
3299                         break;
3300                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3301                         demph_reg_value = 0x2B404040;
3302                         uniqtranscale_reg_value = 0x5548B83A;
3303                         break;
3304                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3305                         demph_reg_value = 0x2B245555;
3306                         uniqtranscale_reg_value = 0x5560B83A;
3307                         break;
3308                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3309                         demph_reg_value = 0x2B405555;
3310                         uniqtranscale_reg_value = 0x5598DA3A;
3311                         break;
3312                 default:
3313                         return 0;
3314                 }
3315                 break;
3316         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3317                 preemph_reg_value = 0x0002000;
3318                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3319                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3320                         demph_reg_value = 0x2B404040;
3321                         uniqtranscale_reg_value = 0x5552B83A;
3322                         break;
3323                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3324                         demph_reg_value = 0x2B404848;
3325                         uniqtranscale_reg_value = 0x5580B83A;
3326                         break;
3327                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3328                         demph_reg_value = 0x2B404040;
3329                         uniqtranscale_reg_value = 0x55ADDA3A;
3330                         break;
3331                 default:
3332                         return 0;
3333                 }
3334                 break;
3335         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3336                 preemph_reg_value = 0x0000000;
3337                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3338                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3339                         demph_reg_value = 0x2B305555;
3340                         uniqtranscale_reg_value = 0x5570B83A;
3341                         break;
3342                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3343                         demph_reg_value = 0x2B2B4040;
3344                         uniqtranscale_reg_value = 0x55ADDA3A;
3345                         break;
3346                 default:
3347                         return 0;
3348                 }
3349                 break;
3350         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3351                 preemph_reg_value = 0x0006000;
3352                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3353                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3354                         demph_reg_value = 0x1B405555;
3355                         uniqtranscale_reg_value = 0x55ADDA3A;
3356                         break;
3357                 default:
3358                         return 0;
3359                 }
3360                 break;
3361         default:
3362                 return 0;
3363         }
3364
3365         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3366                                  uniqtranscale_reg_value, 0);
3367
3368         return 0;
3369 }
3370
3371 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3372 {
3373         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3374         u32 deemph_reg_value, margin_reg_value;
3375         bool uniq_trans_scale = false;
3376         uint8_t train_set = intel_dp->train_set[0];
3377
3378         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3379         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3380                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3381                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3382                         deemph_reg_value = 128;
3383                         margin_reg_value = 52;
3384                         break;
3385                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3386                         deemph_reg_value = 128;
3387                         margin_reg_value = 77;
3388                         break;
3389                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3390                         deemph_reg_value = 128;
3391                         margin_reg_value = 102;
3392                         break;
3393                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3394                         deemph_reg_value = 128;
3395                         margin_reg_value = 154;
3396                         uniq_trans_scale = true;
3397                         break;
3398                 default:
3399                         return 0;
3400                 }
3401                 break;
3402         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3403                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3404                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3405                         deemph_reg_value = 85;
3406                         margin_reg_value = 78;
3407                         break;
3408                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3409                         deemph_reg_value = 85;
3410                         margin_reg_value = 116;
3411                         break;
3412                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3413                         deemph_reg_value = 85;
3414                         margin_reg_value = 154;
3415                         break;
3416                 default:
3417                         return 0;
3418                 }
3419                 break;
3420         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3421                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3422                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3423                         deemph_reg_value = 64;
3424                         margin_reg_value = 104;
3425                         break;
3426                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3427                         deemph_reg_value = 64;
3428                         margin_reg_value = 154;
3429                         break;
3430                 default:
3431                         return 0;
3432                 }
3433                 break;
3434         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3435                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3436                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3437                         deemph_reg_value = 43;
3438                         margin_reg_value = 154;
3439                         break;
3440                 default:
3441                         return 0;
3442                 }
3443                 break;
3444         default:
3445                 return 0;
3446         }
3447
3448         chv_set_phy_signal_level(encoder, deemph_reg_value,
3449                                  margin_reg_value, uniq_trans_scale);
3450
3451         return 0;
3452 }
3453
3454 static uint32_t
3455 gen4_signal_levels(uint8_t train_set)
3456 {
3457         uint32_t        signal_levels = 0;
3458
3459         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3460         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3461         default:
3462                 signal_levels |= DP_VOLTAGE_0_4;
3463                 break;
3464         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3465                 signal_levels |= DP_VOLTAGE_0_6;
3466                 break;
3467         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3468                 signal_levels |= DP_VOLTAGE_0_8;
3469                 break;
3470         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3471                 signal_levels |= DP_VOLTAGE_1_2;
3472                 break;
3473         }
3474         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3475         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3476         default:
3477                 signal_levels |= DP_PRE_EMPHASIS_0;
3478                 break;
3479         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3480                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3481                 break;
3482         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3483                 signal_levels |= DP_PRE_EMPHASIS_6;
3484                 break;
3485         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3486                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3487                 break;
3488         }
3489         return signal_levels;
3490 }
3491
3492 /* Gen6's DP voltage swing and pre-emphasis control */
3493 static uint32_t
3494 gen6_edp_signal_levels(uint8_t train_set)
3495 {
3496         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3497                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3498         switch (signal_levels) {
3499         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3500         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3501                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3502         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3503                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3504         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3505         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3506                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3508         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3509                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3510         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3511         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3512                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3513         default:
3514                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3515                               "0x%x\n", signal_levels);
3516                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3517         }
3518 }
3519
3520 /* Gen7's DP voltage swing and pre-emphasis control */
3521 static uint32_t
3522 gen7_edp_signal_levels(uint8_t train_set)
3523 {
3524         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3525                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3526         switch (signal_levels) {
3527         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3528                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3529         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3530                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3531         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3532                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3533
3534         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3535                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3536         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3537                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3538
3539         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3540                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3541         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3542                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3543
3544         default:
3545                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3546                               "0x%x\n", signal_levels);
3547                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3548         }
3549 }
3550
3551 void
3552 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3553 {
3554         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3555         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556         enum port port = intel_dig_port->base.port;
3557         uint32_t signal_levels, mask = 0;
3558         uint8_t train_set = intel_dp->train_set[0];
3559
3560         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3561                 signal_levels = bxt_signal_levels(intel_dp);
3562         } else if (HAS_DDI(dev_priv)) {
3563                 signal_levels = ddi_signal_levels(intel_dp);
3564                 mask = DDI_BUF_EMP_MASK;
3565         } else if (IS_CHERRYVIEW(dev_priv)) {
3566                 signal_levels = chv_signal_levels(intel_dp);
3567         } else if (IS_VALLEYVIEW(dev_priv)) {
3568                 signal_levels = vlv_signal_levels(intel_dp);
3569         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3570                 signal_levels = gen7_edp_signal_levels(train_set);
3571                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3572         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3573                 signal_levels = gen6_edp_signal_levels(train_set);
3574                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3575         } else {
3576                 signal_levels = gen4_signal_levels(train_set);
3577                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3578         }
3579
3580         if (mask)
3581                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3582
3583         DRM_DEBUG_KMS("Using vswing level %d\n",
3584                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3585         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3586                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3587                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3588
3589         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3590
3591         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3592         POSTING_READ(intel_dp->output_reg);
3593 }
3594
3595 void
3596 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3597                                        uint8_t dp_train_pat)
3598 {
3599         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3600         struct drm_i915_private *dev_priv =
3601                 to_i915(intel_dig_port->base.base.dev);
3602
3603         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3604
3605         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3606         POSTING_READ(intel_dp->output_reg);
3607 }
3608
3609 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3610 {
3611         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3612         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3613         enum port port = intel_dig_port->base.port;
3614         uint32_t val;
3615
3616         if (!HAS_DDI(dev_priv))
3617                 return;
3618
3619         val = I915_READ(DP_TP_CTL(port));
3620         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3621         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3622         I915_WRITE(DP_TP_CTL(port), val);
3623
3624         /*
3625          * On PORT_A we can have only eDP in SST mode. There the only reason
3626          * we need to set idle transmission mode is to work around a HW issue
3627          * where we enable the pipe while not in idle link-training mode.
3628          * In this case there is requirement to wait for a minimum number of
3629          * idle patterns to be sent.
3630          */
3631         if (port == PORT_A)
3632                 return;
3633
3634         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3635                                     DP_TP_STATUS_IDLE_DONE,
3636                                     DP_TP_STATUS_IDLE_DONE,
3637                                     1))
3638                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3639 }
3640
3641 static void
3642 intel_dp_link_down(struct intel_encoder *encoder,
3643                    const struct intel_crtc_state *old_crtc_state)
3644 {
3645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3646         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3647         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3648         enum port port = encoder->port;
3649         uint32_t DP = intel_dp->DP;
3650
3651         if (WARN_ON(HAS_DDI(dev_priv)))
3652                 return;
3653
3654         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3655                 return;
3656
3657         DRM_DEBUG_KMS("\n");
3658
3659         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3660             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3661                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3662                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3663         } else {
3664                 if (IS_CHERRYVIEW(dev_priv))
3665                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3666                 else
3667                         DP &= ~DP_LINK_TRAIN_MASK;
3668                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3669         }
3670         I915_WRITE(intel_dp->output_reg, DP);
3671         POSTING_READ(intel_dp->output_reg);
3672
3673         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3674         I915_WRITE(intel_dp->output_reg, DP);
3675         POSTING_READ(intel_dp->output_reg);
3676
3677         /*
3678          * HW workaround for IBX, we need to move the port
3679          * to transcoder A after disabling it to allow the
3680          * matching HDMI port to be enabled on transcoder A.
3681          */
3682         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3683                 /*
3684                  * We get CPU/PCH FIFO underruns on the other pipe when
3685                  * doing the workaround. Sweep them under the rug.
3686                  */
3687                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3688                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3689
3690                 /* always enable with pattern 1 (as per spec) */
3691                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3692                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3693                 I915_WRITE(intel_dp->output_reg, DP);
3694                 POSTING_READ(intel_dp->output_reg);
3695
3696                 DP &= ~DP_PORT_EN;
3697                 I915_WRITE(intel_dp->output_reg, DP);
3698                 POSTING_READ(intel_dp->output_reg);
3699
3700                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3701                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3702                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3703         }
3704
3705         msleep(intel_dp->panel_power_down_delay);
3706
3707         intel_dp->DP = DP;
3708
3709         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3710                 pps_lock(intel_dp);
3711                 intel_dp->active_pipe = INVALID_PIPE;
3712                 pps_unlock(intel_dp);
3713         }
3714 }
3715
3716 bool
3717 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3718 {
3719         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3720                              sizeof(intel_dp->dpcd)) < 0)
3721                 return false; /* aux transfer failed */
3722
3723         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3724
3725         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3726 }
3727
3728 static bool
3729 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3730 {
3731         struct drm_i915_private *dev_priv =
3732                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3733
3734         /* this function is meant to be called only once */
3735         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3736
3737         if (!intel_dp_read_dpcd(intel_dp))
3738                 return false;
3739
3740         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3741                          drm_dp_is_branch(intel_dp->dpcd));
3742
3743         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3744                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3745                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3746
3747         intel_psr_init_dpcd(intel_dp);
3748
3749         /*
3750          * Read the eDP display control registers.
3751          *
3752          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3753          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3754          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3755          * method). The display control registers should read zero if they're
3756          * not supported anyway.
3757          */
3758         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3759                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3760                              sizeof(intel_dp->edp_dpcd))
3761                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3762                               intel_dp->edp_dpcd);
3763
3764         /* Read the eDP 1.4+ supported link rates. */
3765         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3766                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3767                 int i;
3768
3769                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3770                                 sink_rates, sizeof(sink_rates));
3771
3772                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3773                         int val = le16_to_cpu(sink_rates[i]);
3774
3775                         if (val == 0)
3776                                 break;
3777
3778                         /* Value read multiplied by 200kHz gives the per-lane
3779                          * link rate in kHz. The source rates are, however,
3780                          * stored in terms of LS_Clk kHz. The full conversion
3781                          * back to symbols is
3782                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3783                          */
3784                         intel_dp->sink_rates[i] = (val * 200) / 10;
3785                 }
3786                 intel_dp->num_sink_rates = i;
3787         }
3788
3789         /*
3790          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3791          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3792          */
3793         if (intel_dp->num_sink_rates)
3794                 intel_dp->use_rate_select = true;
3795         else
3796                 intel_dp_set_sink_rates(intel_dp);
3797
3798         intel_dp_set_common_rates(intel_dp);
3799
3800         return true;
3801 }
3802
3803
3804 static bool
3805 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3806 {
3807         u8 sink_count;
3808
3809         if (!intel_dp_read_dpcd(intel_dp))
3810                 return false;
3811
3812         /* Don't clobber cached eDP rates. */
3813         if (!intel_dp_is_edp(intel_dp)) {
3814                 intel_dp_set_sink_rates(intel_dp);
3815                 intel_dp_set_common_rates(intel_dp);
3816         }
3817
3818         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3819                 return false;
3820
3821         /*
3822          * Sink count can change between short pulse hpd hence
3823          * a member variable in intel_dp will track any changes
3824          * between short pulse interrupts.
3825          */
3826         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3827
3828         /*
3829          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3830          * a dongle is present but no display. Unless we require to know
3831          * if a dongle is present or not, we don't need to update
3832          * downstream port information. So, an early return here saves
3833          * time from performing other operations which are not required.
3834          */
3835         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3836                 return false;
3837
3838         if (!drm_dp_is_branch(intel_dp->dpcd))
3839                 return true; /* native DP sink */
3840
3841         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3842                 return true; /* no per-port downstream info */
3843
3844         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3845                              intel_dp->downstream_ports,
3846                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3847                 return false; /* downstream port status fetch failed */
3848
3849         return true;
3850 }
3851
3852 static bool
3853 intel_dp_can_mst(struct intel_dp *intel_dp)
3854 {
3855         u8 mstm_cap;
3856
3857         if (!i915_modparams.enable_dp_mst)
3858                 return false;
3859
3860         if (!intel_dp->can_mst)
3861                 return false;
3862
3863         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3864                 return false;
3865
3866         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3867                 return false;
3868
3869         return mstm_cap & DP_MST_CAP;
3870 }
3871
3872 static void
3873 intel_dp_configure_mst(struct intel_dp *intel_dp)
3874 {
3875         if (!i915_modparams.enable_dp_mst)
3876                 return;
3877
3878         if (!intel_dp->can_mst)
3879                 return;
3880
3881         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3882
3883         if (intel_dp->is_mst)
3884                 DRM_DEBUG_KMS("Sink is MST capable\n");
3885         else
3886                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3887
3888         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3889                                         intel_dp->is_mst);
3890 }
3891
3892 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3893                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3894 {
3895         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3896         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3898         u8 buf;
3899         int ret = 0;
3900         int count = 0;
3901         int attempts = 10;
3902
3903         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3904                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3905                 ret = -EIO;
3906                 goto out;
3907         }
3908
3909         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3910                                buf & ~DP_TEST_SINK_START) < 0) {
3911                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3912                 ret = -EIO;
3913                 goto out;
3914         }
3915
3916         do {
3917                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3918
3919                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3920                                       DP_TEST_SINK_MISC, &buf) < 0) {
3921                         ret = -EIO;
3922                         goto out;
3923                 }
3924                 count = buf & DP_TEST_COUNT_MASK;
3925         } while (--attempts && count);
3926
3927         if (attempts == 0) {
3928                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3929                 ret = -ETIMEDOUT;
3930         }
3931
3932  out:
3933         if (disable_wa)
3934                 hsw_enable_ips(crtc_state);
3935         return ret;
3936 }
3937
3938 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3939                                    struct intel_crtc_state *crtc_state)
3940 {
3941         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3942         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3944         u8 buf;
3945         int ret;
3946
3947         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3948                 return -EIO;
3949
3950         if (!(buf & DP_TEST_CRC_SUPPORTED))
3951                 return -ENOTTY;
3952
3953         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3954                 return -EIO;
3955
3956         if (buf & DP_TEST_SINK_START) {
3957                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3958                 if (ret)
3959                         return ret;
3960         }
3961
3962         hsw_disable_ips(crtc_state);
3963
3964         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3965                                buf | DP_TEST_SINK_START) < 0) {
3966                 hsw_enable_ips(crtc_state);
3967                 return -EIO;
3968         }
3969
3970         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3971         return 0;
3972 }
3973
3974 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3975 {
3976         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3977         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3979         u8 buf;
3980         int count, ret;
3981         int attempts = 6;
3982
3983         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3984         if (ret)
3985                 return ret;
3986
3987         do {
3988                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3989
3990                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3991                                       DP_TEST_SINK_MISC, &buf) < 0) {
3992                         ret = -EIO;
3993                         goto stop;
3994                 }
3995                 count = buf & DP_TEST_COUNT_MASK;
3996
3997         } while (--attempts && count == 0);
3998
3999         if (attempts == 0) {
4000                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4001                 ret = -ETIMEDOUT;
4002                 goto stop;
4003         }
4004
4005         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4006                 ret = -EIO;
4007                 goto stop;
4008         }
4009
4010 stop:
4011         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
4012         return ret;
4013 }
4014
4015 static bool
4016 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4017 {
4018         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4019                                  sink_irq_vector) == 1;
4020 }
4021
4022 static bool
4023 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4024 {
4025         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4026                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4027                 DP_DPRX_ESI_LEN;
4028 }
4029
4030 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4031 {
4032         int status = 0;
4033         int test_link_rate;
4034         uint8_t test_lane_count, test_link_bw;
4035         /* (DP CTS 1.2)
4036          * 4.3.1.11
4037          */
4038         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4039         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4040                                    &test_lane_count);
4041
4042         if (status <= 0) {
4043                 DRM_DEBUG_KMS("Lane count read failed\n");
4044                 return DP_TEST_NAK;
4045         }
4046         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4047
4048         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4049                                    &test_link_bw);
4050         if (status <= 0) {
4051                 DRM_DEBUG_KMS("Link Rate read failed\n");
4052                 return DP_TEST_NAK;
4053         }
4054         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4055
4056         /* Validate the requested link rate and lane count */
4057         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4058                                         test_lane_count))
4059                 return DP_TEST_NAK;
4060
4061         intel_dp->compliance.test_lane_count = test_lane_count;
4062         intel_dp->compliance.test_link_rate = test_link_rate;
4063
4064         return DP_TEST_ACK;
4065 }
4066
4067 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4068 {
4069         uint8_t test_pattern;
4070         uint8_t test_misc;
4071         __be16 h_width, v_height;
4072         int status = 0;
4073
4074         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4075         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4076                                    &test_pattern);
4077         if (status <= 0) {
4078                 DRM_DEBUG_KMS("Test pattern read failed\n");
4079                 return DP_TEST_NAK;
4080         }
4081         if (test_pattern != DP_COLOR_RAMP)
4082                 return DP_TEST_NAK;
4083
4084         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4085                                   &h_width, 2);
4086         if (status <= 0) {
4087                 DRM_DEBUG_KMS("H Width read failed\n");
4088                 return DP_TEST_NAK;
4089         }
4090
4091         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4092                                   &v_height, 2);
4093         if (status <= 0) {
4094                 DRM_DEBUG_KMS("V Height read failed\n");
4095                 return DP_TEST_NAK;
4096         }
4097
4098         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4099                                    &test_misc);
4100         if (status <= 0) {
4101                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4102                 return DP_TEST_NAK;
4103         }
4104         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4105                 return DP_TEST_NAK;
4106         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4107                 return DP_TEST_NAK;
4108         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4109         case DP_TEST_BIT_DEPTH_6:
4110                 intel_dp->compliance.test_data.bpc = 6;
4111                 break;
4112         case DP_TEST_BIT_DEPTH_8:
4113                 intel_dp->compliance.test_data.bpc = 8;
4114                 break;
4115         default:
4116                 return DP_TEST_NAK;
4117         }
4118
4119         intel_dp->compliance.test_data.video_pattern = test_pattern;
4120         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4121         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4122         /* Set test active flag here so userspace doesn't interrupt things */
4123         intel_dp->compliance.test_active = 1;
4124
4125         return DP_TEST_ACK;
4126 }
4127
4128 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4129 {
4130         uint8_t test_result = DP_TEST_ACK;
4131         struct intel_connector *intel_connector = intel_dp->attached_connector;
4132         struct drm_connector *connector = &intel_connector->base;
4133
4134         if (intel_connector->detect_edid == NULL ||
4135             connector->edid_corrupt ||
4136             intel_dp->aux.i2c_defer_count > 6) {
4137                 /* Check EDID read for NACKs, DEFERs and corruption
4138                  * (DP CTS 1.2 Core r1.1)
4139                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4140                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4141                  *    4.2.2.6 : EDID corruption detected
4142                  * Use failsafe mode for all cases
4143                  */
4144                 if (intel_dp->aux.i2c_nack_count > 0 ||
4145                         intel_dp->aux.i2c_defer_count > 0)
4146                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4147                                       intel_dp->aux.i2c_nack_count,
4148                                       intel_dp->aux.i2c_defer_count);
4149                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4150         } else {
4151                 struct edid *block = intel_connector->detect_edid;
4152
4153                 /* We have to write the checksum
4154                  * of the last block read
4155                  */
4156                 block += intel_connector->detect_edid->extensions;
4157
4158                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4159                                        block->checksum) <= 0)
4160                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4161
4162                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4163                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4164         }
4165
4166         /* Set test active flag here so userspace doesn't interrupt things */
4167         intel_dp->compliance.test_active = 1;
4168
4169         return test_result;
4170 }
4171
4172 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4173 {
4174         uint8_t test_result = DP_TEST_NAK;
4175         return test_result;
4176 }
4177
4178 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4179 {
4180         uint8_t response = DP_TEST_NAK;
4181         uint8_t request = 0;
4182         int status;
4183
4184         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4185         if (status <= 0) {
4186                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4187                 goto update_status;
4188         }
4189
4190         switch (request) {
4191         case DP_TEST_LINK_TRAINING:
4192                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4193                 response = intel_dp_autotest_link_training(intel_dp);
4194                 break;
4195         case DP_TEST_LINK_VIDEO_PATTERN:
4196                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4197                 response = intel_dp_autotest_video_pattern(intel_dp);
4198                 break;
4199         case DP_TEST_LINK_EDID_READ:
4200                 DRM_DEBUG_KMS("EDID test requested\n");
4201                 response = intel_dp_autotest_edid(intel_dp);
4202                 break;
4203         case DP_TEST_LINK_PHY_TEST_PATTERN:
4204                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4205                 response = intel_dp_autotest_phy_pattern(intel_dp);
4206                 break;
4207         default:
4208                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4209                 break;
4210         }
4211
4212         if (response & DP_TEST_ACK)
4213                 intel_dp->compliance.test_type = request;
4214
4215 update_status:
4216         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4217         if (status <= 0)
4218                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4219 }
4220
4221 static int
4222 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4223 {
4224         bool bret;
4225
4226         if (intel_dp->is_mst) {
4227                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4228                 int ret = 0;
4229                 int retry;
4230                 bool handled;
4231                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4232 go_again:
4233                 if (bret == true) {
4234
4235                         /* check link status - esi[10] = 0x200c */
4236                         if (intel_dp->active_mst_links &&
4237                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4238                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4239                                 intel_dp_start_link_train(intel_dp);
4240                                 intel_dp_stop_link_train(intel_dp);
4241                         }
4242
4243                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4244                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4245
4246                         if (handled) {
4247                                 for (retry = 0; retry < 3; retry++) {
4248                                         int wret;
4249                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4250                                                                  DP_SINK_COUNT_ESI+1,
4251                                                                  &esi[1], 3);
4252                                         if (wret == 3) {
4253                                                 break;
4254                                         }
4255                                 }
4256
4257                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4258                                 if (bret == true) {
4259                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4260                                         goto go_again;
4261                                 }
4262                         } else
4263                                 ret = 0;
4264
4265                         return ret;
4266                 } else {
4267                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4268                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4269                         intel_dp->is_mst = false;
4270                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4271                         /* send a hotplug event */
4272                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4273                 }
4274         }
4275         return -EINVAL;
4276 }
4277
4278 static bool
4279 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4280 {
4281         u8 link_status[DP_LINK_STATUS_SIZE];
4282
4283         if (!intel_dp->link_trained)
4284                 return false;
4285
4286         if (!intel_dp_get_link_status(intel_dp, link_status))
4287                 return false;
4288
4289         /*
4290          * Validate the cached values of intel_dp->link_rate and
4291          * intel_dp->lane_count before attempting to retrain.
4292          */
4293         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4294                                         intel_dp->lane_count))
4295                 return false;
4296
4297         /* Retrain if Channel EQ or CR not ok */
4298         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4299 }
4300
4301 /*
4302  * If display is now connected check links status,
4303  * there has been known issues of link loss triggering
4304  * long pulse.
4305  *
4306  * Some sinks (eg. ASUS PB287Q) seem to perform some
4307  * weird HPD ping pong during modesets. So we can apparently
4308  * end up with HPD going low during a modeset, and then
4309  * going back up soon after. And once that happens we must
4310  * retrain the link to get a picture. That's in case no
4311  * userspace component reacted to intermittent HPD dip.
4312  */
4313 int intel_dp_retrain_link(struct intel_encoder *encoder,
4314                           struct drm_modeset_acquire_ctx *ctx)
4315 {
4316         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4317         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4318         struct intel_connector *connector = intel_dp->attached_connector;
4319         struct drm_connector_state *conn_state;
4320         struct intel_crtc_state *crtc_state;
4321         struct intel_crtc *crtc;
4322         int ret;
4323
4324         /* FIXME handle the MST connectors as well */
4325
4326         if (!connector || connector->base.status != connector_status_connected)
4327                 return 0;
4328
4329         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4330                                ctx);
4331         if (ret)
4332                 return ret;
4333
4334         conn_state = connector->base.state;
4335
4336         crtc = to_intel_crtc(conn_state->crtc);
4337         if (!crtc)
4338                 return 0;
4339
4340         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4341         if (ret)
4342                 return ret;
4343
4344         crtc_state = to_intel_crtc_state(crtc->base.state);
4345
4346         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4347
4348         if (!crtc_state->base.active)
4349                 return 0;
4350
4351         if (conn_state->commit &&
4352             !try_wait_for_completion(&conn_state->commit->hw_done))
4353                 return 0;
4354
4355         if (!intel_dp_needs_link_retrain(intel_dp))
4356                 return 0;
4357
4358         /* Suppress underruns caused by re-training */
4359         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4360         if (crtc->config->has_pch_encoder)
4361                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4362                                                       intel_crtc_pch_transcoder(crtc), false);
4363
4364         intel_dp_start_link_train(intel_dp);
4365         intel_dp_stop_link_train(intel_dp);
4366
4367         /* Keep underrun reporting disabled until things are stable */
4368         intel_wait_for_vblank(dev_priv, crtc->pipe);
4369
4370         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4371         if (crtc->config->has_pch_encoder)
4372                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4373                                                       intel_crtc_pch_transcoder(crtc), true);
4374
4375         return 0;
4376 }
4377
4378 /*
4379  * If display is now connected check links status,
4380  * there has been known issues of link loss triggering
4381  * long pulse.
4382  *
4383  * Some sinks (eg. ASUS PB287Q) seem to perform some
4384  * weird HPD ping pong during modesets. So we can apparently
4385  * end up with HPD going low during a modeset, and then
4386  * going back up soon after. And once that happens we must
4387  * retrain the link to get a picture. That's in case no
4388  * userspace component reacted to intermittent HPD dip.
4389  */
4390 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4391                              struct intel_connector *connector)
4392 {
4393         struct drm_modeset_acquire_ctx ctx;
4394         bool changed;
4395         int ret;
4396
4397         changed = intel_encoder_hotplug(encoder, connector);
4398
4399         drm_modeset_acquire_init(&ctx, 0);
4400
4401         for (;;) {
4402                 ret = intel_dp_retrain_link(encoder, &ctx);
4403
4404                 if (ret == -EDEADLK) {
4405                         drm_modeset_backoff(&ctx);
4406                         continue;
4407                 }
4408
4409                 break;
4410         }
4411
4412         drm_modeset_drop_locks(&ctx);
4413         drm_modeset_acquire_fini(&ctx);
4414         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4415
4416         return changed;
4417 }
4418
4419 /*
4420  * According to DP spec
4421  * 5.1.2:
4422  *  1. Read DPCD
4423  *  2. Configure link according to Receiver Capabilities
4424  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4425  *  4. Check link status on receipt of hot-plug interrupt
4426  *
4427  * intel_dp_short_pulse -  handles short pulse interrupts
4428  * when full detection is not required.
4429  * Returns %true if short pulse is handled and full detection
4430  * is NOT required and %false otherwise.
4431  */
4432 static bool
4433 intel_dp_short_pulse(struct intel_dp *intel_dp)
4434 {
4435         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4436         u8 sink_irq_vector = 0;
4437         u8 old_sink_count = intel_dp->sink_count;
4438         bool ret;
4439
4440         /*
4441          * Clearing compliance test variables to allow capturing
4442          * of values for next automated test request.
4443          */
4444         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4445
4446         /*
4447          * Now read the DPCD to see if it's actually running
4448          * If the current value of sink count doesn't match with
4449          * the value that was stored earlier or dpcd read failed
4450          * we need to do full detection
4451          */
4452         ret = intel_dp_get_dpcd(intel_dp);
4453
4454         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4455                 /* No need to proceed if we are going to do full detect */
4456                 return false;
4457         }
4458
4459         /* Try to read the source of the interrupt */
4460         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4461             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4462             sink_irq_vector != 0) {
4463                 /* Clear interrupt source */
4464                 drm_dp_dpcd_writeb(&intel_dp->aux,
4465                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4466                                    sink_irq_vector);
4467
4468                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4469                         intel_dp_handle_test_request(intel_dp);
4470                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4471                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4472         }
4473
4474         /* defer to the hotplug work for link retraining if needed */
4475         if (intel_dp_needs_link_retrain(intel_dp))
4476                 return false;
4477
4478         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4479                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4480                 /* Send a Hotplug Uevent to userspace to start modeset */
4481                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4482         }
4483
4484         return true;
4485 }
4486
4487 /* XXX this is probably wrong for multiple downstream ports */
4488 static enum drm_connector_status
4489 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4490 {
4491         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4492         uint8_t *dpcd = intel_dp->dpcd;
4493         uint8_t type;
4494
4495         if (lspcon->active)
4496                 lspcon_resume(lspcon);
4497
4498         if (!intel_dp_get_dpcd(intel_dp))
4499                 return connector_status_disconnected;
4500
4501         if (intel_dp_is_edp(intel_dp))
4502                 return connector_status_connected;
4503
4504         /* if there's no downstream port, we're done */
4505         if (!drm_dp_is_branch(dpcd))
4506                 return connector_status_connected;
4507
4508         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4509         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4510             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4511
4512                 return intel_dp->sink_count ?
4513                 connector_status_connected : connector_status_disconnected;
4514         }
4515
4516         if (intel_dp_can_mst(intel_dp))
4517                 return connector_status_connected;
4518
4519         /* If no HPD, poke DDC gently */
4520         if (drm_probe_ddc(&intel_dp->aux.ddc))
4521                 return connector_status_connected;
4522
4523         /* Well we tried, say unknown for unreliable port types */
4524         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4525                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4526                 if (type == DP_DS_PORT_TYPE_VGA ||
4527                     type == DP_DS_PORT_TYPE_NON_EDID)
4528                         return connector_status_unknown;
4529         } else {
4530                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4531                         DP_DWN_STRM_PORT_TYPE_MASK;
4532                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4533                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4534                         return connector_status_unknown;
4535         }
4536
4537         /* Anything else is out of spec, warn and ignore */
4538         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4539         return connector_status_disconnected;
4540 }
4541
4542 static enum drm_connector_status
4543 edp_detect(struct intel_dp *intel_dp)
4544 {
4545         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4546         enum drm_connector_status status;
4547
4548         status = intel_panel_detect(dev_priv);
4549         if (status == connector_status_unknown)
4550                 status = connector_status_connected;
4551
4552         return status;
4553 }
4554
4555 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4556 {
4557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4558         u32 bit;
4559
4560         switch (encoder->hpd_pin) {
4561         case HPD_PORT_B:
4562                 bit = SDE_PORTB_HOTPLUG;
4563                 break;
4564         case HPD_PORT_C:
4565                 bit = SDE_PORTC_HOTPLUG;
4566                 break;
4567         case HPD_PORT_D:
4568                 bit = SDE_PORTD_HOTPLUG;
4569                 break;
4570         default:
4571                 MISSING_CASE(encoder->hpd_pin);
4572                 return false;
4573         }
4574
4575         return I915_READ(SDEISR) & bit;
4576 }
4577
4578 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4579 {
4580         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4581         u32 bit;
4582
4583         switch (encoder->hpd_pin) {
4584         case HPD_PORT_B:
4585                 bit = SDE_PORTB_HOTPLUG_CPT;
4586                 break;
4587         case HPD_PORT_C:
4588                 bit = SDE_PORTC_HOTPLUG_CPT;
4589                 break;
4590         case HPD_PORT_D:
4591                 bit = SDE_PORTD_HOTPLUG_CPT;
4592                 break;
4593         default:
4594                 MISSING_CASE(encoder->hpd_pin);
4595                 return false;
4596         }
4597
4598         return I915_READ(SDEISR) & bit;
4599 }
4600
4601 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4602 {
4603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4604         u32 bit;
4605
4606         switch (encoder->hpd_pin) {
4607         case HPD_PORT_A:
4608                 bit = SDE_PORTA_HOTPLUG_SPT;
4609                 break;
4610         case HPD_PORT_E:
4611                 bit = SDE_PORTE_HOTPLUG_SPT;
4612                 break;
4613         default:
4614                 return cpt_digital_port_connected(encoder);
4615         }
4616
4617         return I915_READ(SDEISR) & bit;
4618 }
4619
4620 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4621 {
4622         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4623         u32 bit;
4624
4625         switch (encoder->hpd_pin) {
4626         case HPD_PORT_B:
4627                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4628                 break;
4629         case HPD_PORT_C:
4630                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4631                 break;
4632         case HPD_PORT_D:
4633                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4634                 break;
4635         default:
4636                 MISSING_CASE(encoder->hpd_pin);
4637                 return false;
4638         }
4639
4640         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4641 }
4642
4643 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4644 {
4645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4646         u32 bit;
4647
4648         switch (encoder->hpd_pin) {
4649         case HPD_PORT_B:
4650                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4651                 break;
4652         case HPD_PORT_C:
4653                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4654                 break;
4655         case HPD_PORT_D:
4656                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4657                 break;
4658         default:
4659                 MISSING_CASE(encoder->hpd_pin);
4660                 return false;
4661         }
4662
4663         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4664 }
4665
4666 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4667 {
4668         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4669
4670         if (encoder->hpd_pin == HPD_PORT_A)
4671                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4672         else
4673                 return ibx_digital_port_connected(encoder);
4674 }
4675
4676 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4677 {
4678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4679
4680         if (encoder->hpd_pin == HPD_PORT_A)
4681                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4682         else
4683                 return cpt_digital_port_connected(encoder);
4684 }
4685
4686 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4687 {
4688         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4689
4690         if (encoder->hpd_pin == HPD_PORT_A)
4691                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4692         else
4693                 return cpt_digital_port_connected(encoder);
4694 }
4695
4696 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4697 {
4698         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4699
4700         if (encoder->hpd_pin == HPD_PORT_A)
4701                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4702         else
4703                 return cpt_digital_port_connected(encoder);
4704 }
4705
4706 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4707 {
4708         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4709         u32 bit;
4710
4711         switch (encoder->hpd_pin) {
4712         case HPD_PORT_A:
4713                 bit = BXT_DE_PORT_HP_DDIA;
4714                 break;
4715         case HPD_PORT_B:
4716                 bit = BXT_DE_PORT_HP_DDIB;
4717                 break;
4718         case HPD_PORT_C:
4719                 bit = BXT_DE_PORT_HP_DDIC;
4720                 break;
4721         default:
4722                 MISSING_CASE(encoder->hpd_pin);
4723                 return false;
4724         }
4725
4726         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4727 }
4728
4729 /*
4730  * intel_digital_port_connected - is the specified port connected?
4731  * @encoder: intel_encoder
4732  *
4733  * Return %true if port is connected, %false otherwise.
4734  */
4735 bool intel_digital_port_connected(struct intel_encoder *encoder)
4736 {
4737         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4738
4739         if (HAS_GMCH_DISPLAY(dev_priv)) {
4740                 if (IS_GM45(dev_priv))
4741                         return gm45_digital_port_connected(encoder);
4742                 else
4743                         return g4x_digital_port_connected(encoder);
4744         }
4745
4746         if (IS_GEN5(dev_priv))
4747                 return ilk_digital_port_connected(encoder);
4748         else if (IS_GEN6(dev_priv))
4749                 return snb_digital_port_connected(encoder);
4750         else if (IS_GEN7(dev_priv))
4751                 return ivb_digital_port_connected(encoder);
4752         else if (IS_GEN8(dev_priv))
4753                 return bdw_digital_port_connected(encoder);
4754         else if (IS_GEN9_LP(dev_priv))
4755                 return bxt_digital_port_connected(encoder);
4756         else
4757                 return spt_digital_port_connected(encoder);
4758 }
4759
4760 static struct edid *
4761 intel_dp_get_edid(struct intel_dp *intel_dp)
4762 {
4763         struct intel_connector *intel_connector = intel_dp->attached_connector;
4764
4765         /* use cached edid if we have one */
4766         if (intel_connector->edid) {
4767                 /* invalid edid */
4768                 if (IS_ERR(intel_connector->edid))
4769                         return NULL;
4770
4771                 return drm_edid_duplicate(intel_connector->edid);
4772         } else
4773                 return drm_get_edid(&intel_connector->base,
4774                                     &intel_dp->aux.ddc);
4775 }
4776
4777 static void
4778 intel_dp_set_edid(struct intel_dp *intel_dp)
4779 {
4780         struct intel_connector *intel_connector = intel_dp->attached_connector;
4781         struct edid *edid;
4782
4783         intel_dp_unset_edid(intel_dp);
4784         edid = intel_dp_get_edid(intel_dp);
4785         intel_connector->detect_edid = edid;
4786
4787         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4788 }
4789
4790 static void
4791 intel_dp_unset_edid(struct intel_dp *intel_dp)
4792 {
4793         struct intel_connector *intel_connector = intel_dp->attached_connector;
4794
4795         kfree(intel_connector->detect_edid);
4796         intel_connector->detect_edid = NULL;
4797
4798         intel_dp->has_audio = false;
4799 }
4800
4801 static int
4802 intel_dp_long_pulse(struct intel_connector *connector)
4803 {
4804         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4805         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4806         enum drm_connector_status status;
4807         u8 sink_irq_vector = 0;
4808
4809         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4810
4811         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4812
4813         /* Can't disconnect eDP, but you can close the lid... */
4814         if (intel_dp_is_edp(intel_dp))
4815                 status = edp_detect(intel_dp);
4816         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4817                 status = intel_dp_detect_dpcd(intel_dp);
4818         else
4819                 status = connector_status_disconnected;
4820
4821         if (status == connector_status_disconnected) {
4822                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4823
4824                 if (intel_dp->is_mst) {
4825                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4826                                       intel_dp->is_mst,
4827                                       intel_dp->mst_mgr.mst_state);
4828                         intel_dp->is_mst = false;
4829                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4830                                                         intel_dp->is_mst);
4831                 }
4832
4833                 goto out;
4834         }
4835
4836         if (intel_dp->reset_link_params) {
4837                 /* Initial max link lane count */
4838                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4839
4840                 /* Initial max link rate */
4841                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4842
4843                 intel_dp->reset_link_params = false;
4844         }
4845
4846         intel_dp_print_rates(intel_dp);
4847
4848         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4849                          drm_dp_is_branch(intel_dp->dpcd));
4850
4851         intel_dp_configure_mst(intel_dp);
4852
4853         if (intel_dp->is_mst) {
4854                 /*
4855                  * If we are in MST mode then this connector
4856                  * won't appear connected or have anything
4857                  * with EDID on it
4858                  */
4859                 status = connector_status_disconnected;
4860                 goto out;
4861         }
4862
4863         /*
4864          * Clearing NACK and defer counts to get their exact values
4865          * while reading EDID which are required by Compliance tests
4866          * 4.2.2.4 and 4.2.2.5
4867          */
4868         intel_dp->aux.i2c_nack_count = 0;
4869         intel_dp->aux.i2c_defer_count = 0;
4870
4871         intel_dp_set_edid(intel_dp);
4872         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4873                 status = connector_status_connected;
4874         intel_dp->detect_done = true;
4875
4876         /* Try to read the source of the interrupt */
4877         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4878             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4879             sink_irq_vector != 0) {
4880                 /* Clear interrupt source */
4881                 drm_dp_dpcd_writeb(&intel_dp->aux,
4882                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4883                                    sink_irq_vector);
4884
4885                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4886                         intel_dp_handle_test_request(intel_dp);
4887                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4888                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4889         }
4890
4891 out:
4892         if (status != connector_status_connected && !intel_dp->is_mst)
4893                 intel_dp_unset_edid(intel_dp);
4894
4895         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4896         return status;
4897 }
4898
4899 static int
4900 intel_dp_detect(struct drm_connector *connector,
4901                 struct drm_modeset_acquire_ctx *ctx,
4902                 bool force)
4903 {
4904         struct intel_dp *intel_dp = intel_attached_dp(connector);
4905         int status = connector->status;
4906
4907         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4908                       connector->base.id, connector->name);
4909
4910         /* If full detect is not performed yet, do a full detect */
4911         if (!intel_dp->detect_done) {
4912                 struct drm_crtc *crtc;
4913                 int ret;
4914
4915                 crtc = connector->state->crtc;
4916                 if (crtc) {
4917                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4918                         if (ret)
4919                                 return ret;
4920                 }
4921
4922                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4923         }
4924
4925         intel_dp->detect_done = false;
4926
4927         return status;
4928 }
4929
4930 static void
4931 intel_dp_force(struct drm_connector *connector)
4932 {
4933         struct intel_dp *intel_dp = intel_attached_dp(connector);
4934         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4935         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4936
4937         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4938                       connector->base.id, connector->name);
4939         intel_dp_unset_edid(intel_dp);
4940
4941         if (connector->status != connector_status_connected)
4942                 return;
4943
4944         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4945
4946         intel_dp_set_edid(intel_dp);
4947
4948         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4949 }
4950
4951 static int intel_dp_get_modes(struct drm_connector *connector)
4952 {
4953         struct intel_connector *intel_connector = to_intel_connector(connector);
4954         struct edid *edid;
4955
4956         edid = intel_connector->detect_edid;
4957         if (edid) {
4958                 int ret = intel_connector_update_modes(connector, edid);
4959                 if (ret)
4960                         return ret;
4961         }
4962
4963         /* if eDP has no EDID, fall back to fixed mode */
4964         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4965             intel_connector->panel.fixed_mode) {
4966                 struct drm_display_mode *mode;
4967
4968                 mode = drm_mode_duplicate(connector->dev,
4969                                           intel_connector->panel.fixed_mode);
4970                 if (mode) {
4971                         drm_mode_probed_add(connector, mode);
4972                         return 1;
4973                 }
4974         }
4975
4976         return 0;
4977 }
4978
4979 static int
4980 intel_dp_connector_register(struct drm_connector *connector)
4981 {
4982         struct intel_dp *intel_dp = intel_attached_dp(connector);
4983         int ret;
4984
4985         ret = intel_connector_register(connector);
4986         if (ret)
4987                 return ret;
4988
4989         i915_debugfs_connector_add(connector);
4990
4991         DRM_DEBUG_KMS("registering %s bus for %s\n",
4992                       intel_dp->aux.name, connector->kdev->kobj.name);
4993
4994         intel_dp->aux.dev = connector->kdev;
4995         return drm_dp_aux_register(&intel_dp->aux);
4996 }
4997
4998 static void
4999 intel_dp_connector_unregister(struct drm_connector *connector)
5000 {
5001         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
5002         intel_connector_unregister(connector);
5003 }
5004
5005 static void
5006 intel_dp_connector_destroy(struct drm_connector *connector)
5007 {
5008         struct intel_connector *intel_connector = to_intel_connector(connector);
5009
5010         kfree(intel_connector->detect_edid);
5011
5012         if (!IS_ERR_OR_NULL(intel_connector->edid))
5013                 kfree(intel_connector->edid);
5014
5015         /*
5016          * Can't call intel_dp_is_edp() since the encoder may have been
5017          * destroyed already.
5018          */
5019         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5020                 intel_panel_fini(&intel_connector->panel);
5021
5022         drm_connector_cleanup(connector);
5023         kfree(connector);
5024 }
5025
5026 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5027 {
5028         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5029         struct intel_dp *intel_dp = &intel_dig_port->dp;
5030
5031         intel_dp_mst_encoder_cleanup(intel_dig_port);
5032         if (intel_dp_is_edp(intel_dp)) {
5033                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5034                 /*
5035                  * vdd might still be enabled do to the delayed vdd off.
5036                  * Make sure vdd is actually turned off here.
5037                  */
5038                 pps_lock(intel_dp);
5039                 edp_panel_vdd_off_sync(intel_dp);
5040                 pps_unlock(intel_dp);
5041
5042                 if (intel_dp->edp_notifier.notifier_call) {
5043                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5044                         intel_dp->edp_notifier.notifier_call = NULL;
5045                 }
5046         }
5047
5048         intel_dp_aux_fini(intel_dp);
5049
5050         drm_encoder_cleanup(encoder);
5051         kfree(intel_dig_port);
5052 }
5053
5054 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5055 {
5056         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5057
5058         if (!intel_dp_is_edp(intel_dp))
5059                 return;
5060
5061         /*
5062          * vdd might still be enabled do to the delayed vdd off.
5063          * Make sure vdd is actually turned off here.
5064          */
5065         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5066         pps_lock(intel_dp);
5067         edp_panel_vdd_off_sync(intel_dp);
5068         pps_unlock(intel_dp);
5069 }
5070
5071 static
5072 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5073                                 u8 *an)
5074 {
5075         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5076         static const struct drm_dp_aux_msg msg = {
5077                 .request = DP_AUX_NATIVE_WRITE,
5078                 .address = DP_AUX_HDCP_AKSV,
5079                 .size = DRM_HDCP_KSV_LEN,
5080         };
5081         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5082         ssize_t dpcd_ret;
5083         int ret;
5084
5085         /* Output An first, that's easy */
5086         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5087                                      an, DRM_HDCP_AN_LEN);
5088         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5089                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5090                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5091         }
5092
5093         /*
5094          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5095          * order to get it on the wire, we need to create the AUX header as if
5096          * we were writing the data, and then tickle the hardware to output the
5097          * data once the header is sent out.
5098          */
5099         intel_dp_aux_header(txbuf, &msg);
5100
5101         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5102                                 rxbuf, sizeof(rxbuf),
5103                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5104         if (ret < 0) {
5105                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5106                 return ret;
5107         } else if (ret == 0) {
5108                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5109                 return -EIO;
5110         }
5111
5112         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5113         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5114 }
5115
5116 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5117                                    u8 *bksv)
5118 {
5119         ssize_t ret;
5120         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5121                                DRM_HDCP_KSV_LEN);
5122         if (ret != DRM_HDCP_KSV_LEN) {
5123                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5124                 return ret >= 0 ? -EIO : ret;
5125         }
5126         return 0;
5127 }
5128
5129 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5130                                       u8 *bstatus)
5131 {
5132         ssize_t ret;
5133         /*
5134          * For some reason the HDMI and DP HDCP specs call this register
5135          * definition by different names. In the HDMI spec, it's called BSTATUS,
5136          * but in DP it's called BINFO.
5137          */
5138         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5139                                bstatus, DRM_HDCP_BSTATUS_LEN);
5140         if (ret != DRM_HDCP_BSTATUS_LEN) {
5141                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5142                 return ret >= 0 ? -EIO : ret;
5143         }
5144         return 0;
5145 }
5146
5147 static
5148 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5149                              u8 *bcaps)
5150 {
5151         ssize_t ret;
5152
5153         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5154                                bcaps, 1);
5155         if (ret != 1) {
5156                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5157                 return ret >= 0 ? -EIO : ret;
5158         }
5159
5160         return 0;
5161 }
5162
5163 static
5164 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5165                                    bool *repeater_present)
5166 {
5167         ssize_t ret;
5168         u8 bcaps;
5169
5170         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5171         if (ret)
5172                 return ret;
5173
5174         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5175         return 0;
5176 }
5177
5178 static
5179 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5180                                 u8 *ri_prime)
5181 {
5182         ssize_t ret;
5183         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5184                                ri_prime, DRM_HDCP_RI_LEN);
5185         if (ret != DRM_HDCP_RI_LEN) {
5186                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5187                 return ret >= 0 ? -EIO : ret;
5188         }
5189         return 0;
5190 }
5191
5192 static
5193 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5194                                  bool *ksv_ready)
5195 {
5196         ssize_t ret;
5197         u8 bstatus;
5198         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5199                                &bstatus, 1);
5200         if (ret != 1) {
5201                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5202                 return ret >= 0 ? -EIO : ret;
5203         }
5204         *ksv_ready = bstatus & DP_BSTATUS_READY;
5205         return 0;
5206 }
5207
5208 static
5209 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5210                                 int num_downstream, u8 *ksv_fifo)
5211 {
5212         ssize_t ret;
5213         int i;
5214
5215         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5216         for (i = 0; i < num_downstream; i += 3) {
5217                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5218                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5219                                        DP_AUX_HDCP_KSV_FIFO,
5220                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5221                                        len);
5222                 if (ret != len) {
5223                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5224                                   ret);
5225                         return ret >= 0 ? -EIO : ret;
5226                 }
5227         }
5228         return 0;
5229 }
5230
5231 static
5232 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5233                                     int i, u32 *part)
5234 {
5235         ssize_t ret;
5236
5237         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5238                 return -EINVAL;
5239
5240         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5241                                DP_AUX_HDCP_V_PRIME(i), part,
5242                                DRM_HDCP_V_PRIME_PART_LEN);
5243         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5244                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5245                 return ret >= 0 ? -EIO : ret;
5246         }
5247         return 0;
5248 }
5249
5250 static
5251 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5252                                     bool enable)
5253 {
5254         /* Not used for single stream DisplayPort setups */
5255         return 0;
5256 }
5257
5258 static
5259 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5260 {
5261         ssize_t ret;
5262         u8 bstatus;
5263
5264         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5265                                &bstatus, 1);
5266         if (ret != 1) {
5267                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5268                 return false;
5269         }
5270
5271         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5272 }
5273
5274 static
5275 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5276                           bool *hdcp_capable)
5277 {
5278         ssize_t ret;
5279         u8 bcaps;
5280
5281         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5282         if (ret)
5283                 return ret;
5284
5285         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5286         return 0;
5287 }
5288
5289 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5290         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5291         .read_bksv = intel_dp_hdcp_read_bksv,
5292         .read_bstatus = intel_dp_hdcp_read_bstatus,
5293         .repeater_present = intel_dp_hdcp_repeater_present,
5294         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5295         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5296         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5297         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5298         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5299         .check_link = intel_dp_hdcp_check_link,
5300         .hdcp_capable = intel_dp_hdcp_capable,
5301 };
5302
5303 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5304 {
5305         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5306
5307         lockdep_assert_held(&dev_priv->pps_mutex);
5308
5309         if (!edp_have_panel_vdd(intel_dp))
5310                 return;
5311
5312         /*
5313          * The VDD bit needs a power domain reference, so if the bit is
5314          * already enabled when we boot or resume, grab this reference and
5315          * schedule a vdd off, so we don't hold on to the reference
5316          * indefinitely.
5317          */
5318         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5319         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5320
5321         edp_panel_vdd_schedule_off(intel_dp);
5322 }
5323
5324 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5325 {
5326         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5327
5328         if ((intel_dp->DP & DP_PORT_EN) == 0)
5329                 return INVALID_PIPE;
5330
5331         if (IS_CHERRYVIEW(dev_priv))
5332                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5333         else
5334                 return PORT_TO_PIPE(intel_dp->DP);
5335 }
5336
5337 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5338 {
5339         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5340         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5341         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5342
5343         if (!HAS_DDI(dev_priv))
5344                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5345
5346         if (lspcon->active)
5347                 lspcon_resume(lspcon);
5348
5349         intel_dp->reset_link_params = true;
5350
5351         pps_lock(intel_dp);
5352
5353         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5354                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5355
5356         if (intel_dp_is_edp(intel_dp)) {
5357                 /* Reinit the power sequencer, in case BIOS did something with it. */
5358                 intel_dp_pps_init(intel_dp);
5359                 intel_edp_panel_vdd_sanitize(intel_dp);
5360         }
5361
5362         pps_unlock(intel_dp);
5363 }
5364
5365 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5366         .force = intel_dp_force,
5367         .fill_modes = drm_helper_probe_single_connector_modes,
5368         .atomic_get_property = intel_digital_connector_atomic_get_property,
5369         .atomic_set_property = intel_digital_connector_atomic_set_property,
5370         .late_register = intel_dp_connector_register,
5371         .early_unregister = intel_dp_connector_unregister,
5372         .destroy = intel_dp_connector_destroy,
5373         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5374         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5375 };
5376
5377 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5378         .detect_ctx = intel_dp_detect,
5379         .get_modes = intel_dp_get_modes,
5380         .mode_valid = intel_dp_mode_valid,
5381         .atomic_check = intel_digital_connector_atomic_check,
5382 };
5383
5384 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5385         .reset = intel_dp_encoder_reset,
5386         .destroy = intel_dp_encoder_destroy,
5387 };
5388
5389 enum irqreturn
5390 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5391 {
5392         struct intel_dp *intel_dp = &intel_dig_port->dp;
5393         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5394         enum irqreturn ret = IRQ_NONE;
5395
5396         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5397                 /*
5398                  * vdd off can generate a long pulse on eDP which
5399                  * would require vdd on to handle it, and thus we
5400                  * would end up in an endless cycle of
5401                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5402                  */
5403                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5404                               port_name(intel_dig_port->base.port));
5405                 return IRQ_HANDLED;
5406         }
5407
5408         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5409                       port_name(intel_dig_port->base.port),
5410                       long_hpd ? "long" : "short");
5411
5412         if (long_hpd) {
5413                 intel_dp->reset_link_params = true;
5414                 intel_dp->detect_done = false;
5415                 return IRQ_NONE;
5416         }
5417
5418         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5419
5420         if (intel_dp->is_mst) {
5421                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5422                         /*
5423                          * If we were in MST mode, and device is not
5424                          * there, get out of MST mode
5425                          */
5426                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5427                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5428                         intel_dp->is_mst = false;
5429                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5430                                                         intel_dp->is_mst);
5431                         intel_dp->detect_done = false;
5432                         goto put_power;
5433                 }
5434         }
5435
5436         if (!intel_dp->is_mst) {
5437                 bool handled;
5438
5439                 handled = intel_dp_short_pulse(intel_dp);
5440
5441                 /* Short pulse can signify loss of hdcp authentication */
5442                 intel_hdcp_check_link(intel_dp->attached_connector);
5443
5444                 if (!handled) {
5445                         intel_dp->detect_done = false;
5446                         goto put_power;
5447                 }
5448         }
5449
5450         ret = IRQ_HANDLED;
5451
5452 put_power:
5453         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5454
5455         return ret;
5456 }
5457
5458 /* check the VBT to see whether the eDP is on another port */
5459 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5460 {
5461         /*
5462          * eDP not supported on g4x. so bail out early just
5463          * for a bit extra safety in case the VBT is bonkers.
5464          */
5465         if (INTEL_GEN(dev_priv) < 5)
5466                 return false;
5467
5468         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5469                 return true;
5470
5471         return intel_bios_is_port_edp(dev_priv, port);
5472 }
5473
5474 static void
5475 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5476 {
5477         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5478         enum port port = dp_to_dig_port(intel_dp)->base.port;
5479
5480         if (!IS_G4X(dev_priv) && port != PORT_A)
5481                 intel_attach_force_audio_property(connector);
5482
5483         intel_attach_broadcast_rgb_property(connector);
5484
5485         if (intel_dp_is_edp(intel_dp)) {
5486                 u32 allowed_scalers;
5487
5488                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5489                 if (!HAS_GMCH_DISPLAY(dev_priv))
5490                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5491
5492                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5493
5494                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5495
5496         }
5497 }
5498
5499 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5500 {
5501         intel_dp->panel_power_off_time = ktime_get_boottime();
5502         intel_dp->last_power_on = jiffies;
5503         intel_dp->last_backlight_off = jiffies;
5504 }
5505
5506 static void
5507 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5508 {
5509         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5510         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5511         struct pps_registers regs;
5512
5513         intel_pps_get_registers(intel_dp, &regs);
5514
5515         /* Workaround: Need to write PP_CONTROL with the unlock key as
5516          * the very first thing. */
5517         pp_ctl = ironlake_get_pp_control(intel_dp);
5518
5519         pp_on = I915_READ(regs.pp_on);
5520         pp_off = I915_READ(regs.pp_off);
5521         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5522             !HAS_PCH_ICP(dev_priv)) {
5523                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5524                 pp_div = I915_READ(regs.pp_div);
5525         }
5526
5527         /* Pull timing values out of registers */
5528         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5529                      PANEL_POWER_UP_DELAY_SHIFT;
5530
5531         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5532                   PANEL_LIGHT_ON_DELAY_SHIFT;
5533
5534         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5535                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5536
5537         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5538                    PANEL_POWER_DOWN_DELAY_SHIFT;
5539
5540         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5541             HAS_PCH_ICP(dev_priv)) {
5542                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5543                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5544         } else {
5545                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5546                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5547         }
5548 }
5549
5550 static void
5551 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5552 {
5553         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5554                       state_name,
5555                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5556 }
5557
5558 static void
5559 intel_pps_verify_state(struct intel_dp *intel_dp)
5560 {
5561         struct edp_power_seq hw;
5562         struct edp_power_seq *sw = &intel_dp->pps_delays;
5563
5564         intel_pps_readout_hw_state(intel_dp, &hw);
5565
5566         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5567             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5568                 DRM_ERROR("PPS state mismatch\n");
5569                 intel_pps_dump_state("sw", sw);
5570                 intel_pps_dump_state("hw", &hw);
5571         }
5572 }
5573
5574 static void
5575 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5576 {
5577         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5578         struct edp_power_seq cur, vbt, spec,
5579                 *final = &intel_dp->pps_delays;
5580
5581         lockdep_assert_held(&dev_priv->pps_mutex);
5582
5583         /* already initialized? */
5584         if (final->t11_t12 != 0)
5585                 return;
5586
5587         intel_pps_readout_hw_state(intel_dp, &cur);
5588
5589         intel_pps_dump_state("cur", &cur);
5590
5591         vbt = dev_priv->vbt.edp.pps;
5592         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5593          * of 500ms appears to be too short. Ocassionally the panel
5594          * just fails to power back on. Increasing the delay to 800ms
5595          * seems sufficient to avoid this problem.
5596          */
5597         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5598                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5599                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5600                               vbt.t11_t12);
5601         }
5602         /* T11_T12 delay is special and actually in units of 100ms, but zero
5603          * based in the hw (so we need to add 100 ms). But the sw vbt
5604          * table multiplies it with 1000 to make it in units of 100usec,
5605          * too. */
5606         vbt.t11_t12 += 100 * 10;
5607
5608         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5609          * our hw here, which are all in 100usec. */
5610         spec.t1_t3 = 210 * 10;
5611         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5612         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5613         spec.t10 = 500 * 10;
5614         /* This one is special and actually in units of 100ms, but zero
5615          * based in the hw (so we need to add 100 ms). But the sw vbt
5616          * table multiplies it with 1000 to make it in units of 100usec,
5617          * too. */
5618         spec.t11_t12 = (510 + 100) * 10;
5619
5620         intel_pps_dump_state("vbt", &vbt);
5621
5622         /* Use the max of the register settings and vbt. If both are
5623          * unset, fall back to the spec limits. */
5624 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5625                                        spec.field : \
5626                                        max(cur.field, vbt.field))
5627         assign_final(t1_t3);
5628         assign_final(t8);
5629         assign_final(t9);
5630         assign_final(t10);
5631         assign_final(t11_t12);
5632 #undef assign_final
5633
5634 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5635         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5636         intel_dp->backlight_on_delay = get_delay(t8);
5637         intel_dp->backlight_off_delay = get_delay(t9);
5638         intel_dp->panel_power_down_delay = get_delay(t10);
5639         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5640 #undef get_delay
5641
5642         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5643                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5644                       intel_dp->panel_power_cycle_delay);
5645
5646         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5647                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5648
5649         /*
5650          * We override the HW backlight delays to 1 because we do manual waits
5651          * on them. For T8, even BSpec recommends doing it. For T9, if we
5652          * don't do this, we'll end up waiting for the backlight off delay
5653          * twice: once when we do the manual sleep, and once when we disable
5654          * the panel and wait for the PP_STATUS bit to become zero.
5655          */
5656         final->t8 = 1;
5657         final->t9 = 1;
5658
5659         /*
5660          * HW has only a 100msec granularity for t11_t12 so round it up
5661          * accordingly.
5662          */
5663         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5664 }
5665
5666 static void
5667 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5668                                               bool force_disable_vdd)
5669 {
5670         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5671         u32 pp_on, pp_off, pp_div, port_sel = 0;
5672         int div = dev_priv->rawclk_freq / 1000;
5673         struct pps_registers regs;
5674         enum port port = dp_to_dig_port(intel_dp)->base.port;
5675         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5676
5677         lockdep_assert_held(&dev_priv->pps_mutex);
5678
5679         intel_pps_get_registers(intel_dp, &regs);
5680
5681         /*
5682          * On some VLV machines the BIOS can leave the VDD
5683          * enabled even on power seqeuencers which aren't
5684          * hooked up to any port. This would mess up the
5685          * power domain tracking the first time we pick
5686          * one of these power sequencers for use since
5687          * edp_panel_vdd_on() would notice that the VDD was
5688          * already on and therefore wouldn't grab the power
5689          * domain reference. Disable VDD first to avoid this.
5690          * This also avoids spuriously turning the VDD on as
5691          * soon as the new power seqeuencer gets initialized.
5692          */
5693         if (force_disable_vdd) {
5694                 u32 pp = ironlake_get_pp_control(intel_dp);
5695
5696                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5697
5698                 if (pp & EDP_FORCE_VDD)
5699                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5700
5701                 pp &= ~EDP_FORCE_VDD;
5702
5703                 I915_WRITE(regs.pp_ctrl, pp);
5704         }
5705
5706         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5707                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5708         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5709                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5710         /* Compute the divisor for the pp clock, simply match the Bspec
5711          * formula. */
5712         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5713             HAS_PCH_ICP(dev_priv)) {
5714                 pp_div = I915_READ(regs.pp_ctrl);
5715                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5716                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5717                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5718         } else {
5719                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5720                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5721                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5722         }
5723
5724         /* Haswell doesn't have any port selection bits for the panel
5725          * power sequencer any more. */
5726         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5727                 port_sel = PANEL_PORT_SELECT_VLV(port);
5728         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5729                 if (port == PORT_A)
5730                         port_sel = PANEL_PORT_SELECT_DPA;
5731                 else
5732                         port_sel = PANEL_PORT_SELECT_DPD;
5733         }
5734
5735         pp_on |= port_sel;
5736
5737         I915_WRITE(regs.pp_on, pp_on);
5738         I915_WRITE(regs.pp_off, pp_off);
5739         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5740             HAS_PCH_ICP(dev_priv))
5741                 I915_WRITE(regs.pp_ctrl, pp_div);
5742         else
5743                 I915_WRITE(regs.pp_div, pp_div);
5744
5745         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5746                       I915_READ(regs.pp_on),
5747                       I915_READ(regs.pp_off),
5748                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5749                        HAS_PCH_ICP(dev_priv)) ?
5750                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5751                       I915_READ(regs.pp_div));
5752 }
5753
5754 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5755 {
5756         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5757
5758         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5759                 vlv_initial_power_sequencer_setup(intel_dp);
5760         } else {
5761                 intel_dp_init_panel_power_sequencer(intel_dp);
5762                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5763         }
5764 }
5765
5766 /**
5767  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5768  * @dev_priv: i915 device
5769  * @crtc_state: a pointer to the active intel_crtc_state
5770  * @refresh_rate: RR to be programmed
5771  *
5772  * This function gets called when refresh rate (RR) has to be changed from
5773  * one frequency to another. Switches can be between high and low RR
5774  * supported by the panel or to any other RR based on media playback (in
5775  * this case, RR value needs to be passed from user space).
5776  *
5777  * The caller of this function needs to take a lock on dev_priv->drrs.
5778  */
5779 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5780                                     const struct intel_crtc_state *crtc_state,
5781                                     int refresh_rate)
5782 {
5783         struct intel_encoder *encoder;
5784         struct intel_digital_port *dig_port = NULL;
5785         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5787         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5788
5789         if (refresh_rate <= 0) {
5790                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5791                 return;
5792         }
5793
5794         if (intel_dp == NULL) {
5795                 DRM_DEBUG_KMS("DRRS not supported.\n");
5796                 return;
5797         }
5798
5799         dig_port = dp_to_dig_port(intel_dp);
5800         encoder = &dig_port->base;
5801
5802         if (!intel_crtc) {
5803                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5804                 return;
5805         }
5806
5807         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5808                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5809                 return;
5810         }
5811
5812         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5813                         refresh_rate)
5814                 index = DRRS_LOW_RR;
5815
5816         if (index == dev_priv->drrs.refresh_rate_type) {
5817                 DRM_DEBUG_KMS(
5818                         "DRRS requested for previously set RR...ignoring\n");
5819                 return;
5820         }
5821
5822         if (!crtc_state->base.active) {
5823                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5824                 return;
5825         }
5826
5827         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5828                 switch (index) {
5829                 case DRRS_HIGH_RR:
5830                         intel_dp_set_m_n(intel_crtc, M1_N1);
5831                         break;
5832                 case DRRS_LOW_RR:
5833                         intel_dp_set_m_n(intel_crtc, M2_N2);
5834                         break;
5835                 case DRRS_MAX_RR:
5836                 default:
5837                         DRM_ERROR("Unsupported refreshrate type\n");
5838                 }
5839         } else if (INTEL_GEN(dev_priv) > 6) {
5840                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5841                 u32 val;
5842
5843                 val = I915_READ(reg);
5844                 if (index > DRRS_HIGH_RR) {
5845                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5846                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5847                         else
5848                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5849                 } else {
5850                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5851                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5852                         else
5853                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5854                 }
5855                 I915_WRITE(reg, val);
5856         }
5857
5858         dev_priv->drrs.refresh_rate_type = index;
5859
5860         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5861 }
5862
5863 /**
5864  * intel_edp_drrs_enable - init drrs struct if supported
5865  * @intel_dp: DP struct
5866  * @crtc_state: A pointer to the active crtc state.
5867  *
5868  * Initializes frontbuffer_bits and drrs.dp
5869  */
5870 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5871                            const struct intel_crtc_state *crtc_state)
5872 {
5873         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5874
5875         if (!crtc_state->has_drrs) {
5876                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5877                 return;
5878         }
5879
5880         if (dev_priv->psr.enabled) {
5881                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5882                 return;
5883         }
5884
5885         mutex_lock(&dev_priv->drrs.mutex);
5886         if (WARN_ON(dev_priv->drrs.dp)) {
5887                 DRM_ERROR("DRRS already enabled\n");
5888                 goto unlock;
5889         }
5890
5891         dev_priv->drrs.busy_frontbuffer_bits = 0;
5892
5893         dev_priv->drrs.dp = intel_dp;
5894
5895 unlock:
5896         mutex_unlock(&dev_priv->drrs.mutex);
5897 }
5898
5899 /**
5900  * intel_edp_drrs_disable - Disable DRRS
5901  * @intel_dp: DP struct
5902  * @old_crtc_state: Pointer to old crtc_state.
5903  *
5904  */
5905 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5906                             const struct intel_crtc_state *old_crtc_state)
5907 {
5908         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5909
5910         if (!old_crtc_state->has_drrs)
5911                 return;
5912
5913         mutex_lock(&dev_priv->drrs.mutex);
5914         if (!dev_priv->drrs.dp) {
5915                 mutex_unlock(&dev_priv->drrs.mutex);
5916                 return;
5917         }
5918
5919         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5920                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5921                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5922
5923         dev_priv->drrs.dp = NULL;
5924         mutex_unlock(&dev_priv->drrs.mutex);
5925
5926         cancel_delayed_work_sync(&dev_priv->drrs.work);
5927 }
5928
5929 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5930 {
5931         struct drm_i915_private *dev_priv =
5932                 container_of(work, typeof(*dev_priv), drrs.work.work);
5933         struct intel_dp *intel_dp;
5934
5935         mutex_lock(&dev_priv->drrs.mutex);
5936
5937         intel_dp = dev_priv->drrs.dp;
5938
5939         if (!intel_dp)
5940                 goto unlock;
5941
5942         /*
5943          * The delayed work can race with an invalidate hence we need to
5944          * recheck.
5945          */
5946
5947         if (dev_priv->drrs.busy_frontbuffer_bits)
5948                 goto unlock;
5949
5950         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5951                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5952
5953                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5954                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5955         }
5956
5957 unlock:
5958         mutex_unlock(&dev_priv->drrs.mutex);
5959 }
5960
5961 /**
5962  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5963  * @dev_priv: i915 device
5964  * @frontbuffer_bits: frontbuffer plane tracking bits
5965  *
5966  * This function gets called everytime rendering on the given planes start.
5967  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5968  *
5969  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5970  */
5971 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5972                                unsigned int frontbuffer_bits)
5973 {
5974         struct drm_crtc *crtc;
5975         enum pipe pipe;
5976
5977         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5978                 return;
5979
5980         cancel_delayed_work(&dev_priv->drrs.work);
5981
5982         mutex_lock(&dev_priv->drrs.mutex);
5983         if (!dev_priv->drrs.dp) {
5984                 mutex_unlock(&dev_priv->drrs.mutex);
5985                 return;
5986         }
5987
5988         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5989         pipe = to_intel_crtc(crtc)->pipe;
5990
5991         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5992         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5993
5994         /* invalidate means busy screen hence upclock */
5995         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5996                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5997                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5998
5999         mutex_unlock(&dev_priv->drrs.mutex);
6000 }
6001
6002 /**
6003  * intel_edp_drrs_flush - Restart Idleness DRRS
6004  * @dev_priv: i915 device
6005  * @frontbuffer_bits: frontbuffer plane tracking bits
6006  *
6007  * This function gets called every time rendering on the given planes has
6008  * completed or flip on a crtc is completed. So DRRS should be upclocked
6009  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6010  * if no other planes are dirty.
6011  *
6012  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6013  */
6014 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6015                           unsigned int frontbuffer_bits)
6016 {
6017         struct drm_crtc *crtc;
6018         enum pipe pipe;
6019
6020         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6021                 return;
6022
6023         cancel_delayed_work(&dev_priv->drrs.work);
6024
6025         mutex_lock(&dev_priv->drrs.mutex);
6026         if (!dev_priv->drrs.dp) {
6027                 mutex_unlock(&dev_priv->drrs.mutex);
6028                 return;
6029         }
6030
6031         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6032         pipe = to_intel_crtc(crtc)->pipe;
6033
6034         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6035         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6036
6037         /* flush means busy screen hence upclock */
6038         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6039                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6040                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6041
6042         /*
6043          * flush also means no more activity hence schedule downclock, if all
6044          * other fbs are quiescent too
6045          */
6046         if (!dev_priv->drrs.busy_frontbuffer_bits)
6047                 schedule_delayed_work(&dev_priv->drrs.work,
6048                                 msecs_to_jiffies(1000));
6049         mutex_unlock(&dev_priv->drrs.mutex);
6050 }
6051
6052 /**
6053  * DOC: Display Refresh Rate Switching (DRRS)
6054  *
6055  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6056  * which enables swtching between low and high refresh rates,
6057  * dynamically, based on the usage scenario. This feature is applicable
6058  * for internal panels.
6059  *
6060  * Indication that the panel supports DRRS is given by the panel EDID, which
6061  * would list multiple refresh rates for one resolution.
6062  *
6063  * DRRS is of 2 types - static and seamless.
6064  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6065  * (may appear as a blink on screen) and is used in dock-undock scenario.
6066  * Seamless DRRS involves changing RR without any visual effect to the user
6067  * and can be used during normal system usage. This is done by programming
6068  * certain registers.
6069  *
6070  * Support for static/seamless DRRS may be indicated in the VBT based on
6071  * inputs from the panel spec.
6072  *
6073  * DRRS saves power by switching to low RR based on usage scenarios.
6074  *
6075  * The implementation is based on frontbuffer tracking implementation.  When
6076  * there is a disturbance on the screen triggered by user activity or a periodic
6077  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6078  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6079  * made.
6080  *
6081  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6082  * and intel_edp_drrs_flush() are called.
6083  *
6084  * DRRS can be further extended to support other internal panels and also
6085  * the scenario of video playback wherein RR is set based on the rate
6086  * requested by userspace.
6087  */
6088
6089 /**
6090  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6091  * @connector: eDP connector
6092  * @fixed_mode: preferred mode of panel
6093  *
6094  * This function is  called only once at driver load to initialize basic
6095  * DRRS stuff.
6096  *
6097  * Returns:
6098  * Downclock mode if panel supports it, else return NULL.
6099  * DRRS support is determined by the presence of downclock mode (apart
6100  * from VBT setting).
6101  */
6102 static struct drm_display_mode *
6103 intel_dp_drrs_init(struct intel_connector *connector,
6104                    struct drm_display_mode *fixed_mode)
6105 {
6106         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6107         struct drm_display_mode *downclock_mode = NULL;
6108
6109         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6110         mutex_init(&dev_priv->drrs.mutex);
6111
6112         if (INTEL_GEN(dev_priv) <= 6) {
6113                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6114                 return NULL;
6115         }
6116
6117         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6118                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6119                 return NULL;
6120         }
6121
6122         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6123                                                     &connector->base);
6124
6125         if (!downclock_mode) {
6126                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6127                 return NULL;
6128         }
6129
6130         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6131
6132         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6133         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6134         return downclock_mode;
6135 }
6136
6137 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6138                                      struct intel_connector *intel_connector)
6139 {
6140         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6141         struct drm_i915_private *dev_priv = to_i915(dev);
6142         struct drm_connector *connector = &intel_connector->base;
6143         struct drm_display_mode *fixed_mode = NULL;
6144         struct drm_display_mode *alt_fixed_mode = NULL;
6145         struct drm_display_mode *downclock_mode = NULL;
6146         bool has_dpcd;
6147         struct drm_display_mode *scan;
6148         struct edid *edid;
6149         enum pipe pipe = INVALID_PIPE;
6150
6151         if (!intel_dp_is_edp(intel_dp))
6152                 return true;
6153
6154         /*
6155          * On IBX/CPT we may get here with LVDS already registered. Since the
6156          * driver uses the only internal power sequencer available for both
6157          * eDP and LVDS bail out early in this case to prevent interfering
6158          * with an already powered-on LVDS power sequencer.
6159          */
6160         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6161                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6162                 DRM_INFO("LVDS was detected, not registering eDP\n");
6163
6164                 return false;
6165         }
6166
6167         pps_lock(intel_dp);
6168
6169         intel_dp_init_panel_power_timestamps(intel_dp);
6170         intel_dp_pps_init(intel_dp);
6171         intel_edp_panel_vdd_sanitize(intel_dp);
6172
6173         pps_unlock(intel_dp);
6174
6175         /* Cache DPCD and EDID for edp. */
6176         has_dpcd = intel_edp_init_dpcd(intel_dp);
6177
6178         if (!has_dpcd) {
6179                 /* if this fails, presume the device is a ghost */
6180                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6181                 goto out_vdd_off;
6182         }
6183
6184         mutex_lock(&dev->mode_config.mutex);
6185         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6186         if (edid) {
6187                 if (drm_add_edid_modes(connector, edid)) {
6188                         drm_mode_connector_update_edid_property(connector,
6189                                                                 edid);
6190                 } else {
6191                         kfree(edid);
6192                         edid = ERR_PTR(-EINVAL);
6193                 }
6194         } else {
6195                 edid = ERR_PTR(-ENOENT);
6196         }
6197         intel_connector->edid = edid;
6198
6199         /* prefer fixed mode from EDID if available, save an alt mode also */
6200         list_for_each_entry(scan, &connector->probed_modes, head) {
6201                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6202                         fixed_mode = drm_mode_duplicate(dev, scan);
6203                         downclock_mode = intel_dp_drrs_init(
6204                                                 intel_connector, fixed_mode);
6205                 } else if (!alt_fixed_mode) {
6206                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
6207                 }
6208         }
6209
6210         /* fallback to VBT if available for eDP */
6211         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6212                 fixed_mode = drm_mode_duplicate(dev,
6213                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6214                 if (fixed_mode) {
6215                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6216                         connector->display_info.width_mm = fixed_mode->width_mm;
6217                         connector->display_info.height_mm = fixed_mode->height_mm;
6218                 }
6219         }
6220         mutex_unlock(&dev->mode_config.mutex);
6221
6222         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6223                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6224                 register_reboot_notifier(&intel_dp->edp_notifier);
6225
6226                 /*
6227                  * Figure out the current pipe for the initial backlight setup.
6228                  * If the current pipe isn't valid, try the PPS pipe, and if that
6229                  * fails just assume pipe A.
6230                  */
6231                 pipe = vlv_active_pipe(intel_dp);
6232
6233                 if (pipe != PIPE_A && pipe != PIPE_B)
6234                         pipe = intel_dp->pps_pipe;
6235
6236                 if (pipe != PIPE_A && pipe != PIPE_B)
6237                         pipe = PIPE_A;
6238
6239                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6240                               pipe_name(pipe));
6241         }
6242
6243         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
6244                          downclock_mode);
6245         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6246         intel_panel_setup_backlight(connector, pipe);
6247
6248         return true;
6249
6250 out_vdd_off:
6251         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6252         /*
6253          * vdd might still be enabled do to the delayed vdd off.
6254          * Make sure vdd is actually turned off here.
6255          */
6256         pps_lock(intel_dp);
6257         edp_panel_vdd_off_sync(intel_dp);
6258         pps_unlock(intel_dp);
6259
6260         return false;
6261 }
6262
6263 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6264 {
6265         struct intel_connector *intel_connector;
6266         struct drm_connector *connector;
6267
6268         intel_connector = container_of(work, typeof(*intel_connector),
6269                                        modeset_retry_work);
6270         connector = &intel_connector->base;
6271         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6272                       connector->name);
6273
6274         /* Grab the locks before changing connector property*/
6275         mutex_lock(&connector->dev->mode_config.mutex);
6276         /* Set connector link status to BAD and send a Uevent to notify
6277          * userspace to do a modeset.
6278          */
6279         drm_mode_connector_set_link_status_property(connector,
6280                                                     DRM_MODE_LINK_STATUS_BAD);
6281         mutex_unlock(&connector->dev->mode_config.mutex);
6282         /* Send Hotplug uevent so userspace can reprobe */
6283         drm_kms_helper_hotplug_event(connector->dev);
6284 }
6285
6286 bool
6287 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6288                         struct intel_connector *intel_connector)
6289 {
6290         struct drm_connector *connector = &intel_connector->base;
6291         struct intel_dp *intel_dp = &intel_dig_port->dp;
6292         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6293         struct drm_device *dev = intel_encoder->base.dev;
6294         struct drm_i915_private *dev_priv = to_i915(dev);
6295         enum port port = intel_encoder->port;
6296         int type;
6297
6298         /* Initialize the work for modeset in case of link train failure */
6299         INIT_WORK(&intel_connector->modeset_retry_work,
6300                   intel_dp_modeset_retry_work_fn);
6301
6302         if (WARN(intel_dig_port->max_lanes < 1,
6303                  "Not enough lanes (%d) for DP on port %c\n",
6304                  intel_dig_port->max_lanes, port_name(port)))
6305                 return false;
6306
6307         intel_dp_set_source_rates(intel_dp);
6308
6309         intel_dp->reset_link_params = true;
6310         intel_dp->pps_pipe = INVALID_PIPE;
6311         intel_dp->active_pipe = INVALID_PIPE;
6312
6313         /* intel_dp vfuncs */
6314         if (HAS_DDI(dev_priv))
6315                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6316
6317         /* Preserve the current hw state. */
6318         intel_dp->DP = I915_READ(intel_dp->output_reg);
6319         intel_dp->attached_connector = intel_connector;
6320
6321         if (intel_dp_is_port_edp(dev_priv, port))
6322                 type = DRM_MODE_CONNECTOR_eDP;
6323         else
6324                 type = DRM_MODE_CONNECTOR_DisplayPort;
6325
6326         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6327                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6328
6329         /*
6330          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6331          * for DP the encoder type can be set by the caller to
6332          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6333          */
6334         if (type == DRM_MODE_CONNECTOR_eDP)
6335                 intel_encoder->type = INTEL_OUTPUT_EDP;
6336
6337         /* eDP only on port B and/or C on vlv/chv */
6338         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6339                     intel_dp_is_edp(intel_dp) &&
6340                     port != PORT_B && port != PORT_C))
6341                 return false;
6342
6343         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6344                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6345                         port_name(port));
6346
6347         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6348         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6349
6350         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6351                 connector->interlace_allowed = true;
6352         connector->doublescan_allowed = 0;
6353
6354         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6355
6356         intel_dp_aux_init(intel_dp);
6357
6358         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6359                           edp_panel_vdd_work);
6360
6361         intel_connector_attach_encoder(intel_connector, intel_encoder);
6362
6363         if (HAS_DDI(dev_priv))
6364                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6365         else
6366                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6367
6368         /* init MST on ports that can support it */
6369         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6370             (port == PORT_B || port == PORT_C ||
6371              port == PORT_D || port == PORT_F))
6372                 intel_dp_mst_encoder_init(intel_dig_port,
6373                                           intel_connector->base.base.id);
6374
6375         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6376                 intel_dp_aux_fini(intel_dp);
6377                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6378                 goto fail;
6379         }
6380
6381         intel_dp_add_properties(intel_dp, connector);
6382
6383         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6384                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6385                 if (ret)
6386                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6387         }
6388
6389         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6390          * 0xd.  Failure to do so will result in spurious interrupts being
6391          * generated on the port when a cable is not attached.
6392          */
6393         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6394                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6395                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6396         }
6397
6398         return true;
6399
6400 fail:
6401         drm_connector_cleanup(connector);
6402
6403         return false;
6404 }
6405
6406 bool intel_dp_init(struct drm_i915_private *dev_priv,
6407                    i915_reg_t output_reg,
6408                    enum port port)
6409 {
6410         struct intel_digital_port *intel_dig_port;
6411         struct intel_encoder *intel_encoder;
6412         struct drm_encoder *encoder;
6413         struct intel_connector *intel_connector;
6414
6415         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6416         if (!intel_dig_port)
6417                 return false;
6418
6419         intel_connector = intel_connector_alloc();
6420         if (!intel_connector)
6421                 goto err_connector_alloc;
6422
6423         intel_encoder = &intel_dig_port->base;
6424         encoder = &intel_encoder->base;
6425
6426         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6427                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6428                              "DP %c", port_name(port)))
6429                 goto err_encoder_init;
6430
6431         intel_encoder->hotplug = intel_dp_hotplug;
6432         intel_encoder->compute_config = intel_dp_compute_config;
6433         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6434         intel_encoder->get_config = intel_dp_get_config;
6435         intel_encoder->suspend = intel_dp_encoder_suspend;
6436         if (IS_CHERRYVIEW(dev_priv)) {
6437                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6438                 intel_encoder->pre_enable = chv_pre_enable_dp;
6439                 intel_encoder->enable = vlv_enable_dp;
6440                 intel_encoder->disable = vlv_disable_dp;
6441                 intel_encoder->post_disable = chv_post_disable_dp;
6442                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6443         } else if (IS_VALLEYVIEW(dev_priv)) {
6444                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6445                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6446                 intel_encoder->enable = vlv_enable_dp;
6447                 intel_encoder->disable = vlv_disable_dp;
6448                 intel_encoder->post_disable = vlv_post_disable_dp;
6449         } else if (INTEL_GEN(dev_priv) >= 5) {
6450                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6451                 intel_encoder->enable = g4x_enable_dp;
6452                 intel_encoder->disable = ilk_disable_dp;
6453                 intel_encoder->post_disable = ilk_post_disable_dp;
6454         } else {
6455                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6456                 intel_encoder->enable = g4x_enable_dp;
6457                 intel_encoder->disable = g4x_disable_dp;
6458         }
6459
6460         intel_dig_port->dp.output_reg = output_reg;
6461         intel_dig_port->max_lanes = 4;
6462
6463         intel_encoder->type = INTEL_OUTPUT_DP;
6464         intel_encoder->power_domain = intel_port_to_power_domain(port);
6465         if (IS_CHERRYVIEW(dev_priv)) {
6466                 if (port == PORT_D)
6467                         intel_encoder->crtc_mask = 1 << 2;
6468                 else
6469                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6470         } else {
6471                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6472         }
6473         intel_encoder->cloneable = 0;
6474         intel_encoder->port = port;
6475
6476         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6477         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6478
6479         if (port != PORT_A)
6480                 intel_infoframe_init(intel_dig_port);
6481
6482         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6483                 goto err_init_connector;
6484
6485         return true;
6486
6487 err_init_connector:
6488         drm_encoder_cleanup(encoder);
6489 err_encoder_init:
6490         kfree(intel_connector);
6491 err_connector_alloc:
6492         kfree(intel_dig_port);
6493         return false;
6494 }
6495
6496 void intel_dp_mst_suspend(struct drm_device *dev)
6497 {
6498         struct drm_i915_private *dev_priv = to_i915(dev);
6499         int i;
6500
6501         /* disable MST */
6502         for (i = 0; i < I915_MAX_PORTS; i++) {
6503                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6504
6505                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6506                         continue;
6507
6508                 if (intel_dig_port->dp.is_mst)
6509                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6510         }
6511 }
6512
6513 void intel_dp_mst_resume(struct drm_device *dev)
6514 {
6515         struct drm_i915_private *dev_priv = to_i915(dev);
6516         int i;
6517
6518         for (i = 0; i < I915_MAX_PORTS; i++) {
6519                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6520                 int ret;
6521
6522                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6523                         continue;
6524
6525                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6526                 if (ret)
6527                         intel_dp_check_mst_status(&intel_dig_port->dp);
6528         }
6529 }