drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  47 #define DP_DPRX_ESI_LEN 14
  48
  49 /* Compliance test status bits  */
  50 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  51 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  54
  55 struct dp_link_dpll {
  56         int clock;
  57         struct dpll dpll;
  58 };
  59
  60 static const struct dp_link_dpll gen4_dpll[] = {
  61         { 162000,
  62                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  63         { 270000,
  64                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  65 };
  66
  67 static const struct dp_link_dpll pch_dpll[] = {
  68         { 162000,
  69                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  70         { 270000,
  71                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  72 };
  73
  74 static const struct dp_link_dpll vlv_dpll[] = {
  75         { 162000,
  76                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  77         { 270000,
  78                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  79 };
  80
  81 /*
  82  * CHV supports eDP 1.4 that have  more link rates.
  83  * Below only provides the fixed rate but exclude variable rate.
  84  */
  85 static const struct dp_link_dpll chv_dpll[] = {
  86         /*
  87          * CHV requires to program fractional division for m2.
  88          * m2 is stored in fixed point format using formula below
  89          * (m2_int << 22) | m2_fraction
  90          */
  91         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  92                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  93         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  95         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  96                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  97 };
  98
  99 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int skl_rates[] = { 162000, 216000, 270000,
 102                                   324000, 432000, 540000 };
 103 static const int cnl_rates[] = { 162000, 216000, 270000,
 104                                  324000, 432000, 540000,
 105                                  648000, 810000 };
 106 static const int default_rates[] = { 162000, 270000, 540000 };
 107
 108 /**
 109  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 110  * @intel_dp: DP struct
 111  *
 112  * If a CPU or PCH DP output is attached to an eDP panel, this function
 113  * will return true, and false otherwise.
 114  */
 115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 118
 119         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 120 }
 121
 122 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 123 {
 124         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 125
 126         return intel_dig_port->base.base.dev;
 127 }
 128
 129 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 130 {
 131         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 132 }
 133
 134 static void intel_dp_link_down(struct intel_encoder *encoder,
 135                                const struct intel_crtc_state *old_crtc_state);
 136 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 137 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 138 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 139                                            const struct intel_crtc_state *crtc_state);
 140 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 141                                       enum pipe pipe);
 142 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 143
 144 /* update sink rates from dpcd */
 145 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 146 {
 147         int i, max_rate;
 148
 149         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 150
 151         for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
 152                 if (default_rates[i] > max_rate)
 153                         break;
 154                 intel_dp->sink_rates[i] = default_rates[i];
 155         }
 156
 157         intel_dp->num_sink_rates = i;
 158 }
 159
 160 /* Get length of rates array potentially limited by max_rate. */
 161 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 162 {
 163         int i;
 164
 165         /* Limit results by potentially reduced max rate */
 166         for (i = 0; i < len; i++) {
 167                 if (rates[len - i - 1] <= max_rate)
 168                         return len - i;
 169         }
 170
 171         return 0;
 172 }
 173
 174 /* Get length of common rates array potentially limited by max_rate. */
 175 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 176                                           int max_rate)
 177 {
 178         return intel_dp_rate_limit_len(intel_dp->common_rates,
 179                                        intel_dp->num_common_rates, max_rate);
 180 }
 181
 182 /* Theoretical max between source and sink */
 183 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 184 {
 185         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 186 }
 187
 188 /* Theoretical max between source and sink */
 189 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 190 {
 191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 192         int source_max = intel_dig_port->max_lanes;
 193         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 194
 195         return min(source_max, sink_max);
 196 }
 197
 198 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 199 {
 200         return intel_dp->max_link_lane_count;
 201 }
 202
 203 int
 204 intel_dp_link_required(int pixel_clock, int bpp)
 205 {
 206         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 207         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 208 }
 209
 210 int
 211 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 212 {
 213         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 214          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 215          * is transmitted every LS_Clk per lane, there is no need to account for
 216          * the channel encoding that is done in the PHY layer here.
 217          */
 218
 219         return max_link_clock * max_lanes;
 220 }
 221
 222 static int
 223 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 224 {
 225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 226         struct intel_encoder *encoder = &intel_dig_port->base;
 227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 228         int max_dotclk = dev_priv->max_dotclk_freq;
 229         int ds_max_dotclk;
 230
 231         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 232
 233         if (type != DP_DS_PORT_TYPE_VGA)
 234                 return max_dotclk;
 235
 236         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 237                                                     intel_dp->downstream_ports);
 238
 239         if (ds_max_dotclk != 0)
 240                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 241
 242         return max_dotclk;
 243 }
 244
 245 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 246 {
 247         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 248         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 249         enum port port = dig_port->base.port;
 250
 251         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 252
 253         /* Low voltage SKUs are limited to max of 5.4G */
 254         if (voltage == VOLTAGE_INFO_0_85V)
 255                 return 540000;
 256
 257         /* For this SKU 8.1G is supported in all ports */
 258         if (IS_CNL_WITH_PORT_F(dev_priv))
 259                 return 810000;
 260
 261         /* For other SKUs, max rate on ports A and D is 5.4G */
 262         if (port == PORT_A || port == PORT_D)
 263                 return 540000;
 264
 265         return 810000;
 266 }
 267
 268 static void
 269 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 270 {
 271         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 272         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 273         const struct ddi_vbt_port_info *info =
 274                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 275         const int *source_rates;
 276         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 277
 278         /* This should only be done once */
 279         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 280
 281         if (IS_GEN9_LP(dev_priv)) {
 282                 source_rates = bxt_rates;
 283                 size = ARRAY_SIZE(bxt_rates);
 284         } else if (IS_CANNONLAKE(dev_priv)) {
 285                 source_rates = cnl_rates;
 286                 size = ARRAY_SIZE(cnl_rates);
 287                 max_rate = cnl_max_source_rate(intel_dp);
 288         } else if (IS_GEN9_BC(dev_priv)) {
 289                 source_rates = skl_rates;
 290                 size = ARRAY_SIZE(skl_rates);
 291         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 292                    IS_BROADWELL(dev_priv)) {
 293                 source_rates = default_rates;
 294                 size = ARRAY_SIZE(default_rates);
 295         } else {
 296                 source_rates = default_rates;
 297                 size = ARRAY_SIZE(default_rates) - 1;
 298         }
 299
 300         if (max_rate && vbt_max_rate)
 301                 max_rate = min(max_rate, vbt_max_rate);
 302         else if (vbt_max_rate)
 303                 max_rate = vbt_max_rate;
 304
 305         if (max_rate)
 306                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 307
 308         intel_dp->source_rates = source_rates;
 309         intel_dp->num_source_rates = size;
 310 }
 311
 312 static int intersect_rates(const int *source_rates, int source_len,
 313                            const int *sink_rates, int sink_len,
 314                            int *common_rates)
 315 {
 316         int i = 0, j = 0, k = 0;
 317
 318         while (i < source_len && j < sink_len) {
 319                 if (source_rates[i] == sink_rates[j]) {
 320                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 321                                 return k;
 322                         common_rates[k] = source_rates[i];
 323                         ++k;
 324                         ++i;
 325                         ++j;
 326                 } else if (source_rates[i] < sink_rates[j]) {
 327                         ++i;
 328                 } else {
 329                         ++j;
 330                 }
 331         }
 332         return k;
 333 }
 334
 335 /* return index of rate in rates array, or -1 if not found */
 336 static int intel_dp_rate_index(const int *rates, int len, int rate)
 337 {
 338         int i;
 339
 340         for (i = 0; i < len; i++)
 341                 if (rate == rates[i])
 342                         return i;
 343
 344         return -1;
 345 }
 346
 347 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 348 {
 349         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 350
 351         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 352                                                      intel_dp->num_source_rates,
 353                                                      intel_dp->sink_rates,
 354                                                      intel_dp->num_sink_rates,
 355                                                      intel_dp->common_rates);
 356
 357         /* Paranoia, there should always be something in common. */
 358         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 359                 intel_dp->common_rates[0] = default_rates[0];
 360                 intel_dp->num_common_rates = 1;
 361         }
 362 }
 363
 364 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 365                                        uint8_t lane_count)
 366 {
 367         /*
 368          * FIXME: we need to synchronize the current link parameters with
 369          * hardware readout. Currently fast link training doesn't work on
 370          * boot-up.
 371          */
 372         if (link_rate == 0 ||
 373             link_rate > intel_dp->max_link_rate)
 374                 return false;
 375
 376         if (lane_count == 0 ||
 377             lane_count > intel_dp_max_lane_count(intel_dp))
 378                 return false;
 379
 380         return true;
 381 }
 382
 383 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 384                                             int link_rate, uint8_t lane_count)
 385 {
 386         int index;
 387
 388         index = intel_dp_rate_index(intel_dp->common_rates,
 389                                     intel_dp->num_common_rates,
 390                                     link_rate);
 391         if (index > 0) {
 392                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 393                 intel_dp->max_link_lane_count = lane_count;
 394         } else if (lane_count > 1) {
 395                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 396                 intel_dp->max_link_lane_count = lane_count >> 1;
 397         } else {
 398                 DRM_ERROR("Link Training Unsuccessful\n");
 399                 return -1;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static enum drm_mode_status
 406 intel_dp_mode_valid(struct drm_connector *connector,
 407                     struct drm_display_mode *mode)
 408 {
 409         struct intel_dp *intel_dp = intel_attached_dp(connector);
 410         struct intel_connector *intel_connector = to_intel_connector(connector);
 411         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 412         int target_clock = mode->clock;
 413         int max_rate, mode_rate, max_lanes, max_link_clock;
 414         int max_dotclk;
 415
 416         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 417
 418         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 419                 if (mode->hdisplay > fixed_mode->hdisplay)
 420                         return MODE_PANEL;
 421
 422                 if (mode->vdisplay > fixed_mode->vdisplay)
 423                         return MODE_PANEL;
 424
 425                 target_clock = fixed_mode->clock;
 426         }
 427
 428         max_link_clock = intel_dp_max_link_rate(intel_dp);
 429         max_lanes = intel_dp_max_lane_count(intel_dp);
 430
 431         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 432         mode_rate = intel_dp_link_required(target_clock, 18);
 433
 434         if (mode_rate > max_rate || target_clock > max_dotclk)
 435                 return MODE_CLOCK_HIGH;
 436
 437         if (mode->clock < 10000)
 438                 return MODE_CLOCK_LOW;
 439
 440         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 441                 return MODE_H_ILLEGAL;
 442
 443         return MODE_OK;
 444 }
 445
 446 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 447 {
 448         int     i;
 449         uint32_t v = 0;
 450
 451         if (src_bytes > 4)
 452                 src_bytes = 4;
 453         for (i = 0; i < src_bytes; i++)
 454                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 455         return v;
 456 }
 457
 458 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 459 {
 460         int i;
 461         if (dst_bytes > 4)
 462                 dst_bytes = 4;
 463         for (i = 0; i < dst_bytes; i++)
 464                 dst[i] = src >> ((3-i) * 8);
 465 }
 466
 467 static void
 468 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 469 static void
 470 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 471                                               bool force_disable_vdd);
 472 static void
 473 intel_dp_pps_init(struct intel_dp *intel_dp);
 474
 475 static void pps_lock(struct intel_dp *intel_dp)
 476 {
 477         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 478
 479         /*
 480          * See intel_power_sequencer_reset() why we need
 481          * a power domain reference here.
 482          */
 483         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 484
 485         mutex_lock(&dev_priv->pps_mutex);
 486 }
 487
 488 static void pps_unlock(struct intel_dp *intel_dp)
 489 {
 490         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 491
 492         mutex_unlock(&dev_priv->pps_mutex);
 493
 494         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 495 }
 496
 497 static void
 498 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 499 {
 500         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 501         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 502         enum pipe pipe = intel_dp->pps_pipe;
 503         bool pll_enabled, release_cl_override = false;
 504         enum dpio_phy phy = DPIO_PHY(pipe);
 505         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 506         uint32_t DP;
 507
 508         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 509                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 510                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 511                 return;
 512
 513         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 514                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 515
 516         /* Preserve the BIOS-computed detected bit. This is
 517          * supposed to be read-only.
 518          */
 519         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 520         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 521         DP |= DP_PORT_WIDTH(1);
 522         DP |= DP_LINK_TRAIN_PAT_1;
 523
 524         if (IS_CHERRYVIEW(dev_priv))
 525                 DP |= DP_PIPE_SELECT_CHV(pipe);
 526         else if (pipe == PIPE_B)
 527                 DP |= DP_PIPEB_SELECT;
 528
 529         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 530
 531         /*
 532          * The DPLL for the pipe must be enabled for this to work.
 533          * So enable temporarily it if it's not already enabled.
 534          */
 535         if (!pll_enabled) {
 536                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 537                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 538
 539                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 540                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 541                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 542                                   pipe_name(pipe));
 543                         return;
 544                 }
 545         }
 546
 547         /*
 548          * Similar magic as in intel_dp_enable_port().
 549          * We _must_ do this port enable + disable trick
 550          * to make this power seqeuencer lock onto the port.
 551          * Otherwise even VDD force bit won't work.
 552          */
 553         I915_WRITE(intel_dp->output_reg, DP);
 554         POSTING_READ(intel_dp->output_reg);
 555
 556         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 557         POSTING_READ(intel_dp->output_reg);
 558
 559         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 560         POSTING_READ(intel_dp->output_reg);
 561
 562         if (!pll_enabled) {
 563                 vlv_force_pll_off(dev_priv, pipe);
 564
 565                 if (release_cl_override)
 566                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 567         }
 568 }
 569
 570 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 571 {
 572         struct intel_encoder *encoder;
 573         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 574
 575         /*
 576          * We don't have power sequencer currently.
 577          * Pick one that's not used by other ports.
 578          */
 579         for_each_intel_encoder(&dev_priv->drm, encoder) {
 580                 struct intel_dp *intel_dp;
 581
 582                 if (encoder->type != INTEL_OUTPUT_DP &&
 583                     encoder->type != INTEL_OUTPUT_EDP)
 584                         continue;
 585
 586                 intel_dp = enc_to_intel_dp(&encoder->base);
 587
 588                 if (encoder->type == INTEL_OUTPUT_EDP) {
 589                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 590                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 591
 592                         if (intel_dp->pps_pipe != INVALID_PIPE)
 593                                 pipes &= ~(1 << intel_dp->pps_pipe);
 594                 } else {
 595                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 596
 597                         if (intel_dp->active_pipe != INVALID_PIPE)
 598                                 pipes &= ~(1 << intel_dp->active_pipe);
 599                 }
 600         }
 601
 602         if (pipes == 0)
 603                 return INVALID_PIPE;
 604
 605         return ffs(pipes) - 1;
 606 }
 607
 608 static enum pipe
 609 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 610 {
 611         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 612         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 613         enum pipe pipe;
 614
 615         lockdep_assert_held(&dev_priv->pps_mutex);
 616
 617         /* We should never land here with regular DP ports */
 618         WARN_ON(!intel_dp_is_edp(intel_dp));
 619
 620         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 621                 intel_dp->active_pipe != intel_dp->pps_pipe);
 622
 623         if (intel_dp->pps_pipe != INVALID_PIPE)
 624                 return intel_dp->pps_pipe;
 625
 626         pipe = vlv_find_free_pps(dev_priv);
 627
 628         /*
 629          * Didn't find one. This should not happen since there
 630          * are two power sequencers and up to two eDP ports.
 631          */
 632         if (WARN_ON(pipe == INVALID_PIPE))
 633                 pipe = PIPE_A;
 634
 635         vlv_steal_power_sequencer(dev_priv, pipe);
 636         intel_dp->pps_pipe = pipe;
 637
 638         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 639                       pipe_name(intel_dp->pps_pipe),
 640                       port_name(intel_dig_port->base.port));
 641
 642         /* init power sequencer on this pipe and port */
 643         intel_dp_init_panel_power_sequencer(intel_dp);
 644         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 645
 646         /*
 647          * Even vdd force doesn't work until we've made
 648          * the power sequencer lock in on the port.
 649          */
 650         vlv_power_sequencer_kick(intel_dp);
 651
 652         return intel_dp->pps_pipe;
 653 }
 654
 655 static int
 656 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 657 {
 658         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 659
 660         lockdep_assert_held(&dev_priv->pps_mutex);
 661
 662         /* We should never land here with regular DP ports */
 663         WARN_ON(!intel_dp_is_edp(intel_dp));
 664
 665         /*
 666          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 667          * mapping needs to be retrieved from VBT, for now just hard-code to
 668          * use instance #0 always.
 669          */
 670         if (!intel_dp->pps_reset)
 671                 return 0;
 672
 673         intel_dp->pps_reset = false;
 674
 675         /*
 676          * Only the HW needs to be reprogrammed, the SW state is fixed and
 677          * has been setup during connector init.
 678          */
 679         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 680
 681         return 0;
 682 }
 683
 684 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 685                                enum pipe pipe);
 686
 687 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 688                                enum pipe pipe)
 689 {
 690         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 691 }
 692
 693 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 694                                 enum pipe pipe)
 695 {
 696         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 697 }
 698
 699 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 700                          enum pipe pipe)
 701 {
 702         return true;
 703 }
 704
 705 static enum pipe
 706 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 707                      enum port port,
 708                      vlv_pipe_check pipe_check)
 709 {
 710         enum pipe pipe;
 711
 712         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 713                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 714                         PANEL_PORT_SELECT_MASK;
 715
 716                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 717                         continue;
 718
 719                 if (!pipe_check(dev_priv, pipe))
 720                         continue;
 721
 722                 return pipe;
 723         }
 724
 725         return INVALID_PIPE;
 726 }
 727
 728 static void
 729 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 730 {
 731         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 732         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 733         enum port port = intel_dig_port->base.port;
 734
 735         lockdep_assert_held(&dev_priv->pps_mutex);
 736
 737         /* try to find a pipe with this port selected */
 738         /* first pick one where the panel is on */
 739         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 740                                                   vlv_pipe_has_pp_on);
 741         /* didn't find one? pick one where vdd is on */
 742         if (intel_dp->pps_pipe == INVALID_PIPE)
 743                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 744                                                           vlv_pipe_has_vdd_on);
 745         /* didn't find one? pick one with just the correct port */
 746         if (intel_dp->pps_pipe == INVALID_PIPE)
 747                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 748                                                           vlv_pipe_any);
 749
 750         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 751         if (intel_dp->pps_pipe == INVALID_PIPE) {
 752                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 753                               port_name(port));
 754                 return;
 755         }
 756
 757         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 758                       port_name(port), pipe_name(intel_dp->pps_pipe));
 759
 760         intel_dp_init_panel_power_sequencer(intel_dp);
 761         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 762 }
 763
 764 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 765 {
 766         struct intel_encoder *encoder;
 767
 768         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 769                     !IS_GEN9_LP(dev_priv)))
 770                 return;
 771
 772         /*
 773          * We can't grab pps_mutex here due to deadlock with power_domain
 774          * mutex when power_domain functions are called while holding pps_mutex.
 775          * That also means that in order to use pps_pipe the code needs to
 776          * hold both a power domain reference and pps_mutex, and the power domain
 777          * reference get/put must be done while _not_ holding pps_mutex.
 778          * pps_{lock,unlock}() do these steps in the correct order, so one
 779          * should use them always.
 780          */
 781
 782         for_each_intel_encoder(&dev_priv->drm, encoder) {
 783                 struct intel_dp *intel_dp;
 784
 785                 if (encoder->type != INTEL_OUTPUT_DP &&
 786                     encoder->type != INTEL_OUTPUT_EDP &&
 787                     encoder->type != INTEL_OUTPUT_DDI)
 788                         continue;
 789
 790                 intel_dp = enc_to_intel_dp(&encoder->base);
 791
 792                 /* Skip pure DVI/HDMI DDI encoders */
 793                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 794                         continue;
 795
 796                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 797
 798                 if (encoder->type != INTEL_OUTPUT_EDP)
 799                         continue;
 800
 801                 if (IS_GEN9_LP(dev_priv))
 802                         intel_dp->pps_reset = true;
 803                 else
 804                         intel_dp->pps_pipe = INVALID_PIPE;
 805         }
 806 }
 807
 808 struct pps_registers {
 809         i915_reg_t pp_ctrl;
 810         i915_reg_t pp_stat;
 811         i915_reg_t pp_on;
 812         i915_reg_t pp_off;
 813         i915_reg_t pp_div;
 814 };
 815
 816 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 817                                     struct pps_registers *regs)
 818 {
 819         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 820         int pps_idx = 0;
 821
 822         memset(regs, 0, sizeof(*regs));
 823
 824         if (IS_GEN9_LP(dev_priv))
 825                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 826         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 827                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 828
 829         regs->pp_ctrl = PP_CONTROL(pps_idx);
 830         regs->pp_stat = PP_STATUS(pps_idx);
 831         regs->pp_on = PP_ON_DELAYS(pps_idx);
 832         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 833         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 834             !HAS_PCH_ICP(dev_priv))
 835                 regs->pp_div = PP_DIVISOR(pps_idx);
 836 }
 837
 838 static i915_reg_t
 839 _pp_ctrl_reg(struct intel_dp *intel_dp)
 840 {
 841         struct pps_registers regs;
 842
 843         intel_pps_get_registers(intel_dp, &regs);
 844
 845         return regs.pp_ctrl;
 846 }
 847
 848 static i915_reg_t
 849 _pp_stat_reg(struct intel_dp *intel_dp)
 850 {
 851         struct pps_registers regs;
 852
 853         intel_pps_get_registers(intel_dp, &regs);
 854
 855         return regs.pp_stat;
 856 }
 857
 858 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 859    This function only applicable when panel PM state is not to be tracked */
 860 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 861                               void *unused)
 862 {
 863         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 864                                                  edp_notifier);
 865         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 866
 867         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 868                 return 0;
 869
 870         pps_lock(intel_dp);
 871
 872         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 873                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 874                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 875                 u32 pp_div;
 876
 877                 pp_ctrl_reg = PP_CONTROL(pipe);
 878                 pp_div_reg  = PP_DIVISOR(pipe);
 879                 pp_div = I915_READ(pp_div_reg);
 880                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 881
 882                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 883                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 884                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 885                 msleep(intel_dp->panel_power_cycle_delay);
 886         }
 887
 888         pps_unlock(intel_dp);
 889
 890         return 0;
 891 }
 892
 893 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 894 {
 895         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 896
 897         lockdep_assert_held(&dev_priv->pps_mutex);
 898
 899         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 900             intel_dp->pps_pipe == INVALID_PIPE)
 901                 return false;
 902
 903         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 904 }
 905
 906 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 907 {
 908         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 909
 910         lockdep_assert_held(&dev_priv->pps_mutex);
 911
 912         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 913             intel_dp->pps_pipe == INVALID_PIPE)
 914                 return false;
 915
 916         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 917 }
 918
 919 static void
 920 intel_dp_check_edp(struct intel_dp *intel_dp)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 923
 924         if (!intel_dp_is_edp(intel_dp))
 925                 return;
 926
 927         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 928                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 929                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 930                               I915_READ(_pp_stat_reg(intel_dp)),
 931                               I915_READ(_pp_ctrl_reg(intel_dp)));
 932         }
 933 }
 934
 935 static uint32_t
 936 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 937 {
 938         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 939         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 940         uint32_t status;
 941         bool done;
 942
 943 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 944         if (has_aux_irq)
 945                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 946                                           msecs_to_jiffies_timeout(10));
 947         else
 948                 done = wait_for(C, 10) == 0;
 949         if (!done)
 950                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 951                           has_aux_irq);
 952 #undef C
 953
 954         return status;
 955 }
 956
 957 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 958 {
 959         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 960         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 961
 962         if (index)
 963                 return 0;
 964
 965         /*
 966          * The clock divider is based off the hrawclk, and would like to run at
 967          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 968          */
 969         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 970 }
 971
 972 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 973 {
 974         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 975         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 976
 977         if (index)
 978                 return 0;
 979
 980         /*
 981          * The clock divider is based off the cdclk or PCH rawclk, and would
 982          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 983          * divide by 2000 and use that
 984          */
 985         if (intel_dig_port->base.port == PORT_A)
 986                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 987         else
 988                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 989 }
 990
 991 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 992 {
 993         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 994         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 995
 996         if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 997                 /* Workaround for non-ULT HSW */
 998                 switch (index) {
 999                 case 0: return 63;
1000                 case 1: return 72;
1001                 default: return 0;
1002                 }
1003         }
1004
1005         return ilk_get_aux_clock_divider(intel_dp, index);
1006 }
1007
1008 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1009 {
1010         /*
1011          * SKL doesn't need us to program the AUX clock divider (Hardware will
1012          * derive the clock from CDCLK automatically). We still implement the
1013          * get_aux_clock_divider vfunc to plug-in into the existing code.
1014          */
1015         return index ? 0 : 1;
1016 }
1017
1018 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1019                                      bool has_aux_irq,
1020                                      int send_bytes,
1021                                      uint32_t aux_clock_divider)
1022 {
1023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1024         struct drm_i915_private *dev_priv =
1025                         to_i915(intel_dig_port->base.base.dev);
1026         uint32_t precharge, timeout;
1027
1028         if (IS_GEN6(dev_priv))
1029                 precharge = 3;
1030         else
1031                 precharge = 5;
1032
1033         if (IS_BROADWELL(dev_priv))
1034                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1035         else
1036                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1037
1038         return DP_AUX_CH_CTL_SEND_BUSY |
1039                DP_AUX_CH_CTL_DONE |
1040                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1041                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1042                timeout |
1043                DP_AUX_CH_CTL_RECEIVE_ERROR |
1044                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1045                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1046                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1047 }
1048
1049 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1050                                       bool has_aux_irq,
1051                                       int send_bytes,
1052                                       uint32_t unused)
1053 {
1054         return DP_AUX_CH_CTL_SEND_BUSY |
1055                DP_AUX_CH_CTL_DONE |
1056                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1057                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1058                DP_AUX_CH_CTL_TIME_OUT_MAX |
1059                DP_AUX_CH_CTL_RECEIVE_ERROR |
1060                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1061                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1062                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1063 }
1064
1065 static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp,
1066                                           bool has_aux_irq,
1067                                           int send_bytes,
1068                                           uint32_t aux_clock_divider,
1069                                           bool aksv_write)
1070 {
1071         uint32_t val = 0;
1072
1073         if (aksv_write) {
1074                 send_bytes += 5;
1075                 val |= DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1076         }
1077
1078         return val | intel_dp->get_aux_send_ctl(intel_dp,
1079                                                 has_aux_irq,
1080                                                 send_bytes,
1081                                                 aux_clock_divider);
1082 }
1083
1084 static int
1085 intel_dp_aux_ch(struct intel_dp *intel_dp,
1086                 const uint8_t *send, int send_bytes,
1087                 uint8_t *recv, int recv_size, bool aksv_write)
1088 {
1089         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1090         struct drm_i915_private *dev_priv =
1091                         to_i915(intel_dig_port->base.base.dev);
1092         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1093         uint32_t aux_clock_divider;
1094         int i, ret, recv_bytes;
1095         uint32_t status;
1096         int try, clock = 0;
1097         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1098         bool vdd;
1099
1100         pps_lock(intel_dp);
1101
1102         /*
1103          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1104          * In such cases we want to leave VDD enabled and it's up to upper layers
1105          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1106          * ourselves.
1107          */
1108         vdd = edp_panel_vdd_on(intel_dp);
1109
1110         /* dp aux is extremely sensitive to irq latency, hence request the
1111          * lowest possible wakeup latency and so prevent the cpu from going into
1112          * deep sleep states.
1113          */
1114         pm_qos_update_request(&dev_priv->pm_qos, 0);
1115
1116         intel_dp_check_edp(intel_dp);
1117
1118         /* Try to wait for any previous AUX channel activity */
1119         for (try = 0; try < 3; try++) {
1120                 status = I915_READ_NOTRACE(ch_ctl);
1121                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1122                         break;
1123                 msleep(1);
1124         }
1125
1126         if (try == 3) {
1127                 static u32 last_status = -1;
1128                 const u32 status = I915_READ(ch_ctl);
1129
1130                 if (status != last_status) {
1131                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1132                              status);
1133                         last_status = status;
1134                 }
1135
1136                 ret = -EBUSY;
1137                 goto out;
1138         }
1139
1140         /* Only 5 data registers! */
1141         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1142                 ret = -E2BIG;
1143                 goto out;
1144         }
1145
1146         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1147                 u32 send_ctl = intel_dp_get_aux_send_ctl(intel_dp,
1148                                                          has_aux_irq,
1149                                                          send_bytes,
1150                                                          aux_clock_divider,
1151                                                          aksv_write);
1152
1153                 /* Must try at least 3 times according to DP spec */
1154                 for (try = 0; try < 5; try++) {
1155                         /* Load the send data into the aux channel data registers */
1156                         for (i = 0; i < send_bytes; i += 4)
1157                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1158                                            intel_dp_pack_aux(send + i,
1159                                                              send_bytes - i));
1160
1161                         /* Send the command and wait for it to complete */
1162                         I915_WRITE(ch_ctl, send_ctl);
1163
1164                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1165
1166                         /* Clear done status and any errors */
1167                         I915_WRITE(ch_ctl,
1168                                    status |
1169                                    DP_AUX_CH_CTL_DONE |
1170                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1171                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1172
1173                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1174                                 continue;
1175
1176                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1177                          *   400us delay required for errors and timeouts
1178                          *   Timeout errors from the HW already meet this
1179                          *   requirement so skip to next iteration
1180                          */
1181                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1182                                 usleep_range(400, 500);
1183                                 continue;
1184                         }
1185                         if (status & DP_AUX_CH_CTL_DONE)
1186                                 goto done;
1187                 }
1188         }
1189
1190         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1191                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1192                 ret = -EBUSY;
1193                 goto out;
1194         }
1195
1196 done:
1197         /* Check for timeout or receive error.
1198          * Timeouts occur when the sink is not connected
1199          */
1200         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1201                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1202                 ret = -EIO;
1203                 goto out;
1204         }
1205
1206         /* Timeouts occur when the device isn't connected, so they're
1207          * "normal" -- don't fill the kernel log with these */
1208         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1209                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1210                 ret = -ETIMEDOUT;
1211                 goto out;
1212         }
1213
1214         /* Unload any bytes sent back from the other side */
1215         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1216                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1217
1218         /*
1219          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1220          * We have no idea of what happened so we return -EBUSY so
1221          * drm layer takes care for the necessary retries.
1222          */
1223         if (recv_bytes == 0 || recv_bytes > 20) {
1224                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1225                               recv_bytes);
1226                 /*
1227                  * FIXME: This patch was created on top of a series that
1228                  * organize the retries at drm level. There EBUSY should
1229                  * also take care for 1ms wait before retrying.
1230                  * That aux retries re-org is still needed and after that is
1231                  * merged we remove this sleep from here.
1232                  */
1233                 usleep_range(1000, 1500);
1234                 ret = -EBUSY;
1235                 goto out;
1236         }
1237
1238         if (recv_bytes > recv_size)
1239                 recv_bytes = recv_size;
1240
1241         for (i = 0; i < recv_bytes; i += 4)
1242                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1243                                     recv + i, recv_bytes - i);
1244
1245         ret = recv_bytes;
1246 out:
1247         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1248
1249         if (vdd)
1250                 edp_panel_vdd_off(intel_dp, false);
1251
1252         pps_unlock(intel_dp);
1253
1254         return ret;
1255 }
1256
1257 #define BARE_ADDRESS_SIZE       3
1258 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1259 static ssize_t
1260 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1261 {
1262         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1263         uint8_t txbuf[20], rxbuf[20];
1264         size_t txsize, rxsize;
1265         int ret;
1266
1267         txbuf[0] = (msg->request << 4) |
1268                 ((msg->address >> 16) & 0xf);
1269         txbuf[1] = (msg->address >> 8) & 0xff;
1270         txbuf[2] = msg->address & 0xff;
1271         txbuf[3] = msg->size - 1;
1272
1273         switch (msg->request & ~DP_AUX_I2C_MOT) {
1274         case DP_AUX_NATIVE_WRITE:
1275         case DP_AUX_I2C_WRITE:
1276         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1277                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1278                 rxsize = 2; /* 0 or 1 data bytes */
1279
1280                 if (WARN_ON(txsize > 20))
1281                         return -E2BIG;
1282
1283                 WARN_ON(!msg->buffer != !msg->size);
1284
1285                 if (msg->buffer)
1286                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1287
1288                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
1289                                       false);
1290                 if (ret > 0) {
1291                         msg->reply = rxbuf[0] >> 4;
1292
1293                         if (ret > 1) {
1294                                 /* Number of bytes written in a short write. */
1295                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1296                         } else {
1297                                 /* Return payload size. */
1298                                 ret = msg->size;
1299                         }
1300                 }
1301                 break;
1302
1303         case DP_AUX_NATIVE_READ:
1304         case DP_AUX_I2C_READ:
1305                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1306                 rxsize = msg->size + 1;
1307
1308                 if (WARN_ON(rxsize > 20))
1309                         return -E2BIG;
1310
1311                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize,
1312                                       false);
1313                 if (ret > 0) {
1314                         msg->reply = rxbuf[0] >> 4;
1315                         /*
1316                          * Assume happy day, and copy the data. The caller is
1317                          * expected to check msg->reply before touching it.
1318                          *
1319                          * Return payload size.
1320                          */
1321                         ret--;
1322                         memcpy(msg->buffer, rxbuf + 1, ret);
1323                 }
1324                 break;
1325
1326         default:
1327                 ret = -EINVAL;
1328                 break;
1329         }
1330
1331         return ret;
1332 }
1333
1334 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1335                                 enum port port)
1336 {
1337         const struct ddi_vbt_port_info *info =
1338                 &dev_priv->vbt.ddi_port_info[port];
1339         enum port aux_port;
1340
1341         if (!info->alternate_aux_channel) {
1342                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1343                               port_name(port), port_name(port));
1344                 return port;
1345         }
1346
1347         switch (info->alternate_aux_channel) {
1348         case DP_AUX_A:
1349                 aux_port = PORT_A;
1350                 break;
1351         case DP_AUX_B:
1352                 aux_port = PORT_B;
1353                 break;
1354         case DP_AUX_C:
1355                 aux_port = PORT_C;
1356                 break;
1357         case DP_AUX_D:
1358                 aux_port = PORT_D;
1359                 break;
1360         case DP_AUX_F:
1361                 aux_port = PORT_F;
1362                 break;
1363         default:
1364                 MISSING_CASE(info->alternate_aux_channel);
1365                 aux_port = PORT_A;
1366                 break;
1367         }
1368
1369         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1370                       port_name(aux_port), port_name(port));
1371
1372         return aux_port;
1373 }
1374
1375 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1376                                   enum port port)
1377 {
1378         switch (port) {
1379         case PORT_B:
1380         case PORT_C:
1381         case PORT_D:
1382                 return DP_AUX_CH_CTL(port);
1383         default:
1384                 MISSING_CASE(port);
1385                 return DP_AUX_CH_CTL(PORT_B);
1386         }
1387 }
1388
1389 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1390                                    enum port port, int index)
1391 {
1392         switch (port) {
1393         case PORT_B:
1394         case PORT_C:
1395         case PORT_D:
1396                 return DP_AUX_CH_DATA(port, index);
1397         default:
1398                 MISSING_CASE(port);
1399                 return DP_AUX_CH_DATA(PORT_B, index);
1400         }
1401 }
1402
1403 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1404                                   enum port port)
1405 {
1406         switch (port) {
1407         case PORT_A:
1408                 return DP_AUX_CH_CTL(port);
1409         case PORT_B:
1410         case PORT_C:
1411         case PORT_D:
1412                 return PCH_DP_AUX_CH_CTL(port);
1413         default:
1414                 MISSING_CASE(port);
1415                 return DP_AUX_CH_CTL(PORT_A);
1416         }
1417 }
1418
1419 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1420                                    enum port port, int index)
1421 {
1422         switch (port) {
1423         case PORT_A:
1424                 return DP_AUX_CH_DATA(port, index);
1425         case PORT_B:
1426         case PORT_C:
1427         case PORT_D:
1428                 return PCH_DP_AUX_CH_DATA(port, index);
1429         default:
1430                 MISSING_CASE(port);
1431                 return DP_AUX_CH_DATA(PORT_A, index);
1432         }
1433 }
1434
1435 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1436                                   enum port port)
1437 {
1438         switch (port) {
1439         case PORT_A:
1440         case PORT_B:
1441         case PORT_C:
1442         case PORT_D:
1443         case PORT_F:
1444                 return DP_AUX_CH_CTL(port);
1445         default:
1446                 MISSING_CASE(port);
1447                 return DP_AUX_CH_CTL(PORT_A);
1448         }
1449 }
1450
1451 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1452                                    enum port port, int index)
1453 {
1454         switch (port) {
1455         case PORT_A:
1456         case PORT_B:
1457         case PORT_C:
1458         case PORT_D:
1459         case PORT_F:
1460                 return DP_AUX_CH_DATA(port, index);
1461         default:
1462                 MISSING_CASE(port);
1463                 return DP_AUX_CH_DATA(PORT_A, index);
1464         }
1465 }
1466
1467 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1468                                     enum port port)
1469 {
1470         if (INTEL_GEN(dev_priv) >= 9)
1471                 return skl_aux_ctl_reg(dev_priv, port);
1472         else if (HAS_PCH_SPLIT(dev_priv))
1473                 return ilk_aux_ctl_reg(dev_priv, port);
1474         else
1475                 return g4x_aux_ctl_reg(dev_priv, port);
1476 }
1477
1478 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1479                                      enum port port, int index)
1480 {
1481         if (INTEL_GEN(dev_priv) >= 9)
1482                 return skl_aux_data_reg(dev_priv, port, index);
1483         else if (HAS_PCH_SPLIT(dev_priv))
1484                 return ilk_aux_data_reg(dev_priv, port, index);
1485         else
1486                 return g4x_aux_data_reg(dev_priv, port, index);
1487 }
1488
1489 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1490 {
1491         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1492         enum port port = intel_aux_port(dev_priv,
1493                                         dp_to_dig_port(intel_dp)->base.port);
1494         int i;
1495
1496         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1497         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1498                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1499 }
1500
1501 static void
1502 intel_dp_aux_fini(struct intel_dp *intel_dp)
1503 {
1504         kfree(intel_dp->aux.name);
1505 }
1506
1507 static void
1508 intel_dp_aux_init(struct intel_dp *intel_dp)
1509 {
1510         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1511         enum port port = intel_dig_port->base.port;
1512
1513         intel_aux_reg_init(intel_dp);
1514         drm_dp_aux_init(&intel_dp->aux);
1515
1516         /* Failure to allocate our preferred name is not critical */
1517         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1518         intel_dp->aux.transfer = intel_dp_aux_transfer;
1519 }
1520
1521 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1522 {
1523         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1524
1525         return max_rate >= 540000;
1526 }
1527
1528 static void
1529 intel_dp_set_clock(struct intel_encoder *encoder,
1530                    struct intel_crtc_state *pipe_config)
1531 {
1532         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1533         const struct dp_link_dpll *divisor = NULL;
1534         int i, count = 0;
1535
1536         if (IS_G4X(dev_priv)) {
1537                 divisor = gen4_dpll;
1538                 count = ARRAY_SIZE(gen4_dpll);
1539         } else if (HAS_PCH_SPLIT(dev_priv)) {
1540                 divisor = pch_dpll;
1541                 count = ARRAY_SIZE(pch_dpll);
1542         } else if (IS_CHERRYVIEW(dev_priv)) {
1543                 divisor = chv_dpll;
1544                 count = ARRAY_SIZE(chv_dpll);
1545         } else if (IS_VALLEYVIEW(dev_priv)) {
1546                 divisor = vlv_dpll;
1547                 count = ARRAY_SIZE(vlv_dpll);
1548         }
1549
1550         if (divisor && count) {
1551                 for (i = 0; i < count; i++) {
1552                         if (pipe_config->port_clock == divisor[i].clock) {
1553                                 pipe_config->dpll = divisor[i].dpll;
1554                                 pipe_config->clock_set = true;
1555                                 break;
1556                         }
1557                 }
1558         }
1559 }
1560
1561 static void snprintf_int_array(char *str, size_t len,
1562                                const int *array, int nelem)
1563 {
1564         int i;
1565
1566         str[0] = '\0';
1567
1568         for (i = 0; i < nelem; i++) {
1569                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1570                 if (r >= len)
1571                         return;
1572                 str += r;
1573                 len -= r;
1574         }
1575 }
1576
1577 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1578 {
1579         char str[128]; /* FIXME: too big for stack? */
1580
1581         if ((drm_debug & DRM_UT_KMS) == 0)
1582                 return;
1583
1584         snprintf_int_array(str, sizeof(str),
1585                            intel_dp->source_rates, intel_dp->num_source_rates);
1586         DRM_DEBUG_KMS("source rates: %s\n", str);
1587
1588         snprintf_int_array(str, sizeof(str),
1589                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1590         DRM_DEBUG_KMS("sink rates: %s\n", str);
1591
1592         snprintf_int_array(str, sizeof(str),
1593                            intel_dp->common_rates, intel_dp->num_common_rates);
1594         DRM_DEBUG_KMS("common rates: %s\n", str);
1595 }
1596
1597 int
1598 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1599 {
1600         int len;
1601
1602         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1603         if (WARN_ON(len <= 0))
1604                 return 162000;
1605
1606         return intel_dp->common_rates[len - 1];
1607 }
1608
1609 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1610 {
1611         int i = intel_dp_rate_index(intel_dp->sink_rates,
1612                                     intel_dp->num_sink_rates, rate);
1613
1614         if (WARN_ON(i < 0))
1615                 i = 0;
1616
1617         return i;
1618 }
1619
1620 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1621                            uint8_t *link_bw, uint8_t *rate_select)
1622 {
1623         /* eDP 1.4 rate select method. */
1624         if (intel_dp->use_rate_select) {
1625                 *link_bw = 0;
1626                 *rate_select =
1627                         intel_dp_rate_select(intel_dp, port_clock);
1628         } else {
1629                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1630                 *rate_select = 0;
1631         }
1632 }
1633
1634 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1635                                 struct intel_crtc_state *pipe_config)
1636 {
1637         int bpp, bpc;
1638
1639         bpp = pipe_config->pipe_bpp;
1640         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1641
1642         if (bpc > 0)
1643                 bpp = min(bpp, 3*bpc);
1644
1645         /* For DP Compliance we override the computed bpp for the pipe */
1646         if (intel_dp->compliance.test_data.bpc != 0) {
1647                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1648                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1649                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1650                               pipe_config->pipe_bpp);
1651         }
1652         return bpp;
1653 }
1654
1655 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1656                                        struct drm_display_mode *m2)
1657 {
1658         bool bres = false;
1659
1660         if (m1 && m2)
1661                 bres = (m1->hdisplay == m2->hdisplay &&
1662                         m1->hsync_start == m2->hsync_start &&
1663                         m1->hsync_end == m2->hsync_end &&
1664                         m1->htotal == m2->htotal &&
1665                         m1->vdisplay == m2->vdisplay &&
1666                         m1->vsync_start == m2->vsync_start &&
1667                         m1->vsync_end == m2->vsync_end &&
1668                         m1->vtotal == m2->vtotal);
1669         return bres;
1670 }
1671
1672 bool
1673 intel_dp_compute_config(struct intel_encoder *encoder,
1674                         struct intel_crtc_state *pipe_config,
1675                         struct drm_connector_state *conn_state)
1676 {
1677         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1678         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1679         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1680         enum port port = encoder->port;
1681         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1682         struct intel_connector *intel_connector = intel_dp->attached_connector;
1683         struct intel_digital_connector_state *intel_conn_state =
1684                 to_intel_digital_connector_state(conn_state);
1685         int lane_count, clock;
1686         int min_lane_count = 1;
1687         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1688         /* Conveniently, the link BW constants become indices with a shift...*/
1689         int min_clock = 0;
1690         int max_clock;
1691         int bpp, mode_rate;
1692         int link_avail, link_clock;
1693         int common_len;
1694         uint8_t link_bw, rate_select;
1695         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1696                                            DP_DPCD_QUIRK_LIMITED_M_N);
1697
1698         common_len = intel_dp_common_len_rate_limit(intel_dp,
1699                                                     intel_dp->max_link_rate);
1700
1701         /* No common link rates between source and sink */
1702         WARN_ON(common_len <= 0);
1703
1704         max_clock = common_len - 1;
1705
1706         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1707                 pipe_config->has_pch_encoder = true;
1708
1709         pipe_config->has_drrs = false;
1710         if (IS_G4X(dev_priv) || port == PORT_A)
1711                 pipe_config->has_audio = false;
1712         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1713                 pipe_config->has_audio = intel_dp->has_audio;
1714         else
1715                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1716
1717         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1718                 struct drm_display_mode *panel_mode =
1719                         intel_connector->panel.alt_fixed_mode;
1720                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1721
1722                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1723                         panel_mode = intel_connector->panel.fixed_mode;
1724
1725                 drm_mode_debug_printmodeline(panel_mode);
1726
1727                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1728
1729                 if (INTEL_GEN(dev_priv) >= 9) {
1730                         int ret;
1731                         ret = skl_update_scaler_crtc(pipe_config);
1732                         if (ret)
1733                                 return ret;
1734                 }
1735
1736                 if (HAS_GMCH_DISPLAY(dev_priv))
1737                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1738                                                  conn_state->scaling_mode);
1739                 else
1740                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1741                                                 conn_state->scaling_mode);
1742         }
1743
1744         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1745             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1746                 return false;
1747
1748         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1749                 return false;
1750
1751         /* Use values requested by Compliance Test Request */
1752         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1753                 int index;
1754
1755                 /* Validate the compliance test data since max values
1756                  * might have changed due to link train fallback.
1757                  */
1758                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1759                                                intel_dp->compliance.test_lane_count)) {
1760                         index = intel_dp_rate_index(intel_dp->common_rates,
1761                                                     intel_dp->num_common_rates,
1762                                                     intel_dp->compliance.test_link_rate);
1763                         if (index >= 0)
1764                                 min_clock = max_clock = index;
1765                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1766                 }
1767         }
1768         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1769                       "max bw %d pixel clock %iKHz\n",
1770                       max_lane_count, intel_dp->common_rates[max_clock],
1771                       adjusted_mode->crtc_clock);
1772
1773         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1774          * bpc in between. */
1775         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1776         if (intel_dp_is_edp(intel_dp)) {
1777
1778                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1779                 if (intel_connector->base.display_info.bpc == 0 &&
1780                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1781                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1782                                       dev_priv->vbt.edp.bpp);
1783                         bpp = dev_priv->vbt.edp.bpp;
1784                 }
1785
1786                 /*
1787                  * Use the maximum clock and number of lanes the eDP panel
1788                  * advertizes being capable of. The panels are generally
1789                  * designed to support only a single clock and lane
1790                  * configuration, and typically these values correspond to the
1791                  * native resolution of the panel.
1792                  */
1793                 min_lane_count = max_lane_count;
1794                 min_clock = max_clock;
1795         }
1796
1797         for (; bpp >= 6*3; bpp -= 2*3) {
1798                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1799                                                    bpp);
1800
1801                 for (clock = min_clock; clock <= max_clock; clock++) {
1802                         for (lane_count = min_lane_count;
1803                                 lane_count <= max_lane_count;
1804                                 lane_count <<= 1) {
1805
1806                                 link_clock = intel_dp->common_rates[clock];
1807                                 link_avail = intel_dp_max_data_rate(link_clock,
1808                                                                     lane_count);
1809
1810                                 if (mode_rate <= link_avail) {
1811                                         goto found;
1812                                 }
1813                         }
1814                 }
1815         }
1816
1817         return false;
1818
1819 found:
1820         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1821                 /*
1822                  * See:
1823                  * CEA-861-E - 5.1 Default Encoding Parameters
1824                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1825                  */
1826                 pipe_config->limited_color_range =
1827                         bpp != 18 &&
1828                         drm_default_rgb_quant_range(adjusted_mode) ==
1829                         HDMI_QUANTIZATION_RANGE_LIMITED;
1830         } else {
1831                 pipe_config->limited_color_range =
1832                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1833         }
1834
1835         pipe_config->lane_count = lane_count;
1836
1837         pipe_config->pipe_bpp = bpp;
1838         pipe_config->port_clock = intel_dp->common_rates[clock];
1839
1840         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1841                               &link_bw, &rate_select);
1842
1843         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1844                       link_bw, rate_select, pipe_config->lane_count,
1845                       pipe_config->port_clock, bpp);
1846         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1847                       mode_rate, link_avail);
1848
1849         intel_link_compute_m_n(bpp, lane_count,
1850                                adjusted_mode->crtc_clock,
1851                                pipe_config->port_clock,
1852                                &pipe_config->dp_m_n,
1853                                reduce_m_n);
1854
1855         if (intel_connector->panel.downclock_mode != NULL &&
1856                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1857                         pipe_config->has_drrs = true;
1858                         intel_link_compute_m_n(bpp, lane_count,
1859                                 intel_connector->panel.downclock_mode->clock,
1860                                 pipe_config->port_clock,
1861                                 &pipe_config->dp_m2_n2,
1862                                 reduce_m_n);
1863         }
1864
1865         /*
1866          * DPLL0 VCO may need to be adjusted to get the correct
1867          * clock for eDP. This will affect cdclk as well.
1868          */
1869         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1870                 int vco;
1871
1872                 switch (pipe_config->port_clock / 2) {
1873                 case 108000:
1874                 case 216000:
1875                         vco = 8640000;
1876                         break;
1877                 default:
1878                         vco = 8100000;
1879                         break;
1880                 }
1881
1882                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1883         }
1884
1885         if (!HAS_DDI(dev_priv))
1886                 intel_dp_set_clock(encoder, pipe_config);
1887
1888         intel_psr_compute_config(intel_dp, pipe_config);
1889
1890         return true;
1891 }
1892
1893 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1894                               int link_rate, uint8_t lane_count,
1895                               bool link_mst)
1896 {
1897         intel_dp->link_rate = link_rate;
1898         intel_dp->lane_count = lane_count;
1899         intel_dp->link_mst = link_mst;
1900 }
1901
1902 static void intel_dp_prepare(struct intel_encoder *encoder,
1903                              const struct intel_crtc_state *pipe_config)
1904 {
1905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1906         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907         enum port port = encoder->port;
1908         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1909         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1910
1911         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1912                                  pipe_config->lane_count,
1913                                  intel_crtc_has_type(pipe_config,
1914                                                      INTEL_OUTPUT_DP_MST));
1915
1916         /*
1917          * There are four kinds of DP registers:
1918          *
1919          *      IBX PCH
1920          *      SNB CPU
1921          *      IVB CPU
1922          *      CPT PCH
1923          *
1924          * IBX PCH and CPU are the same for almost everything,
1925          * except that the CPU DP PLL is configured in this
1926          * register
1927          *
1928          * CPT PCH is quite different, having many bits moved
1929          * to the TRANS_DP_CTL register instead. That
1930          * configuration happens (oddly) in ironlake_pch_enable
1931          */
1932
1933         /* Preserve the BIOS-computed detected bit. This is
1934          * supposed to be read-only.
1935          */
1936         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1937
1938         /* Handle DP bits in common between all three register formats */
1939         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1940         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1941
1942         /* Split out the IBX/CPU vs CPT settings */
1943
1944         if (IS_GEN7(dev_priv) && port == PORT_A) {
1945                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1946                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1947                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1948                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1949                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1950
1951                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1952                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1953
1954                 intel_dp->DP |= crtc->pipe << 29;
1955         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1956                 u32 trans_dp;
1957
1958                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1959
1960                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1961                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1962                         trans_dp |= TRANS_DP_ENH_FRAMING;
1963                 else
1964                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1965                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1966         } else {
1967                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1968                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1969
1970                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1971                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1972                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1973                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1974                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1975
1976                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1977                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1978
1979                 if (IS_CHERRYVIEW(dev_priv))
1980                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1981                 else if (crtc->pipe == PIPE_B)
1982                         intel_dp->DP |= DP_PIPEB_SELECT;
1983         }
1984 }
1985
1986 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1987 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1988
1989 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1990 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1991
1992 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1993 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1994
1995 static void intel_pps_verify_state(struct intel_dp *intel_dp);
1996
1997 static void wait_panel_status(struct intel_dp *intel_dp,
1998                                        u32 mask,
1999                                        u32 value)
2000 {
2001         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2002         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2003
2004         lockdep_assert_held(&dev_priv->pps_mutex);
2005
2006         intel_pps_verify_state(intel_dp);
2007
2008         pp_stat_reg = _pp_stat_reg(intel_dp);
2009         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2010
2011         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2012                         mask, value,
2013                         I915_READ(pp_stat_reg),
2014                         I915_READ(pp_ctrl_reg));
2015
2016         if (intel_wait_for_register(dev_priv,
2017                                     pp_stat_reg, mask, value,
2018                                     5000))
2019                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2020                                 I915_READ(pp_stat_reg),
2021                                 I915_READ(pp_ctrl_reg));
2022
2023         DRM_DEBUG_KMS("Wait complete\n");
2024 }
2025
2026 static void wait_panel_on(struct intel_dp *intel_dp)
2027 {
2028         DRM_DEBUG_KMS("Wait for panel power on\n");
2029         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2030 }
2031
2032 static void wait_panel_off(struct intel_dp *intel_dp)
2033 {
2034         DRM_DEBUG_KMS("Wait for panel power off time\n");
2035         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2036 }
2037
2038 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2039 {
2040         ktime_t panel_power_on_time;
2041         s64 panel_power_off_duration;
2042
2043         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2044
2045         /* take the difference of currrent time and panel power off time
2046          * and then make panel wait for t11_t12 if needed. */
2047         panel_power_on_time = ktime_get_boottime();
2048         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2049
2050         /* When we disable the VDD override bit last we have to do the manual
2051          * wait. */
2052         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2053                 wait_remaining_ms_from_jiffies(jiffies,
2054                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2055
2056         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2057 }
2058
2059 static void wait_backlight_on(struct intel_dp *intel_dp)
2060 {
2061         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2062                                        intel_dp->backlight_on_delay);
2063 }
2064
2065 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2066 {
2067         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2068                                        intel_dp->backlight_off_delay);
2069 }
2070
2071 /* Read the current pp_control value, unlocking the register if it
2072  * is locked
2073  */
2074
2075 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2076 {
2077         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2078         u32 control;
2079
2080         lockdep_assert_held(&dev_priv->pps_mutex);
2081
2082         control = I915_READ(_pp_ctrl_reg(intel_dp));
2083         if (WARN_ON(!HAS_DDI(dev_priv) &&
2084                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2085                 control &= ~PANEL_UNLOCK_MASK;
2086                 control |= PANEL_UNLOCK_REGS;
2087         }
2088         return control;
2089 }
2090
2091 /*
2092  * Must be paired with edp_panel_vdd_off().
2093  * Must hold pps_mutex around the whole on/off sequence.
2094  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2095  */
2096 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2097 {
2098         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2099         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2100         u32 pp;
2101         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2102         bool need_to_disable = !intel_dp->want_panel_vdd;
2103
2104         lockdep_assert_held(&dev_priv->pps_mutex);
2105
2106         if (!intel_dp_is_edp(intel_dp))
2107                 return false;
2108
2109         cancel_delayed_work(&intel_dp->panel_vdd_work);
2110         intel_dp->want_panel_vdd = true;
2111
2112         if (edp_have_panel_vdd(intel_dp))
2113                 return need_to_disable;
2114
2115         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2116
2117         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2118                       port_name(intel_dig_port->base.port));
2119
2120         if (!edp_have_panel_power(intel_dp))
2121                 wait_panel_power_cycle(intel_dp);
2122
2123         pp = ironlake_get_pp_control(intel_dp);
2124         pp |= EDP_FORCE_VDD;
2125
2126         pp_stat_reg = _pp_stat_reg(intel_dp);
2127         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2128
2129         I915_WRITE(pp_ctrl_reg, pp);
2130         POSTING_READ(pp_ctrl_reg);
2131         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2132                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2133         /*
2134          * If the panel wasn't on, delay before accessing aux channel
2135          */
2136         if (!edp_have_panel_power(intel_dp)) {
2137                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2138                               port_name(intel_dig_port->base.port));
2139                 msleep(intel_dp->panel_power_up_delay);
2140         }
2141
2142         return need_to_disable;
2143 }
2144
2145 /*
2146  * Must be paired with intel_edp_panel_vdd_off() or
2147  * intel_edp_panel_off().
2148  * Nested calls to these functions are not allowed since
2149  * we drop the lock. Caller must use some higher level
2150  * locking to prevent nested calls from other threads.
2151  */
2152 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2153 {
2154         bool vdd;
2155
2156         if (!intel_dp_is_edp(intel_dp))
2157                 return;
2158
2159         pps_lock(intel_dp);
2160         vdd = edp_panel_vdd_on(intel_dp);
2161         pps_unlock(intel_dp);
2162
2163         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2164              port_name(dp_to_dig_port(intel_dp)->base.port));
2165 }
2166
2167 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2168 {
2169         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2170         struct intel_digital_port *intel_dig_port =
2171                 dp_to_dig_port(intel_dp);
2172         u32 pp;
2173         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2174
2175         lockdep_assert_held(&dev_priv->pps_mutex);
2176
2177         WARN_ON(intel_dp->want_panel_vdd);
2178
2179         if (!edp_have_panel_vdd(intel_dp))
2180                 return;
2181
2182         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2183                       port_name(intel_dig_port->base.port));
2184
2185         pp = ironlake_get_pp_control(intel_dp);
2186         pp &= ~EDP_FORCE_VDD;
2187
2188         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2189         pp_stat_reg = _pp_stat_reg(intel_dp);
2190
2191         I915_WRITE(pp_ctrl_reg, pp);
2192         POSTING_READ(pp_ctrl_reg);
2193
2194         /* Make sure sequencer is idle before allowing subsequent activity */
2195         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2196         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2197
2198         if ((pp & PANEL_POWER_ON) == 0)
2199                 intel_dp->panel_power_off_time = ktime_get_boottime();
2200
2201         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2202 }
2203
2204 static void edp_panel_vdd_work(struct work_struct *__work)
2205 {
2206         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2207                                                  struct intel_dp, panel_vdd_work);
2208
2209         pps_lock(intel_dp);
2210         if (!intel_dp->want_panel_vdd)
2211                 edp_panel_vdd_off_sync(intel_dp);
2212         pps_unlock(intel_dp);
2213 }
2214
2215 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2216 {
2217         unsigned long delay;
2218
2219         /*
2220          * Queue the timer to fire a long time from now (relative to the power
2221          * down delay) to keep the panel power up across a sequence of
2222          * operations.
2223          */
2224         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2225         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2226 }
2227
2228 /*
2229  * Must be paired with edp_panel_vdd_on().
2230  * Must hold pps_mutex around the whole on/off sequence.
2231  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2232  */
2233 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2234 {
2235         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2236
2237         lockdep_assert_held(&dev_priv->pps_mutex);
2238
2239         if (!intel_dp_is_edp(intel_dp))
2240                 return;
2241
2242         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2243              port_name(dp_to_dig_port(intel_dp)->base.port));
2244
2245         intel_dp->want_panel_vdd = false;
2246
2247         if (sync)
2248                 edp_panel_vdd_off_sync(intel_dp);
2249         else
2250                 edp_panel_vdd_schedule_off(intel_dp);
2251 }
2252
2253 static void edp_panel_on(struct intel_dp *intel_dp)
2254 {
2255         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2256         u32 pp;
2257         i915_reg_t pp_ctrl_reg;
2258
2259         lockdep_assert_held(&dev_priv->pps_mutex);
2260
2261         if (!intel_dp_is_edp(intel_dp))
2262                 return;
2263
2264         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2265                       port_name(dp_to_dig_port(intel_dp)->base.port));
2266
2267         if (WARN(edp_have_panel_power(intel_dp),
2268                  "eDP port %c panel power already on\n",
2269                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2270                 return;
2271
2272         wait_panel_power_cycle(intel_dp);
2273
2274         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2275         pp = ironlake_get_pp_control(intel_dp);
2276         if (IS_GEN5(dev_priv)) {
2277                 /* ILK workaround: disable reset around power sequence */
2278                 pp &= ~PANEL_POWER_RESET;
2279                 I915_WRITE(pp_ctrl_reg, pp);
2280                 POSTING_READ(pp_ctrl_reg);
2281         }
2282
2283         pp |= PANEL_POWER_ON;
2284         if (!IS_GEN5(dev_priv))
2285                 pp |= PANEL_POWER_RESET;
2286
2287         I915_WRITE(pp_ctrl_reg, pp);
2288         POSTING_READ(pp_ctrl_reg);
2289
2290         wait_panel_on(intel_dp);
2291         intel_dp->last_power_on = jiffies;
2292
2293         if (IS_GEN5(dev_priv)) {
2294                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2295                 I915_WRITE(pp_ctrl_reg, pp);
2296                 POSTING_READ(pp_ctrl_reg);
2297         }
2298 }
2299
2300 void intel_edp_panel_on(struct intel_dp *intel_dp)
2301 {
2302         if (!intel_dp_is_edp(intel_dp))
2303                 return;
2304
2305         pps_lock(intel_dp);
2306         edp_panel_on(intel_dp);
2307         pps_unlock(intel_dp);
2308 }
2309
2310
2311 static void edp_panel_off(struct intel_dp *intel_dp)
2312 {
2313         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2314         u32 pp;
2315         i915_reg_t pp_ctrl_reg;
2316
2317         lockdep_assert_held(&dev_priv->pps_mutex);
2318
2319         if (!intel_dp_is_edp(intel_dp))
2320                 return;
2321
2322         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2323                       port_name(dp_to_dig_port(intel_dp)->base.port));
2324
2325         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2326              port_name(dp_to_dig_port(intel_dp)->base.port));
2327
2328         pp = ironlake_get_pp_control(intel_dp);
2329         /* We need to switch off panel power _and_ force vdd, for otherwise some
2330          * panels get very unhappy and cease to work. */
2331         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2332                 EDP_BLC_ENABLE);
2333
2334         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2335
2336         intel_dp->want_panel_vdd = false;
2337
2338         I915_WRITE(pp_ctrl_reg, pp);
2339         POSTING_READ(pp_ctrl_reg);
2340
2341         wait_panel_off(intel_dp);
2342         intel_dp->panel_power_off_time = ktime_get_boottime();
2343
2344         /* We got a reference when we enabled the VDD. */
2345         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2346 }
2347
2348 void intel_edp_panel_off(struct intel_dp *intel_dp)
2349 {
2350         if (!intel_dp_is_edp(intel_dp))
2351                 return;
2352
2353         pps_lock(intel_dp);
2354         edp_panel_off(intel_dp);
2355         pps_unlock(intel_dp);
2356 }
2357
2358 /* Enable backlight in the panel power control. */
2359 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2360 {
2361         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2362         u32 pp;
2363         i915_reg_t pp_ctrl_reg;
2364
2365         /*
2366          * If we enable the backlight right away following a panel power
2367          * on, we may see slight flicker as the panel syncs with the eDP
2368          * link.  So delay a bit to make sure the image is solid before
2369          * allowing it to appear.
2370          */
2371         wait_backlight_on(intel_dp);
2372
2373         pps_lock(intel_dp);
2374
2375         pp = ironlake_get_pp_control(intel_dp);
2376         pp |= EDP_BLC_ENABLE;
2377
2378         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2379
2380         I915_WRITE(pp_ctrl_reg, pp);
2381         POSTING_READ(pp_ctrl_reg);
2382
2383         pps_unlock(intel_dp);
2384 }
2385
2386 /* Enable backlight PWM and backlight PP control. */
2387 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2388                             const struct drm_connector_state *conn_state)
2389 {
2390         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2391
2392         if (!intel_dp_is_edp(intel_dp))
2393                 return;
2394
2395         DRM_DEBUG_KMS("\n");
2396
2397         intel_panel_enable_backlight(crtc_state, conn_state);
2398         _intel_edp_backlight_on(intel_dp);
2399 }
2400
2401 /* Disable backlight in the panel power control. */
2402 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2403 {
2404         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2405         u32 pp;
2406         i915_reg_t pp_ctrl_reg;
2407
2408         if (!intel_dp_is_edp(intel_dp))
2409                 return;
2410
2411         pps_lock(intel_dp);
2412
2413         pp = ironlake_get_pp_control(intel_dp);
2414         pp &= ~EDP_BLC_ENABLE;
2415
2416         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2417
2418         I915_WRITE(pp_ctrl_reg, pp);
2419         POSTING_READ(pp_ctrl_reg);
2420
2421         pps_unlock(intel_dp);
2422
2423         intel_dp->last_backlight_off = jiffies;
2424         edp_wait_backlight_off(intel_dp);
2425 }
2426
2427 /* Disable backlight PP control and backlight PWM. */
2428 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2429 {
2430         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2431
2432         if (!intel_dp_is_edp(intel_dp))
2433                 return;
2434
2435         DRM_DEBUG_KMS("\n");
2436
2437         _intel_edp_backlight_off(intel_dp);
2438         intel_panel_disable_backlight(old_conn_state);
2439 }
2440
2441 /*
2442  * Hook for controlling the panel power control backlight through the bl_power
2443  * sysfs attribute. Take care to handle multiple calls.
2444  */
2445 static void intel_edp_backlight_power(struct intel_connector *connector,
2446                                       bool enable)
2447 {
2448         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2449         bool is_enabled;
2450
2451         pps_lock(intel_dp);
2452         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2453         pps_unlock(intel_dp);
2454
2455         if (is_enabled == enable)
2456                 return;
2457
2458         DRM_DEBUG_KMS("panel power control backlight %s\n",
2459                       enable ? "enable" : "disable");
2460
2461         if (enable)
2462                 _intel_edp_backlight_on(intel_dp);
2463         else
2464                 _intel_edp_backlight_off(intel_dp);
2465 }
2466
2467 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2468 {
2469         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2470         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2471         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2472
2473         I915_STATE_WARN(cur_state != state,
2474                         "DP port %c state assertion failure (expected %s, current %s)\n",
2475                         port_name(dig_port->base.port),
2476                         onoff(state), onoff(cur_state));
2477 }
2478 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2479
2480 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2481 {
2482         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2483
2484         I915_STATE_WARN(cur_state != state,
2485                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2486                         onoff(state), onoff(cur_state));
2487 }
2488 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2489 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2490
2491 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2492                                 const struct intel_crtc_state *pipe_config)
2493 {
2494         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2495         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2496
2497         assert_pipe_disabled(dev_priv, crtc->pipe);
2498         assert_dp_port_disabled(intel_dp);
2499         assert_edp_pll_disabled(dev_priv);
2500
2501         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2502                       pipe_config->port_clock);
2503
2504         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2505
2506         if (pipe_config->port_clock == 162000)
2507                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2508         else
2509                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2510
2511         I915_WRITE(DP_A, intel_dp->DP);
2512         POSTING_READ(DP_A);
2513         udelay(500);
2514
2515         /*
2516          * [DevILK] Work around required when enabling DP PLL
2517          * while a pipe is enabled going to FDI:
2518          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2519          * 2. Program DP PLL enable
2520          */
2521         if (IS_GEN5(dev_priv))
2522                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2523
2524         intel_dp->DP |= DP_PLL_ENABLE;
2525
2526         I915_WRITE(DP_A, intel_dp->DP);
2527         POSTING_READ(DP_A);
2528         udelay(200);
2529 }
2530
2531 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2532                                  const struct intel_crtc_state *old_crtc_state)
2533 {
2534         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2536
2537         assert_pipe_disabled(dev_priv, crtc->pipe);
2538         assert_dp_port_disabled(intel_dp);
2539         assert_edp_pll_enabled(dev_priv);
2540
2541         DRM_DEBUG_KMS("disabling eDP PLL\n");
2542
2543         intel_dp->DP &= ~DP_PLL_ENABLE;
2544
2545         I915_WRITE(DP_A, intel_dp->DP);
2546         POSTING_READ(DP_A);
2547         udelay(200);
2548 }
2549
2550 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2551 {
2552         /*
2553          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2554          * be capable of signalling downstream hpd with a long pulse.
2555          * Whether or not that means D3 is safe to use is not clear,
2556          * but let's assume so until proven otherwise.
2557          *
2558          * FIXME should really check all downstream ports...
2559          */
2560         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2561                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2562                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2563 }
2564
2565 /* If the sink supports it, try to set the power state appropriately */
2566 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2567 {
2568         int ret, i;
2569
2570         /* Should have a valid DPCD by this point */
2571         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2572                 return;
2573
2574         if (mode != DRM_MODE_DPMS_ON) {
2575                 if (downstream_hpd_needs_d0(intel_dp))
2576                         return;
2577
2578                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2579                                          DP_SET_POWER_D3);
2580         } else {
2581                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2582
2583                 /*
2584                  * When turning on, we need to retry for 1ms to give the sink
2585                  * time to wake up.
2586                  */
2587                 for (i = 0; i < 3; i++) {
2588                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2589                                                  DP_SET_POWER_D0);
2590                         if (ret == 1)
2591                                 break;
2592                         msleep(1);
2593                 }
2594
2595                 if (ret == 1 && lspcon->active)
2596                         lspcon_wait_pcon_mode(lspcon);
2597         }
2598
2599         if (ret != 1)
2600                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2601                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2602 }
2603
2604 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2605                                   enum pipe *pipe)
2606 {
2607         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2608         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2609         enum port port = encoder->port;
2610         u32 tmp;
2611         bool ret;
2612
2613         if (!intel_display_power_get_if_enabled(dev_priv,
2614                                                 encoder->power_domain))
2615                 return false;
2616
2617         ret = false;
2618
2619         tmp = I915_READ(intel_dp->output_reg);
2620
2621         if (!(tmp & DP_PORT_EN))
2622                 goto out;
2623
2624         if (IS_GEN7(dev_priv) && port == PORT_A) {
2625                 *pipe = PORT_TO_PIPE_CPT(tmp);
2626         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2627                 enum pipe p;
2628
2629                 for_each_pipe(dev_priv, p) {
2630                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2631                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2632                                 *pipe = p;
2633                                 ret = true;
2634
2635                                 goto out;
2636                         }
2637                 }
2638
2639                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2640                               i915_mmio_reg_offset(intel_dp->output_reg));
2641         } else if (IS_CHERRYVIEW(dev_priv)) {
2642                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2643         } else {
2644                 *pipe = PORT_TO_PIPE(tmp);
2645         }
2646
2647         ret = true;
2648
2649 out:
2650         intel_display_power_put(dev_priv, encoder->power_domain);
2651
2652         return ret;
2653 }
2654
2655 static void intel_dp_get_config(struct intel_encoder *encoder,
2656                                 struct intel_crtc_state *pipe_config)
2657 {
2658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2659         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2660         u32 tmp, flags = 0;
2661         enum port port = encoder->port;
2662         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2663
2664         if (encoder->type == INTEL_OUTPUT_EDP)
2665                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2666         else
2667                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2668
2669         tmp = I915_READ(intel_dp->output_reg);
2670
2671         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2672
2673         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2674                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2675
2676                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2677                         flags |= DRM_MODE_FLAG_PHSYNC;
2678                 else
2679                         flags |= DRM_MODE_FLAG_NHSYNC;
2680
2681                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2682                         flags |= DRM_MODE_FLAG_PVSYNC;
2683                 else
2684                         flags |= DRM_MODE_FLAG_NVSYNC;
2685         } else {
2686                 if (tmp & DP_SYNC_HS_HIGH)
2687                         flags |= DRM_MODE_FLAG_PHSYNC;
2688                 else
2689                         flags |= DRM_MODE_FLAG_NHSYNC;
2690
2691                 if (tmp & DP_SYNC_VS_HIGH)
2692                         flags |= DRM_MODE_FLAG_PVSYNC;
2693                 else
2694                         flags |= DRM_MODE_FLAG_NVSYNC;
2695         }
2696
2697         pipe_config->base.adjusted_mode.flags |= flags;
2698
2699         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2700                 pipe_config->limited_color_range = true;
2701
2702         pipe_config->lane_count =
2703                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2704
2705         intel_dp_get_m_n(crtc, pipe_config);
2706
2707         if (port == PORT_A) {
2708                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2709                         pipe_config->port_clock = 162000;
2710                 else
2711                         pipe_config->port_clock = 270000;
2712         }
2713
2714         pipe_config->base.adjusted_mode.crtc_clock =
2715                 intel_dotclock_calculate(pipe_config->port_clock,
2716                                          &pipe_config->dp_m_n);
2717
2718         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2719             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2720                 /*
2721                  * This is a big fat ugly hack.
2722                  *
2723                  * Some machines in UEFI boot mode provide us a VBT that has 18
2724                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2725                  * unknown we fail to light up. Yet the same BIOS boots up with
2726                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2727                  * max, not what it tells us to use.
2728                  *
2729                  * Note: This will still be broken if the eDP panel is not lit
2730                  * up by the BIOS, and thus we can't get the mode at module
2731                  * load.
2732                  */
2733                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2734                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2735                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2736         }
2737 }
2738
2739 static void intel_disable_dp(struct intel_encoder *encoder,
2740                              const struct intel_crtc_state *old_crtc_state,
2741                              const struct drm_connector_state *old_conn_state)
2742 {
2743         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2744
2745         if (old_crtc_state->has_audio)
2746                 intel_audio_codec_disable(encoder,
2747                                           old_crtc_state, old_conn_state);
2748
2749         /* Make sure the panel is off before trying to change the mode. But also
2750          * ensure that we have vdd while we switch off the panel. */
2751         intel_edp_panel_vdd_on(intel_dp);
2752         intel_edp_backlight_off(old_conn_state);
2753         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2754         intel_edp_panel_off(intel_dp);
2755 }
2756
2757 static void g4x_disable_dp(struct intel_encoder *encoder,
2758                            const struct intel_crtc_state *old_crtc_state,
2759                            const struct drm_connector_state *old_conn_state)
2760 {
2761         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2762
2763         /* disable the port before the pipe on g4x */
2764         intel_dp_link_down(encoder, old_crtc_state);
2765 }
2766
2767 static void ilk_disable_dp(struct intel_encoder *encoder,
2768                            const struct intel_crtc_state *old_crtc_state,
2769                            const struct drm_connector_state *old_conn_state)
2770 {
2771         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2772 }
2773
2774 static void vlv_disable_dp(struct intel_encoder *encoder,
2775                            const struct intel_crtc_state *old_crtc_state,
2776                            const struct drm_connector_state *old_conn_state)
2777 {
2778         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2779
2780         intel_psr_disable(intel_dp, old_crtc_state);
2781
2782         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2783 }
2784
2785 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2786                                 const struct intel_crtc_state *old_crtc_state,
2787                                 const struct drm_connector_state *old_conn_state)
2788 {
2789         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2790         enum port port = encoder->port;
2791
2792         intel_dp_link_down(encoder, old_crtc_state);
2793
2794         /* Only ilk+ has port A */
2795         if (port == PORT_A)
2796                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2797 }
2798
2799 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2800                                 const struct intel_crtc_state *old_crtc_state,
2801                                 const struct drm_connector_state *old_conn_state)
2802 {
2803         intel_dp_link_down(encoder, old_crtc_state);
2804 }
2805
2806 static void chv_post_disable_dp(struct intel_encoder *encoder,
2807                                 const struct intel_crtc_state *old_crtc_state,
2808                                 const struct drm_connector_state *old_conn_state)
2809 {
2810         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2811
2812         intel_dp_link_down(encoder, old_crtc_state);
2813
2814         mutex_lock(&dev_priv->sb_lock);
2815
2816         /* Assert data lane reset */
2817         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2818
2819         mutex_unlock(&dev_priv->sb_lock);
2820 }
2821
2822 static void
2823 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2824                          uint32_t *DP,
2825                          uint8_t dp_train_pat)
2826 {
2827         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2828         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2829         enum port port = intel_dig_port->base.port;
2830
2831         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2832                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2833                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2834
2835         if (HAS_DDI(dev_priv)) {
2836                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2837
2838                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2839                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2840                 else
2841                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2842
2843                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2844                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2845                 case DP_TRAINING_PATTERN_DISABLE:
2846                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2847
2848                         break;
2849                 case DP_TRAINING_PATTERN_1:
2850                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2851                         break;
2852                 case DP_TRAINING_PATTERN_2:
2853                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2854                         break;
2855                 case DP_TRAINING_PATTERN_3:
2856                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2857                         break;
2858                 }
2859                 I915_WRITE(DP_TP_CTL(port), temp);
2860
2861         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2862                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2863                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2864
2865                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2866                 case DP_TRAINING_PATTERN_DISABLE:
2867                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2868                         break;
2869                 case DP_TRAINING_PATTERN_1:
2870                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2871                         break;
2872                 case DP_TRAINING_PATTERN_2:
2873                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2874                         break;
2875                 case DP_TRAINING_PATTERN_3:
2876                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2877                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2878                         break;
2879                 }
2880
2881         } else {
2882                 if (IS_CHERRYVIEW(dev_priv))
2883                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2884                 else
2885                         *DP &= ~DP_LINK_TRAIN_MASK;
2886
2887                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2888                 case DP_TRAINING_PATTERN_DISABLE:
2889                         *DP |= DP_LINK_TRAIN_OFF;
2890                         break;
2891                 case DP_TRAINING_PATTERN_1:
2892                         *DP |= DP_LINK_TRAIN_PAT_1;
2893                         break;
2894                 case DP_TRAINING_PATTERN_2:
2895                         *DP |= DP_LINK_TRAIN_PAT_2;
2896                         break;
2897                 case DP_TRAINING_PATTERN_3:
2898                         if (IS_CHERRYVIEW(dev_priv)) {
2899                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2900                         } else {
2901                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2902                                 *DP |= DP_LINK_TRAIN_PAT_2;
2903                         }
2904                         break;
2905                 }
2906         }
2907 }
2908
2909 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2910                                  const struct intel_crtc_state *old_crtc_state)
2911 {
2912         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2913
2914         /* enable with pattern 1 (as per spec) */
2915
2916         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2917
2918         /*
2919          * Magic for VLV/CHV. We _must_ first set up the register
2920          * without actually enabling the port, and then do another
2921          * write to enable the port. Otherwise link training will
2922          * fail when the power sequencer is freshly used for this port.
2923          */
2924         intel_dp->DP |= DP_PORT_EN;
2925         if (old_crtc_state->has_audio)
2926                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2927
2928         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2929         POSTING_READ(intel_dp->output_reg);
2930 }
2931
2932 static void intel_enable_dp(struct intel_encoder *encoder,
2933                             const struct intel_crtc_state *pipe_config,
2934                             const struct drm_connector_state *conn_state)
2935 {
2936         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2937         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2938         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2939         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2940         enum pipe pipe = crtc->pipe;
2941
2942         if (WARN_ON(dp_reg & DP_PORT_EN))
2943                 return;
2944
2945         pps_lock(intel_dp);
2946
2947         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2948                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2949
2950         intel_dp_enable_port(intel_dp, pipe_config);
2951
2952         edp_panel_vdd_on(intel_dp);
2953         edp_panel_on(intel_dp);
2954         edp_panel_vdd_off(intel_dp, true);
2955
2956         pps_unlock(intel_dp);
2957
2958         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2959                 unsigned int lane_mask = 0x0;
2960
2961                 if (IS_CHERRYVIEW(dev_priv))
2962                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2963
2964                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2965                                     lane_mask);
2966         }
2967
2968         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2969         intel_dp_start_link_train(intel_dp);
2970         intel_dp_stop_link_train(intel_dp);
2971
2972         if (pipe_config->has_audio) {
2973                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2974                                  pipe_name(pipe));
2975                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2976         }
2977 }
2978
2979 static void g4x_enable_dp(struct intel_encoder *encoder,
2980                           const struct intel_crtc_state *pipe_config,
2981                           const struct drm_connector_state *conn_state)
2982 {
2983         intel_enable_dp(encoder, pipe_config, conn_state);
2984         intel_edp_backlight_on(pipe_config, conn_state);
2985 }
2986
2987 static void vlv_enable_dp(struct intel_encoder *encoder,
2988                           const struct intel_crtc_state *pipe_config,
2989                           const struct drm_connector_state *conn_state)
2990 {
2991         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2992
2993         intel_edp_backlight_on(pipe_config, conn_state);
2994         intel_psr_enable(intel_dp, pipe_config);
2995 }
2996
2997 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2998                               const struct intel_crtc_state *pipe_config,
2999                               const struct drm_connector_state *conn_state)
3000 {
3001         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3002         enum port port = encoder->port;
3003
3004         intel_dp_prepare(encoder, pipe_config);
3005
3006         /* Only ilk+ has port A */
3007         if (port == PORT_A)
3008                 ironlake_edp_pll_on(intel_dp, pipe_config);
3009 }
3010
3011 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3012 {
3013         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3014         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3015         enum pipe pipe = intel_dp->pps_pipe;
3016         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3017
3018         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3019
3020         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3021                 return;
3022
3023         edp_panel_vdd_off_sync(intel_dp);
3024
3025         /*
3026          * VLV seems to get confused when multiple power seqeuencers
3027          * have the same port selected (even if only one has power/vdd
3028          * enabled). The failure manifests as vlv_wait_port_ready() failing
3029          * CHV on the other hand doesn't seem to mind having the same port
3030          * selected in multiple power seqeuencers, but let's clear the
3031          * port select always when logically disconnecting a power sequencer
3032          * from a port.
3033          */
3034         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3035                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3036         I915_WRITE(pp_on_reg, 0);
3037         POSTING_READ(pp_on_reg);
3038
3039         intel_dp->pps_pipe = INVALID_PIPE;
3040 }
3041
3042 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3043                                       enum pipe pipe)
3044 {
3045         struct intel_encoder *encoder;
3046
3047         lockdep_assert_held(&dev_priv->pps_mutex);
3048
3049         for_each_intel_encoder(&dev_priv->drm, encoder) {
3050                 struct intel_dp *intel_dp;
3051                 enum port port;
3052
3053                 if (encoder->type != INTEL_OUTPUT_DP &&
3054                     encoder->type != INTEL_OUTPUT_EDP)
3055                         continue;
3056
3057                 intel_dp = enc_to_intel_dp(&encoder->base);
3058                 port = dp_to_dig_port(intel_dp)->base.port;
3059
3060                 WARN(intel_dp->active_pipe == pipe,
3061                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3062                      pipe_name(pipe), port_name(port));
3063
3064                 if (intel_dp->pps_pipe != pipe)
3065                         continue;
3066
3067                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3068                               pipe_name(pipe), port_name(port));
3069
3070                 /* make sure vdd is off before we steal it */
3071                 vlv_detach_power_sequencer(intel_dp);
3072         }
3073 }
3074
3075 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3076                                            const struct intel_crtc_state *crtc_state)
3077 {
3078         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3079         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3080         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3081
3082         lockdep_assert_held(&dev_priv->pps_mutex);
3083
3084         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3085
3086         if (intel_dp->pps_pipe != INVALID_PIPE &&
3087             intel_dp->pps_pipe != crtc->pipe) {
3088                 /*
3089                  * If another power sequencer was being used on this
3090                  * port previously make sure to turn off vdd there while
3091                  * we still have control of it.
3092                  */
3093                 vlv_detach_power_sequencer(intel_dp);
3094         }
3095
3096         /*
3097          * We may be stealing the power
3098          * sequencer from another port.
3099          */
3100         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3101
3102         intel_dp->active_pipe = crtc->pipe;
3103
3104         if (!intel_dp_is_edp(intel_dp))
3105                 return;
3106
3107         /* now it's all ours */
3108         intel_dp->pps_pipe = crtc->pipe;
3109
3110         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3111                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3112
3113         /* init power sequencer on this pipe and port */
3114         intel_dp_init_panel_power_sequencer(intel_dp);
3115         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3116 }
3117
3118 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3119                               const struct intel_crtc_state *pipe_config,
3120                               const struct drm_connector_state *conn_state)
3121 {
3122         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3123
3124         intel_enable_dp(encoder, pipe_config, conn_state);
3125 }
3126
3127 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3128                                   const struct intel_crtc_state *pipe_config,
3129                                   const struct drm_connector_state *conn_state)
3130 {
3131         intel_dp_prepare(encoder, pipe_config);
3132
3133         vlv_phy_pre_pll_enable(encoder, pipe_config);
3134 }
3135
3136 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3137                               const struct intel_crtc_state *pipe_config,
3138                               const struct drm_connector_state *conn_state)
3139 {
3140         chv_phy_pre_encoder_enable(encoder, pipe_config);
3141
3142         intel_enable_dp(encoder, pipe_config, conn_state);
3143
3144         /* Second common lane will stay alive on its own now */
3145         chv_phy_release_cl2_override(encoder);
3146 }
3147
3148 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3149                                   const struct intel_crtc_state *pipe_config,
3150                                   const struct drm_connector_state *conn_state)
3151 {
3152         intel_dp_prepare(encoder, pipe_config);
3153
3154         chv_phy_pre_pll_enable(encoder, pipe_config);
3155 }
3156
3157 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3158                                     const struct intel_crtc_state *old_crtc_state,
3159                                     const struct drm_connector_state *old_conn_state)
3160 {
3161         chv_phy_post_pll_disable(encoder, old_crtc_state);
3162 }
3163
3164 /*
3165  * Fetch AUX CH registers 0x202 - 0x207 which contain
3166  * link status information
3167  */
3168 bool
3169 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3170 {
3171         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3172                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3173 }
3174
3175 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3176 {
3177         uint8_t psr_caps = 0;
3178
3179         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3180                 return false;
3181         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3182 }
3183
3184 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3185 {
3186         uint8_t dprx = 0;
3187
3188         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3189                               &dprx) != 1)
3190                 return false;
3191         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3192 }
3193
3194 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3195 {
3196         uint8_t alpm_caps = 0;
3197
3198         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3199                               &alpm_caps) != 1)
3200                 return false;
3201         return alpm_caps & DP_ALPM_CAP;
3202 }
3203
3204 /* These are source-specific values. */
3205 uint8_t
3206 intel_dp_voltage_max(struct intel_dp *intel_dp)
3207 {
3208         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3209         enum port port = dp_to_dig_port(intel_dp)->base.port;
3210
3211         if (INTEL_GEN(dev_priv) >= 9) {
3212                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3213                 return intel_ddi_dp_voltage_max(encoder);
3214         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3215                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3216         else if (IS_GEN7(dev_priv) && port == PORT_A)
3217                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3218         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3219                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3220         else
3221                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3222 }
3223
3224 uint8_t
3225 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3226 {
3227         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3228         enum port port = dp_to_dig_port(intel_dp)->base.port;
3229
3230         if (INTEL_GEN(dev_priv) >= 9) {
3231                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3233                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3234                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3235                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3236                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3237                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3238                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3239                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3240                 default:
3241                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3242                 }
3243         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3244                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3245                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3246                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3247                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3248                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3249                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3250                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3251                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3252                 default:
3253                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3254                 }
3255         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3256                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3257                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3258                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3259                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3260                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3261                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3262                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3263                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3264                 default:
3265                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3266                 }
3267         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3268                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3269                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3270                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3273                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3274                 default:
3275                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3276                 }
3277         } else {
3278                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3279                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3280                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3281                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3282                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3284                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3286                 default:
3287                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3288                 }
3289         }
3290 }
3291
3292 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3293 {
3294         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3295         unsigned long demph_reg_value, preemph_reg_value,
3296                 uniqtranscale_reg_value;
3297         uint8_t train_set = intel_dp->train_set[0];
3298
3299         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3300         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3301                 preemph_reg_value = 0x0004000;
3302                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3303                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3304                         demph_reg_value = 0x2B405555;
3305                         uniqtranscale_reg_value = 0x552AB83A;
3306                         break;
3307                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3308                         demph_reg_value = 0x2B404040;
3309                         uniqtranscale_reg_value = 0x5548B83A;
3310                         break;
3311                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3312                         demph_reg_value = 0x2B245555;
3313                         uniqtranscale_reg_value = 0x5560B83A;
3314                         break;
3315                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3316                         demph_reg_value = 0x2B405555;
3317                         uniqtranscale_reg_value = 0x5598DA3A;
3318                         break;
3319                 default:
3320                         return 0;
3321                 }
3322                 break;
3323         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3324                 preemph_reg_value = 0x0002000;
3325                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3326                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3327                         demph_reg_value = 0x2B404040;
3328                         uniqtranscale_reg_value = 0x5552B83A;
3329                         break;
3330                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3331                         demph_reg_value = 0x2B404848;
3332                         uniqtranscale_reg_value = 0x5580B83A;
3333                         break;
3334                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3335                         demph_reg_value = 0x2B404040;
3336                         uniqtranscale_reg_value = 0x55ADDA3A;
3337                         break;
3338                 default:
3339                         return 0;
3340                 }
3341                 break;
3342         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3343                 preemph_reg_value = 0x0000000;
3344                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3345                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3346                         demph_reg_value = 0x2B305555;
3347                         uniqtranscale_reg_value = 0x5570B83A;
3348                         break;
3349                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3350                         demph_reg_value = 0x2B2B4040;
3351                         uniqtranscale_reg_value = 0x55ADDA3A;
3352                         break;
3353                 default:
3354                         return 0;
3355                 }
3356                 break;
3357         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3358                 preemph_reg_value = 0x0006000;
3359                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3360                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3361                         demph_reg_value = 0x1B405555;
3362                         uniqtranscale_reg_value = 0x55ADDA3A;
3363                         break;
3364                 default:
3365                         return 0;
3366                 }
3367                 break;
3368         default:
3369                 return 0;
3370         }
3371
3372         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3373                                  uniqtranscale_reg_value, 0);
3374
3375         return 0;
3376 }
3377
3378 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3379 {
3380         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3381         u32 deemph_reg_value, margin_reg_value;
3382         bool uniq_trans_scale = false;
3383         uint8_t train_set = intel_dp->train_set[0];
3384
3385         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3386         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3387                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3388                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3389                         deemph_reg_value = 128;
3390                         margin_reg_value = 52;
3391                         break;
3392                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3393                         deemph_reg_value = 128;
3394                         margin_reg_value = 77;
3395                         break;
3396                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3397                         deemph_reg_value = 128;
3398                         margin_reg_value = 102;
3399                         break;
3400                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3401                         deemph_reg_value = 128;
3402                         margin_reg_value = 154;
3403                         uniq_trans_scale = true;
3404                         break;
3405                 default:
3406                         return 0;
3407                 }
3408                 break;
3409         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3410                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3411                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3412                         deemph_reg_value = 85;
3413                         margin_reg_value = 78;
3414                         break;
3415                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3416                         deemph_reg_value = 85;
3417                         margin_reg_value = 116;
3418                         break;
3419                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3420                         deemph_reg_value = 85;
3421                         margin_reg_value = 154;
3422                         break;
3423                 default:
3424                         return 0;
3425                 }
3426                 break;
3427         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3428                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3429                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3430                         deemph_reg_value = 64;
3431                         margin_reg_value = 104;
3432                         break;
3433                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3434                         deemph_reg_value = 64;
3435                         margin_reg_value = 154;
3436                         break;
3437                 default:
3438                         return 0;
3439                 }
3440                 break;
3441         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3442                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3443                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3444                         deemph_reg_value = 43;
3445                         margin_reg_value = 154;
3446                         break;
3447                 default:
3448                         return 0;
3449                 }
3450                 break;
3451         default:
3452                 return 0;
3453         }
3454
3455         chv_set_phy_signal_level(encoder, deemph_reg_value,
3456                                  margin_reg_value, uniq_trans_scale);
3457
3458         return 0;
3459 }
3460
3461 static uint32_t
3462 gen4_signal_levels(uint8_t train_set)
3463 {
3464         uint32_t        signal_levels = 0;
3465
3466         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3467         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3468         default:
3469                 signal_levels |= DP_VOLTAGE_0_4;
3470                 break;
3471         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3472                 signal_levels |= DP_VOLTAGE_0_6;
3473                 break;
3474         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3475                 signal_levels |= DP_VOLTAGE_0_8;
3476                 break;
3477         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3478                 signal_levels |= DP_VOLTAGE_1_2;
3479                 break;
3480         }
3481         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3482         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3483         default:
3484                 signal_levels |= DP_PRE_EMPHASIS_0;
3485                 break;
3486         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3487                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3488                 break;
3489         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3490                 signal_levels |= DP_PRE_EMPHASIS_6;
3491                 break;
3492         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3493                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3494                 break;
3495         }
3496         return signal_levels;
3497 }
3498
3499 /* Gen6's DP voltage swing and pre-emphasis control */
3500 static uint32_t
3501 gen6_edp_signal_levels(uint8_t train_set)
3502 {
3503         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3504                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3505         switch (signal_levels) {
3506         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3508                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3509         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3510                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3511         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3512         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3513                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3514         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3515         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3516                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3517         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3518         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3519                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3520         default:
3521                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3522                               "0x%x\n", signal_levels);
3523                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3524         }
3525 }
3526
3527 /* Gen7's DP voltage swing and pre-emphasis control */
3528 static uint32_t
3529 gen7_edp_signal_levels(uint8_t train_set)
3530 {
3531         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3532                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3533         switch (signal_levels) {
3534         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3535                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3536         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3537                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3538         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3539                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3540
3541         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3542                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3543         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3544                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3545
3546         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3547                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3548         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3549                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3550
3551         default:
3552                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3553                               "0x%x\n", signal_levels);
3554                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3555         }
3556 }
3557
3558 void
3559 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3560 {
3561         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3562         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3563         enum port port = intel_dig_port->base.port;
3564         uint32_t signal_levels, mask = 0;
3565         uint8_t train_set = intel_dp->train_set[0];
3566
3567         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3568                 signal_levels = bxt_signal_levels(intel_dp);
3569         } else if (HAS_DDI(dev_priv)) {
3570                 signal_levels = ddi_signal_levels(intel_dp);
3571                 mask = DDI_BUF_EMP_MASK;
3572         } else if (IS_CHERRYVIEW(dev_priv)) {
3573                 signal_levels = chv_signal_levels(intel_dp);
3574         } else if (IS_VALLEYVIEW(dev_priv)) {
3575                 signal_levels = vlv_signal_levels(intel_dp);
3576         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3577                 signal_levels = gen7_edp_signal_levels(train_set);
3578                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3579         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3580                 signal_levels = gen6_edp_signal_levels(train_set);
3581                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3582         } else {
3583                 signal_levels = gen4_signal_levels(train_set);
3584                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3585         }
3586
3587         if (mask)
3588                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3589
3590         DRM_DEBUG_KMS("Using vswing level %d\n",
3591                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3592         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3593                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3594                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3595
3596         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3597
3598         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3599         POSTING_READ(intel_dp->output_reg);
3600 }
3601
3602 void
3603 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3604                                        uint8_t dp_train_pat)
3605 {
3606         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3607         struct drm_i915_private *dev_priv =
3608                 to_i915(intel_dig_port->base.base.dev);
3609
3610         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3611
3612         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3613         POSTING_READ(intel_dp->output_reg);
3614 }
3615
3616 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3617 {
3618         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3619         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3620         enum port port = intel_dig_port->base.port;
3621         uint32_t val;
3622
3623         if (!HAS_DDI(dev_priv))
3624                 return;
3625
3626         val = I915_READ(DP_TP_CTL(port));
3627         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3628         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3629         I915_WRITE(DP_TP_CTL(port), val);
3630
3631         /*
3632          * On PORT_A we can have only eDP in SST mode. There the only reason
3633          * we need to set idle transmission mode is to work around a HW issue
3634          * where we enable the pipe while not in idle link-training mode.
3635          * In this case there is requirement to wait for a minimum number of
3636          * idle patterns to be sent.
3637          */
3638         if (port == PORT_A)
3639                 return;
3640
3641         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3642                                     DP_TP_STATUS_IDLE_DONE,
3643                                     DP_TP_STATUS_IDLE_DONE,
3644                                     1))
3645                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3646 }
3647
3648 static void
3649 intel_dp_link_down(struct intel_encoder *encoder,
3650                    const struct intel_crtc_state *old_crtc_state)
3651 {
3652         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3653         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3654         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3655         enum port port = encoder->port;
3656         uint32_t DP = intel_dp->DP;
3657
3658         if (WARN_ON(HAS_DDI(dev_priv)))
3659                 return;
3660
3661         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3662                 return;
3663
3664         DRM_DEBUG_KMS("\n");
3665
3666         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3667             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3668                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3669                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3670         } else {
3671                 if (IS_CHERRYVIEW(dev_priv))
3672                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3673                 else
3674                         DP &= ~DP_LINK_TRAIN_MASK;
3675                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3676         }
3677         I915_WRITE(intel_dp->output_reg, DP);
3678         POSTING_READ(intel_dp->output_reg);
3679
3680         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3681         I915_WRITE(intel_dp->output_reg, DP);
3682         POSTING_READ(intel_dp->output_reg);
3683
3684         /*
3685          * HW workaround for IBX, we need to move the port
3686          * to transcoder A after disabling it to allow the
3687          * matching HDMI port to be enabled on transcoder A.
3688          */
3689         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3690                 /*
3691                  * We get CPU/PCH FIFO underruns on the other pipe when
3692                  * doing the workaround. Sweep them under the rug.
3693                  */
3694                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3695                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3696
3697                 /* always enable with pattern 1 (as per spec) */
3698                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3699                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3700                 I915_WRITE(intel_dp->output_reg, DP);
3701                 POSTING_READ(intel_dp->output_reg);
3702
3703                 DP &= ~DP_PORT_EN;
3704                 I915_WRITE(intel_dp->output_reg, DP);
3705                 POSTING_READ(intel_dp->output_reg);
3706
3707                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3708                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3709                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3710         }
3711
3712         msleep(intel_dp->panel_power_down_delay);
3713
3714         intel_dp->DP = DP;
3715
3716         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3717                 pps_lock(intel_dp);
3718                 intel_dp->active_pipe = INVALID_PIPE;
3719                 pps_unlock(intel_dp);
3720         }
3721 }
3722
3723 bool
3724 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3725 {
3726         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3727                              sizeof(intel_dp->dpcd)) < 0)
3728                 return false; /* aux transfer failed */
3729
3730         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3731
3732         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3733 }
3734
3735 static bool
3736 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3737 {
3738         struct drm_i915_private *dev_priv =
3739                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3740
3741         /* this function is meant to be called only once */
3742         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3743
3744         if (!intel_dp_read_dpcd(intel_dp))
3745                 return false;
3746
3747         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3748                          drm_dp_is_branch(intel_dp->dpcd));
3749
3750         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3751                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3752                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3753
3754         /* Check if the panel supports PSR */
3755         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3756                          intel_dp->psr_dpcd,
3757                          sizeof(intel_dp->psr_dpcd));
3758         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3759                 dev_priv->psr.sink_support = true;
3760                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3761         }
3762
3763         if (INTEL_GEN(dev_priv) >= 9 &&
3764             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3765                 uint8_t frame_sync_cap;
3766
3767                 dev_priv->psr.sink_support = true;
3768                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3769                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3770                                       &frame_sync_cap) != 1)
3771                         frame_sync_cap = 0;
3772                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3773                 /* PSR2 needs frame sync as well */
3774                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3775                 DRM_DEBUG_KMS("PSR2 %s on sink",
3776                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3777
3778                 if (dev_priv->psr.psr2_support) {
3779                         dev_priv->psr.y_cord_support =
3780                                 intel_dp_get_y_cord_status(intel_dp);
3781                         dev_priv->psr.colorimetry_support =
3782                                 intel_dp_get_colorimetry_status(intel_dp);
3783                         dev_priv->psr.alpm =
3784                                 intel_dp_get_alpm_status(intel_dp);
3785                 }
3786
3787         }
3788
3789         /*
3790          * Read the eDP display control registers.
3791          *
3792          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3793          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3794          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3795          * method). The display control registers should read zero if they're
3796          * not supported anyway.
3797          */
3798         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3799                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3800                              sizeof(intel_dp->edp_dpcd))
3801                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3802                               intel_dp->edp_dpcd);
3803
3804         /* Read the eDP 1.4+ supported link rates. */
3805         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3806                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3807                 int i;
3808
3809                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3810                                 sink_rates, sizeof(sink_rates));
3811
3812                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3813                         int val = le16_to_cpu(sink_rates[i]);
3814
3815                         if (val == 0)
3816                                 break;
3817
3818                         /* Value read multiplied by 200kHz gives the per-lane
3819                          * link rate in kHz. The source rates are, however,
3820                          * stored in terms of LS_Clk kHz. The full conversion
3821                          * back to symbols is
3822                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3823                          */
3824                         intel_dp->sink_rates[i] = (val * 200) / 10;
3825                 }
3826                 intel_dp->num_sink_rates = i;
3827         }
3828
3829         /*
3830          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3831          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3832          */
3833         if (intel_dp->num_sink_rates)
3834                 intel_dp->use_rate_select = true;
3835         else
3836                 intel_dp_set_sink_rates(intel_dp);
3837
3838         intel_dp_set_common_rates(intel_dp);
3839
3840         return true;
3841 }
3842
3843
3844 static bool
3845 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3846 {
3847         u8 sink_count;
3848
3849         if (!intel_dp_read_dpcd(intel_dp))
3850                 return false;
3851
3852         /* Don't clobber cached eDP rates. */
3853         if (!intel_dp_is_edp(intel_dp)) {
3854                 intel_dp_set_sink_rates(intel_dp);
3855                 intel_dp_set_common_rates(intel_dp);
3856         }
3857
3858         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3859                 return false;
3860
3861         /*
3862          * Sink count can change between short pulse hpd hence
3863          * a member variable in intel_dp will track any changes
3864          * between short pulse interrupts.
3865          */
3866         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3867
3868         /*
3869          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3870          * a dongle is present but no display. Unless we require to know
3871          * if a dongle is present or not, we don't need to update
3872          * downstream port information. So, an early return here saves
3873          * time from performing other operations which are not required.
3874          */
3875         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3876                 return false;
3877
3878         if (!drm_dp_is_branch(intel_dp->dpcd))
3879                 return true; /* native DP sink */
3880
3881         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3882                 return true; /* no per-port downstream info */
3883
3884         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3885                              intel_dp->downstream_ports,
3886                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3887                 return false; /* downstream port status fetch failed */
3888
3889         return true;
3890 }
3891
3892 static bool
3893 intel_dp_can_mst(struct intel_dp *intel_dp)
3894 {
3895         u8 mstm_cap;
3896
3897         if (!i915_modparams.enable_dp_mst)
3898                 return false;
3899
3900         if (!intel_dp->can_mst)
3901                 return false;
3902
3903         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3904                 return false;
3905
3906         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3907                 return false;
3908
3909         return mstm_cap & DP_MST_CAP;
3910 }
3911
3912 static void
3913 intel_dp_configure_mst(struct intel_dp *intel_dp)
3914 {
3915         if (!i915_modparams.enable_dp_mst)
3916                 return;
3917
3918         if (!intel_dp->can_mst)
3919                 return;
3920
3921         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3922
3923         if (intel_dp->is_mst)
3924                 DRM_DEBUG_KMS("Sink is MST capable\n");
3925         else
3926                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3927
3928         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3929                                         intel_dp->is_mst);
3930 }
3931
3932 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3933                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3934 {
3935         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3936         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3938         u8 buf;
3939         int ret = 0;
3940         int count = 0;
3941         int attempts = 10;
3942
3943         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3944                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3945                 ret = -EIO;
3946                 goto out;
3947         }
3948
3949         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3950                                buf & ~DP_TEST_SINK_START) < 0) {
3951                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3952                 ret = -EIO;
3953                 goto out;
3954         }
3955
3956         do {
3957                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3958
3959                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3960                                       DP_TEST_SINK_MISC, &buf) < 0) {
3961                         ret = -EIO;
3962                         goto out;
3963                 }
3964                 count = buf & DP_TEST_COUNT_MASK;
3965         } while (--attempts && count);
3966
3967         if (attempts == 0) {
3968                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3969                 ret = -ETIMEDOUT;
3970         }
3971
3972  out:
3973         if (disable_wa)
3974                 hsw_enable_ips(crtc_state);
3975         return ret;
3976 }
3977
3978 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3979                                    struct intel_crtc_state *crtc_state)
3980 {
3981         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3982         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3984         u8 buf;
3985         int ret;
3986
3987         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3988                 return -EIO;
3989
3990         if (!(buf & DP_TEST_CRC_SUPPORTED))
3991                 return -ENOTTY;
3992
3993         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3994                 return -EIO;
3995
3996         if (buf & DP_TEST_SINK_START) {
3997                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3998                 if (ret)
3999                         return ret;
4000         }
4001
4002         hsw_disable_ips(crtc_state);
4003
4004         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4005                                buf | DP_TEST_SINK_START) < 0) {
4006                 hsw_enable_ips(crtc_state);
4007                 return -EIO;
4008         }
4009
4010         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
4011         return 0;
4012 }
4013
4014 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
4015 {
4016         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4017         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4019         u8 buf;
4020         int count, ret;
4021         int attempts = 6;
4022
4023         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
4024         if (ret)
4025                 return ret;
4026
4027         do {
4028                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
4029
4030                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4031                                       DP_TEST_SINK_MISC, &buf) < 0) {
4032                         ret = -EIO;
4033                         goto stop;
4034                 }
4035                 count = buf & DP_TEST_COUNT_MASK;
4036
4037         } while (--attempts && count == 0);
4038
4039         if (attempts == 0) {
4040                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4041                 ret = -ETIMEDOUT;
4042                 goto stop;
4043         }
4044
4045         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4046                 ret = -EIO;
4047                 goto stop;
4048         }
4049
4050 stop:
4051         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
4052         return ret;
4053 }
4054
4055 static bool
4056 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4057 {
4058         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
4059                                  sink_irq_vector) == 1;
4060 }
4061
4062 static bool
4063 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4064 {
4065         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4066                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4067                 DP_DPRX_ESI_LEN;
4068 }
4069
4070 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4071 {
4072         int status = 0;
4073         int test_link_rate;
4074         uint8_t test_lane_count, test_link_bw;
4075         /* (DP CTS 1.2)
4076          * 4.3.1.11
4077          */
4078         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4079         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4080                                    &test_lane_count);
4081
4082         if (status <= 0) {
4083                 DRM_DEBUG_KMS("Lane count read failed\n");
4084                 return DP_TEST_NAK;
4085         }
4086         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4087
4088         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4089                                    &test_link_bw);
4090         if (status <= 0) {
4091                 DRM_DEBUG_KMS("Link Rate read failed\n");
4092                 return DP_TEST_NAK;
4093         }
4094         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4095
4096         /* Validate the requested link rate and lane count */
4097         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4098                                         test_lane_count))
4099                 return DP_TEST_NAK;
4100
4101         intel_dp->compliance.test_lane_count = test_lane_count;
4102         intel_dp->compliance.test_link_rate = test_link_rate;
4103
4104         return DP_TEST_ACK;
4105 }
4106
4107 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4108 {
4109         uint8_t test_pattern;
4110         uint8_t test_misc;
4111         __be16 h_width, v_height;
4112         int status = 0;
4113
4114         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4115         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4116                                    &test_pattern);
4117         if (status <= 0) {
4118                 DRM_DEBUG_KMS("Test pattern read failed\n");
4119                 return DP_TEST_NAK;
4120         }
4121         if (test_pattern != DP_COLOR_RAMP)
4122                 return DP_TEST_NAK;
4123
4124         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4125                                   &h_width, 2);
4126         if (status <= 0) {
4127                 DRM_DEBUG_KMS("H Width read failed\n");
4128                 return DP_TEST_NAK;
4129         }
4130
4131         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4132                                   &v_height, 2);
4133         if (status <= 0) {
4134                 DRM_DEBUG_KMS("V Height read failed\n");
4135                 return DP_TEST_NAK;
4136         }
4137
4138         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4139                                    &test_misc);
4140         if (status <= 0) {
4141                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4142                 return DP_TEST_NAK;
4143         }
4144         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4145                 return DP_TEST_NAK;
4146         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4147                 return DP_TEST_NAK;
4148         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4149         case DP_TEST_BIT_DEPTH_6:
4150                 intel_dp->compliance.test_data.bpc = 6;
4151                 break;
4152         case DP_TEST_BIT_DEPTH_8:
4153                 intel_dp->compliance.test_data.bpc = 8;
4154                 break;
4155         default:
4156                 return DP_TEST_NAK;
4157         }
4158
4159         intel_dp->compliance.test_data.video_pattern = test_pattern;
4160         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4161         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4162         /* Set test active flag here so userspace doesn't interrupt things */
4163         intel_dp->compliance.test_active = 1;
4164
4165         return DP_TEST_ACK;
4166 }
4167
4168 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4169 {
4170         uint8_t test_result = DP_TEST_ACK;
4171         struct intel_connector *intel_connector = intel_dp->attached_connector;
4172         struct drm_connector *connector = &intel_connector->base;
4173
4174         if (intel_connector->detect_edid == NULL ||
4175             connector->edid_corrupt ||
4176             intel_dp->aux.i2c_defer_count > 6) {
4177                 /* Check EDID read for NACKs, DEFERs and corruption
4178                  * (DP CTS 1.2 Core r1.1)
4179                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4180                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4181                  *    4.2.2.6 : EDID corruption detected
4182                  * Use failsafe mode for all cases
4183                  */
4184                 if (intel_dp->aux.i2c_nack_count > 0 ||
4185                         intel_dp->aux.i2c_defer_count > 0)
4186                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4187                                       intel_dp->aux.i2c_nack_count,
4188                                       intel_dp->aux.i2c_defer_count);
4189                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4190         } else {
4191                 struct edid *block = intel_connector->detect_edid;
4192
4193                 /* We have to write the checksum
4194                  * of the last block read
4195                  */
4196                 block += intel_connector->detect_edid->extensions;
4197
4198                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4199                                        block->checksum) <= 0)
4200                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4201
4202                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4203                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4204         }
4205
4206         /* Set test active flag here so userspace doesn't interrupt things */
4207         intel_dp->compliance.test_active = 1;
4208
4209         return test_result;
4210 }
4211
4212 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4213 {
4214         uint8_t test_result = DP_TEST_NAK;
4215         return test_result;
4216 }
4217
4218 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4219 {
4220         uint8_t response = DP_TEST_NAK;
4221         uint8_t request = 0;
4222         int status;
4223
4224         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4225         if (status <= 0) {
4226                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4227                 goto update_status;
4228         }
4229
4230         switch (request) {
4231         case DP_TEST_LINK_TRAINING:
4232                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4233                 response = intel_dp_autotest_link_training(intel_dp);
4234                 break;
4235         case DP_TEST_LINK_VIDEO_PATTERN:
4236                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4237                 response = intel_dp_autotest_video_pattern(intel_dp);
4238                 break;
4239         case DP_TEST_LINK_EDID_READ:
4240                 DRM_DEBUG_KMS("EDID test requested\n");
4241                 response = intel_dp_autotest_edid(intel_dp);
4242                 break;
4243         case DP_TEST_LINK_PHY_TEST_PATTERN:
4244                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4245                 response = intel_dp_autotest_phy_pattern(intel_dp);
4246                 break;
4247         default:
4248                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4249                 break;
4250         }
4251
4252         if (response & DP_TEST_ACK)
4253                 intel_dp->compliance.test_type = request;
4254
4255 update_status:
4256         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4257         if (status <= 0)
4258                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4259 }
4260
4261 static int
4262 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4263 {
4264         bool bret;
4265
4266         if (intel_dp->is_mst) {
4267                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4268                 int ret = 0;
4269                 int retry;
4270                 bool handled;
4271                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4272 go_again:
4273                 if (bret == true) {
4274
4275                         /* check link status - esi[10] = 0x200c */
4276                         if (intel_dp->active_mst_links &&
4277                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4278                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4279                                 intel_dp_start_link_train(intel_dp);
4280                                 intel_dp_stop_link_train(intel_dp);
4281                         }
4282
4283                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4284                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4285
4286                         if (handled) {
4287                                 for (retry = 0; retry < 3; retry++) {
4288                                         int wret;
4289                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4290                                                                  DP_SINK_COUNT_ESI+1,
4291                                                                  &esi[1], 3);
4292                                         if (wret == 3) {
4293                                                 break;
4294                                         }
4295                                 }
4296
4297                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4298                                 if (bret == true) {
4299                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4300                                         goto go_again;
4301                                 }
4302                         } else
4303                                 ret = 0;
4304
4305                         return ret;
4306                 } else {
4307                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4308                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4309                         intel_dp->is_mst = false;
4310                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4311                         /* send a hotplug event */
4312                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4313                 }
4314         }
4315         return -EINVAL;
4316 }
4317
4318 static void
4319 intel_dp_retrain_link(struct intel_dp *intel_dp)
4320 {
4321         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4322         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4323         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4324
4325         /* Suppress underruns caused by re-training */
4326         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4327         if (crtc->config->has_pch_encoder)
4328                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4329                                                       intel_crtc_pch_transcoder(crtc), false);
4330
4331         intel_dp_start_link_train(intel_dp);
4332         intel_dp_stop_link_train(intel_dp);
4333
4334         /* Keep underrun reporting disabled until things are stable */
4335         intel_wait_for_vblank(dev_priv, crtc->pipe);
4336
4337         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4338         if (crtc->config->has_pch_encoder)
4339                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4340                                                       intel_crtc_pch_transcoder(crtc), true);
4341 }
4342
4343 static void
4344 intel_dp_check_link_status(struct intel_dp *intel_dp)
4345 {
4346         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4347         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4348         struct drm_connector_state *conn_state =
4349                 intel_dp->attached_connector->base.state;
4350         u8 link_status[DP_LINK_STATUS_SIZE];
4351
4352         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4353
4354         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4355                 DRM_ERROR("Failed to get link status\n");
4356                 return;
4357         }
4358
4359         if (!conn_state->crtc)
4360                 return;
4361
4362         WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex));
4363
4364         if (!conn_state->crtc->state->active)
4365                 return;
4366
4367         if (conn_state->commit &&
4368             !try_wait_for_completion(&conn_state->commit->hw_done))
4369                 return;
4370
4371         /*
4372          * Validate the cached values of intel_dp->link_rate and
4373          * intel_dp->lane_count before attempting to retrain.
4374          */
4375         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4376                                         intel_dp->lane_count))
4377                 return;
4378
4379         /* Retrain if Channel EQ or CR not ok */
4380         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4381                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4382                               intel_encoder->base.name);
4383
4384                 intel_dp_retrain_link(intel_dp);
4385         }
4386 }
4387
4388 /*
4389  * According to DP spec
4390  * 5.1.2:
4391  *  1. Read DPCD
4392  *  2. Configure link according to Receiver Capabilities
4393  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4394  *  4. Check link status on receipt of hot-plug interrupt
4395  *
4396  * intel_dp_short_pulse -  handles short pulse interrupts
4397  * when full detection is not required.
4398  * Returns %true if short pulse is handled and full detection
4399  * is NOT required and %false otherwise.
4400  */
4401 static bool
4402 intel_dp_short_pulse(struct intel_dp *intel_dp)
4403 {
4404         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4405         u8 sink_irq_vector = 0;
4406         u8 old_sink_count = intel_dp->sink_count;
4407         bool ret;
4408
4409         /*
4410          * Clearing compliance test variables to allow capturing
4411          * of values for next automated test request.
4412          */
4413         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4414
4415         /*
4416          * Now read the DPCD to see if it's actually running
4417          * If the current value of sink count doesn't match with
4418          * the value that was stored earlier or dpcd read failed
4419          * we need to do full detection
4420          */
4421         ret = intel_dp_get_dpcd(intel_dp);
4422
4423         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4424                 /* No need to proceed if we are going to do full detect */
4425                 return false;
4426         }
4427
4428         /* Try to read the source of the interrupt */
4429         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4430             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4431             sink_irq_vector != 0) {
4432                 /* Clear interrupt source */
4433                 drm_dp_dpcd_writeb(&intel_dp->aux,
4434                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4435                                    sink_irq_vector);
4436
4437                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4438                         intel_dp_handle_test_request(intel_dp);
4439                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4440                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4441         }
4442
4443         intel_dp_check_link_status(intel_dp);
4444
4445         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4446                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4447                 /* Send a Hotplug Uevent to userspace to start modeset */
4448                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4449         }
4450
4451         return true;
4452 }
4453
4454 /* XXX this is probably wrong for multiple downstream ports */
4455 static enum drm_connector_status
4456 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4457 {
4458         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4459         uint8_t *dpcd = intel_dp->dpcd;
4460         uint8_t type;
4461
4462         if (lspcon->active)
4463                 lspcon_resume(lspcon);
4464
4465         if (!intel_dp_get_dpcd(intel_dp))
4466                 return connector_status_disconnected;
4467
4468         if (intel_dp_is_edp(intel_dp))
4469                 return connector_status_connected;
4470
4471         /* if there's no downstream port, we're done */
4472         if (!drm_dp_is_branch(dpcd))
4473                 return connector_status_connected;
4474
4475         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4476         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4477             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4478
4479                 return intel_dp->sink_count ?
4480                 connector_status_connected : connector_status_disconnected;
4481         }
4482
4483         if (intel_dp_can_mst(intel_dp))
4484                 return connector_status_connected;
4485
4486         /* If no HPD, poke DDC gently */
4487         if (drm_probe_ddc(&intel_dp->aux.ddc))
4488                 return connector_status_connected;
4489
4490         /* Well we tried, say unknown for unreliable port types */
4491         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4492                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4493                 if (type == DP_DS_PORT_TYPE_VGA ||
4494                     type == DP_DS_PORT_TYPE_NON_EDID)
4495                         return connector_status_unknown;
4496         } else {
4497                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4498                         DP_DWN_STRM_PORT_TYPE_MASK;
4499                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4500                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4501                         return connector_status_unknown;
4502         }
4503
4504         /* Anything else is out of spec, warn and ignore */
4505         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4506         return connector_status_disconnected;
4507 }
4508
4509 static enum drm_connector_status
4510 edp_detect(struct intel_dp *intel_dp)
4511 {
4512         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4513         enum drm_connector_status status;
4514
4515         status = intel_panel_detect(dev_priv);
4516         if (status == connector_status_unknown)
4517                 status = connector_status_connected;
4518
4519         return status;
4520 }
4521
4522 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4523 {
4524         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4525         u32 bit;
4526
4527         switch (encoder->hpd_pin) {
4528         case HPD_PORT_B:
4529                 bit = SDE_PORTB_HOTPLUG;
4530                 break;
4531         case HPD_PORT_C:
4532                 bit = SDE_PORTC_HOTPLUG;
4533                 break;
4534         case HPD_PORT_D:
4535                 bit = SDE_PORTD_HOTPLUG;
4536                 break;
4537         default:
4538                 MISSING_CASE(encoder->hpd_pin);
4539                 return false;
4540         }
4541
4542         return I915_READ(SDEISR) & bit;
4543 }
4544
4545 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4546 {
4547         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4548         u32 bit;
4549
4550         switch (encoder->hpd_pin) {
4551         case HPD_PORT_B:
4552                 bit = SDE_PORTB_HOTPLUG_CPT;
4553                 break;
4554         case HPD_PORT_C:
4555                 bit = SDE_PORTC_HOTPLUG_CPT;
4556                 break;
4557         case HPD_PORT_D:
4558                 bit = SDE_PORTD_HOTPLUG_CPT;
4559                 break;
4560         default:
4561                 MISSING_CASE(encoder->hpd_pin);
4562                 return false;
4563         }
4564
4565         return I915_READ(SDEISR) & bit;
4566 }
4567
4568 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4569 {
4570         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4571         u32 bit;
4572
4573         switch (encoder->hpd_pin) {
4574         case HPD_PORT_A:
4575                 bit = SDE_PORTA_HOTPLUG_SPT;
4576                 break;
4577         case HPD_PORT_E:
4578                 bit = SDE_PORTE_HOTPLUG_SPT;
4579                 break;
4580         default:
4581                 return cpt_digital_port_connected(encoder);
4582         }
4583
4584         return I915_READ(SDEISR) & bit;
4585 }
4586
4587 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4588 {
4589         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4590         u32 bit;
4591
4592         switch (encoder->hpd_pin) {
4593         case HPD_PORT_B:
4594                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4595                 break;
4596         case HPD_PORT_C:
4597                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4598                 break;
4599         case HPD_PORT_D:
4600                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4601                 break;
4602         default:
4603                 MISSING_CASE(encoder->hpd_pin);
4604                 return false;
4605         }
4606
4607         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4608 }
4609
4610 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4611 {
4612         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4613         u32 bit;
4614
4615         switch (encoder->hpd_pin) {
4616         case HPD_PORT_B:
4617                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4618                 break;
4619         case HPD_PORT_C:
4620                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4621                 break;
4622         case HPD_PORT_D:
4623                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4624                 break;
4625         default:
4626                 MISSING_CASE(encoder->hpd_pin);
4627                 return false;
4628         }
4629
4630         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4631 }
4632
4633 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4634 {
4635         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4636
4637         if (encoder->hpd_pin == HPD_PORT_A)
4638                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4639         else
4640                 return ibx_digital_port_connected(encoder);
4641 }
4642
4643 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4644 {
4645         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4646
4647         if (encoder->hpd_pin == HPD_PORT_A)
4648                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4649         else
4650                 return cpt_digital_port_connected(encoder);
4651 }
4652
4653 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4654 {
4655         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4656
4657         if (encoder->hpd_pin == HPD_PORT_A)
4658                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4659         else
4660                 return cpt_digital_port_connected(encoder);
4661 }
4662
4663 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4664 {
4665         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4666
4667         if (encoder->hpd_pin == HPD_PORT_A)
4668                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4669         else
4670                 return cpt_digital_port_connected(encoder);
4671 }
4672
4673 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4674 {
4675         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4676         u32 bit;
4677
4678         switch (encoder->hpd_pin) {
4679         case HPD_PORT_A:
4680                 bit = BXT_DE_PORT_HP_DDIA;
4681                 break;
4682         case HPD_PORT_B:
4683                 bit = BXT_DE_PORT_HP_DDIB;
4684                 break;
4685         case HPD_PORT_C:
4686                 bit = BXT_DE_PORT_HP_DDIC;
4687                 break;
4688         default:
4689                 MISSING_CASE(encoder->hpd_pin);
4690                 return false;
4691         }
4692
4693         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4694 }
4695
4696 /*
4697  * intel_digital_port_connected - is the specified port connected?
4698  * @encoder: intel_encoder
4699  *
4700  * Return %true if port is connected, %false otherwise.
4701  */
4702 bool intel_digital_port_connected(struct intel_encoder *encoder)
4703 {
4704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4705
4706         if (HAS_GMCH_DISPLAY(dev_priv)) {
4707                 if (IS_GM45(dev_priv))
4708                         return gm45_digital_port_connected(encoder);
4709                 else
4710                         return g4x_digital_port_connected(encoder);
4711         }
4712
4713         if (IS_GEN5(dev_priv))
4714                 return ilk_digital_port_connected(encoder);
4715         else if (IS_GEN6(dev_priv))
4716                 return snb_digital_port_connected(encoder);
4717         else if (IS_GEN7(dev_priv))
4718                 return ivb_digital_port_connected(encoder);
4719         else if (IS_GEN8(dev_priv))
4720                 return bdw_digital_port_connected(encoder);
4721         else if (IS_GEN9_LP(dev_priv))
4722                 return bxt_digital_port_connected(encoder);
4723         else
4724                 return spt_digital_port_connected(encoder);
4725 }
4726
4727 static struct edid *
4728 intel_dp_get_edid(struct intel_dp *intel_dp)
4729 {
4730         struct intel_connector *intel_connector = intel_dp->attached_connector;
4731
4732         /* use cached edid if we have one */
4733         if (intel_connector->edid) {
4734                 /* invalid edid */
4735                 if (IS_ERR(intel_connector->edid))
4736                         return NULL;
4737
4738                 return drm_edid_duplicate(intel_connector->edid);
4739         } else
4740                 return drm_get_edid(&intel_connector->base,
4741                                     &intel_dp->aux.ddc);
4742 }
4743
4744 static void
4745 intel_dp_set_edid(struct intel_dp *intel_dp)
4746 {
4747         struct intel_connector *intel_connector = intel_dp->attached_connector;
4748         struct edid *edid;
4749
4750         intel_dp_unset_edid(intel_dp);
4751         edid = intel_dp_get_edid(intel_dp);
4752         intel_connector->detect_edid = edid;
4753
4754         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4755 }
4756
4757 static void
4758 intel_dp_unset_edid(struct intel_dp *intel_dp)
4759 {
4760         struct intel_connector *intel_connector = intel_dp->attached_connector;
4761
4762         kfree(intel_connector->detect_edid);
4763         intel_connector->detect_edid = NULL;
4764
4765         intel_dp->has_audio = false;
4766 }
4767
4768 static int
4769 intel_dp_long_pulse(struct intel_connector *connector)
4770 {
4771         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4772         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4773         enum drm_connector_status status;
4774         u8 sink_irq_vector = 0;
4775
4776         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4777
4778         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4779
4780         /* Can't disconnect eDP, but you can close the lid... */
4781         if (intel_dp_is_edp(intel_dp))
4782                 status = edp_detect(intel_dp);
4783         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4784                 status = intel_dp_detect_dpcd(intel_dp);
4785         else
4786                 status = connector_status_disconnected;
4787
4788         if (status == connector_status_disconnected) {
4789                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4790
4791                 if (intel_dp->is_mst) {
4792                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4793                                       intel_dp->is_mst,
4794                                       intel_dp->mst_mgr.mst_state);
4795                         intel_dp->is_mst = false;
4796                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4797                                                         intel_dp->is_mst);
4798                 }
4799
4800                 goto out;
4801         }
4802
4803         if (intel_dp->reset_link_params) {
4804                 /* Initial max link lane count */
4805                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4806
4807                 /* Initial max link rate */
4808                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4809
4810                 intel_dp->reset_link_params = false;
4811         }
4812
4813         intel_dp_print_rates(intel_dp);
4814
4815         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4816                          drm_dp_is_branch(intel_dp->dpcd));
4817
4818         intel_dp_configure_mst(intel_dp);
4819
4820         if (intel_dp->is_mst) {
4821                 /*
4822                  * If we are in MST mode then this connector
4823                  * won't appear connected or have anything
4824                  * with EDID on it
4825                  */
4826                 status = connector_status_disconnected;
4827                 goto out;
4828         } else {
4829                 /*
4830                  * If display is now connected check links status,
4831                  * there has been known issues of link loss triggerring
4832                  * long pulse.
4833                  *
4834                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4835                  * weird HPD ping pong during modesets. So we can apparently
4836                  * end up with HPD going low during a modeset, and then
4837                  * going back up soon after. And once that happens we must
4838                  * retrain the link to get a picture. That's in case no
4839                  * userspace component reacted to intermittent HPD dip.
4840                  */
4841                 intel_dp_check_link_status(intel_dp);
4842         }
4843
4844         /*
4845          * Clearing NACK and defer counts to get their exact values
4846          * while reading EDID which are required by Compliance tests
4847          * 4.2.2.4 and 4.2.2.5
4848          */
4849         intel_dp->aux.i2c_nack_count = 0;
4850         intel_dp->aux.i2c_defer_count = 0;
4851
4852         intel_dp_set_edid(intel_dp);
4853         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4854                 status = connector_status_connected;
4855         intel_dp->detect_done = true;
4856
4857         /* Try to read the source of the interrupt */
4858         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4859             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4860             sink_irq_vector != 0) {
4861                 /* Clear interrupt source */
4862                 drm_dp_dpcd_writeb(&intel_dp->aux,
4863                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4864                                    sink_irq_vector);
4865
4866                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4867                         intel_dp_handle_test_request(intel_dp);
4868                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4869                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4870         }
4871
4872 out:
4873         if (status != connector_status_connected && !intel_dp->is_mst)
4874                 intel_dp_unset_edid(intel_dp);
4875
4876         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4877         return status;
4878 }
4879
4880 static int
4881 intel_dp_detect(struct drm_connector *connector,
4882                 struct drm_modeset_acquire_ctx *ctx,
4883                 bool force)
4884 {
4885         struct intel_dp *intel_dp = intel_attached_dp(connector);
4886         int status = connector->status;
4887
4888         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4889                       connector->base.id, connector->name);
4890
4891         /* If full detect is not performed yet, do a full detect */
4892         if (!intel_dp->detect_done) {
4893                 struct drm_crtc *crtc;
4894                 int ret;
4895
4896                 crtc = connector->state->crtc;
4897                 if (crtc) {
4898                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4899                         if (ret)
4900                                 return ret;
4901                 }
4902
4903                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4904         }
4905
4906         intel_dp->detect_done = false;
4907
4908         return status;
4909 }
4910
4911 static void
4912 intel_dp_force(struct drm_connector *connector)
4913 {
4914         struct intel_dp *intel_dp = intel_attached_dp(connector);
4915         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4916         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4917
4918         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4919                       connector->base.id, connector->name);
4920         intel_dp_unset_edid(intel_dp);
4921
4922         if (connector->status != connector_status_connected)
4923                 return;
4924
4925         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4926
4927         intel_dp_set_edid(intel_dp);
4928
4929         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4930 }
4931
4932 static int intel_dp_get_modes(struct drm_connector *connector)
4933 {
4934         struct intel_connector *intel_connector = to_intel_connector(connector);
4935         struct edid *edid;
4936
4937         edid = intel_connector->detect_edid;
4938         if (edid) {
4939                 int ret = intel_connector_update_modes(connector, edid);
4940                 if (ret)
4941                         return ret;
4942         }
4943
4944         /* if eDP has no EDID, fall back to fixed mode */
4945         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4946             intel_connector->panel.fixed_mode) {
4947                 struct drm_display_mode *mode;
4948
4949                 mode = drm_mode_duplicate(connector->dev,
4950                                           intel_connector->panel.fixed_mode);
4951                 if (mode) {
4952                         drm_mode_probed_add(connector, mode);
4953                         return 1;
4954                 }
4955         }
4956
4957         return 0;
4958 }
4959
4960 static int
4961 intel_dp_connector_register(struct drm_connector *connector)
4962 {
4963         struct intel_dp *intel_dp = intel_attached_dp(connector);
4964         int ret;
4965
4966         ret = intel_connector_register(connector);
4967         if (ret)
4968                 return ret;
4969
4970         i915_debugfs_connector_add(connector);
4971
4972         DRM_DEBUG_KMS("registering %s bus for %s\n",
4973                       intel_dp->aux.name, connector->kdev->kobj.name);
4974
4975         intel_dp->aux.dev = connector->kdev;
4976         return drm_dp_aux_register(&intel_dp->aux);
4977 }
4978
4979 static void
4980 intel_dp_connector_unregister(struct drm_connector *connector)
4981 {
4982         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4983         intel_connector_unregister(connector);
4984 }
4985
4986 static void
4987 intel_dp_connector_destroy(struct drm_connector *connector)
4988 {
4989         struct intel_connector *intel_connector = to_intel_connector(connector);
4990
4991         kfree(intel_connector->detect_edid);
4992
4993         if (!IS_ERR_OR_NULL(intel_connector->edid))
4994                 kfree(intel_connector->edid);
4995
4996         /*
4997          * Can't call intel_dp_is_edp() since the encoder may have been
4998          * destroyed already.
4999          */
5000         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5001                 intel_panel_fini(&intel_connector->panel);
5002
5003         drm_connector_cleanup(connector);
5004         kfree(connector);
5005 }
5006
5007 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5008 {
5009         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5010         struct intel_dp *intel_dp = &intel_dig_port->dp;
5011
5012         intel_dp_mst_encoder_cleanup(intel_dig_port);
5013         if (intel_dp_is_edp(intel_dp)) {
5014                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5015                 /*
5016                  * vdd might still be enabled do to the delayed vdd off.
5017                  * Make sure vdd is actually turned off here.
5018                  */
5019                 pps_lock(intel_dp);
5020                 edp_panel_vdd_off_sync(intel_dp);
5021                 pps_unlock(intel_dp);
5022
5023                 if (intel_dp->edp_notifier.notifier_call) {
5024                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5025                         intel_dp->edp_notifier.notifier_call = NULL;
5026                 }
5027         }
5028
5029         intel_dp_aux_fini(intel_dp);
5030
5031         drm_encoder_cleanup(encoder);
5032         kfree(intel_dig_port);
5033 }
5034
5035 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5036 {
5037         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5038
5039         if (!intel_dp_is_edp(intel_dp))
5040                 return;
5041
5042         /*
5043          * vdd might still be enabled do to the delayed vdd off.
5044          * Make sure vdd is actually turned off here.
5045          */
5046         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5047         pps_lock(intel_dp);
5048         edp_panel_vdd_off_sync(intel_dp);
5049         pps_unlock(intel_dp);
5050 }
5051
5052 static
5053 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5054                                 u8 *an)
5055 {
5056         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5057         uint8_t txbuf[4], rxbuf[2], reply = 0;
5058         ssize_t dpcd_ret;
5059         int ret;
5060
5061         /* Output An first, that's easy */
5062         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5063                                      an, DRM_HDCP_AN_LEN);
5064         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5065                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5066                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5067         }
5068
5069         /*
5070          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5071          * order to get it on the wire, we need to create the AUX header as if
5072          * we were writing the data, and then tickle the hardware to output the
5073          * data once the header is sent out.
5074          */
5075         txbuf[0] = (DP_AUX_NATIVE_WRITE << 4) |
5076                    ((DP_AUX_HDCP_AKSV >> 16) & 0xf);
5077         txbuf[1] = (DP_AUX_HDCP_AKSV >> 8) & 0xff;
5078         txbuf[2] = DP_AUX_HDCP_AKSV & 0xff;
5079         txbuf[3] = DRM_HDCP_KSV_LEN - 1;
5080
5081         ret = intel_dp_aux_ch(intel_dp, txbuf, sizeof(txbuf), rxbuf,
5082                               sizeof(rxbuf), true);
5083         if (ret < 0) {
5084                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5085                 return ret;
5086         } else if (ret == 0) {
5087                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5088                 return -EIO;
5089         }
5090
5091         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5092         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5093 }
5094
5095 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5096                                    u8 *bksv)
5097 {
5098         ssize_t ret;
5099         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5100                                DRM_HDCP_KSV_LEN);
5101         if (ret != DRM_HDCP_KSV_LEN) {
5102                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5103                 return ret >= 0 ? -EIO : ret;
5104         }
5105         return 0;
5106 }
5107
5108 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5109                                       u8 *bstatus)
5110 {
5111         ssize_t ret;
5112         /*
5113          * For some reason the HDMI and DP HDCP specs call this register
5114          * definition by different names. In the HDMI spec, it's called BSTATUS,
5115          * but in DP it's called BINFO.
5116          */
5117         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5118                                bstatus, DRM_HDCP_BSTATUS_LEN);
5119         if (ret != DRM_HDCP_BSTATUS_LEN) {
5120                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5121                 return ret >= 0 ? -EIO : ret;
5122         }
5123         return 0;
5124 }
5125
5126 static
5127 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5128                              u8 *bcaps)
5129 {
5130         ssize_t ret;
5131
5132         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5133                                bcaps, 1);
5134         if (ret != 1) {
5135                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5136                 return ret >= 0 ? -EIO : ret;
5137         }
5138
5139         return 0;
5140 }
5141
5142 static
5143 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5144                                    bool *repeater_present)
5145 {
5146         ssize_t ret;
5147         u8 bcaps;
5148
5149         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5150         if (ret)
5151                 return ret;
5152
5153         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5154         return 0;
5155 }
5156
5157 static
5158 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5159                                 u8 *ri_prime)
5160 {
5161         ssize_t ret;
5162         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5163                                ri_prime, DRM_HDCP_RI_LEN);
5164         if (ret != DRM_HDCP_RI_LEN) {
5165                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5166                 return ret >= 0 ? -EIO : ret;
5167         }
5168         return 0;
5169 }
5170
5171 static
5172 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5173                                  bool *ksv_ready)
5174 {
5175         ssize_t ret;
5176         u8 bstatus;
5177         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5178                                &bstatus, 1);
5179         if (ret != 1) {
5180                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5181                 return ret >= 0 ? -EIO : ret;
5182         }
5183         *ksv_ready = bstatus & DP_BSTATUS_READY;
5184         return 0;
5185 }
5186
5187 static
5188 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5189                                 int num_downstream, u8 *ksv_fifo)
5190 {
5191         ssize_t ret;
5192         int i;
5193
5194         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5195         for (i = 0; i < num_downstream; i += 3) {
5196                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5197                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5198                                        DP_AUX_HDCP_KSV_FIFO,
5199                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5200                                        len);
5201                 if (ret != len) {
5202                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5203                                   ret);
5204                         return ret >= 0 ? -EIO : ret;
5205                 }
5206         }
5207         return 0;
5208 }
5209
5210 static
5211 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5212                                     int i, u32 *part)
5213 {
5214         ssize_t ret;
5215
5216         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5217                 return -EINVAL;
5218
5219         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5220                                DP_AUX_HDCP_V_PRIME(i), part,
5221                                DRM_HDCP_V_PRIME_PART_LEN);
5222         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5223                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5224                 return ret >= 0 ? -EIO : ret;
5225         }
5226         return 0;
5227 }
5228
5229 static
5230 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5231                                     bool enable)
5232 {
5233         /* Not used for single stream DisplayPort setups */
5234         return 0;
5235 }
5236
5237 static
5238 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5239 {
5240         ssize_t ret;
5241         u8 bstatus;
5242
5243         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5244                                &bstatus, 1);
5245         if (ret != 1) {
5246                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5247                 return false;
5248         }
5249
5250         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5251 }
5252
5253 static
5254 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5255                           bool *hdcp_capable)
5256 {
5257         ssize_t ret;
5258         u8 bcaps;
5259
5260         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5261         if (ret)
5262                 return ret;
5263
5264         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5265         return 0;
5266 }
5267
5268 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5269         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5270         .read_bksv = intel_dp_hdcp_read_bksv,
5271         .read_bstatus = intel_dp_hdcp_read_bstatus,
5272         .repeater_present = intel_dp_hdcp_repeater_present,
5273         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5274         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5275         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5276         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5277         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5278         .check_link = intel_dp_hdcp_check_link,
5279         .hdcp_capable = intel_dp_hdcp_capable,
5280 };
5281
5282 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5283 {
5284         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5285
5286         lockdep_assert_held(&dev_priv->pps_mutex);
5287
5288         if (!edp_have_panel_vdd(intel_dp))
5289                 return;
5290
5291         /*
5292          * The VDD bit needs a power domain reference, so if the bit is
5293          * already enabled when we boot or resume, grab this reference and
5294          * schedule a vdd off, so we don't hold on to the reference
5295          * indefinitely.
5296          */
5297         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5298         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5299
5300         edp_panel_vdd_schedule_off(intel_dp);
5301 }
5302
5303 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5304 {
5305         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5306
5307         if ((intel_dp->DP & DP_PORT_EN) == 0)
5308                 return INVALID_PIPE;
5309
5310         if (IS_CHERRYVIEW(dev_priv))
5311                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5312         else
5313                 return PORT_TO_PIPE(intel_dp->DP);
5314 }
5315
5316 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5317 {
5318         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5319         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5320         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5321
5322         if (!HAS_DDI(dev_priv))
5323                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5324
5325         if (lspcon->active)
5326                 lspcon_resume(lspcon);
5327
5328         intel_dp->reset_link_params = true;
5329
5330         pps_lock(intel_dp);
5331
5332         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5333                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5334
5335         if (intel_dp_is_edp(intel_dp)) {
5336                 /* Reinit the power sequencer, in case BIOS did something with it. */
5337                 intel_dp_pps_init(intel_dp);
5338                 intel_edp_panel_vdd_sanitize(intel_dp);
5339         }
5340
5341         pps_unlock(intel_dp);
5342 }
5343
5344 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5345         .force = intel_dp_force,
5346         .fill_modes = drm_helper_probe_single_connector_modes,
5347         .atomic_get_property = intel_digital_connector_atomic_get_property,
5348         .atomic_set_property = intel_digital_connector_atomic_set_property,
5349         .late_register = intel_dp_connector_register,
5350         .early_unregister = intel_dp_connector_unregister,
5351         .destroy = intel_dp_connector_destroy,
5352         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5353         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5354 };
5355
5356 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5357         .detect_ctx = intel_dp_detect,
5358         .get_modes = intel_dp_get_modes,
5359         .mode_valid = intel_dp_mode_valid,
5360         .atomic_check = intel_digital_connector_atomic_check,
5361 };
5362
5363 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5364         .reset = intel_dp_encoder_reset,
5365         .destroy = intel_dp_encoder_destroy,
5366 };
5367
5368 enum irqreturn
5369 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5370 {
5371         struct intel_dp *intel_dp = &intel_dig_port->dp;
5372         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5373         enum irqreturn ret = IRQ_NONE;
5374
5375         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5376                 /*
5377                  * vdd off can generate a long pulse on eDP which
5378                  * would require vdd on to handle it, and thus we
5379                  * would end up in an endless cycle of
5380                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5381                  */
5382                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5383                               port_name(intel_dig_port->base.port));
5384                 return IRQ_HANDLED;
5385         }
5386
5387         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5388                       port_name(intel_dig_port->base.port),
5389                       long_hpd ? "long" : "short");
5390
5391         if (long_hpd) {
5392                 intel_dp->reset_link_params = true;
5393                 intel_dp->detect_done = false;
5394                 return IRQ_NONE;
5395         }
5396
5397         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5398
5399         if (intel_dp->is_mst) {
5400                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5401                         /*
5402                          * If we were in MST mode, and device is not
5403                          * there, get out of MST mode
5404                          */
5405                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5406                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5407                         intel_dp->is_mst = false;
5408                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5409                                                         intel_dp->is_mst);
5410                         intel_dp->detect_done = false;
5411                         goto put_power;
5412                 }
5413         }
5414
5415         if (!intel_dp->is_mst) {
5416                 struct drm_modeset_acquire_ctx ctx;
5417                 struct drm_connector *connector = &intel_dp->attached_connector->base;
5418                 struct drm_crtc *crtc;
5419                 int iret;
5420                 bool handled = false;
5421
5422                 drm_modeset_acquire_init(&ctx, 0);
5423 retry:
5424                 iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
5425                 if (iret)
5426                         goto err;
5427
5428                 crtc = connector->state->crtc;
5429                 if (crtc) {
5430                         iret = drm_modeset_lock(&crtc->mutex, &ctx);
5431                         if (iret)
5432                                 goto err;
5433                 }
5434
5435                 handled = intel_dp_short_pulse(intel_dp);
5436
5437 err:
5438                 if (iret == -EDEADLK) {
5439                         drm_modeset_backoff(&ctx);
5440                         goto retry;
5441                 }
5442
5443                 drm_modeset_drop_locks(&ctx);
5444                 drm_modeset_acquire_fini(&ctx);
5445                 WARN(iret, "Acquiring modeset locks failed with %i\n", iret);
5446
5447                 /* Short pulse can signify loss of hdcp authentication */
5448                 intel_hdcp_check_link(intel_dp->attached_connector);
5449
5450                 if (!handled) {
5451                         intel_dp->detect_done = false;
5452                         goto put_power;
5453                 }
5454         }
5455
5456         ret = IRQ_HANDLED;
5457
5458 put_power:
5459         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5460
5461         return ret;
5462 }
5463
5464 /* check the VBT to see whether the eDP is on another port */
5465 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5466 {
5467         /*
5468          * eDP not supported on g4x. so bail out early just
5469          * for a bit extra safety in case the VBT is bonkers.
5470          */
5471         if (INTEL_GEN(dev_priv) < 5)
5472                 return false;
5473
5474         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5475                 return true;
5476
5477         return intel_bios_is_port_edp(dev_priv, port);
5478 }
5479
5480 static void
5481 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5482 {
5483         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5484         enum port port = dp_to_dig_port(intel_dp)->base.port;
5485
5486         if (!IS_G4X(dev_priv) && port != PORT_A)
5487                 intel_attach_force_audio_property(connector);
5488
5489         intel_attach_broadcast_rgb_property(connector);
5490
5491         if (intel_dp_is_edp(intel_dp)) {
5492                 u32 allowed_scalers;
5493
5494                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5495                 if (!HAS_GMCH_DISPLAY(dev_priv))
5496                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5497
5498                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5499
5500                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5501
5502         }
5503 }
5504
5505 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5506 {
5507         intel_dp->panel_power_off_time = ktime_get_boottime();
5508         intel_dp->last_power_on = jiffies;
5509         intel_dp->last_backlight_off = jiffies;
5510 }
5511
5512 static void
5513 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5514 {
5515         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5516         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5517         struct pps_registers regs;
5518
5519         intel_pps_get_registers(intel_dp, &regs);
5520
5521         /* Workaround: Need to write PP_CONTROL with the unlock key as
5522          * the very first thing. */
5523         pp_ctl = ironlake_get_pp_control(intel_dp);
5524
5525         pp_on = I915_READ(regs.pp_on);
5526         pp_off = I915_READ(regs.pp_off);
5527         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5528             !HAS_PCH_ICP(dev_priv)) {
5529                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5530                 pp_div = I915_READ(regs.pp_div);
5531         }
5532
5533         /* Pull timing values out of registers */
5534         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5535                      PANEL_POWER_UP_DELAY_SHIFT;
5536
5537         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5538                   PANEL_LIGHT_ON_DELAY_SHIFT;
5539
5540         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5541                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5542
5543         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5544                    PANEL_POWER_DOWN_DELAY_SHIFT;
5545
5546         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5547             HAS_PCH_ICP(dev_priv)) {
5548                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5549                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5550         } else {
5551                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5552                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5553         }
5554 }
5555
5556 static void
5557 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5558 {
5559         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5560                       state_name,
5561                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5562 }
5563
5564 static void
5565 intel_pps_verify_state(struct intel_dp *intel_dp)
5566 {
5567         struct edp_power_seq hw;
5568         struct edp_power_seq *sw = &intel_dp->pps_delays;
5569
5570         intel_pps_readout_hw_state(intel_dp, &hw);
5571
5572         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5573             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5574                 DRM_ERROR("PPS state mismatch\n");
5575                 intel_pps_dump_state("sw", sw);
5576                 intel_pps_dump_state("hw", &hw);
5577         }
5578 }
5579
5580 static void
5581 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5582 {
5583         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5584         struct edp_power_seq cur, vbt, spec,
5585                 *final = &intel_dp->pps_delays;
5586
5587         lockdep_assert_held(&dev_priv->pps_mutex);
5588
5589         /* already initialized? */
5590         if (final->t11_t12 != 0)
5591                 return;
5592
5593         intel_pps_readout_hw_state(intel_dp, &cur);
5594
5595         intel_pps_dump_state("cur", &cur);
5596
5597         vbt = dev_priv->vbt.edp.pps;
5598         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5599          * of 500ms appears to be too short. Ocassionally the panel
5600          * just fails to power back on. Increasing the delay to 800ms
5601          * seems sufficient to avoid this problem.
5602          */
5603         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5604                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5605                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5606                               vbt.t11_t12);
5607         }
5608         /* T11_T12 delay is special and actually in units of 100ms, but zero
5609          * based in the hw (so we need to add 100 ms). But the sw vbt
5610          * table multiplies it with 1000 to make it in units of 100usec,
5611          * too. */
5612         vbt.t11_t12 += 100 * 10;
5613
5614         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5615          * our hw here, which are all in 100usec. */
5616         spec.t1_t3 = 210 * 10;
5617         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5618         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5619         spec.t10 = 500 * 10;
5620         /* This one is special and actually in units of 100ms, but zero
5621          * based in the hw (so we need to add 100 ms). But the sw vbt
5622          * table multiplies it with 1000 to make it in units of 100usec,
5623          * too. */
5624         spec.t11_t12 = (510 + 100) * 10;
5625
5626         intel_pps_dump_state("vbt", &vbt);
5627
5628         /* Use the max of the register settings and vbt. If both are
5629          * unset, fall back to the spec limits. */
5630 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5631                                        spec.field : \
5632                                        max(cur.field, vbt.field))
5633         assign_final(t1_t3);
5634         assign_final(t8);
5635         assign_final(t9);
5636         assign_final(t10);
5637         assign_final(t11_t12);
5638 #undef assign_final
5639
5640 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5641         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5642         intel_dp->backlight_on_delay = get_delay(t8);
5643         intel_dp->backlight_off_delay = get_delay(t9);
5644         intel_dp->panel_power_down_delay = get_delay(t10);
5645         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5646 #undef get_delay
5647
5648         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5649                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5650                       intel_dp->panel_power_cycle_delay);
5651
5652         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5653                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5654
5655         /*
5656          * We override the HW backlight delays to 1 because we do manual waits
5657          * on them. For T8, even BSpec recommends doing it. For T9, if we
5658          * don't do this, we'll end up waiting for the backlight off delay
5659          * twice: once when we do the manual sleep, and once when we disable
5660          * the panel and wait for the PP_STATUS bit to become zero.
5661          */
5662         final->t8 = 1;
5663         final->t9 = 1;
5664
5665         /*
5666          * HW has only a 100msec granularity for t11_t12 so round it up
5667          * accordingly.
5668          */
5669         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5670 }
5671
5672 static void
5673 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5674                                               bool force_disable_vdd)
5675 {
5676         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5677         u32 pp_on, pp_off, pp_div, port_sel = 0;
5678         int div = dev_priv->rawclk_freq / 1000;
5679         struct pps_registers regs;
5680         enum port port = dp_to_dig_port(intel_dp)->base.port;
5681         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5682
5683         lockdep_assert_held(&dev_priv->pps_mutex);
5684
5685         intel_pps_get_registers(intel_dp, &regs);
5686
5687         /*
5688          * On some VLV machines the BIOS can leave the VDD
5689          * enabled even on power seqeuencers which aren't
5690          * hooked up to any port. This would mess up the
5691          * power domain tracking the first time we pick
5692          * one of these power sequencers for use since
5693          * edp_panel_vdd_on() would notice that the VDD was
5694          * already on and therefore wouldn't grab the power
5695          * domain reference. Disable VDD first to avoid this.
5696          * This also avoids spuriously turning the VDD on as
5697          * soon as the new power seqeuencer gets initialized.
5698          */
5699         if (force_disable_vdd) {
5700                 u32 pp = ironlake_get_pp_control(intel_dp);
5701
5702                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5703
5704                 if (pp & EDP_FORCE_VDD)
5705                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5706
5707                 pp &= ~EDP_FORCE_VDD;
5708
5709                 I915_WRITE(regs.pp_ctrl, pp);
5710         }
5711
5712         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5713                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5714         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5715                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5716         /* Compute the divisor for the pp clock, simply match the Bspec
5717          * formula. */
5718         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5719             HAS_PCH_ICP(dev_priv)) {
5720                 pp_div = I915_READ(regs.pp_ctrl);
5721                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5722                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5723                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5724         } else {
5725                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5726                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5727                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5728         }
5729
5730         /* Haswell doesn't have any port selection bits for the panel
5731          * power sequencer any more. */
5732         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5733                 port_sel = PANEL_PORT_SELECT_VLV(port);
5734         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5735                 if (port == PORT_A)
5736                         port_sel = PANEL_PORT_SELECT_DPA;
5737                 else
5738                         port_sel = PANEL_PORT_SELECT_DPD;
5739         }
5740
5741         pp_on |= port_sel;
5742
5743         I915_WRITE(regs.pp_on, pp_on);
5744         I915_WRITE(regs.pp_off, pp_off);
5745         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5746             HAS_PCH_ICP(dev_priv))
5747                 I915_WRITE(regs.pp_ctrl, pp_div);
5748         else
5749                 I915_WRITE(regs.pp_div, pp_div);
5750
5751         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5752                       I915_READ(regs.pp_on),
5753                       I915_READ(regs.pp_off),
5754                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5755                        HAS_PCH_ICP(dev_priv)) ?
5756                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5757                       I915_READ(regs.pp_div));
5758 }
5759
5760 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5761 {
5762         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5763
5764         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5765                 vlv_initial_power_sequencer_setup(intel_dp);
5766         } else {
5767                 intel_dp_init_panel_power_sequencer(intel_dp);
5768                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5769         }
5770 }
5771
5772 /**
5773  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5774  * @dev_priv: i915 device
5775  * @crtc_state: a pointer to the active intel_crtc_state
5776  * @refresh_rate: RR to be programmed
5777  *
5778  * This function gets called when refresh rate (RR) has to be changed from
5779  * one frequency to another. Switches can be between high and low RR
5780  * supported by the panel or to any other RR based on media playback (in
5781  * this case, RR value needs to be passed from user space).
5782  *
5783  * The caller of this function needs to take a lock on dev_priv->drrs.
5784  */
5785 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5786                                     const struct intel_crtc_state *crtc_state,
5787                                     int refresh_rate)
5788 {
5789         struct intel_encoder *encoder;
5790         struct intel_digital_port *dig_port = NULL;
5791         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5793         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5794
5795         if (refresh_rate <= 0) {
5796                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5797                 return;
5798         }
5799
5800         if (intel_dp == NULL) {
5801                 DRM_DEBUG_KMS("DRRS not supported.\n");
5802                 return;
5803         }
5804
5805         dig_port = dp_to_dig_port(intel_dp);
5806         encoder = &dig_port->base;
5807
5808         if (!intel_crtc) {
5809                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5810                 return;
5811         }
5812
5813         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5814                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5815                 return;
5816         }
5817
5818         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5819                         refresh_rate)
5820                 index = DRRS_LOW_RR;
5821
5822         if (index == dev_priv->drrs.refresh_rate_type) {
5823                 DRM_DEBUG_KMS(
5824                         "DRRS requested for previously set RR...ignoring\n");
5825                 return;
5826         }
5827
5828         if (!crtc_state->base.active) {
5829                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5830                 return;
5831         }
5832
5833         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5834                 switch (index) {
5835                 case DRRS_HIGH_RR:
5836                         intel_dp_set_m_n(intel_crtc, M1_N1);
5837                         break;
5838                 case DRRS_LOW_RR:
5839                         intel_dp_set_m_n(intel_crtc, M2_N2);
5840                         break;
5841                 case DRRS_MAX_RR:
5842                 default:
5843                         DRM_ERROR("Unsupported refreshrate type\n");
5844                 }
5845         } else if (INTEL_GEN(dev_priv) > 6) {
5846                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5847                 u32 val;
5848
5849                 val = I915_READ(reg);
5850                 if (index > DRRS_HIGH_RR) {
5851                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5852                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5853                         else
5854                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5855                 } else {
5856                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5857                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5858                         else
5859                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5860                 }
5861                 I915_WRITE(reg, val);
5862         }
5863
5864         dev_priv->drrs.refresh_rate_type = index;
5865
5866         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5867 }
5868
5869 /**
5870  * intel_edp_drrs_enable - init drrs struct if supported
5871  * @intel_dp: DP struct
5872  * @crtc_state: A pointer to the active crtc state.
5873  *
5874  * Initializes frontbuffer_bits and drrs.dp
5875  */
5876 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5877                            const struct intel_crtc_state *crtc_state)
5878 {
5879         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5880
5881         if (!crtc_state->has_drrs) {
5882                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5883                 return;
5884         }
5885
5886         if (dev_priv->psr.enabled) {
5887                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5888                 return;
5889         }
5890
5891         mutex_lock(&dev_priv->drrs.mutex);
5892         if (WARN_ON(dev_priv->drrs.dp)) {
5893                 DRM_ERROR("DRRS already enabled\n");
5894                 goto unlock;
5895         }
5896
5897         dev_priv->drrs.busy_frontbuffer_bits = 0;
5898
5899         dev_priv->drrs.dp = intel_dp;
5900
5901 unlock:
5902         mutex_unlock(&dev_priv->drrs.mutex);
5903 }
5904
5905 /**
5906  * intel_edp_drrs_disable - Disable DRRS
5907  * @intel_dp: DP struct
5908  * @old_crtc_state: Pointer to old crtc_state.
5909  *
5910  */
5911 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5912                             const struct intel_crtc_state *old_crtc_state)
5913 {
5914         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5915
5916         if (!old_crtc_state->has_drrs)
5917                 return;
5918
5919         mutex_lock(&dev_priv->drrs.mutex);
5920         if (!dev_priv->drrs.dp) {
5921                 mutex_unlock(&dev_priv->drrs.mutex);
5922                 return;
5923         }
5924
5925         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5926                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5927                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5928
5929         dev_priv->drrs.dp = NULL;
5930         mutex_unlock(&dev_priv->drrs.mutex);
5931
5932         cancel_delayed_work_sync(&dev_priv->drrs.work);
5933 }
5934
5935 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5936 {
5937         struct drm_i915_private *dev_priv =
5938                 container_of(work, typeof(*dev_priv), drrs.work.work);
5939         struct intel_dp *intel_dp;
5940
5941         mutex_lock(&dev_priv->drrs.mutex);
5942
5943         intel_dp = dev_priv->drrs.dp;
5944
5945         if (!intel_dp)
5946                 goto unlock;
5947
5948         /*
5949          * The delayed work can race with an invalidate hence we need to
5950          * recheck.
5951          */
5952
5953         if (dev_priv->drrs.busy_frontbuffer_bits)
5954                 goto unlock;
5955
5956         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5957                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5958
5959                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5960                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5961         }
5962
5963 unlock:
5964         mutex_unlock(&dev_priv->drrs.mutex);
5965 }
5966
5967 /**
5968  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5969  * @dev_priv: i915 device
5970  * @frontbuffer_bits: frontbuffer plane tracking bits
5971  *
5972  * This function gets called everytime rendering on the given planes start.
5973  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5974  *
5975  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5976  */
5977 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5978                                unsigned int frontbuffer_bits)
5979 {
5980         struct drm_crtc *crtc;
5981         enum pipe pipe;
5982
5983         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5984                 return;
5985
5986         cancel_delayed_work(&dev_priv->drrs.work);
5987
5988         mutex_lock(&dev_priv->drrs.mutex);
5989         if (!dev_priv->drrs.dp) {
5990                 mutex_unlock(&dev_priv->drrs.mutex);
5991                 return;
5992         }
5993
5994         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5995         pipe = to_intel_crtc(crtc)->pipe;
5996
5997         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5998         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5999
6000         /* invalidate means busy screen hence upclock */
6001         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6002                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6003                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6004
6005         mutex_unlock(&dev_priv->drrs.mutex);
6006 }
6007
6008 /**
6009  * intel_edp_drrs_flush - Restart Idleness DRRS
6010  * @dev_priv: i915 device
6011  * @frontbuffer_bits: frontbuffer plane tracking bits
6012  *
6013  * This function gets called every time rendering on the given planes has
6014  * completed or flip on a crtc is completed. So DRRS should be upclocked
6015  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6016  * if no other planes are dirty.
6017  *
6018  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6019  */
6020 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6021                           unsigned int frontbuffer_bits)
6022 {
6023         struct drm_crtc *crtc;
6024         enum pipe pipe;
6025
6026         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6027                 return;
6028
6029         cancel_delayed_work(&dev_priv->drrs.work);
6030
6031         mutex_lock(&dev_priv->drrs.mutex);
6032         if (!dev_priv->drrs.dp) {
6033                 mutex_unlock(&dev_priv->drrs.mutex);
6034                 return;
6035         }
6036
6037         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6038         pipe = to_intel_crtc(crtc)->pipe;
6039
6040         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6041         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6042
6043         /* flush means busy screen hence upclock */
6044         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6045                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6046                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6047
6048         /*
6049          * flush also means no more activity hence schedule downclock, if all
6050          * other fbs are quiescent too
6051          */
6052         if (!dev_priv->drrs.busy_frontbuffer_bits)
6053                 schedule_delayed_work(&dev_priv->drrs.work,
6054                                 msecs_to_jiffies(1000));
6055         mutex_unlock(&dev_priv->drrs.mutex);
6056 }
6057
6058 /**
6059  * DOC: Display Refresh Rate Switching (DRRS)
6060  *
6061  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6062  * which enables swtching between low and high refresh rates,
6063  * dynamically, based on the usage scenario. This feature is applicable
6064  * for internal panels.
6065  *
6066  * Indication that the panel supports DRRS is given by the panel EDID, which
6067  * would list multiple refresh rates for one resolution.
6068  *
6069  * DRRS is of 2 types - static and seamless.
6070  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6071  * (may appear as a blink on screen) and is used in dock-undock scenario.
6072  * Seamless DRRS involves changing RR without any visual effect to the user
6073  * and can be used during normal system usage. This is done by programming
6074  * certain registers.
6075  *
6076  * Support for static/seamless DRRS may be indicated in the VBT based on
6077  * inputs from the panel spec.
6078  *
6079  * DRRS saves power by switching to low RR based on usage scenarios.
6080  *
6081  * The implementation is based on frontbuffer tracking implementation.  When
6082  * there is a disturbance on the screen triggered by user activity or a periodic
6083  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6084  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6085  * made.
6086  *
6087  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6088  * and intel_edp_drrs_flush() are called.
6089  *
6090  * DRRS can be further extended to support other internal panels and also
6091  * the scenario of video playback wherein RR is set based on the rate
6092  * requested by userspace.
6093  */
6094
6095 /**
6096  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6097  * @connector: eDP connector
6098  * @fixed_mode: preferred mode of panel
6099  *
6100  * This function is  called only once at driver load to initialize basic
6101  * DRRS stuff.
6102  *
6103  * Returns:
6104  * Downclock mode if panel supports it, else return NULL.
6105  * DRRS support is determined by the presence of downclock mode (apart
6106  * from VBT setting).
6107  */
6108 static struct drm_display_mode *
6109 intel_dp_drrs_init(struct intel_connector *connector,
6110                    struct drm_display_mode *fixed_mode)
6111 {
6112         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6113         struct drm_display_mode *downclock_mode = NULL;
6114
6115         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6116         mutex_init(&dev_priv->drrs.mutex);
6117
6118         if (INTEL_GEN(dev_priv) <= 6) {
6119                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6120                 return NULL;
6121         }
6122
6123         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6124                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6125                 return NULL;
6126         }
6127
6128         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6129                                                     &connector->base);
6130
6131         if (!downclock_mode) {
6132                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6133                 return NULL;
6134         }
6135
6136         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6137
6138         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6139         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6140         return downclock_mode;
6141 }
6142
6143 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6144                                      struct intel_connector *intel_connector)
6145 {
6146         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6147         struct drm_i915_private *dev_priv = to_i915(dev);
6148         struct drm_connector *connector = &intel_connector->base;
6149         struct drm_display_mode *fixed_mode = NULL;
6150         struct drm_display_mode *alt_fixed_mode = NULL;
6151         struct drm_display_mode *downclock_mode = NULL;
6152         bool has_dpcd;
6153         struct drm_display_mode *scan;
6154         struct edid *edid;
6155         enum pipe pipe = INVALID_PIPE;
6156
6157         if (!intel_dp_is_edp(intel_dp))
6158                 return true;
6159
6160         /*
6161          * On IBX/CPT we may get here with LVDS already registered. Since the
6162          * driver uses the only internal power sequencer available for both
6163          * eDP and LVDS bail out early in this case to prevent interfering
6164          * with an already powered-on LVDS power sequencer.
6165          */
6166         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6167                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6168                 DRM_INFO("LVDS was detected, not registering eDP\n");
6169
6170                 return false;
6171         }
6172
6173         pps_lock(intel_dp);
6174
6175         intel_dp_init_panel_power_timestamps(intel_dp);
6176         intel_dp_pps_init(intel_dp);
6177         intel_edp_panel_vdd_sanitize(intel_dp);
6178
6179         pps_unlock(intel_dp);
6180
6181         /* Cache DPCD and EDID for edp. */
6182         has_dpcd = intel_edp_init_dpcd(intel_dp);
6183
6184         if (!has_dpcd) {
6185                 /* if this fails, presume the device is a ghost */
6186                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6187                 goto out_vdd_off;
6188         }
6189
6190         mutex_lock(&dev->mode_config.mutex);
6191         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6192         if (edid) {
6193                 if (drm_add_edid_modes(connector, edid)) {
6194                         drm_mode_connector_update_edid_property(connector,
6195                                                                 edid);
6196                 } else {
6197                         kfree(edid);
6198                         edid = ERR_PTR(-EINVAL);
6199                 }
6200         } else {
6201                 edid = ERR_PTR(-ENOENT);
6202         }
6203         intel_connector->edid = edid;
6204
6205         /* prefer fixed mode from EDID if available, save an alt mode also */
6206         list_for_each_entry(scan, &connector->probed_modes, head) {
6207                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6208                         fixed_mode = drm_mode_duplicate(dev, scan);
6209                         downclock_mode = intel_dp_drrs_init(
6210                                                 intel_connector, fixed_mode);
6211                 } else if (!alt_fixed_mode) {
6212                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
6213                 }
6214         }
6215
6216         /* fallback to VBT if available for eDP */
6217         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6218                 fixed_mode = drm_mode_duplicate(dev,
6219                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6220                 if (fixed_mode) {
6221                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6222                         connector->display_info.width_mm = fixed_mode->width_mm;
6223                         connector->display_info.height_mm = fixed_mode->height_mm;
6224                 }
6225         }
6226         mutex_unlock(&dev->mode_config.mutex);
6227
6228         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6229                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6230                 register_reboot_notifier(&intel_dp->edp_notifier);
6231
6232                 /*
6233                  * Figure out the current pipe for the initial backlight setup.
6234                  * If the current pipe isn't valid, try the PPS pipe, and if that
6235                  * fails just assume pipe A.
6236                  */
6237                 pipe = vlv_active_pipe(intel_dp);
6238
6239                 if (pipe != PIPE_A && pipe != PIPE_B)
6240                         pipe = intel_dp->pps_pipe;
6241
6242                 if (pipe != PIPE_A && pipe != PIPE_B)
6243                         pipe = PIPE_A;
6244
6245                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6246                               pipe_name(pipe));
6247         }
6248
6249         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
6250                          downclock_mode);
6251         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6252         intel_panel_setup_backlight(connector, pipe);
6253
6254         return true;
6255
6256 out_vdd_off:
6257         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6258         /*
6259          * vdd might still be enabled do to the delayed vdd off.
6260          * Make sure vdd is actually turned off here.
6261          */
6262         pps_lock(intel_dp);
6263         edp_panel_vdd_off_sync(intel_dp);
6264         pps_unlock(intel_dp);
6265
6266         return false;
6267 }
6268
6269 /* Set up the hotplug pin and aux power domain. */
6270 static void
6271 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
6272 {
6273         struct intel_encoder *encoder = &intel_dig_port->base;
6274         struct intel_dp *intel_dp = &intel_dig_port->dp;
6275         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6276         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6277
6278         encoder->hpd_pin = intel_hpd_pin_default(dev_priv, encoder->port);
6279
6280         switch (encoder->port) {
6281         case PORT_A:
6282                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
6283                 break;
6284         case PORT_B:
6285                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
6286                 break;
6287         case PORT_C:
6288                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
6289                 break;
6290         case PORT_D:
6291                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
6292                 break;
6293         case PORT_E:
6294                 /* FIXME: Check VBT for actual wiring of PORT E */
6295                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
6296                 break;
6297         case PORT_F:
6298                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_F;
6299                 break;
6300         default:
6301                 MISSING_CASE(encoder->port);
6302         }
6303 }
6304
6305 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6306 {
6307         struct intel_connector *intel_connector;
6308         struct drm_connector *connector;
6309
6310         intel_connector = container_of(work, typeof(*intel_connector),
6311                                        modeset_retry_work);
6312         connector = &intel_connector->base;
6313         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6314                       connector->name);
6315
6316         /* Grab the locks before changing connector property*/
6317         mutex_lock(&connector->dev->mode_config.mutex);
6318         /* Set connector link status to BAD and send a Uevent to notify
6319          * userspace to do a modeset.
6320          */
6321         drm_mode_connector_set_link_status_property(connector,
6322                                                     DRM_MODE_LINK_STATUS_BAD);
6323         mutex_unlock(&connector->dev->mode_config.mutex);
6324         /* Send Hotplug uevent so userspace can reprobe */
6325         drm_kms_helper_hotplug_event(connector->dev);
6326 }
6327
6328 bool
6329 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6330                         struct intel_connector *intel_connector)
6331 {
6332         struct drm_connector *connector = &intel_connector->base;
6333         struct intel_dp *intel_dp = &intel_dig_port->dp;
6334         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6335         struct drm_device *dev = intel_encoder->base.dev;
6336         struct drm_i915_private *dev_priv = to_i915(dev);
6337         enum port port = intel_encoder->port;
6338         int type;
6339
6340         /* Initialize the work for modeset in case of link train failure */
6341         INIT_WORK(&intel_connector->modeset_retry_work,
6342                   intel_dp_modeset_retry_work_fn);
6343
6344         if (WARN(intel_dig_port->max_lanes < 1,
6345                  "Not enough lanes (%d) for DP on port %c\n",
6346                  intel_dig_port->max_lanes, port_name(port)))
6347                 return false;
6348
6349         intel_dp_set_source_rates(intel_dp);
6350
6351         intel_dp->reset_link_params = true;
6352         intel_dp->pps_pipe = INVALID_PIPE;
6353         intel_dp->active_pipe = INVALID_PIPE;
6354
6355         /* intel_dp vfuncs */
6356         if (INTEL_GEN(dev_priv) >= 9)
6357                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6358         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6359                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6360         else if (HAS_PCH_SPLIT(dev_priv))
6361                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6362         else
6363                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6364
6365         if (INTEL_GEN(dev_priv) >= 9)
6366                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6367         else
6368                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6369
6370         if (HAS_DDI(dev_priv))
6371                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6372
6373         /* Preserve the current hw state. */
6374         intel_dp->DP = I915_READ(intel_dp->output_reg);
6375         intel_dp->attached_connector = intel_connector;
6376
6377         if (intel_dp_is_port_edp(dev_priv, port))
6378                 type = DRM_MODE_CONNECTOR_eDP;
6379         else
6380                 type = DRM_MODE_CONNECTOR_DisplayPort;
6381
6382         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6383                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6384
6385         /*
6386          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6387          * for DP the encoder type can be set by the caller to
6388          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6389          */
6390         if (type == DRM_MODE_CONNECTOR_eDP)
6391                 intel_encoder->type = INTEL_OUTPUT_EDP;
6392
6393         /* eDP only on port B and/or C on vlv/chv */
6394         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6395                     intel_dp_is_edp(intel_dp) &&
6396                     port != PORT_B && port != PORT_C))
6397                 return false;
6398
6399         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6400                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6401                         port_name(port));
6402
6403         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6404         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6405
6406         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6407                 connector->interlace_allowed = true;
6408         connector->doublescan_allowed = 0;
6409
6410         intel_dp_init_connector_port_info(intel_dig_port);
6411
6412         intel_dp_aux_init(intel_dp);
6413
6414         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6415                           edp_panel_vdd_work);
6416
6417         intel_connector_attach_encoder(intel_connector, intel_encoder);
6418
6419         if (HAS_DDI(dev_priv))
6420                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6421         else
6422                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6423
6424         /* init MST on ports that can support it */
6425         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6426             (port == PORT_B || port == PORT_C ||
6427              port == PORT_D || port == PORT_F))
6428                 intel_dp_mst_encoder_init(intel_dig_port,
6429                                           intel_connector->base.base.id);
6430
6431         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6432                 intel_dp_aux_fini(intel_dp);
6433                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6434                 goto fail;
6435         }
6436
6437         intel_dp_add_properties(intel_dp, connector);
6438
6439         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6440                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6441                 if (ret)
6442                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6443         }
6444
6445         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6446          * 0xd.  Failure to do so will result in spurious interrupts being
6447          * generated on the port when a cable is not attached.
6448          */
6449         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6450                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6451                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6452         }
6453
6454         return true;
6455
6456 fail:
6457         drm_connector_cleanup(connector);
6458
6459         return false;
6460 }
6461
6462 bool intel_dp_init(struct drm_i915_private *dev_priv,
6463                    i915_reg_t output_reg,
6464                    enum port port)
6465 {
6466         struct intel_digital_port *intel_dig_port;
6467         struct intel_encoder *intel_encoder;
6468         struct drm_encoder *encoder;
6469         struct intel_connector *intel_connector;
6470
6471         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6472         if (!intel_dig_port)
6473                 return false;
6474
6475         intel_connector = intel_connector_alloc();
6476         if (!intel_connector)
6477                 goto err_connector_alloc;
6478
6479         intel_encoder = &intel_dig_port->base;
6480         encoder = &intel_encoder->base;
6481
6482         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6483                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6484                              "DP %c", port_name(port)))
6485                 goto err_encoder_init;
6486
6487         intel_encoder->compute_config = intel_dp_compute_config;
6488         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6489         intel_encoder->get_config = intel_dp_get_config;
6490         intel_encoder->suspend = intel_dp_encoder_suspend;
6491         if (IS_CHERRYVIEW(dev_priv)) {
6492                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6493                 intel_encoder->pre_enable = chv_pre_enable_dp;
6494                 intel_encoder->enable = vlv_enable_dp;
6495                 intel_encoder->disable = vlv_disable_dp;
6496                 intel_encoder->post_disable = chv_post_disable_dp;
6497                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6498         } else if (IS_VALLEYVIEW(dev_priv)) {
6499                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6500                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6501                 intel_encoder->enable = vlv_enable_dp;
6502                 intel_encoder->disable = vlv_disable_dp;
6503                 intel_encoder->post_disable = vlv_post_disable_dp;
6504         } else if (INTEL_GEN(dev_priv) >= 5) {
6505                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6506                 intel_encoder->enable = g4x_enable_dp;
6507                 intel_encoder->disable = ilk_disable_dp;
6508                 intel_encoder->post_disable = ilk_post_disable_dp;
6509         } else {
6510                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6511                 intel_encoder->enable = g4x_enable_dp;
6512                 intel_encoder->disable = g4x_disable_dp;
6513         }
6514
6515         intel_dig_port->dp.output_reg = output_reg;
6516         intel_dig_port->max_lanes = 4;
6517
6518         intel_encoder->type = INTEL_OUTPUT_DP;
6519         intel_encoder->power_domain = intel_port_to_power_domain(port);
6520         if (IS_CHERRYVIEW(dev_priv)) {
6521                 if (port == PORT_D)
6522                         intel_encoder->crtc_mask = 1 << 2;
6523                 else
6524                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6525         } else {
6526                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6527         }
6528         intel_encoder->cloneable = 0;
6529         intel_encoder->port = port;
6530
6531         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6532         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6533
6534         if (port != PORT_A)
6535                 intel_infoframe_init(intel_dig_port);
6536
6537         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6538                 goto err_init_connector;
6539
6540         return true;
6541
6542 err_init_connector:
6543         drm_encoder_cleanup(encoder);
6544 err_encoder_init:
6545         kfree(intel_connector);
6546 err_connector_alloc:
6547         kfree(intel_dig_port);
6548         return false;
6549 }
6550
6551 void intel_dp_mst_suspend(struct drm_device *dev)
6552 {
6553         struct drm_i915_private *dev_priv = to_i915(dev);
6554         int i;
6555
6556         /* disable MST */
6557         for (i = 0; i < I915_MAX_PORTS; i++) {
6558                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6559
6560                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6561                         continue;
6562
6563                 if (intel_dig_port->dp.is_mst)
6564                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6565         }
6566 }
6567
6568 void intel_dp_mst_resume(struct drm_device *dev)
6569 {
6570         struct drm_i915_private *dev_priv = to_i915(dev);
6571         int i;
6572
6573         for (i = 0; i < I915_MAX_PORTS; i++) {
6574                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6575                 int ret;
6576
6577                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6578                         continue;
6579
6580                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6581                 if (ret)
6582                         intel_dp_check_mst_status(&intel_dig_port->dp);
6583         }
6584 }