2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
74 static bool is_edp(struct intel_dp *intel_dp)
76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
85 return intel_dig_port->base.base.dev;
88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
93 static void intel_dp_link_down(struct intel_dp *intel_dp);
94 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
95 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
98 intel_dp_max_link_bw(struct intel_dp *intel_dp)
100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
112 max_link_bw = DP_LINK_BW_2_7;
115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw = DP_LINK_BW_1_62;
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 * 270000 * 1 * 8 / 10 == 216000
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
141 intel_dp_link_required(int pixel_clock, int bpp)
143 return (pixel_clock * bpp + 9) / 10;
147 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149 return (max_link_clock * max_lanes * 8) / 10;
152 static enum drm_mode_status
153 intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
156 struct intel_dp *intel_dp = intel_attached_dp(connector);
157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
166 if (mode->vdisplay > fixed_mode->vdisplay)
169 target_clock = fixed_mode->clock;
172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
178 if (mode_rate > max_rate)
179 return MODE_CLOCK_HIGH;
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
191 pack_aux(uint8_t *src, int src_bytes)
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
204 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
213 /* hrawclock is 1/4 the FSB frequency */
215 intel_hrawclk(struct drm_device *dev)
217 struct drm_i915_private *dev_priv = dev->dev_private;
220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
234 case CLKCFG_FSB_1067:
236 case CLKCFG_FSB_1333:
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
248 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
252 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
257 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
266 /* modeset should have pipe */
268 return to_intel_crtc(crtc)->pipe;
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
284 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
294 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
304 static bool edp_have_panel_power(struct intel_dp *intel_dp)
306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 struct drm_i915_private *dev_priv = dev->dev_private;
309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
312 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 struct drm_i915_private *dev_priv = dev->dev_private;
317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
322 intel_dp_check_edp(struct intel_dp *intel_dp)
324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 if (!is_edp(intel_dp))
330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
339 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
348 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
351 msecs_to_jiffies_timeout(10));
353 done = wait_for_atomic(C, 10) == 0;
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
362 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
371 return index ? 0 : intel_hrawclk(dev) / 2;
374 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
386 return 225; /* eDP input clock at 450Mhz */
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
392 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
398 if (intel_dig_port->port == PORT_A) {
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
414 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
416 return index ? 0 : 100;
419 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
422 uint32_t aux_clock_divider)
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
438 return DP_AUX_CH_CTL_SEND_BUSY |
440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
443 DP_AUX_CH_CTL_RECEIVE_ERROR |
444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
450 intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
459 uint32_t aux_clock_divider;
460 int i, ret, recv_bytes;
463 bool has_aux_irq = HAS_AUX_IRQ(dev);
466 vdd = _edp_panel_vdd_on(intel_dp);
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
474 intel_dp_check_edp(intel_dp);
476 intel_aux_display_runtime_get(dev_priv);
478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
480 status = I915_READ_NOTRACE(ch_ctl);
481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
512 /* Send the command and wait for it to complete */
513 I915_WRITE(ch_ctl, send_ctl);
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
517 /* Clear done status and any errors */
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
527 if (status & DP_AUX_CH_CTL_DONE)
530 if (status & DP_AUX_CH_CTL_DONE)
534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
570 intel_aux_display_runtime_put(dev_priv);
573 edp_panel_vdd_off(intel_dp, false);
578 #define BARE_ADDRESS_SIZE 3
579 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
581 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
583 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
584 uint8_t txbuf[20], rxbuf[20];
585 size_t txsize, rxsize;
588 txbuf[0] = msg->request << 4;
589 txbuf[1] = msg->address >> 8;
590 txbuf[2] = msg->address & 0xff;
591 txbuf[3] = msg->size - 1;
593 switch (msg->request & ~DP_AUX_I2C_MOT) {
594 case DP_AUX_NATIVE_WRITE:
595 case DP_AUX_I2C_WRITE:
596 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
599 if (WARN_ON(txsize > 20))
602 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
604 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
606 msg->reply = rxbuf[0] >> 4;
608 /* Return payload size. */
613 case DP_AUX_NATIVE_READ:
614 case DP_AUX_I2C_READ:
615 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
616 rxsize = msg->size + 1;
618 if (WARN_ON(rxsize > 20))
621 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
623 msg->reply = rxbuf[0] >> 4;
625 * Assume happy day, and copy the data. The caller is
626 * expected to check msg->reply before touching it.
628 * Return payload size.
631 memcpy(msg->buffer, rxbuf + 1, ret);
644 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
648 enum port port = intel_dig_port->port;
649 const char *name = NULL;
654 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
658 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
662 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
666 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
674 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
676 intel_dp->aux.name = name;
677 intel_dp->aux.dev = dev->dev;
678 intel_dp->aux.transfer = intel_dp_aux_transfer;
680 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
681 connector->base.kdev->kobj.name);
683 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
685 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
690 ret = sysfs_create_link(&connector->base.kdev->kobj,
691 &intel_dp->aux.ddc.dev.kobj,
692 intel_dp->aux.ddc.dev.kobj.name);
694 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
695 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
700 intel_dp_connector_unregister(struct intel_connector *intel_connector)
702 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
704 sysfs_remove_link(&intel_connector->base.kdev->kobj,
705 intel_dp->aux.ddc.dev.kobj.name);
706 intel_connector_unregister(intel_connector);
710 intel_dp_set_clock(struct intel_encoder *encoder,
711 struct intel_crtc_config *pipe_config, int link_bw)
713 struct drm_device *dev = encoder->base.dev;
714 const struct dp_link_dpll *divisor = NULL;
719 count = ARRAY_SIZE(gen4_dpll);
720 } else if (IS_HASWELL(dev)) {
721 /* Haswell has special-purpose DP DDI clocks. */
722 } else if (HAS_PCH_SPLIT(dev)) {
724 count = ARRAY_SIZE(pch_dpll);
725 } else if (IS_VALLEYVIEW(dev)) {
727 count = ARRAY_SIZE(vlv_dpll);
730 if (divisor && count) {
731 for (i = 0; i < count; i++) {
732 if (link_bw == divisor[i].link_bw) {
733 pipe_config->dpll = divisor[i].dpll;
734 pipe_config->clock_set = true;
742 intel_dp_compute_config(struct intel_encoder *encoder,
743 struct intel_crtc_config *pipe_config)
745 struct drm_device *dev = encoder->base.dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
748 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
749 enum port port = dp_to_dig_port(intel_dp)->port;
750 struct intel_crtc *intel_crtc = encoder->new_crtc;
751 struct intel_connector *intel_connector = intel_dp->attached_connector;
752 int lane_count, clock;
753 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
754 /* Conveniently, the link BW constants become indices with a shift...*/
755 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
757 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
758 int link_avail, link_clock;
760 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
761 pipe_config->has_pch_encoder = true;
763 pipe_config->has_dp_encoder = true;
765 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
766 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
768 if (!HAS_PCH_SPLIT(dev))
769 intel_gmch_panel_fitting(intel_crtc, pipe_config,
770 intel_connector->panel.fitting_mode);
772 intel_pch_panel_fitting(intel_crtc, pipe_config,
773 intel_connector->panel.fitting_mode);
776 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
779 DRM_DEBUG_KMS("DP link computation with max lane count %i "
780 "max bw %02x pixel clock %iKHz\n",
781 max_lane_count, bws[max_clock],
782 adjusted_mode->crtc_clock);
784 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
786 bpp = pipe_config->pipe_bpp;
787 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
788 dev_priv->vbt.edp_bpp < bpp) {
789 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
790 dev_priv->vbt.edp_bpp);
791 bpp = dev_priv->vbt.edp_bpp;
794 for (; bpp >= 6*3; bpp -= 2*3) {
795 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
798 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
799 for (clock = 0; clock <= max_clock; clock++) {
800 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
801 link_avail = intel_dp_max_data_rate(link_clock,
804 if (mode_rate <= link_avail) {
814 if (intel_dp->color_range_auto) {
817 * CEA-861-E - 5.1 Default Encoding Parameters
818 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
820 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
821 intel_dp->color_range = DP_COLOR_RANGE_16_235;
823 intel_dp->color_range = 0;
826 if (intel_dp->color_range)
827 pipe_config->limited_color_range = true;
829 intel_dp->link_bw = bws[clock];
830 intel_dp->lane_count = lane_count;
831 pipe_config->pipe_bpp = bpp;
832 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
834 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
835 intel_dp->link_bw, intel_dp->lane_count,
836 pipe_config->port_clock, bpp);
837 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
838 mode_rate, link_avail);
840 intel_link_compute_m_n(bpp, lane_count,
841 adjusted_mode->crtc_clock,
842 pipe_config->port_clock,
843 &pipe_config->dp_m_n);
845 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
850 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
852 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
853 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
854 struct drm_device *dev = crtc->base.dev;
855 struct drm_i915_private *dev_priv = dev->dev_private;
858 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
859 dpa_ctl = I915_READ(DP_A);
860 dpa_ctl &= ~DP_PLL_FREQ_MASK;
862 if (crtc->config.port_clock == 162000) {
863 /* For a long time we've carried around a ILK-DevA w/a for the
864 * 160MHz clock. If we're really unlucky, it's still required.
866 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
867 dpa_ctl |= DP_PLL_FREQ_160MHZ;
868 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
870 dpa_ctl |= DP_PLL_FREQ_270MHZ;
871 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
874 I915_WRITE(DP_A, dpa_ctl);
880 static void intel_dp_mode_set(struct intel_encoder *encoder)
882 struct drm_device *dev = encoder->base.dev;
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
885 enum port port = dp_to_dig_port(intel_dp)->port;
886 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
887 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
890 * There are four kinds of DP registers:
897 * IBX PCH and CPU are the same for almost everything,
898 * except that the CPU DP PLL is configured in this
901 * CPT PCH is quite different, having many bits moved
902 * to the TRANS_DP_CTL register instead. That
903 * configuration happens (oddly) in ironlake_pch_enable
906 /* Preserve the BIOS-computed detected bit. This is
907 * supposed to be read-only.
909 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
911 /* Handle DP bits in common between all three register formats */
912 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
913 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
915 if (intel_dp->has_audio) {
916 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
917 pipe_name(crtc->pipe));
918 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
919 intel_write_eld(&encoder->base, adjusted_mode);
922 /* Split out the IBX/CPU vs CPT settings */
924 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
925 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
926 intel_dp->DP |= DP_SYNC_HS_HIGH;
927 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
928 intel_dp->DP |= DP_SYNC_VS_HIGH;
929 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
931 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
932 intel_dp->DP |= DP_ENHANCED_FRAMING;
934 intel_dp->DP |= crtc->pipe << 29;
935 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
936 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
937 intel_dp->DP |= intel_dp->color_range;
939 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
940 intel_dp->DP |= DP_SYNC_HS_HIGH;
941 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
942 intel_dp->DP |= DP_SYNC_VS_HIGH;
943 intel_dp->DP |= DP_LINK_TRAIN_OFF;
945 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
946 intel_dp->DP |= DP_ENHANCED_FRAMING;
949 intel_dp->DP |= DP_PIPEB_SELECT;
951 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
954 if (port == PORT_A && !IS_VALLEYVIEW(dev))
955 ironlake_set_pll_cpu_edp(intel_dp);
958 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
959 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
961 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
962 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
964 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
965 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
967 static void wait_panel_status(struct intel_dp *intel_dp,
971 struct drm_device *dev = intel_dp_to_dev(intel_dp);
972 struct drm_i915_private *dev_priv = dev->dev_private;
973 u32 pp_stat_reg, pp_ctrl_reg;
975 pp_stat_reg = _pp_stat_reg(intel_dp);
976 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
978 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
980 I915_READ(pp_stat_reg),
981 I915_READ(pp_ctrl_reg));
983 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
984 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
985 I915_READ(pp_stat_reg),
986 I915_READ(pp_ctrl_reg));
989 DRM_DEBUG_KMS("Wait complete\n");
992 static void wait_panel_on(struct intel_dp *intel_dp)
994 DRM_DEBUG_KMS("Wait for panel power on\n");
995 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
998 static void wait_panel_off(struct intel_dp *intel_dp)
1000 DRM_DEBUG_KMS("Wait for panel power off time\n");
1001 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1004 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1006 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1008 /* When we disable the VDD override bit last we have to do the manual
1010 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1011 intel_dp->panel_power_cycle_delay);
1013 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1016 static void wait_backlight_on(struct intel_dp *intel_dp)
1018 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1019 intel_dp->backlight_on_delay);
1022 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1024 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1025 intel_dp->backlight_off_delay);
1028 /* Read the current pp_control value, unlocking the register if it
1032 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1038 control = I915_READ(_pp_ctrl_reg(intel_dp));
1039 control &= ~PANEL_UNLOCK_MASK;
1040 control |= PANEL_UNLOCK_REGS;
1044 static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1046 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1049 u32 pp_stat_reg, pp_ctrl_reg;
1050 bool need_to_disable = !intel_dp->want_panel_vdd;
1052 if (!is_edp(intel_dp))
1055 intel_dp->want_panel_vdd = true;
1057 if (edp_have_panel_vdd(intel_dp))
1058 return need_to_disable;
1060 intel_runtime_pm_get(dev_priv);
1062 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1064 if (!edp_have_panel_power(intel_dp))
1065 wait_panel_power_cycle(intel_dp);
1067 pp = ironlake_get_pp_control(intel_dp);
1068 pp |= EDP_FORCE_VDD;
1070 pp_stat_reg = _pp_stat_reg(intel_dp);
1071 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1073 I915_WRITE(pp_ctrl_reg, pp);
1074 POSTING_READ(pp_ctrl_reg);
1075 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1076 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1078 * If the panel wasn't on, delay before accessing aux channel
1080 if (!edp_have_panel_power(intel_dp)) {
1081 DRM_DEBUG_KMS("eDP was not running\n");
1082 msleep(intel_dp->panel_power_up_delay);
1085 return need_to_disable;
1088 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1090 if (is_edp(intel_dp)) {
1091 bool vdd = _edp_panel_vdd_on(intel_dp);
1093 WARN(!vdd, "eDP VDD already requested on\n");
1097 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1099 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1100 struct drm_i915_private *dev_priv = dev->dev_private;
1102 u32 pp_stat_reg, pp_ctrl_reg;
1104 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1106 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1107 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1109 pp = ironlake_get_pp_control(intel_dp);
1110 pp &= ~EDP_FORCE_VDD;
1112 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1113 pp_stat_reg = _pp_stat_reg(intel_dp);
1115 I915_WRITE(pp_ctrl_reg, pp);
1116 POSTING_READ(pp_ctrl_reg);
1118 /* Make sure sequencer is idle before allowing subsequent activity */
1119 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1120 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1122 if ((pp & POWER_TARGET_ON) == 0)
1123 intel_dp->last_power_cycle = jiffies;
1125 intel_runtime_pm_put(dev_priv);
1129 static void edp_panel_vdd_work(struct work_struct *__work)
1131 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1132 struct intel_dp, panel_vdd_work);
1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1135 mutex_lock(&dev->mode_config.mutex);
1136 edp_panel_vdd_off_sync(intel_dp);
1137 mutex_unlock(&dev->mode_config.mutex);
1140 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1142 if (!is_edp(intel_dp))
1145 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1147 intel_dp->want_panel_vdd = false;
1150 edp_panel_vdd_off_sync(intel_dp);
1153 * Queue the timer to fire a long
1154 * time from now (relative to the power down delay)
1155 * to keep the panel power up across a sequence of operations
1157 schedule_delayed_work(&intel_dp->panel_vdd_work,
1158 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1162 void intel_edp_panel_on(struct intel_dp *intel_dp)
1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1169 if (!is_edp(intel_dp))
1172 DRM_DEBUG_KMS("Turn eDP power on\n");
1174 if (edp_have_panel_power(intel_dp)) {
1175 DRM_DEBUG_KMS("eDP power already on\n");
1179 wait_panel_power_cycle(intel_dp);
1181 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1182 pp = ironlake_get_pp_control(intel_dp);
1184 /* ILK workaround: disable reset around power sequence */
1185 pp &= ~PANEL_POWER_RESET;
1186 I915_WRITE(pp_ctrl_reg, pp);
1187 POSTING_READ(pp_ctrl_reg);
1190 pp |= POWER_TARGET_ON;
1192 pp |= PANEL_POWER_RESET;
1194 I915_WRITE(pp_ctrl_reg, pp);
1195 POSTING_READ(pp_ctrl_reg);
1197 wait_panel_on(intel_dp);
1198 intel_dp->last_power_on = jiffies;
1201 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1202 I915_WRITE(pp_ctrl_reg, pp);
1203 POSTING_READ(pp_ctrl_reg);
1207 void intel_edp_panel_off(struct intel_dp *intel_dp)
1209 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1214 if (!is_edp(intel_dp))
1217 DRM_DEBUG_KMS("Turn eDP power off\n");
1219 edp_wait_backlight_off(intel_dp);
1221 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1223 pp = ironlake_get_pp_control(intel_dp);
1224 /* We need to switch off panel power _and_ force vdd, for otherwise some
1225 * panels get very unhappy and cease to work. */
1226 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1229 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1231 intel_dp->want_panel_vdd = false;
1233 I915_WRITE(pp_ctrl_reg, pp);
1234 POSTING_READ(pp_ctrl_reg);
1236 intel_dp->last_power_cycle = jiffies;
1237 wait_panel_off(intel_dp);
1239 /* We got a reference when we enabled the VDD. */
1240 intel_runtime_pm_put(dev_priv);
1243 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246 struct drm_device *dev = intel_dig_port->base.base.dev;
1247 struct drm_i915_private *dev_priv = dev->dev_private;
1251 if (!is_edp(intel_dp))
1254 DRM_DEBUG_KMS("\n");
1256 * If we enable the backlight right away following a panel power
1257 * on, we may see slight flicker as the panel syncs with the eDP
1258 * link. So delay a bit to make sure the image is solid before
1259 * allowing it to appear.
1261 wait_backlight_on(intel_dp);
1262 pp = ironlake_get_pp_control(intel_dp);
1263 pp |= EDP_BLC_ENABLE;
1265 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1267 I915_WRITE(pp_ctrl_reg, pp);
1268 POSTING_READ(pp_ctrl_reg);
1270 intel_panel_enable_backlight(intel_dp->attached_connector);
1273 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1280 if (!is_edp(intel_dp))
1283 intel_panel_disable_backlight(intel_dp->attached_connector);
1285 DRM_DEBUG_KMS("\n");
1286 pp = ironlake_get_pp_control(intel_dp);
1287 pp &= ~EDP_BLC_ENABLE;
1289 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
1293 intel_dp->last_backlight_off = jiffies;
1296 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1299 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1300 struct drm_device *dev = crtc->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1304 assert_pipe_disabled(dev_priv,
1305 to_intel_crtc(crtc)->pipe);
1307 DRM_DEBUG_KMS("\n");
1308 dpa_ctl = I915_READ(DP_A);
1309 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1310 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1312 /* We don't adjust intel_dp->DP while tearing down the link, to
1313 * facilitate link retraining (e.g. after hotplug). Hence clear all
1314 * enable bits here to ensure that we don't enable too much. */
1315 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1316 intel_dp->DP |= DP_PLL_ENABLE;
1317 I915_WRITE(DP_A, intel_dp->DP);
1322 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1325 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1326 struct drm_device *dev = crtc->dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1330 assert_pipe_disabled(dev_priv,
1331 to_intel_crtc(crtc)->pipe);
1333 dpa_ctl = I915_READ(DP_A);
1334 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1335 "dp pll off, should be on\n");
1336 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1338 /* We can't rely on the value tracked for the DP register in
1339 * intel_dp->DP because link_down must not change that (otherwise link
1340 * re-training will fail. */
1341 dpa_ctl &= ~DP_PLL_ENABLE;
1342 I915_WRITE(DP_A, dpa_ctl);
1347 /* If the sink supports it, try to set the power state appropriately */
1348 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1352 /* Should have a valid DPCD by this point */
1353 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1356 if (mode != DRM_MODE_DPMS_ON) {
1357 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1360 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1363 * When turning on, we need to retry for 1ms to give the sink
1366 for (i = 0; i < 3; i++) {
1367 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1376 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1379 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380 enum port port = dp_to_dig_port(intel_dp)->port;
1381 struct drm_device *dev = encoder->base.dev;
1382 struct drm_i915_private *dev_priv = dev->dev_private;
1383 enum intel_display_power_domain power_domain;
1386 power_domain = intel_display_port_power_domain(encoder);
1387 if (!intel_display_power_enabled(dev_priv, power_domain))
1390 tmp = I915_READ(intel_dp->output_reg);
1392 if (!(tmp & DP_PORT_EN))
1395 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1396 *pipe = PORT_TO_PIPE_CPT(tmp);
1397 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1398 *pipe = PORT_TO_PIPE(tmp);
1404 switch (intel_dp->output_reg) {
1406 trans_sel = TRANS_DP_PORT_SEL_B;
1409 trans_sel = TRANS_DP_PORT_SEL_C;
1412 trans_sel = TRANS_DP_PORT_SEL_D;
1419 trans_dp = I915_READ(TRANS_DP_CTL(i));
1420 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1426 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1427 intel_dp->output_reg);
1433 static void intel_dp_get_config(struct intel_encoder *encoder,
1434 struct intel_crtc_config *pipe_config)
1436 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1438 struct drm_device *dev = encoder->base.dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440 enum port port = dp_to_dig_port(intel_dp)->port;
1441 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1444 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1445 tmp = I915_READ(intel_dp->output_reg);
1446 if (tmp & DP_SYNC_HS_HIGH)
1447 flags |= DRM_MODE_FLAG_PHSYNC;
1449 flags |= DRM_MODE_FLAG_NHSYNC;
1451 if (tmp & DP_SYNC_VS_HIGH)
1452 flags |= DRM_MODE_FLAG_PVSYNC;
1454 flags |= DRM_MODE_FLAG_NVSYNC;
1456 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1457 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1458 flags |= DRM_MODE_FLAG_PHSYNC;
1460 flags |= DRM_MODE_FLAG_NHSYNC;
1462 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1463 flags |= DRM_MODE_FLAG_PVSYNC;
1465 flags |= DRM_MODE_FLAG_NVSYNC;
1468 pipe_config->adjusted_mode.flags |= flags;
1470 pipe_config->has_dp_encoder = true;
1472 intel_dp_get_m_n(crtc, pipe_config);
1474 if (port == PORT_A) {
1475 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1476 pipe_config->port_clock = 162000;
1478 pipe_config->port_clock = 270000;
1481 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1482 &pipe_config->dp_m_n);
1484 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1485 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1487 pipe_config->adjusted_mode.crtc_clock = dotclock;
1489 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1490 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1492 * This is a big fat ugly hack.
1494 * Some machines in UEFI boot mode provide us a VBT that has 18
1495 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1496 * unknown we fail to light up. Yet the same BIOS boots up with
1497 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1498 * max, not what it tells us to use.
1500 * Note: This will still be broken if the eDP panel is not lit
1501 * up by the BIOS, and thus we can't get the mode at module
1504 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1505 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1506 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1510 static bool is_edp_psr(struct drm_device *dev)
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1514 return dev_priv->psr.sink_support;
1517 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1524 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1527 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1528 struct edp_vsc_psr *vsc_psr)
1530 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1531 struct drm_device *dev = dig_port->base.base.dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1534 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1535 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1536 uint32_t *data = (uint32_t *) vsc_psr;
1539 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1540 the video DIP being updated before program video DIP data buffer
1541 registers for DIP being updated. */
1542 I915_WRITE(ctl_reg, 0);
1543 POSTING_READ(ctl_reg);
1545 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1546 if (i < sizeof(struct edp_vsc_psr))
1547 I915_WRITE(data_reg + i, *data++);
1549 I915_WRITE(data_reg + i, 0);
1552 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1553 POSTING_READ(ctl_reg);
1556 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 struct edp_vsc_psr psr_vsc;
1562 if (intel_dp->psr_setup_done)
1565 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1566 memset(&psr_vsc, 0, sizeof(psr_vsc));
1567 psr_vsc.sdp_header.HB0 = 0;
1568 psr_vsc.sdp_header.HB1 = 0x7;
1569 psr_vsc.sdp_header.HB2 = 0x2;
1570 psr_vsc.sdp_header.HB3 = 0x8;
1571 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1573 /* Avoid continuous PSR exit by masking memup and hpd */
1574 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1575 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1577 intel_dp->psr_setup_done = true;
1580 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1582 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 uint32_t aux_clock_divider;
1585 int precharge = 0x3;
1586 int msg_size = 5; /* Header(4) + Message(1) */
1588 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1590 /* Enable PSR in sink */
1591 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1592 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1593 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1595 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1596 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1598 /* Setup AUX registers */
1599 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1600 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1601 I915_WRITE(EDP_PSR_AUX_CTL(dev),
1602 DP_AUX_CH_CTL_TIME_OUT_400us |
1603 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1604 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1605 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1608 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1610 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 uint32_t max_sleep_time = 0x1f;
1613 uint32_t idle_frames = 1;
1615 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1617 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1618 val |= EDP_PSR_LINK_STANDBY;
1619 val |= EDP_PSR_TP2_TP3_TIME_0us;
1620 val |= EDP_PSR_TP1_TIME_0us;
1621 val |= EDP_PSR_SKIP_AUX_EXIT;
1623 val |= EDP_PSR_LINK_DISABLE;
1625 I915_WRITE(EDP_PSR_CTL(dev), val |
1626 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1627 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1628 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1632 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1634 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1635 struct drm_device *dev = dig_port->base.base.dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct drm_crtc *crtc = dig_port->base.base.crtc;
1638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1639 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1640 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1642 dev_priv->psr.source_ok = false;
1644 if (!HAS_PSR(dev)) {
1645 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1649 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1650 (dig_port->port != PORT_A)) {
1651 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1655 if (!i915.enable_psr) {
1656 DRM_DEBUG_KMS("PSR disable by flag\n");
1660 crtc = dig_port->base.base.crtc;
1662 DRM_DEBUG_KMS("crtc not active for PSR\n");
1666 intel_crtc = to_intel_crtc(crtc);
1667 if (!intel_crtc_active(crtc)) {
1668 DRM_DEBUG_KMS("crtc not active for PSR\n");
1672 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1673 if (obj->tiling_mode != I915_TILING_X ||
1674 obj->fence_reg == I915_FENCE_REG_NONE) {
1675 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1679 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1680 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1684 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1686 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1690 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1691 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1695 dev_priv->psr.source_ok = true;
1699 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1703 if (!intel_edp_psr_match_conditions(intel_dp) ||
1704 intel_edp_is_psr_enabled(dev))
1707 /* Setup PSR once */
1708 intel_edp_psr_setup(intel_dp);
1710 /* Enable PSR on the panel */
1711 intel_edp_psr_enable_sink(intel_dp);
1713 /* Enable PSR on the host */
1714 intel_edp_psr_enable_source(intel_dp);
1717 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1721 if (intel_edp_psr_match_conditions(intel_dp) &&
1722 !intel_edp_is_psr_enabled(dev))
1723 intel_edp_psr_do_enable(intel_dp);
1726 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1728 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1731 if (!intel_edp_is_psr_enabled(dev))
1734 I915_WRITE(EDP_PSR_CTL(dev),
1735 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1737 /* Wait till PSR is idle */
1738 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1739 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1740 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1743 void intel_edp_psr_update(struct drm_device *dev)
1745 struct intel_encoder *encoder;
1746 struct intel_dp *intel_dp = NULL;
1748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1749 if (encoder->type == INTEL_OUTPUT_EDP) {
1750 intel_dp = enc_to_intel_dp(&encoder->base);
1752 if (!is_edp_psr(dev))
1755 if (!intel_edp_psr_match_conditions(intel_dp))
1756 intel_edp_psr_disable(intel_dp);
1758 if (!intel_edp_is_psr_enabled(dev))
1759 intel_edp_psr_do_enable(intel_dp);
1763 static void intel_disable_dp(struct intel_encoder *encoder)
1765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1766 enum port port = dp_to_dig_port(intel_dp)->port;
1767 struct drm_device *dev = encoder->base.dev;
1769 /* Make sure the panel is off before trying to change the mode. But also
1770 * ensure that we have vdd while we switch off the panel. */
1771 intel_edp_panel_vdd_on(intel_dp);
1772 intel_edp_backlight_off(intel_dp);
1773 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1774 intel_edp_panel_off(intel_dp);
1776 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1777 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1778 intel_dp_link_down(intel_dp);
1781 static void intel_post_disable_dp(struct intel_encoder *encoder)
1783 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1784 enum port port = dp_to_dig_port(intel_dp)->port;
1785 struct drm_device *dev = encoder->base.dev;
1787 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1788 intel_dp_link_down(intel_dp);
1789 if (!IS_VALLEYVIEW(dev))
1790 ironlake_edp_pll_off(intel_dp);
1794 static void intel_enable_dp(struct intel_encoder *encoder)
1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1797 struct drm_device *dev = encoder->base.dev;
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1801 if (WARN_ON(dp_reg & DP_PORT_EN))
1804 intel_edp_panel_vdd_on(intel_dp);
1805 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1806 intel_dp_start_link_train(intel_dp);
1807 intel_edp_panel_on(intel_dp);
1808 edp_panel_vdd_off(intel_dp, true);
1809 intel_dp_complete_link_train(intel_dp);
1810 intel_dp_stop_link_train(intel_dp);
1813 static void g4x_enable_dp(struct intel_encoder *encoder)
1815 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1817 intel_enable_dp(encoder);
1818 intel_edp_backlight_on(intel_dp);
1821 static void vlv_enable_dp(struct intel_encoder *encoder)
1823 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1825 intel_edp_backlight_on(intel_dp);
1828 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1830 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1831 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1833 if (dport->port == PORT_A)
1834 ironlake_edp_pll_on(intel_dp);
1837 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1839 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1840 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1841 struct drm_device *dev = encoder->base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1844 enum dpio_channel port = vlv_dport_to_channel(dport);
1845 int pipe = intel_crtc->pipe;
1846 struct edp_power_seq power_seq;
1849 mutex_lock(&dev_priv->dpio_lock);
1851 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1858 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1859 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1860 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1862 mutex_unlock(&dev_priv->dpio_lock);
1864 if (is_edp(intel_dp)) {
1865 /* init power sequencer on this pipe and port */
1866 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1867 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1871 intel_enable_dp(encoder);
1873 vlv_wait_port_ready(dev_priv, dport);
1876 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1878 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1879 struct drm_device *dev = encoder->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_crtc *intel_crtc =
1882 to_intel_crtc(encoder->base.crtc);
1883 enum dpio_channel port = vlv_dport_to_channel(dport);
1884 int pipe = intel_crtc->pipe;
1886 /* Program Tx lane resets to default */
1887 mutex_lock(&dev_priv->dpio_lock);
1888 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1889 DPIO_PCS_TX_LANE2_RESET |
1890 DPIO_PCS_TX_LANE1_RESET);
1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1892 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1893 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1894 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1895 DPIO_PCS_CLK_SOFT_RESET);
1897 /* Fix up inter-pair skew failure */
1898 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1899 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1900 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1901 mutex_unlock(&dev_priv->dpio_lock);
1905 * Native read with retry for link status and receiver capability reads for
1906 * cases where the sink may still be asleep.
1908 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1909 * supposed to retry 3 times per the spec.
1912 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1913 void *buffer, size_t size)
1918 for (i = 0; i < 3; i++) {
1919 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1929 * Fetch AUX CH registers 0x202 - 0x207 which contain
1930 * link status information
1933 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1935 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1938 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1942 * These are source-specific values; current Intel hardware supports
1943 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1947 intel_dp_voltage_max(struct intel_dp *intel_dp)
1949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1950 enum port port = dp_to_dig_port(intel_dp)->port;
1952 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1953 return DP_TRAIN_VOLTAGE_SWING_1200;
1954 else if (IS_GEN7(dev) && port == PORT_A)
1955 return DP_TRAIN_VOLTAGE_SWING_800;
1956 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1957 return DP_TRAIN_VOLTAGE_SWING_1200;
1959 return DP_TRAIN_VOLTAGE_SWING_800;
1963 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1965 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1966 enum port port = dp_to_dig_port(intel_dp)->port;
1968 if (IS_BROADWELL(dev)) {
1969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1970 case DP_TRAIN_VOLTAGE_SWING_400:
1971 case DP_TRAIN_VOLTAGE_SWING_600:
1972 return DP_TRAIN_PRE_EMPHASIS_6;
1973 case DP_TRAIN_VOLTAGE_SWING_800:
1974 return DP_TRAIN_PRE_EMPHASIS_3_5;
1975 case DP_TRAIN_VOLTAGE_SWING_1200:
1977 return DP_TRAIN_PRE_EMPHASIS_0;
1979 } else if (IS_HASWELL(dev)) {
1980 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1981 case DP_TRAIN_VOLTAGE_SWING_400:
1982 return DP_TRAIN_PRE_EMPHASIS_9_5;
1983 case DP_TRAIN_VOLTAGE_SWING_600:
1984 return DP_TRAIN_PRE_EMPHASIS_6;
1985 case DP_TRAIN_VOLTAGE_SWING_800:
1986 return DP_TRAIN_PRE_EMPHASIS_3_5;
1987 case DP_TRAIN_VOLTAGE_SWING_1200:
1989 return DP_TRAIN_PRE_EMPHASIS_0;
1991 } else if (IS_VALLEYVIEW(dev)) {
1992 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1993 case DP_TRAIN_VOLTAGE_SWING_400:
1994 return DP_TRAIN_PRE_EMPHASIS_9_5;
1995 case DP_TRAIN_VOLTAGE_SWING_600:
1996 return DP_TRAIN_PRE_EMPHASIS_6;
1997 case DP_TRAIN_VOLTAGE_SWING_800:
1998 return DP_TRAIN_PRE_EMPHASIS_3_5;
1999 case DP_TRAIN_VOLTAGE_SWING_1200:
2001 return DP_TRAIN_PRE_EMPHASIS_0;
2003 } else if (IS_GEN7(dev) && port == PORT_A) {
2004 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2005 case DP_TRAIN_VOLTAGE_SWING_400:
2006 return DP_TRAIN_PRE_EMPHASIS_6;
2007 case DP_TRAIN_VOLTAGE_SWING_600:
2008 case DP_TRAIN_VOLTAGE_SWING_800:
2009 return DP_TRAIN_PRE_EMPHASIS_3_5;
2011 return DP_TRAIN_PRE_EMPHASIS_0;
2014 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2015 case DP_TRAIN_VOLTAGE_SWING_400:
2016 return DP_TRAIN_PRE_EMPHASIS_6;
2017 case DP_TRAIN_VOLTAGE_SWING_600:
2018 return DP_TRAIN_PRE_EMPHASIS_6;
2019 case DP_TRAIN_VOLTAGE_SWING_800:
2020 return DP_TRAIN_PRE_EMPHASIS_3_5;
2021 case DP_TRAIN_VOLTAGE_SWING_1200:
2023 return DP_TRAIN_PRE_EMPHASIS_0;
2028 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2033 struct intel_crtc *intel_crtc =
2034 to_intel_crtc(dport->base.base.crtc);
2035 unsigned long demph_reg_value, preemph_reg_value,
2036 uniqtranscale_reg_value;
2037 uint8_t train_set = intel_dp->train_set[0];
2038 enum dpio_channel port = vlv_dport_to_channel(dport);
2039 int pipe = intel_crtc->pipe;
2041 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2042 case DP_TRAIN_PRE_EMPHASIS_0:
2043 preemph_reg_value = 0x0004000;
2044 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2045 case DP_TRAIN_VOLTAGE_SWING_400:
2046 demph_reg_value = 0x2B405555;
2047 uniqtranscale_reg_value = 0x552AB83A;
2049 case DP_TRAIN_VOLTAGE_SWING_600:
2050 demph_reg_value = 0x2B404040;
2051 uniqtranscale_reg_value = 0x5548B83A;
2053 case DP_TRAIN_VOLTAGE_SWING_800:
2054 demph_reg_value = 0x2B245555;
2055 uniqtranscale_reg_value = 0x5560B83A;
2057 case DP_TRAIN_VOLTAGE_SWING_1200:
2058 demph_reg_value = 0x2B405555;
2059 uniqtranscale_reg_value = 0x5598DA3A;
2065 case DP_TRAIN_PRE_EMPHASIS_3_5:
2066 preemph_reg_value = 0x0002000;
2067 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2068 case DP_TRAIN_VOLTAGE_SWING_400:
2069 demph_reg_value = 0x2B404040;
2070 uniqtranscale_reg_value = 0x5552B83A;
2072 case DP_TRAIN_VOLTAGE_SWING_600:
2073 demph_reg_value = 0x2B404848;
2074 uniqtranscale_reg_value = 0x5580B83A;
2076 case DP_TRAIN_VOLTAGE_SWING_800:
2077 demph_reg_value = 0x2B404040;
2078 uniqtranscale_reg_value = 0x55ADDA3A;
2084 case DP_TRAIN_PRE_EMPHASIS_6:
2085 preemph_reg_value = 0x0000000;
2086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2087 case DP_TRAIN_VOLTAGE_SWING_400:
2088 demph_reg_value = 0x2B305555;
2089 uniqtranscale_reg_value = 0x5570B83A;
2091 case DP_TRAIN_VOLTAGE_SWING_600:
2092 demph_reg_value = 0x2B2B4040;
2093 uniqtranscale_reg_value = 0x55ADDA3A;
2099 case DP_TRAIN_PRE_EMPHASIS_9_5:
2100 preemph_reg_value = 0x0006000;
2101 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2102 case DP_TRAIN_VOLTAGE_SWING_400:
2103 demph_reg_value = 0x1B405555;
2104 uniqtranscale_reg_value = 0x55ADDA3A;
2114 mutex_lock(&dev_priv->dpio_lock);
2115 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2116 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2118 uniqtranscale_reg_value);
2119 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2120 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2121 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2123 mutex_unlock(&dev_priv->dpio_lock);
2129 intel_get_adjust_train(struct intel_dp *intel_dp,
2130 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2135 uint8_t voltage_max;
2136 uint8_t preemph_max;
2138 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2139 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2140 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2148 voltage_max = intel_dp_voltage_max(intel_dp);
2149 if (v >= voltage_max)
2150 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2152 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2153 if (p >= preemph_max)
2154 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2156 for (lane = 0; lane < 4; lane++)
2157 intel_dp->train_set[lane] = v | p;
2161 intel_gen4_signal_levels(uint8_t train_set)
2163 uint32_t signal_levels = 0;
2165 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2166 case DP_TRAIN_VOLTAGE_SWING_400:
2168 signal_levels |= DP_VOLTAGE_0_4;
2170 case DP_TRAIN_VOLTAGE_SWING_600:
2171 signal_levels |= DP_VOLTAGE_0_6;
2173 case DP_TRAIN_VOLTAGE_SWING_800:
2174 signal_levels |= DP_VOLTAGE_0_8;
2176 case DP_TRAIN_VOLTAGE_SWING_1200:
2177 signal_levels |= DP_VOLTAGE_1_2;
2180 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2181 case DP_TRAIN_PRE_EMPHASIS_0:
2183 signal_levels |= DP_PRE_EMPHASIS_0;
2185 case DP_TRAIN_PRE_EMPHASIS_3_5:
2186 signal_levels |= DP_PRE_EMPHASIS_3_5;
2188 case DP_TRAIN_PRE_EMPHASIS_6:
2189 signal_levels |= DP_PRE_EMPHASIS_6;
2191 case DP_TRAIN_PRE_EMPHASIS_9_5:
2192 signal_levels |= DP_PRE_EMPHASIS_9_5;
2195 return signal_levels;
2198 /* Gen6's DP voltage swing and pre-emphasis control */
2200 intel_gen6_edp_signal_levels(uint8_t train_set)
2202 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2203 DP_TRAIN_PRE_EMPHASIS_MASK);
2204 switch (signal_levels) {
2205 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2206 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2207 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2208 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2209 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2210 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2211 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2212 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2213 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2214 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2215 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2216 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2217 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2218 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2220 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2221 "0x%x\n", signal_levels);
2222 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2226 /* Gen7's DP voltage swing and pre-emphasis control */
2228 intel_gen7_edp_signal_levels(uint8_t train_set)
2230 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2231 DP_TRAIN_PRE_EMPHASIS_MASK);
2232 switch (signal_levels) {
2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2234 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2235 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2236 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2237 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2238 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2240 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2241 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2242 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2243 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2245 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2246 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2247 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2248 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2251 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2252 "0x%x\n", signal_levels);
2253 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2257 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2259 intel_hsw_signal_levels(uint8_t train_set)
2261 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2262 DP_TRAIN_PRE_EMPHASIS_MASK);
2263 switch (signal_levels) {
2264 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2265 return DDI_BUF_EMP_400MV_0DB_HSW;
2266 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2267 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2268 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2269 return DDI_BUF_EMP_400MV_6DB_HSW;
2270 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2271 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2274 return DDI_BUF_EMP_600MV_0DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2277 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2278 return DDI_BUF_EMP_600MV_6DB_HSW;
2280 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2281 return DDI_BUF_EMP_800MV_0DB_HSW;
2282 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2283 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2285 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2286 "0x%x\n", signal_levels);
2287 return DDI_BUF_EMP_400MV_0DB_HSW;
2292 intel_bdw_signal_levels(uint8_t train_set)
2294 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2295 DP_TRAIN_PRE_EMPHASIS_MASK);
2296 switch (signal_levels) {
2297 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2298 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2300 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2301 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2302 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2304 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2305 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2306 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2307 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2308 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2309 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2311 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2313 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2316 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2320 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2321 "0x%x\n", signal_levels);
2322 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2326 /* Properly updates "DP" with the correct signal levels. */
2328 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2330 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2331 enum port port = intel_dig_port->port;
2332 struct drm_device *dev = intel_dig_port->base.base.dev;
2333 uint32_t signal_levels, mask;
2334 uint8_t train_set = intel_dp->train_set[0];
2336 if (IS_BROADWELL(dev)) {
2337 signal_levels = intel_bdw_signal_levels(train_set);
2338 mask = DDI_BUF_EMP_MASK;
2339 } else if (IS_HASWELL(dev)) {
2340 signal_levels = intel_hsw_signal_levels(train_set);
2341 mask = DDI_BUF_EMP_MASK;
2342 } else if (IS_VALLEYVIEW(dev)) {
2343 signal_levels = intel_vlv_signal_levels(intel_dp);
2345 } else if (IS_GEN7(dev) && port == PORT_A) {
2346 signal_levels = intel_gen7_edp_signal_levels(train_set);
2347 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2348 } else if (IS_GEN6(dev) && port == PORT_A) {
2349 signal_levels = intel_gen6_edp_signal_levels(train_set);
2350 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2352 signal_levels = intel_gen4_signal_levels(train_set);
2353 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2356 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2358 *DP = (*DP & ~mask) | signal_levels;
2362 intel_dp_set_link_train(struct intel_dp *intel_dp,
2364 uint8_t dp_train_pat)
2366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2367 struct drm_device *dev = intel_dig_port->base.base.dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 enum port port = intel_dig_port->port;
2370 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2374 uint32_t temp = I915_READ(DP_TP_CTL(port));
2376 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2377 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2379 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2381 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2382 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2383 case DP_TRAINING_PATTERN_DISABLE:
2384 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2387 case DP_TRAINING_PATTERN_1:
2388 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2390 case DP_TRAINING_PATTERN_2:
2391 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2393 case DP_TRAINING_PATTERN_3:
2394 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2397 I915_WRITE(DP_TP_CTL(port), temp);
2399 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2400 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2402 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2403 case DP_TRAINING_PATTERN_DISABLE:
2404 *DP |= DP_LINK_TRAIN_OFF_CPT;
2406 case DP_TRAINING_PATTERN_1:
2407 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2409 case DP_TRAINING_PATTERN_2:
2410 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2412 case DP_TRAINING_PATTERN_3:
2413 DRM_ERROR("DP training pattern 3 not supported\n");
2414 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2419 *DP &= ~DP_LINK_TRAIN_MASK;
2421 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2422 case DP_TRAINING_PATTERN_DISABLE:
2423 *DP |= DP_LINK_TRAIN_OFF;
2425 case DP_TRAINING_PATTERN_1:
2426 *DP |= DP_LINK_TRAIN_PAT_1;
2428 case DP_TRAINING_PATTERN_2:
2429 *DP |= DP_LINK_TRAIN_PAT_2;
2431 case DP_TRAINING_PATTERN_3:
2432 DRM_ERROR("DP training pattern 3 not supported\n");
2433 *DP |= DP_LINK_TRAIN_PAT_2;
2438 I915_WRITE(intel_dp->output_reg, *DP);
2439 POSTING_READ(intel_dp->output_reg);
2441 buf[0] = dp_train_pat;
2442 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2443 DP_TRAINING_PATTERN_DISABLE) {
2444 /* don't write DP_TRAINING_LANEx_SET on disable */
2447 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2448 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2449 len = intel_dp->lane_count + 1;
2452 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2459 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2460 uint8_t dp_train_pat)
2462 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2463 intel_dp_set_signal_levels(intel_dp, DP);
2464 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2468 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2469 const uint8_t link_status[DP_LINK_STATUS_SIZE])
2471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2472 struct drm_device *dev = intel_dig_port->base.base.dev;
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2476 intel_get_adjust_train(intel_dp, link_status);
2477 intel_dp_set_signal_levels(intel_dp, DP);
2479 I915_WRITE(intel_dp->output_reg, *DP);
2480 POSTING_READ(intel_dp->output_reg);
2482 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2483 intel_dp->train_set, intel_dp->lane_count);
2485 return ret == intel_dp->lane_count;
2488 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2490 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2491 struct drm_device *dev = intel_dig_port->base.base.dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 enum port port = intel_dig_port->port;
2499 val = I915_READ(DP_TP_CTL(port));
2500 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2501 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2502 I915_WRITE(DP_TP_CTL(port), val);
2505 * On PORT_A we can have only eDP in SST mode. There the only reason
2506 * we need to set idle transmission mode is to work around a HW issue
2507 * where we enable the pipe while not in idle link-training mode.
2508 * In this case there is requirement to wait for a minimum number of
2509 * idle patterns to be sent.
2514 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2516 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2519 /* Enable corresponding port and start training pattern 1 */
2521 intel_dp_start_link_train(struct intel_dp *intel_dp)
2523 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2524 struct drm_device *dev = encoder->dev;
2527 int voltage_tries, loop_tries;
2528 uint32_t DP = intel_dp->DP;
2529 uint8_t link_config[2];
2532 intel_ddi_prepare_link_retrain(encoder);
2534 /* Write the link configuration data */
2535 link_config[0] = intel_dp->link_bw;
2536 link_config[1] = intel_dp->lane_count;
2537 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2538 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2539 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2542 link_config[1] = DP_SET_ANSI_8B10B;
2543 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2547 /* clock recovery */
2548 if (!intel_dp_reset_link_train(intel_dp, &DP,
2549 DP_TRAINING_PATTERN_1 |
2550 DP_LINK_SCRAMBLING_DISABLE)) {
2551 DRM_ERROR("failed to enable link training\n");
2559 uint8_t link_status[DP_LINK_STATUS_SIZE];
2561 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2562 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2563 DRM_ERROR("failed to get link status\n");
2567 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2568 DRM_DEBUG_KMS("clock recovery OK\n");
2572 /* Check to see if we've tried the max voltage */
2573 for (i = 0; i < intel_dp->lane_count; i++)
2574 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2576 if (i == intel_dp->lane_count) {
2578 if (loop_tries == 5) {
2579 DRM_ERROR("too many full retries, give up\n");
2582 intel_dp_reset_link_train(intel_dp, &DP,
2583 DP_TRAINING_PATTERN_1 |
2584 DP_LINK_SCRAMBLING_DISABLE);
2589 /* Check to see if we've tried the same voltage 5 times */
2590 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2592 if (voltage_tries == 5) {
2593 DRM_ERROR("too many voltage retries, give up\n");
2598 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2600 /* Update training set as requested by target */
2601 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2602 DRM_ERROR("failed to update link training\n");
2611 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2613 bool channel_eq = false;
2614 int tries, cr_tries;
2615 uint32_t DP = intel_dp->DP;
2616 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2618 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2619 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2620 training_pattern = DP_TRAINING_PATTERN_3;
2622 /* channel equalization */
2623 if (!intel_dp_set_link_train(intel_dp, &DP,
2625 DP_LINK_SCRAMBLING_DISABLE)) {
2626 DRM_ERROR("failed to start channel equalization\n");
2634 uint8_t link_status[DP_LINK_STATUS_SIZE];
2637 DRM_ERROR("failed to train DP, aborting\n");
2641 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2642 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2643 DRM_ERROR("failed to get link status\n");
2647 /* Make sure clock is still ok */
2648 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2649 intel_dp_start_link_train(intel_dp);
2650 intel_dp_set_link_train(intel_dp, &DP,
2652 DP_LINK_SCRAMBLING_DISABLE);
2657 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2662 /* Try 5 times, then try clock recovery if that fails */
2664 intel_dp_link_down(intel_dp);
2665 intel_dp_start_link_train(intel_dp);
2666 intel_dp_set_link_train(intel_dp, &DP,
2668 DP_LINK_SCRAMBLING_DISABLE);
2674 /* Update training set as requested by target */
2675 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2676 DRM_ERROR("failed to update link training\n");
2682 intel_dp_set_idle_link_train(intel_dp);
2687 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2691 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2693 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2694 DP_TRAINING_PATTERN_DISABLE);
2698 intel_dp_link_down(struct intel_dp *intel_dp)
2700 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2701 enum port port = intel_dig_port->port;
2702 struct drm_device *dev = intel_dig_port->base.base.dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc =
2705 to_intel_crtc(intel_dig_port->base.base.crtc);
2706 uint32_t DP = intel_dp->DP;
2709 * DDI code has a strict mode set sequence and we should try to respect
2710 * it, otherwise we might hang the machine in many different ways. So we
2711 * really should be disabling the port only on a complete crtc_disable
2712 * sequence. This function is just called under two conditions on DDI
2714 * - Link train failed while doing crtc_enable, and on this case we
2715 * really should respect the mode set sequence and wait for a
2717 * - Someone turned the monitor off and intel_dp_check_link_status
2718 * called us. We don't need to disable the whole port on this case, so
2719 * when someone turns the monitor on again,
2720 * intel_ddi_prepare_link_retrain will take care of redoing the link
2726 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2729 DRM_DEBUG_KMS("\n");
2731 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2732 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2733 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2735 DP &= ~DP_LINK_TRAIN_MASK;
2736 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2738 POSTING_READ(intel_dp->output_reg);
2740 /* We don't really know why we're doing this */
2741 intel_wait_for_vblank(dev, intel_crtc->pipe);
2743 if (HAS_PCH_IBX(dev) &&
2744 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2745 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2747 /* Hardware workaround: leaving our transcoder select
2748 * set to transcoder B while it's off will prevent the
2749 * corresponding HDMI output on transcoder A.
2751 * Combine this with another hardware workaround:
2752 * transcoder select bit can only be cleared while the
2755 DP &= ~DP_PIPEB_SELECT;
2756 I915_WRITE(intel_dp->output_reg, DP);
2758 /* Changes to enable or select take place the vblank
2759 * after being written.
2761 if (WARN_ON(crtc == NULL)) {
2762 /* We should never try to disable a port without a crtc
2763 * attached. For paranoia keep the code around for a
2765 POSTING_READ(intel_dp->output_reg);
2768 intel_wait_for_vblank(dev, intel_crtc->pipe);
2771 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2772 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2773 POSTING_READ(intel_dp->output_reg);
2774 msleep(intel_dp->panel_power_down_delay);
2778 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2780 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2781 struct drm_device *dev = dig_port->base.base.dev;
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2784 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2786 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2787 sizeof(intel_dp->dpcd)) < 0)
2788 return false; /* aux transfer failed */
2790 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2791 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2792 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2794 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2795 return false; /* DPCD not present */
2797 /* Check if the panel supports PSR */
2798 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2799 if (is_edp(intel_dp)) {
2800 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2802 sizeof(intel_dp->psr_dpcd));
2803 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2804 dev_priv->psr.sink_support = true;
2805 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2809 /* Training Pattern 3 support */
2810 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2811 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2812 intel_dp->use_tps3 = true;
2813 DRM_DEBUG_KMS("Displayport TPS3 supported");
2815 intel_dp->use_tps3 = false;
2817 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2818 DP_DWN_STRM_PORT_PRESENT))
2819 return true; /* native DP sink */
2821 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2822 return true; /* no per-port downstream info */
2824 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2825 intel_dp->downstream_ports,
2826 DP_MAX_DOWNSTREAM_PORTS) < 0)
2827 return false; /* downstream port status fetch failed */
2833 intel_dp_probe_oui(struct intel_dp *intel_dp)
2837 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2840 intel_edp_panel_vdd_on(intel_dp);
2842 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2843 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2844 buf[0], buf[1], buf[2]);
2846 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2847 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2848 buf[0], buf[1], buf[2]);
2850 edp_panel_vdd_off(intel_dp, false);
2853 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2855 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2856 struct drm_device *dev = intel_dig_port->base.base.dev;
2857 struct intel_crtc *intel_crtc =
2858 to_intel_crtc(intel_dig_port->base.base.crtc);
2861 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2864 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2867 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2868 DP_TEST_SINK_START) < 0)
2871 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2872 intel_wait_for_vblank(dev, intel_crtc->pipe);
2873 intel_wait_for_vblank(dev, intel_crtc->pipe);
2875 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2878 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2883 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2885 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2886 DP_DEVICE_SERVICE_IRQ_VECTOR,
2887 sink_irq_vector, 1) == 1;
2891 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2893 /* NAK by default */
2894 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2898 * According to DP spec
2901 * 2. Configure link according to Receiver Capabilities
2902 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2903 * 4. Check link status on receipt of hot-plug interrupt
2907 intel_dp_check_link_status(struct intel_dp *intel_dp)
2909 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2911 u8 link_status[DP_LINK_STATUS_SIZE];
2913 if (!intel_encoder->connectors_active)
2916 if (WARN_ON(!intel_encoder->base.crtc))
2919 /* Try to read receiver status if the link appears to be up */
2920 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2924 /* Now read the DPCD to see if it's actually running */
2925 if (!intel_dp_get_dpcd(intel_dp)) {
2929 /* Try to read the source of the interrupt */
2930 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2931 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2932 /* Clear interrupt source */
2933 drm_dp_dpcd_writeb(&intel_dp->aux,
2934 DP_DEVICE_SERVICE_IRQ_VECTOR,
2937 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2938 intel_dp_handle_test_request(intel_dp);
2939 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2940 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2943 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2944 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2945 drm_get_encoder_name(&intel_encoder->base));
2946 intel_dp_start_link_train(intel_dp);
2947 intel_dp_complete_link_train(intel_dp);
2948 intel_dp_stop_link_train(intel_dp);
2952 /* XXX this is probably wrong for multiple downstream ports */
2953 static enum drm_connector_status
2954 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2956 uint8_t *dpcd = intel_dp->dpcd;
2959 if (!intel_dp_get_dpcd(intel_dp))
2960 return connector_status_disconnected;
2962 /* if there's no downstream port, we're done */
2963 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2964 return connector_status_connected;
2966 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2967 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2968 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2971 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2973 return connector_status_unknown;
2975 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2976 : connector_status_disconnected;
2979 /* If no HPD, poke DDC gently */
2980 if (drm_probe_ddc(&intel_dp->aux.ddc))
2981 return connector_status_connected;
2983 /* Well we tried, say unknown for unreliable port types */
2984 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2985 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2986 if (type == DP_DS_PORT_TYPE_VGA ||
2987 type == DP_DS_PORT_TYPE_NON_EDID)
2988 return connector_status_unknown;
2990 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2991 DP_DWN_STRM_PORT_TYPE_MASK;
2992 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2993 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2994 return connector_status_unknown;
2997 /* Anything else is out of spec, warn and ignore */
2998 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2999 return connector_status_disconnected;
3002 static enum drm_connector_status
3003 ironlake_dp_detect(struct intel_dp *intel_dp)
3005 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3008 enum drm_connector_status status;
3010 /* Can't disconnect eDP, but you can close the lid... */
3011 if (is_edp(intel_dp)) {
3012 status = intel_panel_detect(dev);
3013 if (status == connector_status_unknown)
3014 status = connector_status_connected;
3018 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3019 return connector_status_disconnected;
3021 return intel_dp_detect_dpcd(intel_dp);
3024 static enum drm_connector_status
3025 g4x_dp_detect(struct intel_dp *intel_dp)
3027 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3032 /* Can't disconnect eDP, but you can close the lid... */
3033 if (is_edp(intel_dp)) {
3034 enum drm_connector_status status;
3036 status = intel_panel_detect(dev);
3037 if (status == connector_status_unknown)
3038 status = connector_status_connected;
3042 if (IS_VALLEYVIEW(dev)) {
3043 switch (intel_dig_port->port) {
3045 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3048 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3051 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3054 return connector_status_unknown;
3057 switch (intel_dig_port->port) {
3059 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3062 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3065 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3068 return connector_status_unknown;
3072 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3073 return connector_status_disconnected;
3075 return intel_dp_detect_dpcd(intel_dp);
3078 static struct edid *
3079 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3081 struct intel_connector *intel_connector = to_intel_connector(connector);
3083 /* use cached edid if we have one */
3084 if (intel_connector->edid) {
3086 if (IS_ERR(intel_connector->edid))
3089 return drm_edid_duplicate(intel_connector->edid);
3092 return drm_get_edid(connector, adapter);
3096 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3098 struct intel_connector *intel_connector = to_intel_connector(connector);
3100 /* use cached edid if we have one */
3101 if (intel_connector->edid) {
3103 if (IS_ERR(intel_connector->edid))
3106 return intel_connector_update_modes(connector,
3107 intel_connector->edid);
3110 return intel_ddc_get_modes(connector, adapter);
3113 static enum drm_connector_status
3114 intel_dp_detect(struct drm_connector *connector, bool force)
3116 struct intel_dp *intel_dp = intel_attached_dp(connector);
3117 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3118 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3119 struct drm_device *dev = connector->dev;
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 enum drm_connector_status status;
3122 enum intel_display_power_domain power_domain;
3123 struct edid *edid = NULL;
3125 intel_runtime_pm_get(dev_priv);
3127 power_domain = intel_display_port_power_domain(intel_encoder);
3128 intel_display_power_get(dev_priv, power_domain);
3130 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3131 connector->base.id, drm_get_connector_name(connector));
3133 intel_dp->has_audio = false;
3135 if (HAS_PCH_SPLIT(dev))
3136 status = ironlake_dp_detect(intel_dp);
3138 status = g4x_dp_detect(intel_dp);
3140 if (status != connector_status_connected)
3143 intel_dp_probe_oui(intel_dp);
3145 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3146 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3148 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3150 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3155 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3156 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3157 status = connector_status_connected;
3160 intel_display_power_put(dev_priv, power_domain);
3162 intel_runtime_pm_put(dev_priv);
3167 static int intel_dp_get_modes(struct drm_connector *connector)
3169 struct intel_dp *intel_dp = intel_attached_dp(connector);
3170 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3171 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3172 struct intel_connector *intel_connector = to_intel_connector(connector);
3173 struct drm_device *dev = connector->dev;
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 enum intel_display_power_domain power_domain;
3178 /* We should parse the EDID data and find out if it has an audio sink
3181 power_domain = intel_display_port_power_domain(intel_encoder);
3182 intel_display_power_get(dev_priv, power_domain);
3184 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3185 intel_display_power_put(dev_priv, power_domain);
3189 /* if eDP has no EDID, fall back to fixed mode */
3190 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3191 struct drm_display_mode *mode;
3192 mode = drm_mode_duplicate(dev,
3193 intel_connector->panel.fixed_mode);
3195 drm_mode_probed_add(connector, mode);
3203 intel_dp_detect_audio(struct drm_connector *connector)
3205 struct intel_dp *intel_dp = intel_attached_dp(connector);
3206 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3207 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3208 struct drm_device *dev = connector->dev;
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 enum intel_display_power_domain power_domain;
3212 bool has_audio = false;
3214 power_domain = intel_display_port_power_domain(intel_encoder);
3215 intel_display_power_get(dev_priv, power_domain);
3217 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3219 has_audio = drm_detect_monitor_audio(edid);
3223 intel_display_power_put(dev_priv, power_domain);
3229 intel_dp_set_property(struct drm_connector *connector,
3230 struct drm_property *property,
3233 struct drm_i915_private *dev_priv = connector->dev->dev_private;
3234 struct intel_connector *intel_connector = to_intel_connector(connector);
3235 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3236 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3239 ret = drm_object_property_set_value(&connector->base, property, val);
3243 if (property == dev_priv->force_audio_property) {
3247 if (i == intel_dp->force_audio)
3250 intel_dp->force_audio = i;
3252 if (i == HDMI_AUDIO_AUTO)
3253 has_audio = intel_dp_detect_audio(connector);
3255 has_audio = (i == HDMI_AUDIO_ON);
3257 if (has_audio == intel_dp->has_audio)
3260 intel_dp->has_audio = has_audio;
3264 if (property == dev_priv->broadcast_rgb_property) {
3265 bool old_auto = intel_dp->color_range_auto;
3266 uint32_t old_range = intel_dp->color_range;
3269 case INTEL_BROADCAST_RGB_AUTO:
3270 intel_dp->color_range_auto = true;
3272 case INTEL_BROADCAST_RGB_FULL:
3273 intel_dp->color_range_auto = false;
3274 intel_dp->color_range = 0;
3276 case INTEL_BROADCAST_RGB_LIMITED:
3277 intel_dp->color_range_auto = false;
3278 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3284 if (old_auto == intel_dp->color_range_auto &&
3285 old_range == intel_dp->color_range)
3291 if (is_edp(intel_dp) &&
3292 property == connector->dev->mode_config.scaling_mode_property) {
3293 if (val == DRM_MODE_SCALE_NONE) {
3294 DRM_DEBUG_KMS("no scaling not supported\n");
3298 if (intel_connector->panel.fitting_mode == val) {
3299 /* the eDP scaling property is not changed */
3302 intel_connector->panel.fitting_mode = val;
3310 if (intel_encoder->base.crtc)
3311 intel_crtc_restore_mode(intel_encoder->base.crtc);
3317 intel_dp_connector_destroy(struct drm_connector *connector)
3319 struct intel_connector *intel_connector = to_intel_connector(connector);
3321 if (!IS_ERR_OR_NULL(intel_connector->edid))
3322 kfree(intel_connector->edid);
3324 /* Can't call is_edp() since the encoder may have been destroyed
3326 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3327 intel_panel_fini(&intel_connector->panel);
3329 drm_connector_cleanup(connector);
3333 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3335 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3336 struct intel_dp *intel_dp = &intel_dig_port->dp;
3337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3339 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3340 drm_encoder_cleanup(encoder);
3341 if (is_edp(intel_dp)) {
3342 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3343 mutex_lock(&dev->mode_config.mutex);
3344 edp_panel_vdd_off_sync(intel_dp);
3345 mutex_unlock(&dev->mode_config.mutex);
3347 kfree(intel_dig_port);
3350 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3351 .dpms = intel_connector_dpms,
3352 .detect = intel_dp_detect,
3353 .fill_modes = drm_helper_probe_single_connector_modes,
3354 .set_property = intel_dp_set_property,
3355 .destroy = intel_dp_connector_destroy,
3358 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3359 .get_modes = intel_dp_get_modes,
3360 .mode_valid = intel_dp_mode_valid,
3361 .best_encoder = intel_best_encoder,
3364 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3365 .destroy = intel_dp_encoder_destroy,
3369 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3371 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3373 intel_dp_check_link_status(intel_dp);
3376 /* Return which DP Port should be selected for Transcoder DP control */
3378 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3380 struct drm_device *dev = crtc->dev;
3381 struct intel_encoder *intel_encoder;
3382 struct intel_dp *intel_dp;
3384 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3385 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3387 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3388 intel_encoder->type == INTEL_OUTPUT_EDP)
3389 return intel_dp->output_reg;
3395 /* check the VBT to see whether the eDP is on DP-D port */
3396 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 union child_device_config *p_child;
3401 static const short port_mapping[] = {
3402 [PORT_B] = PORT_IDPB,
3403 [PORT_C] = PORT_IDPC,
3404 [PORT_D] = PORT_IDPD,
3410 if (!dev_priv->vbt.child_dev_num)
3413 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3414 p_child = dev_priv->vbt.child_dev + i;
3416 if (p_child->common.dvo_port == port_mapping[port] &&
3417 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3418 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3425 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3427 struct intel_connector *intel_connector = to_intel_connector(connector);
3429 intel_attach_force_audio_property(connector);
3430 intel_attach_broadcast_rgb_property(connector);
3431 intel_dp->color_range_auto = true;
3433 if (is_edp(intel_dp)) {
3434 drm_mode_create_scaling_mode_property(connector->dev);
3435 drm_object_attach_property(
3437 connector->dev->mode_config.scaling_mode_property,
3438 DRM_MODE_SCALE_ASPECT);
3439 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3443 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3445 intel_dp->last_power_cycle = jiffies;
3446 intel_dp->last_power_on = jiffies;
3447 intel_dp->last_backlight_off = jiffies;
3451 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3452 struct intel_dp *intel_dp,
3453 struct edp_power_seq *out)
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct edp_power_seq cur, vbt, spec, final;
3457 u32 pp_on, pp_off, pp_div, pp;
3458 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3460 if (HAS_PCH_SPLIT(dev)) {
3461 pp_ctrl_reg = PCH_PP_CONTROL;
3462 pp_on_reg = PCH_PP_ON_DELAYS;
3463 pp_off_reg = PCH_PP_OFF_DELAYS;
3464 pp_div_reg = PCH_PP_DIVISOR;
3466 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3468 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3469 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3470 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3471 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3474 /* Workaround: Need to write PP_CONTROL with the unlock key as
3475 * the very first thing. */
3476 pp = ironlake_get_pp_control(intel_dp);
3477 I915_WRITE(pp_ctrl_reg, pp);
3479 pp_on = I915_READ(pp_on_reg);
3480 pp_off = I915_READ(pp_off_reg);
3481 pp_div = I915_READ(pp_div_reg);
3483 /* Pull timing values out of registers */
3484 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3485 PANEL_POWER_UP_DELAY_SHIFT;
3487 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3488 PANEL_LIGHT_ON_DELAY_SHIFT;
3490 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3491 PANEL_LIGHT_OFF_DELAY_SHIFT;
3493 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3494 PANEL_POWER_DOWN_DELAY_SHIFT;
3496 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3497 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3499 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3500 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3502 vbt = dev_priv->vbt.edp_pps;
3504 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3505 * our hw here, which are all in 100usec. */
3506 spec.t1_t3 = 210 * 10;
3507 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3508 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3509 spec.t10 = 500 * 10;
3510 /* This one is special and actually in units of 100ms, but zero
3511 * based in the hw (so we need to add 100 ms). But the sw vbt
3512 * table multiplies it with 1000 to make it in units of 100usec,
3514 spec.t11_t12 = (510 + 100) * 10;
3516 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3517 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3519 /* Use the max of the register settings and vbt. If both are
3520 * unset, fall back to the spec limits. */
3521 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3523 max(cur.field, vbt.field))
3524 assign_final(t1_t3);
3528 assign_final(t11_t12);
3531 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3532 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3533 intel_dp->backlight_on_delay = get_delay(t8);
3534 intel_dp->backlight_off_delay = get_delay(t9);
3535 intel_dp->panel_power_down_delay = get_delay(t10);
3536 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3539 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3540 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3541 intel_dp->panel_power_cycle_delay);
3543 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3544 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3551 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3552 struct intel_dp *intel_dp,
3553 struct edp_power_seq *seq)
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556 u32 pp_on, pp_off, pp_div, port_sel = 0;
3557 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3558 int pp_on_reg, pp_off_reg, pp_div_reg;
3560 if (HAS_PCH_SPLIT(dev)) {
3561 pp_on_reg = PCH_PP_ON_DELAYS;
3562 pp_off_reg = PCH_PP_OFF_DELAYS;
3563 pp_div_reg = PCH_PP_DIVISOR;
3565 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3567 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3568 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3569 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3573 * And finally store the new values in the power sequencer. The
3574 * backlight delays are set to 1 because we do manual waits on them. For
3575 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3576 * we'll end up waiting for the backlight off delay twice: once when we
3577 * do the manual sleep, and once when we disable the panel and wait for
3578 * the PP_STATUS bit to become zero.
3580 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3581 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3582 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3583 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3584 /* Compute the divisor for the pp clock, simply match the Bspec
3586 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3587 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3588 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3590 /* Haswell doesn't have any port selection bits for the panel
3591 * power sequencer any more. */
3592 if (IS_VALLEYVIEW(dev)) {
3593 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3594 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3596 port_sel = PANEL_PORT_SELECT_DPC_VLV;
3597 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3598 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3599 port_sel = PANEL_PORT_SELECT_DPA;
3601 port_sel = PANEL_PORT_SELECT_DPD;
3606 I915_WRITE(pp_on_reg, pp_on);
3607 I915_WRITE(pp_off_reg, pp_off);
3608 I915_WRITE(pp_div_reg, pp_div);
3610 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3611 I915_READ(pp_on_reg),
3612 I915_READ(pp_off_reg),
3613 I915_READ(pp_div_reg));
3616 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3617 struct intel_connector *intel_connector,
3618 struct edp_power_seq *power_seq)
3620 struct drm_connector *connector = &intel_connector->base;
3621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3622 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3623 struct drm_device *dev = intel_encoder->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct drm_display_mode *fixed_mode = NULL;
3627 struct drm_display_mode *scan;
3630 if (!is_edp(intel_dp))
3633 /* The VDD bit needs a power domain reference, so if the bit is already
3634 * enabled when we boot, grab this reference. */
3635 if (edp_have_panel_vdd(intel_dp)) {
3636 enum intel_display_power_domain power_domain;
3637 power_domain = intel_display_port_power_domain(intel_encoder);
3638 intel_display_power_get(dev_priv, power_domain);
3641 /* Cache DPCD and EDID for edp. */
3642 intel_edp_panel_vdd_on(intel_dp);
3643 has_dpcd = intel_dp_get_dpcd(intel_dp);
3644 edp_panel_vdd_off(intel_dp, false);
3647 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3648 dev_priv->no_aux_handshake =
3649 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3650 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3652 /* if this fails, presume the device is a ghost */
3653 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3657 /* We now know it's not a ghost, init power sequence regs. */
3658 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3660 mutex_lock(&dev->mode_config.mutex);
3661 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3663 if (drm_add_edid_modes(connector, edid)) {
3664 drm_mode_connector_update_edid_property(connector,
3666 drm_edid_to_eld(connector, edid);
3669 edid = ERR_PTR(-EINVAL);
3672 edid = ERR_PTR(-ENOENT);
3674 intel_connector->edid = edid;
3676 /* prefer fixed mode from EDID if available */
3677 list_for_each_entry(scan, &connector->probed_modes, head) {
3678 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3679 fixed_mode = drm_mode_duplicate(dev, scan);
3684 /* fallback to VBT if available for eDP */
3685 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3686 fixed_mode = drm_mode_duplicate(dev,
3687 dev_priv->vbt.lfp_lvds_vbt_mode);
3689 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3691 mutex_unlock(&dev->mode_config.mutex);
3693 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3694 intel_panel_setup_backlight(connector);
3700 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3701 struct intel_connector *intel_connector)
3703 struct drm_connector *connector = &intel_connector->base;
3704 struct intel_dp *intel_dp = &intel_dig_port->dp;
3705 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3706 struct drm_device *dev = intel_encoder->base.dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 enum port port = intel_dig_port->port;
3709 struct edp_power_seq power_seq = { 0 };
3712 /* intel_dp vfuncs */
3713 if (IS_VALLEYVIEW(dev))
3714 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3715 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3716 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3717 else if (HAS_PCH_SPLIT(dev))
3718 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3720 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3722 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3724 /* Preserve the current hw state. */
3725 intel_dp->DP = I915_READ(intel_dp->output_reg);
3726 intel_dp->attached_connector = intel_connector;
3728 if (intel_dp_is_edp(dev, port))
3729 type = DRM_MODE_CONNECTOR_eDP;
3731 type = DRM_MODE_CONNECTOR_DisplayPort;
3734 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3735 * for DP the encoder type can be set by the caller to
3736 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3738 if (type == DRM_MODE_CONNECTOR_eDP)
3739 intel_encoder->type = INTEL_OUTPUT_EDP;
3741 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3742 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3745 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3746 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3748 connector->interlace_allowed = true;
3749 connector->doublescan_allowed = 0;
3751 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3752 edp_panel_vdd_work);
3754 intel_connector_attach_encoder(intel_connector, intel_encoder);
3755 drm_sysfs_connector_add(connector);
3758 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3760 intel_connector->get_hw_state = intel_connector_get_hw_state;
3761 intel_connector->unregister = intel_dp_connector_unregister;
3763 /* Set up the hotplug pin. */
3766 intel_encoder->hpd_pin = HPD_PORT_A;
3769 intel_encoder->hpd_pin = HPD_PORT_B;
3772 intel_encoder->hpd_pin = HPD_PORT_C;
3775 intel_encoder->hpd_pin = HPD_PORT_D;
3781 if (is_edp(intel_dp)) {
3782 intel_dp_init_panel_power_timestamps(intel_dp);
3783 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3786 intel_dp_aux_init(intel_dp, intel_connector);
3788 intel_dp->psr_setup_done = false;
3790 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3791 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3792 if (is_edp(intel_dp)) {
3793 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3794 mutex_lock(&dev->mode_config.mutex);
3795 edp_panel_vdd_off_sync(intel_dp);
3796 mutex_unlock(&dev->mode_config.mutex);
3798 drm_sysfs_connector_remove(connector);
3799 drm_connector_cleanup(connector);
3803 intel_dp_add_properties(intel_dp, connector);
3805 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3806 * 0xd. Failure to do so will result in spurious interrupts being
3807 * generated on the port when a cable is not attached.
3809 if (IS_G4X(dev) && !IS_GM45(dev)) {
3810 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3811 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3818 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3820 struct intel_digital_port *intel_dig_port;
3821 struct intel_encoder *intel_encoder;
3822 struct drm_encoder *encoder;
3823 struct intel_connector *intel_connector;
3825 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3826 if (!intel_dig_port)
3829 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3830 if (!intel_connector) {
3831 kfree(intel_dig_port);
3835 intel_encoder = &intel_dig_port->base;
3836 encoder = &intel_encoder->base;
3838 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3839 DRM_MODE_ENCODER_TMDS);
3841 intel_encoder->compute_config = intel_dp_compute_config;
3842 intel_encoder->mode_set = intel_dp_mode_set;
3843 intel_encoder->disable = intel_disable_dp;
3844 intel_encoder->post_disable = intel_post_disable_dp;
3845 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3846 intel_encoder->get_config = intel_dp_get_config;
3847 if (IS_VALLEYVIEW(dev)) {
3848 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3849 intel_encoder->pre_enable = vlv_pre_enable_dp;
3850 intel_encoder->enable = vlv_enable_dp;
3852 intel_encoder->pre_enable = g4x_pre_enable_dp;
3853 intel_encoder->enable = g4x_enable_dp;
3856 intel_dig_port->port = port;
3857 intel_dig_port->dp.output_reg = output_reg;
3859 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3860 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3861 intel_encoder->cloneable = 0;
3862 intel_encoder->hot_plug = intel_dp_hot_plug;
3864 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3865 drm_encoder_cleanup(encoder);
3866 kfree(intel_dig_port);
3867 kfree(intel_connector);