drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static int
 194 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 195 {
 196         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 197         struct intel_encoder *encoder = &intel_dig_port->base;
 198         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 199         int max_dotclk = dev_priv->max_dotclk_freq;
 200         int ds_max_dotclk;
 201
 202         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 203
 204         if (type != DP_DS_PORT_TYPE_VGA)
 205                 return max_dotclk;
 206
 207         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 208                                                     intel_dp->downstream_ports);
 209
 210         if (ds_max_dotclk != 0)
 211                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 212
 213         return max_dotclk;
 214 }
 215
 216 static int
 217 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 218 {
 219         if (intel_dp->num_sink_rates) {
 220                 *sink_rates = intel_dp->sink_rates;
 221                 return intel_dp->num_sink_rates;
 222         }
 223
 224         *sink_rates = default_rates;
 225
 226         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
 227 }
 228
 229 static int
 230 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
 231 {
 232         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 233         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 234         int size;
 235
 236         if (IS_BROXTON(dev_priv)) {
 237                 *source_rates = bxt_rates;
 238                 size = ARRAY_SIZE(bxt_rates);
 239         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 240                 *source_rates = skl_rates;
 241                 size = ARRAY_SIZE(skl_rates);
 242         } else {
 243                 *source_rates = default_rates;
 244                 size = ARRAY_SIZE(default_rates);
 245         }
 246
 247         /* This depends on the fact that 5.4 is last value in the array */
 248         if (!intel_dp_source_supports_hbr2(intel_dp))
 249                 size--;
 250
 251         return size;
 252 }
 253
 254 static int intersect_rates(const int *source_rates, int source_len,
 255                            const int *sink_rates, int sink_len,
 256                            int *common_rates)
 257 {
 258         int i = 0, j = 0, k = 0;
 259
 260         while (i < source_len && j < sink_len) {
 261                 if (source_rates[i] == sink_rates[j]) {
 262                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 263                                 return k;
 264                         common_rates[k] = source_rates[i];
 265                         ++k;
 266                         ++i;
 267                         ++j;
 268                 } else if (source_rates[i] < sink_rates[j]) {
 269                         ++i;
 270                 } else {
 271                         ++j;
 272                 }
 273         }
 274         return k;
 275 }
 276
 277 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 278                                  int *common_rates)
 279 {
 280         const int *source_rates, *sink_rates;
 281         int source_len, sink_len;
 282
 283         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 284         source_len = intel_dp_source_rates(intel_dp, &source_rates);
 285
 286         return intersect_rates(source_rates, source_len,
 287                                sink_rates, sink_len,
 288                                common_rates);
 289 }
 290
 291 static enum drm_mode_status
 292 intel_dp_mode_valid(struct drm_connector *connector,
 293                     struct drm_display_mode *mode)
 294 {
 295         struct intel_dp *intel_dp = intel_attached_dp(connector);
 296         struct intel_connector *intel_connector = to_intel_connector(connector);
 297         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 298         int target_clock = mode->clock;
 299         int max_rate, mode_rate, max_lanes, max_link_clock;
 300         int max_dotclk;
 301
 302         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 303
 304         if (is_edp(intel_dp) && fixed_mode) {
 305                 if (mode->hdisplay > fixed_mode->hdisplay)
 306                         return MODE_PANEL;
 307
 308                 if (mode->vdisplay > fixed_mode->vdisplay)
 309                         return MODE_PANEL;
 310
 311                 target_clock = fixed_mode->clock;
 312         }
 313
 314         max_link_clock = intel_dp_max_link_rate(intel_dp);
 315         max_lanes = intel_dp_max_lane_count(intel_dp);
 316
 317         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 318         mode_rate = intel_dp_link_required(target_clock, 18);
 319
 320         if (mode_rate > max_rate || target_clock > max_dotclk)
 321                 return MODE_CLOCK_HIGH;
 322
 323         if (mode->clock < 10000)
 324                 return MODE_CLOCK_LOW;
 325
 326         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 327                 return MODE_H_ILLEGAL;
 328
 329         return MODE_OK;
 330 }
 331
 332 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 333 {
 334         int     i;
 335         uint32_t v = 0;
 336
 337         if (src_bytes > 4)
 338                 src_bytes = 4;
 339         for (i = 0; i < src_bytes; i++)
 340                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 341         return v;
 342 }
 343
 344 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 345 {
 346         int i;
 347         if (dst_bytes > 4)
 348                 dst_bytes = 4;
 349         for (i = 0; i < dst_bytes; i++)
 350                 dst[i] = src >> ((3-i) * 8);
 351 }
 352
 353 static void
 354 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 355                                     struct intel_dp *intel_dp);
 356 static void
 357 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 358                                               struct intel_dp *intel_dp);
 359 static void
 360 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 361
 362 static void pps_lock(struct intel_dp *intel_dp)
 363 {
 364         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 365         struct intel_encoder *encoder = &intel_dig_port->base;
 366         struct drm_device *dev = encoder->base.dev;
 367         struct drm_i915_private *dev_priv = to_i915(dev);
 368         enum intel_display_power_domain power_domain;
 369
 370         /*
 371          * See vlv_power_sequencer_reset() why we need
 372          * a power domain reference here.
 373          */
 374         power_domain = intel_display_port_aux_power_domain(encoder);
 375         intel_display_power_get(dev_priv, power_domain);
 376
 377         mutex_lock(&dev_priv->pps_mutex);
 378 }
 379
 380 static void pps_unlock(struct intel_dp *intel_dp)
 381 {
 382         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 383         struct intel_encoder *encoder = &intel_dig_port->base;
 384         struct drm_device *dev = encoder->base.dev;
 385         struct drm_i915_private *dev_priv = to_i915(dev);
 386         enum intel_display_power_domain power_domain;
 387
 388         mutex_unlock(&dev_priv->pps_mutex);
 389
 390         power_domain = intel_display_port_aux_power_domain(encoder);
 391         intel_display_power_put(dev_priv, power_domain);
 392 }
 393
 394 static void
 395 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 396 {
 397         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 398         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 399         enum pipe pipe = intel_dp->pps_pipe;
 400         bool pll_enabled, release_cl_override = false;
 401         enum dpio_phy phy = DPIO_PHY(pipe);
 402         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 403         uint32_t DP;
 404
 405         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 406                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 407                  pipe_name(pipe), port_name(intel_dig_port->port)))
 408                 return;
 409
 410         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 411                       pipe_name(pipe), port_name(intel_dig_port->port));
 412
 413         /* Preserve the BIOS-computed detected bit. This is
 414          * supposed to be read-only.
 415          */
 416         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 417         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 418         DP |= DP_PORT_WIDTH(1);
 419         DP |= DP_LINK_TRAIN_PAT_1;
 420
 421         if (IS_CHERRYVIEW(dev_priv))
 422                 DP |= DP_PIPE_SELECT_CHV(pipe);
 423         else if (pipe == PIPE_B)
 424                 DP |= DP_PIPEB_SELECT;
 425
 426         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 427
 428         /*
 429          * The DPLL for the pipe must be enabled for this to work.
 430          * So enable temporarily it if it's not already enabled.
 431          */
 432         if (!pll_enabled) {
 433                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 434                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 435
 436                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 437                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 438                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 439                                   pipe_name(pipe));
 440                         return;
 441                 }
 442         }
 443
 444         /*
 445          * Similar magic as in intel_dp_enable_port().
 446          * We _must_ do this port enable + disable trick
 447          * to make this power seqeuencer lock onto the port.
 448          * Otherwise even VDD force bit won't work.
 449          */
 450         I915_WRITE(intel_dp->output_reg, DP);
 451         POSTING_READ(intel_dp->output_reg);
 452
 453         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 454         POSTING_READ(intel_dp->output_reg);
 455
 456         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 457         POSTING_READ(intel_dp->output_reg);
 458
 459         if (!pll_enabled) {
 460                 vlv_force_pll_off(dev_priv, pipe);
 461
 462                 if (release_cl_override)
 463                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 464         }
 465 }
 466
 467 static enum pipe
 468 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 469 {
 470         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 471         struct drm_device *dev = intel_dig_port->base.base.dev;
 472         struct drm_i915_private *dev_priv = to_i915(dev);
 473         struct intel_encoder *encoder;
 474         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 475         enum pipe pipe;
 476
 477         lockdep_assert_held(&dev_priv->pps_mutex);
 478
 479         /* We should never land here with regular DP ports */
 480         WARN_ON(!is_edp(intel_dp));
 481
 482         if (intel_dp->pps_pipe != INVALID_PIPE)
 483                 return intel_dp->pps_pipe;
 484
 485         /*
 486          * We don't have power sequencer currently.
 487          * Pick one that's not used by other ports.
 488          */
 489         for_each_intel_encoder(dev, encoder) {
 490                 struct intel_dp *tmp;
 491
 492                 if (encoder->type != INTEL_OUTPUT_EDP)
 493                         continue;
 494
 495                 tmp = enc_to_intel_dp(&encoder->base);
 496
 497                 if (tmp->pps_pipe != INVALID_PIPE)
 498                         pipes &= ~(1 << tmp->pps_pipe);
 499         }
 500
 501         /*
 502          * Didn't find one. This should not happen since there
 503          * are two power sequencers and up to two eDP ports.
 504          */
 505         if (WARN_ON(pipes == 0))
 506                 pipe = PIPE_A;
 507         else
 508                 pipe = ffs(pipes) - 1;
 509
 510         vlv_steal_power_sequencer(dev, pipe);
 511         intel_dp->pps_pipe = pipe;
 512
 513         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 514                       pipe_name(intel_dp->pps_pipe),
 515                       port_name(intel_dig_port->port));
 516
 517         /* init power sequencer on this pipe and port */
 518         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 519         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 520
 521         /*
 522          * Even vdd force doesn't work until we've made
 523          * the power sequencer lock in on the port.
 524          */
 525         vlv_power_sequencer_kick(intel_dp);
 526
 527         return intel_dp->pps_pipe;
 528 }
 529
 530 static int
 531 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 532 {
 533         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 534         struct drm_device *dev = intel_dig_port->base.base.dev;
 535         struct drm_i915_private *dev_priv = to_i915(dev);
 536
 537         lockdep_assert_held(&dev_priv->pps_mutex);
 538
 539         /* We should never land here with regular DP ports */
 540         WARN_ON(!is_edp(intel_dp));
 541
 542         /*
 543          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 544          * mapping needs to be retrieved from VBT, for now just hard-code to
 545          * use instance #0 always.
 546          */
 547         if (!intel_dp->pps_reset)
 548                 return 0;
 549
 550         intel_dp->pps_reset = false;
 551
 552         /*
 553          * Only the HW needs to be reprogrammed, the SW state is fixed and
 554          * has been setup during connector init.
 555          */
 556         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 557
 558         return 0;
 559 }
 560
 561 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 562                                enum pipe pipe);
 563
 564 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 565                                enum pipe pipe)
 566 {
 567         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 568 }
 569
 570 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 571                                 enum pipe pipe)
 572 {
 573         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 574 }
 575
 576 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 577                          enum pipe pipe)
 578 {
 579         return true;
 580 }
 581
 582 static enum pipe
 583 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 584                      enum port port,
 585                      vlv_pipe_check pipe_check)
 586 {
 587         enum pipe pipe;
 588
 589         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 590                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 591                         PANEL_PORT_SELECT_MASK;
 592
 593                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 594                         continue;
 595
 596                 if (!pipe_check(dev_priv, pipe))
 597                         continue;
 598
 599                 return pipe;
 600         }
 601
 602         return INVALID_PIPE;
 603 }
 604
 605 static void
 606 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 607 {
 608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 609         struct drm_device *dev = intel_dig_port->base.base.dev;
 610         struct drm_i915_private *dev_priv = to_i915(dev);
 611         enum port port = intel_dig_port->port;
 612
 613         lockdep_assert_held(&dev_priv->pps_mutex);
 614
 615         /* try to find a pipe with this port selected */
 616         /* first pick one where the panel is on */
 617         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 618                                                   vlv_pipe_has_pp_on);
 619         /* didn't find one? pick one where vdd is on */
 620         if (intel_dp->pps_pipe == INVALID_PIPE)
 621                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 622                                                           vlv_pipe_has_vdd_on);
 623         /* didn't find one? pick one with just the correct port */
 624         if (intel_dp->pps_pipe == INVALID_PIPE)
 625                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 626                                                           vlv_pipe_any);
 627
 628         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 629         if (intel_dp->pps_pipe == INVALID_PIPE) {
 630                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 631                               port_name(port));
 632                 return;
 633         }
 634
 635         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 636                       port_name(port), pipe_name(intel_dp->pps_pipe));
 637
 638         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 639         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 640 }
 641
 642 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 643 {
 644         struct drm_device *dev = &dev_priv->drm;
 645         struct intel_encoder *encoder;
 646
 647         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 648                     !IS_BROXTON(dev_priv)))
 649                 return;
 650
 651         /*
 652          * We can't grab pps_mutex here due to deadlock with power_domain
 653          * mutex when power_domain functions are called while holding pps_mutex.
 654          * That also means that in order to use pps_pipe the code needs to
 655          * hold both a power domain reference and pps_mutex, and the power domain
 656          * reference get/put must be done while _not_ holding pps_mutex.
 657          * pps_{lock,unlock}() do these steps in the correct order, so one
 658          * should use them always.
 659          */
 660
 661         for_each_intel_encoder(dev, encoder) {
 662                 struct intel_dp *intel_dp;
 663
 664                 if (encoder->type != INTEL_OUTPUT_EDP)
 665                         continue;
 666
 667                 intel_dp = enc_to_intel_dp(&encoder->base);
 668                 if (IS_BROXTON(dev_priv))
 669                         intel_dp->pps_reset = true;
 670                 else
 671                         intel_dp->pps_pipe = INVALID_PIPE;
 672         }
 673 }
 674
 675 struct pps_registers {
 676         i915_reg_t pp_ctrl;
 677         i915_reg_t pp_stat;
 678         i915_reg_t pp_on;
 679         i915_reg_t pp_off;
 680         i915_reg_t pp_div;
 681 };
 682
 683 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 684                                     struct intel_dp *intel_dp,
 685                                     struct pps_registers *regs)
 686 {
 687         int pps_idx = 0;
 688
 689         memset(regs, 0, sizeof(*regs));
 690
 691         if (IS_BROXTON(dev_priv))
 692                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 693         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 694                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 695
 696         regs->pp_ctrl = PP_CONTROL(pps_idx);
 697         regs->pp_stat = PP_STATUS(pps_idx);
 698         regs->pp_on = PP_ON_DELAYS(pps_idx);
 699         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 700         if (!IS_BROXTON(dev_priv))
 701                 regs->pp_div = PP_DIVISOR(pps_idx);
 702 }
 703
 704 static i915_reg_t
 705 _pp_ctrl_reg(struct intel_dp *intel_dp)
 706 {
 707         struct pps_registers regs;
 708
 709         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 710                                 &regs);
 711
 712         return regs.pp_ctrl;
 713 }
 714
 715 static i915_reg_t
 716 _pp_stat_reg(struct intel_dp *intel_dp)
 717 {
 718         struct pps_registers regs;
 719
 720         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 721                                 &regs);
 722
 723         return regs.pp_stat;
 724 }
 725
 726 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 727    This function only applicable when panel PM state is not to be tracked */
 728 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 729                               void *unused)
 730 {
 731         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 732                                                  edp_notifier);
 733         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 734         struct drm_i915_private *dev_priv = to_i915(dev);
 735
 736         if (!is_edp(intel_dp) || code != SYS_RESTART)
 737                 return 0;
 738
 739         pps_lock(intel_dp);
 740
 741         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 742                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 743                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 744                 u32 pp_div;
 745
 746                 pp_ctrl_reg = PP_CONTROL(pipe);
 747                 pp_div_reg  = PP_DIVISOR(pipe);
 748                 pp_div = I915_READ(pp_div_reg);
 749                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 750
 751                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 752                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 753                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 754                 msleep(intel_dp->panel_power_cycle_delay);
 755         }
 756
 757         pps_unlock(intel_dp);
 758
 759         return 0;
 760 }
 761
 762 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 763 {
 764         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 765         struct drm_i915_private *dev_priv = to_i915(dev);
 766
 767         lockdep_assert_held(&dev_priv->pps_mutex);
 768
 769         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 770             intel_dp->pps_pipe == INVALID_PIPE)
 771                 return false;
 772
 773         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 774 }
 775
 776 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 777 {
 778         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 779         struct drm_i915_private *dev_priv = to_i915(dev);
 780
 781         lockdep_assert_held(&dev_priv->pps_mutex);
 782
 783         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 784             intel_dp->pps_pipe == INVALID_PIPE)
 785                 return false;
 786
 787         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 788 }
 789
 790 static void
 791 intel_dp_check_edp(struct intel_dp *intel_dp)
 792 {
 793         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 794         struct drm_i915_private *dev_priv = to_i915(dev);
 795
 796         if (!is_edp(intel_dp))
 797                 return;
 798
 799         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 800                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 801                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 802                               I915_READ(_pp_stat_reg(intel_dp)),
 803                               I915_READ(_pp_ctrl_reg(intel_dp)));
 804         }
 805 }
 806
 807 static uint32_t
 808 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 809 {
 810         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 811         struct drm_device *dev = intel_dig_port->base.base.dev;
 812         struct drm_i915_private *dev_priv = to_i915(dev);
 813         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 814         uint32_t status;
 815         bool done;
 816
 817 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 818         if (has_aux_irq)
 819                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 820                                           msecs_to_jiffies_timeout(10));
 821         else
 822                 done = wait_for(C, 10) == 0;
 823         if (!done)
 824                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 825                           has_aux_irq);
 826 #undef C
 827
 828         return status;
 829 }
 830
 831 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 832 {
 833         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 834         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 835
 836         if (index)
 837                 return 0;
 838
 839         /*
 840          * The clock divider is based off the hrawclk, and would like to run at
 841          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 842          */
 843         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 844 }
 845
 846 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 847 {
 848         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 849         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 850
 851         if (index)
 852                 return 0;
 853
 854         /*
 855          * The clock divider is based off the cdclk or PCH rawclk, and would
 856          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 857          * divide by 2000 and use that
 858          */
 859         if (intel_dig_port->port == PORT_A)
 860                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 861         else
 862                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 863 }
 864
 865 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 866 {
 867         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 868         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 869
 870         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 871                 /* Workaround for non-ULT HSW */
 872                 switch (index) {
 873                 case 0: return 63;
 874                 case 1: return 72;
 875                 default: return 0;
 876                 }
 877         }
 878
 879         return ilk_get_aux_clock_divider(intel_dp, index);
 880 }
 881
 882 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 883 {
 884         /*
 885          * SKL doesn't need us to program the AUX clock divider (Hardware will
 886          * derive the clock from CDCLK automatically). We still implement the
 887          * get_aux_clock_divider vfunc to plug-in into the existing code.
 888          */
 889         return index ? 0 : 1;
 890 }
 891
 892 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 893                                      bool has_aux_irq,
 894                                      int send_bytes,
 895                                      uint32_t aux_clock_divider)
 896 {
 897         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 898         struct drm_i915_private *dev_priv =
 899                         to_i915(intel_dig_port->base.base.dev);
 900         uint32_t precharge, timeout;
 901
 902         if (IS_GEN6(dev_priv))
 903                 precharge = 3;
 904         else
 905                 precharge = 5;
 906
 907         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
 908                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 909         else
 910                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 911
 912         return DP_AUX_CH_CTL_SEND_BUSY |
 913                DP_AUX_CH_CTL_DONE |
 914                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 915                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 916                timeout |
 917                DP_AUX_CH_CTL_RECEIVE_ERROR |
 918                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 919                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 920                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 921 }
 922
 923 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 924                                       bool has_aux_irq,
 925                                       int send_bytes,
 926                                       uint32_t unused)
 927 {
 928         return DP_AUX_CH_CTL_SEND_BUSY |
 929                DP_AUX_CH_CTL_DONE |
 930                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 931                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 932                DP_AUX_CH_CTL_TIME_OUT_1600us |
 933                DP_AUX_CH_CTL_RECEIVE_ERROR |
 934                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 935                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
 936                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 937 }
 938
 939 static int
 940 intel_dp_aux_ch(struct intel_dp *intel_dp,
 941                 const uint8_t *send, int send_bytes,
 942                 uint8_t *recv, int recv_size)
 943 {
 944         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 945         struct drm_i915_private *dev_priv =
 946                         to_i915(intel_dig_port->base.base.dev);
 947         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 948         uint32_t aux_clock_divider;
 949         int i, ret, recv_bytes;
 950         uint32_t status;
 951         int try, clock = 0;
 952         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
 953         bool vdd;
 954
 955         pps_lock(intel_dp);
 956
 957         /*
 958          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 959          * In such cases we want to leave VDD enabled and it's up to upper layers
 960          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 961          * ourselves.
 962          */
 963         vdd = edp_panel_vdd_on(intel_dp);
 964
 965         /* dp aux is extremely sensitive to irq latency, hence request the
 966          * lowest possible wakeup latency and so prevent the cpu from going into
 967          * deep sleep states.
 968          */
 969         pm_qos_update_request(&dev_priv->pm_qos, 0);
 970
 971         intel_dp_check_edp(intel_dp);
 972
 973         /* Try to wait for any previous AUX channel activity */
 974         for (try = 0; try < 3; try++) {
 975                 status = I915_READ_NOTRACE(ch_ctl);
 976                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 977                         break;
 978                 msleep(1);
 979         }
 980
 981         if (try == 3) {
 982                 static u32 last_status = -1;
 983                 const u32 status = I915_READ(ch_ctl);
 984
 985                 if (status != last_status) {
 986                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 987                              status);
 988                         last_status = status;
 989                 }
 990
 991                 ret = -EBUSY;
 992                 goto out;
 993         }
 994
 995         /* Only 5 data registers! */
 996         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 997                 ret = -E2BIG;
 998                 goto out;
 999         }
1000
1001         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1002                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1003                                                           has_aux_irq,
1004                                                           send_bytes,
1005                                                           aux_clock_divider);
1006
1007                 /* Must try at least 3 times according to DP spec */
1008                 for (try = 0; try < 5; try++) {
1009                         /* Load the send data into the aux channel data registers */
1010                         for (i = 0; i < send_bytes; i += 4)
1011                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1012                                            intel_dp_pack_aux(send + i,
1013                                                              send_bytes - i));
1014
1015                         /* Send the command and wait for it to complete */
1016                         I915_WRITE(ch_ctl, send_ctl);
1017
1018                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1019
1020                         /* Clear done status and any errors */
1021                         I915_WRITE(ch_ctl,
1022                                    status |
1023                                    DP_AUX_CH_CTL_DONE |
1024                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1025                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1026
1027                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1028                                 continue;
1029
1030                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1031                          *   400us delay required for errors and timeouts
1032                          *   Timeout errors from the HW already meet this
1033                          *   requirement so skip to next iteration
1034                          */
1035                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1036                                 usleep_range(400, 500);
1037                                 continue;
1038                         }
1039                         if (status & DP_AUX_CH_CTL_DONE)
1040                                 goto done;
1041                 }
1042         }
1043
1044         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1045                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1046                 ret = -EBUSY;
1047                 goto out;
1048         }
1049
1050 done:
1051         /* Check for timeout or receive error.
1052          * Timeouts occur when the sink is not connected
1053          */
1054         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1055                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1056                 ret = -EIO;
1057                 goto out;
1058         }
1059
1060         /* Timeouts occur when the device isn't connected, so they're
1061          * "normal" -- don't fill the kernel log with these */
1062         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1063                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1064                 ret = -ETIMEDOUT;
1065                 goto out;
1066         }
1067
1068         /* Unload any bytes sent back from the other side */
1069         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1070                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1071
1072         /*
1073          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1074          * We have no idea of what happened so we return -EBUSY so
1075          * drm layer takes care for the necessary retries.
1076          */
1077         if (recv_bytes == 0 || recv_bytes > 20) {
1078                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1079                               recv_bytes);
1080                 /*
1081                  * FIXME: This patch was created on top of a series that
1082                  * organize the retries at drm level. There EBUSY should
1083                  * also take care for 1ms wait before retrying.
1084                  * That aux retries re-org is still needed and after that is
1085                  * merged we remove this sleep from here.
1086                  */
1087                 usleep_range(1000, 1500);
1088                 ret = -EBUSY;
1089                 goto out;
1090         }
1091
1092         if (recv_bytes > recv_size)
1093                 recv_bytes = recv_size;
1094
1095         for (i = 0; i < recv_bytes; i += 4)
1096                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1097                                     recv + i, recv_bytes - i);
1098
1099         ret = recv_bytes;
1100 out:
1101         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1102
1103         if (vdd)
1104                 edp_panel_vdd_off(intel_dp, false);
1105
1106         pps_unlock(intel_dp);
1107
1108         return ret;
1109 }
1110
1111 #define BARE_ADDRESS_SIZE       3
1112 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1113 static ssize_t
1114 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1115 {
1116         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1117         uint8_t txbuf[20], rxbuf[20];
1118         size_t txsize, rxsize;
1119         int ret;
1120
1121         txbuf[0] = (msg->request << 4) |
1122                 ((msg->address >> 16) & 0xf);
1123         txbuf[1] = (msg->address >> 8) & 0xff;
1124         txbuf[2] = msg->address & 0xff;
1125         txbuf[3] = msg->size - 1;
1126
1127         switch (msg->request & ~DP_AUX_I2C_MOT) {
1128         case DP_AUX_NATIVE_WRITE:
1129         case DP_AUX_I2C_WRITE:
1130         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1131                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1132                 rxsize = 2; /* 0 or 1 data bytes */
1133
1134                 if (WARN_ON(txsize > 20))
1135                         return -E2BIG;
1136
1137                 WARN_ON(!msg->buffer != !msg->size);
1138
1139                 if (msg->buffer)
1140                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1141
1142                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1143                 if (ret > 0) {
1144                         msg->reply = rxbuf[0] >> 4;
1145
1146                         if (ret > 1) {
1147                                 /* Number of bytes written in a short write. */
1148                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1149                         } else {
1150                                 /* Return payload size. */
1151                                 ret = msg->size;
1152                         }
1153                 }
1154                 break;
1155
1156         case DP_AUX_NATIVE_READ:
1157         case DP_AUX_I2C_READ:
1158                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1159                 rxsize = msg->size + 1;
1160
1161                 if (WARN_ON(rxsize > 20))
1162                         return -E2BIG;
1163
1164                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1165                 if (ret > 0) {
1166                         msg->reply = rxbuf[0] >> 4;
1167                         /*
1168                          * Assume happy day, and copy the data. The caller is
1169                          * expected to check msg->reply before touching it.
1170                          *
1171                          * Return payload size.
1172                          */
1173                         ret--;
1174                         memcpy(msg->buffer, rxbuf + 1, ret);
1175                 }
1176                 break;
1177
1178         default:
1179                 ret = -EINVAL;
1180                 break;
1181         }
1182
1183         return ret;
1184 }
1185
1186 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1187                                 enum port port)
1188 {
1189         const struct ddi_vbt_port_info *info =
1190                 &dev_priv->vbt.ddi_port_info[port];
1191         enum port aux_port;
1192
1193         if (!info->alternate_aux_channel) {
1194                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1195                               port_name(port), port_name(port));
1196                 return port;
1197         }
1198
1199         switch (info->alternate_aux_channel) {
1200         case DP_AUX_A:
1201                 aux_port = PORT_A;
1202                 break;
1203         case DP_AUX_B:
1204                 aux_port = PORT_B;
1205                 break;
1206         case DP_AUX_C:
1207                 aux_port = PORT_C;
1208                 break;
1209         case DP_AUX_D:
1210                 aux_port = PORT_D;
1211                 break;
1212         default:
1213                 MISSING_CASE(info->alternate_aux_channel);
1214                 aux_port = PORT_A;
1215                 break;
1216         }
1217
1218         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1219                       port_name(aux_port), port_name(port));
1220
1221         return aux_port;
1222 }
1223
1224 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1225                                   enum port port)
1226 {
1227         switch (port) {
1228         case PORT_B:
1229         case PORT_C:
1230         case PORT_D:
1231                 return DP_AUX_CH_CTL(port);
1232         default:
1233                 MISSING_CASE(port);
1234                 return DP_AUX_CH_CTL(PORT_B);
1235         }
1236 }
1237
1238 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1239                                    enum port port, int index)
1240 {
1241         switch (port) {
1242         case PORT_B:
1243         case PORT_C:
1244         case PORT_D:
1245                 return DP_AUX_CH_DATA(port, index);
1246         default:
1247                 MISSING_CASE(port);
1248                 return DP_AUX_CH_DATA(PORT_B, index);
1249         }
1250 }
1251
1252 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1253                                   enum port port)
1254 {
1255         switch (port) {
1256         case PORT_A:
1257                 return DP_AUX_CH_CTL(port);
1258         case PORT_B:
1259         case PORT_C:
1260         case PORT_D:
1261                 return PCH_DP_AUX_CH_CTL(port);
1262         default:
1263                 MISSING_CASE(port);
1264                 return DP_AUX_CH_CTL(PORT_A);
1265         }
1266 }
1267
1268 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1269                                    enum port port, int index)
1270 {
1271         switch (port) {
1272         case PORT_A:
1273                 return DP_AUX_CH_DATA(port, index);
1274         case PORT_B:
1275         case PORT_C:
1276         case PORT_D:
1277                 return PCH_DP_AUX_CH_DATA(port, index);
1278         default:
1279                 MISSING_CASE(port);
1280                 return DP_AUX_CH_DATA(PORT_A, index);
1281         }
1282 }
1283
1284 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1285                                   enum port port)
1286 {
1287         switch (port) {
1288         case PORT_A:
1289         case PORT_B:
1290         case PORT_C:
1291         case PORT_D:
1292                 return DP_AUX_CH_CTL(port);
1293         default:
1294                 MISSING_CASE(port);
1295                 return DP_AUX_CH_CTL(PORT_A);
1296         }
1297 }
1298
1299 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1300                                    enum port port, int index)
1301 {
1302         switch (port) {
1303         case PORT_A:
1304         case PORT_B:
1305         case PORT_C:
1306         case PORT_D:
1307                 return DP_AUX_CH_DATA(port, index);
1308         default:
1309                 MISSING_CASE(port);
1310                 return DP_AUX_CH_DATA(PORT_A, index);
1311         }
1312 }
1313
1314 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1315                                     enum port port)
1316 {
1317         if (INTEL_INFO(dev_priv)->gen >= 9)
1318                 return skl_aux_ctl_reg(dev_priv, port);
1319         else if (HAS_PCH_SPLIT(dev_priv))
1320                 return ilk_aux_ctl_reg(dev_priv, port);
1321         else
1322                 return g4x_aux_ctl_reg(dev_priv, port);
1323 }
1324
1325 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1326                                      enum port port, int index)
1327 {
1328         if (INTEL_INFO(dev_priv)->gen >= 9)
1329                 return skl_aux_data_reg(dev_priv, port, index);
1330         else if (HAS_PCH_SPLIT(dev_priv))
1331                 return ilk_aux_data_reg(dev_priv, port, index);
1332         else
1333                 return g4x_aux_data_reg(dev_priv, port, index);
1334 }
1335
1336 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1337 {
1338         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1339         enum port port = intel_aux_port(dev_priv,
1340                                         dp_to_dig_port(intel_dp)->port);
1341         int i;
1342
1343         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1344         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1345                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1346 }
1347
1348 static void
1349 intel_dp_aux_fini(struct intel_dp *intel_dp)
1350 {
1351         kfree(intel_dp->aux.name);
1352 }
1353
1354 static void
1355 intel_dp_aux_init(struct intel_dp *intel_dp)
1356 {
1357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358         enum port port = intel_dig_port->port;
1359
1360         intel_aux_reg_init(intel_dp);
1361         drm_dp_aux_init(&intel_dp->aux);
1362
1363         /* Failure to allocate our preferred name is not critical */
1364         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1365         intel_dp->aux.transfer = intel_dp_aux_transfer;
1366 }
1367
1368 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1369 {
1370         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1371         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1372
1373         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1374             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1375                 return true;
1376         else
1377                 return false;
1378 }
1379
1380 static void
1381 intel_dp_set_clock(struct intel_encoder *encoder,
1382                    struct intel_crtc_state *pipe_config)
1383 {
1384         struct drm_device *dev = encoder->base.dev;
1385         struct drm_i915_private *dev_priv = to_i915(dev);
1386         const struct dp_link_dpll *divisor = NULL;
1387         int i, count = 0;
1388
1389         if (IS_G4X(dev_priv)) {
1390                 divisor = gen4_dpll;
1391                 count = ARRAY_SIZE(gen4_dpll);
1392         } else if (HAS_PCH_SPLIT(dev_priv)) {
1393                 divisor = pch_dpll;
1394                 count = ARRAY_SIZE(pch_dpll);
1395         } else if (IS_CHERRYVIEW(dev_priv)) {
1396                 divisor = chv_dpll;
1397                 count = ARRAY_SIZE(chv_dpll);
1398         } else if (IS_VALLEYVIEW(dev_priv)) {
1399                 divisor = vlv_dpll;
1400                 count = ARRAY_SIZE(vlv_dpll);
1401         }
1402
1403         if (divisor && count) {
1404                 for (i = 0; i < count; i++) {
1405                         if (pipe_config->port_clock == divisor[i].clock) {
1406                                 pipe_config->dpll = divisor[i].dpll;
1407                                 pipe_config->clock_set = true;
1408                                 break;
1409                         }
1410                 }
1411         }
1412 }
1413
1414 static void snprintf_int_array(char *str, size_t len,
1415                                const int *array, int nelem)
1416 {
1417         int i;
1418
1419         str[0] = '\0';
1420
1421         for (i = 0; i < nelem; i++) {
1422                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1423                 if (r >= len)
1424                         return;
1425                 str += r;
1426                 len -= r;
1427         }
1428 }
1429
1430 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1431 {
1432         const int *source_rates, *sink_rates;
1433         int source_len, sink_len, common_len;
1434         int common_rates[DP_MAX_SUPPORTED_RATES];
1435         char str[128]; /* FIXME: too big for stack? */
1436
1437         if ((drm_debug & DRM_UT_KMS) == 0)
1438                 return;
1439
1440         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1441         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1442         DRM_DEBUG_KMS("source rates: %s\n", str);
1443
1444         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1445         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1446         DRM_DEBUG_KMS("sink rates: %s\n", str);
1447
1448         common_len = intel_dp_common_rates(intel_dp, common_rates);
1449         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1450         DRM_DEBUG_KMS("common rates: %s\n", str);
1451 }
1452
1453 bool
1454 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1455 {
1456         u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1457                                                       DP_SINK_OUI;
1458
1459         return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1460                sizeof(*desc);
1461 }
1462
1463 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1464 {
1465         struct intel_dp_desc *desc = &intel_dp->desc;
1466         bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1467                        DP_OUI_SUPPORT;
1468         int dev_id_len;
1469
1470         if (!__intel_dp_read_desc(intel_dp, desc))
1471                 return false;
1472
1473         dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1474         DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1475                       drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1476                       (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1477                       dev_id_len, desc->device_id,
1478                       desc->hw_rev >> 4, desc->hw_rev & 0xf,
1479                       desc->sw_major_rev, desc->sw_minor_rev);
1480
1481         return true;
1482 }
1483
1484 static int rate_to_index(int find, const int *rates)
1485 {
1486         int i = 0;
1487
1488         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1489                 if (find == rates[i])
1490                         break;
1491
1492         return i;
1493 }
1494
1495 int
1496 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1497 {
1498         int rates[DP_MAX_SUPPORTED_RATES] = {};
1499         int len;
1500
1501         len = intel_dp_common_rates(intel_dp, rates);
1502         if (WARN_ON(len <= 0))
1503                 return 162000;
1504
1505         return rates[len - 1];
1506 }
1507
1508 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1509 {
1510         return rate_to_index(rate, intel_dp->sink_rates);
1511 }
1512
1513 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1514                            uint8_t *link_bw, uint8_t *rate_select)
1515 {
1516         if (intel_dp->num_sink_rates) {
1517                 *link_bw = 0;
1518                 *rate_select =
1519                         intel_dp_rate_select(intel_dp, port_clock);
1520         } else {
1521                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1522                 *rate_select = 0;
1523         }
1524 }
1525
1526 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1527                                 struct intel_crtc_state *pipe_config)
1528 {
1529         int bpp, bpc;
1530
1531         bpp = pipe_config->pipe_bpp;
1532         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1533
1534         if (bpc > 0)
1535                 bpp = min(bpp, 3*bpc);
1536
1537         return bpp;
1538 }
1539
1540 bool
1541 intel_dp_compute_config(struct intel_encoder *encoder,
1542                         struct intel_crtc_state *pipe_config,
1543                         struct drm_connector_state *conn_state)
1544 {
1545         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1546         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1548         enum port port = dp_to_dig_port(intel_dp)->port;
1549         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1550         struct intel_connector *intel_connector = intel_dp->attached_connector;
1551         int lane_count, clock;
1552         int min_lane_count = 1;
1553         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1554         /* Conveniently, the link BW constants become indices with a shift...*/
1555         int min_clock = 0;
1556         int max_clock;
1557         int bpp, mode_rate;
1558         int link_avail, link_clock;
1559         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1560         int common_len;
1561         uint8_t link_bw, rate_select;
1562
1563         common_len = intel_dp_common_rates(intel_dp, common_rates);
1564
1565         /* No common link rates between source and sink */
1566         WARN_ON(common_len <= 0);
1567
1568         max_clock = common_len - 1;
1569
1570         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1571                 pipe_config->has_pch_encoder = true;
1572
1573         pipe_config->has_drrs = false;
1574         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1575
1576         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1577                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1578                                        adjusted_mode);
1579
1580                 if (INTEL_GEN(dev_priv) >= 9) {
1581                         int ret;
1582                         ret = skl_update_scaler_crtc(pipe_config);
1583                         if (ret)
1584                                 return ret;
1585                 }
1586
1587                 if (HAS_GMCH_DISPLAY(dev_priv))
1588                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1589                                                  intel_connector->panel.fitting_mode);
1590                 else
1591                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1592                                                 intel_connector->panel.fitting_mode);
1593         }
1594
1595         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1596                 return false;
1597
1598         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1599                       "max bw %d pixel clock %iKHz\n",
1600                       max_lane_count, common_rates[max_clock],
1601                       adjusted_mode->crtc_clock);
1602
1603         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1604          * bpc in between. */
1605         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1606         if (is_edp(intel_dp)) {
1607
1608                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1609                 if (intel_connector->base.display_info.bpc == 0 &&
1610                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1611                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1612                                       dev_priv->vbt.edp.bpp);
1613                         bpp = dev_priv->vbt.edp.bpp;
1614                 }
1615
1616                 /*
1617                  * Use the maximum clock and number of lanes the eDP panel
1618                  * advertizes being capable of. The panels are generally
1619                  * designed to support only a single clock and lane
1620                  * configuration, and typically these values correspond to the
1621                  * native resolution of the panel.
1622                  */
1623                 min_lane_count = max_lane_count;
1624                 min_clock = max_clock;
1625         }
1626
1627         for (; bpp >= 6*3; bpp -= 2*3) {
1628                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1629                                                    bpp);
1630
1631                 for (clock = min_clock; clock <= max_clock; clock++) {
1632                         for (lane_count = min_lane_count;
1633                                 lane_count <= max_lane_count;
1634                                 lane_count <<= 1) {
1635
1636                                 link_clock = common_rates[clock];
1637                                 link_avail = intel_dp_max_data_rate(link_clock,
1638                                                                     lane_count);
1639
1640                                 if (mode_rate <= link_avail) {
1641                                         goto found;
1642                                 }
1643                         }
1644                 }
1645         }
1646
1647         return false;
1648
1649 found:
1650         if (intel_dp->color_range_auto) {
1651                 /*
1652                  * See:
1653                  * CEA-861-E - 5.1 Default Encoding Parameters
1654                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1655                  */
1656                 pipe_config->limited_color_range =
1657                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1658         } else {
1659                 pipe_config->limited_color_range =
1660                         intel_dp->limited_color_range;
1661         }
1662
1663         pipe_config->lane_count = lane_count;
1664
1665         pipe_config->pipe_bpp = bpp;
1666         pipe_config->port_clock = common_rates[clock];
1667
1668         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1669                               &link_bw, &rate_select);
1670
1671         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1672                       link_bw, rate_select, pipe_config->lane_count,
1673                       pipe_config->port_clock, bpp);
1674         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1675                       mode_rate, link_avail);
1676
1677         intel_link_compute_m_n(bpp, lane_count,
1678                                adjusted_mode->crtc_clock,
1679                                pipe_config->port_clock,
1680                                &pipe_config->dp_m_n);
1681
1682         if (intel_connector->panel.downclock_mode != NULL &&
1683                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1684                         pipe_config->has_drrs = true;
1685                         intel_link_compute_m_n(bpp, lane_count,
1686                                 intel_connector->panel.downclock_mode->clock,
1687                                 pipe_config->port_clock,
1688                                 &pipe_config->dp_m2_n2);
1689         }
1690
1691         /*
1692          * DPLL0 VCO may need to be adjusted to get the correct
1693          * clock for eDP. This will affect cdclk as well.
1694          */
1695         if (is_edp(intel_dp) &&
1696             (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1697                 int vco;
1698
1699                 switch (pipe_config->port_clock / 2) {
1700                 case 108000:
1701                 case 216000:
1702                         vco = 8640000;
1703                         break;
1704                 default:
1705                         vco = 8100000;
1706                         break;
1707                 }
1708
1709                 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1710         }
1711
1712         if (!HAS_DDI(dev_priv))
1713                 intel_dp_set_clock(encoder, pipe_config);
1714
1715         return true;
1716 }
1717
1718 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1719                               int link_rate, uint8_t lane_count,
1720                               bool link_mst)
1721 {
1722         intel_dp->link_rate = link_rate;
1723         intel_dp->lane_count = lane_count;
1724         intel_dp->link_mst = link_mst;
1725 }
1726
1727 static void intel_dp_prepare(struct intel_encoder *encoder,
1728                              struct intel_crtc_state *pipe_config)
1729 {
1730         struct drm_device *dev = encoder->base.dev;
1731         struct drm_i915_private *dev_priv = to_i915(dev);
1732         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1733         enum port port = dp_to_dig_port(intel_dp)->port;
1734         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1735         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1736
1737         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1738                                  pipe_config->lane_count,
1739                                  intel_crtc_has_type(pipe_config,
1740                                                      INTEL_OUTPUT_DP_MST));
1741
1742         /*
1743          * There are four kinds of DP registers:
1744          *
1745          *      IBX PCH
1746          *      SNB CPU
1747          *      IVB CPU
1748          *      CPT PCH
1749          *
1750          * IBX PCH and CPU are the same for almost everything,
1751          * except that the CPU DP PLL is configured in this
1752          * register
1753          *
1754          * CPT PCH is quite different, having many bits moved
1755          * to the TRANS_DP_CTL register instead. That
1756          * configuration happens (oddly) in ironlake_pch_enable
1757          */
1758
1759         /* Preserve the BIOS-computed detected bit. This is
1760          * supposed to be read-only.
1761          */
1762         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1763
1764         /* Handle DP bits in common between all three register formats */
1765         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1766         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1767
1768         /* Split out the IBX/CPU vs CPT settings */
1769
1770         if (IS_GEN7(dev_priv) && port == PORT_A) {
1771                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1772                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1773                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1774                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1775                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1776
1777                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1778                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1779
1780                 intel_dp->DP |= crtc->pipe << 29;
1781         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1782                 u32 trans_dp;
1783
1784                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1785
1786                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1787                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1788                         trans_dp |= TRANS_DP_ENH_FRAMING;
1789                 else
1790                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1791                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1792         } else {
1793                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1794                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1795
1796                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1797                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1798                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1799                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1800                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1801
1802                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1803                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1804
1805                 if (IS_CHERRYVIEW(dev_priv))
1806                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1807                 else if (crtc->pipe == PIPE_B)
1808                         intel_dp->DP |= DP_PIPEB_SELECT;
1809         }
1810 }
1811
1812 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1813 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1814
1815 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1816 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1817
1818 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1819 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1820
1821 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1822                                    struct intel_dp *intel_dp);
1823
1824 static void wait_panel_status(struct intel_dp *intel_dp,
1825                                        u32 mask,
1826                                        u32 value)
1827 {
1828         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1829         struct drm_i915_private *dev_priv = to_i915(dev);
1830         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1831
1832         lockdep_assert_held(&dev_priv->pps_mutex);
1833
1834         intel_pps_verify_state(dev_priv, intel_dp);
1835
1836         pp_stat_reg = _pp_stat_reg(intel_dp);
1837         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1838
1839         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1840                         mask, value,
1841                         I915_READ(pp_stat_reg),
1842                         I915_READ(pp_ctrl_reg));
1843
1844         if (intel_wait_for_register(dev_priv,
1845                                     pp_stat_reg, mask, value,
1846                                     5000))
1847                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1848                                 I915_READ(pp_stat_reg),
1849                                 I915_READ(pp_ctrl_reg));
1850
1851         DRM_DEBUG_KMS("Wait complete\n");
1852 }
1853
1854 static void wait_panel_on(struct intel_dp *intel_dp)
1855 {
1856         DRM_DEBUG_KMS("Wait for panel power on\n");
1857         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1858 }
1859
1860 static void wait_panel_off(struct intel_dp *intel_dp)
1861 {
1862         DRM_DEBUG_KMS("Wait for panel power off time\n");
1863         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1864 }
1865
1866 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1867 {
1868         ktime_t panel_power_on_time;
1869         s64 panel_power_off_duration;
1870
1871         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1872
1873         /* take the difference of currrent time and panel power off time
1874          * and then make panel wait for t11_t12 if needed. */
1875         panel_power_on_time = ktime_get_boottime();
1876         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1877
1878         /* When we disable the VDD override bit last we have to do the manual
1879          * wait. */
1880         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1881                 wait_remaining_ms_from_jiffies(jiffies,
1882                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1883
1884         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1885 }
1886
1887 static void wait_backlight_on(struct intel_dp *intel_dp)
1888 {
1889         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1890                                        intel_dp->backlight_on_delay);
1891 }
1892
1893 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1894 {
1895         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1896                                        intel_dp->backlight_off_delay);
1897 }
1898
1899 /* Read the current pp_control value, unlocking the register if it
1900  * is locked
1901  */
1902
1903 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1904 {
1905         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1906         struct drm_i915_private *dev_priv = to_i915(dev);
1907         u32 control;
1908
1909         lockdep_assert_held(&dev_priv->pps_mutex);
1910
1911         control = I915_READ(_pp_ctrl_reg(intel_dp));
1912         if (WARN_ON(!HAS_DDI(dev_priv) &&
1913                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1914                 control &= ~PANEL_UNLOCK_MASK;
1915                 control |= PANEL_UNLOCK_REGS;
1916         }
1917         return control;
1918 }
1919
1920 /*
1921  * Must be paired with edp_panel_vdd_off().
1922  * Must hold pps_mutex around the whole on/off sequence.
1923  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1924  */
1925 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1926 {
1927         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1928         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1929         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1930         struct drm_i915_private *dev_priv = to_i915(dev);
1931         enum intel_display_power_domain power_domain;
1932         u32 pp;
1933         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1934         bool need_to_disable = !intel_dp->want_panel_vdd;
1935
1936         lockdep_assert_held(&dev_priv->pps_mutex);
1937
1938         if (!is_edp(intel_dp))
1939                 return false;
1940
1941         cancel_delayed_work(&intel_dp->panel_vdd_work);
1942         intel_dp->want_panel_vdd = true;
1943
1944         if (edp_have_panel_vdd(intel_dp))
1945                 return need_to_disable;
1946
1947         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1948         intel_display_power_get(dev_priv, power_domain);
1949
1950         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1951                       port_name(intel_dig_port->port));
1952
1953         if (!edp_have_panel_power(intel_dp))
1954                 wait_panel_power_cycle(intel_dp);
1955
1956         pp = ironlake_get_pp_control(intel_dp);
1957         pp |= EDP_FORCE_VDD;
1958
1959         pp_stat_reg = _pp_stat_reg(intel_dp);
1960         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1961
1962         I915_WRITE(pp_ctrl_reg, pp);
1963         POSTING_READ(pp_ctrl_reg);
1964         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1965                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1966         /*
1967          * If the panel wasn't on, delay before accessing aux channel
1968          */
1969         if (!edp_have_panel_power(intel_dp)) {
1970                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1971                               port_name(intel_dig_port->port));
1972                 msleep(intel_dp->panel_power_up_delay);
1973         }
1974
1975         return need_to_disable;
1976 }
1977
1978 /*
1979  * Must be paired with intel_edp_panel_vdd_off() or
1980  * intel_edp_panel_off().
1981  * Nested calls to these functions are not allowed since
1982  * we drop the lock. Caller must use some higher level
1983  * locking to prevent nested calls from other threads.
1984  */
1985 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1986 {
1987         bool vdd;
1988
1989         if (!is_edp(intel_dp))
1990                 return;
1991
1992         pps_lock(intel_dp);
1993         vdd = edp_panel_vdd_on(intel_dp);
1994         pps_unlock(intel_dp);
1995
1996         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1997              port_name(dp_to_dig_port(intel_dp)->port));
1998 }
1999
2000 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2001 {
2002         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2003         struct drm_i915_private *dev_priv = to_i915(dev);
2004         struct intel_digital_port *intel_dig_port =
2005                 dp_to_dig_port(intel_dp);
2006         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2007         enum intel_display_power_domain power_domain;
2008         u32 pp;
2009         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2010
2011         lockdep_assert_held(&dev_priv->pps_mutex);
2012
2013         WARN_ON(intel_dp->want_panel_vdd);
2014
2015         if (!edp_have_panel_vdd(intel_dp))
2016                 return;
2017
2018         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2019                       port_name(intel_dig_port->port));
2020
2021         pp = ironlake_get_pp_control(intel_dp);
2022         pp &= ~EDP_FORCE_VDD;
2023
2024         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2025         pp_stat_reg = _pp_stat_reg(intel_dp);
2026
2027         I915_WRITE(pp_ctrl_reg, pp);
2028         POSTING_READ(pp_ctrl_reg);
2029
2030         /* Make sure sequencer is idle before allowing subsequent activity */
2031         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2032         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2033
2034         if ((pp & PANEL_POWER_ON) == 0)
2035                 intel_dp->panel_power_off_time = ktime_get_boottime();
2036
2037         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2038         intel_display_power_put(dev_priv, power_domain);
2039 }
2040
2041 static void edp_panel_vdd_work(struct work_struct *__work)
2042 {
2043         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2044                                                  struct intel_dp, panel_vdd_work);
2045
2046         pps_lock(intel_dp);
2047         if (!intel_dp->want_panel_vdd)
2048                 edp_panel_vdd_off_sync(intel_dp);
2049         pps_unlock(intel_dp);
2050 }
2051
2052 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2053 {
2054         unsigned long delay;
2055
2056         /*
2057          * Queue the timer to fire a long time from now (relative to the power
2058          * down delay) to keep the panel power up across a sequence of
2059          * operations.
2060          */
2061         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2062         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2063 }
2064
2065 /*
2066  * Must be paired with edp_panel_vdd_on().
2067  * Must hold pps_mutex around the whole on/off sequence.
2068  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2069  */
2070 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2071 {
2072         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2073
2074         lockdep_assert_held(&dev_priv->pps_mutex);
2075
2076         if (!is_edp(intel_dp))
2077                 return;
2078
2079         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2080              port_name(dp_to_dig_port(intel_dp)->port));
2081
2082         intel_dp->want_panel_vdd = false;
2083
2084         if (sync)
2085                 edp_panel_vdd_off_sync(intel_dp);
2086         else
2087                 edp_panel_vdd_schedule_off(intel_dp);
2088 }
2089
2090 static void edp_panel_on(struct intel_dp *intel_dp)
2091 {
2092         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2093         struct drm_i915_private *dev_priv = to_i915(dev);
2094         u32 pp;
2095         i915_reg_t pp_ctrl_reg;
2096
2097         lockdep_assert_held(&dev_priv->pps_mutex);
2098
2099         if (!is_edp(intel_dp))
2100                 return;
2101
2102         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2103                       port_name(dp_to_dig_port(intel_dp)->port));
2104
2105         if (WARN(edp_have_panel_power(intel_dp),
2106                  "eDP port %c panel power already on\n",
2107                  port_name(dp_to_dig_port(intel_dp)->port)))
2108                 return;
2109
2110         wait_panel_power_cycle(intel_dp);
2111
2112         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2113         pp = ironlake_get_pp_control(intel_dp);
2114         if (IS_GEN5(dev_priv)) {
2115                 /* ILK workaround: disable reset around power sequence */
2116                 pp &= ~PANEL_POWER_RESET;
2117                 I915_WRITE(pp_ctrl_reg, pp);
2118                 POSTING_READ(pp_ctrl_reg);
2119         }
2120
2121         pp |= PANEL_POWER_ON;
2122         if (!IS_GEN5(dev_priv))
2123                 pp |= PANEL_POWER_RESET;
2124
2125         I915_WRITE(pp_ctrl_reg, pp);
2126         POSTING_READ(pp_ctrl_reg);
2127
2128         wait_panel_on(intel_dp);
2129         intel_dp->last_power_on = jiffies;
2130
2131         if (IS_GEN5(dev_priv)) {
2132                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2133                 I915_WRITE(pp_ctrl_reg, pp);
2134                 POSTING_READ(pp_ctrl_reg);
2135         }
2136 }
2137
2138 void intel_edp_panel_on(struct intel_dp *intel_dp)
2139 {
2140         if (!is_edp(intel_dp))
2141                 return;
2142
2143         pps_lock(intel_dp);
2144         edp_panel_on(intel_dp);
2145         pps_unlock(intel_dp);
2146 }
2147
2148
2149 static void edp_panel_off(struct intel_dp *intel_dp)
2150 {
2151         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2152         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2153         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2154         struct drm_i915_private *dev_priv = to_i915(dev);
2155         enum intel_display_power_domain power_domain;
2156         u32 pp;
2157         i915_reg_t pp_ctrl_reg;
2158
2159         lockdep_assert_held(&dev_priv->pps_mutex);
2160
2161         if (!is_edp(intel_dp))
2162                 return;
2163
2164         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2165                       port_name(dp_to_dig_port(intel_dp)->port));
2166
2167         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2168              port_name(dp_to_dig_port(intel_dp)->port));
2169
2170         pp = ironlake_get_pp_control(intel_dp);
2171         /* We need to switch off panel power _and_ force vdd, for otherwise some
2172          * panels get very unhappy and cease to work. */
2173         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2174                 EDP_BLC_ENABLE);
2175
2176         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2177
2178         intel_dp->want_panel_vdd = false;
2179
2180         I915_WRITE(pp_ctrl_reg, pp);
2181         POSTING_READ(pp_ctrl_reg);
2182
2183         intel_dp->panel_power_off_time = ktime_get_boottime();
2184         wait_panel_off(intel_dp);
2185
2186         /* We got a reference when we enabled the VDD. */
2187         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2188         intel_display_power_put(dev_priv, power_domain);
2189 }
2190
2191 void intel_edp_panel_off(struct intel_dp *intel_dp)
2192 {
2193         if (!is_edp(intel_dp))
2194                 return;
2195
2196         pps_lock(intel_dp);
2197         edp_panel_off(intel_dp);
2198         pps_unlock(intel_dp);
2199 }
2200
2201 /* Enable backlight in the panel power control. */
2202 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2203 {
2204         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2205         struct drm_device *dev = intel_dig_port->base.base.dev;
2206         struct drm_i915_private *dev_priv = to_i915(dev);
2207         u32 pp;
2208         i915_reg_t pp_ctrl_reg;
2209
2210         /*
2211          * If we enable the backlight right away following a panel power
2212          * on, we may see slight flicker as the panel syncs with the eDP
2213          * link.  So delay a bit to make sure the image is solid before
2214          * allowing it to appear.
2215          */
2216         wait_backlight_on(intel_dp);
2217
2218         pps_lock(intel_dp);
2219
2220         pp = ironlake_get_pp_control(intel_dp);
2221         pp |= EDP_BLC_ENABLE;
2222
2223         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2224
2225         I915_WRITE(pp_ctrl_reg, pp);
2226         POSTING_READ(pp_ctrl_reg);
2227
2228         pps_unlock(intel_dp);
2229 }
2230
2231 /* Enable backlight PWM and backlight PP control. */
2232 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2233 {
2234         if (!is_edp(intel_dp))
2235                 return;
2236
2237         DRM_DEBUG_KMS("\n");
2238
2239         intel_panel_enable_backlight(intel_dp->attached_connector);
2240         _intel_edp_backlight_on(intel_dp);
2241 }
2242
2243 /* Disable backlight in the panel power control. */
2244 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2245 {
2246         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2247         struct drm_i915_private *dev_priv = to_i915(dev);
2248         u32 pp;
2249         i915_reg_t pp_ctrl_reg;
2250
2251         if (!is_edp(intel_dp))
2252                 return;
2253
2254         pps_lock(intel_dp);
2255
2256         pp = ironlake_get_pp_control(intel_dp);
2257         pp &= ~EDP_BLC_ENABLE;
2258
2259         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2260
2261         I915_WRITE(pp_ctrl_reg, pp);
2262         POSTING_READ(pp_ctrl_reg);
2263
2264         pps_unlock(intel_dp);
2265
2266         intel_dp->last_backlight_off = jiffies;
2267         edp_wait_backlight_off(intel_dp);
2268 }
2269
2270 /* Disable backlight PP control and backlight PWM. */
2271 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2272 {
2273         if (!is_edp(intel_dp))
2274                 return;
2275
2276         DRM_DEBUG_KMS("\n");
2277
2278         _intel_edp_backlight_off(intel_dp);
2279         intel_panel_disable_backlight(intel_dp->attached_connector);
2280 }
2281
2282 /*
2283  * Hook for controlling the panel power control backlight through the bl_power
2284  * sysfs attribute. Take care to handle multiple calls.
2285  */
2286 static void intel_edp_backlight_power(struct intel_connector *connector,
2287                                       bool enable)
2288 {
2289         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2290         bool is_enabled;
2291
2292         pps_lock(intel_dp);
2293         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2294         pps_unlock(intel_dp);
2295
2296         if (is_enabled == enable)
2297                 return;
2298
2299         DRM_DEBUG_KMS("panel power control backlight %s\n",
2300                       enable ? "enable" : "disable");
2301
2302         if (enable)
2303                 _intel_edp_backlight_on(intel_dp);
2304         else
2305                 _intel_edp_backlight_off(intel_dp);
2306 }
2307
2308 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2309 {
2310         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2311         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2312         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2313
2314         I915_STATE_WARN(cur_state != state,
2315                         "DP port %c state assertion failure (expected %s, current %s)\n",
2316                         port_name(dig_port->port),
2317                         onoff(state), onoff(cur_state));
2318 }
2319 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2320
2321 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2322 {
2323         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2324
2325         I915_STATE_WARN(cur_state != state,
2326                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2327                         onoff(state), onoff(cur_state));
2328 }
2329 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2330 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2331
2332 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2333                                 struct intel_crtc_state *pipe_config)
2334 {
2335         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2336         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2337
2338         assert_pipe_disabled(dev_priv, crtc->pipe);
2339         assert_dp_port_disabled(intel_dp);
2340         assert_edp_pll_disabled(dev_priv);
2341
2342         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2343                       pipe_config->port_clock);
2344
2345         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2346
2347         if (pipe_config->port_clock == 162000)
2348                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2349         else
2350                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2351
2352         I915_WRITE(DP_A, intel_dp->DP);
2353         POSTING_READ(DP_A);
2354         udelay(500);
2355
2356         /*
2357          * [DevILK] Work around required when enabling DP PLL
2358          * while a pipe is enabled going to FDI:
2359          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2360          * 2. Program DP PLL enable
2361          */
2362         if (IS_GEN5(dev_priv))
2363                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2364
2365         intel_dp->DP |= DP_PLL_ENABLE;
2366
2367         I915_WRITE(DP_A, intel_dp->DP);
2368         POSTING_READ(DP_A);
2369         udelay(200);
2370 }
2371
2372 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2373 {
2374         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2375         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2376         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2377
2378         assert_pipe_disabled(dev_priv, crtc->pipe);
2379         assert_dp_port_disabled(intel_dp);
2380         assert_edp_pll_enabled(dev_priv);
2381
2382         DRM_DEBUG_KMS("disabling eDP PLL\n");
2383
2384         intel_dp->DP &= ~DP_PLL_ENABLE;
2385
2386         I915_WRITE(DP_A, intel_dp->DP);
2387         POSTING_READ(DP_A);
2388         udelay(200);
2389 }
2390
2391 /* If the sink supports it, try to set the power state appropriately */
2392 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2393 {
2394         int ret, i;
2395
2396         /* Should have a valid DPCD by this point */
2397         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2398                 return;
2399
2400         if (mode != DRM_MODE_DPMS_ON) {
2401                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2402                                          DP_SET_POWER_D3);
2403         } else {
2404                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2405
2406                 /*
2407                  * When turning on, we need to retry for 1ms to give the sink
2408                  * time to wake up.
2409                  */
2410                 for (i = 0; i < 3; i++) {
2411                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2412                                                  DP_SET_POWER_D0);
2413                         if (ret == 1)
2414                                 break;
2415                         msleep(1);
2416                 }
2417
2418                 if (ret == 1 && lspcon->active)
2419                         lspcon_wait_pcon_mode(lspcon);
2420         }
2421
2422         if (ret != 1)
2423                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2424                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2425 }
2426
2427 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2428                                   enum pipe *pipe)
2429 {
2430         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2431         enum port port = dp_to_dig_port(intel_dp)->port;
2432         struct drm_device *dev = encoder->base.dev;
2433         struct drm_i915_private *dev_priv = to_i915(dev);
2434         enum intel_display_power_domain power_domain;
2435         u32 tmp;
2436         bool ret;
2437
2438         power_domain = intel_display_port_power_domain(encoder);
2439         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2440                 return false;
2441
2442         ret = false;
2443
2444         tmp = I915_READ(intel_dp->output_reg);
2445
2446         if (!(tmp & DP_PORT_EN))
2447                 goto out;
2448
2449         if (IS_GEN7(dev_priv) && port == PORT_A) {
2450                 *pipe = PORT_TO_PIPE_CPT(tmp);
2451         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2452                 enum pipe p;
2453
2454                 for_each_pipe(dev_priv, p) {
2455                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2456                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2457                                 *pipe = p;
2458                                 ret = true;
2459
2460                                 goto out;
2461                         }
2462                 }
2463
2464                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2465                               i915_mmio_reg_offset(intel_dp->output_reg));
2466         } else if (IS_CHERRYVIEW(dev_priv)) {
2467                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2468         } else {
2469                 *pipe = PORT_TO_PIPE(tmp);
2470         }
2471
2472         ret = true;
2473
2474 out:
2475         intel_display_power_put(dev_priv, power_domain);
2476
2477         return ret;
2478 }
2479
2480 static void intel_dp_get_config(struct intel_encoder *encoder,
2481                                 struct intel_crtc_state *pipe_config)
2482 {
2483         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2484         u32 tmp, flags = 0;
2485         struct drm_device *dev = encoder->base.dev;
2486         struct drm_i915_private *dev_priv = to_i915(dev);
2487         enum port port = dp_to_dig_port(intel_dp)->port;
2488         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2489
2490         tmp = I915_READ(intel_dp->output_reg);
2491
2492         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2493
2494         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2495                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2496
2497                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2498                         flags |= DRM_MODE_FLAG_PHSYNC;
2499                 else
2500                         flags |= DRM_MODE_FLAG_NHSYNC;
2501
2502                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2503                         flags |= DRM_MODE_FLAG_PVSYNC;
2504                 else
2505                         flags |= DRM_MODE_FLAG_NVSYNC;
2506         } else {
2507                 if (tmp & DP_SYNC_HS_HIGH)
2508                         flags |= DRM_MODE_FLAG_PHSYNC;
2509                 else
2510                         flags |= DRM_MODE_FLAG_NHSYNC;
2511
2512                 if (tmp & DP_SYNC_VS_HIGH)
2513                         flags |= DRM_MODE_FLAG_PVSYNC;
2514                 else
2515                         flags |= DRM_MODE_FLAG_NVSYNC;
2516         }
2517
2518         pipe_config->base.adjusted_mode.flags |= flags;
2519
2520         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2521                 pipe_config->limited_color_range = true;
2522
2523         pipe_config->lane_count =
2524                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2525
2526         intel_dp_get_m_n(crtc, pipe_config);
2527
2528         if (port == PORT_A) {
2529                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2530                         pipe_config->port_clock = 162000;
2531                 else
2532                         pipe_config->port_clock = 270000;
2533         }
2534
2535         pipe_config->base.adjusted_mode.crtc_clock =
2536                 intel_dotclock_calculate(pipe_config->port_clock,
2537                                          &pipe_config->dp_m_n);
2538
2539         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2540             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2541                 /*
2542                  * This is a big fat ugly hack.
2543                  *
2544                  * Some machines in UEFI boot mode provide us a VBT that has 18
2545                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2546                  * unknown we fail to light up. Yet the same BIOS boots up with
2547                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2548                  * max, not what it tells us to use.
2549                  *
2550                  * Note: This will still be broken if the eDP panel is not lit
2551                  * up by the BIOS, and thus we can't get the mode at module
2552                  * load.
2553                  */
2554                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2555                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2556                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2557         }
2558 }
2559
2560 static void intel_disable_dp(struct intel_encoder *encoder,
2561                              struct intel_crtc_state *old_crtc_state,
2562                              struct drm_connector_state *old_conn_state)
2563 {
2564         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2566
2567         if (old_crtc_state->has_audio)
2568                 intel_audio_codec_disable(encoder);
2569
2570         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2571                 intel_psr_disable(intel_dp);
2572
2573         /* Make sure the panel is off before trying to change the mode. But also
2574          * ensure that we have vdd while we switch off the panel. */
2575         intel_edp_panel_vdd_on(intel_dp);
2576         intel_edp_backlight_off(intel_dp);
2577         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2578         intel_edp_panel_off(intel_dp);
2579
2580         /* disable the port before the pipe on g4x */
2581         if (INTEL_GEN(dev_priv) < 5)
2582                 intel_dp_link_down(intel_dp);
2583 }
2584
2585 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2586                                 struct intel_crtc_state *old_crtc_state,
2587                                 struct drm_connector_state *old_conn_state)
2588 {
2589         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2590         enum port port = dp_to_dig_port(intel_dp)->port;
2591
2592         intel_dp_link_down(intel_dp);
2593
2594         /* Only ilk+ has port A */
2595         if (port == PORT_A)
2596                 ironlake_edp_pll_off(intel_dp);
2597 }
2598
2599 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2600                                 struct intel_crtc_state *old_crtc_state,
2601                                 struct drm_connector_state *old_conn_state)
2602 {
2603         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2604
2605         intel_dp_link_down(intel_dp);
2606 }
2607
2608 static void chv_post_disable_dp(struct intel_encoder *encoder,
2609                                 struct intel_crtc_state *old_crtc_state,
2610                                 struct drm_connector_state *old_conn_state)
2611 {
2612         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2613         struct drm_device *dev = encoder->base.dev;
2614         struct drm_i915_private *dev_priv = to_i915(dev);
2615
2616         intel_dp_link_down(intel_dp);
2617
2618         mutex_lock(&dev_priv->sb_lock);
2619
2620         /* Assert data lane reset */
2621         chv_data_lane_soft_reset(encoder, true);
2622
2623         mutex_unlock(&dev_priv->sb_lock);
2624 }
2625
2626 static void
2627 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2628                          uint32_t *DP,
2629                          uint8_t dp_train_pat)
2630 {
2631         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2632         struct drm_device *dev = intel_dig_port->base.base.dev;
2633         struct drm_i915_private *dev_priv = to_i915(dev);
2634         enum port port = intel_dig_port->port;
2635
2636         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2637                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2638                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2639
2640         if (HAS_DDI(dev_priv)) {
2641                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2642
2643                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2644                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2645                 else
2646                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2647
2648                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2649                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2650                 case DP_TRAINING_PATTERN_DISABLE:
2651                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2652
2653                         break;
2654                 case DP_TRAINING_PATTERN_1:
2655                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2656                         break;
2657                 case DP_TRAINING_PATTERN_2:
2658                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2659                         break;
2660                 case DP_TRAINING_PATTERN_3:
2661                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2662                         break;
2663                 }
2664                 I915_WRITE(DP_TP_CTL(port), temp);
2665
2666         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2667                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2668                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2669
2670                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2671                 case DP_TRAINING_PATTERN_DISABLE:
2672                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2673                         break;
2674                 case DP_TRAINING_PATTERN_1:
2675                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2676                         break;
2677                 case DP_TRAINING_PATTERN_2:
2678                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2679                         break;
2680                 case DP_TRAINING_PATTERN_3:
2681                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2682                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2683                         break;
2684                 }
2685
2686         } else {
2687                 if (IS_CHERRYVIEW(dev_priv))
2688                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2689                 else
2690                         *DP &= ~DP_LINK_TRAIN_MASK;
2691
2692                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2693                 case DP_TRAINING_PATTERN_DISABLE:
2694                         *DP |= DP_LINK_TRAIN_OFF;
2695                         break;
2696                 case DP_TRAINING_PATTERN_1:
2697                         *DP |= DP_LINK_TRAIN_PAT_1;
2698                         break;
2699                 case DP_TRAINING_PATTERN_2:
2700                         *DP |= DP_LINK_TRAIN_PAT_2;
2701                         break;
2702                 case DP_TRAINING_PATTERN_3:
2703                         if (IS_CHERRYVIEW(dev_priv)) {
2704                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2705                         } else {
2706                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2707                                 *DP |= DP_LINK_TRAIN_PAT_2;
2708                         }
2709                         break;
2710                 }
2711         }
2712 }
2713
2714 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2715                                  struct intel_crtc_state *old_crtc_state)
2716 {
2717         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2718         struct drm_i915_private *dev_priv = to_i915(dev);
2719
2720         /* enable with pattern 1 (as per spec) */
2721
2722         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2723
2724         /*
2725          * Magic for VLV/CHV. We _must_ first set up the register
2726          * without actually enabling the port, and then do another
2727          * write to enable the port. Otherwise link training will
2728          * fail when the power sequencer is freshly used for this port.
2729          */
2730         intel_dp->DP |= DP_PORT_EN;
2731         if (old_crtc_state->has_audio)
2732                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2733
2734         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2735         POSTING_READ(intel_dp->output_reg);
2736 }
2737
2738 static void intel_enable_dp(struct intel_encoder *encoder,
2739                             struct intel_crtc_state *pipe_config,
2740                             struct drm_connector_state *conn_state)
2741 {
2742         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2743         struct drm_device *dev = encoder->base.dev;
2744         struct drm_i915_private *dev_priv = to_i915(dev);
2745         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2746         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2747         enum pipe pipe = crtc->pipe;
2748
2749         if (WARN_ON(dp_reg & DP_PORT_EN))
2750                 return;
2751
2752         pps_lock(intel_dp);
2753
2754         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2755                 vlv_init_panel_power_sequencer(intel_dp);
2756
2757         intel_dp_enable_port(intel_dp, pipe_config);
2758
2759         edp_panel_vdd_on(intel_dp);
2760         edp_panel_on(intel_dp);
2761         edp_panel_vdd_off(intel_dp, true);
2762
2763         pps_unlock(intel_dp);
2764
2765         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2766                 unsigned int lane_mask = 0x0;
2767
2768                 if (IS_CHERRYVIEW(dev_priv))
2769                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2770
2771                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2772                                     lane_mask);
2773         }
2774
2775         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2776         intel_dp_start_link_train(intel_dp);
2777         intel_dp_stop_link_train(intel_dp);
2778
2779         if (pipe_config->has_audio) {
2780                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2781                                  pipe_name(pipe));
2782                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2783         }
2784 }
2785
2786 static void g4x_enable_dp(struct intel_encoder *encoder,
2787                           struct intel_crtc_state *pipe_config,
2788                           struct drm_connector_state *conn_state)
2789 {
2790         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2791
2792         intel_enable_dp(encoder, pipe_config, conn_state);
2793         intel_edp_backlight_on(intel_dp);
2794 }
2795
2796 static void vlv_enable_dp(struct intel_encoder *encoder,
2797                           struct intel_crtc_state *pipe_config,
2798                           struct drm_connector_state *conn_state)
2799 {
2800         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2801
2802         intel_edp_backlight_on(intel_dp);
2803         intel_psr_enable(intel_dp);
2804 }
2805
2806 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2807                               struct intel_crtc_state *pipe_config,
2808                               struct drm_connector_state *conn_state)
2809 {
2810         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2811         enum port port = dp_to_dig_port(intel_dp)->port;
2812
2813         intel_dp_prepare(encoder, pipe_config);
2814
2815         /* Only ilk+ has port A */
2816         if (port == PORT_A)
2817                 ironlake_edp_pll_on(intel_dp, pipe_config);
2818 }
2819
2820 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2821 {
2822         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2823         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2824         enum pipe pipe = intel_dp->pps_pipe;
2825         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2826
2827         edp_panel_vdd_off_sync(intel_dp);
2828
2829         /*
2830          * VLV seems to get confused when multiple power seqeuencers
2831          * have the same port selected (even if only one has power/vdd
2832          * enabled). The failure manifests as vlv_wait_port_ready() failing
2833          * CHV on the other hand doesn't seem to mind having the same port
2834          * selected in multiple power seqeuencers, but let's clear the
2835          * port select always when logically disconnecting a power sequencer
2836          * from a port.
2837          */
2838         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2839                       pipe_name(pipe), port_name(intel_dig_port->port));
2840         I915_WRITE(pp_on_reg, 0);
2841         POSTING_READ(pp_on_reg);
2842
2843         intel_dp->pps_pipe = INVALID_PIPE;
2844 }
2845
2846 static void vlv_steal_power_sequencer(struct drm_device *dev,
2847                                       enum pipe pipe)
2848 {
2849         struct drm_i915_private *dev_priv = to_i915(dev);
2850         struct intel_encoder *encoder;
2851
2852         lockdep_assert_held(&dev_priv->pps_mutex);
2853
2854         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2855                 return;
2856
2857         for_each_intel_encoder(dev, encoder) {
2858                 struct intel_dp *intel_dp;
2859                 enum port port;
2860
2861                 if (encoder->type != INTEL_OUTPUT_EDP)
2862                         continue;
2863
2864                 intel_dp = enc_to_intel_dp(&encoder->base);
2865                 port = dp_to_dig_port(intel_dp)->port;
2866
2867                 if (intel_dp->pps_pipe != pipe)
2868                         continue;
2869
2870                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2871                               pipe_name(pipe), port_name(port));
2872
2873                 WARN(encoder->base.crtc,
2874                      "stealing pipe %c power sequencer from active eDP port %c\n",
2875                      pipe_name(pipe), port_name(port));
2876
2877                 /* make sure vdd is off before we steal it */
2878                 vlv_detach_power_sequencer(intel_dp);
2879         }
2880 }
2881
2882 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2883 {
2884         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2885         struct intel_encoder *encoder = &intel_dig_port->base;
2886         struct drm_device *dev = encoder->base.dev;
2887         struct drm_i915_private *dev_priv = to_i915(dev);
2888         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2889
2890         lockdep_assert_held(&dev_priv->pps_mutex);
2891
2892         if (!is_edp(intel_dp))
2893                 return;
2894
2895         if (intel_dp->pps_pipe == crtc->pipe)
2896                 return;
2897
2898         /*
2899          * If another power sequencer was being used on this
2900          * port previously make sure to turn off vdd there while
2901          * we still have control of it.
2902          */
2903         if (intel_dp->pps_pipe != INVALID_PIPE)
2904                 vlv_detach_power_sequencer(intel_dp);
2905
2906         /*
2907          * We may be stealing the power
2908          * sequencer from another port.
2909          */
2910         vlv_steal_power_sequencer(dev, crtc->pipe);
2911
2912         /* now it's all ours */
2913         intel_dp->pps_pipe = crtc->pipe;
2914
2915         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2916                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2917
2918         /* init power sequencer on this pipe and port */
2919         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2920         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2921 }
2922
2923 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2924                               struct intel_crtc_state *pipe_config,
2925                               struct drm_connector_state *conn_state)
2926 {
2927         vlv_phy_pre_encoder_enable(encoder);
2928
2929         intel_enable_dp(encoder, pipe_config, conn_state);
2930 }
2931
2932 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2933                                   struct intel_crtc_state *pipe_config,
2934                                   struct drm_connector_state *conn_state)
2935 {
2936         intel_dp_prepare(encoder, pipe_config);
2937
2938         vlv_phy_pre_pll_enable(encoder);
2939 }
2940
2941 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2942                               struct intel_crtc_state *pipe_config,
2943                               struct drm_connector_state *conn_state)
2944 {
2945         chv_phy_pre_encoder_enable(encoder);
2946
2947         intel_enable_dp(encoder, pipe_config, conn_state);
2948
2949         /* Second common lane will stay alive on its own now */
2950         chv_phy_release_cl2_override(encoder);
2951 }
2952
2953 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2954                                   struct intel_crtc_state *pipe_config,
2955                                   struct drm_connector_state *conn_state)
2956 {
2957         intel_dp_prepare(encoder, pipe_config);
2958
2959         chv_phy_pre_pll_enable(encoder);
2960 }
2961
2962 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2963                                     struct intel_crtc_state *pipe_config,
2964                                     struct drm_connector_state *conn_state)
2965 {
2966         chv_phy_post_pll_disable(encoder);
2967 }
2968
2969 /*
2970  * Fetch AUX CH registers 0x202 - 0x207 which contain
2971  * link status information
2972  */
2973 bool
2974 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2975 {
2976         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2977                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2978 }
2979
2980 /* These are source-specific values. */
2981 uint8_t
2982 intel_dp_voltage_max(struct intel_dp *intel_dp)
2983 {
2984         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2985         enum port port = dp_to_dig_port(intel_dp)->port;
2986
2987         if (IS_BROXTON(dev_priv))
2988                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2989         else if (INTEL_GEN(dev_priv) >= 9) {
2990                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2991                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2992                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2993         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2994                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2995         else if (IS_GEN7(dev_priv) && port == PORT_A)
2996                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2997         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2998                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2999         else
3000                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3001 }
3002
3003 uint8_t
3004 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3005 {
3006         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3007         enum port port = dp_to_dig_port(intel_dp)->port;
3008
3009         if (INTEL_GEN(dev_priv) >= 9) {
3010                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3011                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3012                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3013                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3014                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3016                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3017                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3018                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3019                 default:
3020                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3021                 }
3022         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3023                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3024                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3025                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3026                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3027                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3029                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3030                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3031                 default:
3032                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3033                 }
3034         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3035                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3037                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3038                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3039                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3040                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3041                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3042                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3043                 default:
3044                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3045                 }
3046         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3047                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3048                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3049                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3051                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3052                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3053                 default:
3054                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3055                 }
3056         } else {
3057                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3058                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3059                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3060                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3061                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3062                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3063                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3064                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3065                 default:
3066                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3067                 }
3068         }
3069 }
3070
3071 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3072 {
3073         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3074         unsigned long demph_reg_value, preemph_reg_value,
3075                 uniqtranscale_reg_value;
3076         uint8_t train_set = intel_dp->train_set[0];
3077
3078         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3079         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3080                 preemph_reg_value = 0x0004000;
3081                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3082                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3083                         demph_reg_value = 0x2B405555;
3084                         uniqtranscale_reg_value = 0x552AB83A;
3085                         break;
3086                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3087                         demph_reg_value = 0x2B404040;
3088                         uniqtranscale_reg_value = 0x5548B83A;
3089                         break;
3090                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3091                         demph_reg_value = 0x2B245555;
3092                         uniqtranscale_reg_value = 0x5560B83A;
3093                         break;
3094                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3095                         demph_reg_value = 0x2B405555;
3096                         uniqtranscale_reg_value = 0x5598DA3A;
3097                         break;
3098                 default:
3099                         return 0;
3100                 }
3101                 break;
3102         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3103                 preemph_reg_value = 0x0002000;
3104                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3105                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3106                         demph_reg_value = 0x2B404040;
3107                         uniqtranscale_reg_value = 0x5552B83A;
3108                         break;
3109                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3110                         demph_reg_value = 0x2B404848;
3111                         uniqtranscale_reg_value = 0x5580B83A;
3112                         break;
3113                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3114                         demph_reg_value = 0x2B404040;
3115                         uniqtranscale_reg_value = 0x55ADDA3A;
3116                         break;
3117                 default:
3118                         return 0;
3119                 }
3120                 break;
3121         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3122                 preemph_reg_value = 0x0000000;
3123                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3124                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3125                         demph_reg_value = 0x2B305555;
3126                         uniqtranscale_reg_value = 0x5570B83A;
3127                         break;
3128                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3129                         demph_reg_value = 0x2B2B4040;
3130                         uniqtranscale_reg_value = 0x55ADDA3A;
3131                         break;
3132                 default:
3133                         return 0;
3134                 }
3135                 break;
3136         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3137                 preemph_reg_value = 0x0006000;
3138                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3139                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3140                         demph_reg_value = 0x1B405555;
3141                         uniqtranscale_reg_value = 0x55ADDA3A;
3142                         break;
3143                 default:
3144                         return 0;
3145                 }
3146                 break;
3147         default:
3148                 return 0;
3149         }
3150
3151         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3152                                  uniqtranscale_reg_value, 0);
3153
3154         return 0;
3155 }
3156
3157 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3158 {
3159         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3160         u32 deemph_reg_value, margin_reg_value;
3161         bool uniq_trans_scale = false;
3162         uint8_t train_set = intel_dp->train_set[0];
3163
3164         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3165         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3166                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3167                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3168                         deemph_reg_value = 128;
3169                         margin_reg_value = 52;
3170                         break;
3171                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3172                         deemph_reg_value = 128;
3173                         margin_reg_value = 77;
3174                         break;
3175                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3176                         deemph_reg_value = 128;
3177                         margin_reg_value = 102;
3178                         break;
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3180                         deemph_reg_value = 128;
3181                         margin_reg_value = 154;
3182                         uniq_trans_scale = true;
3183                         break;
3184                 default:
3185                         return 0;
3186                 }
3187                 break;
3188         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3189                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3191                         deemph_reg_value = 85;
3192                         margin_reg_value = 78;
3193                         break;
3194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3195                         deemph_reg_value = 85;
3196                         margin_reg_value = 116;
3197                         break;
3198                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3199                         deemph_reg_value = 85;
3200                         margin_reg_value = 154;
3201                         break;
3202                 default:
3203                         return 0;
3204                 }
3205                 break;
3206         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3207                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3209                         deemph_reg_value = 64;
3210                         margin_reg_value = 104;
3211                         break;
3212                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3213                         deemph_reg_value = 64;
3214                         margin_reg_value = 154;
3215                         break;
3216                 default:
3217                         return 0;
3218                 }
3219                 break;
3220         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3221                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3222                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3223                         deemph_reg_value = 43;
3224                         margin_reg_value = 154;
3225                         break;
3226                 default:
3227                         return 0;
3228                 }
3229                 break;
3230         default:
3231                 return 0;
3232         }
3233
3234         chv_set_phy_signal_level(encoder, deemph_reg_value,
3235                                  margin_reg_value, uniq_trans_scale);
3236
3237         return 0;
3238 }
3239
3240 static uint32_t
3241 gen4_signal_levels(uint8_t train_set)
3242 {
3243         uint32_t        signal_levels = 0;
3244
3245         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3246         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3247         default:
3248                 signal_levels |= DP_VOLTAGE_0_4;
3249                 break;
3250         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3251                 signal_levels |= DP_VOLTAGE_0_6;
3252                 break;
3253         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3254                 signal_levels |= DP_VOLTAGE_0_8;
3255                 break;
3256         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3257                 signal_levels |= DP_VOLTAGE_1_2;
3258                 break;
3259         }
3260         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3261         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3262         default:
3263                 signal_levels |= DP_PRE_EMPHASIS_0;
3264                 break;
3265         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3266                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3267                 break;
3268         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3269                 signal_levels |= DP_PRE_EMPHASIS_6;
3270                 break;
3271         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3272                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3273                 break;
3274         }
3275         return signal_levels;
3276 }
3277
3278 /* Gen6's DP voltage swing and pre-emphasis control */
3279 static uint32_t
3280 gen6_edp_signal_levels(uint8_t train_set)
3281 {
3282         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3283                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3284         switch (signal_levels) {
3285         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3286         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3287                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3288         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3289                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3290         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3291         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3292                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3293         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3294         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3295                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3296         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3297         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3298                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3299         default:
3300                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3301                               "0x%x\n", signal_levels);
3302                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3303         }
3304 }
3305
3306 /* Gen7's DP voltage swing and pre-emphasis control */
3307 static uint32_t
3308 gen7_edp_signal_levels(uint8_t train_set)
3309 {
3310         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3311                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3312         switch (signal_levels) {
3313         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3314                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3315         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3316                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3317         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3318                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3319
3320         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3321                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3322         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3323                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3324
3325         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3326                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3327         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3328                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3329
3330         default:
3331                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3332                               "0x%x\n", signal_levels);
3333                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3334         }
3335 }
3336
3337 void
3338 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3339 {
3340         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3341         enum port port = intel_dig_port->port;
3342         struct drm_device *dev = intel_dig_port->base.base.dev;
3343         struct drm_i915_private *dev_priv = to_i915(dev);
3344         uint32_t signal_levels, mask = 0;
3345         uint8_t train_set = intel_dp->train_set[0];
3346
3347         if (HAS_DDI(dev_priv)) {
3348                 signal_levels = ddi_signal_levels(intel_dp);
3349
3350                 if (IS_BROXTON(dev_priv))
3351                         signal_levels = 0;
3352                 else
3353                         mask = DDI_BUF_EMP_MASK;
3354         } else if (IS_CHERRYVIEW(dev_priv)) {
3355                 signal_levels = chv_signal_levels(intel_dp);
3356         } else if (IS_VALLEYVIEW(dev_priv)) {
3357                 signal_levels = vlv_signal_levels(intel_dp);
3358         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3359                 signal_levels = gen7_edp_signal_levels(train_set);
3360                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3361         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3362                 signal_levels = gen6_edp_signal_levels(train_set);
3363                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3364         } else {
3365                 signal_levels = gen4_signal_levels(train_set);
3366                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3367         }
3368
3369         if (mask)
3370                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3371
3372         DRM_DEBUG_KMS("Using vswing level %d\n",
3373                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3374         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3375                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3376                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3377
3378         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3379
3380         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3381         POSTING_READ(intel_dp->output_reg);
3382 }
3383
3384 void
3385 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3386                                        uint8_t dp_train_pat)
3387 {
3388         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3389         struct drm_i915_private *dev_priv =
3390                 to_i915(intel_dig_port->base.base.dev);
3391
3392         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3393
3394         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3395         POSTING_READ(intel_dp->output_reg);
3396 }
3397
3398 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3399 {
3400         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3401         struct drm_device *dev = intel_dig_port->base.base.dev;
3402         struct drm_i915_private *dev_priv = to_i915(dev);
3403         enum port port = intel_dig_port->port;
3404         uint32_t val;
3405
3406         if (!HAS_DDI(dev_priv))
3407                 return;
3408
3409         val = I915_READ(DP_TP_CTL(port));
3410         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3411         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3412         I915_WRITE(DP_TP_CTL(port), val);
3413
3414         /*
3415          * On PORT_A we can have only eDP in SST mode. There the only reason
3416          * we need to set idle transmission mode is to work around a HW issue
3417          * where we enable the pipe while not in idle link-training mode.
3418          * In this case there is requirement to wait for a minimum number of
3419          * idle patterns to be sent.
3420          */
3421         if (port == PORT_A)
3422                 return;
3423
3424         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3425                                     DP_TP_STATUS_IDLE_DONE,
3426                                     DP_TP_STATUS_IDLE_DONE,
3427                                     1))
3428                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3429 }
3430
3431 static void
3432 intel_dp_link_down(struct intel_dp *intel_dp)
3433 {
3434         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3435         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3436         enum port port = intel_dig_port->port;
3437         struct drm_device *dev = intel_dig_port->base.base.dev;
3438         struct drm_i915_private *dev_priv = to_i915(dev);
3439         uint32_t DP = intel_dp->DP;
3440
3441         if (WARN_ON(HAS_DDI(dev_priv)))
3442                 return;
3443
3444         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3445                 return;
3446
3447         DRM_DEBUG_KMS("\n");
3448
3449         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3450             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3451                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3452                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3453         } else {
3454                 if (IS_CHERRYVIEW(dev_priv))
3455                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3456                 else
3457                         DP &= ~DP_LINK_TRAIN_MASK;
3458                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3459         }
3460         I915_WRITE(intel_dp->output_reg, DP);
3461         POSTING_READ(intel_dp->output_reg);
3462
3463         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3464         I915_WRITE(intel_dp->output_reg, DP);
3465         POSTING_READ(intel_dp->output_reg);
3466
3467         /*
3468          * HW workaround for IBX, we need to move the port
3469          * to transcoder A after disabling it to allow the
3470          * matching HDMI port to be enabled on transcoder A.
3471          */
3472         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3473                 /*
3474                  * We get CPU/PCH FIFO underruns on the other pipe when
3475                  * doing the workaround. Sweep them under the rug.
3476                  */
3477                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3478                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3479
3480                 /* always enable with pattern 1 (as per spec) */
3481                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3482                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3483                 I915_WRITE(intel_dp->output_reg, DP);
3484                 POSTING_READ(intel_dp->output_reg);
3485
3486                 DP &= ~DP_PORT_EN;
3487                 I915_WRITE(intel_dp->output_reg, DP);
3488                 POSTING_READ(intel_dp->output_reg);
3489
3490                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3491                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3492                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3493         }
3494
3495         msleep(intel_dp->panel_power_down_delay);
3496
3497         intel_dp->DP = DP;
3498 }
3499
3500 bool
3501 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3502 {
3503         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3504                              sizeof(intel_dp->dpcd)) < 0)
3505                 return false; /* aux transfer failed */
3506
3507         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3508
3509         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3510 }
3511
3512 static bool
3513 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3514 {
3515         struct drm_i915_private *dev_priv =
3516                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3517
3518         /* this function is meant to be called only once */
3519         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3520
3521         if (!intel_dp_read_dpcd(intel_dp))
3522                 return false;
3523
3524         intel_dp_read_desc(intel_dp);
3525
3526         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3527                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3528                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3529
3530         /* Check if the panel supports PSR */
3531         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3532                          intel_dp->psr_dpcd,
3533                          sizeof(intel_dp->psr_dpcd));
3534         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3535                 dev_priv->psr.sink_support = true;
3536                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3537         }
3538
3539         if (INTEL_GEN(dev_priv) >= 9 &&
3540             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3541                 uint8_t frame_sync_cap;
3542
3543                 dev_priv->psr.sink_support = true;
3544                 drm_dp_dpcd_read(&intel_dp->aux,
3545                                  DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3546                                  &frame_sync_cap, 1);
3547                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3548                 /* PSR2 needs frame sync as well */
3549                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3550                 DRM_DEBUG_KMS("PSR2 %s on sink",
3551                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3552         }
3553
3554         /* Read the eDP Display control capabilities registers */
3555         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3556             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3557                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3558                              sizeof(intel_dp->edp_dpcd))
3559                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3560                               intel_dp->edp_dpcd);
3561
3562         /* Intermediate frequency support */
3563         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3564                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3565                 int i;
3566
3567                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3568                                 sink_rates, sizeof(sink_rates));
3569
3570                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3571                         int val = le16_to_cpu(sink_rates[i]);
3572
3573                         if (val == 0)
3574                                 break;
3575
3576                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3577                         intel_dp->sink_rates[i] = (val * 200) / 10;
3578                 }
3579                 intel_dp->num_sink_rates = i;
3580         }
3581
3582         return true;
3583 }
3584
3585
3586 static bool
3587 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3588 {
3589         if (!intel_dp_read_dpcd(intel_dp))
3590                 return false;
3591
3592         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3593                              &intel_dp->sink_count, 1) < 0)
3594                 return false;
3595
3596         /*
3597          * Sink count can change between short pulse hpd hence
3598          * a member variable in intel_dp will track any changes
3599          * between short pulse interrupts.
3600          */
3601         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3602
3603         /*
3604          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3605          * a dongle is present but no display. Unless we require to know
3606          * if a dongle is present or not, we don't need to update
3607          * downstream port information. So, an early return here saves
3608          * time from performing other operations which are not required.
3609          */
3610         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3611                 return false;
3612
3613         if (!drm_dp_is_branch(intel_dp->dpcd))
3614                 return true; /* native DP sink */
3615
3616         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3617                 return true; /* no per-port downstream info */
3618
3619         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3620                              intel_dp->downstream_ports,
3621                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3622                 return false; /* downstream port status fetch failed */
3623
3624         return true;
3625 }
3626
3627 static bool
3628 intel_dp_can_mst(struct intel_dp *intel_dp)
3629 {
3630         u8 buf[1];
3631
3632         if (!i915.enable_dp_mst)
3633                 return false;
3634
3635         if (!intel_dp->can_mst)
3636                 return false;
3637
3638         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3639                 return false;
3640
3641         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3642                 return false;
3643
3644         return buf[0] & DP_MST_CAP;
3645 }
3646
3647 static void
3648 intel_dp_configure_mst(struct intel_dp *intel_dp)
3649 {
3650         if (!i915.enable_dp_mst)
3651                 return;
3652
3653         if (!intel_dp->can_mst)
3654                 return;
3655
3656         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3657
3658         if (intel_dp->is_mst)
3659                 DRM_DEBUG_KMS("Sink is MST capable\n");
3660         else
3661                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3662
3663         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3664                                         intel_dp->is_mst);
3665 }
3666
3667 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3668 {
3669         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3670         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3671         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3672         u8 buf;
3673         int ret = 0;
3674         int count = 0;
3675         int attempts = 10;
3676
3677         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3678                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3679                 ret = -EIO;
3680                 goto out;
3681         }
3682
3683         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3684                                buf & ~DP_TEST_SINK_START) < 0) {
3685                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3686                 ret = -EIO;
3687                 goto out;
3688         }
3689
3690         do {
3691                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3692
3693                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3694                                       DP_TEST_SINK_MISC, &buf) < 0) {
3695                         ret = -EIO;
3696                         goto out;
3697                 }
3698                 count = buf & DP_TEST_COUNT_MASK;
3699         } while (--attempts && count);
3700
3701         if (attempts == 0) {
3702                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3703                 ret = -ETIMEDOUT;
3704         }
3705
3706  out:
3707         hsw_enable_ips(intel_crtc);
3708         return ret;
3709 }
3710
3711 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3712 {
3713         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3714         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3715         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3716         u8 buf;
3717         int ret;
3718
3719         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3720                 return -EIO;
3721
3722         if (!(buf & DP_TEST_CRC_SUPPORTED))
3723                 return -ENOTTY;
3724
3725         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3726                 return -EIO;
3727
3728         if (buf & DP_TEST_SINK_START) {
3729                 ret = intel_dp_sink_crc_stop(intel_dp);
3730                 if (ret)
3731                         return ret;
3732         }
3733
3734         hsw_disable_ips(intel_crtc);
3735
3736         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3737                                buf | DP_TEST_SINK_START) < 0) {
3738                 hsw_enable_ips(intel_crtc);
3739                 return -EIO;
3740         }
3741
3742         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3743         return 0;
3744 }
3745
3746 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3747 {
3748         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3749         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3750         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3751         u8 buf;
3752         int count, ret;
3753         int attempts = 6;
3754
3755         ret = intel_dp_sink_crc_start(intel_dp);
3756         if (ret)
3757                 return ret;
3758
3759         do {
3760                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3761
3762                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3763                                       DP_TEST_SINK_MISC, &buf) < 0) {
3764                         ret = -EIO;
3765                         goto stop;
3766                 }
3767                 count = buf & DP_TEST_COUNT_MASK;
3768
3769         } while (--attempts && count == 0);
3770
3771         if (attempts == 0) {
3772                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3773                 ret = -ETIMEDOUT;
3774                 goto stop;
3775         }
3776
3777         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3778                 ret = -EIO;
3779                 goto stop;
3780         }
3781
3782 stop:
3783         intel_dp_sink_crc_stop(intel_dp);
3784         return ret;
3785 }
3786
3787 static bool
3788 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3789 {
3790         return drm_dp_dpcd_read(&intel_dp->aux,
3791                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3792                                        sink_irq_vector, 1) == 1;
3793 }
3794
3795 static bool
3796 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3797 {
3798         int ret;
3799
3800         ret = drm_dp_dpcd_read(&intel_dp->aux,
3801                                              DP_SINK_COUNT_ESI,
3802                                              sink_irq_vector, 14);
3803         if (ret != 14)
3804                 return false;
3805
3806         return true;
3807 }
3808
3809 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3810 {
3811         uint8_t test_result = DP_TEST_ACK;
3812         return test_result;
3813 }
3814
3815 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3816 {
3817         uint8_t test_result = DP_TEST_NAK;
3818         return test_result;
3819 }
3820
3821 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3822 {
3823         uint8_t test_result = DP_TEST_NAK;
3824         struct intel_connector *intel_connector = intel_dp->attached_connector;
3825         struct drm_connector *connector = &intel_connector->base;
3826
3827         if (intel_connector->detect_edid == NULL ||
3828             connector->edid_corrupt ||
3829             intel_dp->aux.i2c_defer_count > 6) {
3830                 /* Check EDID read for NACKs, DEFERs and corruption
3831                  * (DP CTS 1.2 Core r1.1)
3832                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3833                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3834                  *    4.2.2.6 : EDID corruption detected
3835                  * Use failsafe mode for all cases
3836                  */
3837                 if (intel_dp->aux.i2c_nack_count > 0 ||
3838                         intel_dp->aux.i2c_defer_count > 0)
3839                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3840                                       intel_dp->aux.i2c_nack_count,
3841                                       intel_dp->aux.i2c_defer_count);
3842                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3843         } else {
3844                 struct edid *block = intel_connector->detect_edid;
3845
3846                 /* We have to write the checksum
3847                  * of the last block read
3848                  */
3849                 block += intel_connector->detect_edid->extensions;
3850
3851                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3852                                         DP_TEST_EDID_CHECKSUM,
3853                                         &block->checksum,
3854                                         1))
3855                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3856
3857                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3858                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3859         }
3860
3861         /* Set test active flag here so userspace doesn't interrupt things */
3862         intel_dp->compliance_test_active = 1;
3863
3864         return test_result;
3865 }
3866
3867 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3868 {
3869         uint8_t test_result = DP_TEST_NAK;
3870         return test_result;
3871 }
3872
3873 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3874 {
3875         uint8_t response = DP_TEST_NAK;
3876         uint8_t rxdata = 0;
3877         int status = 0;
3878
3879         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3880         if (status <= 0) {
3881                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3882                 goto update_status;
3883         }
3884
3885         switch (rxdata) {
3886         case DP_TEST_LINK_TRAINING:
3887                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3888                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3889                 response = intel_dp_autotest_link_training(intel_dp);
3890                 break;
3891         case DP_TEST_LINK_VIDEO_PATTERN:
3892                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3893                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3894                 response = intel_dp_autotest_video_pattern(intel_dp);
3895                 break;
3896         case DP_TEST_LINK_EDID_READ:
3897                 DRM_DEBUG_KMS("EDID test requested\n");
3898                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3899                 response = intel_dp_autotest_edid(intel_dp);
3900                 break;
3901         case DP_TEST_LINK_PHY_TEST_PATTERN:
3902                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3903                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3904                 response = intel_dp_autotest_phy_pattern(intel_dp);
3905                 break;
3906         default:
3907                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3908                 break;
3909         }
3910
3911 update_status:
3912         status = drm_dp_dpcd_write(&intel_dp->aux,
3913                                    DP_TEST_RESPONSE,
3914                                    &response, 1);
3915         if (status <= 0)
3916                 DRM_DEBUG_KMS("Could not write test response to sink\n");
3917 }
3918
3919 static int
3920 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3921 {
3922         bool bret;
3923
3924         if (intel_dp->is_mst) {
3925                 u8 esi[16] = { 0 };
3926                 int ret = 0;
3927                 int retry;
3928                 bool handled;
3929                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3930 go_again:
3931                 if (bret == true) {
3932
3933                         /* check link status - esi[10] = 0x200c */
3934                         if (intel_dp->active_mst_links &&
3935                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3936                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3937                                 intel_dp_start_link_train(intel_dp);
3938                                 intel_dp_stop_link_train(intel_dp);
3939                         }
3940
3941                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3942                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3943
3944                         if (handled) {
3945                                 for (retry = 0; retry < 3; retry++) {
3946                                         int wret;
3947                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3948                                                                  DP_SINK_COUNT_ESI+1,
3949                                                                  &esi[1], 3);
3950                                         if (wret == 3) {
3951                                                 break;
3952                                         }
3953                                 }
3954
3955                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3956                                 if (bret == true) {
3957                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3958                                         goto go_again;
3959                                 }
3960                         } else
3961                                 ret = 0;
3962
3963                         return ret;
3964                 } else {
3965                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3966                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3967                         intel_dp->is_mst = false;
3968                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3969                         /* send a hotplug event */
3970                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3971                 }
3972         }
3973         return -EINVAL;
3974 }
3975
3976 static void
3977 intel_dp_retrain_link(struct intel_dp *intel_dp)
3978 {
3979         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3981         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3982
3983         /* Suppress underruns caused by re-training */
3984         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3985         if (crtc->config->has_pch_encoder)
3986                 intel_set_pch_fifo_underrun_reporting(dev_priv,
3987                                                       intel_crtc_pch_transcoder(crtc), false);
3988
3989         intel_dp_start_link_train(intel_dp);
3990         intel_dp_stop_link_train(intel_dp);
3991
3992         /* Keep underrun reporting disabled until things are stable */
3993         intel_wait_for_vblank(dev_priv, crtc->pipe);
3994
3995         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3996         if (crtc->config->has_pch_encoder)
3997                 intel_set_pch_fifo_underrun_reporting(dev_priv,
3998                                                       intel_crtc_pch_transcoder(crtc), true);
3999 }
4000
4001 static void
4002 intel_dp_check_link_status(struct intel_dp *intel_dp)
4003 {
4004         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4005         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4006         u8 link_status[DP_LINK_STATUS_SIZE];
4007
4008         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4009
4010         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4011                 DRM_ERROR("Failed to get link status\n");
4012                 return;
4013         }
4014
4015         if (!intel_encoder->base.crtc)
4016                 return;
4017
4018         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4019                 return;
4020
4021         /* FIXME: we need to synchronize this sort of stuff with hardware
4022          * readout */
4023         if (WARN_ON_ONCE(!intel_dp->lane_count))
4024                 return;
4025
4026         /* if link training is requested we should perform it always */
4027         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4028             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4029                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4030                               intel_encoder->base.name);
4031
4032                 intel_dp_retrain_link(intel_dp);
4033         }
4034 }
4035
4036 /*
4037  * According to DP spec
4038  * 5.1.2:
4039  *  1. Read DPCD
4040  *  2. Configure link according to Receiver Capabilities
4041  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4042  *  4. Check link status on receipt of hot-plug interrupt
4043  *
4044  * intel_dp_short_pulse -  handles short pulse interrupts
4045  * when full detection is not required.
4046  * Returns %true if short pulse is handled and full detection
4047  * is NOT required and %false otherwise.
4048  */
4049 static bool
4050 intel_dp_short_pulse(struct intel_dp *intel_dp)
4051 {
4052         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4053         u8 sink_irq_vector = 0;
4054         u8 old_sink_count = intel_dp->sink_count;
4055         bool ret;
4056
4057         /*
4058          * Clearing compliance test variables to allow capturing
4059          * of values for next automated test request.
4060          */
4061         intel_dp->compliance_test_active = 0;
4062         intel_dp->compliance_test_type = 0;
4063         intel_dp->compliance_test_data = 0;
4064
4065         /*
4066          * Now read the DPCD to see if it's actually running
4067          * If the current value of sink count doesn't match with
4068          * the value that was stored earlier or dpcd read failed
4069          * we need to do full detection
4070          */
4071         ret = intel_dp_get_dpcd(intel_dp);
4072
4073         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4074                 /* No need to proceed if we are going to do full detect */
4075                 return false;
4076         }
4077
4078         /* Try to read the source of the interrupt */
4079         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4080             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4081             sink_irq_vector != 0) {
4082                 /* Clear interrupt source */
4083                 drm_dp_dpcd_writeb(&intel_dp->aux,
4084                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4085                                    sink_irq_vector);
4086
4087                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4088                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4089                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4090                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4091         }
4092
4093         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4094         intel_dp_check_link_status(intel_dp);
4095         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4096
4097         return true;
4098 }
4099
4100 /* XXX this is probably wrong for multiple downstream ports */
4101 static enum drm_connector_status
4102 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4103 {
4104         uint8_t *dpcd = intel_dp->dpcd;
4105         uint8_t type;
4106
4107         if (!intel_dp_get_dpcd(intel_dp))
4108                 return connector_status_disconnected;
4109
4110         if (is_edp(intel_dp))
4111                 return connector_status_connected;
4112
4113         /* if there's no downstream port, we're done */
4114         if (!drm_dp_is_branch(dpcd))
4115                 return connector_status_connected;
4116
4117         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4118         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4119             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4120
4121                 return intel_dp->sink_count ?
4122                 connector_status_connected : connector_status_disconnected;
4123         }
4124
4125         if (intel_dp_can_mst(intel_dp))
4126                 return connector_status_connected;
4127
4128         /* If no HPD, poke DDC gently */
4129         if (drm_probe_ddc(&intel_dp->aux.ddc))
4130                 return connector_status_connected;
4131
4132         /* Well we tried, say unknown for unreliable port types */
4133         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4134                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4135                 if (type == DP_DS_PORT_TYPE_VGA ||
4136                     type == DP_DS_PORT_TYPE_NON_EDID)
4137                         return connector_status_unknown;
4138         } else {
4139                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4140                         DP_DWN_STRM_PORT_TYPE_MASK;
4141                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4142                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4143                         return connector_status_unknown;
4144         }
4145
4146         /* Anything else is out of spec, warn and ignore */
4147         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4148         return connector_status_disconnected;
4149 }
4150
4151 static enum drm_connector_status
4152 edp_detect(struct intel_dp *intel_dp)
4153 {
4154         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4155         enum drm_connector_status status;
4156
4157         status = intel_panel_detect(dev);
4158         if (status == connector_status_unknown)
4159                 status = connector_status_connected;
4160
4161         return status;
4162 }
4163
4164 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4165                                        struct intel_digital_port *port)
4166 {
4167         u32 bit;
4168
4169         switch (port->port) {
4170         case PORT_A:
4171                 return true;
4172         case PORT_B:
4173                 bit = SDE_PORTB_HOTPLUG;
4174                 break;
4175         case PORT_C:
4176                 bit = SDE_PORTC_HOTPLUG;
4177                 break;
4178         case PORT_D:
4179                 bit = SDE_PORTD_HOTPLUG;
4180                 break;
4181         default:
4182                 MISSING_CASE(port->port);
4183                 return false;
4184         }
4185
4186         return I915_READ(SDEISR) & bit;
4187 }
4188
4189 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4190                                        struct intel_digital_port *port)
4191 {
4192         u32 bit;
4193
4194         switch (port->port) {
4195         case PORT_A:
4196                 return true;
4197         case PORT_B:
4198                 bit = SDE_PORTB_HOTPLUG_CPT;
4199                 break;
4200         case PORT_C:
4201                 bit = SDE_PORTC_HOTPLUG_CPT;
4202                 break;
4203         case PORT_D:
4204                 bit = SDE_PORTD_HOTPLUG_CPT;
4205                 break;
4206         case PORT_E:
4207                 bit = SDE_PORTE_HOTPLUG_SPT;
4208                 break;
4209         default:
4210                 MISSING_CASE(port->port);
4211                 return false;
4212         }
4213
4214         return I915_READ(SDEISR) & bit;
4215 }
4216
4217 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4218                                        struct intel_digital_port *port)
4219 {
4220         u32 bit;
4221
4222         switch (port->port) {
4223         case PORT_B:
4224                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4225                 break;
4226         case PORT_C:
4227                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4228                 break;
4229         case PORT_D:
4230                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4231                 break;
4232         default:
4233                 MISSING_CASE(port->port);
4234                 return false;
4235         }
4236
4237         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4238 }
4239
4240 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4241                                         struct intel_digital_port *port)
4242 {
4243         u32 bit;
4244
4245         switch (port->port) {
4246         case PORT_B:
4247                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4248                 break;
4249         case PORT_C:
4250                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4251                 break;
4252         case PORT_D:
4253                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4254                 break;
4255         default:
4256                 MISSING_CASE(port->port);
4257                 return false;
4258         }
4259
4260         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4261 }
4262
4263 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4264                                        struct intel_digital_port *intel_dig_port)
4265 {
4266         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4267         enum port port;
4268         u32 bit;
4269
4270         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4271         switch (port) {
4272         case PORT_A:
4273                 bit = BXT_DE_PORT_HP_DDIA;
4274                 break;
4275         case PORT_B:
4276                 bit = BXT_DE_PORT_HP_DDIB;
4277                 break;
4278         case PORT_C:
4279                 bit = BXT_DE_PORT_HP_DDIC;
4280                 break;
4281         default:
4282                 MISSING_CASE(port);
4283                 return false;
4284         }
4285
4286         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4287 }
4288
4289 /*
4290  * intel_digital_port_connected - is the specified port connected?
4291  * @dev_priv: i915 private structure
4292  * @port: the port to test
4293  *
4294  * Return %true if @port is connected, %false otherwise.
4295  */
4296 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4297                                          struct intel_digital_port *port)
4298 {
4299         if (HAS_PCH_IBX(dev_priv))
4300                 return ibx_digital_port_connected(dev_priv, port);
4301         else if (HAS_PCH_SPLIT(dev_priv))
4302                 return cpt_digital_port_connected(dev_priv, port);
4303         else if (IS_BROXTON(dev_priv))
4304                 return bxt_digital_port_connected(dev_priv, port);
4305         else if (IS_GM45(dev_priv))
4306                 return gm45_digital_port_connected(dev_priv, port);
4307         else
4308                 return g4x_digital_port_connected(dev_priv, port);
4309 }
4310
4311 static struct edid *
4312 intel_dp_get_edid(struct intel_dp *intel_dp)
4313 {
4314         struct intel_connector *intel_connector = intel_dp->attached_connector;
4315
4316         /* use cached edid if we have one */
4317         if (intel_connector->edid) {
4318                 /* invalid edid */
4319                 if (IS_ERR(intel_connector->edid))
4320                         return NULL;
4321
4322                 return drm_edid_duplicate(intel_connector->edid);
4323         } else
4324                 return drm_get_edid(&intel_connector->base,
4325                                     &intel_dp->aux.ddc);
4326 }
4327
4328 static void
4329 intel_dp_set_edid(struct intel_dp *intel_dp)
4330 {
4331         struct intel_connector *intel_connector = intel_dp->attached_connector;
4332         struct edid *edid;
4333
4334         intel_dp_unset_edid(intel_dp);
4335         edid = intel_dp_get_edid(intel_dp);
4336         intel_connector->detect_edid = edid;
4337
4338         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4339                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4340         else
4341                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4342 }
4343
4344 static void
4345 intel_dp_unset_edid(struct intel_dp *intel_dp)
4346 {
4347         struct intel_connector *intel_connector = intel_dp->attached_connector;
4348
4349         kfree(intel_connector->detect_edid);
4350         intel_connector->detect_edid = NULL;
4351
4352         intel_dp->has_audio = false;
4353 }
4354
4355 static enum drm_connector_status
4356 intel_dp_long_pulse(struct intel_connector *intel_connector)
4357 {
4358         struct drm_connector *connector = &intel_connector->base;
4359         struct intel_dp *intel_dp = intel_attached_dp(connector);
4360         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4361         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4362         struct drm_device *dev = connector->dev;
4363         enum drm_connector_status status;
4364         enum intel_display_power_domain power_domain;
4365         u8 sink_irq_vector = 0;
4366
4367         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4368         intel_display_power_get(to_i915(dev), power_domain);
4369
4370         /* Can't disconnect eDP, but you can close the lid... */
4371         if (is_edp(intel_dp))
4372                 status = edp_detect(intel_dp);
4373         else if (intel_digital_port_connected(to_i915(dev),
4374                                               dp_to_dig_port(intel_dp)))
4375                 status = intel_dp_detect_dpcd(intel_dp);
4376         else
4377                 status = connector_status_disconnected;
4378
4379         if (status == connector_status_disconnected) {
4380                 intel_dp->compliance_test_active = 0;
4381                 intel_dp->compliance_test_type = 0;
4382                 intel_dp->compliance_test_data = 0;
4383
4384                 if (intel_dp->is_mst) {
4385                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4386                                       intel_dp->is_mst,
4387                                       intel_dp->mst_mgr.mst_state);
4388                         intel_dp->is_mst = false;
4389                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4390                                                         intel_dp->is_mst);
4391                 }
4392
4393                 goto out;
4394         }
4395
4396         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4397                 intel_encoder->type = INTEL_OUTPUT_DP;
4398
4399         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4400                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4401                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4402
4403         intel_dp_print_rates(intel_dp);
4404
4405         intel_dp_read_desc(intel_dp);
4406
4407         intel_dp_configure_mst(intel_dp);
4408
4409         if (intel_dp->is_mst) {
4410                 /*
4411                  * If we are in MST mode then this connector
4412                  * won't appear connected or have anything
4413                  * with EDID on it
4414                  */
4415                 status = connector_status_disconnected;
4416                 goto out;
4417         } else if (connector->status == connector_status_connected) {
4418                 /*
4419                  * If display was connected already and is still connected
4420                  * check links status, there has been known issues of
4421                  * link loss triggerring long pulse!!!!
4422                  */
4423                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4424                 intel_dp_check_link_status(intel_dp);
4425                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4426                 goto out;
4427         }
4428
4429         /*
4430          * Clearing NACK and defer counts to get their exact values
4431          * while reading EDID which are required by Compliance tests
4432          * 4.2.2.4 and 4.2.2.5
4433          */
4434         intel_dp->aux.i2c_nack_count = 0;
4435         intel_dp->aux.i2c_defer_count = 0;
4436
4437         intel_dp_set_edid(intel_dp);
4438         if (is_edp(intel_dp) || intel_connector->detect_edid)
4439                 status = connector_status_connected;
4440         intel_dp->detect_done = true;
4441
4442         /* Try to read the source of the interrupt */
4443         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4444             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4445             sink_irq_vector != 0) {
4446                 /* Clear interrupt source */
4447                 drm_dp_dpcd_writeb(&intel_dp->aux,
4448                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4449                                    sink_irq_vector);
4450
4451                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4452                         intel_dp_handle_test_request(intel_dp);
4453                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4454                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4455         }
4456
4457 out:
4458         if (status != connector_status_connected && !intel_dp->is_mst)
4459                 intel_dp_unset_edid(intel_dp);
4460
4461         intel_display_power_put(to_i915(dev), power_domain);
4462         return status;
4463 }
4464
4465 static enum drm_connector_status
4466 intel_dp_detect(struct drm_connector *connector, bool force)
4467 {
4468         struct intel_dp *intel_dp = intel_attached_dp(connector);
4469         enum drm_connector_status status = connector->status;
4470
4471         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4472                       connector->base.id, connector->name);
4473
4474         /* If full detect is not performed yet, do a full detect */
4475         if (!intel_dp->detect_done)
4476                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4477
4478         intel_dp->detect_done = false;
4479
4480         return status;
4481 }
4482
4483 static void
4484 intel_dp_force(struct drm_connector *connector)
4485 {
4486         struct intel_dp *intel_dp = intel_attached_dp(connector);
4487         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4488         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4489         enum intel_display_power_domain power_domain;
4490
4491         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4492                       connector->base.id, connector->name);
4493         intel_dp_unset_edid(intel_dp);
4494
4495         if (connector->status != connector_status_connected)
4496                 return;
4497
4498         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4499         intel_display_power_get(dev_priv, power_domain);
4500
4501         intel_dp_set_edid(intel_dp);
4502
4503         intel_display_power_put(dev_priv, power_domain);
4504
4505         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4506                 intel_encoder->type = INTEL_OUTPUT_DP;
4507 }
4508
4509 static int intel_dp_get_modes(struct drm_connector *connector)
4510 {
4511         struct intel_connector *intel_connector = to_intel_connector(connector);
4512         struct edid *edid;
4513
4514         edid = intel_connector->detect_edid;
4515         if (edid) {
4516                 int ret = intel_connector_update_modes(connector, edid);
4517                 if (ret)
4518                         return ret;
4519         }
4520
4521         /* if eDP has no EDID, fall back to fixed mode */
4522         if (is_edp(intel_attached_dp(connector)) &&
4523             intel_connector->panel.fixed_mode) {
4524                 struct drm_display_mode *mode;
4525
4526                 mode = drm_mode_duplicate(connector->dev,
4527                                           intel_connector->panel.fixed_mode);
4528                 if (mode) {
4529                         drm_mode_probed_add(connector, mode);
4530                         return 1;
4531                 }
4532         }
4533
4534         return 0;
4535 }
4536
4537 static bool
4538 intel_dp_detect_audio(struct drm_connector *connector)
4539 {
4540         bool has_audio = false;
4541         struct edid *edid;
4542
4543         edid = to_intel_connector(connector)->detect_edid;
4544         if (edid)
4545                 has_audio = drm_detect_monitor_audio(edid);
4546
4547         return has_audio;
4548 }
4549
4550 static int
4551 intel_dp_set_property(struct drm_connector *connector,
4552                       struct drm_property *property,
4553                       uint64_t val)
4554 {
4555         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4556         struct intel_connector *intel_connector = to_intel_connector(connector);
4557         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4558         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4559         int ret;
4560
4561         ret = drm_object_property_set_value(&connector->base, property, val);
4562         if (ret)
4563                 return ret;
4564
4565         if (property == dev_priv->force_audio_property) {
4566                 int i = val;
4567                 bool has_audio;
4568
4569                 if (i == intel_dp->force_audio)
4570                         return 0;
4571
4572                 intel_dp->force_audio = i;
4573
4574                 if (i == HDMI_AUDIO_AUTO)
4575                         has_audio = intel_dp_detect_audio(connector);
4576                 else
4577                         has_audio = (i == HDMI_AUDIO_ON);
4578
4579                 if (has_audio == intel_dp->has_audio)
4580                         return 0;
4581
4582                 intel_dp->has_audio = has_audio;
4583                 goto done;
4584         }
4585
4586         if (property == dev_priv->broadcast_rgb_property) {
4587                 bool old_auto = intel_dp->color_range_auto;
4588                 bool old_range = intel_dp->limited_color_range;
4589
4590                 switch (val) {
4591                 case INTEL_BROADCAST_RGB_AUTO:
4592                         intel_dp->color_range_auto = true;
4593                         break;
4594                 case INTEL_BROADCAST_RGB_FULL:
4595                         intel_dp->color_range_auto = false;
4596                         intel_dp->limited_color_range = false;
4597                         break;
4598                 case INTEL_BROADCAST_RGB_LIMITED:
4599                         intel_dp->color_range_auto = false;
4600                         intel_dp->limited_color_range = true;
4601                         break;
4602                 default:
4603                         return -EINVAL;
4604                 }
4605
4606                 if (old_auto == intel_dp->color_range_auto &&
4607                     old_range == intel_dp->limited_color_range)
4608                         return 0;
4609
4610                 goto done;
4611         }
4612
4613         if (is_edp(intel_dp) &&
4614             property == connector->dev->mode_config.scaling_mode_property) {
4615                 if (val == DRM_MODE_SCALE_NONE) {
4616                         DRM_DEBUG_KMS("no scaling not supported\n");
4617                         return -EINVAL;
4618                 }
4619                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4620                     val == DRM_MODE_SCALE_CENTER) {
4621                         DRM_DEBUG_KMS("centering not supported\n");
4622                         return -EINVAL;
4623                 }
4624
4625                 if (intel_connector->panel.fitting_mode == val) {
4626                         /* the eDP scaling property is not changed */
4627                         return 0;
4628                 }
4629                 intel_connector->panel.fitting_mode = val;
4630
4631                 goto done;
4632         }
4633
4634         return -EINVAL;
4635
4636 done:
4637         if (intel_encoder->base.crtc)
4638                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4639
4640         return 0;
4641 }
4642
4643 static int
4644 intel_dp_connector_register(struct drm_connector *connector)
4645 {
4646         struct intel_dp *intel_dp = intel_attached_dp(connector);
4647         int ret;
4648
4649         ret = intel_connector_register(connector);
4650         if (ret)
4651                 return ret;
4652
4653         i915_debugfs_connector_add(connector);
4654
4655         DRM_DEBUG_KMS("registering %s bus for %s\n",
4656                       intel_dp->aux.name, connector->kdev->kobj.name);
4657
4658         intel_dp->aux.dev = connector->kdev;
4659         return drm_dp_aux_register(&intel_dp->aux);
4660 }
4661
4662 static void
4663 intel_dp_connector_unregister(struct drm_connector *connector)
4664 {
4665         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4666         intel_connector_unregister(connector);
4667 }
4668
4669 static void
4670 intel_dp_connector_destroy(struct drm_connector *connector)
4671 {
4672         struct intel_connector *intel_connector = to_intel_connector(connector);
4673
4674         kfree(intel_connector->detect_edid);
4675
4676         if (!IS_ERR_OR_NULL(intel_connector->edid))
4677                 kfree(intel_connector->edid);
4678
4679         /* Can't call is_edp() since the encoder may have been destroyed
4680          * already. */
4681         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4682                 intel_panel_fini(&intel_connector->panel);
4683
4684         drm_connector_cleanup(connector);
4685         kfree(connector);
4686 }
4687
4688 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4689 {
4690         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4691         struct intel_dp *intel_dp = &intel_dig_port->dp;
4692
4693         intel_dp_mst_encoder_cleanup(intel_dig_port);
4694         if (is_edp(intel_dp)) {
4695                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4696                 /*
4697                  * vdd might still be enabled do to the delayed vdd off.
4698                  * Make sure vdd is actually turned off here.
4699                  */
4700                 pps_lock(intel_dp);
4701                 edp_panel_vdd_off_sync(intel_dp);
4702                 pps_unlock(intel_dp);
4703
4704                 if (intel_dp->edp_notifier.notifier_call) {
4705                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4706                         intel_dp->edp_notifier.notifier_call = NULL;
4707                 }
4708         }
4709
4710         intel_dp_aux_fini(intel_dp);
4711
4712         drm_encoder_cleanup(encoder);
4713         kfree(intel_dig_port);
4714 }
4715
4716 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4717 {
4718         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4719
4720         if (!is_edp(intel_dp))
4721                 return;
4722
4723         /*
4724          * vdd might still be enabled do to the delayed vdd off.
4725          * Make sure vdd is actually turned off here.
4726          */
4727         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4728         pps_lock(intel_dp);
4729         edp_panel_vdd_off_sync(intel_dp);
4730         pps_unlock(intel_dp);
4731 }
4732
4733 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4734 {
4735         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4736         struct drm_device *dev = intel_dig_port->base.base.dev;
4737         struct drm_i915_private *dev_priv = to_i915(dev);
4738         enum intel_display_power_domain power_domain;
4739
4740         lockdep_assert_held(&dev_priv->pps_mutex);
4741
4742         if (!edp_have_panel_vdd(intel_dp))
4743                 return;
4744
4745         /*
4746          * The VDD bit needs a power domain reference, so if the bit is
4747          * already enabled when we boot or resume, grab this reference and
4748          * schedule a vdd off, so we don't hold on to the reference
4749          * indefinitely.
4750          */
4751         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4752         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4753         intel_display_power_get(dev_priv, power_domain);
4754
4755         edp_panel_vdd_schedule_off(intel_dp);
4756 }
4757
4758 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4759 {
4760         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4761         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4762         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4763
4764         if (!HAS_DDI(dev_priv))
4765                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4766
4767         if (lspcon->active)
4768                 lspcon_resume(lspcon);
4769
4770         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4771                 return;
4772
4773         pps_lock(intel_dp);
4774
4775         /* Reinit the power sequencer, in case BIOS did something with it. */
4776         intel_dp_pps_init(encoder->dev, intel_dp);
4777         intel_edp_panel_vdd_sanitize(intel_dp);
4778
4779         pps_unlock(intel_dp);
4780 }
4781
4782 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4783         .dpms = drm_atomic_helper_connector_dpms,
4784         .detect = intel_dp_detect,
4785         .force = intel_dp_force,
4786         .fill_modes = drm_helper_probe_single_connector_modes,
4787         .set_property = intel_dp_set_property,
4788         .atomic_get_property = intel_connector_atomic_get_property,
4789         .late_register = intel_dp_connector_register,
4790         .early_unregister = intel_dp_connector_unregister,
4791         .destroy = intel_dp_connector_destroy,
4792         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4793         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4794 };
4795
4796 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4797         .get_modes = intel_dp_get_modes,
4798         .mode_valid = intel_dp_mode_valid,
4799 };
4800
4801 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4802         .reset = intel_dp_encoder_reset,
4803         .destroy = intel_dp_encoder_destroy,
4804 };
4805
4806 enum irqreturn
4807 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4808 {
4809         struct intel_dp *intel_dp = &intel_dig_port->dp;
4810         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4811         struct drm_device *dev = intel_dig_port->base.base.dev;
4812         struct drm_i915_private *dev_priv = to_i915(dev);
4813         enum intel_display_power_domain power_domain;
4814         enum irqreturn ret = IRQ_NONE;
4815
4816         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4817             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4818                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4819
4820         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4821                 /*
4822                  * vdd off can generate a long pulse on eDP which
4823                  * would require vdd on to handle it, and thus we
4824                  * would end up in an endless cycle of
4825                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4826                  */
4827                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4828                               port_name(intel_dig_port->port));
4829                 return IRQ_HANDLED;
4830         }
4831
4832         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4833                       port_name(intel_dig_port->port),
4834                       long_hpd ? "long" : "short");
4835
4836         if (long_hpd) {
4837                 intel_dp->detect_done = false;
4838                 return IRQ_NONE;
4839         }
4840
4841         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4842         intel_display_power_get(dev_priv, power_domain);
4843
4844         if (intel_dp->is_mst) {
4845                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4846                         /*
4847                          * If we were in MST mode, and device is not
4848                          * there, get out of MST mode
4849                          */
4850                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4851                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4852                         intel_dp->is_mst = false;
4853                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4854                                                         intel_dp->is_mst);
4855                         intel_dp->detect_done = false;
4856                         goto put_power;
4857                 }
4858         }
4859
4860         if (!intel_dp->is_mst) {
4861                 if (!intel_dp_short_pulse(intel_dp)) {
4862                         intel_dp->detect_done = false;
4863                         goto put_power;
4864                 }
4865         }
4866
4867         ret = IRQ_HANDLED;
4868
4869 put_power:
4870         intel_display_power_put(dev_priv, power_domain);
4871
4872         return ret;
4873 }
4874
4875 /* check the VBT to see whether the eDP is on another port */
4876 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
4877 {
4878         /*
4879          * eDP not supported on g4x. so bail out early just
4880          * for a bit extra safety in case the VBT is bonkers.
4881          */
4882         if (INTEL_GEN(dev_priv) < 5)
4883                 return false;
4884
4885         if (port == PORT_A)
4886                 return true;
4887
4888         return intel_bios_is_port_edp(dev_priv, port);
4889 }
4890
4891 void
4892 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4893 {
4894         struct intel_connector *intel_connector = to_intel_connector(connector);
4895
4896         intel_attach_force_audio_property(connector);
4897         intel_attach_broadcast_rgb_property(connector);
4898         intel_dp->color_range_auto = true;
4899
4900         if (is_edp(intel_dp)) {
4901                 drm_mode_create_scaling_mode_property(connector->dev);
4902                 drm_object_attach_property(
4903                         &connector->base,
4904                         connector->dev->mode_config.scaling_mode_property,
4905                         DRM_MODE_SCALE_ASPECT);
4906                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4907         }
4908 }
4909
4910 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4911 {
4912         intel_dp->panel_power_off_time = ktime_get_boottime();
4913         intel_dp->last_power_on = jiffies;
4914         intel_dp->last_backlight_off = jiffies;
4915 }
4916
4917 static void
4918 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4919                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
4920 {
4921         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4922         struct pps_registers regs;
4923
4924         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4925
4926         /* Workaround: Need to write PP_CONTROL with the unlock key as
4927          * the very first thing. */
4928         pp_ctl = ironlake_get_pp_control(intel_dp);
4929
4930         pp_on = I915_READ(regs.pp_on);
4931         pp_off = I915_READ(regs.pp_off);
4932         if (!IS_BROXTON(dev_priv)) {
4933                 I915_WRITE(regs.pp_ctrl, pp_ctl);
4934                 pp_div = I915_READ(regs.pp_div);
4935         }
4936
4937         /* Pull timing values out of registers */
4938         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4939                      PANEL_POWER_UP_DELAY_SHIFT;
4940
4941         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4942                   PANEL_LIGHT_ON_DELAY_SHIFT;
4943
4944         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4945                   PANEL_LIGHT_OFF_DELAY_SHIFT;
4946
4947         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4948                    PANEL_POWER_DOWN_DELAY_SHIFT;
4949
4950         if (IS_BROXTON(dev_priv)) {
4951                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4952                         BXT_POWER_CYCLE_DELAY_SHIFT;
4953                 if (tmp > 0)
4954                         seq->t11_t12 = (tmp - 1) * 1000;
4955                 else
4956                         seq->t11_t12 = 0;
4957         } else {
4958                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4959                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4960         }
4961 }
4962
4963 static void
4964 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4965 {
4966         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4967                       state_name,
4968                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4969 }
4970
4971 static void
4972 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4973                        struct intel_dp *intel_dp)
4974 {
4975         struct edp_power_seq hw;
4976         struct edp_power_seq *sw = &intel_dp->pps_delays;
4977
4978         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4979
4980         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4981             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4982                 DRM_ERROR("PPS state mismatch\n");
4983                 intel_pps_dump_state("sw", sw);
4984                 intel_pps_dump_state("hw", &hw);
4985         }
4986 }
4987
4988 static void
4989 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4990                                     struct intel_dp *intel_dp)
4991 {
4992         struct drm_i915_private *dev_priv = to_i915(dev);
4993         struct edp_power_seq cur, vbt, spec,
4994                 *final = &intel_dp->pps_delays;
4995
4996         lockdep_assert_held(&dev_priv->pps_mutex);
4997
4998         /* already initialized? */
4999         if (final->t11_t12 != 0)
5000                 return;
5001
5002         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5003
5004         intel_pps_dump_state("cur", &cur);
5005
5006         vbt = dev_priv->vbt.edp.pps;
5007
5008         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5009          * our hw here, which are all in 100usec. */
5010         spec.t1_t3 = 210 * 10;
5011         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5012         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5013         spec.t10 = 500 * 10;
5014         /* This one is special and actually in units of 100ms, but zero
5015          * based in the hw (so we need to add 100 ms). But the sw vbt
5016          * table multiplies it with 1000 to make it in units of 100usec,
5017          * too. */
5018         spec.t11_t12 = (510 + 100) * 10;
5019
5020         intel_pps_dump_state("vbt", &vbt);
5021
5022         /* Use the max of the register settings and vbt. If both are
5023          * unset, fall back to the spec limits. */
5024 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5025                                        spec.field : \
5026                                        max(cur.field, vbt.field))
5027         assign_final(t1_t3);
5028         assign_final(t8);
5029         assign_final(t9);
5030         assign_final(t10);
5031         assign_final(t11_t12);
5032 #undef assign_final
5033
5034 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5035         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5036         intel_dp->backlight_on_delay = get_delay(t8);
5037         intel_dp->backlight_off_delay = get_delay(t9);
5038         intel_dp->panel_power_down_delay = get_delay(t10);
5039         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5040 #undef get_delay
5041
5042         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5043                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5044                       intel_dp->panel_power_cycle_delay);
5045
5046         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5047                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5048
5049         /*
5050          * We override the HW backlight delays to 1 because we do manual waits
5051          * on them. For T8, even BSpec recommends doing it. For T9, if we
5052          * don't do this, we'll end up waiting for the backlight off delay
5053          * twice: once when we do the manual sleep, and once when we disable
5054          * the panel and wait for the PP_STATUS bit to become zero.
5055          */
5056         final->t8 = 1;
5057         final->t9 = 1;
5058 }
5059
5060 static void
5061 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5062                                               struct intel_dp *intel_dp)
5063 {
5064         struct drm_i915_private *dev_priv = to_i915(dev);
5065         u32 pp_on, pp_off, pp_div, port_sel = 0;
5066         int div = dev_priv->rawclk_freq / 1000;
5067         struct pps_registers regs;
5068         enum port port = dp_to_dig_port(intel_dp)->port;
5069         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5070
5071         lockdep_assert_held(&dev_priv->pps_mutex);
5072
5073         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5074
5075         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5076                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5077         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5078                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5079         /* Compute the divisor for the pp clock, simply match the Bspec
5080          * formula. */
5081         if (IS_BROXTON(dev_priv)) {
5082                 pp_div = I915_READ(regs.pp_ctrl);
5083                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5084                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5085                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5086         } else {
5087                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5088                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5089                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5090         }
5091
5092         /* Haswell doesn't have any port selection bits for the panel
5093          * power sequencer any more. */
5094         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5095                 port_sel = PANEL_PORT_SELECT_VLV(port);
5096         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5097                 if (port == PORT_A)
5098                         port_sel = PANEL_PORT_SELECT_DPA;
5099                 else
5100                         port_sel = PANEL_PORT_SELECT_DPD;
5101         }
5102
5103         pp_on |= port_sel;
5104
5105         I915_WRITE(regs.pp_on, pp_on);
5106         I915_WRITE(regs.pp_off, pp_off);
5107         if (IS_BROXTON(dev_priv))
5108                 I915_WRITE(regs.pp_ctrl, pp_div);
5109         else
5110                 I915_WRITE(regs.pp_div, pp_div);
5111
5112         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5113                       I915_READ(regs.pp_on),
5114                       I915_READ(regs.pp_off),
5115                       IS_BROXTON(dev_priv) ?
5116                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5117                       I915_READ(regs.pp_div));
5118 }
5119
5120 static void intel_dp_pps_init(struct drm_device *dev,
5121                               struct intel_dp *intel_dp)
5122 {
5123         struct drm_i915_private *dev_priv = to_i915(dev);
5124
5125         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5126                 vlv_initial_power_sequencer_setup(intel_dp);
5127         } else {
5128                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5129                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5130         }
5131 }
5132
5133 /**
5134  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5135  * @dev_priv: i915 device
5136  * @crtc_state: a pointer to the active intel_crtc_state
5137  * @refresh_rate: RR to be programmed
5138  *
5139  * This function gets called when refresh rate (RR) has to be changed from
5140  * one frequency to another. Switches can be between high and low RR
5141  * supported by the panel or to any other RR based on media playback (in
5142  * this case, RR value needs to be passed from user space).
5143  *
5144  * The caller of this function needs to take a lock on dev_priv->drrs.
5145  */
5146 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5147                                     struct intel_crtc_state *crtc_state,
5148                                     int refresh_rate)
5149 {
5150         struct intel_encoder *encoder;
5151         struct intel_digital_port *dig_port = NULL;
5152         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5154         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5155
5156         if (refresh_rate <= 0) {
5157                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5158                 return;
5159         }
5160
5161         if (intel_dp == NULL) {
5162                 DRM_DEBUG_KMS("DRRS not supported.\n");
5163                 return;
5164         }
5165
5166         /*
5167          * FIXME: This needs proper synchronization with psr state for some
5168          * platforms that cannot have PSR and DRRS enabled at the same time.
5169          */
5170
5171         dig_port = dp_to_dig_port(intel_dp);
5172         encoder = &dig_port->base;
5173         intel_crtc = to_intel_crtc(encoder->base.crtc);
5174
5175         if (!intel_crtc) {
5176                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5177                 return;
5178         }
5179
5180         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5181                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5182                 return;
5183         }
5184
5185         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5186                         refresh_rate)
5187                 index = DRRS_LOW_RR;
5188
5189         if (index == dev_priv->drrs.refresh_rate_type) {
5190                 DRM_DEBUG_KMS(
5191                         "DRRS requested for previously set RR...ignoring\n");
5192                 return;
5193         }
5194
5195         if (!crtc_state->base.active) {
5196                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5197                 return;
5198         }
5199
5200         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5201                 switch (index) {
5202                 case DRRS_HIGH_RR:
5203                         intel_dp_set_m_n(intel_crtc, M1_N1);
5204                         break;
5205                 case DRRS_LOW_RR:
5206                         intel_dp_set_m_n(intel_crtc, M2_N2);
5207                         break;
5208                 case DRRS_MAX_RR:
5209                 default:
5210                         DRM_ERROR("Unsupported refreshrate type\n");
5211                 }
5212         } else if (INTEL_GEN(dev_priv) > 6) {
5213                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5214                 u32 val;
5215
5216                 val = I915_READ(reg);
5217                 if (index > DRRS_HIGH_RR) {
5218                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5219                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5220                         else
5221                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5222                 } else {
5223                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5224                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5225                         else
5226                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5227                 }
5228                 I915_WRITE(reg, val);
5229         }
5230
5231         dev_priv->drrs.refresh_rate_type = index;
5232
5233         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5234 }
5235
5236 /**
5237  * intel_edp_drrs_enable - init drrs struct if supported
5238  * @intel_dp: DP struct
5239  * @crtc_state: A pointer to the active crtc state.
5240  *
5241  * Initializes frontbuffer_bits and drrs.dp
5242  */
5243 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5244                            struct intel_crtc_state *crtc_state)
5245 {
5246         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5247         struct drm_i915_private *dev_priv = to_i915(dev);
5248
5249         if (!crtc_state->has_drrs) {
5250                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5251                 return;
5252         }
5253
5254         mutex_lock(&dev_priv->drrs.mutex);
5255         if (WARN_ON(dev_priv->drrs.dp)) {
5256                 DRM_ERROR("DRRS already enabled\n");
5257                 goto unlock;
5258         }
5259
5260         dev_priv->drrs.busy_frontbuffer_bits = 0;
5261
5262         dev_priv->drrs.dp = intel_dp;
5263
5264 unlock:
5265         mutex_unlock(&dev_priv->drrs.mutex);
5266 }
5267
5268 /**
5269  * intel_edp_drrs_disable - Disable DRRS
5270  * @intel_dp: DP struct
5271  * @old_crtc_state: Pointer to old crtc_state.
5272  *
5273  */
5274 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5275                             struct intel_crtc_state *old_crtc_state)
5276 {
5277         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5278         struct drm_i915_private *dev_priv = to_i915(dev);
5279
5280         if (!old_crtc_state->has_drrs)
5281                 return;
5282
5283         mutex_lock(&dev_priv->drrs.mutex);
5284         if (!dev_priv->drrs.dp) {
5285                 mutex_unlock(&dev_priv->drrs.mutex);
5286                 return;
5287         }
5288
5289         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5290                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5291                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5292
5293         dev_priv->drrs.dp = NULL;
5294         mutex_unlock(&dev_priv->drrs.mutex);
5295
5296         cancel_delayed_work_sync(&dev_priv->drrs.work);
5297 }
5298
5299 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5300 {
5301         struct drm_i915_private *dev_priv =
5302                 container_of(work, typeof(*dev_priv), drrs.work.work);
5303         struct intel_dp *intel_dp;
5304
5305         mutex_lock(&dev_priv->drrs.mutex);
5306
5307         intel_dp = dev_priv->drrs.dp;
5308
5309         if (!intel_dp)
5310                 goto unlock;
5311
5312         /*
5313          * The delayed work can race with an invalidate hence we need to
5314          * recheck.
5315          */
5316
5317         if (dev_priv->drrs.busy_frontbuffer_bits)
5318                 goto unlock;
5319
5320         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5321                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5322
5323                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5324                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5325         }
5326
5327 unlock:
5328         mutex_unlock(&dev_priv->drrs.mutex);
5329 }
5330
5331 /**
5332  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5333  * @dev_priv: i915 device
5334  * @frontbuffer_bits: frontbuffer plane tracking bits
5335  *
5336  * This function gets called everytime rendering on the given planes start.
5337  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5338  *
5339  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5340  */
5341 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5342                                unsigned int frontbuffer_bits)
5343 {
5344         struct drm_crtc *crtc;
5345         enum pipe pipe;
5346
5347         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5348                 return;
5349
5350         cancel_delayed_work(&dev_priv->drrs.work);
5351
5352         mutex_lock(&dev_priv->drrs.mutex);
5353         if (!dev_priv->drrs.dp) {
5354                 mutex_unlock(&dev_priv->drrs.mutex);
5355                 return;
5356         }
5357
5358         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5359         pipe = to_intel_crtc(crtc)->pipe;
5360
5361         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5362         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5363
5364         /* invalidate means busy screen hence upclock */
5365         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5366                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5367                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5368
5369         mutex_unlock(&dev_priv->drrs.mutex);
5370 }
5371
5372 /**
5373  * intel_edp_drrs_flush - Restart Idleness DRRS
5374  * @dev_priv: i915 device
5375  * @frontbuffer_bits: frontbuffer plane tracking bits
5376  *
5377  * This function gets called every time rendering on the given planes has
5378  * completed or flip on a crtc is completed. So DRRS should be upclocked
5379  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5380  * if no other planes are dirty.
5381  *
5382  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5383  */
5384 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5385                           unsigned int frontbuffer_bits)
5386 {
5387         struct drm_crtc *crtc;
5388         enum pipe pipe;
5389
5390         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5391                 return;
5392
5393         cancel_delayed_work(&dev_priv->drrs.work);
5394
5395         mutex_lock(&dev_priv->drrs.mutex);
5396         if (!dev_priv->drrs.dp) {
5397                 mutex_unlock(&dev_priv->drrs.mutex);
5398                 return;
5399         }
5400
5401         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5402         pipe = to_intel_crtc(crtc)->pipe;
5403
5404         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5405         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5406
5407         /* flush means busy screen hence upclock */
5408         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5409                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5410                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5411
5412         /*
5413          * flush also means no more activity hence schedule downclock, if all
5414          * other fbs are quiescent too
5415          */
5416         if (!dev_priv->drrs.busy_frontbuffer_bits)
5417                 schedule_delayed_work(&dev_priv->drrs.work,
5418                                 msecs_to_jiffies(1000));
5419         mutex_unlock(&dev_priv->drrs.mutex);
5420 }
5421
5422 /**
5423  * DOC: Display Refresh Rate Switching (DRRS)
5424  *
5425  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5426  * which enables swtching between low and high refresh rates,
5427  * dynamically, based on the usage scenario. This feature is applicable
5428  * for internal panels.
5429  *
5430  * Indication that the panel supports DRRS is given by the panel EDID, which
5431  * would list multiple refresh rates for one resolution.
5432  *
5433  * DRRS is of 2 types - static and seamless.
5434  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5435  * (may appear as a blink on screen) and is used in dock-undock scenario.
5436  * Seamless DRRS involves changing RR without any visual effect to the user
5437  * and can be used during normal system usage. This is done by programming
5438  * certain registers.
5439  *
5440  * Support for static/seamless DRRS may be indicated in the VBT based on
5441  * inputs from the panel spec.
5442  *
5443  * DRRS saves power by switching to low RR based on usage scenarios.
5444  *
5445  * The implementation is based on frontbuffer tracking implementation.  When
5446  * there is a disturbance on the screen triggered by user activity or a periodic
5447  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5448  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5449  * made.
5450  *
5451  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5452  * and intel_edp_drrs_flush() are called.
5453  *
5454  * DRRS can be further extended to support other internal panels and also
5455  * the scenario of video playback wherein RR is set based on the rate
5456  * requested by userspace.
5457  */
5458
5459 /**
5460  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5461  * @intel_connector: eDP connector
5462  * @fixed_mode: preferred mode of panel
5463  *
5464  * This function is  called only once at driver load to initialize basic
5465  * DRRS stuff.
5466  *
5467  * Returns:
5468  * Downclock mode if panel supports it, else return NULL.
5469  * DRRS support is determined by the presence of downclock mode (apart
5470  * from VBT setting).
5471  */
5472 static struct drm_display_mode *
5473 intel_dp_drrs_init(struct intel_connector *intel_connector,
5474                 struct drm_display_mode *fixed_mode)
5475 {
5476         struct drm_connector *connector = &intel_connector->base;
5477         struct drm_device *dev = connector->dev;
5478         struct drm_i915_private *dev_priv = to_i915(dev);
5479         struct drm_display_mode *downclock_mode = NULL;
5480
5481         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5482         mutex_init(&dev_priv->drrs.mutex);
5483
5484         if (INTEL_GEN(dev_priv) <= 6) {
5485                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5486                 return NULL;
5487         }
5488
5489         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5490                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5491                 return NULL;
5492         }
5493
5494         downclock_mode = intel_find_panel_downclock
5495                                         (dev, fixed_mode, connector);
5496
5497         if (!downclock_mode) {
5498                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5499                 return NULL;
5500         }
5501
5502         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5503
5504         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5505         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5506         return downclock_mode;
5507 }
5508
5509 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5510                                      struct intel_connector *intel_connector)
5511 {
5512         struct drm_connector *connector = &intel_connector->base;
5513         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5514         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5515         struct drm_device *dev = intel_encoder->base.dev;
5516         struct drm_i915_private *dev_priv = to_i915(dev);
5517         struct drm_display_mode *fixed_mode = NULL;
5518         struct drm_display_mode *downclock_mode = NULL;
5519         bool has_dpcd;
5520         struct drm_display_mode *scan;
5521         struct edid *edid;
5522         enum pipe pipe = INVALID_PIPE;
5523
5524         if (!is_edp(intel_dp))
5525                 return true;
5526
5527         /*
5528          * On IBX/CPT we may get here with LVDS already registered. Since the
5529          * driver uses the only internal power sequencer available for both
5530          * eDP and LVDS bail out early in this case to prevent interfering
5531          * with an already powered-on LVDS power sequencer.
5532          */
5533         if (intel_get_lvds_encoder(dev)) {
5534                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5535                 DRM_INFO("LVDS was detected, not registering eDP\n");
5536
5537                 return false;
5538         }
5539
5540         pps_lock(intel_dp);
5541
5542         intel_dp_init_panel_power_timestamps(intel_dp);
5543         intel_dp_pps_init(dev, intel_dp);
5544         intel_edp_panel_vdd_sanitize(intel_dp);
5545
5546         pps_unlock(intel_dp);
5547
5548         /* Cache DPCD and EDID for edp. */
5549         has_dpcd = intel_edp_init_dpcd(intel_dp);
5550
5551         if (!has_dpcd) {
5552                 /* if this fails, presume the device is a ghost */
5553                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5554                 goto out_vdd_off;
5555         }
5556
5557         mutex_lock(&dev->mode_config.mutex);
5558         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5559         if (edid) {
5560                 if (drm_add_edid_modes(connector, edid)) {
5561                         drm_mode_connector_update_edid_property(connector,
5562                                                                 edid);
5563                         drm_edid_to_eld(connector, edid);
5564                 } else {
5565                         kfree(edid);
5566                         edid = ERR_PTR(-EINVAL);
5567                 }
5568         } else {
5569                 edid = ERR_PTR(-ENOENT);
5570         }
5571         intel_connector->edid = edid;
5572
5573         /* prefer fixed mode from EDID if available */
5574         list_for_each_entry(scan, &connector->probed_modes, head) {
5575                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5576                         fixed_mode = drm_mode_duplicate(dev, scan);
5577                         downclock_mode = intel_dp_drrs_init(
5578                                                 intel_connector, fixed_mode);
5579                         break;
5580                 }
5581         }
5582
5583         /* fallback to VBT if available for eDP */
5584         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5585                 fixed_mode = drm_mode_duplicate(dev,
5586                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5587                 if (fixed_mode) {
5588                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5589                         connector->display_info.width_mm = fixed_mode->width_mm;
5590                         connector->display_info.height_mm = fixed_mode->height_mm;
5591                 }
5592         }
5593         mutex_unlock(&dev->mode_config.mutex);
5594
5595         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5596                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5597                 register_reboot_notifier(&intel_dp->edp_notifier);
5598
5599                 /*
5600                  * Figure out the current pipe for the initial backlight setup.
5601                  * If the current pipe isn't valid, try the PPS pipe, and if that
5602                  * fails just assume pipe A.
5603                  */
5604                 if (IS_CHERRYVIEW(dev_priv))
5605                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5606                 else
5607                         pipe = PORT_TO_PIPE(intel_dp->DP);
5608
5609                 if (pipe != PIPE_A && pipe != PIPE_B)
5610                         pipe = intel_dp->pps_pipe;
5611
5612                 if (pipe != PIPE_A && pipe != PIPE_B)
5613                         pipe = PIPE_A;
5614
5615                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5616                               pipe_name(pipe));
5617         }
5618
5619         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5620         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5621         intel_panel_setup_backlight(connector, pipe);
5622
5623         return true;
5624
5625 out_vdd_off:
5626         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5627         /*
5628          * vdd might still be enabled do to the delayed vdd off.
5629          * Make sure vdd is actually turned off here.
5630          */
5631         pps_lock(intel_dp);
5632         edp_panel_vdd_off_sync(intel_dp);
5633         pps_unlock(intel_dp);
5634
5635         return false;
5636 }
5637
5638 bool
5639 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5640                         struct intel_connector *intel_connector)
5641 {
5642         struct drm_connector *connector = &intel_connector->base;
5643         struct intel_dp *intel_dp = &intel_dig_port->dp;
5644         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5645         struct drm_device *dev = intel_encoder->base.dev;
5646         struct drm_i915_private *dev_priv = to_i915(dev);
5647         enum port port = intel_dig_port->port;
5648         int type;
5649
5650         if (WARN(intel_dig_port->max_lanes < 1,
5651                  "Not enough lanes (%d) for DP on port %c\n",
5652                  intel_dig_port->max_lanes, port_name(port)))
5653                 return false;
5654
5655         intel_dp->pps_pipe = INVALID_PIPE;
5656
5657         /* intel_dp vfuncs */
5658         if (INTEL_GEN(dev_priv) >= 9)
5659                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5660         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5661                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5662         else if (HAS_PCH_SPLIT(dev_priv))
5663                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5664         else
5665                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5666
5667         if (INTEL_GEN(dev_priv) >= 9)
5668                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5669         else
5670                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5671
5672         if (HAS_DDI(dev_priv))
5673                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5674
5675         /* Preserve the current hw state. */
5676         intel_dp->DP = I915_READ(intel_dp->output_reg);
5677         intel_dp->attached_connector = intel_connector;
5678
5679         if (intel_dp_is_edp(dev_priv, port))
5680                 type = DRM_MODE_CONNECTOR_eDP;
5681         else
5682                 type = DRM_MODE_CONNECTOR_DisplayPort;
5683
5684         /*
5685          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5686          * for DP the encoder type can be set by the caller to
5687          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5688          */
5689         if (type == DRM_MODE_CONNECTOR_eDP)
5690                 intel_encoder->type = INTEL_OUTPUT_EDP;
5691
5692         /* eDP only on port B and/or C on vlv/chv */
5693         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5694                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5695                 return false;
5696
5697         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5698                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5699                         port_name(port));
5700
5701         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5702         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5703
5704         connector->interlace_allowed = true;
5705         connector->doublescan_allowed = 0;
5706
5707         intel_dp_aux_init(intel_dp);
5708
5709         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5710                           edp_panel_vdd_work);
5711
5712         intel_connector_attach_encoder(intel_connector, intel_encoder);
5713
5714         if (HAS_DDI(dev_priv))
5715                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5716         else
5717                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5718
5719         /* Set up the hotplug pin. */
5720         switch (port) {
5721         case PORT_A:
5722                 intel_encoder->hpd_pin = HPD_PORT_A;
5723                 break;
5724         case PORT_B:
5725                 intel_encoder->hpd_pin = HPD_PORT_B;
5726                 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5727                         intel_encoder->hpd_pin = HPD_PORT_A;
5728                 break;
5729         case PORT_C:
5730                 intel_encoder->hpd_pin = HPD_PORT_C;
5731                 break;
5732         case PORT_D:
5733                 intel_encoder->hpd_pin = HPD_PORT_D;
5734                 break;
5735         case PORT_E:
5736                 intel_encoder->hpd_pin = HPD_PORT_E;
5737                 break;
5738         default:
5739                 BUG();
5740         }
5741
5742         /* init MST on ports that can support it */
5743         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
5744             (port == PORT_B || port == PORT_C || port == PORT_D))
5745                 intel_dp_mst_encoder_init(intel_dig_port,
5746                                           intel_connector->base.base.id);
5747
5748         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5749                 intel_dp_aux_fini(intel_dp);
5750                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5751                 goto fail;
5752         }
5753
5754         intel_dp_add_properties(intel_dp, connector);
5755
5756         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5757          * 0xd.  Failure to do so will result in spurious interrupts being
5758          * generated on the port when a cable is not attached.
5759          */
5760         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5761                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5762                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5763         }
5764
5765         return true;
5766
5767 fail:
5768         drm_connector_cleanup(connector);
5769
5770         return false;
5771 }
5772
5773 bool intel_dp_init(struct drm_i915_private *dev_priv,
5774                    i915_reg_t output_reg,
5775                    enum port port)
5776 {
5777         struct intel_digital_port *intel_dig_port;
5778         struct intel_encoder *intel_encoder;
5779         struct drm_encoder *encoder;
5780         struct intel_connector *intel_connector;
5781
5782         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5783         if (!intel_dig_port)
5784                 return false;
5785
5786         intel_connector = intel_connector_alloc();
5787         if (!intel_connector)
5788                 goto err_connector_alloc;
5789
5790         intel_encoder = &intel_dig_port->base;
5791         encoder = &intel_encoder->base;
5792
5793         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
5794                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
5795                              "DP %c", port_name(port)))
5796                 goto err_encoder_init;
5797
5798         intel_encoder->compute_config = intel_dp_compute_config;
5799         intel_encoder->disable = intel_disable_dp;
5800         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5801         intel_encoder->get_config = intel_dp_get_config;
5802         intel_encoder->suspend = intel_dp_encoder_suspend;
5803         if (IS_CHERRYVIEW(dev_priv)) {
5804                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5805                 intel_encoder->pre_enable = chv_pre_enable_dp;
5806                 intel_encoder->enable = vlv_enable_dp;
5807                 intel_encoder->post_disable = chv_post_disable_dp;
5808                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5809         } else if (IS_VALLEYVIEW(dev_priv)) {
5810                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5811                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5812                 intel_encoder->enable = vlv_enable_dp;
5813                 intel_encoder->post_disable = vlv_post_disable_dp;
5814         } else {
5815                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5816                 intel_encoder->enable = g4x_enable_dp;
5817                 if (INTEL_GEN(dev_priv) >= 5)
5818                         intel_encoder->post_disable = ilk_post_disable_dp;
5819         }
5820
5821         intel_dig_port->port = port;
5822         intel_dig_port->dp.output_reg = output_reg;
5823         intel_dig_port->max_lanes = 4;
5824
5825         intel_encoder->type = INTEL_OUTPUT_DP;
5826         if (IS_CHERRYVIEW(dev_priv)) {
5827                 if (port == PORT_D)
5828                         intel_encoder->crtc_mask = 1 << 2;
5829                 else
5830                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5831         } else {
5832                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5833         }
5834         intel_encoder->cloneable = 0;
5835         intel_encoder->port = port;
5836
5837         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5838         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5839
5840         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5841                 goto err_init_connector;
5842
5843         return true;
5844
5845 err_init_connector:
5846         drm_encoder_cleanup(encoder);
5847 err_encoder_init:
5848         kfree(intel_connector);
5849 err_connector_alloc:
5850         kfree(intel_dig_port);
5851         return false;
5852 }
5853
5854 void intel_dp_mst_suspend(struct drm_device *dev)
5855 {
5856         struct drm_i915_private *dev_priv = to_i915(dev);
5857         int i;
5858
5859         /* disable MST */
5860         for (i = 0; i < I915_MAX_PORTS; i++) {
5861                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5862
5863                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5864                         continue;
5865
5866                 if (intel_dig_port->dp.is_mst)
5867                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5868         }
5869 }
5870
5871 void intel_dp_mst_resume(struct drm_device *dev)
5872 {
5873         struct drm_i915_private *dev_priv = to_i915(dev);
5874         int i;
5875
5876         for (i = 0; i < I915_MAX_PORTS; i++) {
5877                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5878                 int ret;
5879
5880                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5881                         continue;
5882
5883                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5884                 if (ret)
5885                         intel_dp_check_mst_status(&intel_dig_port->dp);
5886         }
5887 }