2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
34 #include "drm_crtc_helper.h"
35 #include "intel_drv.h"
38 #include "drm_dp_helper.h"
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 #define DP_LINK_CONFIGURATION_SIZE 9
47 struct intel_encoder base;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
62 uint8_t link_status[DP_LINK_STATUS_SIZE];
63 int panel_power_up_delay;
64 int panel_power_down_delay;
65 int panel_power_cycle_delay;
66 int backlight_on_delay;
67 int backlight_off_delay;
68 struct drm_display_mode *panel_fixed_mode; /* for eDP */
69 struct delayed_work panel_vdd_work;
71 unsigned long panel_off_jiffies;
75 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
76 * @intel_dp: DP struct
78 * If a CPU or PCH DP output is attached to an eDP panel, this function
79 * will return true, and false otherwise.
81 static bool is_edp(struct intel_dp *intel_dp)
83 return intel_dp->base.type == INTEL_OUTPUT_EDP;
87 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
88 * @intel_dp: DP struct
90 * Returns true if the given DP struct corresponds to a PCH DP port attached
91 * to an eDP panel, false otherwise. Helpful for determining whether we
92 * may need FDI resources for a given DP output or not.
94 static bool is_pch_edp(struct intel_dp *intel_dp)
96 return intel_dp->is_pch_edp;
100 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
101 * @intel_dp: DP struct
103 * Returns true if the given DP struct corresponds to a CPU eDP port.
105 static bool is_cpu_edp(struct intel_dp *intel_dp)
107 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
110 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
112 return container_of(encoder, struct intel_dp, base.base);
115 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117 return container_of(intel_attached_encoder(connector),
118 struct intel_dp, base);
122 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
123 * @encoder: DRM encoder
125 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
126 * by intel_display.c.
128 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
130 struct intel_dp *intel_dp;
135 intel_dp = enc_to_intel_dp(encoder);
137 return is_pch_edp(intel_dp);
140 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
141 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
142 static void intel_dp_link_down(struct intel_dp *intel_dp);
145 intel_edp_link_config(struct intel_encoder *intel_encoder,
146 int *lane_num, int *link_bw)
148 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
150 *lane_num = intel_dp->lane_count;
151 if (intel_dp->link_bw == DP_LINK_BW_1_62)
153 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
158 intel_dp_max_lane_count(struct intel_dp *intel_dp)
160 int max_lane_count = 4;
162 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
163 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
164 switch (max_lane_count) {
165 case 1: case 2: case 4:
171 return max_lane_count;
175 intel_dp_max_link_bw(struct intel_dp *intel_dp)
177 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
179 switch (max_link_bw) {
180 case DP_LINK_BW_1_62:
184 max_link_bw = DP_LINK_BW_1_62;
191 intel_dp_link_clock(uint8_t link_bw)
193 if (link_bw == DP_LINK_BW_2_7)
200 * The units on the numbers in the next two are... bizarre. Examples will
201 * make it clearer; this one parallels an example in the eDP spec.
203 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
205 * 270000 * 1 * 8 / 10 == 216000
207 * The actual data capacity of that configuration is 2.16Gbit/s, so the
208 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
209 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
210 * 119000. At 18bpp that's 2142000 kilobits per second.
212 * Thus the strange-looking division by 10 in intel_dp_link_required, to
213 * get the result in decakilobits instead of kilobits.
217 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
219 struct drm_crtc *crtc = intel_dp->base.base.crtc;
220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
224 bpp = intel_crtc->bpp;
226 return (pixel_clock * bpp + 9) / 10;
230 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
232 return (max_link_clock * max_lanes * 8) / 10;
236 intel_dp_mode_valid(struct drm_connector *connector,
237 struct drm_display_mode *mode)
239 struct intel_dp *intel_dp = intel_attached_dp(connector);
240 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
241 int max_lanes = intel_dp_max_lane_count(intel_dp);
243 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
244 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
247 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
251 if (intel_dp_link_required(intel_dp, mode->clock)
252 > intel_dp_max_data_rate(max_link_clock, max_lanes))
253 return MODE_CLOCK_HIGH;
255 if (mode->clock < 10000)
256 return MODE_CLOCK_LOW;
262 pack_aux(uint8_t *src, int src_bytes)
269 for (i = 0; i < src_bytes; i++)
270 v |= ((uint32_t) src[i]) << ((3-i) * 8);
275 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
280 for (i = 0; i < dst_bytes; i++)
281 dst[i] = src >> ((3-i) * 8);
284 /* hrawclock is 1/4 the FSB frequency */
286 intel_hrawclk(struct drm_device *dev)
288 struct drm_i915_private *dev_priv = dev->dev_private;
291 clkcfg = I915_READ(CLKCFG);
292 switch (clkcfg & CLKCFG_FSB_MASK) {
301 case CLKCFG_FSB_1067:
303 case CLKCFG_FSB_1333:
305 /* these two are just a guess; one of them might be right */
306 case CLKCFG_FSB_1600:
307 case CLKCFG_FSB_1600_ALT:
314 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
316 struct drm_device *dev = intel_dp->base.base.dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
319 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
322 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
324 struct drm_device *dev = intel_dp->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
327 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
331 intel_dp_check_edp(struct intel_dp *intel_dp)
333 struct drm_device *dev = intel_dp->base.base.dev;
334 struct drm_i915_private *dev_priv = dev->dev_private;
336 if (!is_edp(intel_dp))
338 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
339 WARN(1, "eDP powered off while attempting aux channel communication.\n");
340 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
341 I915_READ(PCH_PP_STATUS),
342 I915_READ(PCH_PP_CONTROL));
347 intel_dp_aux_ch(struct intel_dp *intel_dp,
348 uint8_t *send, int send_bytes,
349 uint8_t *recv, int recv_size)
351 uint32_t output_reg = intel_dp->output_reg;
352 struct drm_device *dev = intel_dp->base.base.dev;
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 uint32_t ch_ctl = output_reg + 0x10;
355 uint32_t ch_data = ch_ctl + 4;
359 uint32_t aux_clock_divider;
362 intel_dp_check_edp(intel_dp);
363 /* The clock divider is based off the hrawclk,
364 * and would like to run at 2MHz. So, take the
365 * hrawclk value and divide by 2 and use that
367 * Note that PCH attached eDP panels should use a 125MHz input
370 if (is_cpu_edp(intel_dp)) {
372 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
374 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
375 } else if (HAS_PCH_SPLIT(dev))
376 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
378 aux_clock_divider = intel_hrawclk(dev) / 2;
385 /* Try to wait for any previous AUX channel activity */
386 for (try = 0; try < 3; try++) {
387 status = I915_READ(ch_ctl);
388 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
394 WARN(1, "dp_aux_ch not started status 0x%08x\n",
399 /* Must try at least 3 times according to DP spec */
400 for (try = 0; try < 5; try++) {
401 /* Load the send data into the aux channel data registers */
402 for (i = 0; i < send_bytes; i += 4)
403 I915_WRITE(ch_data + i,
404 pack_aux(send + i, send_bytes - i));
406 /* Send the command and wait for it to complete */
408 DP_AUX_CH_CTL_SEND_BUSY |
409 DP_AUX_CH_CTL_TIME_OUT_400us |
410 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
411 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
412 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
414 DP_AUX_CH_CTL_TIME_OUT_ERROR |
415 DP_AUX_CH_CTL_RECEIVE_ERROR);
417 status = I915_READ(ch_ctl);
418 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
423 /* Clear done status and any errors */
427 DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR);
429 if (status & DP_AUX_CH_CTL_DONE)
433 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
434 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
438 /* Check for timeout or receive error.
439 * Timeouts occur when the sink is not connected
441 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
442 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
446 /* Timeouts occur when the device isn't connected, so they're
447 * "normal" -- don't fill the kernel log with these */
448 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
449 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
453 /* Unload any bytes sent back from the other side */
454 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
455 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
456 if (recv_bytes > recv_size)
457 recv_bytes = recv_size;
459 for (i = 0; i < recv_bytes; i += 4)
460 unpack_aux(I915_READ(ch_data + i),
461 recv + i, recv_bytes - i);
466 /* Write data to the aux channel in native mode */
468 intel_dp_aux_native_write(struct intel_dp *intel_dp,
469 uint16_t address, uint8_t *send, int send_bytes)
476 intel_dp_check_edp(intel_dp);
479 msg[0] = AUX_NATIVE_WRITE << 4;
480 msg[1] = address >> 8;
481 msg[2] = address & 0xff;
482 msg[3] = send_bytes - 1;
483 memcpy(&msg[4], send, send_bytes);
484 msg_bytes = send_bytes + 4;
486 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
489 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
491 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
499 /* Write a single byte to the aux channel in native mode */
501 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
502 uint16_t address, uint8_t byte)
504 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
507 /* read bytes from a native aux channel */
509 intel_dp_aux_native_read(struct intel_dp *intel_dp,
510 uint16_t address, uint8_t *recv, int recv_bytes)
519 intel_dp_check_edp(intel_dp);
520 msg[0] = AUX_NATIVE_READ << 4;
521 msg[1] = address >> 8;
522 msg[2] = address & 0xff;
523 msg[3] = recv_bytes - 1;
526 reply_bytes = recv_bytes + 1;
529 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
536 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
537 memcpy(recv, reply + 1, ret - 1);
540 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
548 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
549 uint8_t write_byte, uint8_t *read_byte)
551 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
552 struct intel_dp *intel_dp = container_of(adapter,
555 uint16_t address = algo_data->address;
563 intel_dp_check_edp(intel_dp);
564 /* Set up the command byte */
565 if (mode & MODE_I2C_READ)
566 msg[0] = AUX_I2C_READ << 4;
568 msg[0] = AUX_I2C_WRITE << 4;
570 if (!(mode & MODE_I2C_STOP))
571 msg[0] |= AUX_I2C_MOT << 4;
573 msg[1] = address >> 8;
594 for (retry = 0; retry < 5; retry++) {
595 ret = intel_dp_aux_ch(intel_dp,
599 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
603 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
604 case AUX_NATIVE_REPLY_ACK:
605 /* I2C-over-AUX Reply field is only valid
606 * when paired with AUX ACK.
609 case AUX_NATIVE_REPLY_NACK:
610 DRM_DEBUG_KMS("aux_ch native nack\n");
612 case AUX_NATIVE_REPLY_DEFER:
616 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
621 switch (reply[0] & AUX_I2C_REPLY_MASK) {
622 case AUX_I2C_REPLY_ACK:
623 if (mode == MODE_I2C_READ) {
624 *read_byte = reply[1];
626 return reply_bytes - 1;
627 case AUX_I2C_REPLY_NACK:
628 DRM_DEBUG_KMS("aux_i2c nack\n");
630 case AUX_I2C_REPLY_DEFER:
631 DRM_DEBUG_KMS("aux_i2c defer\n");
635 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
640 DRM_ERROR("too many retries, giving up\n");
644 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
645 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
648 intel_dp_i2c_init(struct intel_dp *intel_dp,
649 struct intel_connector *intel_connector, const char *name)
653 DRM_DEBUG_KMS("i2c_init %s\n", name);
654 intel_dp->algo.running = false;
655 intel_dp->algo.address = 0;
656 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
658 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
659 intel_dp->adapter.owner = THIS_MODULE;
660 intel_dp->adapter.class = I2C_CLASS_DDC;
661 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
662 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
663 intel_dp->adapter.algo_data = &intel_dp->algo;
664 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
666 ironlake_edp_panel_vdd_on(intel_dp);
667 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
668 ironlake_edp_panel_vdd_off(intel_dp, false);
673 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
674 struct drm_display_mode *adjusted_mode)
676 struct drm_device *dev = encoder->dev;
677 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
678 int lane_count, clock;
679 int max_lane_count = intel_dp_max_lane_count(intel_dp);
680 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
681 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
683 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
684 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
685 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
686 mode, adjusted_mode);
688 * the mode->clock is used to calculate the Data&Link M/N
689 * of the pipe. For the eDP the fixed clock should be used.
691 mode->clock = intel_dp->panel_fixed_mode->clock;
694 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
695 for (clock = 0; clock <= max_clock; clock++) {
696 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
698 if (intel_dp_link_required(intel_dp, mode->clock)
700 intel_dp->link_bw = bws[clock];
701 intel_dp->lane_count = lane_count;
702 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
703 DRM_DEBUG_KMS("Display port link bw %02x lane "
704 "count %d clock %d\n",
705 intel_dp->link_bw, intel_dp->lane_count,
706 adjusted_mode->clock);
715 struct intel_dp_m_n {
724 intel_reduce_ratio(uint32_t *num, uint32_t *den)
726 while (*num > 0xffffff || *den > 0xffffff) {
733 intel_dp_compute_m_n(int bpp,
737 struct intel_dp_m_n *m_n)
740 m_n->gmch_m = (pixel_clock * bpp) >> 3;
741 m_n->gmch_n = link_clock * nlanes;
742 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
743 m_n->link_m = pixel_clock;
744 m_n->link_n = link_clock;
745 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
749 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
750 struct drm_display_mode *adjusted_mode)
752 struct drm_device *dev = crtc->dev;
753 struct drm_mode_config *mode_config = &dev->mode_config;
754 struct drm_encoder *encoder;
755 struct drm_i915_private *dev_priv = dev->dev_private;
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758 struct intel_dp_m_n m_n;
759 int pipe = intel_crtc->pipe;
762 * Find the lane count in the intel_encoder private
764 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
765 struct intel_dp *intel_dp;
767 if (encoder->crtc != crtc)
770 intel_dp = enc_to_intel_dp(encoder);
771 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
772 lane_count = intel_dp->lane_count;
774 } else if (is_edp(intel_dp)) {
775 lane_count = dev_priv->edp.lanes;
781 * Compute the GMCH and Link ratios. The '3' here is
782 * the number of bytes_per_pixel post-LUT, which we always
783 * set up for 8-bits of R/G/B, or 3 bytes total.
785 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
786 mode->clock, adjusted_mode->clock, &m_n);
788 if (HAS_PCH_SPLIT(dev)) {
789 I915_WRITE(TRANSDATA_M1(pipe),
790 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
792 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
793 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
794 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
796 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
797 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
799 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
800 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
801 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
805 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
806 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
809 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
810 struct drm_display_mode *adjusted_mode)
812 struct drm_device *dev = encoder->dev;
813 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
814 struct drm_crtc *crtc = intel_dp->base.base.crtc;
815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
817 /* Turn on the eDP PLL if needed */
818 if (is_edp(intel_dp)) {
819 if (!is_pch_edp(intel_dp))
820 ironlake_edp_pll_on(encoder);
822 ironlake_edp_pll_off(encoder);
825 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
826 intel_dp->DP |= intel_dp->color_range;
828 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
829 intel_dp->DP |= DP_SYNC_HS_HIGH;
830 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
831 intel_dp->DP |= DP_SYNC_VS_HIGH;
833 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
834 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
836 intel_dp->DP |= DP_LINK_TRAIN_OFF;
838 switch (intel_dp->lane_count) {
840 intel_dp->DP |= DP_PORT_WIDTH_1;
843 intel_dp->DP |= DP_PORT_WIDTH_2;
846 intel_dp->DP |= DP_PORT_WIDTH_4;
849 if (intel_dp->has_audio) {
850 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
851 pipe_name(intel_crtc->pipe));
852 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
853 intel_write_eld(encoder, adjusted_mode);
856 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
857 intel_dp->link_configuration[0] = intel_dp->link_bw;
858 intel_dp->link_configuration[1] = intel_dp->lane_count;
859 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
862 * Check for DPCD version > 1.1 and enhanced framing support
864 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
865 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
866 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
867 intel_dp->DP |= DP_ENHANCED_FRAMING;
870 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
871 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
872 intel_dp->DP |= DP_PIPEB_SELECT;
874 if (is_cpu_edp(intel_dp)) {
875 /* don't miss out required setting for eDP */
876 intel_dp->DP |= DP_PLL_ENABLE;
877 if (adjusted_mode->clock < 200000)
878 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
880 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
884 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
886 unsigned long off_time;
889 DRM_DEBUG_KMS("Wait for panel power off time\n");
891 if (ironlake_edp_have_panel_power(intel_dp) ||
892 ironlake_edp_have_panel_vdd(intel_dp))
894 DRM_DEBUG_KMS("Panel still on, no delay needed\n");
898 off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
899 if (time_after(jiffies, off_time)) {
900 DRM_DEBUG_KMS("Time already passed");
903 delay = jiffies_to_msecs(off_time - jiffies);
904 if (delay > intel_dp->panel_power_down_delay)
905 delay = intel_dp->panel_power_down_delay;
906 DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
910 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
912 struct drm_device *dev = intel_dp->base.base.dev;
913 struct drm_i915_private *dev_priv = dev->dev_private;
916 if (!is_edp(intel_dp))
918 DRM_DEBUG_KMS("Turn eDP VDD on\n");
920 WARN(intel_dp->want_panel_vdd,
921 "eDP VDD already requested on\n");
923 intel_dp->want_panel_vdd = true;
924 if (ironlake_edp_have_panel_vdd(intel_dp)) {
925 DRM_DEBUG_KMS("eDP VDD already on\n");
929 ironlake_wait_panel_off(intel_dp);
930 pp = I915_READ(PCH_PP_CONTROL);
931 pp &= ~PANEL_UNLOCK_MASK;
932 pp |= PANEL_UNLOCK_REGS;
934 I915_WRITE(PCH_PP_CONTROL, pp);
935 POSTING_READ(PCH_PP_CONTROL);
936 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
937 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
940 * If the panel wasn't on, delay before accessing aux channel
942 if (!ironlake_edp_have_panel_power(intel_dp)) {
943 DRM_DEBUG_KMS("eDP was not running\n");
944 msleep(intel_dp->panel_power_up_delay);
948 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
950 struct drm_device *dev = intel_dp->base.base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
954 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
955 pp = I915_READ(PCH_PP_CONTROL);
956 pp &= ~PANEL_UNLOCK_MASK;
957 pp |= PANEL_UNLOCK_REGS;
958 pp &= ~EDP_FORCE_VDD;
959 I915_WRITE(PCH_PP_CONTROL, pp);
960 POSTING_READ(PCH_PP_CONTROL);
962 /* Make sure sequencer is idle before allowing subsequent activity */
963 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
964 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
965 intel_dp->panel_off_jiffies = jiffies;
969 static void ironlake_panel_vdd_work(struct work_struct *__work)
971 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
972 struct intel_dp, panel_vdd_work);
973 struct drm_device *dev = intel_dp->base.base.dev;
975 mutex_lock(&dev->struct_mutex);
976 ironlake_panel_vdd_off_sync(intel_dp);
977 mutex_unlock(&dev->struct_mutex);
980 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
982 if (!is_edp(intel_dp))
985 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
986 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
988 intel_dp->want_panel_vdd = false;
991 ironlake_panel_vdd_off_sync(intel_dp);
994 * Queue the timer to fire a long
995 * time from now (relative to the power down delay)
996 * to keep the panel power up across a sequence of operations
998 schedule_delayed_work(&intel_dp->panel_vdd_work,
999 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1003 /* Returns true if the panel was already on when called */
1004 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1006 struct drm_device *dev = intel_dp->base.base.dev;
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
1010 if (!is_edp(intel_dp))
1012 if (ironlake_edp_have_panel_power(intel_dp))
1015 ironlake_wait_panel_off(intel_dp);
1016 pp = I915_READ(PCH_PP_CONTROL);
1017 pp &= ~PANEL_UNLOCK_MASK;
1018 pp |= PANEL_UNLOCK_REGS;
1021 /* ILK workaround: disable reset around power sequence */
1022 pp &= ~PANEL_POWER_RESET;
1023 I915_WRITE(PCH_PP_CONTROL, pp);
1024 POSTING_READ(PCH_PP_CONTROL);
1027 pp |= POWER_TARGET_ON;
1028 I915_WRITE(PCH_PP_CONTROL, pp);
1029 POSTING_READ(PCH_PP_CONTROL);
1031 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1033 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1034 I915_READ(PCH_PP_STATUS));
1037 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1038 I915_WRITE(PCH_PP_CONTROL, pp);
1039 POSTING_READ(PCH_PP_CONTROL);
1043 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
1045 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1046 struct drm_device *dev = encoder->dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1049 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
1051 if (!is_edp(intel_dp))
1053 pp = I915_READ(PCH_PP_CONTROL);
1054 pp &= ~PANEL_UNLOCK_MASK;
1055 pp |= PANEL_UNLOCK_REGS;
1058 /* ILK workaround: disable reset around power sequence */
1059 pp &= ~PANEL_POWER_RESET;
1060 I915_WRITE(PCH_PP_CONTROL, pp);
1061 POSTING_READ(PCH_PP_CONTROL);
1064 intel_dp->panel_off_jiffies = jiffies;
1067 pp &= ~POWER_TARGET_ON;
1068 I915_WRITE(PCH_PP_CONTROL, pp);
1069 POSTING_READ(PCH_PP_CONTROL);
1070 pp &= ~POWER_TARGET_ON;
1071 I915_WRITE(PCH_PP_CONTROL, pp);
1072 POSTING_READ(PCH_PP_CONTROL);
1073 msleep(intel_dp->panel_power_cycle_delay);
1075 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1076 DRM_ERROR("panel off wait timed out: 0x%08x\n",
1077 I915_READ(PCH_PP_STATUS));
1079 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1080 I915_WRITE(PCH_PP_CONTROL, pp);
1081 POSTING_READ(PCH_PP_CONTROL);
1085 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1087 struct drm_device *dev = intel_dp->base.base.dev;
1088 struct drm_i915_private *dev_priv = dev->dev_private;
1091 if (!is_edp(intel_dp))
1094 DRM_DEBUG_KMS("\n");
1096 * If we enable the backlight right away following a panel power
1097 * on, we may see slight flicker as the panel syncs with the eDP
1098 * link. So delay a bit to make sure the image is solid before
1099 * allowing it to appear.
1101 msleep(intel_dp->backlight_on_delay);
1102 pp = I915_READ(PCH_PP_CONTROL);
1103 pp &= ~PANEL_UNLOCK_MASK;
1104 pp |= PANEL_UNLOCK_REGS;
1105 pp |= EDP_BLC_ENABLE;
1106 I915_WRITE(PCH_PP_CONTROL, pp);
1107 POSTING_READ(PCH_PP_CONTROL);
1110 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1112 struct drm_device *dev = intel_dp->base.base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1116 if (!is_edp(intel_dp))
1119 DRM_DEBUG_KMS("\n");
1120 pp = I915_READ(PCH_PP_CONTROL);
1121 pp &= ~PANEL_UNLOCK_MASK;
1122 pp |= PANEL_UNLOCK_REGS;
1123 pp &= ~EDP_BLC_ENABLE;
1124 I915_WRITE(PCH_PP_CONTROL, pp);
1125 POSTING_READ(PCH_PP_CONTROL);
1126 msleep(intel_dp->backlight_off_delay);
1129 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1131 struct drm_device *dev = encoder->dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1135 DRM_DEBUG_KMS("\n");
1136 dpa_ctl = I915_READ(DP_A);
1137 dpa_ctl |= DP_PLL_ENABLE;
1138 I915_WRITE(DP_A, dpa_ctl);
1143 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1145 struct drm_device *dev = encoder->dev;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1149 dpa_ctl = I915_READ(DP_A);
1150 dpa_ctl &= ~DP_PLL_ENABLE;
1151 I915_WRITE(DP_A, dpa_ctl);
1156 /* If the sink supports it, try to set the power state appropriately */
1157 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1161 /* Should have a valid DPCD by this point */
1162 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1165 if (mode != DRM_MODE_DPMS_ON) {
1166 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1169 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1172 * When turning on, we need to retry for 1ms to give the sink
1175 for (i = 0; i < 3; i++) {
1176 ret = intel_dp_aux_native_write_1(intel_dp,
1186 static void intel_dp_prepare(struct drm_encoder *encoder)
1188 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1190 /* Wake up the sink first */
1191 ironlake_edp_panel_vdd_on(intel_dp);
1192 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1193 ironlake_edp_panel_vdd_off(intel_dp, false);
1195 /* Make sure the panel is off before trying to
1198 ironlake_edp_backlight_off(intel_dp);
1199 intel_dp_link_down(intel_dp);
1200 ironlake_edp_panel_off(encoder);
1203 static void intel_dp_commit(struct drm_encoder *encoder)
1205 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1206 struct drm_device *dev = encoder->dev;
1207 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1209 ironlake_edp_panel_vdd_on(intel_dp);
1210 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1211 intel_dp_start_link_train(intel_dp);
1212 ironlake_edp_panel_on(intel_dp);
1213 ironlake_edp_panel_vdd_off(intel_dp, true);
1215 intel_dp_complete_link_train(intel_dp);
1216 ironlake_edp_backlight_on(intel_dp);
1218 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1220 if (HAS_PCH_CPT(dev))
1221 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1225 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1227 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1228 struct drm_device *dev = encoder->dev;
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1232 if (mode != DRM_MODE_DPMS_ON) {
1233 ironlake_edp_panel_vdd_on(intel_dp);
1234 if (is_edp(intel_dp))
1235 ironlake_edp_backlight_off(intel_dp);
1236 intel_dp_sink_dpms(intel_dp, mode);
1237 intel_dp_link_down(intel_dp);
1238 ironlake_edp_panel_off(encoder);
1239 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1240 ironlake_edp_pll_off(encoder);
1241 ironlake_edp_panel_vdd_off(intel_dp, false);
1243 ironlake_edp_panel_vdd_on(intel_dp);
1244 intel_dp_sink_dpms(intel_dp, mode);
1245 if (!(dp_reg & DP_PORT_EN)) {
1246 intel_dp_start_link_train(intel_dp);
1247 ironlake_edp_panel_on(intel_dp);
1248 ironlake_edp_panel_vdd_off(intel_dp, true);
1249 intel_dp_complete_link_train(intel_dp);
1250 ironlake_edp_backlight_on(intel_dp);
1252 ironlake_edp_panel_vdd_off(intel_dp, false);
1253 ironlake_edp_backlight_on(intel_dp);
1255 intel_dp->dpms_mode = mode;
1259 * Native read with retry for link status and receiver capability reads for
1260 * cases where the sink may still be asleep.
1263 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1264 uint8_t *recv, int recv_bytes)
1269 * Sinks are *supposed* to come up within 1ms from an off state,
1270 * but we're also supposed to retry 3 times per the spec.
1272 for (i = 0; i < 3; i++) {
1273 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1275 if (ret == recv_bytes)
1284 * Fetch AUX CH registers 0x202 - 0x207 which contain
1285 * link status information
1288 intel_dp_get_link_status(struct intel_dp *intel_dp)
1290 return intel_dp_aux_native_read_retry(intel_dp,
1292 intel_dp->link_status,
1293 DP_LINK_STATUS_SIZE);
1297 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1300 return link_status[r - DP_LANE0_1_STATUS];
1304 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1307 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1308 int s = ((lane & 1) ?
1309 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1310 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1311 uint8_t l = intel_dp_link_status(link_status, i);
1313 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1317 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1320 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1321 int s = ((lane & 1) ?
1322 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1323 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1324 uint8_t l = intel_dp_link_status(link_status, i);
1326 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1331 static char *voltage_names[] = {
1332 "0.4V", "0.6V", "0.8V", "1.2V"
1334 static char *pre_emph_names[] = {
1335 "0dB", "3.5dB", "6dB", "9.5dB"
1337 static char *link_train_names[] = {
1338 "pattern 1", "pattern 2", "idle", "off"
1343 * These are source-specific values; current Intel hardware supports
1344 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1346 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1349 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1351 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1352 case DP_TRAIN_VOLTAGE_SWING_400:
1353 return DP_TRAIN_PRE_EMPHASIS_6;
1354 case DP_TRAIN_VOLTAGE_SWING_600:
1355 return DP_TRAIN_PRE_EMPHASIS_6;
1356 case DP_TRAIN_VOLTAGE_SWING_800:
1357 return DP_TRAIN_PRE_EMPHASIS_3_5;
1358 case DP_TRAIN_VOLTAGE_SWING_1200:
1360 return DP_TRAIN_PRE_EMPHASIS_0;
1365 intel_get_adjust_train(struct intel_dp *intel_dp)
1371 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1372 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1373 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1381 if (v >= I830_DP_VOLTAGE_MAX)
1382 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1384 if (p >= intel_dp_pre_emphasis_max(v))
1385 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1387 for (lane = 0; lane < 4; lane++)
1388 intel_dp->train_set[lane] = v | p;
1392 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1394 uint32_t signal_levels = 0;
1396 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1397 case DP_TRAIN_VOLTAGE_SWING_400:
1399 signal_levels |= DP_VOLTAGE_0_4;
1401 case DP_TRAIN_VOLTAGE_SWING_600:
1402 signal_levels |= DP_VOLTAGE_0_6;
1404 case DP_TRAIN_VOLTAGE_SWING_800:
1405 signal_levels |= DP_VOLTAGE_0_8;
1407 case DP_TRAIN_VOLTAGE_SWING_1200:
1408 signal_levels |= DP_VOLTAGE_1_2;
1411 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1412 case DP_TRAIN_PRE_EMPHASIS_0:
1414 signal_levels |= DP_PRE_EMPHASIS_0;
1416 case DP_TRAIN_PRE_EMPHASIS_3_5:
1417 signal_levels |= DP_PRE_EMPHASIS_3_5;
1419 case DP_TRAIN_PRE_EMPHASIS_6:
1420 signal_levels |= DP_PRE_EMPHASIS_6;
1422 case DP_TRAIN_PRE_EMPHASIS_9_5:
1423 signal_levels |= DP_PRE_EMPHASIS_9_5;
1426 return signal_levels;
1429 /* Gen6's DP voltage swing and pre-emphasis control */
1431 intel_gen6_edp_signal_levels(uint8_t train_set)
1433 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1434 DP_TRAIN_PRE_EMPHASIS_MASK);
1435 switch (signal_levels) {
1436 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1437 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1438 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1439 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1440 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1441 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1442 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1443 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1444 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1445 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1446 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1447 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1448 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1449 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1451 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1452 "0x%x\n", signal_levels);
1453 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1458 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1461 int i = DP_LANE0_1_STATUS + (lane >> 1);
1462 int s = (lane & 1) * 4;
1463 uint8_t l = intel_dp_link_status(link_status, i);
1465 return (l >> s) & 0xf;
1468 /* Check for clock recovery is done on all channels */
1470 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1473 uint8_t lane_status;
1475 for (lane = 0; lane < lane_count; lane++) {
1476 lane_status = intel_get_lane_status(link_status, lane);
1477 if ((lane_status & DP_LANE_CR_DONE) == 0)
1483 /* Check to see if channel eq is done on all channels */
1484 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1485 DP_LANE_CHANNEL_EQ_DONE|\
1486 DP_LANE_SYMBOL_LOCKED)
1488 intel_channel_eq_ok(struct intel_dp *intel_dp)
1491 uint8_t lane_status;
1494 lane_align = intel_dp_link_status(intel_dp->link_status,
1495 DP_LANE_ALIGN_STATUS_UPDATED);
1496 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1498 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1499 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1500 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1507 intel_dp_set_link_train(struct intel_dp *intel_dp,
1508 uint32_t dp_reg_value,
1509 uint8_t dp_train_pat)
1511 struct drm_device *dev = intel_dp->base.base.dev;
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1515 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1516 POSTING_READ(intel_dp->output_reg);
1518 intel_dp_aux_native_write_1(intel_dp,
1519 DP_TRAINING_PATTERN_SET,
1522 ret = intel_dp_aux_native_write(intel_dp,
1523 DP_TRAINING_LANE0_SET,
1524 intel_dp->train_set, 4);
1531 /* Enable corresponding port and start training pattern 1 */
1533 intel_dp_start_link_train(struct intel_dp *intel_dp)
1535 struct drm_device *dev = intel_dp->base.base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1540 bool clock_recovery = false;
1543 uint32_t DP = intel_dp->DP;
1546 * On CPT we have to enable the port in training pattern 1, which
1547 * will happen below in intel_dp_set_link_train. Otherwise, enable
1548 * the port and wait for it to become active.
1550 if (!HAS_PCH_CPT(dev)) {
1551 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1552 POSTING_READ(intel_dp->output_reg);
1553 intel_wait_for_vblank(dev, intel_crtc->pipe);
1556 /* Write the link configuration data */
1557 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1558 intel_dp->link_configuration,
1559 DP_LINK_CONFIGURATION_SIZE);
1562 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1563 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1565 DP &= ~DP_LINK_TRAIN_MASK;
1566 memset(intel_dp->train_set, 0, 4);
1569 clock_recovery = false;
1571 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1572 uint32_t signal_levels;
1573 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1574 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1575 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1577 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1578 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1581 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1582 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1584 reg = DP | DP_LINK_TRAIN_PAT_1;
1586 if (!intel_dp_set_link_train(intel_dp, reg,
1587 DP_TRAINING_PATTERN_1 |
1588 DP_LINK_SCRAMBLING_DISABLE))
1590 /* Set training pattern 1 */
1593 if (!intel_dp_get_link_status(intel_dp))
1596 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1597 clock_recovery = true;
1601 /* Check to see if we've tried the max voltage */
1602 for (i = 0; i < intel_dp->lane_count; i++)
1603 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1605 if (i == intel_dp->lane_count)
1608 /* Check to see if we've tried the same voltage 5 times */
1609 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1615 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1617 /* Compute new intel_dp->train_set as requested by target */
1618 intel_get_adjust_train(intel_dp);
1625 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1627 struct drm_device *dev = intel_dp->base.base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 bool channel_eq = false;
1630 int tries, cr_tries;
1632 uint32_t DP = intel_dp->DP;
1634 /* channel equalization */
1639 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1640 uint32_t signal_levels;
1643 DRM_ERROR("failed to train DP, aborting\n");
1644 intel_dp_link_down(intel_dp);
1648 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1649 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1650 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1652 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1653 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1656 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1657 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1659 reg = DP | DP_LINK_TRAIN_PAT_2;
1661 /* channel eq pattern */
1662 if (!intel_dp_set_link_train(intel_dp, reg,
1663 DP_TRAINING_PATTERN_2 |
1664 DP_LINK_SCRAMBLING_DISABLE))
1668 if (!intel_dp_get_link_status(intel_dp))
1671 /* Make sure clock is still ok */
1672 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1673 intel_dp_start_link_train(intel_dp);
1678 if (intel_channel_eq_ok(intel_dp)) {
1683 /* Try 5 times, then try clock recovery if that fails */
1685 intel_dp_link_down(intel_dp);
1686 intel_dp_start_link_train(intel_dp);
1692 /* Compute new intel_dp->train_set as requested by target */
1693 intel_get_adjust_train(intel_dp);
1697 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1698 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1700 reg = DP | DP_LINK_TRAIN_OFF;
1702 I915_WRITE(intel_dp->output_reg, reg);
1703 POSTING_READ(intel_dp->output_reg);
1704 intel_dp_aux_native_write_1(intel_dp,
1705 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1709 intel_dp_link_down(struct intel_dp *intel_dp)
1711 struct drm_device *dev = intel_dp->base.base.dev;
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713 uint32_t DP = intel_dp->DP;
1715 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1718 DRM_DEBUG_KMS("\n");
1720 if (is_edp(intel_dp)) {
1721 DP &= ~DP_PLL_ENABLE;
1722 I915_WRITE(intel_dp->output_reg, DP);
1723 POSTING_READ(intel_dp->output_reg);
1727 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1728 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1729 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1731 DP &= ~DP_LINK_TRAIN_MASK;
1732 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1734 POSTING_READ(intel_dp->output_reg);
1738 if (is_edp(intel_dp))
1739 DP |= DP_LINK_TRAIN_OFF;
1741 if (!HAS_PCH_CPT(dev) &&
1742 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1743 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1745 /* Hardware workaround: leaving our transcoder select
1746 * set to transcoder B while it's off will prevent the
1747 * corresponding HDMI output on transcoder A.
1749 * Combine this with another hardware workaround:
1750 * transcoder select bit can only be cleared while the
1753 DP &= ~DP_PIPEB_SELECT;
1754 I915_WRITE(intel_dp->output_reg, DP);
1756 /* Changes to enable or select take place the vblank
1757 * after being written.
1760 /* We can arrive here never having been attached
1761 * to a CRTC, for instance, due to inheriting
1762 * random state from the BIOS.
1764 * If the pipe is not running, play safe and
1765 * wait for the clocks to stabilise before
1768 POSTING_READ(intel_dp->output_reg);
1771 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1774 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1775 POSTING_READ(intel_dp->output_reg);
1776 msleep(intel_dp->panel_power_down_delay);
1780 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1782 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1783 sizeof(intel_dp->dpcd)) &&
1784 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1792 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1796 ret = intel_dp_aux_native_read_retry(intel_dp,
1797 DP_DEVICE_SERVICE_IRQ_VECTOR,
1798 sink_irq_vector, 1);
1806 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1808 /* NAK by default */
1809 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1813 * According to DP spec
1816 * 2. Configure link according to Receiver Capabilities
1817 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1818 * 4. Check link status on receipt of hot-plug interrupt
1822 intel_dp_check_link_status(struct intel_dp *intel_dp)
1826 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1829 if (!intel_dp->base.base.crtc)
1832 /* Try to read receiver status if the link appears to be up */
1833 if (!intel_dp_get_link_status(intel_dp)) {
1834 intel_dp_link_down(intel_dp);
1838 /* Now read the DPCD to see if it's actually running */
1839 if (!intel_dp_get_dpcd(intel_dp)) {
1840 intel_dp_link_down(intel_dp);
1844 /* Try to read the source of the interrupt */
1845 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1846 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1847 /* Clear interrupt source */
1848 intel_dp_aux_native_write_1(intel_dp,
1849 DP_DEVICE_SERVICE_IRQ_VECTOR,
1852 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1853 intel_dp_handle_test_request(intel_dp);
1854 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1855 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1858 if (!intel_channel_eq_ok(intel_dp)) {
1859 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1860 drm_get_encoder_name(&intel_dp->base.base));
1861 intel_dp_start_link_train(intel_dp);
1862 intel_dp_complete_link_train(intel_dp);
1866 static enum drm_connector_status
1867 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1869 if (intel_dp_get_dpcd(intel_dp))
1870 return connector_status_connected;
1871 return connector_status_disconnected;
1874 static enum drm_connector_status
1875 ironlake_dp_detect(struct intel_dp *intel_dp)
1877 enum drm_connector_status status;
1879 /* Can't disconnect eDP, but you can close the lid... */
1880 if (is_edp(intel_dp)) {
1881 status = intel_panel_detect(intel_dp->base.base.dev);
1882 if (status == connector_status_unknown)
1883 status = connector_status_connected;
1887 return intel_dp_detect_dpcd(intel_dp);
1890 static enum drm_connector_status
1891 g4x_dp_detect(struct intel_dp *intel_dp)
1893 struct drm_device *dev = intel_dp->base.base.dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1897 switch (intel_dp->output_reg) {
1899 bit = DPB_HOTPLUG_INT_STATUS;
1902 bit = DPC_HOTPLUG_INT_STATUS;
1905 bit = DPD_HOTPLUG_INT_STATUS;
1908 return connector_status_unknown;
1911 temp = I915_READ(PORT_HOTPLUG_STAT);
1913 if ((temp & bit) == 0)
1914 return connector_status_disconnected;
1916 return intel_dp_detect_dpcd(intel_dp);
1919 static struct edid *
1920 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1922 struct intel_dp *intel_dp = intel_attached_dp(connector);
1925 ironlake_edp_panel_vdd_on(intel_dp);
1926 edid = drm_get_edid(connector, adapter);
1927 ironlake_edp_panel_vdd_off(intel_dp, false);
1932 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1934 struct intel_dp *intel_dp = intel_attached_dp(connector);
1937 ironlake_edp_panel_vdd_on(intel_dp);
1938 ret = intel_ddc_get_modes(connector, adapter);
1939 ironlake_edp_panel_vdd_off(intel_dp, false);
1945 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1947 * \return true if DP port is connected.
1948 * \return false if DP port is disconnected.
1950 static enum drm_connector_status
1951 intel_dp_detect(struct drm_connector *connector, bool force)
1953 struct intel_dp *intel_dp = intel_attached_dp(connector);
1954 struct drm_device *dev = intel_dp->base.base.dev;
1955 enum drm_connector_status status;
1956 struct edid *edid = NULL;
1958 intel_dp->has_audio = false;
1960 if (HAS_PCH_SPLIT(dev))
1961 status = ironlake_dp_detect(intel_dp);
1963 status = g4x_dp_detect(intel_dp);
1965 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1966 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1967 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1968 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1970 if (status != connector_status_connected)
1973 if (intel_dp->force_audio) {
1974 intel_dp->has_audio = intel_dp->force_audio > 0;
1976 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1978 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1979 connector->display_info.raw_edid = NULL;
1984 return connector_status_connected;
1987 static int intel_dp_get_modes(struct drm_connector *connector)
1989 struct intel_dp *intel_dp = intel_attached_dp(connector);
1990 struct drm_device *dev = intel_dp->base.base.dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1994 /* We should parse the EDID data and find out if it has an audio sink
1997 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1999 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2000 struct drm_display_mode *newmode;
2001 list_for_each_entry(newmode, &connector->probed_modes,
2003 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2004 intel_dp->panel_fixed_mode =
2005 drm_mode_duplicate(dev, newmode);
2013 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2014 if (is_edp(intel_dp)) {
2015 /* initialize panel mode from VBT if available for eDP */
2016 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2017 intel_dp->panel_fixed_mode =
2018 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2019 if (intel_dp->panel_fixed_mode) {
2020 intel_dp->panel_fixed_mode->type |=
2021 DRM_MODE_TYPE_PREFERRED;
2024 if (intel_dp->panel_fixed_mode) {
2025 struct drm_display_mode *mode;
2026 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2027 drm_mode_probed_add(connector, mode);
2035 intel_dp_detect_audio(struct drm_connector *connector)
2037 struct intel_dp *intel_dp = intel_attached_dp(connector);
2039 bool has_audio = false;
2041 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2043 has_audio = drm_detect_monitor_audio(edid);
2045 connector->display_info.raw_edid = NULL;
2053 intel_dp_set_property(struct drm_connector *connector,
2054 struct drm_property *property,
2057 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2058 struct intel_dp *intel_dp = intel_attached_dp(connector);
2061 ret = drm_connector_property_set_value(connector, property, val);
2065 if (property == dev_priv->force_audio_property) {
2069 if (i == intel_dp->force_audio)
2072 intel_dp->force_audio = i;
2075 has_audio = intel_dp_detect_audio(connector);
2079 if (has_audio == intel_dp->has_audio)
2082 intel_dp->has_audio = has_audio;
2086 if (property == dev_priv->broadcast_rgb_property) {
2087 if (val == !!intel_dp->color_range)
2090 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2097 if (intel_dp->base.base.crtc) {
2098 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2099 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2108 intel_dp_destroy(struct drm_connector *connector)
2110 struct drm_device *dev = connector->dev;
2112 if (intel_dpd_is_edp(dev))
2113 intel_panel_destroy_backlight(dev);
2115 drm_sysfs_connector_remove(connector);
2116 drm_connector_cleanup(connector);
2120 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2122 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2124 i2c_del_adapter(&intel_dp->adapter);
2125 drm_encoder_cleanup(encoder);
2126 if (is_edp(intel_dp)) {
2127 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2128 ironlake_panel_vdd_off_sync(intel_dp);
2133 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2134 .dpms = intel_dp_dpms,
2135 .mode_fixup = intel_dp_mode_fixup,
2136 .prepare = intel_dp_prepare,
2137 .mode_set = intel_dp_mode_set,
2138 .commit = intel_dp_commit,
2141 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2142 .dpms = drm_helper_connector_dpms,
2143 .detect = intel_dp_detect,
2144 .fill_modes = drm_helper_probe_single_connector_modes,
2145 .set_property = intel_dp_set_property,
2146 .destroy = intel_dp_destroy,
2149 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2150 .get_modes = intel_dp_get_modes,
2151 .mode_valid = intel_dp_mode_valid,
2152 .best_encoder = intel_best_encoder,
2155 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2156 .destroy = intel_dp_encoder_destroy,
2160 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2162 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2164 intel_dp_check_link_status(intel_dp);
2167 /* Return which DP Port should be selected for Transcoder DP control */
2169 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2171 struct drm_device *dev = crtc->dev;
2172 struct drm_mode_config *mode_config = &dev->mode_config;
2173 struct drm_encoder *encoder;
2175 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2176 struct intel_dp *intel_dp;
2178 if (encoder->crtc != crtc)
2181 intel_dp = enc_to_intel_dp(encoder);
2182 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2183 return intel_dp->output_reg;
2189 /* check the VBT to see whether the eDP is on DP-D port */
2190 bool intel_dpd_is_edp(struct drm_device *dev)
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 struct child_device_config *p_child;
2196 if (!dev_priv->child_dev_num)
2199 for (i = 0; i < dev_priv->child_dev_num; i++) {
2200 p_child = dev_priv->child_dev + i;
2202 if (p_child->dvo_port == PORT_IDPD &&
2203 p_child->device_type == DEVICE_TYPE_eDP)
2210 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2212 intel_attach_force_audio_property(connector);
2213 intel_attach_broadcast_rgb_property(connector);
2217 intel_dp_init(struct drm_device *dev, int output_reg)
2219 struct drm_i915_private *dev_priv = dev->dev_private;
2220 struct drm_connector *connector;
2221 struct intel_dp *intel_dp;
2222 struct intel_encoder *intel_encoder;
2223 struct intel_connector *intel_connector;
2224 const char *name = NULL;
2227 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2231 intel_dp->output_reg = output_reg;
2232 intel_dp->dpms_mode = -1;
2234 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2235 if (!intel_connector) {
2239 intel_encoder = &intel_dp->base;
2241 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2242 if (intel_dpd_is_edp(dev))
2243 intel_dp->is_pch_edp = true;
2245 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2246 type = DRM_MODE_CONNECTOR_eDP;
2247 intel_encoder->type = INTEL_OUTPUT_EDP;
2249 type = DRM_MODE_CONNECTOR_DisplayPort;
2250 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2253 connector = &intel_connector->base;
2254 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2255 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2257 connector->polled = DRM_CONNECTOR_POLL_HPD;
2259 if (output_reg == DP_B || output_reg == PCH_DP_B)
2260 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2261 else if (output_reg == DP_C || output_reg == PCH_DP_C)
2262 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2263 else if (output_reg == DP_D || output_reg == PCH_DP_D)
2264 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2266 if (is_edp(intel_dp)) {
2267 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2268 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2269 ironlake_panel_vdd_work);
2272 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2273 connector->interlace_allowed = true;
2274 connector->doublescan_allowed = 0;
2276 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2277 DRM_MODE_ENCODER_TMDS);
2278 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2280 intel_connector_attach_encoder(intel_connector, intel_encoder);
2281 drm_sysfs_connector_add(connector);
2283 /* Set up the DDC bus. */
2284 switch (output_reg) {
2290 dev_priv->hotplug_supported_mask |=
2291 HDMIB_HOTPLUG_INT_STATUS;
2296 dev_priv->hotplug_supported_mask |=
2297 HDMIC_HOTPLUG_INT_STATUS;
2302 dev_priv->hotplug_supported_mask |=
2303 HDMID_HOTPLUG_INT_STATUS;
2308 /* Cache some DPCD data in the eDP case */
2309 if (is_edp(intel_dp)) {
2311 struct edp_power_seq cur, vbt;
2312 u32 pp_on, pp_off, pp_div;
2314 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2315 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2316 pp_div = I915_READ(PCH_PP_DIVISOR);
2318 /* Pull timing values out of registers */
2319 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2320 PANEL_POWER_UP_DELAY_SHIFT;
2322 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2323 PANEL_LIGHT_ON_DELAY_SHIFT;
2325 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2326 PANEL_LIGHT_OFF_DELAY_SHIFT;
2328 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2329 PANEL_POWER_DOWN_DELAY_SHIFT;
2331 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2332 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2334 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2335 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2337 vbt = dev_priv->edp.pps;
2339 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2340 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2342 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2344 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2345 intel_dp->backlight_on_delay = get_delay(t8);
2346 intel_dp->backlight_off_delay = get_delay(t9);
2347 intel_dp->panel_power_down_delay = get_delay(t10);
2348 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2350 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2351 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2352 intel_dp->panel_power_cycle_delay);
2354 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2355 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2357 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
2359 ironlake_edp_panel_vdd_on(intel_dp);
2360 ret = intel_dp_get_dpcd(intel_dp);
2361 ironlake_edp_panel_vdd_off(intel_dp, false);
2363 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2364 dev_priv->no_aux_handshake =
2365 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2366 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2368 /* if this fails, presume the device is a ghost */
2369 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2370 intel_dp_encoder_destroy(&intel_dp->base.base);
2371 intel_dp_destroy(&intel_connector->base);
2376 intel_dp_i2c_init(intel_dp, intel_connector, name);
2378 intel_encoder->hot_plug = intel_dp_hot_plug;
2380 if (is_edp(intel_dp)) {
2381 dev_priv->int_edp_connector = connector;
2382 intel_panel_setup_backlight(dev);
2385 intel_dp_add_properties(intel_dp, connector);
2387 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2388 * 0xd. Failure to do so will result in spurious interrupts being
2389 * generated on the port when a cable is not attached.
2391 if (IS_G4X(dev) && !IS_GM45(dev)) {
2392 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2393 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);