drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132
 133 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 134 {
 135         return ~((1 << lane_count) - 1) & 0xf;
 136 }
 137
 138 static int
 139 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 140 {
 141         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 142
 143         switch (max_link_bw) {
 144         case DP_LINK_BW_1_62:
 145         case DP_LINK_BW_2_7:
 146         case DP_LINK_BW_5_4:
 147                 break;
 148         default:
 149                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 150                      max_link_bw);
 151                 max_link_bw = DP_LINK_BW_1_62;
 152                 break;
 153         }
 154         return max_link_bw;
 155 }
 156
 157 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 158 {
 159         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 160         struct drm_device *dev = intel_dig_port->base.base.dev;
 161         u8 source_max, sink_max;
 162
 163         source_max = 4;
 164         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 165             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 166                 source_max = 2;
 167
 168         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 169
 170         return min(source_max, sink_max);
 171 }
 172
 173 /*
 174  * The units on the numbers in the next two are... bizarre.  Examples will
 175  * make it clearer; this one parallels an example in the eDP spec.
 176  *
 177  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 178  *
 179  *     270000 * 1 * 8 / 10 == 216000
 180  *
 181  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 182  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 183  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 184  * 119000.  At 18bpp that's 2142000 kilobits per second.
 185  *
 186  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 187  * get the result in decakilobits instead of kilobits.
 188  */
 189
 190 static int
 191 intel_dp_link_required(int pixel_clock, int bpp)
 192 {
 193         return (pixel_clock * bpp + 9) / 10;
 194 }
 195
 196 static int
 197 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 198 {
 199         return (max_link_clock * max_lanes * 8) / 10;
 200 }
 201
 202 static enum drm_mode_status
 203 intel_dp_mode_valid(struct drm_connector *connector,
 204                     struct drm_display_mode *mode)
 205 {
 206         struct intel_dp *intel_dp = intel_attached_dp(connector);
 207         struct intel_connector *intel_connector = to_intel_connector(connector);
 208         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 209         int target_clock = mode->clock;
 210         int max_rate, mode_rate, max_lanes, max_link_clock;
 211
 212         if (is_edp(intel_dp) && fixed_mode) {
 213                 if (mode->hdisplay > fixed_mode->hdisplay)
 214                         return MODE_PANEL;
 215
 216                 if (mode->vdisplay > fixed_mode->vdisplay)
 217                         return MODE_PANEL;
 218
 219                 target_clock = fixed_mode->clock;
 220         }
 221
 222         max_link_clock = intel_dp_max_link_rate(intel_dp);
 223         max_lanes = intel_dp_max_lane_count(intel_dp);
 224
 225         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 226         mode_rate = intel_dp_link_required(target_clock, 18);
 227
 228         if (mode_rate > max_rate)
 229                 return MODE_CLOCK_HIGH;
 230
 231         if (mode->clock < 10000)
 232                 return MODE_CLOCK_LOW;
 233
 234         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 235                 return MODE_H_ILLEGAL;
 236
 237         return MODE_OK;
 238 }
 239
 240 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 241 {
 242         int     i;
 243         uint32_t v = 0;
 244
 245         if (src_bytes > 4)
 246                 src_bytes = 4;
 247         for (i = 0; i < src_bytes; i++)
 248                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 249         return v;
 250 }
 251
 252 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 253 {
 254         int i;
 255         if (dst_bytes > 4)
 256                 dst_bytes = 4;
 257         for (i = 0; i < dst_bytes; i++)
 258                 dst[i] = src >> ((3-i) * 8);
 259 }
 260
 261 static void
 262 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 263                                     struct intel_dp *intel_dp);
 264 static void
 265 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 266                                               struct intel_dp *intel_dp);
 267
 268 static void pps_lock(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 271         struct intel_encoder *encoder = &intel_dig_port->base;
 272         struct drm_device *dev = encoder->base.dev;
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         enum intel_display_power_domain power_domain;
 275
 276         /*
 277          * See vlv_power_sequencer_reset() why we need
 278          * a power domain reference here.
 279          */
 280         power_domain = intel_display_port_power_domain(encoder);
 281         intel_display_power_get(dev_priv, power_domain);
 282
 283         mutex_lock(&dev_priv->pps_mutex);
 284 }
 285
 286 static void pps_unlock(struct intel_dp *intel_dp)
 287 {
 288         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 289         struct intel_encoder *encoder = &intel_dig_port->base;
 290         struct drm_device *dev = encoder->base.dev;
 291         struct drm_i915_private *dev_priv = dev->dev_private;
 292         enum intel_display_power_domain power_domain;
 293
 294         mutex_unlock(&dev_priv->pps_mutex);
 295
 296         power_domain = intel_display_port_power_domain(encoder);
 297         intel_display_power_put(dev_priv, power_domain);
 298 }
 299
 300 static void
 301 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 302 {
 303         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 304         struct drm_device *dev = intel_dig_port->base.base.dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         enum pipe pipe = intel_dp->pps_pipe;
 307         bool pll_enabled, release_cl_override = false;
 308         enum dpio_phy phy = DPIO_PHY(pipe);
 309         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 310         uint32_t DP;
 311
 312         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 313                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 314                  pipe_name(pipe), port_name(intel_dig_port->port)))
 315                 return;
 316
 317         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 318                       pipe_name(pipe), port_name(intel_dig_port->port));
 319
 320         /* Preserve the BIOS-computed detected bit. This is
 321          * supposed to be read-only.
 322          */
 323         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 324         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 325         DP |= DP_PORT_WIDTH(1);
 326         DP |= DP_LINK_TRAIN_PAT_1;
 327
 328         if (IS_CHERRYVIEW(dev))
 329                 DP |= DP_PIPE_SELECT_CHV(pipe);
 330         else if (pipe == PIPE_B)
 331                 DP |= DP_PIPEB_SELECT;
 332
 333         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 334
 335         /*
 336          * The DPLL for the pipe must be enabled for this to work.
 337          * So enable temporarily it if it's not already enabled.
 338          */
 339         if (!pll_enabled) {
 340                 release_cl_override = IS_CHERRYVIEW(dev) &&
 341                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 342
 343                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 344                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 345         }
 346
 347         /*
 348          * Similar magic as in intel_dp_enable_port().
 349          * We _must_ do this port enable + disable trick
 350          * to make this power seqeuencer lock onto the port.
 351          * Otherwise even VDD force bit won't work.
 352          */
 353         I915_WRITE(intel_dp->output_reg, DP);
 354         POSTING_READ(intel_dp->output_reg);
 355
 356         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 357         POSTING_READ(intel_dp->output_reg);
 358
 359         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 360         POSTING_READ(intel_dp->output_reg);
 361
 362         if (!pll_enabled) {
 363                 vlv_force_pll_off(dev, pipe);
 364
 365                 if (release_cl_override)
 366                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 367         }
 368 }
 369
 370 static enum pipe
 371 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 372 {
 373         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 374         struct drm_device *dev = intel_dig_port->base.base.dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376         struct intel_encoder *encoder;
 377         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 378         enum pipe pipe;
 379
 380         lockdep_assert_held(&dev_priv->pps_mutex);
 381
 382         /* We should never land here with regular DP ports */
 383         WARN_ON(!is_edp(intel_dp));
 384
 385         if (intel_dp->pps_pipe != INVALID_PIPE)
 386                 return intel_dp->pps_pipe;
 387
 388         /*
 389          * We don't have power sequencer currently.
 390          * Pick one that's not used by other ports.
 391          */
 392         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 393                             base.head) {
 394                 struct intel_dp *tmp;
 395
 396                 if (encoder->type != INTEL_OUTPUT_EDP)
 397                         continue;
 398
 399                 tmp = enc_to_intel_dp(&encoder->base);
 400
 401                 if (tmp->pps_pipe != INVALID_PIPE)
 402                         pipes &= ~(1 << tmp->pps_pipe);
 403         }
 404
 405         /*
 406          * Didn't find one. This should not happen since there
 407          * are two power sequencers and up to two eDP ports.
 408          */
 409         if (WARN_ON(pipes == 0))
 410                 pipe = PIPE_A;
 411         else
 412                 pipe = ffs(pipes) - 1;
 413
 414         vlv_steal_power_sequencer(dev, pipe);
 415         intel_dp->pps_pipe = pipe;
 416
 417         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 418                       pipe_name(intel_dp->pps_pipe),
 419                       port_name(intel_dig_port->port));
 420
 421         /* init power sequencer on this pipe and port */
 422         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 423         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 424
 425         /*
 426          * Even vdd force doesn't work until we've made
 427          * the power sequencer lock in on the port.
 428          */
 429         vlv_power_sequencer_kick(intel_dp);
 430
 431         return intel_dp->pps_pipe;
 432 }
 433
 434 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 435                                enum pipe pipe);
 436
 437 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 438                                enum pipe pipe)
 439 {
 440         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 441 }
 442
 443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 444                                 enum pipe pipe)
 445 {
 446         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 447 }
 448
 449 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 450                          enum pipe pipe)
 451 {
 452         return true;
 453 }
 454
 455 static enum pipe
 456 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 457                      enum port port,
 458                      vlv_pipe_check pipe_check)
 459 {
 460         enum pipe pipe;
 461
 462         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 463                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 464                         PANEL_PORT_SELECT_MASK;
 465
 466                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 467                         continue;
 468
 469                 if (!pipe_check(dev_priv, pipe))
 470                         continue;
 471
 472                 return pipe;
 473         }
 474
 475         return INVALID_PIPE;
 476 }
 477
 478 static void
 479 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 480 {
 481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 482         struct drm_device *dev = intel_dig_port->base.base.dev;
 483         struct drm_i915_private *dev_priv = dev->dev_private;
 484         enum port port = intel_dig_port->port;
 485
 486         lockdep_assert_held(&dev_priv->pps_mutex);
 487
 488         /* try to find a pipe with this port selected */
 489         /* first pick one where the panel is on */
 490         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 491                                                   vlv_pipe_has_pp_on);
 492         /* didn't find one? pick one where vdd is on */
 493         if (intel_dp->pps_pipe == INVALID_PIPE)
 494                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 495                                                           vlv_pipe_has_vdd_on);
 496         /* didn't find one? pick one with just the correct port */
 497         if (intel_dp->pps_pipe == INVALID_PIPE)
 498                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 499                                                           vlv_pipe_any);
 500
 501         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 502         if (intel_dp->pps_pipe == INVALID_PIPE) {
 503                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 504                               port_name(port));
 505                 return;
 506         }
 507
 508         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 509                       port_name(port), pipe_name(intel_dp->pps_pipe));
 510
 511         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 512         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 513 }
 514
 515 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 516 {
 517         struct drm_device *dev = dev_priv->dev;
 518         struct intel_encoder *encoder;
 519
 520         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 521                 return;
 522
 523         /*
 524          * We can't grab pps_mutex here due to deadlock with power_domain
 525          * mutex when power_domain functions are called while holding pps_mutex.
 526          * That also means that in order to use pps_pipe the code needs to
 527          * hold both a power domain reference and pps_mutex, and the power domain
 528          * reference get/put must be done while _not_ holding pps_mutex.
 529          * pps_{lock,unlock}() do these steps in the correct order, so one
 530          * should use them always.
 531          */
 532
 533         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 534                 struct intel_dp *intel_dp;
 535
 536                 if (encoder->type != INTEL_OUTPUT_EDP)
 537                         continue;
 538
 539                 intel_dp = enc_to_intel_dp(&encoder->base);
 540                 intel_dp->pps_pipe = INVALID_PIPE;
 541         }
 542 }
 543
 544 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 545 {
 546         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 547
 548         if (IS_BROXTON(dev))
 549                 return BXT_PP_CONTROL(0);
 550         else if (HAS_PCH_SPLIT(dev))
 551                 return PCH_PP_CONTROL;
 552         else
 553                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 554 }
 555
 556 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 557 {
 558         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 559
 560         if (IS_BROXTON(dev))
 561                 return BXT_PP_STATUS(0);
 562         else if (HAS_PCH_SPLIT(dev))
 563                 return PCH_PP_STATUS;
 564         else
 565                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 566 }
 567
 568 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 569    This function only applicable when panel PM state is not to be tracked */
 570 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 571                               void *unused)
 572 {
 573         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 574                                                  edp_notifier);
 575         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 576         struct drm_i915_private *dev_priv = dev->dev_private;
 577         u32 pp_div;
 578         u32 pp_ctrl_reg, pp_div_reg;
 579
 580         if (!is_edp(intel_dp) || code != SYS_RESTART)
 581                 return 0;
 582
 583         pps_lock(intel_dp);
 584
 585         if (IS_VALLEYVIEW(dev)) {
 586                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 587
 588                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 589                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 590                 pp_div = I915_READ(pp_div_reg);
 591                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 592
 593                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 594                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 595                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 596                 msleep(intel_dp->panel_power_cycle_delay);
 597         }
 598
 599         pps_unlock(intel_dp);
 600
 601         return 0;
 602 }
 603
 604 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 605 {
 606         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608
 609         lockdep_assert_held(&dev_priv->pps_mutex);
 610
 611         if (IS_VALLEYVIEW(dev) &&
 612             intel_dp->pps_pipe == INVALID_PIPE)
 613                 return false;
 614
 615         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 616 }
 617
 618 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 619 {
 620         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622
 623         lockdep_assert_held(&dev_priv->pps_mutex);
 624
 625         if (IS_VALLEYVIEW(dev) &&
 626             intel_dp->pps_pipe == INVALID_PIPE)
 627                 return false;
 628
 629         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 630 }
 631
 632 static void
 633 intel_dp_check_edp(struct intel_dp *intel_dp)
 634 {
 635         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 636         struct drm_i915_private *dev_priv = dev->dev_private;
 637
 638         if (!is_edp(intel_dp))
 639                 return;
 640
 641         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 642                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 643                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 644                               I915_READ(_pp_stat_reg(intel_dp)),
 645                               I915_READ(_pp_ctrl_reg(intel_dp)));
 646         }
 647 }
 648
 649 static uint32_t
 650 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 651 {
 652         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 653         struct drm_device *dev = intel_dig_port->base.base.dev;
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 656         uint32_t status;
 657         bool done;
 658
 659 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 660         if (has_aux_irq)
 661                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 662                                           msecs_to_jiffies_timeout(10));
 663         else
 664                 done = wait_for_atomic(C, 10) == 0;
 665         if (!done)
 666                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 667                           has_aux_irq);
 668 #undef C
 669
 670         return status;
 671 }
 672
 673 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 674 {
 675         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 676         struct drm_device *dev = intel_dig_port->base.base.dev;
 677
 678         /*
 679          * The clock divider is based off the hrawclk, and would like to run at
 680          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 681          */
 682         return index ? 0 : intel_hrawclk(dev) / 2;
 683 }
 684
 685 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 686 {
 687         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 688         struct drm_device *dev = intel_dig_port->base.base.dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690
 691         if (index)
 692                 return 0;
 693
 694         if (intel_dig_port->port == PORT_A) {
 695                 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
 696
 697         } else {
 698                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 699         }
 700 }
 701
 702 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 703 {
 704         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 705         struct drm_device *dev = intel_dig_port->base.base.dev;
 706         struct drm_i915_private *dev_priv = dev->dev_private;
 707
 708         if (intel_dig_port->port == PORT_A) {
 709                 if (index)
 710                         return 0;
 711                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 712         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 713                 /* Workaround for non-ULT HSW */
 714                 switch (index) {
 715                 case 0: return 63;
 716                 case 1: return 72;
 717                 default: return 0;
 718                 }
 719         } else  {
 720                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 721         }
 722 }
 723
 724 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 725 {
 726         return index ? 0 : 100;
 727 }
 728
 729 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 730 {
 731         /*
 732          * SKL doesn't need us to program the AUX clock divider (Hardware will
 733          * derive the clock from CDCLK automatically). We still implement the
 734          * get_aux_clock_divider vfunc to plug-in into the existing code.
 735          */
 736         return index ? 0 : 1;
 737 }
 738
 739 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 740                                       bool has_aux_irq,
 741                                       int send_bytes,
 742                                       uint32_t aux_clock_divider)
 743 {
 744         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 745         struct drm_device *dev = intel_dig_port->base.base.dev;
 746         uint32_t precharge, timeout;
 747
 748         if (IS_GEN6(dev))
 749                 precharge = 3;
 750         else
 751                 precharge = 5;
 752
 753         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 754                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 755         else
 756                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 757
 758         return DP_AUX_CH_CTL_SEND_BUSY |
 759                DP_AUX_CH_CTL_DONE |
 760                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 761                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 762                timeout |
 763                DP_AUX_CH_CTL_RECEIVE_ERROR |
 764                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 765                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 766                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 767 }
 768
 769 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 770                                       bool has_aux_irq,
 771                                       int send_bytes,
 772                                       uint32_t unused)
 773 {
 774         return DP_AUX_CH_CTL_SEND_BUSY |
 775                DP_AUX_CH_CTL_DONE |
 776                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 777                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 778                DP_AUX_CH_CTL_TIME_OUT_1600us |
 779                DP_AUX_CH_CTL_RECEIVE_ERROR |
 780                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 781                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 782 }
 783
 784 static int
 785 intel_dp_aux_ch(struct intel_dp *intel_dp,
 786                 const uint8_t *send, int send_bytes,
 787                 uint8_t *recv, int recv_size)
 788 {
 789         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 790         struct drm_device *dev = intel_dig_port->base.base.dev;
 791         struct drm_i915_private *dev_priv = dev->dev_private;
 792         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 793         uint32_t ch_data = ch_ctl + 4;
 794         uint32_t aux_clock_divider;
 795         int i, ret, recv_bytes;
 796         uint32_t status;
 797         int try, clock = 0;
 798         bool has_aux_irq = HAS_AUX_IRQ(dev);
 799         bool vdd;
 800
 801         pps_lock(intel_dp);
 802
 803         /*
 804          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 805          * In such cases we want to leave VDD enabled and it's up to upper layers
 806          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 807          * ourselves.
 808          */
 809         vdd = edp_panel_vdd_on(intel_dp);
 810
 811         /* dp aux is extremely sensitive to irq latency, hence request the
 812          * lowest possible wakeup latency and so prevent the cpu from going into
 813          * deep sleep states.
 814          */
 815         pm_qos_update_request(&dev_priv->pm_qos, 0);
 816
 817         intel_dp_check_edp(intel_dp);
 818
 819         intel_aux_display_runtime_get(dev_priv);
 820
 821         /* Try to wait for any previous AUX channel activity */
 822         for (try = 0; try < 3; try++) {
 823                 status = I915_READ_NOTRACE(ch_ctl);
 824                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 825                         break;
 826                 msleep(1);
 827         }
 828
 829         if (try == 3) {
 830                 static u32 last_status = -1;
 831                 const u32 status = I915_READ(ch_ctl);
 832
 833                 if (status != last_status) {
 834                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 835                              status);
 836                         last_status = status;
 837                 }
 838
 839                 ret = -EBUSY;
 840                 goto out;
 841         }
 842
 843         /* Only 5 data registers! */
 844         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 845                 ret = -E2BIG;
 846                 goto out;
 847         }
 848
 849         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 850                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 851                                                           has_aux_irq,
 852                                                           send_bytes,
 853                                                           aux_clock_divider);
 854
 855                 /* Must try at least 3 times according to DP spec */
 856                 for (try = 0; try < 5; try++) {
 857                         /* Load the send data into the aux channel data registers */
 858                         for (i = 0; i < send_bytes; i += 4)
 859                                 I915_WRITE(ch_data + i,
 860                                            intel_dp_pack_aux(send + i,
 861                                                              send_bytes - i));
 862
 863                         /* Send the command and wait for it to complete */
 864                         I915_WRITE(ch_ctl, send_ctl);
 865
 866                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 867
 868                         /* Clear done status and any errors */
 869                         I915_WRITE(ch_ctl,
 870                                    status |
 871                                    DP_AUX_CH_CTL_DONE |
 872                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 873                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 874
 875                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 876                                 continue;
 877
 878                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 879                          *   400us delay required for errors and timeouts
 880                          *   Timeout errors from the HW already meet this
 881                          *   requirement so skip to next iteration
 882                          */
 883                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 884                                 usleep_range(400, 500);
 885                                 continue;
 886                         }
 887                         if (status & DP_AUX_CH_CTL_DONE)
 888                                 goto done;
 889                 }
 890         }
 891
 892         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 893                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 894                 ret = -EBUSY;
 895                 goto out;
 896         }
 897
 898 done:
 899         /* Check for timeout or receive error.
 900          * Timeouts occur when the sink is not connected
 901          */
 902         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 903                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 904                 ret = -EIO;
 905                 goto out;
 906         }
 907
 908         /* Timeouts occur when the device isn't connected, so they're
 909          * "normal" -- don't fill the kernel log with these */
 910         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 911                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 912                 ret = -ETIMEDOUT;
 913                 goto out;
 914         }
 915
 916         /* Unload any bytes sent back from the other side */
 917         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 918                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 919         if (recv_bytes > recv_size)
 920                 recv_bytes = recv_size;
 921
 922         for (i = 0; i < recv_bytes; i += 4)
 923                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 924                                     recv + i, recv_bytes - i);
 925
 926         ret = recv_bytes;
 927 out:
 928         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 929         intel_aux_display_runtime_put(dev_priv);
 930
 931         if (vdd)
 932                 edp_panel_vdd_off(intel_dp, false);
 933
 934         pps_unlock(intel_dp);
 935
 936         return ret;
 937 }
 938
 939 #define BARE_ADDRESS_SIZE       3
 940 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 941 static ssize_t
 942 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 943 {
 944         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 945         uint8_t txbuf[20], rxbuf[20];
 946         size_t txsize, rxsize;
 947         int ret;
 948
 949         txbuf[0] = (msg->request << 4) |
 950                 ((msg->address >> 16) & 0xf);
 951         txbuf[1] = (msg->address >> 8) & 0xff;
 952         txbuf[2] = msg->address & 0xff;
 953         txbuf[3] = msg->size - 1;
 954
 955         switch (msg->request & ~DP_AUX_I2C_MOT) {
 956         case DP_AUX_NATIVE_WRITE:
 957         case DP_AUX_I2C_WRITE:
 958         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 959                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 960                 rxsize = 2; /* 0 or 1 data bytes */
 961
 962                 if (WARN_ON(txsize > 20))
 963                         return -E2BIG;
 964
 965                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 966
 967                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 968                 if (ret > 0) {
 969                         msg->reply = rxbuf[0] >> 4;
 970
 971                         if (ret > 1) {
 972                                 /* Number of bytes written in a short write. */
 973                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 974                         } else {
 975                                 /* Return payload size. */
 976                                 ret = msg->size;
 977                         }
 978                 }
 979                 break;
 980
 981         case DP_AUX_NATIVE_READ:
 982         case DP_AUX_I2C_READ:
 983                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 984                 rxsize = msg->size + 1;
 985
 986                 if (WARN_ON(rxsize > 20))
 987                         return -E2BIG;
 988
 989                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 990                 if (ret > 0) {
 991                         msg->reply = rxbuf[0] >> 4;
 992                         /*
 993                          * Assume happy day, and copy the data. The caller is
 994                          * expected to check msg->reply before touching it.
 995                          *
 996                          * Return payload size.
 997                          */
 998                         ret--;
 999                         memcpy(msg->buffer, rxbuf + 1, ret);
1000                 }
1001                 break;
1002
1003         default:
1004                 ret = -EINVAL;
1005                 break;
1006         }
1007
1008         return ret;
1009 }
1010
1011 static void
1012 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1013 {
1014         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1015         struct drm_i915_private *dev_priv = dev->dev_private;
1016         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1017         enum port port = intel_dig_port->port;
1018         struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1019         const char *name = NULL;
1020         uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1021         int ret;
1022
1023         /* On SKL we don't have Aux for port E so we rely on VBT to set
1024          * a proper alternate aux channel.
1025          */
1026         if (IS_SKYLAKE(dev) && port == PORT_E) {
1027                 switch (info->alternate_aux_channel) {
1028                 case DP_AUX_B:
1029                         porte_aux_ctl_reg = DPB_AUX_CH_CTL;
1030                         break;
1031                 case DP_AUX_C:
1032                         porte_aux_ctl_reg = DPC_AUX_CH_CTL;
1033                         break;
1034                 case DP_AUX_D:
1035                         porte_aux_ctl_reg = DPD_AUX_CH_CTL;
1036                         break;
1037                 case DP_AUX_A:
1038                 default:
1039                         porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1040                 }
1041         }
1042
1043         switch (port) {
1044         case PORT_A:
1045                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1046                 name = "DPDDC-A";
1047                 break;
1048         case PORT_B:
1049                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1050                 name = "DPDDC-B";
1051                 break;
1052         case PORT_C:
1053                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1054                 name = "DPDDC-C";
1055                 break;
1056         case PORT_D:
1057                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1058                 name = "DPDDC-D";
1059                 break;
1060         case PORT_E:
1061                 intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
1062                 name = "DPDDC-E";
1063                 break;
1064         default:
1065                 BUG();
1066         }
1067
1068         /*
1069          * The AUX_CTL register is usually DP_CTL + 0x10.
1070          *
1071          * On Haswell and Broadwell though:
1072          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1073          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1074          *
1075          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1076          */
1077         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
1078                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1079
1080         intel_dp->aux.name = name;
1081         intel_dp->aux.dev = dev->dev;
1082         intel_dp->aux.transfer = intel_dp_aux_transfer;
1083
1084         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1085                       connector->base.kdev->kobj.name);
1086
1087         ret = drm_dp_aux_register(&intel_dp->aux);
1088         if (ret < 0) {
1089                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1090                           name, ret);
1091                 return;
1092         }
1093
1094         ret = sysfs_create_link(&connector->base.kdev->kobj,
1095                                 &intel_dp->aux.ddc.dev.kobj,
1096                                 intel_dp->aux.ddc.dev.kobj.name);
1097         if (ret < 0) {
1098                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1099                 drm_dp_aux_unregister(&intel_dp->aux);
1100         }
1101 }
1102
1103 static void
1104 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1105 {
1106         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1107
1108         if (!intel_connector->mst_port)
1109                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1110                                   intel_dp->aux.ddc.dev.kobj.name);
1111         intel_connector_unregister(intel_connector);
1112 }
1113
1114 static void
1115 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1116 {
1117         u32 ctrl1;
1118
1119         memset(&pipe_config->dpll_hw_state, 0,
1120                sizeof(pipe_config->dpll_hw_state));
1121
1122         pipe_config->ddi_pll_sel = SKL_DPLL0;
1123         pipe_config->dpll_hw_state.cfgcr1 = 0;
1124         pipe_config->dpll_hw_state.cfgcr2 = 0;
1125
1126         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1127         switch (pipe_config->port_clock / 2) {
1128         case 81000:
1129                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1130                                               SKL_DPLL0);
1131                 break;
1132         case 135000:
1133                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1134                                               SKL_DPLL0);
1135                 break;
1136         case 270000:
1137                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1138                                               SKL_DPLL0);
1139                 break;
1140         case 162000:
1141                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1142                                               SKL_DPLL0);
1143                 break;
1144         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1145         results in CDCLK change. Need to handle the change of CDCLK by
1146         disabling pipes and re-enabling them */
1147         case 108000:
1148                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1149                                               SKL_DPLL0);
1150                 break;
1151         case 216000:
1152                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1153                                               SKL_DPLL0);
1154                 break;
1155
1156         }
1157         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1158 }
1159
1160 void
1161 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1162 {
1163         memset(&pipe_config->dpll_hw_state, 0,
1164                sizeof(pipe_config->dpll_hw_state));
1165
1166         switch (pipe_config->port_clock / 2) {
1167         case 81000:
1168                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1169                 break;
1170         case 135000:
1171                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1172                 break;
1173         case 270000:
1174                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1175                 break;
1176         }
1177 }
1178
1179 static int
1180 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1181 {
1182         if (intel_dp->num_sink_rates) {
1183                 *sink_rates = intel_dp->sink_rates;
1184                 return intel_dp->num_sink_rates;
1185         }
1186
1187         *sink_rates = default_rates;
1188
1189         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1190 }
1191
1192 static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
1193 {
1194         /* WaDisableHBR2:skl */
1195         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1196                 return false;
1197
1198         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1199             (INTEL_INFO(dev)->gen >= 9))
1200                 return true;
1201         else
1202                 return false;
1203 }
1204
1205 static int
1206 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1207 {
1208         int size;
1209
1210         if (IS_BROXTON(dev)) {
1211                 *source_rates = bxt_rates;
1212                 size = ARRAY_SIZE(bxt_rates);
1213         } else if (IS_SKYLAKE(dev)) {
1214                 *source_rates = skl_rates;
1215                 size = ARRAY_SIZE(skl_rates);
1216         } else {
1217                 *source_rates = default_rates;
1218                 size = ARRAY_SIZE(default_rates);
1219         }
1220
1221         /* This depends on the fact that 5.4 is last value in the array */
1222         if (!intel_dp_source_supports_hbr2(dev))
1223                 size--;
1224
1225         return size;
1226 }
1227
1228 static void
1229 intel_dp_set_clock(struct intel_encoder *encoder,
1230                    struct intel_crtc_state *pipe_config)
1231 {
1232         struct drm_device *dev = encoder->base.dev;
1233         const struct dp_link_dpll *divisor = NULL;
1234         int i, count = 0;
1235
1236         if (IS_G4X(dev)) {
1237                 divisor = gen4_dpll;
1238                 count = ARRAY_SIZE(gen4_dpll);
1239         } else if (HAS_PCH_SPLIT(dev)) {
1240                 divisor = pch_dpll;
1241                 count = ARRAY_SIZE(pch_dpll);
1242         } else if (IS_CHERRYVIEW(dev)) {
1243                 divisor = chv_dpll;
1244                 count = ARRAY_SIZE(chv_dpll);
1245         } else if (IS_VALLEYVIEW(dev)) {
1246                 divisor = vlv_dpll;
1247                 count = ARRAY_SIZE(vlv_dpll);
1248         }
1249
1250         if (divisor && count) {
1251                 for (i = 0; i < count; i++) {
1252                         if (pipe_config->port_clock == divisor[i].clock) {
1253                                 pipe_config->dpll = divisor[i].dpll;
1254                                 pipe_config->clock_set = true;
1255                                 break;
1256                         }
1257                 }
1258         }
1259 }
1260
1261 static int intersect_rates(const int *source_rates, int source_len,
1262                            const int *sink_rates, int sink_len,
1263                            int *common_rates)
1264 {
1265         int i = 0, j = 0, k = 0;
1266
1267         while (i < source_len && j < sink_len) {
1268                 if (source_rates[i] == sink_rates[j]) {
1269                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1270                                 return k;
1271                         common_rates[k] = source_rates[i];
1272                         ++k;
1273                         ++i;
1274                         ++j;
1275                 } else if (source_rates[i] < sink_rates[j]) {
1276                         ++i;
1277                 } else {
1278                         ++j;
1279                 }
1280         }
1281         return k;
1282 }
1283
1284 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1285                                  int *common_rates)
1286 {
1287         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1288         const int *source_rates, *sink_rates;
1289         int source_len, sink_len;
1290
1291         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1292         source_len = intel_dp_source_rates(dev, &source_rates);
1293
1294         return intersect_rates(source_rates, source_len,
1295                                sink_rates, sink_len,
1296                                common_rates);
1297 }
1298
1299 static void snprintf_int_array(char *str, size_t len,
1300                                const int *array, int nelem)
1301 {
1302         int i;
1303
1304         str[0] = '\0';
1305
1306         for (i = 0; i < nelem; i++) {
1307                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1308                 if (r >= len)
1309                         return;
1310                 str += r;
1311                 len -= r;
1312         }
1313 }
1314
1315 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1316 {
1317         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1318         const int *source_rates, *sink_rates;
1319         int source_len, sink_len, common_len;
1320         int common_rates[DP_MAX_SUPPORTED_RATES];
1321         char str[128]; /* FIXME: too big for stack? */
1322
1323         if ((drm_debug & DRM_UT_KMS) == 0)
1324                 return;
1325
1326         source_len = intel_dp_source_rates(dev, &source_rates);
1327         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1328         DRM_DEBUG_KMS("source rates: %s\n", str);
1329
1330         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1331         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1332         DRM_DEBUG_KMS("sink rates: %s\n", str);
1333
1334         common_len = intel_dp_common_rates(intel_dp, common_rates);
1335         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1336         DRM_DEBUG_KMS("common rates: %s\n", str);
1337 }
1338
1339 static int rate_to_index(int find, const int *rates)
1340 {
1341         int i = 0;
1342
1343         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1344                 if (find == rates[i])
1345                         break;
1346
1347         return i;
1348 }
1349
1350 int
1351 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1352 {
1353         int rates[DP_MAX_SUPPORTED_RATES] = {};
1354         int len;
1355
1356         len = intel_dp_common_rates(intel_dp, rates);
1357         if (WARN_ON(len <= 0))
1358                 return 162000;
1359
1360         return rates[rate_to_index(0, rates) - 1];
1361 }
1362
1363 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1364 {
1365         return rate_to_index(rate, intel_dp->sink_rates);
1366 }
1367
1368 static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1369                                   uint8_t *link_bw, uint8_t *rate_select)
1370 {
1371         if (intel_dp->num_sink_rates) {
1372                 *link_bw = 0;
1373                 *rate_select =
1374                         intel_dp_rate_select(intel_dp, port_clock);
1375         } else {
1376                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1377                 *rate_select = 0;
1378         }
1379 }
1380
1381 bool
1382 intel_dp_compute_config(struct intel_encoder *encoder,
1383                         struct intel_crtc_state *pipe_config)
1384 {
1385         struct drm_device *dev = encoder->base.dev;
1386         struct drm_i915_private *dev_priv = dev->dev_private;
1387         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1388         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1389         enum port port = dp_to_dig_port(intel_dp)->port;
1390         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1391         struct intel_connector *intel_connector = intel_dp->attached_connector;
1392         int lane_count, clock;
1393         int min_lane_count = 1;
1394         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1395         /* Conveniently, the link BW constants become indices with a shift...*/
1396         int min_clock = 0;
1397         int max_clock;
1398         int bpp, mode_rate;
1399         int link_avail, link_clock;
1400         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1401         int common_len;
1402         uint8_t link_bw, rate_select;
1403
1404         common_len = intel_dp_common_rates(intel_dp, common_rates);
1405
1406         /* No common link rates between source and sink */
1407         WARN_ON(common_len <= 0);
1408
1409         max_clock = common_len - 1;
1410
1411         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1412                 pipe_config->has_pch_encoder = true;
1413
1414         pipe_config->has_dp_encoder = true;
1415         pipe_config->has_drrs = false;
1416         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1417
1418         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1419                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1420                                        adjusted_mode);
1421
1422                 if (INTEL_INFO(dev)->gen >= 9) {
1423                         int ret;
1424                         ret = skl_update_scaler_crtc(pipe_config);
1425                         if (ret)
1426                                 return ret;
1427                 }
1428
1429                 if (!HAS_PCH_SPLIT(dev))
1430                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1431                                                  intel_connector->panel.fitting_mode);
1432                 else
1433                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1434                                                 intel_connector->panel.fitting_mode);
1435         }
1436
1437         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1438                 return false;
1439
1440         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1441                       "max bw %d pixel clock %iKHz\n",
1442                       max_lane_count, common_rates[max_clock],
1443                       adjusted_mode->crtc_clock);
1444
1445         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1446          * bpc in between. */
1447         bpp = pipe_config->pipe_bpp;
1448         if (is_edp(intel_dp)) {
1449
1450                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1451                 if (intel_connector->base.display_info.bpc == 0 &&
1452                         (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1453                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1454                                       dev_priv->vbt.edp_bpp);
1455                         bpp = dev_priv->vbt.edp_bpp;
1456                 }
1457
1458                 /*
1459                  * Use the maximum clock and number of lanes the eDP panel
1460                  * advertizes being capable of. The panels are generally
1461                  * designed to support only a single clock and lane
1462                  * configuration, and typically these values correspond to the
1463                  * native resolution of the panel.
1464                  */
1465                 min_lane_count = max_lane_count;
1466                 min_clock = max_clock;
1467         }
1468
1469         for (; bpp >= 6*3; bpp -= 2*3) {
1470                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1471                                                    bpp);
1472
1473                 for (clock = min_clock; clock <= max_clock; clock++) {
1474                         for (lane_count = min_lane_count;
1475                                 lane_count <= max_lane_count;
1476                                 lane_count <<= 1) {
1477
1478                                 link_clock = common_rates[clock];
1479                                 link_avail = intel_dp_max_data_rate(link_clock,
1480                                                                     lane_count);
1481
1482                                 if (mode_rate <= link_avail) {
1483                                         goto found;
1484                                 }
1485                         }
1486                 }
1487         }
1488
1489         return false;
1490
1491 found:
1492         if (intel_dp->color_range_auto) {
1493                 /*
1494                  * See:
1495                  * CEA-861-E - 5.1 Default Encoding Parameters
1496                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1497                  */
1498                 pipe_config->limited_color_range =
1499                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1500         } else {
1501                 pipe_config->limited_color_range =
1502                         intel_dp->limited_color_range;
1503         }
1504
1505         pipe_config->lane_count = lane_count;
1506
1507         pipe_config->pipe_bpp = bpp;
1508         pipe_config->port_clock = common_rates[clock];
1509
1510         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1511                               &link_bw, &rate_select);
1512
1513         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1514                       link_bw, rate_select, pipe_config->lane_count,
1515                       pipe_config->port_clock, bpp);
1516         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1517                       mode_rate, link_avail);
1518
1519         intel_link_compute_m_n(bpp, lane_count,
1520                                adjusted_mode->crtc_clock,
1521                                pipe_config->port_clock,
1522                                &pipe_config->dp_m_n);
1523
1524         if (intel_connector->panel.downclock_mode != NULL &&
1525                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1526                         pipe_config->has_drrs = true;
1527                         intel_link_compute_m_n(bpp, lane_count,
1528                                 intel_connector->panel.downclock_mode->clock,
1529                                 pipe_config->port_clock,
1530                                 &pipe_config->dp_m2_n2);
1531         }
1532
1533         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1534                 skl_edp_set_pll_config(pipe_config);
1535         else if (IS_BROXTON(dev))
1536                 /* handled in ddi */;
1537         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1538                 hsw_dp_set_ddi_pll_sel(pipe_config);
1539         else
1540                 intel_dp_set_clock(encoder, pipe_config);
1541
1542         return true;
1543 }
1544
1545 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1546 {
1547         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1548         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         u32 dpa_ctl;
1552
1553         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1554                       crtc->config->port_clock);
1555         dpa_ctl = I915_READ(DP_A);
1556         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1557
1558         if (crtc->config->port_clock == 162000) {
1559                 /* For a long time we've carried around a ILK-DevA w/a for the
1560                  * 160MHz clock. If we're really unlucky, it's still required.
1561                  */
1562                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1563                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1564                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1565         } else {
1566                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1567                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1568         }
1569
1570         I915_WRITE(DP_A, dpa_ctl);
1571
1572         POSTING_READ(DP_A);
1573         udelay(500);
1574 }
1575
1576 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1577                               const struct intel_crtc_state *pipe_config)
1578 {
1579         intel_dp->link_rate = pipe_config->port_clock;
1580         intel_dp->lane_count = pipe_config->lane_count;
1581 }
1582
1583 static void intel_dp_prepare(struct intel_encoder *encoder)
1584 {
1585         struct drm_device *dev = encoder->base.dev;
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1588         enum port port = dp_to_dig_port(intel_dp)->port;
1589         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1590         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1591
1592         intel_dp_set_link_params(intel_dp, crtc->config);
1593
1594         /*
1595          * There are four kinds of DP registers:
1596          *
1597          *      IBX PCH
1598          *      SNB CPU
1599          *      IVB CPU
1600          *      CPT PCH
1601          *
1602          * IBX PCH and CPU are the same for almost everything,
1603          * except that the CPU DP PLL is configured in this
1604          * register
1605          *
1606          * CPT PCH is quite different, having many bits moved
1607          * to the TRANS_DP_CTL register instead. That
1608          * configuration happens (oddly) in ironlake_pch_enable
1609          */
1610
1611         /* Preserve the BIOS-computed detected bit. This is
1612          * supposed to be read-only.
1613          */
1614         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1615
1616         /* Handle DP bits in common between all three register formats */
1617         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1618         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1619
1620         if (crtc->config->has_audio)
1621                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1622
1623         /* Split out the IBX/CPU vs CPT settings */
1624
1625         if (IS_GEN7(dev) && port == PORT_A) {
1626                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1627                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1628                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1629                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1630                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1631
1632                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1633                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1634
1635                 intel_dp->DP |= crtc->pipe << 29;
1636         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1637                 u32 trans_dp;
1638
1639                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1640
1641                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1642                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1643                         trans_dp |= TRANS_DP_ENH_FRAMING;
1644                 else
1645                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1646                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1647         } else {
1648                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1649                     crtc->config->limited_color_range)
1650                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1651
1652                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1653                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1654                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1655                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1656                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1657
1658                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1659                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1660
1661                 if (IS_CHERRYVIEW(dev))
1662                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1663                 else if (crtc->pipe == PIPE_B)
1664                         intel_dp->DP |= DP_PIPEB_SELECT;
1665         }
1666 }
1667
1668 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1669 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1670
1671 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1672 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1673
1674 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1675 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1676
1677 static void wait_panel_status(struct intel_dp *intel_dp,
1678                                        u32 mask,
1679                                        u32 value)
1680 {
1681         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1682         struct drm_i915_private *dev_priv = dev->dev_private;
1683         u32 pp_stat_reg, pp_ctrl_reg;
1684
1685         lockdep_assert_held(&dev_priv->pps_mutex);
1686
1687         pp_stat_reg = _pp_stat_reg(intel_dp);
1688         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1689
1690         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1691                         mask, value,
1692                         I915_READ(pp_stat_reg),
1693                         I915_READ(pp_ctrl_reg));
1694
1695         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1696                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1697                                 I915_READ(pp_stat_reg),
1698                                 I915_READ(pp_ctrl_reg));
1699         }
1700
1701         DRM_DEBUG_KMS("Wait complete\n");
1702 }
1703
1704 static void wait_panel_on(struct intel_dp *intel_dp)
1705 {
1706         DRM_DEBUG_KMS("Wait for panel power on\n");
1707         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1708 }
1709
1710 static void wait_panel_off(struct intel_dp *intel_dp)
1711 {
1712         DRM_DEBUG_KMS("Wait for panel power off time\n");
1713         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1714 }
1715
1716 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1717 {
1718         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1719
1720         /* When we disable the VDD override bit last we have to do the manual
1721          * wait. */
1722         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1723                                        intel_dp->panel_power_cycle_delay);
1724
1725         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1726 }
1727
1728 static void wait_backlight_on(struct intel_dp *intel_dp)
1729 {
1730         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1731                                        intel_dp->backlight_on_delay);
1732 }
1733
1734 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1735 {
1736         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1737                                        intel_dp->backlight_off_delay);
1738 }
1739
1740 /* Read the current pp_control value, unlocking the register if it
1741  * is locked
1742  */
1743
1744 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1745 {
1746         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748         u32 control;
1749
1750         lockdep_assert_held(&dev_priv->pps_mutex);
1751
1752         control = I915_READ(_pp_ctrl_reg(intel_dp));
1753         if (!IS_BROXTON(dev)) {
1754                 control &= ~PANEL_UNLOCK_MASK;
1755                 control |= PANEL_UNLOCK_REGS;
1756         }
1757         return control;
1758 }
1759
1760 /*
1761  * Must be paired with edp_panel_vdd_off().
1762  * Must hold pps_mutex around the whole on/off sequence.
1763  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1764  */
1765 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1766 {
1767         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1769         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         enum intel_display_power_domain power_domain;
1772         u32 pp;
1773         u32 pp_stat_reg, pp_ctrl_reg;
1774         bool need_to_disable = !intel_dp->want_panel_vdd;
1775
1776         lockdep_assert_held(&dev_priv->pps_mutex);
1777
1778         if (!is_edp(intel_dp))
1779                 return false;
1780
1781         cancel_delayed_work(&intel_dp->panel_vdd_work);
1782         intel_dp->want_panel_vdd = true;
1783
1784         if (edp_have_panel_vdd(intel_dp))
1785                 return need_to_disable;
1786
1787         power_domain = intel_display_port_power_domain(intel_encoder);
1788         intel_display_power_get(dev_priv, power_domain);
1789
1790         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1791                       port_name(intel_dig_port->port));
1792
1793         if (!edp_have_panel_power(intel_dp))
1794                 wait_panel_power_cycle(intel_dp);
1795
1796         pp = ironlake_get_pp_control(intel_dp);
1797         pp |= EDP_FORCE_VDD;
1798
1799         pp_stat_reg = _pp_stat_reg(intel_dp);
1800         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1801
1802         I915_WRITE(pp_ctrl_reg, pp);
1803         POSTING_READ(pp_ctrl_reg);
1804         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1805                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1806         /*
1807          * If the panel wasn't on, delay before accessing aux channel
1808          */
1809         if (!edp_have_panel_power(intel_dp)) {
1810                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1811                               port_name(intel_dig_port->port));
1812                 msleep(intel_dp->panel_power_up_delay);
1813         }
1814
1815         return need_to_disable;
1816 }
1817
1818 /*
1819  * Must be paired with intel_edp_panel_vdd_off() or
1820  * intel_edp_panel_off().
1821  * Nested calls to these functions are not allowed since
1822  * we drop the lock. Caller must use some higher level
1823  * locking to prevent nested calls from other threads.
1824  */
1825 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1826 {
1827         bool vdd;
1828
1829         if (!is_edp(intel_dp))
1830                 return;
1831
1832         pps_lock(intel_dp);
1833         vdd = edp_panel_vdd_on(intel_dp);
1834         pps_unlock(intel_dp);
1835
1836         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1837              port_name(dp_to_dig_port(intel_dp)->port));
1838 }
1839
1840 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1841 {
1842         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843         struct drm_i915_private *dev_priv = dev->dev_private;
1844         struct intel_digital_port *intel_dig_port =
1845                 dp_to_dig_port(intel_dp);
1846         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1847         enum intel_display_power_domain power_domain;
1848         u32 pp;
1849         u32 pp_stat_reg, pp_ctrl_reg;
1850
1851         lockdep_assert_held(&dev_priv->pps_mutex);
1852
1853         WARN_ON(intel_dp->want_panel_vdd);
1854
1855         if (!edp_have_panel_vdd(intel_dp))
1856                 return;
1857
1858         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1859                       port_name(intel_dig_port->port));
1860
1861         pp = ironlake_get_pp_control(intel_dp);
1862         pp &= ~EDP_FORCE_VDD;
1863
1864         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1865         pp_stat_reg = _pp_stat_reg(intel_dp);
1866
1867         I915_WRITE(pp_ctrl_reg, pp);
1868         POSTING_READ(pp_ctrl_reg);
1869
1870         /* Make sure sequencer is idle before allowing subsequent activity */
1871         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1872         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1873
1874         if ((pp & POWER_TARGET_ON) == 0)
1875                 intel_dp->last_power_cycle = jiffies;
1876
1877         power_domain = intel_display_port_power_domain(intel_encoder);
1878         intel_display_power_put(dev_priv, power_domain);
1879 }
1880
1881 static void edp_panel_vdd_work(struct work_struct *__work)
1882 {
1883         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1884                                                  struct intel_dp, panel_vdd_work);
1885
1886         pps_lock(intel_dp);
1887         if (!intel_dp->want_panel_vdd)
1888                 edp_panel_vdd_off_sync(intel_dp);
1889         pps_unlock(intel_dp);
1890 }
1891
1892 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1893 {
1894         unsigned long delay;
1895
1896         /*
1897          * Queue the timer to fire a long time from now (relative to the power
1898          * down delay) to keep the panel power up across a sequence of
1899          * operations.
1900          */
1901         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1902         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1903 }
1904
1905 /*
1906  * Must be paired with edp_panel_vdd_on().
1907  * Must hold pps_mutex around the whole on/off sequence.
1908  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1909  */
1910 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1911 {
1912         struct drm_i915_private *dev_priv =
1913                 intel_dp_to_dev(intel_dp)->dev_private;
1914
1915         lockdep_assert_held(&dev_priv->pps_mutex);
1916
1917         if (!is_edp(intel_dp))
1918                 return;
1919
1920         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1921              port_name(dp_to_dig_port(intel_dp)->port));
1922
1923         intel_dp->want_panel_vdd = false;
1924
1925         if (sync)
1926                 edp_panel_vdd_off_sync(intel_dp);
1927         else
1928                 edp_panel_vdd_schedule_off(intel_dp);
1929 }
1930
1931 static void edp_panel_on(struct intel_dp *intel_dp)
1932 {
1933         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1934         struct drm_i915_private *dev_priv = dev->dev_private;
1935         u32 pp;
1936         u32 pp_ctrl_reg;
1937
1938         lockdep_assert_held(&dev_priv->pps_mutex);
1939
1940         if (!is_edp(intel_dp))
1941                 return;
1942
1943         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1944                       port_name(dp_to_dig_port(intel_dp)->port));
1945
1946         if (WARN(edp_have_panel_power(intel_dp),
1947                  "eDP port %c panel power already on\n",
1948                  port_name(dp_to_dig_port(intel_dp)->port)))
1949                 return;
1950
1951         wait_panel_power_cycle(intel_dp);
1952
1953         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1954         pp = ironlake_get_pp_control(intel_dp);
1955         if (IS_GEN5(dev)) {
1956                 /* ILK workaround: disable reset around power sequence */
1957                 pp &= ~PANEL_POWER_RESET;
1958                 I915_WRITE(pp_ctrl_reg, pp);
1959                 POSTING_READ(pp_ctrl_reg);
1960         }
1961
1962         pp |= POWER_TARGET_ON;
1963         if (!IS_GEN5(dev))
1964                 pp |= PANEL_POWER_RESET;
1965
1966         I915_WRITE(pp_ctrl_reg, pp);
1967         POSTING_READ(pp_ctrl_reg);
1968
1969         wait_panel_on(intel_dp);
1970         intel_dp->last_power_on = jiffies;
1971
1972         if (IS_GEN5(dev)) {
1973                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1974                 I915_WRITE(pp_ctrl_reg, pp);
1975                 POSTING_READ(pp_ctrl_reg);
1976         }
1977 }
1978
1979 void intel_edp_panel_on(struct intel_dp *intel_dp)
1980 {
1981         if (!is_edp(intel_dp))
1982                 return;
1983
1984         pps_lock(intel_dp);
1985         edp_panel_on(intel_dp);
1986         pps_unlock(intel_dp);
1987 }
1988
1989
1990 static void edp_panel_off(struct intel_dp *intel_dp)
1991 {
1992         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1993         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1994         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996         enum intel_display_power_domain power_domain;
1997         u32 pp;
1998         u32 pp_ctrl_reg;
1999
2000         lockdep_assert_held(&dev_priv->pps_mutex);
2001
2002         if (!is_edp(intel_dp))
2003                 return;
2004
2005         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2006                       port_name(dp_to_dig_port(intel_dp)->port));
2007
2008         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2009              port_name(dp_to_dig_port(intel_dp)->port));
2010
2011         pp = ironlake_get_pp_control(intel_dp);
2012         /* We need to switch off panel power _and_ force vdd, for otherwise some
2013          * panels get very unhappy and cease to work. */
2014         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2015                 EDP_BLC_ENABLE);
2016
2017         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2018
2019         intel_dp->want_panel_vdd = false;
2020
2021         I915_WRITE(pp_ctrl_reg, pp);
2022         POSTING_READ(pp_ctrl_reg);
2023
2024         intel_dp->last_power_cycle = jiffies;
2025         wait_panel_off(intel_dp);
2026
2027         /* We got a reference when we enabled the VDD. */
2028         power_domain = intel_display_port_power_domain(intel_encoder);
2029         intel_display_power_put(dev_priv, power_domain);
2030 }
2031
2032 void intel_edp_panel_off(struct intel_dp *intel_dp)
2033 {
2034         if (!is_edp(intel_dp))
2035                 return;
2036
2037         pps_lock(intel_dp);
2038         edp_panel_off(intel_dp);
2039         pps_unlock(intel_dp);
2040 }
2041
2042 /* Enable backlight in the panel power control. */
2043 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2044 {
2045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2046         struct drm_device *dev = intel_dig_port->base.base.dev;
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         u32 pp;
2049         u32 pp_ctrl_reg;
2050
2051         /*
2052          * If we enable the backlight right away following a panel power
2053          * on, we may see slight flicker as the panel syncs with the eDP
2054          * link.  So delay a bit to make sure the image is solid before
2055          * allowing it to appear.
2056          */
2057         wait_backlight_on(intel_dp);
2058
2059         pps_lock(intel_dp);
2060
2061         pp = ironlake_get_pp_control(intel_dp);
2062         pp |= EDP_BLC_ENABLE;
2063
2064         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2065
2066         I915_WRITE(pp_ctrl_reg, pp);
2067         POSTING_READ(pp_ctrl_reg);
2068
2069         pps_unlock(intel_dp);
2070 }
2071
2072 /* Enable backlight PWM and backlight PP control. */
2073 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2074 {
2075         if (!is_edp(intel_dp))
2076                 return;
2077
2078         DRM_DEBUG_KMS("\n");
2079
2080         intel_panel_enable_backlight(intel_dp->attached_connector);
2081         _intel_edp_backlight_on(intel_dp);
2082 }
2083
2084 /* Disable backlight in the panel power control. */
2085 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2086 {
2087         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089         u32 pp;
2090         u32 pp_ctrl_reg;
2091
2092         if (!is_edp(intel_dp))
2093                 return;
2094
2095         pps_lock(intel_dp);
2096
2097         pp = ironlake_get_pp_control(intel_dp);
2098         pp &= ~EDP_BLC_ENABLE;
2099
2100         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2101
2102         I915_WRITE(pp_ctrl_reg, pp);
2103         POSTING_READ(pp_ctrl_reg);
2104
2105         pps_unlock(intel_dp);
2106
2107         intel_dp->last_backlight_off = jiffies;
2108         edp_wait_backlight_off(intel_dp);
2109 }
2110
2111 /* Disable backlight PP control and backlight PWM. */
2112 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2113 {
2114         if (!is_edp(intel_dp))
2115                 return;
2116
2117         DRM_DEBUG_KMS("\n");
2118
2119         _intel_edp_backlight_off(intel_dp);
2120         intel_panel_disable_backlight(intel_dp->attached_connector);
2121 }
2122
2123 /*
2124  * Hook for controlling the panel power control backlight through the bl_power
2125  * sysfs attribute. Take care to handle multiple calls.
2126  */
2127 static void intel_edp_backlight_power(struct intel_connector *connector,
2128                                       bool enable)
2129 {
2130         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2131         bool is_enabled;
2132
2133         pps_lock(intel_dp);
2134         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2135         pps_unlock(intel_dp);
2136
2137         if (is_enabled == enable)
2138                 return;
2139
2140         DRM_DEBUG_KMS("panel power control backlight %s\n",
2141                       enable ? "enable" : "disable");
2142
2143         if (enable)
2144                 _intel_edp_backlight_on(intel_dp);
2145         else
2146                 _intel_edp_backlight_off(intel_dp);
2147 }
2148
2149 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2150 {
2151         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2152         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2153         struct drm_device *dev = crtc->dev;
2154         struct drm_i915_private *dev_priv = dev->dev_private;
2155         u32 dpa_ctl;
2156
2157         assert_pipe_disabled(dev_priv,
2158                              to_intel_crtc(crtc)->pipe);
2159
2160         DRM_DEBUG_KMS("\n");
2161         dpa_ctl = I915_READ(DP_A);
2162         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2163         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2164
2165         /* We don't adjust intel_dp->DP while tearing down the link, to
2166          * facilitate link retraining (e.g. after hotplug). Hence clear all
2167          * enable bits here to ensure that we don't enable too much. */
2168         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2169         intel_dp->DP |= DP_PLL_ENABLE;
2170         I915_WRITE(DP_A, intel_dp->DP);
2171         POSTING_READ(DP_A);
2172         udelay(200);
2173 }
2174
2175 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2176 {
2177         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2178         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2179         struct drm_device *dev = crtc->dev;
2180         struct drm_i915_private *dev_priv = dev->dev_private;
2181         u32 dpa_ctl;
2182
2183         assert_pipe_disabled(dev_priv,
2184                              to_intel_crtc(crtc)->pipe);
2185
2186         dpa_ctl = I915_READ(DP_A);
2187         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2188              "dp pll off, should be on\n");
2189         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2190
2191         /* We can't rely on the value tracked for the DP register in
2192          * intel_dp->DP because link_down must not change that (otherwise link
2193          * re-training will fail. */
2194         dpa_ctl &= ~DP_PLL_ENABLE;
2195         I915_WRITE(DP_A, dpa_ctl);
2196         POSTING_READ(DP_A);
2197         udelay(200);
2198 }
2199
2200 /* If the sink supports it, try to set the power state appropriately */
2201 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2202 {
2203         int ret, i;
2204
2205         /* Should have a valid DPCD by this point */
2206         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2207                 return;
2208
2209         if (mode != DRM_MODE_DPMS_ON) {
2210                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2211                                          DP_SET_POWER_D3);
2212         } else {
2213                 /*
2214                  * When turning on, we need to retry for 1ms to give the sink
2215                  * time to wake up.
2216                  */
2217                 for (i = 0; i < 3; i++) {
2218                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2219                                                  DP_SET_POWER_D0);
2220                         if (ret == 1)
2221                                 break;
2222                         msleep(1);
2223                 }
2224         }
2225
2226         if (ret != 1)
2227                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2228                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2229 }
2230
2231 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2232                                   enum pipe *pipe)
2233 {
2234         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2235         enum port port = dp_to_dig_port(intel_dp)->port;
2236         struct drm_device *dev = encoder->base.dev;
2237         struct drm_i915_private *dev_priv = dev->dev_private;
2238         enum intel_display_power_domain power_domain;
2239         u32 tmp;
2240
2241         power_domain = intel_display_port_power_domain(encoder);
2242         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2243                 return false;
2244
2245         tmp = I915_READ(intel_dp->output_reg);
2246
2247         if (!(tmp & DP_PORT_EN))
2248                 return false;
2249
2250         if (IS_GEN7(dev) && port == PORT_A) {
2251                 *pipe = PORT_TO_PIPE_CPT(tmp);
2252         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2253                 enum pipe p;
2254
2255                 for_each_pipe(dev_priv, p) {
2256                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2257                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2258                                 *pipe = p;
2259                                 return true;
2260                         }
2261                 }
2262
2263                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2264                               intel_dp->output_reg);
2265         } else if (IS_CHERRYVIEW(dev)) {
2266                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2267         } else {
2268                 *pipe = PORT_TO_PIPE(tmp);
2269         }
2270
2271         return true;
2272 }
2273
2274 static void intel_dp_get_config(struct intel_encoder *encoder,
2275                                 struct intel_crtc_state *pipe_config)
2276 {
2277         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2278         u32 tmp, flags = 0;
2279         struct drm_device *dev = encoder->base.dev;
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         enum port port = dp_to_dig_port(intel_dp)->port;
2282         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2283         int dotclock;
2284
2285         tmp = I915_READ(intel_dp->output_reg);
2286
2287         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2288
2289         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2290                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2291
2292                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2293                         flags |= DRM_MODE_FLAG_PHSYNC;
2294                 else
2295                         flags |= DRM_MODE_FLAG_NHSYNC;
2296
2297                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2298                         flags |= DRM_MODE_FLAG_PVSYNC;
2299                 else
2300                         flags |= DRM_MODE_FLAG_NVSYNC;
2301         } else {
2302                 if (tmp & DP_SYNC_HS_HIGH)
2303                         flags |= DRM_MODE_FLAG_PHSYNC;
2304                 else
2305                         flags |= DRM_MODE_FLAG_NHSYNC;
2306
2307                 if (tmp & DP_SYNC_VS_HIGH)
2308                         flags |= DRM_MODE_FLAG_PVSYNC;
2309                 else
2310                         flags |= DRM_MODE_FLAG_NVSYNC;
2311         }
2312
2313         pipe_config->base.adjusted_mode.flags |= flags;
2314
2315         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2316             tmp & DP_COLOR_RANGE_16_235)
2317                 pipe_config->limited_color_range = true;
2318
2319         pipe_config->has_dp_encoder = true;
2320
2321         pipe_config->lane_count =
2322                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2323
2324         intel_dp_get_m_n(crtc, pipe_config);
2325
2326         if (port == PORT_A) {
2327                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2328                         pipe_config->port_clock = 162000;
2329                 else
2330                         pipe_config->port_clock = 270000;
2331         }
2332
2333         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2334                                             &pipe_config->dp_m_n);
2335
2336         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2337                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2338
2339         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2340
2341         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2342             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2343                 /*
2344                  * This is a big fat ugly hack.
2345                  *
2346                  * Some machines in UEFI boot mode provide us a VBT that has 18
2347                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2348                  * unknown we fail to light up. Yet the same BIOS boots up with
2349                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2350                  * max, not what it tells us to use.
2351                  *
2352                  * Note: This will still be broken if the eDP panel is not lit
2353                  * up by the BIOS, and thus we can't get the mode at module
2354                  * load.
2355                  */
2356                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2357                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2358                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2359         }
2360 }
2361
2362 static void intel_disable_dp(struct intel_encoder *encoder)
2363 {
2364         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2365         struct drm_device *dev = encoder->base.dev;
2366         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2367
2368         if (crtc->config->has_audio)
2369                 intel_audio_codec_disable(encoder);
2370
2371         if (HAS_PSR(dev) && !HAS_DDI(dev))
2372                 intel_psr_disable(intel_dp);
2373
2374         /* Make sure the panel is off before trying to change the mode. But also
2375          * ensure that we have vdd while we switch off the panel. */
2376         intel_edp_panel_vdd_on(intel_dp);
2377         intel_edp_backlight_off(intel_dp);
2378         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2379         intel_edp_panel_off(intel_dp);
2380
2381         /* disable the port before the pipe on g4x */
2382         if (INTEL_INFO(dev)->gen < 5)
2383                 intel_dp_link_down(intel_dp);
2384 }
2385
2386 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2387 {
2388         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2389         enum port port = dp_to_dig_port(intel_dp)->port;
2390
2391         intel_dp_link_down(intel_dp);
2392         if (port == PORT_A)
2393                 ironlake_edp_pll_off(intel_dp);
2394 }
2395
2396 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2397 {
2398         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2399
2400         intel_dp_link_down(intel_dp);
2401 }
2402
2403 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2404                                      bool reset)
2405 {
2406         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2407         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2408         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2409         enum pipe pipe = crtc->pipe;
2410         uint32_t val;
2411
2412         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2413         if (reset)
2414                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2415         else
2416                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2417         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2418
2419         if (crtc->config->lane_count > 2) {
2420                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2421                 if (reset)
2422                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2423                 else
2424                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2425                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2426         }
2427
2428         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2429         val |= CHV_PCS_REQ_SOFTRESET_EN;
2430         if (reset)
2431                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2432         else
2433                 val |= DPIO_PCS_CLK_SOFT_RESET;
2434         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2435
2436         if (crtc->config->lane_count > 2) {
2437                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2438                 val |= CHV_PCS_REQ_SOFTRESET_EN;
2439                 if (reset)
2440                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
2441                 else
2442                         val |= DPIO_PCS_CLK_SOFT_RESET;
2443                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2444         }
2445 }
2446
2447 static void chv_post_disable_dp(struct intel_encoder *encoder)
2448 {
2449         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2450         struct drm_device *dev = encoder->base.dev;
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452
2453         intel_dp_link_down(intel_dp);
2454
2455         mutex_lock(&dev_priv->sb_lock);
2456
2457         /* Assert data lane reset */
2458         chv_data_lane_soft_reset(encoder, true);
2459
2460         mutex_unlock(&dev_priv->sb_lock);
2461 }
2462
2463 static void
2464 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2465                          uint32_t *DP,
2466                          uint8_t dp_train_pat)
2467 {
2468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2469         struct drm_device *dev = intel_dig_port->base.base.dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         enum port port = intel_dig_port->port;
2472
2473         if (HAS_DDI(dev)) {
2474                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2475
2476                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2477                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2478                 else
2479                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2480
2481                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2482                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2483                 case DP_TRAINING_PATTERN_DISABLE:
2484                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2485
2486                         break;
2487                 case DP_TRAINING_PATTERN_1:
2488                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2489                         break;
2490                 case DP_TRAINING_PATTERN_2:
2491                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2492                         break;
2493                 case DP_TRAINING_PATTERN_3:
2494                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2495                         break;
2496                 }
2497                 I915_WRITE(DP_TP_CTL(port), temp);
2498
2499         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2500                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2501                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2502
2503                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2504                 case DP_TRAINING_PATTERN_DISABLE:
2505                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2506                         break;
2507                 case DP_TRAINING_PATTERN_1:
2508                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2509                         break;
2510                 case DP_TRAINING_PATTERN_2:
2511                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2512                         break;
2513                 case DP_TRAINING_PATTERN_3:
2514                         DRM_ERROR("DP training pattern 3 not supported\n");
2515                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2516                         break;
2517                 }
2518
2519         } else {
2520                 if (IS_CHERRYVIEW(dev))
2521                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2522                 else
2523                         *DP &= ~DP_LINK_TRAIN_MASK;
2524
2525                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2526                 case DP_TRAINING_PATTERN_DISABLE:
2527                         *DP |= DP_LINK_TRAIN_OFF;
2528                         break;
2529                 case DP_TRAINING_PATTERN_1:
2530                         *DP |= DP_LINK_TRAIN_PAT_1;
2531                         break;
2532                 case DP_TRAINING_PATTERN_2:
2533                         *DP |= DP_LINK_TRAIN_PAT_2;
2534                         break;
2535                 case DP_TRAINING_PATTERN_3:
2536                         if (IS_CHERRYVIEW(dev)) {
2537                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2538                         } else {
2539                                 DRM_ERROR("DP training pattern 3 not supported\n");
2540                                 *DP |= DP_LINK_TRAIN_PAT_2;
2541                         }
2542                         break;
2543                 }
2544         }
2545 }
2546
2547 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2548 {
2549         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2550         struct drm_i915_private *dev_priv = dev->dev_private;
2551
2552         /* enable with pattern 1 (as per spec) */
2553         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2554                                  DP_TRAINING_PATTERN_1);
2555
2556         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2557         POSTING_READ(intel_dp->output_reg);
2558
2559         /*
2560          * Magic for VLV/CHV. We _must_ first set up the register
2561          * without actually enabling the port, and then do another
2562          * write to enable the port. Otherwise link training will
2563          * fail when the power sequencer is freshly used for this port.
2564          */
2565         intel_dp->DP |= DP_PORT_EN;
2566
2567         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2568         POSTING_READ(intel_dp->output_reg);
2569 }
2570
2571 static void intel_enable_dp(struct intel_encoder *encoder)
2572 {
2573         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2574         struct drm_device *dev = encoder->base.dev;
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2577         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2578
2579         if (WARN_ON(dp_reg & DP_PORT_EN))
2580                 return;
2581
2582         pps_lock(intel_dp);
2583
2584         if (IS_VALLEYVIEW(dev))
2585                 vlv_init_panel_power_sequencer(intel_dp);
2586
2587         intel_dp_enable_port(intel_dp);
2588
2589         edp_panel_vdd_on(intel_dp);
2590         edp_panel_on(intel_dp);
2591         edp_panel_vdd_off(intel_dp, true);
2592
2593         pps_unlock(intel_dp);
2594
2595         if (IS_VALLEYVIEW(dev)) {
2596                 unsigned int lane_mask = 0x0;
2597
2598                 if (IS_CHERRYVIEW(dev))
2599                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2600
2601                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2602                                     lane_mask);
2603         }
2604
2605         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2606         intel_dp_start_link_train(intel_dp);
2607         intel_dp_complete_link_train(intel_dp);
2608         intel_dp_stop_link_train(intel_dp);
2609
2610         if (crtc->config->has_audio) {
2611                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2612                                  pipe_name(crtc->pipe));
2613                 intel_audio_codec_enable(encoder);
2614         }
2615 }
2616
2617 static void g4x_enable_dp(struct intel_encoder *encoder)
2618 {
2619         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2620
2621         intel_enable_dp(encoder);
2622         intel_edp_backlight_on(intel_dp);
2623 }
2624
2625 static void vlv_enable_dp(struct intel_encoder *encoder)
2626 {
2627         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2628
2629         intel_edp_backlight_on(intel_dp);
2630         intel_psr_enable(intel_dp);
2631 }
2632
2633 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2634 {
2635         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2636         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2637
2638         intel_dp_prepare(encoder);
2639
2640         /* Only ilk+ has port A */
2641         if (dport->port == PORT_A) {
2642                 ironlake_set_pll_cpu_edp(intel_dp);
2643                 ironlake_edp_pll_on(intel_dp);
2644         }
2645 }
2646
2647 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2648 {
2649         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2650         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2651         enum pipe pipe = intel_dp->pps_pipe;
2652         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2653
2654         edp_panel_vdd_off_sync(intel_dp);
2655
2656         /*
2657          * VLV seems to get confused when multiple power seqeuencers
2658          * have the same port selected (even if only one has power/vdd
2659          * enabled). The failure manifests as vlv_wait_port_ready() failing
2660          * CHV on the other hand doesn't seem to mind having the same port
2661          * selected in multiple power seqeuencers, but let's clear the
2662          * port select always when logically disconnecting a power sequencer
2663          * from a port.
2664          */
2665         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2666                       pipe_name(pipe), port_name(intel_dig_port->port));
2667         I915_WRITE(pp_on_reg, 0);
2668         POSTING_READ(pp_on_reg);
2669
2670         intel_dp->pps_pipe = INVALID_PIPE;
2671 }
2672
2673 static void vlv_steal_power_sequencer(struct drm_device *dev,
2674                                       enum pipe pipe)
2675 {
2676         struct drm_i915_private *dev_priv = dev->dev_private;
2677         struct intel_encoder *encoder;
2678
2679         lockdep_assert_held(&dev_priv->pps_mutex);
2680
2681         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2682                 return;
2683
2684         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2685                             base.head) {
2686                 struct intel_dp *intel_dp;
2687                 enum port port;
2688
2689                 if (encoder->type != INTEL_OUTPUT_EDP)
2690                         continue;
2691
2692                 intel_dp = enc_to_intel_dp(&encoder->base);
2693                 port = dp_to_dig_port(intel_dp)->port;
2694
2695                 if (intel_dp->pps_pipe != pipe)
2696                         continue;
2697
2698                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2699                               pipe_name(pipe), port_name(port));
2700
2701                 WARN(encoder->base.crtc,
2702                      "stealing pipe %c power sequencer from active eDP port %c\n",
2703                      pipe_name(pipe), port_name(port));
2704
2705                 /* make sure vdd is off before we steal it */
2706                 vlv_detach_power_sequencer(intel_dp);
2707         }
2708 }
2709
2710 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2711 {
2712         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2713         struct intel_encoder *encoder = &intel_dig_port->base;
2714         struct drm_device *dev = encoder->base.dev;
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2717
2718         lockdep_assert_held(&dev_priv->pps_mutex);
2719
2720         if (!is_edp(intel_dp))
2721                 return;
2722
2723         if (intel_dp->pps_pipe == crtc->pipe)
2724                 return;
2725
2726         /*
2727          * If another power sequencer was being used on this
2728          * port previously make sure to turn off vdd there while
2729          * we still have control of it.
2730          */
2731         if (intel_dp->pps_pipe != INVALID_PIPE)
2732                 vlv_detach_power_sequencer(intel_dp);
2733
2734         /*
2735          * We may be stealing the power
2736          * sequencer from another port.
2737          */
2738         vlv_steal_power_sequencer(dev, crtc->pipe);
2739
2740         /* now it's all ours */
2741         intel_dp->pps_pipe = crtc->pipe;
2742
2743         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2744                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2745
2746         /* init power sequencer on this pipe and port */
2747         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2748         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2749 }
2750
2751 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2752 {
2753         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2754         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2755         struct drm_device *dev = encoder->base.dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2758         enum dpio_channel port = vlv_dport_to_channel(dport);
2759         int pipe = intel_crtc->pipe;
2760         u32 val;
2761
2762         mutex_lock(&dev_priv->sb_lock);
2763
2764         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2765         val = 0;
2766         if (pipe)
2767                 val |= (1<<21);
2768         else
2769                 val &= ~(1<<21);
2770         val |= 0x001000c4;
2771         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2772         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2773         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2774
2775         mutex_unlock(&dev_priv->sb_lock);
2776
2777         intel_enable_dp(encoder);
2778 }
2779
2780 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2781 {
2782         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2783         struct drm_device *dev = encoder->base.dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc =
2786                 to_intel_crtc(encoder->base.crtc);
2787         enum dpio_channel port = vlv_dport_to_channel(dport);
2788         int pipe = intel_crtc->pipe;
2789
2790         intel_dp_prepare(encoder);
2791
2792         /* Program Tx lane resets to default */
2793         mutex_lock(&dev_priv->sb_lock);
2794         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2795                          DPIO_PCS_TX_LANE2_RESET |
2796                          DPIO_PCS_TX_LANE1_RESET);
2797         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2798                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2799                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2800                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2801                                  DPIO_PCS_CLK_SOFT_RESET);
2802
2803         /* Fix up inter-pair skew failure */
2804         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2805         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2806         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2807         mutex_unlock(&dev_priv->sb_lock);
2808 }
2809
2810 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2811 {
2812         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2813         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2814         struct drm_device *dev = encoder->base.dev;
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         struct intel_crtc *intel_crtc =
2817                 to_intel_crtc(encoder->base.crtc);
2818         enum dpio_channel ch = vlv_dport_to_channel(dport);
2819         int pipe = intel_crtc->pipe;
2820         int data, i, stagger;
2821         u32 val;
2822
2823         mutex_lock(&dev_priv->sb_lock);
2824
2825         /* allow hardware to manage TX FIFO reset source */
2826         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2827         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2828         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2829
2830         if (intel_crtc->config->lane_count > 2) {
2831                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2832                 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2833                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2834         }
2835
2836         /* Program Tx lane latency optimal setting*/
2837         for (i = 0; i < intel_crtc->config->lane_count; i++) {
2838                 /* Set the upar bit */
2839                 if (intel_crtc->config->lane_count == 1)
2840                         data = 0x0;
2841                 else
2842                         data = (i == 1) ? 0x0 : 0x1;
2843                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2844                                 data << DPIO_UPAR_SHIFT);
2845         }
2846
2847         /* Data lane stagger programming */
2848         if (intel_crtc->config->port_clock > 270000)
2849                 stagger = 0x18;
2850         else if (intel_crtc->config->port_clock > 135000)
2851                 stagger = 0xd;
2852         else if (intel_crtc->config->port_clock > 67500)
2853                 stagger = 0x7;
2854         else if (intel_crtc->config->port_clock > 33750)
2855                 stagger = 0x4;
2856         else
2857                 stagger = 0x2;
2858
2859         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2860         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2861         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2862
2863         if (intel_crtc->config->lane_count > 2) {
2864                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2865                 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2866                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2867         }
2868
2869         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2870                        DPIO_LANESTAGGER_STRAP(stagger) |
2871                        DPIO_LANESTAGGER_STRAP_OVRD |
2872                        DPIO_TX1_STAGGER_MASK(0x1f) |
2873                        DPIO_TX1_STAGGER_MULT(6) |
2874                        DPIO_TX2_STAGGER_MULT(0));
2875
2876         if (intel_crtc->config->lane_count > 2) {
2877                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2878                                DPIO_LANESTAGGER_STRAP(stagger) |
2879                                DPIO_LANESTAGGER_STRAP_OVRD |
2880                                DPIO_TX1_STAGGER_MASK(0x1f) |
2881                                DPIO_TX1_STAGGER_MULT(7) |
2882                                DPIO_TX2_STAGGER_MULT(5));
2883         }
2884
2885         /* Deassert data lane reset */
2886         chv_data_lane_soft_reset(encoder, false);
2887
2888         mutex_unlock(&dev_priv->sb_lock);
2889
2890         intel_enable_dp(encoder);
2891
2892         /* Second common lane will stay alive on its own now */
2893         if (dport->release_cl2_override) {
2894                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2895                 dport->release_cl2_override = false;
2896         }
2897 }
2898
2899 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2900 {
2901         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2902         struct drm_device *dev = encoder->base.dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         struct intel_crtc *intel_crtc =
2905                 to_intel_crtc(encoder->base.crtc);
2906         enum dpio_channel ch = vlv_dport_to_channel(dport);
2907         enum pipe pipe = intel_crtc->pipe;
2908         unsigned int lane_mask =
2909                 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
2910         u32 val;
2911
2912         intel_dp_prepare(encoder);
2913
2914         /*
2915          * Must trick the second common lane into life.
2916          * Otherwise we can't even access the PLL.
2917          */
2918         if (ch == DPIO_CH0 && pipe == PIPE_B)
2919                 dport->release_cl2_override =
2920                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
2921
2922         chv_phy_powergate_lanes(encoder, true, lane_mask);
2923
2924         mutex_lock(&dev_priv->sb_lock);
2925
2926         /* Assert data lane reset */
2927         chv_data_lane_soft_reset(encoder, true);
2928
2929         /* program left/right clock distribution */
2930         if (pipe != PIPE_B) {
2931                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2932                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2933                 if (ch == DPIO_CH0)
2934                         val |= CHV_BUFLEFTENA1_FORCE;
2935                 if (ch == DPIO_CH1)
2936                         val |= CHV_BUFRIGHTENA1_FORCE;
2937                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2938         } else {
2939                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2940                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2941                 if (ch == DPIO_CH0)
2942                         val |= CHV_BUFLEFTENA2_FORCE;
2943                 if (ch == DPIO_CH1)
2944                         val |= CHV_BUFRIGHTENA2_FORCE;
2945                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2946         }
2947
2948         /* program clock channel usage */
2949         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2950         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2951         if (pipe != PIPE_B)
2952                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2953         else
2954                 val |= CHV_PCS_USEDCLKCHANNEL;
2955         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2956
2957         if (intel_crtc->config->lane_count > 2) {
2958                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2959                 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2960                 if (pipe != PIPE_B)
2961                         val &= ~CHV_PCS_USEDCLKCHANNEL;
2962                 else
2963                         val |= CHV_PCS_USEDCLKCHANNEL;
2964                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2965         }
2966
2967         /*
2968          * This a a bit weird since generally CL
2969          * matches the pipe, but here we need to
2970          * pick the CL based on the port.
2971          */
2972         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2973         if (pipe != PIPE_B)
2974                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2975         else
2976                 val |= CHV_CMN_USEDCLKCHANNEL;
2977         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2978
2979         mutex_unlock(&dev_priv->sb_lock);
2980 }
2981
2982 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2983 {
2984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2985         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2986         u32 val;
2987
2988         mutex_lock(&dev_priv->sb_lock);
2989
2990         /* disable left/right clock distribution */
2991         if (pipe != PIPE_B) {
2992                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2993                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2994                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2995         } else {
2996                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2997                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2998                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2999         }
3000
3001         mutex_unlock(&dev_priv->sb_lock);
3002
3003         /*
3004          * Leave the power down bit cleared for at least one
3005          * lane so that chv_powergate_phy_ch() will power
3006          * on something when the channel is otherwise unused.
3007          * When the port is off and the override is removed
3008          * the lanes power down anyway, so otherwise it doesn't
3009          * really matter what the state of power down bits is
3010          * after this.
3011          */
3012         chv_phy_powergate_lanes(encoder, false, 0x0);
3013 }
3014
3015 /*
3016  * Native read with retry for link status and receiver capability reads for
3017  * cases where the sink may still be asleep.
3018  *
3019  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3020  * supposed to retry 3 times per the spec.
3021  */
3022 static ssize_t
3023 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3024                         void *buffer, size_t size)
3025 {
3026         ssize_t ret;
3027         int i;
3028
3029         /*
3030          * Sometime we just get the same incorrect byte repeated
3031          * over the entire buffer. Doing just one throw away read
3032          * initially seems to "solve" it.
3033          */
3034         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3035
3036         for (i = 0; i < 3; i++) {
3037                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3038                 if (ret == size)
3039                         return ret;
3040                 msleep(1);
3041         }
3042
3043         return ret;
3044 }
3045
3046 /*
3047  * Fetch AUX CH registers 0x202 - 0x207 which contain
3048  * link status information
3049  */
3050 static bool
3051 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3052 {
3053         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3054                                        DP_LANE0_1_STATUS,
3055                                        link_status,
3056                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3057 }
3058
3059 /* These are source-specific values. */
3060 static uint8_t
3061 intel_dp_voltage_max(struct intel_dp *intel_dp)
3062 {
3063         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3064         struct drm_i915_private *dev_priv = dev->dev_private;
3065         enum port port = dp_to_dig_port(intel_dp)->port;
3066
3067         if (IS_BROXTON(dev))
3068                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3069         else if (INTEL_INFO(dev)->gen >= 9) {
3070                 if (dev_priv->edp_low_vswing && port == PORT_A)
3071                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3072                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3073         } else if (IS_VALLEYVIEW(dev))
3074                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3075         else if (IS_GEN7(dev) && port == PORT_A)
3076                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3077         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3078                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3079         else
3080                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3081 }
3082
3083 static uint8_t
3084 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3085 {
3086         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3087         enum port port = dp_to_dig_port(intel_dp)->port;
3088
3089         if (INTEL_INFO(dev)->gen >= 9) {
3090                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3091                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3092                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3093                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3094                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3095                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3096                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3097                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3098                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3099                 default:
3100                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3101                 }
3102         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3103                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3104                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3105                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3106                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3107                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3108                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3109                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3110                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3111                 default:
3112                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3113                 }
3114         } else if (IS_VALLEYVIEW(dev)) {
3115                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3116                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3117                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3118                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3119                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3120                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3121                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3122                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3123                 default:
3124                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3125                 }
3126         } else if (IS_GEN7(dev) && port == PORT_A) {
3127                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3128                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3129                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3130                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3132                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3133                 default:
3134                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3135                 }
3136         } else {
3137                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3138                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3139                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3140                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3141                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3142                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3143                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3144                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3145                 default:
3146                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3147                 }
3148         }
3149 }
3150
3151 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3152 {
3153         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3154         struct drm_i915_private *dev_priv = dev->dev_private;
3155         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3156         struct intel_crtc *intel_crtc =
3157                 to_intel_crtc(dport->base.base.crtc);
3158         unsigned long demph_reg_value, preemph_reg_value,
3159                 uniqtranscale_reg_value;
3160         uint8_t train_set = intel_dp->train_set[0];
3161         enum dpio_channel port = vlv_dport_to_channel(dport);
3162         int pipe = intel_crtc->pipe;
3163
3164         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3165         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3166                 preemph_reg_value = 0x0004000;
3167                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3169                         demph_reg_value = 0x2B405555;
3170                         uniqtranscale_reg_value = 0x552AB83A;
3171                         break;
3172                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3173                         demph_reg_value = 0x2B404040;
3174                         uniqtranscale_reg_value = 0x5548B83A;
3175                         break;
3176                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3177                         demph_reg_value = 0x2B245555;
3178                         uniqtranscale_reg_value = 0x5560B83A;
3179                         break;
3180                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3181                         demph_reg_value = 0x2B405555;
3182                         uniqtranscale_reg_value = 0x5598DA3A;
3183                         break;
3184                 default:
3185                         return 0;
3186                 }
3187                 break;
3188         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3189                 preemph_reg_value = 0x0002000;
3190                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3191                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3192                         demph_reg_value = 0x2B404040;
3193                         uniqtranscale_reg_value = 0x5552B83A;
3194                         break;
3195                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3196                         demph_reg_value = 0x2B404848;
3197                         uniqtranscale_reg_value = 0x5580B83A;
3198                         break;
3199                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3200                         demph_reg_value = 0x2B404040;
3201                         uniqtranscale_reg_value = 0x55ADDA3A;
3202                         break;
3203                 default:
3204                         return 0;
3205                 }
3206                 break;
3207         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3208                 preemph_reg_value = 0x0000000;
3209                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3210                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3211                         demph_reg_value = 0x2B305555;
3212                         uniqtranscale_reg_value = 0x5570B83A;
3213                         break;
3214                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3215                         demph_reg_value = 0x2B2B4040;
3216                         uniqtranscale_reg_value = 0x55ADDA3A;
3217                         break;
3218                 default:
3219                         return 0;
3220                 }
3221                 break;
3222         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3223                 preemph_reg_value = 0x0006000;
3224                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3225                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3226                         demph_reg_value = 0x1B405555;
3227                         uniqtranscale_reg_value = 0x55ADDA3A;
3228                         break;
3229                 default:
3230                         return 0;
3231                 }
3232                 break;
3233         default:
3234                 return 0;
3235         }
3236
3237         mutex_lock(&dev_priv->sb_lock);
3238         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3239         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3240         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3241                          uniqtranscale_reg_value);
3242         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3243         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3244         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3245         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3246         mutex_unlock(&dev_priv->sb_lock);
3247
3248         return 0;
3249 }
3250
3251 static bool chv_need_uniq_trans_scale(uint8_t train_set)
3252 {
3253         return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3254                 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3255 }
3256
3257 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3258 {
3259         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3262         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3263         u32 deemph_reg_value, margin_reg_value, val;
3264         uint8_t train_set = intel_dp->train_set[0];
3265         enum dpio_channel ch = vlv_dport_to_channel(dport);
3266         enum pipe pipe = intel_crtc->pipe;
3267         int i;
3268
3269         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3270         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3271                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3272                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3273                         deemph_reg_value = 128;
3274                         margin_reg_value = 52;
3275                         break;
3276                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3277                         deemph_reg_value = 128;
3278                         margin_reg_value = 77;
3279                         break;
3280                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3281                         deemph_reg_value = 128;
3282                         margin_reg_value = 102;
3283                         break;
3284                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3285                         deemph_reg_value = 128;
3286                         margin_reg_value = 154;
3287                         /* FIXME extra to set for 1200 */
3288                         break;
3289                 default:
3290                         return 0;
3291                 }
3292                 break;
3293         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3294                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3295                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3296                         deemph_reg_value = 85;
3297                         margin_reg_value = 78;
3298                         break;
3299                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3300                         deemph_reg_value = 85;
3301                         margin_reg_value = 116;
3302                         break;
3303                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3304                         deemph_reg_value = 85;
3305                         margin_reg_value = 154;
3306                         break;
3307                 default:
3308                         return 0;
3309                 }
3310                 break;
3311         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3312                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3313                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3314                         deemph_reg_value = 64;
3315                         margin_reg_value = 104;
3316                         break;
3317                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3318                         deemph_reg_value = 64;
3319                         margin_reg_value = 154;
3320                         break;
3321                 default:
3322                         return 0;
3323                 }
3324                 break;
3325         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3326                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3327                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3328                         deemph_reg_value = 43;
3329                         margin_reg_value = 154;
3330                         break;
3331                 default:
3332                         return 0;
3333                 }
3334                 break;
3335         default:
3336                 return 0;
3337         }
3338
3339         mutex_lock(&dev_priv->sb_lock);
3340
3341         /* Clear calc init */
3342         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3343         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3344         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3345         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3346         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3347
3348         if (intel_crtc->config->lane_count > 2) {
3349                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3350                 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3351                 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3352                 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3353                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3354         }
3355
3356         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3357         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3358         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3359         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3360
3361         if (intel_crtc->config->lane_count > 2) {
3362                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3363                 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3364                 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3365                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3366         }
3367
3368         /* Program swing deemph */
3369         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3370                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3371                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3372                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3373                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3374         }
3375
3376         /* Program swing margin */
3377         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3378                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3379
3380                 val &= ~DPIO_SWING_MARGIN000_MASK;
3381                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3382
3383                 /*
3384                  * Supposedly this value shouldn't matter when unique transition
3385                  * scale is disabled, but in fact it does matter. Let's just
3386                  * always program the same value and hope it's OK.
3387                  */
3388                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3389                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3390
3391                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3392         }
3393
3394         /*
3395          * The document said it needs to set bit 27 for ch0 and bit 26
3396          * for ch1. Might be a typo in the doc.
3397          * For now, for this unique transition scale selection, set bit
3398          * 27 for ch0 and ch1.
3399          */
3400         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3401                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3402                 if (chv_need_uniq_trans_scale(train_set))
3403                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3404                 else
3405                         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3406                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3407         }
3408
3409         /* Start swing calculation */
3410         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3411         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3412         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3413
3414         if (intel_crtc->config->lane_count > 2) {
3415                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3416                 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3417                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3418         }
3419
3420         /* LRC Bypass */
3421         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3422         val |= DPIO_LRC_BYPASS;
3423         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3424
3425         mutex_unlock(&dev_priv->sb_lock);
3426
3427         return 0;
3428 }
3429
3430 static void
3431 intel_get_adjust_train(struct intel_dp *intel_dp,
3432                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3433 {
3434         uint8_t v = 0;
3435         uint8_t p = 0;
3436         int lane;
3437         uint8_t voltage_max;
3438         uint8_t preemph_max;
3439
3440         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3441                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3442                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3443
3444                 if (this_v > v)
3445                         v = this_v;
3446                 if (this_p > p)
3447                         p = this_p;
3448         }
3449
3450         voltage_max = intel_dp_voltage_max(intel_dp);
3451         if (v >= voltage_max)
3452                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3453
3454         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3455         if (p >= preemph_max)
3456                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3457
3458         for (lane = 0; lane < 4; lane++)
3459                 intel_dp->train_set[lane] = v | p;
3460 }
3461
3462 static uint32_t
3463 gen4_signal_levels(uint8_t train_set)
3464 {
3465         uint32_t        signal_levels = 0;
3466
3467         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3468         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3469         default:
3470                 signal_levels |= DP_VOLTAGE_0_4;
3471                 break;
3472         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3473                 signal_levels |= DP_VOLTAGE_0_6;
3474                 break;
3475         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3476                 signal_levels |= DP_VOLTAGE_0_8;
3477                 break;
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3479                 signal_levels |= DP_VOLTAGE_1_2;
3480                 break;
3481         }
3482         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3483         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3484         default:
3485                 signal_levels |= DP_PRE_EMPHASIS_0;
3486                 break;
3487         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3488                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3489                 break;
3490         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3491                 signal_levels |= DP_PRE_EMPHASIS_6;
3492                 break;
3493         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3494                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3495                 break;
3496         }
3497         return signal_levels;
3498 }
3499
3500 /* Gen6's DP voltage swing and pre-emphasis control */
3501 static uint32_t
3502 gen6_edp_signal_levels(uint8_t train_set)
3503 {
3504         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3505                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3506         switch (signal_levels) {
3507         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3508         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3509                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3510         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3511                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3512         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3513         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3514                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3515         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3516         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3517                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3518         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3519         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3520                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3521         default:
3522                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3523                               "0x%x\n", signal_levels);
3524                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3525         }
3526 }
3527
3528 /* Gen7's DP voltage swing and pre-emphasis control */
3529 static uint32_t
3530 gen7_edp_signal_levels(uint8_t train_set)
3531 {
3532         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3533                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3534         switch (signal_levels) {
3535         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3536                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3537         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3538                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3539         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3540                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3541
3542         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3543                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3544         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3545                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3546
3547         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3548                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3549         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3550                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3551
3552         default:
3553                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3554                               "0x%x\n", signal_levels);
3555                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3556         }
3557 }
3558
3559 /* Properly updates "DP" with the correct signal levels. */
3560 static void
3561 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3562 {
3563         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3564         enum port port = intel_dig_port->port;
3565         struct drm_device *dev = intel_dig_port->base.base.dev;
3566         uint32_t signal_levels, mask = 0;
3567         uint8_t train_set = intel_dp->train_set[0];
3568
3569         if (HAS_DDI(dev)) {
3570                 signal_levels = ddi_signal_levels(intel_dp);
3571
3572                 if (IS_BROXTON(dev))
3573                         signal_levels = 0;
3574                 else
3575                         mask = DDI_BUF_EMP_MASK;
3576         } else if (IS_CHERRYVIEW(dev)) {
3577                 signal_levels = chv_signal_levels(intel_dp);
3578         } else if (IS_VALLEYVIEW(dev)) {
3579                 signal_levels = vlv_signal_levels(intel_dp);
3580         } else if (IS_GEN7(dev) && port == PORT_A) {
3581                 signal_levels = gen7_edp_signal_levels(train_set);
3582                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3583         } else if (IS_GEN6(dev) && port == PORT_A) {
3584                 signal_levels = gen6_edp_signal_levels(train_set);
3585                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3586         } else {
3587                 signal_levels = gen4_signal_levels(train_set);
3588                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3589         }
3590
3591         if (mask)
3592                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3593
3594         DRM_DEBUG_KMS("Using vswing level %d\n",
3595                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3596         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3597                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3598                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3599
3600         *DP = (*DP & ~mask) | signal_levels;
3601 }
3602
3603 static bool
3604 intel_dp_set_link_train(struct intel_dp *intel_dp,
3605                         uint32_t *DP,
3606                         uint8_t dp_train_pat)
3607 {
3608         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3609         struct drm_i915_private *dev_priv =
3610                 to_i915(intel_dig_port->base.base.dev);
3611         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3612         int ret, len;
3613
3614         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3615
3616         I915_WRITE(intel_dp->output_reg, *DP);
3617         POSTING_READ(intel_dp->output_reg);
3618
3619         buf[0] = dp_train_pat;
3620         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3621             DP_TRAINING_PATTERN_DISABLE) {
3622                 /* don't write DP_TRAINING_LANEx_SET on disable */
3623                 len = 1;
3624         } else {
3625                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3626                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3627                 len = intel_dp->lane_count + 1;
3628         }
3629
3630         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3631                                 buf, len);
3632
3633         return ret == len;
3634 }
3635
3636 static bool
3637 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3638                         uint8_t dp_train_pat)
3639 {
3640         if (!intel_dp->train_set_valid)
3641                 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3642         intel_dp_set_signal_levels(intel_dp, DP);
3643         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3644 }
3645
3646 static bool
3647 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3648                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3649 {
3650         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651         struct drm_i915_private *dev_priv =
3652                 to_i915(intel_dig_port->base.base.dev);
3653         int ret;
3654
3655         intel_get_adjust_train(intel_dp, link_status);
3656         intel_dp_set_signal_levels(intel_dp, DP);
3657
3658         I915_WRITE(intel_dp->output_reg, *DP);
3659         POSTING_READ(intel_dp->output_reg);
3660
3661         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3662                                 intel_dp->train_set, intel_dp->lane_count);
3663
3664         return ret == intel_dp->lane_count;
3665 }
3666
3667 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3668 {
3669         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3670         struct drm_device *dev = intel_dig_port->base.base.dev;
3671         struct drm_i915_private *dev_priv = dev->dev_private;
3672         enum port port = intel_dig_port->port;
3673         uint32_t val;
3674
3675         if (!HAS_DDI(dev))
3676                 return;
3677
3678         val = I915_READ(DP_TP_CTL(port));
3679         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3680         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3681         I915_WRITE(DP_TP_CTL(port), val);
3682
3683         /*
3684          * On PORT_A we can have only eDP in SST mode. There the only reason
3685          * we need to set idle transmission mode is to work around a HW issue
3686          * where we enable the pipe while not in idle link-training mode.
3687          * In this case there is requirement to wait for a minimum number of
3688          * idle patterns to be sent.
3689          */
3690         if (port == PORT_A)
3691                 return;
3692
3693         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3694                      1))
3695                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3696 }
3697
3698 /* Enable corresponding port and start training pattern 1 */
3699 void
3700 intel_dp_start_link_train(struct intel_dp *intel_dp)
3701 {
3702         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3703         struct drm_device *dev = encoder->dev;
3704         int i;
3705         uint8_t voltage;
3706         int voltage_tries, loop_tries;
3707         uint32_t DP = intel_dp->DP;
3708         uint8_t link_config[2];
3709         uint8_t link_bw, rate_select;
3710
3711         if (HAS_DDI(dev))
3712                 intel_ddi_prepare_link_retrain(encoder);
3713
3714         intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
3715                               &link_bw, &rate_select);
3716
3717         /* Write the link configuration data */
3718         link_config[0] = link_bw;
3719         link_config[1] = intel_dp->lane_count;
3720         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3721                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3722         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3723         if (intel_dp->num_sink_rates)
3724                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3725                                   &rate_select, 1);
3726
3727         link_config[0] = 0;
3728         link_config[1] = DP_SET_ANSI_8B10B;
3729         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3730
3731         DP |= DP_PORT_EN;
3732
3733         /* clock recovery */
3734         if (!intel_dp_reset_link_train(intel_dp, &DP,
3735                                        DP_TRAINING_PATTERN_1 |
3736                                        DP_LINK_SCRAMBLING_DISABLE)) {
3737                 DRM_ERROR("failed to enable link training\n");
3738                 return;
3739         }
3740
3741         voltage = 0xff;
3742         voltage_tries = 0;
3743         loop_tries = 0;
3744         for (;;) {
3745                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3746
3747                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3748                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3749                         DRM_ERROR("failed to get link status\n");
3750                         break;
3751                 }
3752
3753                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3754                         DRM_DEBUG_KMS("clock recovery OK\n");
3755                         break;
3756                 }
3757
3758                 /*
3759                  * if we used previously trained voltage and pre-emphasis values
3760                  * and we don't get clock recovery, reset link training values
3761                  */
3762                 if (intel_dp->train_set_valid) {
3763                         DRM_DEBUG_KMS("clock recovery not ok, reset");
3764                         /* clear the flag as we are not reusing train set */
3765                         intel_dp->train_set_valid = false;
3766                         if (!intel_dp_reset_link_train(intel_dp, &DP,
3767                                                        DP_TRAINING_PATTERN_1 |
3768                                                        DP_LINK_SCRAMBLING_DISABLE)) {
3769                                 DRM_ERROR("failed to enable link training\n");
3770                                 return;
3771                         }
3772                         continue;
3773                 }
3774
3775                 /* Check to see if we've tried the max voltage */
3776                 for (i = 0; i < intel_dp->lane_count; i++)
3777                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3778                                 break;
3779                 if (i == intel_dp->lane_count) {
3780                         ++loop_tries;
3781                         if (loop_tries == 5) {
3782                                 DRM_ERROR("too many full retries, give up\n");
3783                                 break;
3784                         }
3785                         intel_dp_reset_link_train(intel_dp, &DP,
3786                                                   DP_TRAINING_PATTERN_1 |
3787                                                   DP_LINK_SCRAMBLING_DISABLE);
3788                         voltage_tries = 0;
3789                         continue;
3790                 }
3791
3792                 /* Check to see if we've tried the same voltage 5 times */
3793                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3794                         ++voltage_tries;
3795                         if (voltage_tries == 5) {
3796                                 DRM_ERROR("too many voltage retries, give up\n");
3797                                 break;
3798                         }
3799                 } else
3800                         voltage_tries = 0;
3801                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3802
3803                 /* Update training set as requested by target */
3804                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3805                         DRM_ERROR("failed to update link training\n");
3806                         break;
3807                 }
3808         }
3809
3810         intel_dp->DP = DP;
3811 }
3812
3813 void
3814 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3815 {
3816         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3817         struct drm_device *dev = dig_port->base.base.dev;
3818         bool channel_eq = false;
3819         int tries, cr_tries;
3820         uint32_t DP = intel_dp->DP;
3821         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3822
3823         /*
3824          * Training Pattern 3 for HBR2 or 1.2 devices that support it.
3825          *
3826          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
3827          * also mandatory for downstream devices that support HBR2.
3828          *
3829          * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
3830          * supported but still not enabled.
3831          */
3832         if (intel_dp_source_supports_hbr2(dev) &&
3833             drm_dp_tps3_supported(intel_dp->dpcd))
3834                 training_pattern = DP_TRAINING_PATTERN_3;
3835         else if (intel_dp->link_rate == 540000)
3836                 DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
3837
3838         /* channel equalization */
3839         if (!intel_dp_set_link_train(intel_dp, &DP,
3840                                      training_pattern |
3841                                      DP_LINK_SCRAMBLING_DISABLE)) {
3842                 DRM_ERROR("failed to start channel equalization\n");
3843                 return;
3844         }
3845
3846         tries = 0;
3847         cr_tries = 0;
3848         channel_eq = false;
3849         for (;;) {
3850                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3851
3852                 if (cr_tries > 5) {
3853                         DRM_ERROR("failed to train DP, aborting\n");
3854                         break;
3855                 }
3856
3857                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3858                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3859                         DRM_ERROR("failed to get link status\n");
3860                         break;
3861                 }
3862
3863                 /* Make sure clock is still ok */
3864                 if (!drm_dp_clock_recovery_ok(link_status,
3865                                               intel_dp->lane_count)) {
3866                         intel_dp->train_set_valid = false;
3867                         intel_dp_start_link_train(intel_dp);
3868                         intel_dp_set_link_train(intel_dp, &DP,
3869                                                 training_pattern |
3870                                                 DP_LINK_SCRAMBLING_DISABLE);
3871                         cr_tries++;
3872                         continue;
3873                 }
3874
3875                 if (drm_dp_channel_eq_ok(link_status,
3876                                          intel_dp->lane_count)) {
3877                         channel_eq = true;
3878                         break;
3879                 }
3880
3881                 /* Try 5 times, then try clock recovery if that fails */
3882                 if (tries > 5) {
3883                         intel_dp->train_set_valid = false;
3884                         intel_dp_start_link_train(intel_dp);
3885                         intel_dp_set_link_train(intel_dp, &DP,
3886                                                 training_pattern |
3887                                                 DP_LINK_SCRAMBLING_DISABLE);
3888                         tries = 0;
3889                         cr_tries++;
3890                         continue;
3891                 }
3892
3893                 /* Update training set as requested by target */
3894                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3895                         DRM_ERROR("failed to update link training\n");
3896                         break;
3897                 }
3898                 ++tries;
3899         }
3900
3901         intel_dp_set_idle_link_train(intel_dp);
3902
3903         intel_dp->DP = DP;
3904
3905         if (channel_eq) {
3906                 intel_dp->train_set_valid = true;
3907                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3908         }
3909 }
3910
3911 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3912 {
3913         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3914                                 DP_TRAINING_PATTERN_DISABLE);
3915 }
3916
3917 static void
3918 intel_dp_link_down(struct intel_dp *intel_dp)
3919 {
3920         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3921         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3922         enum port port = intel_dig_port->port;
3923         struct drm_device *dev = intel_dig_port->base.base.dev;
3924         struct drm_i915_private *dev_priv = dev->dev_private;
3925         uint32_t DP = intel_dp->DP;
3926
3927         if (WARN_ON(HAS_DDI(dev)))
3928                 return;
3929
3930         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3931                 return;
3932
3933         DRM_DEBUG_KMS("\n");
3934
3935         if ((IS_GEN7(dev) && port == PORT_A) ||
3936             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3937                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3938                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3939         } else {
3940                 if (IS_CHERRYVIEW(dev))
3941                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3942                 else
3943                         DP &= ~DP_LINK_TRAIN_MASK;
3944                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3945         }
3946         I915_WRITE(intel_dp->output_reg, DP);
3947         POSTING_READ(intel_dp->output_reg);
3948
3949         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3950         I915_WRITE(intel_dp->output_reg, DP);
3951         POSTING_READ(intel_dp->output_reg);
3952
3953         /*
3954          * HW workaround for IBX, we need to move the port
3955          * to transcoder A after disabling it to allow the
3956          * matching HDMI port to be enabled on transcoder A.
3957          */
3958         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3959                 /* always enable with pattern 1 (as per spec) */
3960                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3961                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3962                 I915_WRITE(intel_dp->output_reg, DP);
3963                 POSTING_READ(intel_dp->output_reg);
3964
3965                 DP &= ~DP_PORT_EN;
3966                 I915_WRITE(intel_dp->output_reg, DP);
3967                 POSTING_READ(intel_dp->output_reg);
3968         }
3969
3970         msleep(intel_dp->panel_power_down_delay);
3971 }
3972
3973 static bool
3974 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3975 {
3976         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3977         struct drm_device *dev = dig_port->base.base.dev;
3978         struct drm_i915_private *dev_priv = dev->dev_private;
3979         uint8_t rev;
3980
3981         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3982                                     sizeof(intel_dp->dpcd)) < 0)
3983                 return false; /* aux transfer failed */
3984
3985         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3986
3987         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3988                 return false; /* DPCD not present */
3989
3990         /* Check if the panel supports PSR */
3991         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3992         if (is_edp(intel_dp)) {
3993                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3994                                         intel_dp->psr_dpcd,
3995                                         sizeof(intel_dp->psr_dpcd));
3996                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3997                         dev_priv->psr.sink_support = true;
3998                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3999                 }
4000
4001                 if (INTEL_INFO(dev)->gen >= 9 &&
4002                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
4003                         uint8_t frame_sync_cap;
4004
4005                         dev_priv->psr.sink_support = true;
4006                         intel_dp_dpcd_read_wake(&intel_dp->aux,
4007                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
4008                                         &frame_sync_cap, 1);
4009                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
4010                         /* PSR2 needs frame sync as well */
4011                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
4012                         DRM_DEBUG_KMS("PSR2 %s on sink",
4013                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
4014                 }
4015         }
4016
4017         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4018                       yesno(intel_dp_source_supports_hbr2(dev)),
4019                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4020
4021         /* Intermediate frequency support */
4022         if (is_edp(intel_dp) &&
4023             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
4024             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
4025             (rev >= 0x03)) { /* eDp v1.4 or higher */
4026                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4027                 int i;
4028
4029                 intel_dp_dpcd_read_wake(&intel_dp->aux,
4030                                 DP_SUPPORTED_LINK_RATES,
4031                                 sink_rates,
4032                                 sizeof(sink_rates));
4033
4034                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4035                         int val = le16_to_cpu(sink_rates[i]);
4036
4037                         if (val == 0)
4038                                 break;
4039
4040                         /* Value read is in kHz while drm clock is saved in deca-kHz */
4041                         intel_dp->sink_rates[i] = (val * 200) / 10;
4042                 }
4043                 intel_dp->num_sink_rates = i;
4044         }
4045
4046         intel_dp_print_rates(intel_dp);
4047
4048         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4049               DP_DWN_STRM_PORT_PRESENT))
4050                 return true; /* native DP sink */
4051
4052         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4053                 return true; /* no per-port downstream info */
4054
4055         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4056                                     intel_dp->downstream_ports,
4057                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
4058                 return false; /* downstream port status fetch failed */
4059
4060         return true;
4061 }
4062
4063 static void
4064 intel_dp_probe_oui(struct intel_dp *intel_dp)
4065 {
4066         u8 buf[3];
4067
4068         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
4069                 return;
4070
4071         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
4072                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4073                               buf[0], buf[1], buf[2]);
4074
4075         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
4076                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4077                               buf[0], buf[1], buf[2]);
4078 }
4079
4080 static bool
4081 intel_dp_probe_mst(struct intel_dp *intel_dp)
4082 {
4083         u8 buf[1];
4084
4085         if (!intel_dp->can_mst)
4086                 return false;
4087
4088         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4089                 return false;
4090
4091         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
4092                 if (buf[0] & DP_MST_CAP) {
4093                         DRM_DEBUG_KMS("Sink is MST capable\n");
4094                         intel_dp->is_mst = true;
4095                 } else {
4096                         DRM_DEBUG_KMS("Sink is not MST capable\n");
4097                         intel_dp->is_mst = false;
4098                 }
4099         }
4100
4101         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4102         return intel_dp->is_mst;
4103 }
4104
4105 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
4106 {
4107         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4108         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4109         u8 buf;
4110         int ret = 0;
4111
4112         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4113                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4114                 ret = -EIO;
4115                 goto out;
4116         }
4117
4118         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4119                                buf & ~DP_TEST_SINK_START) < 0) {
4120                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4121                 ret = -EIO;
4122                 goto out;
4123         }
4124
4125         intel_dp->sink_crc.started = false;
4126  out:
4127         hsw_enable_ips(intel_crtc);
4128         return ret;
4129 }
4130
4131 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4132 {
4133         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4134         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4135         u8 buf;
4136         int ret;
4137
4138         if (intel_dp->sink_crc.started) {
4139                 ret = intel_dp_sink_crc_stop(intel_dp);
4140                 if (ret)
4141                         return ret;
4142         }
4143
4144         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4145                 return -EIO;
4146
4147         if (!(buf & DP_TEST_CRC_SUPPORTED))
4148                 return -ENOTTY;
4149
4150         intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4151
4152         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4153                 return -EIO;
4154
4155         hsw_disable_ips(intel_crtc);
4156
4157         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4158                                buf | DP_TEST_SINK_START) < 0) {
4159                 hsw_enable_ips(intel_crtc);
4160                 return -EIO;
4161         }
4162
4163         intel_dp->sink_crc.started = true;
4164         return 0;
4165 }
4166
4167 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4168 {
4169         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4170         struct drm_device *dev = dig_port->base.base.dev;
4171         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4172         u8 buf;
4173         int count, ret;
4174         int attempts = 6;
4175         bool old_equal_new;
4176
4177         ret = intel_dp_sink_crc_start(intel_dp);
4178         if (ret)
4179                 return ret;
4180
4181         do {
4182                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4183
4184                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4185                                       DP_TEST_SINK_MISC, &buf) < 0) {
4186                         ret = -EIO;
4187                         goto stop;
4188                 }
4189                 count = buf & DP_TEST_COUNT_MASK;
4190
4191                 /*
4192                  * Count might be reset during the loop. In this case
4193                  * last known count needs to be reset as well.
4194                  */
4195                 if (count == 0)
4196                         intel_dp->sink_crc.last_count = 0;
4197
4198                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4199                         ret = -EIO;
4200                         goto stop;
4201                 }
4202
4203                 old_equal_new = (count == intel_dp->sink_crc.last_count &&
4204                                  !memcmp(intel_dp->sink_crc.last_crc, crc,
4205                                          6 * sizeof(u8)));
4206
4207         } while (--attempts && (count == 0 || old_equal_new));
4208
4209         intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4210         memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
4211
4212         if (attempts == 0) {
4213                 if (old_equal_new) {
4214                         DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
4215                 } else {
4216                         DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4217                         ret = -ETIMEDOUT;
4218                         goto stop;
4219                 }
4220         }
4221
4222 stop:
4223         intel_dp_sink_crc_stop(intel_dp);
4224         return ret;
4225 }
4226
4227 static bool
4228 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4229 {
4230         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4231                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4232                                        sink_irq_vector, 1) == 1;
4233 }
4234
4235 static bool
4236 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4237 {
4238         int ret;
4239
4240         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4241                                              DP_SINK_COUNT_ESI,
4242                                              sink_irq_vector, 14);
4243         if (ret != 14)
4244                 return false;
4245
4246         return true;
4247 }
4248
4249 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4250 {
4251         uint8_t test_result = DP_TEST_ACK;
4252         return test_result;
4253 }
4254
4255 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4256 {
4257         uint8_t test_result = DP_TEST_NAK;
4258         return test_result;
4259 }
4260
4261 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4262 {
4263         uint8_t test_result = DP_TEST_NAK;
4264         struct intel_connector *intel_connector = intel_dp->attached_connector;
4265         struct drm_connector *connector = &intel_connector->base;
4266
4267         if (intel_connector->detect_edid == NULL ||
4268             connector->edid_corrupt ||
4269             intel_dp->aux.i2c_defer_count > 6) {
4270                 /* Check EDID read for NACKs, DEFERs and corruption
4271                  * (DP CTS 1.2 Core r1.1)
4272                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4273                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4274                  *    4.2.2.6 : EDID corruption detected
4275                  * Use failsafe mode for all cases
4276                  */
4277                 if (intel_dp->aux.i2c_nack_count > 0 ||
4278                         intel_dp->aux.i2c_defer_count > 0)
4279                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4280                                       intel_dp->aux.i2c_nack_count,
4281                                       intel_dp->aux.i2c_defer_count);
4282                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4283         } else {
4284                 struct edid *block = intel_connector->detect_edid;
4285
4286                 /* We have to write the checksum
4287                  * of the last block read
4288                  */
4289                 block += intel_connector->detect_edid->extensions;
4290
4291                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4292                                         DP_TEST_EDID_CHECKSUM,
4293                                         &block->checksum,
4294                                         1))
4295                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4296
4297                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4298                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4299         }
4300
4301         /* Set test active flag here so userspace doesn't interrupt things */
4302         intel_dp->compliance_test_active = 1;
4303
4304         return test_result;
4305 }
4306
4307 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4308 {
4309         uint8_t test_result = DP_TEST_NAK;
4310         return test_result;
4311 }
4312
4313 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4314 {
4315         uint8_t response = DP_TEST_NAK;
4316         uint8_t rxdata = 0;
4317         int status = 0;
4318
4319         intel_dp->compliance_test_active = 0;
4320         intel_dp->compliance_test_type = 0;
4321         intel_dp->compliance_test_data = 0;
4322
4323         intel_dp->aux.i2c_nack_count = 0;
4324         intel_dp->aux.i2c_defer_count = 0;
4325
4326         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4327         if (status <= 0) {
4328                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4329                 goto update_status;
4330         }
4331
4332         switch (rxdata) {
4333         case DP_TEST_LINK_TRAINING:
4334                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4335                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4336                 response = intel_dp_autotest_link_training(intel_dp);
4337                 break;
4338         case DP_TEST_LINK_VIDEO_PATTERN:
4339                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4340                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4341                 response = intel_dp_autotest_video_pattern(intel_dp);
4342                 break;
4343         case DP_TEST_LINK_EDID_READ:
4344                 DRM_DEBUG_KMS("EDID test requested\n");
4345                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4346                 response = intel_dp_autotest_edid(intel_dp);
4347                 break;
4348         case DP_TEST_LINK_PHY_TEST_PATTERN:
4349                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4350                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4351                 response = intel_dp_autotest_phy_pattern(intel_dp);
4352                 break;
4353         default:
4354                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4355                 break;
4356         }
4357
4358 update_status:
4359         status = drm_dp_dpcd_write(&intel_dp->aux,
4360                                    DP_TEST_RESPONSE,
4361                                    &response, 1);
4362         if (status <= 0)
4363                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4364 }
4365
4366 static int
4367 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4368 {
4369         bool bret;
4370
4371         if (intel_dp->is_mst) {
4372                 u8 esi[16] = { 0 };
4373                 int ret = 0;
4374                 int retry;
4375                 bool handled;
4376                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4377 go_again:
4378                 if (bret == true) {
4379
4380                         /* check link status - esi[10] = 0x200c */
4381                         if (intel_dp->active_mst_links &&
4382                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4383                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4384                                 intel_dp_start_link_train(intel_dp);
4385                                 intel_dp_complete_link_train(intel_dp);
4386                                 intel_dp_stop_link_train(intel_dp);
4387                         }
4388
4389                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4390                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4391
4392                         if (handled) {
4393                                 for (retry = 0; retry < 3; retry++) {
4394                                         int wret;
4395                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4396                                                                  DP_SINK_COUNT_ESI+1,
4397                                                                  &esi[1], 3);
4398                                         if (wret == 3) {
4399                                                 break;
4400                                         }
4401                                 }
4402
4403                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4404                                 if (bret == true) {
4405                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4406                                         goto go_again;
4407                                 }
4408                         } else
4409                                 ret = 0;
4410
4411                         return ret;
4412                 } else {
4413                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4414                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4415                         intel_dp->is_mst = false;
4416                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4417                         /* send a hotplug event */
4418                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4419                 }
4420         }
4421         return -EINVAL;
4422 }
4423
4424 /*
4425  * According to DP spec
4426  * 5.1.2:
4427  *  1. Read DPCD
4428  *  2. Configure link according to Receiver Capabilities
4429  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4430  *  4. Check link status on receipt of hot-plug interrupt
4431  */
4432 static void
4433 intel_dp_check_link_status(struct intel_dp *intel_dp)
4434 {
4435         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4436         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4437         u8 sink_irq_vector;
4438         u8 link_status[DP_LINK_STATUS_SIZE];
4439
4440         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4441
4442         if (!intel_encoder->base.crtc)
4443                 return;
4444
4445         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4446                 return;
4447
4448         /* Try to read receiver status if the link appears to be up */
4449         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4450                 return;
4451         }
4452
4453         /* Now read the DPCD to see if it's actually running */
4454         if (!intel_dp_get_dpcd(intel_dp)) {
4455                 return;
4456         }
4457
4458         /* Try to read the source of the interrupt */
4459         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4460             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4461                 /* Clear interrupt source */
4462                 drm_dp_dpcd_writeb(&intel_dp->aux,
4463                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4464                                    sink_irq_vector);
4465
4466                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4467                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4468                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4469                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4470         }
4471
4472         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4473                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4474                               intel_encoder->base.name);
4475                 intel_dp_start_link_train(intel_dp);
4476                 intel_dp_complete_link_train(intel_dp);
4477                 intel_dp_stop_link_train(intel_dp);
4478         }
4479 }
4480
4481 /* XXX this is probably wrong for multiple downstream ports */
4482 static enum drm_connector_status
4483 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4484 {
4485         uint8_t *dpcd = intel_dp->dpcd;
4486         uint8_t type;
4487
4488         if (!intel_dp_get_dpcd(intel_dp))
4489                 return connector_status_disconnected;
4490
4491         /* if there's no downstream port, we're done */
4492         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4493                 return connector_status_connected;
4494
4495         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4496         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4497             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4498                 uint8_t reg;
4499
4500                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4501                                             &reg, 1) < 0)
4502                         return connector_status_unknown;
4503
4504                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4505                                               : connector_status_disconnected;
4506         }
4507
4508         /* If no HPD, poke DDC gently */
4509         if (drm_probe_ddc(&intel_dp->aux.ddc))
4510                 return connector_status_connected;
4511
4512         /* Well we tried, say unknown for unreliable port types */
4513         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4514                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4515                 if (type == DP_DS_PORT_TYPE_VGA ||
4516                     type == DP_DS_PORT_TYPE_NON_EDID)
4517                         return connector_status_unknown;
4518         } else {
4519                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4520                         DP_DWN_STRM_PORT_TYPE_MASK;
4521                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4522                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4523                         return connector_status_unknown;
4524         }
4525
4526         /* Anything else is out of spec, warn and ignore */
4527         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4528         return connector_status_disconnected;
4529 }
4530
4531 static enum drm_connector_status
4532 edp_detect(struct intel_dp *intel_dp)
4533 {
4534         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4535         enum drm_connector_status status;
4536
4537         status = intel_panel_detect(dev);
4538         if (status == connector_status_unknown)
4539                 status = connector_status_connected;
4540
4541         return status;
4542 }
4543
4544 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4545                                        struct intel_digital_port *port)
4546 {
4547         u32 bit;
4548
4549         switch (port->port) {
4550         case PORT_A:
4551                 return true;
4552         case PORT_B:
4553                 bit = SDE_PORTB_HOTPLUG;
4554                 break;
4555         case PORT_C:
4556                 bit = SDE_PORTC_HOTPLUG;
4557                 break;
4558         case PORT_D:
4559                 bit = SDE_PORTD_HOTPLUG;
4560                 break;
4561         default:
4562                 MISSING_CASE(port->port);
4563                 return false;
4564         }
4565
4566         return I915_READ(SDEISR) & bit;
4567 }
4568
4569 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4570                                        struct intel_digital_port *port)
4571 {
4572         u32 bit;
4573
4574         switch (port->port) {
4575         case PORT_A:
4576                 return true;
4577         case PORT_B:
4578                 bit = SDE_PORTB_HOTPLUG_CPT;
4579                 break;
4580         case PORT_C:
4581                 bit = SDE_PORTC_HOTPLUG_CPT;
4582                 break;
4583         case PORT_D:
4584                 bit = SDE_PORTD_HOTPLUG_CPT;
4585                 break;
4586         case PORT_E:
4587                 bit = SDE_PORTE_HOTPLUG_SPT;
4588                 break;
4589         default:
4590                 MISSING_CASE(port->port);
4591                 return false;
4592         }
4593
4594         return I915_READ(SDEISR) & bit;
4595 }
4596
4597 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4598                                        struct intel_digital_port *port)
4599 {
4600         u32 bit;
4601
4602         switch (port->port) {
4603         case PORT_B:
4604                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4605                 break;
4606         case PORT_C:
4607                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4608                 break;
4609         case PORT_D:
4610                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4611                 break;
4612         default:
4613                 MISSING_CASE(port->port);
4614                 return false;
4615         }
4616
4617         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4618 }
4619
4620 static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4621                                        struct intel_digital_port *port)
4622 {
4623         u32 bit;
4624
4625         switch (port->port) {
4626         case PORT_B:
4627                 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4628                 break;
4629         case PORT_C:
4630                 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4631                 break;
4632         case PORT_D:
4633                 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4634                 break;
4635         default:
4636                 MISSING_CASE(port->port);
4637                 return false;
4638         }
4639
4640         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4641 }
4642
4643 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4644                                        struct intel_digital_port *intel_dig_port)
4645 {
4646         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4647         enum port port;
4648         u32 bit;
4649
4650         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4651         switch (port) {
4652         case PORT_A:
4653                 bit = BXT_DE_PORT_HP_DDIA;
4654                 break;
4655         case PORT_B:
4656                 bit = BXT_DE_PORT_HP_DDIB;
4657                 break;
4658         case PORT_C:
4659                 bit = BXT_DE_PORT_HP_DDIC;
4660                 break;
4661         default:
4662                 MISSING_CASE(port);
4663                 return false;
4664         }
4665
4666         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4667 }
4668
4669 /*
4670  * intel_digital_port_connected - is the specified port connected?
4671  * @dev_priv: i915 private structure
4672  * @port: the port to test
4673  *
4674  * Return %true if @port is connected, %false otherwise.
4675  */
4676 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4677                                          struct intel_digital_port *port)
4678 {
4679         if (HAS_PCH_IBX(dev_priv))
4680                 return ibx_digital_port_connected(dev_priv, port);
4681         if (HAS_PCH_SPLIT(dev_priv))
4682                 return cpt_digital_port_connected(dev_priv, port);
4683         else if (IS_BROXTON(dev_priv))
4684                 return bxt_digital_port_connected(dev_priv, port);
4685         else if (IS_VALLEYVIEW(dev_priv))
4686                 return vlv_digital_port_connected(dev_priv, port);
4687         else
4688                 return g4x_digital_port_connected(dev_priv, port);
4689 }
4690
4691 static enum drm_connector_status
4692 ironlake_dp_detect(struct intel_dp *intel_dp)
4693 {
4694         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4697
4698         if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4699                 return connector_status_disconnected;
4700
4701         return intel_dp_detect_dpcd(intel_dp);
4702 }
4703
4704 static enum drm_connector_status
4705 g4x_dp_detect(struct intel_dp *intel_dp)
4706 {
4707         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4708         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4709
4710         /* Can't disconnect eDP, but you can close the lid... */
4711         if (is_edp(intel_dp)) {
4712                 enum drm_connector_status status;
4713
4714                 status = intel_panel_detect(dev);
4715                 if (status == connector_status_unknown)
4716                         status = connector_status_connected;
4717                 return status;
4718         }
4719
4720         if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
4721                 return connector_status_disconnected;
4722
4723         return intel_dp_detect_dpcd(intel_dp);
4724 }
4725
4726 static struct edid *
4727 intel_dp_get_edid(struct intel_dp *intel_dp)
4728 {
4729         struct intel_connector *intel_connector = intel_dp->attached_connector;
4730
4731         /* use cached edid if we have one */
4732         if (intel_connector->edid) {
4733                 /* invalid edid */
4734                 if (IS_ERR(intel_connector->edid))
4735                         return NULL;
4736
4737                 return drm_edid_duplicate(intel_connector->edid);
4738         } else
4739                 return drm_get_edid(&intel_connector->base,
4740                                     &intel_dp->aux.ddc);
4741 }
4742
4743 static void
4744 intel_dp_set_edid(struct intel_dp *intel_dp)
4745 {
4746         struct intel_connector *intel_connector = intel_dp->attached_connector;
4747         struct edid *edid;
4748
4749         edid = intel_dp_get_edid(intel_dp);
4750         intel_connector->detect_edid = edid;
4751
4752         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4753                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4754         else
4755                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4756 }
4757
4758 static void
4759 intel_dp_unset_edid(struct intel_dp *intel_dp)
4760 {
4761         struct intel_connector *intel_connector = intel_dp->attached_connector;
4762
4763         kfree(intel_connector->detect_edid);
4764         intel_connector->detect_edid = NULL;
4765
4766         intel_dp->has_audio = false;
4767 }
4768
4769 static enum intel_display_power_domain
4770 intel_dp_power_get(struct intel_dp *dp)
4771 {
4772         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4773         enum intel_display_power_domain power_domain;
4774
4775         power_domain = intel_display_port_power_domain(encoder);
4776         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4777
4778         return power_domain;
4779 }
4780
4781 static void
4782 intel_dp_power_put(struct intel_dp *dp,
4783                    enum intel_display_power_domain power_domain)
4784 {
4785         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4786         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4787 }
4788
4789 static enum drm_connector_status
4790 intel_dp_detect(struct drm_connector *connector, bool force)
4791 {
4792         struct intel_dp *intel_dp = intel_attached_dp(connector);
4793         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4794         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4795         struct drm_device *dev = connector->dev;
4796         enum drm_connector_status status;
4797         enum intel_display_power_domain power_domain;
4798         bool ret;
4799         u8 sink_irq_vector;
4800
4801         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4802                       connector->base.id, connector->name);
4803         intel_dp_unset_edid(intel_dp);
4804
4805         if (intel_dp->is_mst) {
4806                 /* MST devices are disconnected from a monitor POV */
4807                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4808                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4809                 return connector_status_disconnected;
4810         }
4811
4812         power_domain = intel_dp_power_get(intel_dp);
4813
4814         /* Can't disconnect eDP, but you can close the lid... */
4815         if (is_edp(intel_dp))
4816                 status = edp_detect(intel_dp);
4817         else if (HAS_PCH_SPLIT(dev))
4818                 status = ironlake_dp_detect(intel_dp);
4819         else
4820                 status = g4x_dp_detect(intel_dp);
4821         if (status != connector_status_connected)
4822                 goto out;
4823
4824         intel_dp_probe_oui(intel_dp);
4825
4826         ret = intel_dp_probe_mst(intel_dp);
4827         if (ret) {
4828                 /* if we are in MST mode then this connector
4829                    won't appear connected or have anything with EDID on it */
4830                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4831                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4832                 status = connector_status_disconnected;
4833                 goto out;
4834         }
4835
4836         intel_dp_set_edid(intel_dp);
4837
4838         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4839                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4840         status = connector_status_connected;
4841
4842         /* Try to read the source of the interrupt */
4843         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4844             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4845                 /* Clear interrupt source */
4846                 drm_dp_dpcd_writeb(&intel_dp->aux,
4847                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4848                                    sink_irq_vector);
4849
4850                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4851                         intel_dp_handle_test_request(intel_dp);
4852                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4853                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4854         }
4855
4856 out:
4857         intel_dp_power_put(intel_dp, power_domain);
4858         return status;
4859 }
4860
4861 static void
4862 intel_dp_force(struct drm_connector *connector)
4863 {
4864         struct intel_dp *intel_dp = intel_attached_dp(connector);
4865         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4866         enum intel_display_power_domain power_domain;
4867
4868         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4869                       connector->base.id, connector->name);
4870         intel_dp_unset_edid(intel_dp);
4871
4872         if (connector->status != connector_status_connected)
4873                 return;
4874
4875         power_domain = intel_dp_power_get(intel_dp);
4876
4877         intel_dp_set_edid(intel_dp);
4878
4879         intel_dp_power_put(intel_dp, power_domain);
4880
4881         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4882                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4883 }
4884
4885 static int intel_dp_get_modes(struct drm_connector *connector)
4886 {
4887         struct intel_connector *intel_connector = to_intel_connector(connector);
4888         struct edid *edid;
4889
4890         edid = intel_connector->detect_edid;
4891         if (edid) {
4892                 int ret = intel_connector_update_modes(connector, edid);
4893                 if (ret)
4894                         return ret;
4895         }
4896
4897         /* if eDP has no EDID, fall back to fixed mode */
4898         if (is_edp(intel_attached_dp(connector)) &&
4899             intel_connector->panel.fixed_mode) {
4900                 struct drm_display_mode *mode;
4901
4902                 mode = drm_mode_duplicate(connector->dev,
4903                                           intel_connector->panel.fixed_mode);
4904                 if (mode) {
4905                         drm_mode_probed_add(connector, mode);
4906                         return 1;
4907                 }
4908         }
4909
4910         return 0;
4911 }
4912
4913 static bool
4914 intel_dp_detect_audio(struct drm_connector *connector)
4915 {
4916         bool has_audio = false;
4917         struct edid *edid;
4918
4919         edid = to_intel_connector(connector)->detect_edid;
4920         if (edid)
4921                 has_audio = drm_detect_monitor_audio(edid);
4922
4923         return has_audio;
4924 }
4925
4926 static int
4927 intel_dp_set_property(struct drm_connector *connector,
4928                       struct drm_property *property,
4929                       uint64_t val)
4930 {
4931         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4932         struct intel_connector *intel_connector = to_intel_connector(connector);
4933         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4934         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4935         int ret;
4936
4937         ret = drm_object_property_set_value(&connector->base, property, val);
4938         if (ret)
4939                 return ret;
4940
4941         if (property == dev_priv->force_audio_property) {
4942                 int i = val;
4943                 bool has_audio;
4944
4945                 if (i == intel_dp->force_audio)
4946                         return 0;
4947
4948                 intel_dp->force_audio = i;
4949
4950                 if (i == HDMI_AUDIO_AUTO)
4951                         has_audio = intel_dp_detect_audio(connector);
4952                 else
4953                         has_audio = (i == HDMI_AUDIO_ON);
4954
4955                 if (has_audio == intel_dp->has_audio)
4956                         return 0;
4957
4958                 intel_dp->has_audio = has_audio;
4959                 goto done;
4960         }
4961
4962         if (property == dev_priv->broadcast_rgb_property) {
4963                 bool old_auto = intel_dp->color_range_auto;
4964                 bool old_range = intel_dp->limited_color_range;
4965
4966                 switch (val) {
4967                 case INTEL_BROADCAST_RGB_AUTO:
4968                         intel_dp->color_range_auto = true;
4969                         break;
4970                 case INTEL_BROADCAST_RGB_FULL:
4971                         intel_dp->color_range_auto = false;
4972                         intel_dp->limited_color_range = false;
4973                         break;
4974                 case INTEL_BROADCAST_RGB_LIMITED:
4975                         intel_dp->color_range_auto = false;
4976                         intel_dp->limited_color_range = true;
4977                         break;
4978                 default:
4979                         return -EINVAL;
4980                 }
4981
4982                 if (old_auto == intel_dp->color_range_auto &&
4983                     old_range == intel_dp->limited_color_range)
4984                         return 0;
4985
4986                 goto done;
4987         }
4988
4989         if (is_edp(intel_dp) &&
4990             property == connector->dev->mode_config.scaling_mode_property) {
4991                 if (val == DRM_MODE_SCALE_NONE) {
4992                         DRM_DEBUG_KMS("no scaling not supported\n");
4993                         return -EINVAL;
4994                 }
4995
4996                 if (intel_connector->panel.fitting_mode == val) {
4997                         /* the eDP scaling property is not changed */
4998                         return 0;
4999                 }
5000                 intel_connector->panel.fitting_mode = val;
5001
5002                 goto done;
5003         }
5004
5005         return -EINVAL;
5006
5007 done:
5008         if (intel_encoder->base.crtc)
5009                 intel_crtc_restore_mode(intel_encoder->base.crtc);
5010
5011         return 0;
5012 }
5013
5014 static void
5015 intel_dp_connector_destroy(struct drm_connector *connector)
5016 {
5017         struct intel_connector *intel_connector = to_intel_connector(connector);
5018
5019         kfree(intel_connector->detect_edid);
5020
5021         if (!IS_ERR_OR_NULL(intel_connector->edid))
5022                 kfree(intel_connector->edid);
5023
5024         /* Can't call is_edp() since the encoder may have been destroyed
5025          * already. */
5026         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5027                 intel_panel_fini(&intel_connector->panel);
5028
5029         drm_connector_cleanup(connector);
5030         kfree(connector);
5031 }
5032
5033 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5034 {
5035         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5036         struct intel_dp *intel_dp = &intel_dig_port->dp;
5037
5038         drm_dp_aux_unregister(&intel_dp->aux);
5039         intel_dp_mst_encoder_cleanup(intel_dig_port);
5040         if (is_edp(intel_dp)) {
5041                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5042                 /*
5043                  * vdd might still be enabled do to the delayed vdd off.
5044                  * Make sure vdd is actually turned off here.
5045                  */
5046                 pps_lock(intel_dp);
5047                 edp_panel_vdd_off_sync(intel_dp);
5048                 pps_unlock(intel_dp);
5049
5050                 if (intel_dp->edp_notifier.notifier_call) {
5051                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5052                         intel_dp->edp_notifier.notifier_call = NULL;
5053                 }
5054         }
5055         drm_encoder_cleanup(encoder);
5056         kfree(intel_dig_port);
5057 }
5058
5059 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5060 {
5061         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5062
5063         if (!is_edp(intel_dp))
5064                 return;
5065
5066         /*
5067          * vdd might still be enabled do to the delayed vdd off.
5068          * Make sure vdd is actually turned off here.
5069          */
5070         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5071         pps_lock(intel_dp);
5072         edp_panel_vdd_off_sync(intel_dp);
5073         pps_unlock(intel_dp);
5074 }
5075
5076 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5077 {
5078         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5079         struct drm_device *dev = intel_dig_port->base.base.dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         enum intel_display_power_domain power_domain;
5082
5083         lockdep_assert_held(&dev_priv->pps_mutex);
5084
5085         if (!edp_have_panel_vdd(intel_dp))
5086                 return;
5087
5088         /*
5089          * The VDD bit needs a power domain reference, so if the bit is
5090          * already enabled when we boot or resume, grab this reference and
5091          * schedule a vdd off, so we don't hold on to the reference
5092          * indefinitely.
5093          */
5094         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5095         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
5096         intel_display_power_get(dev_priv, power_domain);
5097
5098         edp_panel_vdd_schedule_off(intel_dp);
5099 }
5100
5101 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
5102 {
5103         struct intel_dp *intel_dp;
5104
5105         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
5106                 return;
5107
5108         intel_dp = enc_to_intel_dp(encoder);
5109
5110         pps_lock(intel_dp);
5111
5112         /*
5113          * Read out the current power sequencer assignment,
5114          * in case the BIOS did something with it.
5115          */
5116         if (IS_VALLEYVIEW(encoder->dev))
5117                 vlv_initial_power_sequencer_setup(intel_dp);
5118
5119         intel_edp_panel_vdd_sanitize(intel_dp);
5120
5121         pps_unlock(intel_dp);
5122 }
5123
5124 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5125         .dpms = drm_atomic_helper_connector_dpms,
5126         .detect = intel_dp_detect,
5127         .force = intel_dp_force,
5128         .fill_modes = drm_helper_probe_single_connector_modes,
5129         .set_property = intel_dp_set_property,
5130         .atomic_get_property = intel_connector_atomic_get_property,
5131         .destroy = intel_dp_connector_destroy,
5132         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5133         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5134 };
5135
5136 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5137         .get_modes = intel_dp_get_modes,
5138         .mode_valid = intel_dp_mode_valid,
5139         .best_encoder = intel_best_encoder,
5140 };
5141
5142 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5143         .reset = intel_dp_encoder_reset,
5144         .destroy = intel_dp_encoder_destroy,
5145 };
5146
5147 enum irqreturn
5148 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5149 {
5150         struct intel_dp *intel_dp = &intel_dig_port->dp;
5151         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5152         struct drm_device *dev = intel_dig_port->base.base.dev;
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         enum intel_display_power_domain power_domain;
5155         enum irqreturn ret = IRQ_NONE;
5156
5157         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
5158                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
5159
5160         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5161                 /*
5162                  * vdd off can generate a long pulse on eDP which
5163                  * would require vdd on to handle it, and thus we
5164                  * would end up in an endless cycle of
5165                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5166                  */
5167                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5168                               port_name(intel_dig_port->port));
5169                 return IRQ_HANDLED;
5170         }
5171
5172         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5173                       port_name(intel_dig_port->port),
5174                       long_hpd ? "long" : "short");
5175
5176         power_domain = intel_display_port_power_domain(intel_encoder);
5177         intel_display_power_get(dev_priv, power_domain);
5178
5179         if (long_hpd) {
5180                 /* indicate that we need to restart link training */
5181                 intel_dp->train_set_valid = false;
5182
5183                 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5184                         goto mst_fail;
5185
5186                 if (!intel_dp_get_dpcd(intel_dp)) {
5187                         goto mst_fail;
5188                 }
5189
5190                 intel_dp_probe_oui(intel_dp);
5191
5192                 if (!intel_dp_probe_mst(intel_dp)) {
5193                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5194                         intel_dp_check_link_status(intel_dp);
5195                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5196                         goto mst_fail;
5197                 }
5198         } else {
5199                 if (intel_dp->is_mst) {
5200                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5201                                 goto mst_fail;
5202                 }
5203
5204                 if (!intel_dp->is_mst) {
5205                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5206                         intel_dp_check_link_status(intel_dp);
5207                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5208                 }
5209         }
5210
5211         ret = IRQ_HANDLED;
5212
5213         goto put_power;
5214 mst_fail:
5215         /* if we were in MST mode, and device is not there get out of MST mode */
5216         if (intel_dp->is_mst) {
5217                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5218                 intel_dp->is_mst = false;
5219                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5220         }
5221 put_power:
5222         intel_display_power_put(dev_priv, power_domain);
5223
5224         return ret;
5225 }
5226
5227 /* Return which DP Port should be selected for Transcoder DP control */
5228 int
5229 intel_trans_dp_port_sel(struct drm_crtc *crtc)
5230 {
5231         struct drm_device *dev = crtc->dev;
5232         struct intel_encoder *intel_encoder;
5233         struct intel_dp *intel_dp;
5234
5235         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5236                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
5237
5238                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
5239                     intel_encoder->type == INTEL_OUTPUT_EDP)
5240                         return intel_dp->output_reg;
5241         }
5242
5243         return -1;
5244 }
5245
5246 /* check the VBT to see whether the eDP is on another port */
5247 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5248 {
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250         union child_device_config *p_child;
5251         int i;
5252         static const short port_mapping[] = {
5253                 [PORT_B] = DVO_PORT_DPB,
5254                 [PORT_C] = DVO_PORT_DPC,
5255                 [PORT_D] = DVO_PORT_DPD,
5256                 [PORT_E] = DVO_PORT_DPE,
5257         };
5258
5259         /*
5260          * eDP not supported on g4x. so bail out early just
5261          * for a bit extra safety in case the VBT is bonkers.
5262          */
5263         if (INTEL_INFO(dev)->gen < 5)
5264                 return false;
5265
5266         if (port == PORT_A)
5267                 return true;
5268
5269         if (!dev_priv->vbt.child_dev_num)
5270                 return false;
5271
5272         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5273                 p_child = dev_priv->vbt.child_dev + i;
5274
5275                 if (p_child->common.dvo_port == port_mapping[port] &&
5276                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5277                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5278                         return true;
5279         }
5280         return false;
5281 }
5282
5283 void
5284 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5285 {
5286         struct intel_connector *intel_connector = to_intel_connector(connector);
5287
5288         intel_attach_force_audio_property(connector);
5289         intel_attach_broadcast_rgb_property(connector);
5290         intel_dp->color_range_auto = true;
5291
5292         if (is_edp(intel_dp)) {
5293                 drm_mode_create_scaling_mode_property(connector->dev);
5294                 drm_object_attach_property(
5295                         &connector->base,
5296                         connector->dev->mode_config.scaling_mode_property,
5297                         DRM_MODE_SCALE_ASPECT);
5298                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5299         }
5300 }
5301
5302 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5303 {
5304         intel_dp->last_power_cycle = jiffies;
5305         intel_dp->last_power_on = jiffies;
5306         intel_dp->last_backlight_off = jiffies;
5307 }
5308
5309 static void
5310 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5311                                     struct intel_dp *intel_dp)
5312 {
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct edp_power_seq cur, vbt, spec,
5315                 *final = &intel_dp->pps_delays;
5316         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5317         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
5318
5319         lockdep_assert_held(&dev_priv->pps_mutex);
5320
5321         /* already initialized? */
5322         if (final->t11_t12 != 0)
5323                 return;
5324
5325         if (IS_BROXTON(dev)) {
5326                 /*
5327                  * TODO: BXT has 2 sets of PPS registers.
5328                  * Correct Register for Broxton need to be identified
5329                  * using VBT. hardcoding for now
5330                  */
5331                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5332                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5333                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5334         } else if (HAS_PCH_SPLIT(dev)) {
5335                 pp_ctrl_reg = PCH_PP_CONTROL;
5336                 pp_on_reg = PCH_PP_ON_DELAYS;
5337                 pp_off_reg = PCH_PP_OFF_DELAYS;
5338                 pp_div_reg = PCH_PP_DIVISOR;
5339         } else {
5340                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5341
5342                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5343                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5344                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5345                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5346         }
5347
5348         /* Workaround: Need to write PP_CONTROL with the unlock key as
5349          * the very first thing. */
5350         pp_ctl = ironlake_get_pp_control(intel_dp);
5351
5352         pp_on = I915_READ(pp_on_reg);
5353         pp_off = I915_READ(pp_off_reg);
5354         if (!IS_BROXTON(dev)) {
5355                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5356                 pp_div = I915_READ(pp_div_reg);
5357         }
5358
5359         /* Pull timing values out of registers */
5360         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5361                 PANEL_POWER_UP_DELAY_SHIFT;
5362
5363         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5364                 PANEL_LIGHT_ON_DELAY_SHIFT;
5365
5366         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5367                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5368
5369         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5370                 PANEL_POWER_DOWN_DELAY_SHIFT;
5371
5372         if (IS_BROXTON(dev)) {
5373                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5374                         BXT_POWER_CYCLE_DELAY_SHIFT;
5375                 if (tmp > 0)
5376                         cur.t11_t12 = (tmp - 1) * 1000;
5377                 else
5378                         cur.t11_t12 = 0;
5379         } else {
5380                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5381                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5382         }
5383
5384         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5385                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5386
5387         vbt = dev_priv->vbt.edp_pps;
5388
5389         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5390          * our hw here, which are all in 100usec. */
5391         spec.t1_t3 = 210 * 10;
5392         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5393         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5394         spec.t10 = 500 * 10;
5395         /* This one is special and actually in units of 100ms, but zero
5396          * based in the hw (so we need to add 100 ms). But the sw vbt
5397          * table multiplies it with 1000 to make it in units of 100usec,
5398          * too. */
5399         spec.t11_t12 = (510 + 100) * 10;
5400
5401         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5402                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5403
5404         /* Use the max of the register settings and vbt. If both are
5405          * unset, fall back to the spec limits. */
5406 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5407                                        spec.field : \
5408                                        max(cur.field, vbt.field))
5409         assign_final(t1_t3);
5410         assign_final(t8);
5411         assign_final(t9);
5412         assign_final(t10);
5413         assign_final(t11_t12);
5414 #undef assign_final
5415
5416 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5417         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5418         intel_dp->backlight_on_delay = get_delay(t8);
5419         intel_dp->backlight_off_delay = get_delay(t9);
5420         intel_dp->panel_power_down_delay = get_delay(t10);
5421         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5422 #undef get_delay
5423
5424         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5425                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5426                       intel_dp->panel_power_cycle_delay);
5427
5428         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5429                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5430 }
5431
5432 static void
5433 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5434                                               struct intel_dp *intel_dp)
5435 {
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437         u32 pp_on, pp_off, pp_div, port_sel = 0;
5438         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5439         int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
5440         enum port port = dp_to_dig_port(intel_dp)->port;
5441         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5442
5443         lockdep_assert_held(&dev_priv->pps_mutex);
5444
5445         if (IS_BROXTON(dev)) {
5446                 /*
5447                  * TODO: BXT has 2 sets of PPS registers.
5448                  * Correct Register for Broxton need to be identified
5449                  * using VBT. hardcoding for now
5450                  */
5451                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5452                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5453                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5454
5455         } else if (HAS_PCH_SPLIT(dev)) {
5456                 pp_on_reg = PCH_PP_ON_DELAYS;
5457                 pp_off_reg = PCH_PP_OFF_DELAYS;
5458                 pp_div_reg = PCH_PP_DIVISOR;
5459         } else {
5460                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5461
5462                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5463                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5464                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5465         }
5466
5467         /*
5468          * And finally store the new values in the power sequencer. The
5469          * backlight delays are set to 1 because we do manual waits on them. For
5470          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5471          * we'll end up waiting for the backlight off delay twice: once when we
5472          * do the manual sleep, and once when we disable the panel and wait for
5473          * the PP_STATUS bit to become zero.
5474          */
5475         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5476                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5477         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5478                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5479         /* Compute the divisor for the pp clock, simply match the Bspec
5480          * formula. */
5481         if (IS_BROXTON(dev)) {
5482                 pp_div = I915_READ(pp_ctrl_reg);
5483                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5484                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5485                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5486         } else {
5487                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5488                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5489                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5490         }
5491
5492         /* Haswell doesn't have any port selection bits for the panel
5493          * power sequencer any more. */
5494         if (IS_VALLEYVIEW(dev)) {
5495                 port_sel = PANEL_PORT_SELECT_VLV(port);
5496         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5497                 if (port == PORT_A)
5498                         port_sel = PANEL_PORT_SELECT_DPA;
5499                 else
5500                         port_sel = PANEL_PORT_SELECT_DPD;
5501         }
5502
5503         pp_on |= port_sel;
5504
5505         I915_WRITE(pp_on_reg, pp_on);
5506         I915_WRITE(pp_off_reg, pp_off);
5507         if (IS_BROXTON(dev))
5508                 I915_WRITE(pp_ctrl_reg, pp_div);
5509         else
5510                 I915_WRITE(pp_div_reg, pp_div);
5511
5512         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5513                       I915_READ(pp_on_reg),
5514                       I915_READ(pp_off_reg),
5515                       IS_BROXTON(dev) ?
5516                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5517                       I915_READ(pp_div_reg));
5518 }
5519
5520 /**
5521  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5522  * @dev: DRM device
5523  * @refresh_rate: RR to be programmed
5524  *
5525  * This function gets called when refresh rate (RR) has to be changed from
5526  * one frequency to another. Switches can be between high and low RR
5527  * supported by the panel or to any other RR based on media playback (in
5528  * this case, RR value needs to be passed from user space).
5529  *
5530  * The caller of this function needs to take a lock on dev_priv->drrs.
5531  */
5532 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5533 {
5534         struct drm_i915_private *dev_priv = dev->dev_private;
5535         struct intel_encoder *encoder;
5536         struct intel_digital_port *dig_port = NULL;
5537         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5538         struct intel_crtc_state *config = NULL;
5539         struct intel_crtc *intel_crtc = NULL;
5540         u32 reg, val;
5541         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5542
5543         if (refresh_rate <= 0) {
5544                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5545                 return;
5546         }
5547
5548         if (intel_dp == NULL) {
5549                 DRM_DEBUG_KMS("DRRS not supported.\n");
5550                 return;
5551         }
5552
5553         /*
5554          * FIXME: This needs proper synchronization with psr state for some
5555          * platforms that cannot have PSR and DRRS enabled at the same time.
5556          */
5557
5558         dig_port = dp_to_dig_port(intel_dp);
5559         encoder = &dig_port->base;
5560         intel_crtc = to_intel_crtc(encoder->base.crtc);
5561
5562         if (!intel_crtc) {
5563                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5564                 return;
5565         }
5566
5567         config = intel_crtc->config;
5568
5569         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5570                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5571                 return;
5572         }
5573
5574         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5575                         refresh_rate)
5576                 index = DRRS_LOW_RR;
5577
5578         if (index == dev_priv->drrs.refresh_rate_type) {
5579                 DRM_DEBUG_KMS(
5580                         "DRRS requested for previously set RR...ignoring\n");
5581                 return;
5582         }
5583
5584         if (!intel_crtc->active) {
5585                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5586                 return;
5587         }
5588
5589         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5590                 switch (index) {
5591                 case DRRS_HIGH_RR:
5592                         intel_dp_set_m_n(intel_crtc, M1_N1);
5593                         break;
5594                 case DRRS_LOW_RR:
5595                         intel_dp_set_m_n(intel_crtc, M2_N2);
5596                         break;
5597                 case DRRS_MAX_RR:
5598                 default:
5599                         DRM_ERROR("Unsupported refreshrate type\n");
5600                 }
5601         } else if (INTEL_INFO(dev)->gen > 6) {
5602                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5603                 val = I915_READ(reg);
5604
5605                 if (index > DRRS_HIGH_RR) {
5606                         if (IS_VALLEYVIEW(dev))
5607                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5608                         else
5609                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5610                 } else {
5611                         if (IS_VALLEYVIEW(dev))
5612                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5613                         else
5614                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5615                 }
5616                 I915_WRITE(reg, val);
5617         }
5618
5619         dev_priv->drrs.refresh_rate_type = index;
5620
5621         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5622 }
5623
5624 /**
5625  * intel_edp_drrs_enable - init drrs struct if supported
5626  * @intel_dp: DP struct
5627  *
5628  * Initializes frontbuffer_bits and drrs.dp
5629  */
5630 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5631 {
5632         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5633         struct drm_i915_private *dev_priv = dev->dev_private;
5634         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5635         struct drm_crtc *crtc = dig_port->base.base.crtc;
5636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5637
5638         if (!intel_crtc->config->has_drrs) {
5639                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5640                 return;
5641         }
5642
5643         mutex_lock(&dev_priv->drrs.mutex);
5644         if (WARN_ON(dev_priv->drrs.dp)) {
5645                 DRM_ERROR("DRRS already enabled\n");
5646                 goto unlock;
5647         }
5648
5649         dev_priv->drrs.busy_frontbuffer_bits = 0;
5650
5651         dev_priv->drrs.dp = intel_dp;
5652
5653 unlock:
5654         mutex_unlock(&dev_priv->drrs.mutex);
5655 }
5656
5657 /**
5658  * intel_edp_drrs_disable - Disable DRRS
5659  * @intel_dp: DP struct
5660  *
5661  */
5662 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5663 {
5664         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5665         struct drm_i915_private *dev_priv = dev->dev_private;
5666         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5667         struct drm_crtc *crtc = dig_port->base.base.crtc;
5668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5669
5670         if (!intel_crtc->config->has_drrs)
5671                 return;
5672
5673         mutex_lock(&dev_priv->drrs.mutex);
5674         if (!dev_priv->drrs.dp) {
5675                 mutex_unlock(&dev_priv->drrs.mutex);
5676                 return;
5677         }
5678
5679         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5680                 intel_dp_set_drrs_state(dev_priv->dev,
5681                         intel_dp->attached_connector->panel.
5682                         fixed_mode->vrefresh);
5683
5684         dev_priv->drrs.dp = NULL;
5685         mutex_unlock(&dev_priv->drrs.mutex);
5686
5687         cancel_delayed_work_sync(&dev_priv->drrs.work);
5688 }
5689
5690 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5691 {
5692         struct drm_i915_private *dev_priv =
5693                 container_of(work, typeof(*dev_priv), drrs.work.work);
5694         struct intel_dp *intel_dp;
5695
5696         mutex_lock(&dev_priv->drrs.mutex);
5697
5698         intel_dp = dev_priv->drrs.dp;
5699
5700         if (!intel_dp)
5701                 goto unlock;
5702
5703         /*
5704          * The delayed work can race with an invalidate hence we need to
5705          * recheck.
5706          */
5707
5708         if (dev_priv->drrs.busy_frontbuffer_bits)
5709                 goto unlock;
5710
5711         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5712                 intel_dp_set_drrs_state(dev_priv->dev,
5713                         intel_dp->attached_connector->panel.
5714                         downclock_mode->vrefresh);
5715
5716 unlock:
5717         mutex_unlock(&dev_priv->drrs.mutex);
5718 }
5719
5720 /**
5721  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5722  * @dev: DRM device
5723  * @frontbuffer_bits: frontbuffer plane tracking bits
5724  *
5725  * This function gets called everytime rendering on the given planes start.
5726  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5727  *
5728  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5729  */
5730 void intel_edp_drrs_invalidate(struct drm_device *dev,
5731                 unsigned frontbuffer_bits)
5732 {
5733         struct drm_i915_private *dev_priv = dev->dev_private;
5734         struct drm_crtc *crtc;
5735         enum pipe pipe;
5736
5737         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5738                 return;
5739
5740         cancel_delayed_work(&dev_priv->drrs.work);
5741
5742         mutex_lock(&dev_priv->drrs.mutex);
5743         if (!dev_priv->drrs.dp) {
5744                 mutex_unlock(&dev_priv->drrs.mutex);
5745                 return;
5746         }
5747
5748         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5749         pipe = to_intel_crtc(crtc)->pipe;
5750
5751         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5752         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5753
5754         /* invalidate means busy screen hence upclock */
5755         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5756                 intel_dp_set_drrs_state(dev_priv->dev,
5757                                 dev_priv->drrs.dp->attached_connector->panel.
5758                                 fixed_mode->vrefresh);
5759
5760         mutex_unlock(&dev_priv->drrs.mutex);
5761 }
5762
5763 /**
5764  * intel_edp_drrs_flush - Restart Idleness DRRS
5765  * @dev: DRM device
5766  * @frontbuffer_bits: frontbuffer plane tracking bits
5767  *
5768  * This function gets called every time rendering on the given planes has
5769  * completed or flip on a crtc is completed. So DRRS should be upclocked
5770  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5771  * if no other planes are dirty.
5772  *
5773  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5774  */
5775 void intel_edp_drrs_flush(struct drm_device *dev,
5776                 unsigned frontbuffer_bits)
5777 {
5778         struct drm_i915_private *dev_priv = dev->dev_private;
5779         struct drm_crtc *crtc;
5780         enum pipe pipe;
5781
5782         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5783                 return;
5784
5785         cancel_delayed_work(&dev_priv->drrs.work);
5786
5787         mutex_lock(&dev_priv->drrs.mutex);
5788         if (!dev_priv->drrs.dp) {
5789                 mutex_unlock(&dev_priv->drrs.mutex);
5790                 return;
5791         }
5792
5793         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5794         pipe = to_intel_crtc(crtc)->pipe;
5795
5796         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5797         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5798
5799         /* flush means busy screen hence upclock */
5800         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5801                 intel_dp_set_drrs_state(dev_priv->dev,
5802                                 dev_priv->drrs.dp->attached_connector->panel.
5803                                 fixed_mode->vrefresh);
5804
5805         /*
5806          * flush also means no more activity hence schedule downclock, if all
5807          * other fbs are quiescent too
5808          */
5809         if (!dev_priv->drrs.busy_frontbuffer_bits)
5810                 schedule_delayed_work(&dev_priv->drrs.work,
5811                                 msecs_to_jiffies(1000));
5812         mutex_unlock(&dev_priv->drrs.mutex);
5813 }
5814
5815 /**
5816  * DOC: Display Refresh Rate Switching (DRRS)
5817  *
5818  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5819  * which enables swtching between low and high refresh rates,
5820  * dynamically, based on the usage scenario. This feature is applicable
5821  * for internal panels.
5822  *
5823  * Indication that the panel supports DRRS is given by the panel EDID, which
5824  * would list multiple refresh rates for one resolution.
5825  *
5826  * DRRS is of 2 types - static and seamless.
5827  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5828  * (may appear as a blink on screen) and is used in dock-undock scenario.
5829  * Seamless DRRS involves changing RR without any visual effect to the user
5830  * and can be used during normal system usage. This is done by programming
5831  * certain registers.
5832  *
5833  * Support for static/seamless DRRS may be indicated in the VBT based on
5834  * inputs from the panel spec.
5835  *
5836  * DRRS saves power by switching to low RR based on usage scenarios.
5837  *
5838  * eDP DRRS:-
5839  *        The implementation is based on frontbuffer tracking implementation.
5840  * When there is a disturbance on the screen triggered by user activity or a
5841  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5842  * When there is no movement on screen, after a timeout of 1 second, a switch
5843  * to low RR is made.
5844  *        For integration with frontbuffer tracking code,
5845  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5846  *
5847  * DRRS can be further extended to support other internal panels and also
5848  * the scenario of video playback wherein RR is set based on the rate
5849  * requested by userspace.
5850  */
5851
5852 /**
5853  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5854  * @intel_connector: eDP connector
5855  * @fixed_mode: preferred mode of panel
5856  *
5857  * This function is  called only once at driver load to initialize basic
5858  * DRRS stuff.
5859  *
5860  * Returns:
5861  * Downclock mode if panel supports it, else return NULL.
5862  * DRRS support is determined by the presence of downclock mode (apart
5863  * from VBT setting).
5864  */
5865 static struct drm_display_mode *
5866 intel_dp_drrs_init(struct intel_connector *intel_connector,
5867                 struct drm_display_mode *fixed_mode)
5868 {
5869         struct drm_connector *connector = &intel_connector->base;
5870         struct drm_device *dev = connector->dev;
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872         struct drm_display_mode *downclock_mode = NULL;
5873
5874         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5875         mutex_init(&dev_priv->drrs.mutex);
5876
5877         if (INTEL_INFO(dev)->gen <= 6) {
5878                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5879                 return NULL;
5880         }
5881
5882         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5883                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5884                 return NULL;
5885         }
5886
5887         downclock_mode = intel_find_panel_downclock
5888                                         (dev, fixed_mode, connector);
5889
5890         if (!downclock_mode) {
5891                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5892                 return NULL;
5893         }
5894
5895         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5896
5897         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5898         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5899         return downclock_mode;
5900 }
5901
5902 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5903                                      struct intel_connector *intel_connector)
5904 {
5905         struct drm_connector *connector = &intel_connector->base;
5906         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5907         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5908         struct drm_device *dev = intel_encoder->base.dev;
5909         struct drm_i915_private *dev_priv = dev->dev_private;
5910         struct drm_display_mode *fixed_mode = NULL;
5911         struct drm_display_mode *downclock_mode = NULL;
5912         bool has_dpcd;
5913         struct drm_display_mode *scan;
5914         struct edid *edid;
5915         enum pipe pipe = INVALID_PIPE;
5916
5917         if (!is_edp(intel_dp))
5918                 return true;
5919
5920         pps_lock(intel_dp);
5921         intel_edp_panel_vdd_sanitize(intel_dp);
5922         pps_unlock(intel_dp);
5923
5924         /* Cache DPCD and EDID for edp. */
5925         has_dpcd = intel_dp_get_dpcd(intel_dp);
5926
5927         if (has_dpcd) {
5928                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5929                         dev_priv->no_aux_handshake =
5930                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5931                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5932         } else {
5933                 /* if this fails, presume the device is a ghost */
5934                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5935                 return false;
5936         }
5937
5938         /* We now know it's not a ghost, init power sequence regs. */
5939         pps_lock(intel_dp);
5940         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5941         pps_unlock(intel_dp);
5942
5943         mutex_lock(&dev->mode_config.mutex);
5944         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5945         if (edid) {
5946                 if (drm_add_edid_modes(connector, edid)) {
5947                         drm_mode_connector_update_edid_property(connector,
5948                                                                 edid);
5949                         drm_edid_to_eld(connector, edid);
5950                 } else {
5951                         kfree(edid);
5952                         edid = ERR_PTR(-EINVAL);
5953                 }
5954         } else {
5955                 edid = ERR_PTR(-ENOENT);
5956         }
5957         intel_connector->edid = edid;
5958
5959         /* prefer fixed mode from EDID if available */
5960         list_for_each_entry(scan, &connector->probed_modes, head) {
5961                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5962                         fixed_mode = drm_mode_duplicate(dev, scan);
5963                         downclock_mode = intel_dp_drrs_init(
5964                                                 intel_connector, fixed_mode);
5965                         break;
5966                 }
5967         }
5968
5969         /* fallback to VBT if available for eDP */
5970         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5971                 fixed_mode = drm_mode_duplicate(dev,
5972                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5973                 if (fixed_mode)
5974                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5975         }
5976         mutex_unlock(&dev->mode_config.mutex);
5977
5978         if (IS_VALLEYVIEW(dev)) {
5979                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5980                 register_reboot_notifier(&intel_dp->edp_notifier);
5981
5982                 /*
5983                  * Figure out the current pipe for the initial backlight setup.
5984                  * If the current pipe isn't valid, try the PPS pipe, and if that
5985                  * fails just assume pipe A.
5986                  */
5987                 if (IS_CHERRYVIEW(dev))
5988                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5989                 else
5990                         pipe = PORT_TO_PIPE(intel_dp->DP);
5991
5992                 if (pipe != PIPE_A && pipe != PIPE_B)
5993                         pipe = intel_dp->pps_pipe;
5994
5995                 if (pipe != PIPE_A && pipe != PIPE_B)
5996                         pipe = PIPE_A;
5997
5998                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5999                               pipe_name(pipe));
6000         }
6001
6002         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6003         intel_connector->panel.backlight_power = intel_edp_backlight_power;
6004         intel_panel_setup_backlight(connector, pipe);
6005
6006         return true;
6007 }
6008
6009 bool
6010 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6011                         struct intel_connector *intel_connector)
6012 {
6013         struct drm_connector *connector = &intel_connector->base;
6014         struct intel_dp *intel_dp = &intel_dig_port->dp;
6015         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6016         struct drm_device *dev = intel_encoder->base.dev;
6017         struct drm_i915_private *dev_priv = dev->dev_private;
6018         enum port port = intel_dig_port->port;
6019         int type;
6020
6021         intel_dp->pps_pipe = INVALID_PIPE;
6022
6023         /* intel_dp vfuncs */
6024         if (INTEL_INFO(dev)->gen >= 9)
6025                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6026         else if (IS_VALLEYVIEW(dev))
6027                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
6028         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
6029                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6030         else if (HAS_PCH_SPLIT(dev))
6031                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6032         else
6033                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
6034
6035         if (INTEL_INFO(dev)->gen >= 9)
6036                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6037         else
6038                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
6039
6040         /* Preserve the current hw state. */
6041         intel_dp->DP = I915_READ(intel_dp->output_reg);
6042         intel_dp->attached_connector = intel_connector;
6043
6044         if (intel_dp_is_edp(dev, port))
6045                 type = DRM_MODE_CONNECTOR_eDP;
6046         else
6047                 type = DRM_MODE_CONNECTOR_DisplayPort;
6048
6049         /*
6050          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6051          * for DP the encoder type can be set by the caller to
6052          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6053          */
6054         if (type == DRM_MODE_CONNECTOR_eDP)
6055                 intel_encoder->type = INTEL_OUTPUT_EDP;
6056
6057         /* eDP only on port B and/or C on vlv/chv */
6058         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
6059                     port != PORT_B && port != PORT_C))
6060                 return false;
6061
6062         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6063                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6064                         port_name(port));
6065
6066         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6067         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6068
6069         connector->interlace_allowed = true;
6070         connector->doublescan_allowed = 0;
6071
6072         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6073                           edp_panel_vdd_work);
6074
6075         intel_connector_attach_encoder(intel_connector, intel_encoder);
6076         drm_connector_register(connector);
6077
6078         if (HAS_DDI(dev))
6079                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6080         else
6081                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6082         intel_connector->unregister = intel_dp_connector_unregister;
6083
6084         /* Set up the hotplug pin. */
6085         switch (port) {
6086         case PORT_A:
6087                 intel_encoder->hpd_pin = HPD_PORT_A;
6088                 break;
6089         case PORT_B:
6090                 intel_encoder->hpd_pin = HPD_PORT_B;
6091                 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
6092                         intel_encoder->hpd_pin = HPD_PORT_A;
6093                 break;
6094         case PORT_C:
6095                 intel_encoder->hpd_pin = HPD_PORT_C;
6096                 break;
6097         case PORT_D:
6098                 intel_encoder->hpd_pin = HPD_PORT_D;
6099                 break;
6100         case PORT_E:
6101                 intel_encoder->hpd_pin = HPD_PORT_E;
6102                 break;
6103         default:
6104                 BUG();
6105         }
6106
6107         if (is_edp(intel_dp)) {
6108                 pps_lock(intel_dp);
6109                 intel_dp_init_panel_power_timestamps(intel_dp);
6110                 if (IS_VALLEYVIEW(dev))
6111                         vlv_initial_power_sequencer_setup(intel_dp);
6112                 else
6113                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
6114                 pps_unlock(intel_dp);
6115         }
6116
6117         intel_dp_aux_init(intel_dp, intel_connector);
6118
6119         /* init MST on ports that can support it */
6120         if (HAS_DP_MST(dev) &&
6121             (port == PORT_B || port == PORT_C || port == PORT_D))
6122                 intel_dp_mst_encoder_init(intel_dig_port,
6123                                           intel_connector->base.base.id);
6124
6125         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6126                 drm_dp_aux_unregister(&intel_dp->aux);
6127                 if (is_edp(intel_dp)) {
6128                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6129                         /*
6130                          * vdd might still be enabled do to the delayed vdd off.
6131                          * Make sure vdd is actually turned off here.
6132                          */
6133                         pps_lock(intel_dp);
6134                         edp_panel_vdd_off_sync(intel_dp);
6135                         pps_unlock(intel_dp);
6136                 }
6137                 drm_connector_unregister(connector);
6138                 drm_connector_cleanup(connector);
6139                 return false;
6140         }
6141
6142         intel_dp_add_properties(intel_dp, connector);
6143
6144         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6145          * 0xd.  Failure to do so will result in spurious interrupts being
6146          * generated on the port when a cable is not attached.
6147          */
6148         if (IS_G4X(dev) && !IS_GM45(dev)) {
6149                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6150                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6151         }
6152
6153         i915_debugfs_connector_add(connector);
6154
6155         return true;
6156 }
6157
6158 void
6159 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
6160 {
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162         struct intel_digital_port *intel_dig_port;
6163         struct intel_encoder *intel_encoder;
6164         struct drm_encoder *encoder;
6165         struct intel_connector *intel_connector;
6166
6167         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6168         if (!intel_dig_port)
6169                 return;
6170
6171         intel_connector = intel_connector_alloc();
6172         if (!intel_connector) {
6173                 kfree(intel_dig_port);
6174                 return;
6175         }
6176
6177         intel_encoder = &intel_dig_port->base;
6178         encoder = &intel_encoder->base;
6179
6180         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
6181                          DRM_MODE_ENCODER_TMDS);
6182
6183         intel_encoder->compute_config = intel_dp_compute_config;
6184         intel_encoder->disable = intel_disable_dp;
6185         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6186         intel_encoder->get_config = intel_dp_get_config;
6187         intel_encoder->suspend = intel_dp_encoder_suspend;
6188         if (IS_CHERRYVIEW(dev)) {
6189                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6190                 intel_encoder->pre_enable = chv_pre_enable_dp;
6191                 intel_encoder->enable = vlv_enable_dp;
6192                 intel_encoder->post_disable = chv_post_disable_dp;
6193                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6194         } else if (IS_VALLEYVIEW(dev)) {
6195                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6196                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6197                 intel_encoder->enable = vlv_enable_dp;
6198                 intel_encoder->post_disable = vlv_post_disable_dp;
6199         } else {
6200                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6201                 intel_encoder->enable = g4x_enable_dp;
6202                 if (INTEL_INFO(dev)->gen >= 5)
6203                         intel_encoder->post_disable = ilk_post_disable_dp;
6204         }
6205
6206         intel_dig_port->port = port;
6207         intel_dig_port->dp.output_reg = output_reg;
6208
6209         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6210         if (IS_CHERRYVIEW(dev)) {
6211                 if (port == PORT_D)
6212                         intel_encoder->crtc_mask = 1 << 2;
6213                 else
6214                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6215         } else {
6216                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6217         }
6218         intel_encoder->cloneable = 0;
6219
6220         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6221         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6222
6223         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
6224                 drm_encoder_cleanup(encoder);
6225                 kfree(intel_dig_port);
6226                 kfree(intel_connector);
6227         }
6228 }
6229
6230 void intel_dp_mst_suspend(struct drm_device *dev)
6231 {
6232         struct drm_i915_private *dev_priv = dev->dev_private;
6233         int i;
6234
6235         /* disable MST */
6236         for (i = 0; i < I915_MAX_PORTS; i++) {
6237                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6238                 if (!intel_dig_port)
6239                         continue;
6240
6241                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6242                         if (!intel_dig_port->dp.can_mst)
6243                                 continue;
6244                         if (intel_dig_port->dp.is_mst)
6245                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6246                 }
6247         }
6248 }
6249
6250 void intel_dp_mst_resume(struct drm_device *dev)
6251 {
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         int i;
6254
6255         for (i = 0; i < I915_MAX_PORTS; i++) {
6256                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6257                 if (!intel_dig_port)
6258                         continue;
6259                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6260                         int ret;
6261
6262                         if (!intel_dig_port->dp.can_mst)
6263                                 continue;
6264
6265                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6266                         if (ret != 0) {
6267                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6268                         }
6269                 }
6270         }
6271 }