2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_set_mode(struct drm_atomic_state *state);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void chv_prepare_pll(struct intel_crtc *crtc,
105 const struct intel_crtc_state *pipe_config);
106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117 if (!connector->mst_port)
118 return connector->encoder;
120 return &connector->mst_port->mst_encoders[pipe]->base;
129 int p2_slow, p2_fast;
132 typedef struct intel_limit intel_limit_t;
134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
139 intel_pch_rawclk(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
143 WARN_ON(!HAS_PCH_SPLIT(dev));
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
148 static inline u32 /* units of 100MHz */
149 intel_fdi_link_freq(struct drm_device *dev)
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
158 static const intel_limit_t intel_limits_i8xx_dac = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
171 static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
184 static const intel_limit_t intel_limits_i8xx_lvds = {
185 .dot = { .min = 25000, .max = 350000 },
186 .vco = { .min = 908000, .max = 1512000 },
187 .n = { .min = 2, .max = 16 },
188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
197 static const intel_limit_t intel_limits_i9xx_sdvo = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
210 static const intel_limit_t intel_limits_i9xx_lvds = {
211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
224 static const intel_limit_t intel_limits_g4x_sdvo = {
225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
239 static const intel_limit_t intel_limits_g4x_hdmi = {
240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
280 static const intel_limit_t intel_limits_pineview_sdvo = {
281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
283 /* Pineview's Ncounter is a ring counter */
284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
286 /* Pineview only has one combined m divider, which we treat as m2. */
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
295 static const intel_limit_t intel_limits_pineview_lvds = {
296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
308 /* Ironlake / Sandybridge
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
313 static const intel_limit_t intel_limits_ironlake_dac = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
352 /* LVDS 100mhz refclk limits. */
353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
379 static const intel_limit_t intel_limits_vlv = {
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
387 .vco = { .min = 4000000, .max = 6000000 },
388 .n = { .min = 1, .max = 7 },
389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
395 static const intel_limit_t intel_limits_chv = {
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
403 .vco = { .min = 4800000, .max = 6480000 },
404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
411 static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
423 static void vlv_clock(int refclk, intel_clock_t *clock)
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
427 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
434 needs_modeset(struct drm_crtc_state *state)
436 return state->mode_changed || state->active_changed;
440 * Returns whether any output on the specified pipe is of the specified type
442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
444 struct drm_device *dev = crtc->base.dev;
445 struct intel_encoder *encoder;
447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
448 if (encoder->type == type)
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
463 struct drm_atomic_state *state = crtc_state->base.state;
464 struct drm_connector *connector;
465 struct drm_connector_state *connector_state;
466 struct intel_encoder *encoder;
467 int i, num_connectors = 0;
469 for_each_connector_in_state(state, connector, connector_state, i) {
470 if (connector_state->crtc != crtc_state->base.crtc)
475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
480 WARN_ON(num_connectors == 0);
485 static const intel_limit_t *
486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
488 struct drm_device *dev = crtc_state->base.crtc->dev;
489 const intel_limit_t *limit;
491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
492 if (intel_is_dual_link_lvds(dev)) {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_dual_lvds_100m;
496 limit = &intel_limits_ironlake_dual_lvds;
498 if (refclk == 100000)
499 limit = &intel_limits_ironlake_single_lvds_100m;
501 limit = &intel_limits_ironlake_single_lvds;
504 limit = &intel_limits_ironlake_dac;
509 static const intel_limit_t *
510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
512 struct drm_device *dev = crtc_state->base.crtc->dev;
513 const intel_limit_t *limit;
515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 limit = &intel_limits_g4x_dual_channel_lvds;
519 limit = &intel_limits_g4x_single_channel_lvds;
520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
522 limit = &intel_limits_g4x_hdmi;
523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
524 limit = &intel_limits_g4x_sdvo;
525 } else /* The option is for other outputs */
526 limit = &intel_limits_i9xx_sdvo;
531 static const intel_limit_t *
532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
534 struct drm_device *dev = crtc_state->base.crtc->dev;
535 const intel_limit_t *limit;
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
540 limit = intel_ironlake_limit(crtc_state, refclk);
541 else if (IS_G4X(dev)) {
542 limit = intel_g4x_limit(crtc_state);
543 } else if (IS_PINEVIEW(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_pineview_lvds;
547 limit = &intel_limits_pineview_sdvo;
548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
550 } else if (IS_VALLEYVIEW(dev)) {
551 limit = &intel_limits_vlv;
552 } else if (!IS_GEN2(dev)) {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i9xx_lvds;
556 limit = &intel_limits_i9xx_sdvo;
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
559 limit = &intel_limits_i8xx_lvds;
560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
561 limit = &intel_limits_i8xx_dvo;
563 limit = &intel_limits_i8xx_dac;
568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
569 static void pineview_clock(int refclk, intel_clock_t *clock)
571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
584 static void i9xx_clock(int refclk, intel_clock_t *clock)
586 clock->m = i9xx_dpll_compute_m(clock);
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 static void chv_clock(int refclk, intel_clock_t *clock)
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
605 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
611 static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
618 INTELPllInvalid("p1 out of range\n");
619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
620 INTELPllInvalid("m2 out of range\n");
621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
622 INTELPllInvalid("m1 out of range\n");
624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
636 INTELPllInvalid("vco out of range\n");
637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
641 INTELPllInvalid("dot out of range\n");
647 i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
653 struct drm_device *dev = crtc->base.dev;
657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
663 if (intel_is_dual_link_lvds(dev))
664 clock.p2 = limit->p2.p2_fast;
666 clock.p2 = limit->p2.p2_slow;
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
671 clock.p2 = limit->p2.p2_fast;
674 memset(best_clock, 0, sizeof(*best_clock));
676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
680 if (clock.m2 >= clock.m1)
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
693 clock.p != match_clock->p)
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
706 return (err != target);
710 pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
716 struct drm_device *dev = crtc->base.dev;
720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
726 if (intel_is_dual_link_lvds(dev))
727 clock.p2 = limit->p2.p2_fast;
729 clock.p2 = limit->p2.p2_slow;
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
734 clock.p2 = limit->p2.p2_fast;
737 memset(best_clock, 0, sizeof(*best_clock));
739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
749 pineview_clock(refclk, &clock);
750 if (!intel_PLL_is_valid(dev, limit,
754 clock.p != match_clock->p)
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
767 return (err != target);
771 g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
777 struct drm_device *dev = crtc->base.dev;
781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
786 if (intel_is_dual_link_lvds(dev))
787 clock.p2 = limit->p2.p2_fast;
789 clock.p2 = limit->p2.p2_slow;
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
794 clock.p2 = limit->p2.p2_fast;
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
799 /* based on hardware requirement, prefer smaller n to precision */
800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
801 /* based on hardware requirement, prefere larger m1,m2 */
802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
810 i9xx_clock(refclk, &clock);
811 if (!intel_PLL_is_valid(dev, limit,
815 this_err = abs(clock.dot - target);
816 if (this_err < err_most) {
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
843 if (IS_CHERRYVIEW(dev)) {
846 return calculated_clock->p > best_clock->p;
849 if (WARN_ON_ONCE(!target_freq))
852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
866 return *error_ppm + 10 < best_error_ppm;
870 vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
876 struct drm_device *dev = crtc->base.dev;
878 unsigned int bestppm = 1000000;
879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
883 target *= 5; /* fast clock */
885 memset(best_clock, 0, sizeof(*best_clock));
887 /* based on hardware requirement, prefer smaller n to precision */
888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
892 clock.p = clock.p1 * clock.p2;
893 /* based on hardware requirement, prefer bigger m1,m2 values */
894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
900 vlv_clock(refclk, &clock);
902 if (!intel_PLL_is_valid(dev, limit,
906 if (!vlv_PLL_is_optimal(dev, target,
924 chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
930 struct drm_device *dev = crtc->base.dev;
931 unsigned int best_error_ppm;
936 memset(best_clock, 0, sizeof(*best_clock));
937 best_error_ppm = 1000000;
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
951 unsigned int error_ppm;
953 clock.p = clock.p1 * clock.p2;
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
958 if (m2 > INT_MAX/clock.m1)
963 chv_clock(refclk, &clock);
965 if (!intel_PLL_is_valid(dev, limit, &clock))
968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
973 best_error_ppm = error_ppm;
981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
984 int refclk = i9xx_get_refclk(crtc_state, 0);
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
990 bool intel_crtc_active(struct drm_crtc *crtc)
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
997 * We can ditch the adjusted_mode.crtc_clock check as soon
998 * as Haswell has gained clock readout/fastboot support.
1000 * We can ditch the crtc->primary->fb check as soon as we can
1001 * properly reconstruct framebuffers.
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1007 return intel_crtc->active && crtc->primary->state->fb &&
1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1017 return intel_crtc->config->cpu_transcoder;
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1028 line_mask = DSL_LINEMASK_GEN2;
1030 line_mask = DSL_LINEMASK_GEN3;
1032 line1 = I915_READ(reg) & line_mask;
1034 line2 = I915_READ(reg) & line_mask;
1036 return line1 == line2;
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
1041 * @crtc: crtc whose pipe to wait for
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1057 struct drm_device *dev = crtc->base.dev;
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060 enum pipe pipe = crtc->pipe;
1062 if (INTEL_INFO(dev)->gen >= 4) {
1063 int reg = PIPECONF(cpu_transcoder);
1065 /* Wait for the Pipe State to go off */
1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1068 WARN(1, "pipe_off wait timed out\n");
1070 /* Wait for the display line to settle */
1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072 WARN(1, "pipe_off wait timed out\n");
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1081 * Returns true if @port is connected, false otherwise.
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1088 if (HAS_PCH_IBX(dev_priv->dev)) {
1089 switch (port->port) {
1091 bit = SDE_PORTB_HOTPLUG;
1094 bit = SDE_PORTC_HOTPLUG;
1097 bit = SDE_PORTD_HOTPLUG;
1103 switch (port->port) {
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1118 return I915_READ(SDEISR) & bit;
1121 static const char *state_string(bool enabled)
1123 return enabled ? "on" : "off";
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
1137 I915_STATE_WARN(cur_state != state,
1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1148 mutex_lock(&dev_priv->sb_lock);
1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150 mutex_unlock(&dev_priv->sb_lock);
1152 cur_state = val & DSI_PLL_VCO_EN;
1153 I915_STATE_WARN(cur_state != state,
1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1165 if (crtc->config->shared_dpll < 0)
1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1177 struct intel_dpll_hw_state hw_state;
1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184 I915_STATE_WARN(cur_state != state,
1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1238 /* ILK FDI PLL is always enabled */
1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243 if (HAS_DDI(dev_priv->dev))
1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1269 struct drm_device *dev = dev_priv->dev;
1272 enum pipe panel_pipe = PIPE_A;
1275 if (WARN_ON(HAS_DDI(dev)))
1278 if (HAS_PCH_SPLIT(dev)) {
1281 pp_reg = PCH_PP_CONTROL;
1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1293 pp_reg = PP_CONTROL;
1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1303 I915_STATE_WARN(panel_pipe == pipe && locked,
1304 "panel assertion failure, pipe %c regs locked\n",
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1311 struct drm_device *dev = dev_priv->dev;
1314 if (IS_845G(dev) || IS_I865G(dev))
1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1319 I915_STATE_WARN(cur_state != state,
1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1340 if (!intel_display_power_is_enabled(dev_priv,
1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1349 I915_STATE_WARN(cur_state != state,
1350 "pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364 I915_STATE_WARN(cur_state != state,
1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1375 struct drm_device *dev = dev_priv->dev;
1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385 "plane %c assertion failure, should be disabled but not\n",
1390 /* Need to check both planes against the pipe */
1391 for_each_pipe(dev_priv, i) {
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1405 struct drm_device *dev = dev_priv->dev;
1409 if (INTEL_INFO(dev)->gen >= 9) {
1410 for_each_sprite(dev_priv, pipe, sprite) {
1411 val = I915_READ(PLANE_CTL(pipe, sprite));
1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1416 } else if (IS_VALLEYVIEW(dev)) {
1417 for_each_sprite(dev_priv, pipe, sprite) {
1418 reg = SPCNTR(pipe, sprite);
1419 val = I915_READ(reg);
1420 I915_STATE_WARN(val & SP_ENABLE,
1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422 sprite_name(pipe, sprite), pipe_name(pipe));
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1426 val = I915_READ(reg);
1427 I915_STATE_WARN(val & SPRITE_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
1432 val = I915_READ(reg);
1433 I915_STATE_WARN(val & DVS_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442 drm_crtc_vblank_put(crtc);
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1465 reg = PCH_TRANSCONF(pipe);
1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
1468 I915_STATE_WARN(enabled,
1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
1476 if ((val & DP_PORT_EN) == 0)
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1497 if ((val & SDVO_ENABLE) == 0)
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1516 if ((val & LVDS_PORT_EN) == 0)
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545 enum pipe pipe, int reg, u32 port_sel)
1547 u32 val = I915_READ(reg);
1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550 reg, pipe_name(pipe));
1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553 && (val & DP_PIPEB_SELECT),
1554 "IBX PCH dp port still using transcoder B\n");
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1560 u32 val = I915_READ(reg);
1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563 reg, pipe_name(pipe));
1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566 && (val & SDVO_PIPE_B_SELECT),
1567 "IBX PCH hdmi port still using transcoder B\n");
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581 val = I915_READ(reg);
1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
1587 val = I915_READ(reg);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 static void intel_init_dpio(struct drm_device *dev)
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1601 if (!IS_VALLEYVIEW(dev))
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618 const struct intel_crtc_state *pipe_config)
1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1630 /* PLL is protected by panel, make sure we can write it */
1631 if (IS_MOBILE(dev_priv->dev))
1632 assert_panel_unlocked(dev_priv, crtc->pipe);
1634 I915_WRITE(reg, dpll);
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642 POSTING_READ(DPLL_MD(crtc->pipe));
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1653 udelay(150); /* wait for warmup */
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657 const struct intel_crtc_state *pipe_config)
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1669 mutex_lock(&dev_priv->sb_lock);
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1676 mutex_unlock(&dev_priv->sb_lock);
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1686 /* Check PLL is locked */
1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1690 /* not sure when this should be written */
1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692 POSTING_READ(DPLL_MD(pipe));
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1697 struct intel_crtc *crtc;
1700 for_each_intel_crtc(dev, crtc)
1701 count += crtc->base.state->active &&
1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
1714 assert_pipe_disabled(dev_priv, crtc->pipe);
1716 /* No really, not for ILK+ */
1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1719 /* PLL is protected by panel, make sure we can write it */
1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1736 /* Wait for the clocks to stabilize. */
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
1742 crtc->config->dpll_hw_state.dpll_md);
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1747 * So write it again.
1749 I915_WRITE(reg, dpll);
1752 /* We do this three times for luck */
1753 I915_WRITE(reg, dpll);
1755 udelay(150); /* wait for warmup */
1756 I915_WRITE(reg, dpll);
1758 udelay(150); /* wait for warmup */
1759 I915_WRITE(reg, dpll);
1761 udelay(150); /* wait for warmup */
1765 * i9xx_disable_pll - disable a PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1771 * Note! This is for pre-ILK only.
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782 !intel_num_dvo_pipes(dev)) {
1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
1827 /* Set PLL en = 0 */
1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
1834 mutex_lock(&dev_priv->sb_lock);
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1852 mutex_unlock(&dev_priv->sb_lock);
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
1862 switch (dport->port) {
1864 port_mask = DPLL_PORTB_READY_MASK;
1868 port_mask = DPLL_PORTC_READY_MASK;
1870 expected_mask <<= 4;
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891 if (WARN_ON(pll == NULL))
1894 WARN_ON(!pll->config.crtc_mask);
1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1900 pll->mode_set(dev_priv, pll);
1905 * intel_enable_shared_dpll - enable PCH PLL
1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918 if (WARN_ON(pll == NULL))
1921 if (WARN_ON(pll->config.crtc_mask == 0))
1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925 pll->name, pll->active, pll->on,
1926 crtc->base.base.id);
1928 if (pll->active++) {
1930 assert_shared_dpll_enabled(dev_priv, pll);
1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938 pll->enable(dev_priv, pll);
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1948 /* PCH only available on ILK+ */
1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
1950 if (WARN_ON(pll == NULL))
1953 if (WARN_ON(pll->config.crtc_mask == 0))
1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
1958 crtc->base.base.id);
1960 if (WARN_ON(pll->active == 0)) {
1961 assert_shared_dpll_disabled(dev_priv, pll);
1965 assert_shared_dpll_enabled(dev_priv, pll);
1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971 pll->disable(dev_priv, pll);
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1980 struct drm_device *dev = dev_priv->dev;
1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 uint32_t reg, val, pipeconf_val;
1985 /* PCH only available on ILK+ */
1986 BUG_ON(!HAS_PCH_SPLIT(dev));
1988 /* Make sure PCH DPLL is enabled */
1989 assert_shared_dpll_enabled(dev_priv,
1990 intel_crtc_to_shared_dpll(intel_crtc));
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
2005 reg = PCH_TRANSCONF(pipe);
2006 val = I915_READ(reg);
2007 pipeconf_val = I915_READ(PIPECONF(pipe));
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
2015 val &= ~PIPECONF_BPC_MASK;
2016 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017 val |= PIPECONF_8BPC;
2019 val |= pipeconf_val & PIPECONF_BPC_MASK;
2022 val &= ~TRANS_INTERLACE_MASK;
2023 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2024 if (HAS_PCH_IBX(dev_priv->dev) &&
2025 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2026 val |= TRANS_LEGACY_INTERLACED_ILK;
2028 val |= TRANS_INTERLACED;
2030 val |= TRANS_PROGRESSIVE;
2032 I915_WRITE(reg, val | TRANS_ENABLE);
2033 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2037 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2038 enum transcoder cpu_transcoder)
2040 u32 val, pipeconf_val;
2042 /* PCH only available on ILK+ */
2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2045 /* FDI must be feeding us bits for PCH ports */
2046 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2047 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2049 /* Workaround: set timing override bit. */
2050 val = I915_READ(_TRANSA_CHICKEN2);
2051 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2052 I915_WRITE(_TRANSA_CHICKEN2, val);
2055 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2057 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058 PIPECONF_INTERLACED_ILK)
2059 val |= TRANS_INTERLACED;
2061 val |= TRANS_PROGRESSIVE;
2063 I915_WRITE(LPT_TRANSCONF, val);
2064 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2065 DRM_ERROR("Failed to enable PCH transcoder\n");
2068 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2071 struct drm_device *dev = dev_priv->dev;
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv, pipe);
2076 assert_fdi_rx_disabled(dev_priv, pipe);
2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv, pipe);
2081 reg = PCH_TRANSCONF(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(reg, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2089 if (!HAS_PCH_IBX(dev)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg = TRANS_CHICKEN2(pipe);
2092 val = I915_READ(reg);
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(reg, val);
2098 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2102 val = I915_READ(LPT_TRANSCONF);
2103 val &= ~TRANS_ENABLE;
2104 I915_WRITE(LPT_TRANSCONF, val);
2105 /* wait for PCH transcoder off, transcoder state */
2106 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2107 DRM_ERROR("Failed to disable PCH transcoder\n");
2109 /* Workaround: clear timing override bit. */
2110 val = I915_READ(_TRANSA_CHICKEN2);
2111 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2112 I915_WRITE(_TRANSA_CHICKEN2, val);
2116 * intel_enable_pipe - enable a pipe, asserting requirements
2117 * @crtc: crtc responsible for the pipe
2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2122 static void intel_enable_pipe(struct intel_crtc *crtc)
2124 struct drm_device *dev = crtc->base.dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe = crtc->pipe;
2127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2129 enum pipe pch_transcoder;
2133 assert_planes_disabled(dev_priv, pipe);
2134 assert_cursor_disabled(dev_priv, pipe);
2135 assert_sprites_disabled(dev_priv, pipe);
2137 if (HAS_PCH_LPT(dev_priv->dev))
2138 pch_transcoder = TRANSCODER_A;
2140 pch_transcoder = pipe;
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149 assert_dsi_pll_enabled(dev_priv);
2151 assert_pll_enabled(dev_priv, pipe);
2153 if (crtc->config->has_pch_encoder) {
2154 /* if driving the PCH, we need FDI enabled */
2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
2159 /* FIXME: assert CPU port conditions for SNB+ */
2162 reg = PIPECONF(cpu_transcoder);
2163 val = I915_READ(reg);
2164 if (val & PIPECONF_ENABLE) {
2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
2175 * intel_disable_pipe - disable a pipe, asserting requirements
2176 * @crtc: crtc whose pipes is to be disabled
2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
2182 * Will wait until the pipe has shut down before returning.
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188 enum pipe pipe = crtc->pipe;
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2196 assert_planes_disabled(dev_priv, pipe);
2197 assert_cursor_disabled(dev_priv, pipe);
2198 assert_sprites_disabled(dev_priv, pipe);
2200 reg = PIPECONF(cpu_transcoder);
2201 val = I915_READ(reg);
2202 if ((val & PIPECONF_ENABLE) == 0)
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2209 if (crtc->config->double_wide)
2210 val &= ~PIPECONF_DOUBLE_WIDE;
2212 /* Don't disable pipe or pipe PLLs if needed */
2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215 val &= ~PIPECONF_ENABLE;
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2238 to_intel_plane_state(plane->state)->visible = true;
2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2244 static bool need_vtd_wa(struct drm_device *dev)
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2254 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 case I915_FORMAT_MOD_Y_TILED:
2270 case I915_FORMAT_MOD_Yf_TILED:
2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
2286 "128-bit pixels are not supported for display!");
2292 MISSING_CASE(fb_format_modifier);
2301 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2312 struct intel_rotation_info *info = &view->rotation_info;
2314 *view = i915_ggtt_view_normal;
2319 if (!intel_rotation_90_or_270(plane_state->rotation))
2322 *view = i915_ggtt_view_rotated;
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2332 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2334 if (INTEL_INFO(dev_priv)->gen >= 9)
2336 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337 IS_VALLEYVIEW(dev_priv))
2339 else if (INTEL_INFO(dev_priv)->gen >= 4)
2346 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
2348 const struct drm_plane_state *plane_state,
2349 struct intel_engine_cs *pipelined)
2351 struct drm_device *dev = fb->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2354 struct i915_ggtt_view view;
2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
2362 alignment = intel_linear_alignment(dev_priv);
2364 case I915_FORMAT_MOD_X_TILED:
2365 if (INTEL_INFO(dev)->gen >= 9)
2366 alignment = 256 * 1024;
2368 /* pin() will align the object as required by fence */
2372 case I915_FORMAT_MOD_Y_TILED:
2373 case I915_FORMAT_MOD_Yf_TILED:
2374 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2377 alignment = 1 * 1024 * 1024;
2380 MISSING_CASE(fb->modifier[0]);
2384 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2393 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394 alignment = 256 * 1024;
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2403 intel_runtime_pm_get(dev_priv);
2405 dev_priv->mm.interruptible = false;
2406 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2409 goto err_interruptible;
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2416 ret = i915_gem_object_get_fence(obj);
2420 i915_gem_object_pin_fence(obj);
2422 dev_priv->mm.interruptible = true;
2423 intel_runtime_pm_put(dev_priv);
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2429 dev_priv->mm.interruptible = true;
2430 intel_runtime_pm_put(dev_priv);
2434 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435 const struct drm_plane_state *plane_state)
2437 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2438 struct i915_ggtt_view view;
2441 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2443 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444 WARN_ONCE(ret, "Couldn't get view from plane state!");
2446 i915_gem_object_unpin_fence(obj);
2447 i915_gem_object_unpin_from_display_plane(obj, &view);
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2454 unsigned int tiling_mode,
2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
2464 tiles = *x / (512/cpp);
2467 return tile_rows * pitch * 8 + tiles * 4096;
2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470 unsigned int offset;
2472 offset = *y * pitch + *x * cpp;
2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
2479 static int i9xx_format_to_fourcc(int format)
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2509 return DRM_FORMAT_ABGR8888;
2511 return DRM_FORMAT_XBGR8888;
2514 return DRM_FORMAT_ARGB8888;
2516 return DRM_FORMAT_XRGB8888;
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2520 return DRM_FORMAT_XBGR2101010;
2522 return DRM_FORMAT_XRGB2101010;
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_gem_object *obj = NULL;
2532 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2533 struct drm_framebuffer *fb = &plane_config->fb->base;
2534 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2538 size_aligned -= base_aligned;
2540 if (plane_config->size == 0)
2543 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2550 obj->tiling_mode = plane_config->tiling;
2551 if (obj->tiling_mode == I915_TILING_X)
2552 obj->stride = fb->pitches[0];
2554 mode_cmd.pixel_format = fb->pixel_format;
2555 mode_cmd.width = fb->width;
2556 mode_cmd.height = fb->height;
2557 mode_cmd.pitches[0] = fb->pitches[0];
2558 mode_cmd.modifier[0] = fb->modifier[0];
2559 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2561 mutex_lock(&dev->struct_mutex);
2562 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2564 DRM_DEBUG_KMS("intel fb init failed\n");
2567 mutex_unlock(&dev->struct_mutex);
2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2573 drm_gem_object_unreference(&obj->base);
2574 mutex_unlock(&dev->struct_mutex);
2578 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2580 update_state_fb(struct drm_plane *plane)
2582 if (plane->fb == plane->state->fb)
2585 if (plane->state->fb)
2586 drm_framebuffer_unreference(plane->state->fb);
2587 plane->state->fb = plane->fb;
2588 if (plane->state->fb)
2589 drm_framebuffer_reference(plane->state->fb);
2593 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594 struct intel_initial_plane_config *plane_config)
2596 struct drm_device *dev = intel_crtc->base.dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2599 struct intel_crtc *i;
2600 struct drm_i915_gem_object *obj;
2601 struct drm_plane *primary = intel_crtc->base.primary;
2602 struct drm_framebuffer *fb;
2604 if (!plane_config->fb)
2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608 fb = &plane_config->fb->base;
2612 kfree(plane_config->fb);
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2618 for_each_crtc(dev, c) {
2619 i = to_intel_crtc(c);
2621 if (c == &intel_crtc->base)
2627 fb = c->primary->fb;
2631 obj = intel_fb_obj(fb);
2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633 drm_framebuffer_reference(fb);
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
2647 update_state_fb(primary);
2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
2661 struct drm_i915_gem_object *obj;
2662 int plane = intel_crtc->plane;
2663 unsigned long linear_offset;
2665 u32 reg = DSPCNTR(plane);
2668 if (!visible || !fb) {
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2673 I915_WRITE(DSPADDR(plane), 0);
2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2686 dspcntr |= DISPLAY_PLANE_ENABLE;
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2695 I915_WRITE(DSPSIZE(plane),
2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
2698 I915_WRITE(DSPPOS(plane), 0);
2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2707 switch (fb->pixel_format) {
2709 dspcntr |= DISPPLANE_8BPP;
2711 case DRM_FORMAT_XRGB1555:
2712 dspcntr |= DISPPLANE_BGRX555;
2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2717 case DRM_FORMAT_XRGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2720 case DRM_FORMAT_XBGR8888:
2721 dspcntr |= DISPPLANE_RGBX888;
2723 case DRM_FORMAT_XRGB2101010:
2724 dspcntr |= DISPPLANE_BGRX101010;
2726 case DRM_FORMAT_XBGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
2748 linear_offset -= intel_crtc->dspaddr_offset;
2750 intel_crtc->dspaddr_offset = linear_offset;
2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754 dspcntr |= DISPPLANE_ROTATE_180;
2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2766 I915_WRITE(reg, dspcntr);
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 if (INTEL_INFO(dev)->gen >= 4) {
2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
2788 struct drm_i915_gem_object *obj;
2789 int plane = intel_crtc->plane;
2790 unsigned long linear_offset;
2792 u32 reg = DSPCNTR(plane);
2795 if (!visible || !fb) {
2797 I915_WRITE(DSPSURF(plane), 0);
2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2810 dspcntr |= DISPLAY_PLANE_ENABLE;
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2815 switch (fb->pixel_format) {
2817 dspcntr |= DISPPLANE_8BPP;
2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
2822 case DRM_FORMAT_XRGB8888:
2823 dspcntr |= DISPPLANE_BGRX888;
2825 case DRM_FORMAT_XBGR8888:
2826 dspcntr |= DISPPLANE_RGBX888;
2828 case DRM_FORMAT_XRGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2831 case DRM_FORMAT_XBGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
2845 intel_crtc->dspaddr_offset =
2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866 I915_WRITE(reg, dspcntr);
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2909 MISSING_CASE(fb_modifier);
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2935 if (!intel_crtc || !intel_crtc->config)
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2956 switch (pixel_format) {
2958 return PLANE_CTL_FORMAT_INDEXED;
2959 case DRM_FORMAT_RGB565:
2960 return PLANE_CTL_FORMAT_RGB_565;
2961 case DRM_FORMAT_XBGR8888:
2962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 case DRM_FORMAT_XRGB8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888;
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2970 case DRM_FORMAT_ABGR8888:
2971 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973 case DRM_FORMAT_ARGB8888:
2974 return PLANE_CTL_FORMAT_XRGB_8888 |
2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976 case DRM_FORMAT_XRGB2101010:
2977 return PLANE_CTL_FORMAT_XRGB_2101010;
2978 case DRM_FORMAT_XBGR2101010:
2979 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2980 case DRM_FORMAT_YUYV:
2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2982 case DRM_FORMAT_YVYU:
2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2984 case DRM_FORMAT_UYVY:
2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2986 case DRM_FORMAT_VYUY:
2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2989 MISSING_CASE(pixel_format);
2995 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2997 switch (fb_modifier) {
2998 case DRM_FORMAT_MOD_NONE:
3000 case I915_FORMAT_MOD_X_TILED:
3001 return PLANE_CTL_TILED_X;
3002 case I915_FORMAT_MOD_Y_TILED:
3003 return PLANE_CTL_TILED_Y;
3004 case I915_FORMAT_MOD_Yf_TILED:
3005 return PLANE_CTL_TILED_YF;
3007 MISSING_CASE(fb_modifier);
3013 u32 skl_plane_ctl_rotation(unsigned int rotation)
3016 case BIT(DRM_ROTATE_0):
3019 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3020 * while i915 HW rotation is clockwise, thats why this swapping.
3022 case BIT(DRM_ROTATE_90):
3023 return PLANE_CTL_ROTATE_270;
3024 case BIT(DRM_ROTATE_180):
3025 return PLANE_CTL_ROTATE_180;
3026 case BIT(DRM_ROTATE_270):
3027 return PLANE_CTL_ROTATE_90;
3029 MISSING_CASE(rotation);
3035 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3036 struct drm_framebuffer *fb,
3039 struct drm_device *dev = crtc->dev;
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042 struct drm_plane *plane = crtc->primary;
3043 bool visible = to_intel_plane_state(plane->state)->visible;
3044 struct drm_i915_gem_object *obj;
3045 int pipe = intel_crtc->pipe;
3046 u32 plane_ctl, stride_div, stride;
3047 u32 tile_height, plane_offset, plane_size;
3048 unsigned int rotation;
3049 int x_offset, y_offset;
3050 unsigned long surf_addr;
3051 struct intel_crtc_state *crtc_state = intel_crtc->config;
3052 struct intel_plane_state *plane_state;
3053 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3054 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3057 plane_state = to_intel_plane_state(plane->state);
3059 if (!visible || !fb) {
3060 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3061 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3062 POSTING_READ(PLANE_CTL(pipe, 0));
3066 plane_ctl = PLANE_CTL_ENABLE |
3067 PLANE_CTL_PIPE_GAMMA_ENABLE |
3068 PLANE_CTL_PIPE_CSC_ENABLE;
3070 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3071 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3072 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3074 rotation = plane->state->rotation;
3075 plane_ctl |= skl_plane_ctl_rotation(rotation);
3077 obj = intel_fb_obj(fb);
3078 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3080 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3083 * FIXME: intel_plane_state->src, dst aren't set when transitional
3084 * update_plane helpers are called from legacy paths.
3085 * Once full atomic crtc is available, below check can be avoided.
3087 if (drm_rect_width(&plane_state->src)) {
3088 scaler_id = plane_state->scaler_id;
3089 src_x = plane_state->src.x1 >> 16;
3090 src_y = plane_state->src.y1 >> 16;
3091 src_w = drm_rect_width(&plane_state->src) >> 16;
3092 src_h = drm_rect_height(&plane_state->src) >> 16;
3093 dst_x = plane_state->dst.x1;
3094 dst_y = plane_state->dst.y1;
3095 dst_w = drm_rect_width(&plane_state->dst);
3096 dst_h = drm_rect_height(&plane_state->dst);
3098 WARN_ON(x != src_x || y != src_y);
3100 src_w = intel_crtc->config->pipe_src_w;
3101 src_h = intel_crtc->config->pipe_src_h;
3104 if (intel_rotation_90_or_270(rotation)) {
3105 /* stride = Surface height in tiles */
3106 tile_height = intel_tile_height(dev, fb->pixel_format,
3108 stride = DIV_ROUND_UP(fb->height, tile_height);
3109 x_offset = stride * tile_height - y - src_h;
3111 plane_size = (src_w - 1) << 16 | (src_h - 1);
3113 stride = fb->pitches[0] / stride_div;
3116 plane_size = (src_h - 1) << 16 | (src_w - 1);
3118 plane_offset = y_offset << 16 | x_offset;
3120 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3121 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3122 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3123 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3125 if (scaler_id >= 0) {
3126 uint32_t ps_ctrl = 0;
3128 WARN_ON(!dst_w || !dst_h);
3129 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3130 crtc_state->scaler_state.scalers[scaler_id].mode;
3131 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3132 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3133 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3134 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3135 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3140 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3142 POSTING_READ(PLANE_SURF(pipe, 0));
3145 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3147 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3148 int x, int y, enum mode_set_atomic state)
3150 struct drm_device *dev = crtc->dev;
3151 struct drm_i915_private *dev_priv = dev->dev_private;
3153 if (dev_priv->display.disable_fbc)
3154 dev_priv->display.disable_fbc(dev);
3156 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3161 static void intel_complete_page_flips(struct drm_device *dev)
3163 struct drm_crtc *crtc;
3165 for_each_crtc(dev, crtc) {
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 enum plane plane = intel_crtc->plane;
3169 intel_prepare_page_flip(dev, plane);
3170 intel_finish_page_flip_plane(dev, plane);
3174 static void intel_update_primary_planes(struct drm_device *dev)
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct drm_crtc *crtc;
3179 for_each_crtc(dev, crtc) {
3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 drm_modeset_lock(&crtc->mutex, NULL);
3184 * FIXME: Once we have proper support for primary planes (and
3185 * disabling them without disabling the entire crtc) allow again
3186 * a NULL crtc->primary->fb.
3188 if (intel_crtc->active && crtc->primary->fb)
3189 dev_priv->display.update_primary_plane(crtc,
3193 drm_modeset_unlock(&crtc->mutex);
3197 void intel_prepare_reset(struct drm_device *dev)
3199 /* no reset support for gen2 */
3203 /* reset doesn't touch the display */
3204 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3207 drm_modeset_lock_all(dev);
3209 * Disabling the crtcs gracefully seems nicer. Also the
3210 * g33 docs say we should at least disable all the planes.
3212 intel_display_suspend(dev);
3215 void intel_finish_reset(struct drm_device *dev)
3217 struct drm_i915_private *dev_priv = to_i915(dev);
3220 * Flips in the rings will be nuked by the reset,
3221 * so complete all pending flips so that user space
3222 * will get its events and not get stuck.
3224 intel_complete_page_flips(dev);
3226 /* no reset support for gen2 */
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3233 * Flips in the rings have been nuked by the reset,
3234 * so update the base address of all primary
3235 * planes to the the last fb to make sure we're
3236 * showing the correct fb after a reset.
3238 intel_update_primary_planes(dev);
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3246 intel_runtime_pm_disable_interrupts(dev_priv);
3247 intel_runtime_pm_enable_interrupts(dev_priv);
3249 intel_modeset_init_hw(dev);
3251 spin_lock_irq(&dev_priv->irq_lock);
3252 if (dev_priv->display.hpd_irq_setup)
3253 dev_priv->display.hpd_irq_setup(dev);
3254 spin_unlock_irq(&dev_priv->irq_lock);
3256 intel_modeset_setup_hw_state(dev, true);
3258 intel_hpd_init(dev_priv);
3260 drm_modeset_unlock_all(dev);
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3266 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268 bool was_interruptible = dev_priv->mm.interruptible;
3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3282 dev_priv->mm.interruptible = false;
3283 ret = i915_gem_object_wait_rendering(obj, true);
3284 dev_priv->mm.interruptible = was_interruptible;
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3300 spin_lock_irq(&dev->event_lock);
3301 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302 spin_unlock_irq(&dev->event_lock);
3307 static void intel_update_pipe_size(struct intel_crtc *crtc)
3309 struct drm_device *dev = crtc->base.dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 const struct drm_display_mode *adjusted_mode;
3317 * Update pipe size and adjust fitter if needed: the reason for this is
3318 * that in compute_mode_changes we check the native mode (not the pfit
3319 * mode) to see if we can flip rather than do a full mode set. In the
3320 * fastboot case, we'll flip, but if we don't update the pipesrc and
3321 * pfit state, we'll end up with a big fb scanned out into the wrong
3324 * To fix this properly, we need to hoist the checks up into
3325 * compute_mode_changes (or above), check the actual pfit state and
3326 * whether the platform allows pfit disable with pipe active, and only
3327 * then update the pipesrc and pfit state, even on the flip path.
3330 adjusted_mode = &crtc->config->base.adjusted_mode;
3332 I915_WRITE(PIPESRC(crtc->pipe),
3333 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3334 (adjusted_mode->crtc_vdisplay - 1));
3335 if (!crtc->config->pch_pfit.enabled &&
3336 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3337 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3338 I915_WRITE(PF_CTL(crtc->pipe), 0);
3339 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3340 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3342 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3343 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 int pipe = intel_crtc->pipe;
3354 /* enable normal train */
3355 reg = FDI_TX_CTL(pipe);
3356 temp = I915_READ(reg);
3357 if (IS_IVYBRIDGE(dev)) {
3358 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3359 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3364 I915_WRITE(reg, temp);
3366 reg = FDI_RX_CTL(pipe);
3367 temp = I915_READ(reg);
3368 if (HAS_PCH_CPT(dev)) {
3369 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3370 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3372 temp &= ~FDI_LINK_TRAIN_NONE;
3373 temp |= FDI_LINK_TRAIN_NONE;
3375 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3377 /* wait one idle pattern time */
3381 /* IVB wants error correction enabled */
3382 if (IS_IVYBRIDGE(dev))
3383 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3384 FDI_FE_ERRC_ENABLE);
3387 /* The FDI link training functions for ILK/Ibexpeak. */
3388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3390 struct drm_device *dev = crtc->dev;
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393 int pipe = intel_crtc->pipe;
3394 u32 reg, temp, tries;
3396 /* FDI needs bits from pipe first */
3397 assert_pipe_enabled(dev_priv, pipe);
3399 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3401 reg = FDI_RX_IMR(pipe);
3402 temp = I915_READ(reg);
3403 temp &= ~FDI_RX_SYMBOL_LOCK;
3404 temp &= ~FDI_RX_BIT_LOCK;
3405 I915_WRITE(reg, temp);
3409 /* enable CPU FDI TX and PCH FDI RX */
3410 reg = FDI_TX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3413 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1;
3416 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3418 reg = FDI_RX_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
3422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427 /* Ironlake workaround, enable clock pointer after FDI enable*/
3428 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3430 FDI_RX_PHASE_SYNC_POINTER_EN);
3432 reg = FDI_RX_IIR(pipe);
3433 for (tries = 0; tries < 5; tries++) {
3434 temp = I915_READ(reg);
3435 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3437 if ((temp & FDI_RX_BIT_LOCK)) {
3438 DRM_DEBUG_KMS("FDI train 1 done.\n");
3439 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444 DRM_ERROR("FDI train 1 fail!\n");
3447 reg = FDI_TX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_2;
3451 I915_WRITE(reg, temp);
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 I915_WRITE(reg, temp);
3462 reg = FDI_RX_IIR(pipe);
3463 for (tries = 0; tries < 5; tries++) {
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467 if (temp & FDI_RX_SYMBOL_LOCK) {
3468 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3469 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 DRM_ERROR("FDI train 2 fail!\n");
3476 DRM_DEBUG_KMS("FDI train done\n");
3480 static const int snb_b_fdi_train_param[] = {
3481 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3482 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3483 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3484 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3487 /* The FDI link training functions for SNB/Cougarpoint. */
3488 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493 int pipe = intel_crtc->pipe;
3494 u32 reg, temp, i, retry;
3496 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3498 reg = FDI_RX_IMR(pipe);
3499 temp = I915_READ(reg);
3500 temp &= ~FDI_RX_SYMBOL_LOCK;
3501 temp &= ~FDI_RX_BIT_LOCK;
3502 I915_WRITE(reg, temp);
3507 /* enable CPU FDI TX and PCH FDI RX */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3511 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3516 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3517 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3519 I915_WRITE(FDI_RX_MISC(pipe),
3520 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1;
3531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536 for (i = 0; i < 4; i++) {
3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
3541 I915_WRITE(reg, temp);
3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_BIT_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done.\n");
3561 DRM_ERROR("FDI train 1 fail!\n");
3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_LINK_TRAIN_NONE;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3573 I915_WRITE(reg, temp);
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2;
3584 I915_WRITE(reg, temp);
3589 for (i = 0; i < 4; i++) {
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
3594 I915_WRITE(reg, temp);
3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_SYMBOL_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3605 DRM_DEBUG_KMS("FDI train 2 done.\n");
3614 DRM_ERROR("FDI train 2 fail!\n");
3616 DRM_DEBUG_KMS("FDI train done.\n");
3619 /* Manual link training for Ivy Bridge A0 parts */
3620 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625 int pipe = intel_crtc->pipe;
3626 u32 reg, temp, i, j;
3628 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3630 reg = FDI_RX_IMR(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~FDI_RX_SYMBOL_LOCK;
3633 temp &= ~FDI_RX_BIT_LOCK;
3634 I915_WRITE(reg, temp);
3639 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3640 I915_READ(FDI_RX_IIR(pipe)));
3642 /* Try each vswing and preemphasis setting twice before moving on */
3643 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3644 /* disable first in case we need to retry */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3648 temp &= ~FDI_TX_ENABLE;
3649 I915_WRITE(reg, temp);
3651 reg = FDI_RX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_LINK_TRAIN_AUTO;
3654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3655 temp &= ~FDI_RX_ENABLE;
3656 I915_WRITE(reg, temp);
3658 /* enable CPU FDI TX and PCH FDI RX */
3659 reg = FDI_TX_CTL(pipe);
3660 temp = I915_READ(reg);
3661 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3662 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3663 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3665 temp |= snb_b_fdi_train_param[j/2];
3666 temp |= FDI_COMPOSITE_SYNC;
3667 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3669 I915_WRITE(FDI_RX_MISC(pipe),
3670 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3675 temp |= FDI_COMPOSITE_SYNC;
3676 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3679 udelay(1); /* should be 0.5us */
3681 for (i = 0; i < 4; i++) {
3682 reg = FDI_RX_IIR(pipe);
3683 temp = I915_READ(reg);
3684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3686 if (temp & FDI_RX_BIT_LOCK ||
3687 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3688 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3689 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3693 udelay(1); /* should be 0.5us */
3696 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 reg = FDI_TX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3704 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3705 I915_WRITE(reg, temp);
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3711 I915_WRITE(reg, temp);
3714 udelay(2); /* should be 1.5us */
3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3721 if (temp & FDI_RX_SYMBOL_LOCK ||
3722 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3724 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3728 udelay(2); /* should be 1.5us */
3731 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3735 DRM_DEBUG_KMS("FDI train done.\n");
3738 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3740 struct drm_device *dev = intel_crtc->base.dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 int pipe = intel_crtc->pipe;
3746 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
3749 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3750 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3751 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3752 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757 /* Switch from Rawclk to PCDclk */
3758 temp = I915_READ(reg);
3759 I915_WRITE(reg, temp | FDI_PCDCLK);
3764 /* Enable CPU FDI TX PLL, always on for Ironlake */
3765 reg = FDI_TX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3768 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3777 struct drm_device *dev = intel_crtc->base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 int pipe = intel_crtc->pipe;
3782 /* Switch from PCDclk to Rawclk */
3783 reg = FDI_RX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3787 /* Disable CPU FDI TX PLL */
3788 reg = FDI_TX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795 reg = FDI_RX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3799 /* Wait for the clocks to turn off. */
3804 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809 int pipe = intel_crtc->pipe;
3812 /* disable CPU FDI tx and PCH FDI rx */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~(0x7 << 16);
3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3822 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827 /* Ironlake workaround, disable clock pointer after downing FDI */
3828 if (HAS_PCH_IBX(dev))
3829 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3831 /* still set train pattern 1 */
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 I915_WRITE(reg, temp);
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 if (HAS_PCH_CPT(dev)) {
3841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1;
3847 /* BPC in FDI rx is consistent with that in PIPECONF */
3848 temp &= ~(0x07 << 16);
3849 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3850 I915_WRITE(reg, temp);
3856 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3858 struct intel_crtc *crtc;
3860 /* Note that we don't need to be called with mode_config.lock here
3861 * as our list of CRTC objects is static for the lifetime of the
3862 * device and so cannot disappear as we iterate. Similarly, we can
3863 * happily treat the predicates as racy, atomic checks as userspace
3864 * cannot claim and pin a new fb without at least acquring the
3865 * struct_mutex and so serialising with us.
3867 for_each_intel_crtc(dev, crtc) {
3868 if (atomic_read(&crtc->unpin_work_count) == 0)
3871 if (crtc->unpin_work)
3872 intel_wait_for_vblank(dev, crtc->pipe);
3880 static void page_flip_completed(struct intel_crtc *intel_crtc)
3882 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3883 struct intel_unpin_work *work = intel_crtc->unpin_work;
3885 /* ensure that the unpin work is consistent wrt ->pending. */
3887 intel_crtc->unpin_work = NULL;
3890 drm_send_vblank_event(intel_crtc->base.dev,
3894 drm_crtc_vblank_put(&intel_crtc->base);
3896 wake_up_all(&dev_priv->pending_flip_queue);
3897 queue_work(dev_priv->wq, &work->work);
3899 trace_i915_flip_complete(intel_crtc->plane,
3900 work->pending_flip_obj);
3903 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3905 struct drm_device *dev = crtc->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3908 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3909 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3910 !intel_crtc_has_pending_flip(crtc),
3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3914 spin_lock_irq(&dev->event_lock);
3915 if (intel_crtc->unpin_work) {
3916 WARN_ONCE(1, "Removing stuck page flip\n");
3917 page_flip_completed(intel_crtc);
3919 spin_unlock_irq(&dev->event_lock);
3922 if (crtc->primary->fb) {
3923 mutex_lock(&dev->struct_mutex);
3924 intel_finish_fb(crtc->primary->fb);
3925 mutex_unlock(&dev->struct_mutex);
3929 /* Program iCLKIP clock to the desired frequency */
3930 static void lpt_program_iclkip(struct drm_crtc *crtc)
3932 struct drm_device *dev = crtc->dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3938 mutex_lock(&dev_priv->sb_lock);
3940 /* It is necessary to ungate the pixclk gate prior to programming
3941 * the divisors, and gate it back when it is done.
3943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945 /* Disable SSCCTL */
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3947 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3951 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3952 if (clock == 20000) {
3957 /* The iCLK virtual clock root frequency is in MHz,
3958 * but the adjusted_mode->crtc_clock in in KHz. To get the
3959 * divisors, it is necessary to divide one by another, so we
3960 * convert the virtual clock precision to KHz here for higher
3963 u32 iclk_virtual_root_freq = 172800 * 1000;
3964 u32 iclk_pi_range = 64;
3965 u32 desired_divisor, msb_divisor_value, pi_value;
3967 desired_divisor = (iclk_virtual_root_freq / clock);
3968 msb_divisor_value = desired_divisor / iclk_pi_range;
3969 pi_value = desired_divisor % iclk_pi_range;
3972 divsel = msb_divisor_value - 2;
3973 phaseinc = pi_value;
3976 /* This should not happen with any sane values */
3977 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3978 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3979 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3980 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3982 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3989 /* Program SSCDIVINTPHASE6 */
3990 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3991 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3992 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3993 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3994 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3995 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3996 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3999 /* Program SSCAUXDIV */
4000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4003 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4005 /* Enable modulator and associated divider */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4007 temp &= ~SBI_SSCCTL_DISABLE;
4008 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4010 /* Wait for initialization time */
4013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4015 mutex_unlock(&dev_priv->sb_lock);
4018 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4019 enum pipe pch_transcoder)
4021 struct drm_device *dev = crtc->base.dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4025 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4026 I915_READ(HTOTAL(cpu_transcoder)));
4027 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4028 I915_READ(HBLANK(cpu_transcoder)));
4029 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4030 I915_READ(HSYNC(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4033 I915_READ(VTOTAL(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4035 I915_READ(VBLANK(cpu_transcoder)));
4036 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4037 I915_READ(VSYNC(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4039 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4042 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4047 temp = I915_READ(SOUTH_CHICKEN1);
4048 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4054 temp &= ~FDI_BC_BIFURCATION_SELECT;
4056 temp |= FDI_BC_BIFURCATION_SELECT;
4058 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4059 I915_WRITE(SOUTH_CHICKEN1, temp);
4060 POSTING_READ(SOUTH_CHICKEN1);
4063 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4065 struct drm_device *dev = intel_crtc->base.dev;
4067 switch (intel_crtc->pipe) {
4071 if (intel_crtc->config->fdi_lanes > 2)
4072 cpt_set_fdi_bc_bifurcation(dev, false);
4074 cpt_set_fdi_bc_bifurcation(dev, true);
4078 cpt_set_fdi_bc_bifurcation(dev, true);
4087 * Enable PCH resources required for PCH ports:
4089 * - FDI training & RX/TX
4090 * - update transcoder timings
4091 * - DP transcoding bits
4094 static void ironlake_pch_enable(struct drm_crtc *crtc)
4096 struct drm_device *dev = crtc->dev;
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4099 int pipe = intel_crtc->pipe;
4102 assert_pch_transcoder_disabled(dev_priv, pipe);
4104 if (IS_IVYBRIDGE(dev))
4105 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4107 /* Write the TU size bits before fdi link training, so that error
4108 * detection works. */
4109 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4110 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4112 /* For PCH output, training FDI link */
4113 dev_priv->display.fdi_link_train(crtc);
4115 /* We need to program the right clock selection before writing the pixel
4116 * mutliplier into the DPLL. */
4117 if (HAS_PCH_CPT(dev)) {
4120 temp = I915_READ(PCH_DPLL_SEL);
4121 temp |= TRANS_DPLL_ENABLE(pipe);
4122 sel = TRANS_DPLLB_SEL(pipe);
4123 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4127 I915_WRITE(PCH_DPLL_SEL, temp);
4130 /* XXX: pch pll's can be enabled any time before we enable the PCH
4131 * transcoder, and we actually should do this to not upset any PCH
4132 * transcoder that already use the clock when we share it.
4134 * Note that enable_shared_dpll tries to do the right thing, but
4135 * get_shared_dpll unconditionally resets the pll - we need that to have
4136 * the right LVDS enable sequence. */
4137 intel_enable_shared_dpll(intel_crtc);
4139 /* set transcoder timing, panel must allow it */
4140 assert_panel_unlocked(dev_priv, pipe);
4141 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4143 intel_fdi_normal_train(crtc);
4145 /* For PCH DP, enable TRANS_DP_CTL */
4146 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4147 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4148 reg = TRANS_DP_CTL(pipe);
4149 temp = I915_READ(reg);
4150 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4151 TRANS_DP_SYNC_MASK |
4153 temp |= TRANS_DP_OUTPUT_ENABLE;
4154 temp |= bpc << 9; /* same format but at 11:9 */
4156 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4157 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4158 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4159 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4161 switch (intel_trans_dp_port_sel(crtc)) {
4163 temp |= TRANS_DP_PORT_SEL_B;
4166 temp |= TRANS_DP_PORT_SEL_C;
4169 temp |= TRANS_DP_PORT_SEL_D;
4175 I915_WRITE(reg, temp);
4178 ironlake_enable_pch_transcoder(dev_priv, pipe);
4181 static void lpt_pch_enable(struct drm_crtc *crtc)
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4188 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4190 lpt_program_iclkip(crtc);
4192 /* Set transcoder timing. */
4193 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4195 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4198 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4199 struct intel_crtc_state *crtc_state)
4201 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4202 struct intel_shared_dpll *pll;
4203 struct intel_shared_dpll_config *shared_dpll;
4204 enum intel_dpll_id i;
4206 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4208 if (HAS_PCH_IBX(dev_priv->dev)) {
4209 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4210 i = (enum intel_dpll_id) crtc->pipe;
4211 pll = &dev_priv->shared_dplls[i];
4213 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4214 crtc->base.base.id, pll->name);
4216 WARN_ON(shared_dpll[i].crtc_mask);
4221 if (IS_BROXTON(dev_priv->dev)) {
4222 /* PLL is attached to port in bxt */
4223 struct intel_encoder *encoder;
4224 struct intel_digital_port *intel_dig_port;
4226 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4227 if (WARN_ON(!encoder))
4230 intel_dig_port = enc_to_dig_port(&encoder->base);
4231 /* 1:1 mapping between ports and PLLs */
4232 i = (enum intel_dpll_id)intel_dig_port->port;
4233 pll = &dev_priv->shared_dplls[i];
4234 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4235 crtc->base.base.id, pll->name);
4236 WARN_ON(shared_dpll[i].crtc_mask);
4241 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4242 pll = &dev_priv->shared_dplls[i];
4244 /* Only want to check enabled timings first */
4245 if (shared_dpll[i].crtc_mask == 0)
4248 if (memcmp(&crtc_state->dpll_hw_state,
4249 &shared_dpll[i].hw_state,
4250 sizeof(crtc_state->dpll_hw_state)) == 0) {
4251 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4252 crtc->base.base.id, pll->name,
4253 shared_dpll[i].crtc_mask,
4259 /* Ok no matching timings, maybe there's a free one? */
4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
4262 if (shared_dpll[i].crtc_mask == 0) {
4263 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4264 crtc->base.base.id, pll->name);
4272 if (shared_dpll[i].crtc_mask == 0)
4273 shared_dpll[i].hw_state =
4274 crtc_state->dpll_hw_state;
4276 crtc_state->shared_dpll = i;
4277 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4278 pipe_name(crtc->pipe));
4280 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4285 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4287 struct drm_i915_private *dev_priv = to_i915(state->dev);
4288 struct intel_shared_dpll_config *shared_dpll;
4289 struct intel_shared_dpll *pll;
4290 enum intel_dpll_id i;
4292 if (!to_intel_atomic_state(state)->dpll_set)
4295 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297 pll = &dev_priv->shared_dplls[i];
4298 pll->config = shared_dpll[i];
4302 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 int dslreg = PIPEDSL(pipe);
4308 temp = I915_READ(dslreg);
4310 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4311 if (wait_for(I915_READ(dslreg) != temp, 5))
4312 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4317 * skl_update_scaler_users - Stages update to crtc's scaler state
4319 * @crtc_state: crtc_state
4320 * @plane: plane (NULL indicates crtc is requesting update)
4321 * @plane_state: plane's state
4322 * @force_detach: request unconditional detachment of scaler
4324 * This function updates scaler state for requested plane or crtc.
4325 * To request scaler usage update for a plane, caller shall pass plane pointer.
4326 * To request scaler usage update for crtc, caller shall pass plane pointer
4330 * 0 - scaler_usage updated successfully
4331 * error - requested scaling cannot be supported or other error condition
4334 skl_update_scaler_users(
4335 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4336 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4341 int src_w, src_h, dst_w, dst_h;
4343 struct drm_framebuffer *fb;
4344 struct intel_crtc_scaler_state *scaler_state;
4345 unsigned int rotation;
4347 if (!intel_crtc || !crtc_state)
4350 scaler_state = &crtc_state->scaler_state;
4352 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4353 fb = intel_plane ? plane_state->base.fb : NULL;
4356 src_w = drm_rect_width(&plane_state->src) >> 16;
4357 src_h = drm_rect_height(&plane_state->src) >> 16;
4358 dst_w = drm_rect_width(&plane_state->dst);
4359 dst_h = drm_rect_height(&plane_state->dst);
4360 scaler_id = &plane_state->scaler_id;
4361 rotation = plane_state->base.rotation;
4363 struct drm_display_mode *adjusted_mode =
4364 &crtc_state->base.adjusted_mode;
4365 src_w = crtc_state->pipe_src_w;
4366 src_h = crtc_state->pipe_src_h;
4367 dst_w = adjusted_mode->hdisplay;
4368 dst_h = adjusted_mode->vdisplay;
4369 scaler_id = &scaler_state->scaler_id;
4370 rotation = DRM_ROTATE_0;
4373 need_scaling = intel_rotation_90_or_270(rotation) ?
4374 (src_h != dst_w || src_w != dst_h):
4375 (src_w != dst_w || src_h != dst_h);
4378 * if plane is being disabled or scaler is no more required or force detach
4379 * - free scaler binded to this plane/crtc
4380 * - in order to do this, update crtc->scaler_usage
4382 * Here scaler state in crtc_state is set free so that
4383 * scaler can be assigned to other user. Actual register
4384 * update to free the scaler is done in plane/panel-fit programming.
4385 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4387 if (force_detach || !need_scaling || (intel_plane &&
4388 (!fb || !plane_state->visible))) {
4389 if (*scaler_id >= 0) {
4390 scaler_state->scaler_users &= ~(1 << idx);
4391 scaler_state->scalers[*scaler_id].in_use = 0;
4393 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4394 "crtc_state = %p scaler_users = 0x%x\n",
4395 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4396 intel_plane ? intel_plane->base.base.id :
4397 intel_crtc->base.base.id, crtc_state,
4398 scaler_state->scaler_users);
4405 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4406 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4408 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4409 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4410 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4411 "size is out of scaler range\n",
4412 intel_plane ? "PLANE" : "CRTC",
4413 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4414 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4418 /* check colorkey */
4419 if (WARN_ON(intel_plane &&
4420 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4421 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4422 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4426 /* Check src format */
4428 switch (fb->pixel_format) {
4429 case DRM_FORMAT_RGB565:
4430 case DRM_FORMAT_XBGR8888:
4431 case DRM_FORMAT_XRGB8888:
4432 case DRM_FORMAT_ABGR8888:
4433 case DRM_FORMAT_ARGB8888:
4434 case DRM_FORMAT_XRGB2101010:
4435 case DRM_FORMAT_XBGR2101010:
4436 case DRM_FORMAT_YUYV:
4437 case DRM_FORMAT_YVYU:
4438 case DRM_FORMAT_UYVY:
4439 case DRM_FORMAT_VYUY:
4442 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4443 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4448 /* mark this plane as a scaler user in crtc_state */
4449 scaler_state->scaler_users |= (1 << idx);
4450 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4451 "crtc_state = %p scaler_users = 0x%x\n",
4452 intel_plane ? "PLANE" : "CRTC",
4453 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4454 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4458 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4460 struct drm_device *dev = crtc->base.dev;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 int pipe = crtc->pipe;
4463 struct intel_crtc_scaler_state *scaler_state =
4464 &crtc->config->scaler_state;
4466 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4468 /* To update pfit, first update scaler state */
4469 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4470 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4471 skl_detach_scalers(crtc);
4475 if (crtc->config->pch_pfit.enabled) {
4478 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4479 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4483 id = scaler_state->scaler_id;
4484 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4485 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4486 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4487 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4489 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4493 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4495 struct drm_device *dev = crtc->base.dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 int pipe = crtc->pipe;
4499 if (crtc->config->pch_pfit.enabled) {
4500 /* Force use of hard-coded filter coefficients
4501 * as some pre-programmed values are broken,
4504 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4505 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4506 PF_PIPE_SEL_IVB(pipe));
4508 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4509 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4510 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4514 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4516 struct drm_device *dev = crtc->dev;
4517 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4518 struct drm_plane *plane;
4519 struct intel_plane *intel_plane;
4521 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4522 intel_plane = to_intel_plane(plane);
4523 if (intel_plane->pipe == pipe)
4524 intel_plane_restore(&intel_plane->base);
4528 void hsw_enable_ips(struct intel_crtc *crtc)
4530 struct drm_device *dev = crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4533 if (!crtc->config->ips_enabled)
4536 /* We can only enable IPS after we enable a plane and wait for a vblank */
4537 intel_wait_for_vblank(dev, crtc->pipe);
4539 assert_plane_enabled(dev_priv, crtc->plane);
4540 if (IS_BROADWELL(dev)) {
4541 mutex_lock(&dev_priv->rps.hw_lock);
4542 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4543 mutex_unlock(&dev_priv->rps.hw_lock);
4544 /* Quoting Art Runyan: "its not safe to expect any particular
4545 * value in IPS_CTL bit 31 after enabling IPS through the
4546 * mailbox." Moreover, the mailbox may return a bogus state,
4547 * so we need to just enable it and continue on.
4550 I915_WRITE(IPS_CTL, IPS_ENABLE);
4551 /* The bit only becomes 1 in the next vblank, so this wait here
4552 * is essentially intel_wait_for_vblank. If we don't have this
4553 * and don't wait for vblanks until the end of crtc_enable, then
4554 * the HW state readout code will complain that the expected
4555 * IPS_CTL value is not the one we read. */
4556 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4557 DRM_ERROR("Timed out waiting for IPS enable\n");
4561 void hsw_disable_ips(struct intel_crtc *crtc)
4563 struct drm_device *dev = crtc->base.dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4566 if (!crtc->config->ips_enabled)
4569 assert_plane_enabled(dev_priv, crtc->plane);
4570 if (IS_BROADWELL(dev)) {
4571 mutex_lock(&dev_priv->rps.hw_lock);
4572 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4575 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4576 DRM_ERROR("Timed out waiting for IPS disable\n");
4578 I915_WRITE(IPS_CTL, 0);
4579 POSTING_READ(IPS_CTL);
4582 /* We need to wait for a vblank before we can disable the plane. */
4583 intel_wait_for_vblank(dev, crtc->pipe);
4586 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4587 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4589 struct drm_device *dev = crtc->dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592 enum pipe pipe = intel_crtc->pipe;
4593 int palreg = PALETTE(pipe);
4595 bool reenable_ips = false;
4597 /* The clocks have to be on to load the palette. */
4598 if (!crtc->state->active)
4601 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4602 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4603 assert_dsi_pll_enabled(dev_priv);
4605 assert_pll_enabled(dev_priv, pipe);
4608 /* use legacy palette for Ironlake */
4609 if (!HAS_GMCH_DISPLAY(dev))
4610 palreg = LGC_PALETTE(pipe);
4612 /* Workaround : Do not read or write the pipe palette/gamma data while
4613 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4615 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4616 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4617 GAMMA_MODE_MODE_SPLIT)) {
4618 hsw_disable_ips(intel_crtc);
4619 reenable_ips = true;
4622 for (i = 0; i < 256; i++) {
4623 I915_WRITE(palreg + 4 * i,
4624 (intel_crtc->lut_r[i] << 16) |
4625 (intel_crtc->lut_g[i] << 8) |
4626 intel_crtc->lut_b[i]);
4630 hsw_enable_ips(intel_crtc);
4633 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4635 if (intel_crtc->overlay) {
4636 struct drm_device *dev = intel_crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4639 mutex_lock(&dev->struct_mutex);
4640 dev_priv->mm.interruptible = false;
4641 (void) intel_overlay_switch_off(intel_crtc->overlay);
4642 dev_priv->mm.interruptible = true;
4643 mutex_unlock(&dev->struct_mutex);
4646 /* Let userspace switch the overlay on again. In most cases userspace
4647 * has to recompute where to put it anyway.
4652 * intel_post_enable_primary - Perform operations after enabling primary plane
4653 * @crtc: the CRTC whose primary plane was just enabled
4655 * Performs potentially sleeping operations that must be done after the primary
4656 * plane is enabled, such as updating FBC and IPS. Note that this may be
4657 * called due to an explicit primary plane update, or due to an implicit
4658 * re-enable that is caused when a sprite plane is updated to no longer
4659 * completely hide the primary plane.
4662 intel_post_enable_primary(struct drm_crtc *crtc)
4664 struct drm_device *dev = crtc->dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4667 int pipe = intel_crtc->pipe;
4670 * BDW signals flip done immediately if the plane
4671 * is disabled, even if the plane enable is already
4672 * armed to occur at the next vblank :(
4674 if (IS_BROADWELL(dev))
4675 intel_wait_for_vblank(dev, pipe);
4678 * FIXME IPS should be fine as long as one plane is
4679 * enabled, but in practice it seems to have problems
4680 * when going from primary only to sprite only and vice
4683 hsw_enable_ips(intel_crtc);
4685 mutex_lock(&dev->struct_mutex);
4686 intel_fbc_update(dev);
4687 mutex_unlock(&dev->struct_mutex);
4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4740 if (HAS_GMCH_DISPLAY(dev))
4741 intel_set_memory_cxsr(dev_priv, false);
4743 mutex_lock(&dev->struct_mutex);
4744 if (dev_priv->fbc.crtc == intel_crtc)
4745 intel_fbc_disable(dev);
4746 mutex_unlock(&dev->struct_mutex);
4749 * FIXME IPS should be fine as long as one plane is
4750 * enabled, but in practice it seems to have problems
4751 * when going from primary only to sprite only and vice
4754 hsw_disable_ips(intel_crtc);
4757 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4759 struct drm_device *dev = crtc->dev;
4760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4761 int pipe = intel_crtc->pipe;
4763 intel_enable_primary_hw_plane(crtc->primary, crtc);
4764 intel_enable_sprite_planes(crtc);
4765 if (to_intel_plane_state(crtc->cursor->state)->visible)
4766 intel_crtc_update_cursor(crtc, true);
4768 intel_post_enable_primary(crtc);
4771 * FIXME: Once we grow proper nuclear flip support out of this we need
4772 * to compute the mask of flip planes precisely. For the time being
4773 * consider this a flip to a NULL plane.
4775 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4778 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4780 struct drm_device *dev = crtc->dev;
4781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782 struct intel_plane *intel_plane;
4783 int pipe = intel_crtc->pipe;
4785 intel_crtc_wait_for_pending_flips(crtc);
4787 intel_pre_disable_primary(crtc);
4789 intel_crtc_dpms_overlay_disable(intel_crtc);
4790 for_each_intel_plane(dev, intel_plane) {
4791 if (intel_plane->pipe == pipe) {
4792 struct drm_crtc *from = intel_plane->base.crtc;
4794 intel_plane->disable_plane(&intel_plane->base,
4795 from ?: crtc, true);
4800 * FIXME: Once we grow proper nuclear flip support out of this we need
4801 * to compute the mask of flip planes precisely. For the time being
4802 * consider this a flip to a NULL plane.
4804 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4807 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812 struct intel_encoder *encoder;
4813 int pipe = intel_crtc->pipe;
4815 if (WARN_ON(intel_crtc->active))
4818 if (intel_crtc->config->has_pch_encoder)
4819 intel_prepare_shared_dpll(intel_crtc);
4821 if (intel_crtc->config->has_dp_encoder)
4822 intel_dp_set_m_n(intel_crtc, M1_N1);
4824 intel_set_pipe_timings(intel_crtc);
4826 if (intel_crtc->config->has_pch_encoder) {
4827 intel_cpu_transcoder_set_m_n(intel_crtc,
4828 &intel_crtc->config->fdi_m_n, NULL);
4831 ironlake_set_pipeconf(crtc);
4833 intel_crtc->active = true;
4835 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4836 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 if (encoder->pre_enable)
4840 encoder->pre_enable(encoder);
4842 if (intel_crtc->config->has_pch_encoder) {
4843 /* Note: FDI PLL enabling _must_ be done before we enable the
4844 * cpu pipes, hence this is separate from all the other fdi/pch
4846 ironlake_fdi_pll_enable(intel_crtc);
4848 assert_fdi_tx_disabled(dev_priv, pipe);
4849 assert_fdi_rx_disabled(dev_priv, pipe);
4852 ironlake_pfit_enable(intel_crtc);
4855 * On ILK+ LUT must be loaded before the pipe is running but with
4858 intel_crtc_load_lut(crtc);
4860 intel_update_watermarks(crtc);
4861 intel_enable_pipe(intel_crtc);
4863 if (intel_crtc->config->has_pch_encoder)
4864 ironlake_pch_enable(crtc);
4866 assert_vblank_disabled(crtc);
4867 drm_crtc_vblank_on(crtc);
4869 for_each_encoder_on_crtc(dev, crtc, encoder)
4870 encoder->enable(encoder);
4872 if (HAS_PCH_CPT(dev))
4873 cpt_verify_modeset(dev, intel_crtc->pipe);
4876 /* IPS only exists on ULT machines and is tied to pipe A. */
4877 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4879 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4882 static void haswell_crtc_enable(struct drm_crtc *crtc)
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *encoder;
4888 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4889 struct intel_crtc_state *pipe_config =
4890 to_intel_crtc_state(crtc->state);
4892 if (WARN_ON(intel_crtc->active))
4895 if (intel_crtc_to_shared_dpll(intel_crtc))
4896 intel_enable_shared_dpll(intel_crtc);
4898 if (intel_crtc->config->has_dp_encoder)
4899 intel_dp_set_m_n(intel_crtc, M1_N1);
4901 intel_set_pipe_timings(intel_crtc);
4903 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4904 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4905 intel_crtc->config->pixel_multiplier - 1);
4908 if (intel_crtc->config->has_pch_encoder) {
4909 intel_cpu_transcoder_set_m_n(intel_crtc,
4910 &intel_crtc->config->fdi_m_n, NULL);
4913 haswell_set_pipeconf(crtc);
4915 intel_set_pipe_csc(crtc);
4917 intel_crtc->active = true;
4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 if (encoder->pre_enable)
4922 encoder->pre_enable(encoder);
4924 if (intel_crtc->config->has_pch_encoder) {
4925 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4927 dev_priv->display.fdi_link_train(crtc);
4930 intel_ddi_enable_pipe_clock(intel_crtc);
4932 if (INTEL_INFO(dev)->gen == 9)
4933 skylake_pfit_update(intel_crtc, 1);
4934 else if (INTEL_INFO(dev)->gen < 9)
4935 ironlake_pfit_enable(intel_crtc);
4937 MISSING_CASE(INTEL_INFO(dev)->gen);
4940 * On ILK+ LUT must be loaded before the pipe is running but with
4943 intel_crtc_load_lut(crtc);
4945 intel_ddi_set_pipe_settings(crtc);
4946 intel_ddi_enable_transcoder_func(crtc);
4948 intel_update_watermarks(crtc);
4949 intel_enable_pipe(intel_crtc);
4951 if (intel_crtc->config->has_pch_encoder)
4952 lpt_pch_enable(crtc);
4954 if (intel_crtc->config->dp_encoder_is_mst)
4955 intel_ddi_set_vc_payload_alloc(crtc, true);
4957 assert_vblank_disabled(crtc);
4958 drm_crtc_vblank_on(crtc);
4960 for_each_encoder_on_crtc(dev, crtc, encoder) {
4961 encoder->enable(encoder);
4962 intel_opregion_notify_encoder(encoder, true);
4965 /* If we change the relative order between pipe/planes enabling, we need
4966 * to change the workaround. */
4967 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4968 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4969 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4974 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4976 struct drm_device *dev = crtc->base.dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 int pipe = crtc->pipe;
4980 /* To avoid upsetting the power well on haswell only disable the pfit if
4981 * it's in use. The hw state code will make sure we get this right. */
4982 if (crtc->config->pch_pfit.enabled) {
4983 I915_WRITE(PF_CTL(pipe), 0);
4984 I915_WRITE(PF_WIN_POS(pipe), 0);
4985 I915_WRITE(PF_WIN_SZ(pipe), 0);
4989 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994 struct intel_encoder *encoder;
4995 int pipe = intel_crtc->pipe;
4998 if (WARN_ON(!intel_crtc->active))
5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 encoder->disable(encoder);
5004 drm_crtc_vblank_off(crtc);
5005 assert_vblank_disabled(crtc);
5007 if (intel_crtc->config->has_pch_encoder)
5008 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5010 intel_disable_pipe(intel_crtc);
5012 ironlake_pfit_disable(intel_crtc);
5014 if (intel_crtc->config->has_pch_encoder)
5015 ironlake_fdi_disable(crtc);
5017 for_each_encoder_on_crtc(dev, crtc, encoder)
5018 if (encoder->post_disable)
5019 encoder->post_disable(encoder);
5021 if (intel_crtc->config->has_pch_encoder) {
5022 ironlake_disable_pch_transcoder(dev_priv, pipe);
5024 if (HAS_PCH_CPT(dev)) {
5025 /* disable TRANS_DP_CTL */
5026 reg = TRANS_DP_CTL(pipe);
5027 temp = I915_READ(reg);
5028 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5029 TRANS_DP_PORT_SEL_MASK);
5030 temp |= TRANS_DP_PORT_SEL_NONE;
5031 I915_WRITE(reg, temp);
5033 /* disable DPLL_SEL */
5034 temp = I915_READ(PCH_DPLL_SEL);
5035 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5036 I915_WRITE(PCH_DPLL_SEL, temp);
5039 /* disable PCH DPLL */
5040 intel_disable_shared_dpll(intel_crtc);
5042 ironlake_fdi_pll_disable(intel_crtc);
5045 intel_crtc->active = false;
5046 intel_update_watermarks(crtc);
5048 mutex_lock(&dev->struct_mutex);
5049 intel_fbc_update(dev);
5050 mutex_unlock(&dev->struct_mutex);
5053 static void haswell_crtc_disable(struct drm_crtc *crtc)
5055 struct drm_device *dev = crtc->dev;
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058 struct intel_encoder *encoder;
5059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5061 if (WARN_ON(!intel_crtc->active))
5064 for_each_encoder_on_crtc(dev, crtc, encoder) {
5065 intel_opregion_notify_encoder(encoder, false);
5066 encoder->disable(encoder);
5069 drm_crtc_vblank_off(crtc);
5070 assert_vblank_disabled(crtc);
5072 if (intel_crtc->config->has_pch_encoder)
5073 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5075 intel_disable_pipe(intel_crtc);
5077 if (intel_crtc->config->dp_encoder_is_mst)
5078 intel_ddi_set_vc_payload_alloc(crtc, false);
5080 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5082 if (INTEL_INFO(dev)->gen == 9)
5083 skylake_pfit_update(intel_crtc, 0);
5084 else if (INTEL_INFO(dev)->gen < 9)
5085 ironlake_pfit_disable(intel_crtc);
5087 MISSING_CASE(INTEL_INFO(dev)->gen);
5089 intel_ddi_disable_pipe_clock(intel_crtc);
5091 if (intel_crtc->config->has_pch_encoder) {
5092 lpt_disable_pch_transcoder(dev_priv);
5093 intel_ddi_fdi_disable(crtc);
5096 for_each_encoder_on_crtc(dev, crtc, encoder)
5097 if (encoder->post_disable)
5098 encoder->post_disable(encoder);
5100 intel_crtc->active = false;
5101 intel_update_watermarks(crtc);
5103 mutex_lock(&dev->struct_mutex);
5104 intel_fbc_update(dev);
5105 mutex_unlock(&dev->struct_mutex);
5107 if (intel_crtc_to_shared_dpll(intel_crtc))
5108 intel_disable_shared_dpll(intel_crtc);
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5113 struct drm_device *dev = crtc->base.dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc_state *pipe_config = crtc->config;
5117 if (!pipe_config->gmch_pfit.control)
5121 * The panel fitter should only be adjusted whilst the pipe is disabled,
5122 * according to register description and PRM.
5124 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125 assert_pipe_disabled(dev_priv, crtc->pipe);
5127 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5130 /* Border color in case we don't scale up to the full screen. Black by
5131 * default, change to something else for debugging. */
5132 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5139 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5141 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5143 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5145 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5148 return POWER_DOMAIN_PORT_OTHER;
5152 #define for_each_power_domain(domain, mask) \
5153 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5154 if ((1 << (domain)) & (mask))
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5159 struct drm_device *dev = intel_encoder->base.dev;
5160 struct intel_digital_port *intel_dig_port;
5162 switch (intel_encoder->type) {
5163 case INTEL_OUTPUT_UNKNOWN:
5164 /* Only DDI platforms should ever use this output type */
5165 WARN_ON_ONCE(!HAS_DDI(dev));
5166 case INTEL_OUTPUT_DISPLAYPORT:
5167 case INTEL_OUTPUT_HDMI:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_power_domain(intel_dig_port->port);
5174 case INTEL_OUTPUT_ANALOG:
5175 return POWER_DOMAIN_PORT_CRT;
5176 case INTEL_OUTPUT_DSI:
5177 return POWER_DOMAIN_PORT_DSI;
5179 return POWER_DOMAIN_PORT_OTHER;
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5185 struct drm_device *dev = crtc->dev;
5186 struct intel_encoder *intel_encoder;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 enum pipe pipe = intel_crtc->pipe;
5190 enum transcoder transcoder;
5192 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5194 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5196 if (intel_crtc->config->pch_pfit.enabled ||
5197 intel_crtc->config->pch_pfit.force_thru)
5198 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5200 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5201 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5206 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5208 struct drm_device *dev = state->dev;
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5211 struct intel_crtc *crtc;
5214 * First get all needed power domains, then put all unneeded, to avoid
5215 * any unnecessary toggling of the power wells.
5217 for_each_intel_crtc(dev, crtc) {
5218 enum intel_display_power_domain domain;
5220 if (!crtc->base.state->enable)
5223 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5225 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5226 intel_display_power_get(dev_priv, domain);
5229 if (dev_priv->display.modeset_global_resources)
5230 dev_priv->display.modeset_global_resources(state);
5232 for_each_intel_crtc(dev, crtc) {
5233 enum intel_display_power_domain domain;
5235 for_each_power_domain(domain, crtc->enabled_power_domains)
5236 intel_display_power_put(dev_priv, domain);
5238 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5241 intel_display_set_init_power(dev_priv, false);
5244 static void intel_update_max_cdclk(struct drm_device *dev)
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5248 if (IS_SKYLAKE(dev)) {
5249 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5251 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5252 dev_priv->max_cdclk_freq = 675000;
5253 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5254 dev_priv->max_cdclk_freq = 540000;
5255 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5256 dev_priv->max_cdclk_freq = 450000;
5258 dev_priv->max_cdclk_freq = 337500;
5259 } else if (IS_BROADWELL(dev)) {
5261 * FIXME with extra cooling we can allow
5262 * 540 MHz for ULX and 675 Mhz for ULT.
5263 * How can we know if extra cooling is
5264 * available? PCI ID, VTB, something else?
5266 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5267 dev_priv->max_cdclk_freq = 450000;
5268 else if (IS_BDW_ULX(dev))
5269 dev_priv->max_cdclk_freq = 450000;
5270 else if (IS_BDW_ULT(dev))
5271 dev_priv->max_cdclk_freq = 540000;
5273 dev_priv->max_cdclk_freq = 675000;
5274 } else if (IS_CHERRYVIEW(dev)) {
5275 dev_priv->max_cdclk_freq = 320000;
5276 } else if (IS_VALLEYVIEW(dev)) {
5277 dev_priv->max_cdclk_freq = 400000;
5279 /* otherwise assume cdclk is fixed */
5280 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5283 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5284 dev_priv->max_cdclk_freq);
5287 static void intel_update_cdclk(struct drm_device *dev)
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5291 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5292 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5293 dev_priv->cdclk_freq);
5296 * Program the gmbus_freq based on the cdclk frequency.
5297 * BSpec erroneously claims we should aim for 4MHz, but
5298 * in fact 1MHz is the correct frequency.
5300 if (IS_VALLEYVIEW(dev)) {
5302 * Program the gmbus_freq based on the cdclk frequency.
5303 * BSpec erroneously claims we should aim for 4MHz, but
5304 * in fact 1MHz is the correct frequency.
5306 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5309 if (dev_priv->max_cdclk_freq == 0)
5310 intel_update_max_cdclk(dev);
5313 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5318 uint32_t current_freq;
5321 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5322 switch (frequency) {
5324 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5325 ratio = BXT_DE_PLL_RATIO(60);
5328 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5329 ratio = BXT_DE_PLL_RATIO(60);
5332 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5333 ratio = BXT_DE_PLL_RATIO(60);
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5337 ratio = BXT_DE_PLL_RATIO(60);
5340 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5341 ratio = BXT_DE_PLL_RATIO(65);
5345 * Bypass frequency with DE PLL disabled. Init ratio, divider
5346 * to suppress GCC warning.
5352 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5357 mutex_lock(&dev_priv->rps.hw_lock);
5358 /* Inform power controller of upcoming frequency change */
5359 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5361 mutex_unlock(&dev_priv->rps.hw_lock);
5364 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5369 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5370 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5371 current_freq = current_freq * 500 + 1000;
5374 * DE PLL has to be disabled when
5375 * - setting to 19.2MHz (bypass, PLL isn't used)
5376 * - before setting to 624MHz (PLL needs toggling)
5377 * - before setting to any frequency from 624MHz (PLL needs toggling)
5379 if (frequency == 19200 || frequency == 624000 ||
5380 current_freq == 624000) {
5381 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5383 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5385 DRM_ERROR("timout waiting for DE PLL unlock\n");
5388 if (frequency != 19200) {
5391 val = I915_READ(BXT_DE_PLL_CTL);
5392 val &= ~BXT_DE_PLL_RATIO_MASK;
5394 I915_WRITE(BXT_DE_PLL_CTL, val);
5396 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5398 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5399 DRM_ERROR("timeout waiting for DE PLL lock\n");
5401 val = I915_READ(CDCLK_CTL);
5402 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5405 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5408 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409 if (frequency >= 500000)
5410 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5412 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5413 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5414 val |= (frequency - 1000) / 500;
5415 I915_WRITE(CDCLK_CTL, val);
5418 mutex_lock(&dev_priv->rps.hw_lock);
5419 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5420 DIV_ROUND_UP(frequency, 25000));
5421 mutex_unlock(&dev_priv->rps.hw_lock);
5424 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5429 intel_update_cdclk(dev);
5432 void broxton_init_cdclk(struct drm_device *dev)
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5438 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5439 * or else the reset will hang because there is no PCH to respond.
5440 * Move the handshake programming to initialization sequence.
5441 * Previously was left up to BIOS.
5443 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5444 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5445 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5447 /* Enable PG1 for cdclk */
5448 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5450 /* check if cd clock is enabled */
5451 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5452 DRM_DEBUG_KMS("Display already initialized\n");
5458 * - The initial CDCLK needs to be read from VBT.
5459 * Need to make this change after VBT has changes for BXT.
5460 * - check if setting the max (or any) cdclk freq is really necessary
5461 * here, it belongs to modeset time
5463 broxton_set_cdclk(dev, 624000);
5465 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5466 POSTING_READ(DBUF_CTL);
5470 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5471 DRM_ERROR("DBuf power enable timeout!\n");
5474 void broxton_uninit_cdclk(struct drm_device *dev)
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5478 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5479 POSTING_READ(DBUF_CTL);
5483 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5484 DRM_ERROR("DBuf power disable timeout!\n");
5486 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5487 broxton_set_cdclk(dev, 19200);
5489 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5492 static const struct skl_cdclk_entry {
5495 } skl_cdclk_frequencies[] = {
5496 { .freq = 308570, .vco = 8640 },
5497 { .freq = 337500, .vco = 8100 },
5498 { .freq = 432000, .vco = 8640 },
5499 { .freq = 450000, .vco = 8100 },
5500 { .freq = 540000, .vco = 8100 },
5501 { .freq = 617140, .vco = 8640 },
5502 { .freq = 675000, .vco = 8100 },
5505 static unsigned int skl_cdclk_decimal(unsigned int freq)
5507 return (freq - 1000) / 500;
5510 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5514 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5515 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5517 if (e->freq == freq)
5525 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5527 unsigned int min_freq;
5530 /* select the minimum CDCLK before enabling DPLL 0 */
5531 val = I915_READ(CDCLK_CTL);
5532 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5533 val |= CDCLK_FREQ_337_308;
5535 if (required_vco == 8640)
5540 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5542 I915_WRITE(CDCLK_CTL, val);
5543 POSTING_READ(CDCLK_CTL);
5546 * We always enable DPLL0 with the lowest link rate possible, but still
5547 * taking into account the VCO required to operate the eDP panel at the
5548 * desired frequency. The usual DP link rates operate with a VCO of
5549 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5550 * The modeset code is responsible for the selection of the exact link
5551 * rate later on, with the constraint of choosing a frequency that
5552 * works with required_vco.
5554 val = I915_READ(DPLL_CTRL1);
5556 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5557 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5558 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5559 if (required_vco == 8640)
5560 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5563 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5566 I915_WRITE(DPLL_CTRL1, val);
5567 POSTING_READ(DPLL_CTRL1);
5569 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5571 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5572 DRM_ERROR("DPLL0 not locked\n");
5575 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5580 /* inform PCU we want to change CDCLK */
5581 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5582 mutex_lock(&dev_priv->rps.hw_lock);
5583 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5584 mutex_unlock(&dev_priv->rps.hw_lock);
5586 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5589 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5593 for (i = 0; i < 15; i++) {
5594 if (skl_cdclk_pcu_ready(dev_priv))
5602 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5604 struct drm_device *dev = dev_priv->dev;
5605 u32 freq_select, pcu_ack;
5607 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5609 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5610 DRM_ERROR("failed to inform PCU about cdclk change\n");
5618 freq_select = CDCLK_FREQ_450_432;
5622 freq_select = CDCLK_FREQ_540;
5628 freq_select = CDCLK_FREQ_337_308;
5633 freq_select = CDCLK_FREQ_675_617;
5638 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5639 POSTING_READ(CDCLK_CTL);
5641 /* inform PCU of the change */
5642 mutex_lock(&dev_priv->rps.hw_lock);
5643 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5644 mutex_unlock(&dev_priv->rps.hw_lock);
5646 intel_update_cdclk(dev);
5649 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5651 /* disable DBUF power */
5652 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5653 POSTING_READ(DBUF_CTL);
5657 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5658 DRM_ERROR("DBuf power disable timeout\n");
5661 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5662 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5663 DRM_ERROR("Couldn't disable DPLL0\n");
5665 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5668 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5671 unsigned int required_vco;
5673 /* enable PCH reset handshake */
5674 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5675 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5677 /* enable PG1 and Misc I/O */
5678 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5680 /* DPLL0 already enabed !? */
5681 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5682 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5687 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5688 skl_dpll0_enable(dev_priv, required_vco);
5690 /* set CDCLK to the frequency the BIOS chose */
5691 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5693 /* enable DBUF power */
5694 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5695 POSTING_READ(DBUF_CTL);
5699 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5700 DRM_ERROR("DBuf power enable timeout\n");
5703 /* returns HPLL frequency in kHz */
5704 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5706 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5708 /* Obtain SKU information */
5709 mutex_lock(&dev_priv->sb_lock);
5710 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5711 CCK_FUSE_HPLL_FREQ_MASK;
5712 mutex_unlock(&dev_priv->sb_lock);
5714 return vco_freq[hpll_freq] * 1000;
5717 /* Adjust CDclk dividers to allow high res or save power if possible */
5718 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5723 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5724 != dev_priv->cdclk_freq);
5726 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5728 else if (cdclk == 266667)
5733 mutex_lock(&dev_priv->rps.hw_lock);
5734 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5735 val &= ~DSPFREQGUAR_MASK;
5736 val |= (cmd << DSPFREQGUAR_SHIFT);
5737 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5738 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5739 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5741 DRM_ERROR("timed out waiting for CDclk change\n");
5743 mutex_unlock(&dev_priv->rps.hw_lock);
5745 mutex_lock(&dev_priv->sb_lock);
5747 if (cdclk == 400000) {
5750 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5752 /* adjust cdclk divider */
5753 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5754 val &= ~DISPLAY_FREQUENCY_VALUES;
5756 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5758 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5759 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5761 DRM_ERROR("timed out waiting for CDclk change\n");
5764 /* adjust self-refresh exit latency value */
5765 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5769 * For high bandwidth configs, we set a higher latency in the bunit
5770 * so that the core display fetch happens in time to avoid underruns.
5772 if (cdclk == 400000)
5773 val |= 4500 / 250; /* 4.5 usec */
5775 val |= 3000 / 250; /* 3.0 usec */
5776 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5778 mutex_unlock(&dev_priv->sb_lock);
5780 intel_update_cdclk(dev);
5783 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5788 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5789 != dev_priv->cdclk_freq);
5798 MISSING_CASE(cdclk);
5803 * Specs are full of misinformation, but testing on actual
5804 * hardware has shown that we just need to write the desired
5805 * CCK divider into the Punit register.
5807 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5809 mutex_lock(&dev_priv->rps.hw_lock);
5810 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5811 val &= ~DSPFREQGUAR_MASK_CHV;
5812 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5813 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5814 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5815 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5817 DRM_ERROR("timed out waiting for CDclk change\n");
5819 mutex_unlock(&dev_priv->rps.hw_lock);
5821 intel_update_cdclk(dev);
5824 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5827 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5828 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5831 * Really only a few cases to deal with, as only 4 CDclks are supported:
5834 * 320/333MHz (depends on HPLL freq)
5836 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5837 * of the lower bin and adjust if needed.
5839 * We seem to get an unstable or solid color picture at 200MHz.
5840 * Not sure what's wrong. For now use 200MHz only when all pipes
5843 if (!IS_CHERRYVIEW(dev_priv) &&
5844 max_pixclk > freq_320*limit/100)
5846 else if (max_pixclk > 266667*limit/100)
5848 else if (max_pixclk > 0)
5854 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5859 * - remove the guardband, it's not needed on BXT
5860 * - set 19.2MHz bypass frequency if there are no active pipes
5862 if (max_pixclk > 576000*9/10)
5864 else if (max_pixclk > 384000*9/10)
5866 else if (max_pixclk > 288000*9/10)
5868 else if (max_pixclk > 144000*9/10)
5874 /* Compute the max pixel clock for new configuration. Uses atomic state if
5875 * that's non-NULL, look at current state otherwise. */
5876 static int intel_mode_max_pixclk(struct drm_device *dev,
5877 struct drm_atomic_state *state)
5879 struct intel_crtc *intel_crtc;
5880 struct intel_crtc_state *crtc_state;
5883 for_each_intel_crtc(dev, intel_crtc) {
5886 intel_atomic_get_crtc_state(state, intel_crtc);
5888 crtc_state = intel_crtc->config;
5889 if (IS_ERR(crtc_state))
5890 return PTR_ERR(crtc_state);
5892 if (!crtc_state->base.enable)
5895 max_pixclk = max(max_pixclk,
5896 crtc_state->base.adjusted_mode.crtc_clock);
5902 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5904 struct drm_i915_private *dev_priv = to_i915(state->dev);
5905 struct drm_crtc *crtc;
5906 struct drm_crtc_state *crtc_state;
5907 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5913 if (IS_VALLEYVIEW(dev_priv))
5914 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5916 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5918 if (cdclk == dev_priv->cdclk_freq)
5921 /* add all active pipes to the state */
5922 for_each_crtc(state->dev, crtc) {
5923 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5924 if (IS_ERR(crtc_state))
5925 return PTR_ERR(crtc_state);
5927 if (!crtc_state->active || needs_modeset(crtc_state))
5930 crtc_state->mode_changed = true;
5932 ret = drm_atomic_add_affected_connectors(state, crtc);
5936 ret = drm_atomic_add_affected_planes(state, crtc);
5944 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5946 unsigned int credits, default_credits;
5948 if (IS_CHERRYVIEW(dev_priv))
5949 default_credits = PFI_CREDIT(12);
5951 default_credits = PFI_CREDIT(8);
5953 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5954 /* CHV suggested value is 31 or 63 */
5955 if (IS_CHERRYVIEW(dev_priv))
5956 credits = PFI_CREDIT_63;
5958 credits = PFI_CREDIT(15);
5960 credits = default_credits;
5964 * WA - write default credits before re-programming
5965 * FIXME: should we also set the resend bit here?
5967 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5970 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5971 credits | PFI_CREDIT_RESEND);
5974 * FIXME is this guaranteed to clear
5975 * immediately or should we poll for it?
5977 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5980 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5982 struct drm_device *dev = old_state->dev;
5983 struct drm_i915_private *dev_priv = dev->dev_private;
5984 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5987 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5989 if (WARN_ON(max_pixclk < 0))
5992 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5994 if (req_cdclk != dev_priv->cdclk_freq) {
5996 * FIXME: We can end up here with all power domains off, yet
5997 * with a CDCLK frequency other than the minimum. To account
5998 * for this take the PIPE-A power domain, which covers the HW
5999 * blocks needed for the following programming. This can be
6000 * removed once it's guaranteed that we get here either with
6001 * the minimum CDCLK set, or the required power domains
6004 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6006 if (IS_CHERRYVIEW(dev))
6007 cherryview_set_cdclk(dev, req_cdclk);
6009 valleyview_set_cdclk(dev, req_cdclk);
6011 vlv_program_pfi_credits(dev_priv);
6013 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6017 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6019 struct drm_device *dev = crtc->dev;
6020 struct drm_i915_private *dev_priv = to_i915(dev);
6021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6022 struct intel_encoder *encoder;
6023 int pipe = intel_crtc->pipe;
6026 if (WARN_ON(intel_crtc->active))
6029 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6032 if (IS_CHERRYVIEW(dev))
6033 chv_prepare_pll(intel_crtc, intel_crtc->config);
6035 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6038 if (intel_crtc->config->has_dp_encoder)
6039 intel_dp_set_m_n(intel_crtc, M1_N1);
6041 intel_set_pipe_timings(intel_crtc);
6043 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6046 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6047 I915_WRITE(CHV_CANVAS(pipe), 0);
6050 i9xx_set_pipeconf(intel_crtc);
6052 intel_crtc->active = true;
6054 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6056 for_each_encoder_on_crtc(dev, crtc, encoder)
6057 if (encoder->pre_pll_enable)
6058 encoder->pre_pll_enable(encoder);
6061 if (IS_CHERRYVIEW(dev))
6062 chv_enable_pll(intel_crtc, intel_crtc->config);
6064 vlv_enable_pll(intel_crtc, intel_crtc->config);
6067 for_each_encoder_on_crtc(dev, crtc, encoder)
6068 if (encoder->pre_enable)
6069 encoder->pre_enable(encoder);
6071 i9xx_pfit_enable(intel_crtc);
6073 intel_crtc_load_lut(crtc);
6075 intel_update_watermarks(crtc);
6076 intel_enable_pipe(intel_crtc);
6078 assert_vblank_disabled(crtc);
6079 drm_crtc_vblank_on(crtc);
6081 for_each_encoder_on_crtc(dev, crtc, encoder)
6082 encoder->enable(encoder);
6085 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6087 struct drm_device *dev = crtc->base.dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6090 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6091 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6094 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = to_i915(dev);
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099 struct intel_encoder *encoder;
6100 int pipe = intel_crtc->pipe;
6102 if (WARN_ON(intel_crtc->active))
6105 i9xx_set_pll_dividers(intel_crtc);
6107 if (intel_crtc->config->has_dp_encoder)
6108 intel_dp_set_m_n(intel_crtc, M1_N1);
6110 intel_set_pipe_timings(intel_crtc);
6112 i9xx_set_pipeconf(intel_crtc);
6114 intel_crtc->active = true;
6117 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6119 for_each_encoder_on_crtc(dev, crtc, encoder)
6120 if (encoder->pre_enable)
6121 encoder->pre_enable(encoder);
6123 i9xx_enable_pll(intel_crtc);
6125 i9xx_pfit_enable(intel_crtc);
6127 intel_crtc_load_lut(crtc);
6129 intel_update_watermarks(crtc);
6130 intel_enable_pipe(intel_crtc);
6132 assert_vblank_disabled(crtc);
6133 drm_crtc_vblank_on(crtc);
6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 encoder->enable(encoder);
6139 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6144 if (!crtc->config->gmch_pfit.control)
6147 assert_pipe_disabled(dev_priv, crtc->pipe);
6149 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6150 I915_READ(PFIT_CONTROL));
6151 I915_WRITE(PFIT_CONTROL, 0);
6154 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6156 struct drm_device *dev = crtc->dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159 struct intel_encoder *encoder;
6160 int pipe = intel_crtc->pipe;
6162 if (WARN_ON(!intel_crtc->active))
6166 * On gen2 planes are double buffered but the pipe isn't, so we must
6167 * wait for planes to fully turn off before disabling the pipe.
6168 * We also need to wait on all gmch platforms because of the
6169 * self-refresh mode constraint explained above.
6171 intel_wait_for_vblank(dev, pipe);
6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 encoder->disable(encoder);
6176 drm_crtc_vblank_off(crtc);
6177 assert_vblank_disabled(crtc);
6179 intel_disable_pipe(intel_crtc);
6181 i9xx_pfit_disable(intel_crtc);
6183 for_each_encoder_on_crtc(dev, crtc, encoder)
6184 if (encoder->post_disable)
6185 encoder->post_disable(encoder);
6187 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6188 if (IS_CHERRYVIEW(dev))
6189 chv_disable_pll(dev_priv, pipe);
6190 else if (IS_VALLEYVIEW(dev))
6191 vlv_disable_pll(dev_priv, pipe);
6193 i9xx_disable_pll(intel_crtc);
6197 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6199 intel_crtc->active = false;
6200 intel_update_watermarks(crtc);
6202 mutex_lock(&dev->struct_mutex);
6203 intel_fbc_update(dev);
6204 mutex_unlock(&dev->struct_mutex);
6207 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6211 enum intel_display_power_domain domain;
6212 unsigned long domains;
6214 if (!intel_crtc->active)
6217 intel_crtc_disable_planes(crtc);
6218 dev_priv->display.crtc_disable(crtc);
6220 domains = intel_crtc->enabled_power_domains;
6221 for_each_power_domain(domain, domains)
6222 intel_display_power_put(dev_priv, domain);
6223 intel_crtc->enabled_power_domains = 0;
6227 * turn all crtc's off, but do not adjust state
6228 * This has to be paired with a call to intel_modeset_setup_hw_state.
6230 void intel_display_suspend(struct drm_device *dev)
6232 struct drm_crtc *crtc;
6234 for_each_crtc(dev, crtc)
6235 intel_crtc_disable_noatomic(crtc);
6238 /* Master function to enable/disable CRTC and corresponding power wells */
6239 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_mode_config *config = &dev->mode_config;
6243 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245 struct intel_crtc_state *pipe_config;
6246 struct drm_atomic_state *state;
6249 if (enable == intel_crtc->active)
6252 if (enable && !crtc->state->enable)
6255 /* this function should be called with drm_modeset_lock_all for now */
6258 lockdep_assert_held(&ctx->ww_ctx);
6260 state = drm_atomic_state_alloc(dev);
6261 if (WARN_ON(!state))
6264 state->acquire_ctx = ctx;
6265 state->allow_modeset = true;
6267 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6268 if (IS_ERR(pipe_config)) {
6269 ret = PTR_ERR(pipe_config);
6272 pipe_config->base.active = enable;
6274 ret = intel_set_mode(state);
6279 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6280 drm_atomic_state_free(state);
6285 * Sets the power management mode of the pipe and plane.
6287 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6289 struct drm_device *dev = crtc->dev;
6290 struct intel_encoder *intel_encoder;
6291 bool enable = false;
6293 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6294 enable |= intel_encoder->connectors_active;
6296 intel_crtc_control(crtc, enable);
6299 void intel_encoder_destroy(struct drm_encoder *encoder)
6301 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6303 drm_encoder_cleanup(encoder);
6304 kfree(intel_encoder);
6307 /* Simple dpms helper for encoders with just one connector, no cloning and only
6308 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6309 * state of the entire output pipe. */
6310 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6312 if (mode == DRM_MODE_DPMS_ON) {
6313 encoder->connectors_active = true;
6315 intel_crtc_update_dpms(encoder->base.crtc);
6317 encoder->connectors_active = false;
6319 intel_crtc_update_dpms(encoder->base.crtc);
6323 /* Cross check the actual hw state with our own modeset state tracking (and it's
6324 * internal consistency). */
6325 static void intel_connector_check_state(struct intel_connector *connector)
6327 if (connector->get_hw_state(connector)) {
6328 struct intel_encoder *encoder = connector->encoder;
6329 struct drm_crtc *crtc;
6330 bool encoder_enabled;
6333 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6334 connector->base.base.id,
6335 connector->base.name);
6337 /* there is no real hw state for MST connectors */
6338 if (connector->mst_port)
6341 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6342 "wrong connector dpms state\n");
6343 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6344 "active connector not linked to encoder\n");
6347 I915_STATE_WARN(!encoder->connectors_active,
6348 "encoder->connectors_active not set\n");
6350 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6351 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6352 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6355 crtc = encoder->base.crtc;
6357 I915_STATE_WARN(!crtc->state->enable,
6358 "crtc not enabled\n");
6359 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6360 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6361 "encoder active on the wrong pipe\n");
6366 int intel_connector_init(struct intel_connector *connector)
6368 struct drm_connector_state *connector_state;
6370 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6371 if (!connector_state)
6374 connector->base.state = connector_state;
6378 struct intel_connector *intel_connector_alloc(void)
6380 struct intel_connector *connector;
6382 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6386 if (intel_connector_init(connector) < 0) {
6394 /* Even simpler default implementation, if there's really no special case to
6396 void intel_connector_dpms(struct drm_connector *connector, int mode)
6398 /* All the simple cases only support two dpms states. */
6399 if (mode != DRM_MODE_DPMS_ON)
6400 mode = DRM_MODE_DPMS_OFF;
6402 if (mode == connector->dpms)
6405 connector->dpms = mode;
6407 /* Only need to change hw state when actually enabled */
6408 if (connector->encoder)
6409 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6411 intel_modeset_check_state(connector->dev);
6414 /* Simple connector->get_hw_state implementation for encoders that support only
6415 * one connector and no cloning and hence the encoder state determines the state
6416 * of the connector. */
6417 bool intel_connector_get_hw_state(struct intel_connector *connector)
6420 struct intel_encoder *encoder = connector->encoder;
6422 return encoder->get_hw_state(encoder, &pipe);
6425 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6427 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6428 return crtc_state->fdi_lanes;
6433 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6434 struct intel_crtc_state *pipe_config)
6436 struct drm_atomic_state *state = pipe_config->base.state;
6437 struct intel_crtc *other_crtc;
6438 struct intel_crtc_state *other_crtc_state;
6440 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6441 pipe_name(pipe), pipe_config->fdi_lanes);
6442 if (pipe_config->fdi_lanes > 4) {
6443 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6444 pipe_name(pipe), pipe_config->fdi_lanes);
6448 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6449 if (pipe_config->fdi_lanes > 2) {
6450 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6451 pipe_config->fdi_lanes);
6458 if (INTEL_INFO(dev)->num_pipes == 2)
6461 /* Ivybridge 3 pipe is really complicated */
6466 if (pipe_config->fdi_lanes <= 2)
6469 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6471 intel_atomic_get_crtc_state(state, other_crtc);
6472 if (IS_ERR(other_crtc_state))
6473 return PTR_ERR(other_crtc_state);
6475 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6476 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6482 if (pipe_config->fdi_lanes > 2) {
6483 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6484 pipe_name(pipe), pipe_config->fdi_lanes);
6488 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6490 intel_atomic_get_crtc_state(state, other_crtc);
6491 if (IS_ERR(other_crtc_state))
6492 return PTR_ERR(other_crtc_state);
6494 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6495 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6505 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6506 struct intel_crtc_state *pipe_config)
6508 struct drm_device *dev = intel_crtc->base.dev;
6509 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6510 int lane, link_bw, fdi_dotclock, ret;
6511 bool needs_recompute = false;
6514 /* FDI is a binary signal running at ~2.7GHz, encoding
6515 * each output octet as 10 bits. The actual frequency
6516 * is stored as a divider into a 100MHz clock, and the
6517 * mode pixel clock is stored in units of 1KHz.
6518 * Hence the bw of each lane in terms of the mode signal
6521 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6523 fdi_dotclock = adjusted_mode->crtc_clock;
6525 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6526 pipe_config->pipe_bpp);
6528 pipe_config->fdi_lanes = lane;
6530 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6531 link_bw, &pipe_config->fdi_m_n);
6533 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6534 intel_crtc->pipe, pipe_config);
6535 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6536 pipe_config->pipe_bpp -= 2*3;
6537 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6538 pipe_config->pipe_bpp);
6539 needs_recompute = true;
6540 pipe_config->bw_constrained = true;
6545 if (needs_recompute)
6551 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6552 struct intel_crtc_state *pipe_config)
6554 if (pipe_config->pipe_bpp > 24)
6557 /* HSW can handle pixel rate up to cdclk? */
6558 if (IS_HASWELL(dev_priv->dev))
6562 * We compare against max which means we must take
6563 * the increased cdclk requirement into account when
6564 * calculating the new cdclk.
6566 * Should measure whether using a lower cdclk w/o IPS
6568 return ilk_pipe_pixel_rate(pipe_config) <=
6569 dev_priv->max_cdclk_freq * 95 / 100;
6572 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6573 struct intel_crtc_state *pipe_config)
6575 struct drm_device *dev = crtc->base.dev;
6576 struct drm_i915_private *dev_priv = dev->dev_private;
6578 pipe_config->ips_enabled = i915.enable_ips &&
6579 hsw_crtc_supports_ips(crtc) &&
6580 pipe_config_supports_ips(dev_priv, pipe_config);
6583 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6584 struct intel_crtc_state *pipe_config)
6586 struct drm_device *dev = crtc->base.dev;
6587 struct drm_i915_private *dev_priv = dev->dev_private;
6588 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6591 /* FIXME should check pixel clock limits on all platforms */
6592 if (INTEL_INFO(dev)->gen < 4) {
6593 int clock_limit = dev_priv->max_cdclk_freq;
6596 * Enable pixel doubling when the dot clock
6597 * is > 90% of the (display) core speed.
6599 * GDG double wide on either pipe,
6600 * otherwise pipe A only.
6602 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6603 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6605 pipe_config->double_wide = true;
6608 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6613 * Pipe horizontal size must be even in:
6615 * - LVDS dual channel mode
6616 * - Double wide pipe
6618 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6619 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6620 pipe_config->pipe_src_w &= ~1;
6622 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6623 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6625 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6626 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6630 hsw_compute_ips_config(crtc, pipe_config);
6632 if (pipe_config->has_pch_encoder)
6633 return ironlake_fdi_compute_config(crtc, pipe_config);
6635 /* FIXME: remove below call once atomic mode set is place and all crtc
6636 * related checks called from atomic_crtc_check function */
6638 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6639 crtc, pipe_config->base.state);
6640 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6645 static int skylake_get_display_clock_speed(struct drm_device *dev)
6647 struct drm_i915_private *dev_priv = to_i915(dev);
6648 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6649 uint32_t cdctl = I915_READ(CDCLK_CTL);
6652 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6653 return 24000; /* 24MHz is the cd freq with NSSC ref */
6655 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6658 linkrate = (I915_READ(DPLL_CTRL1) &
6659 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6661 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6662 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6664 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6665 case CDCLK_FREQ_450_432:
6667 case CDCLK_FREQ_337_308:
6669 case CDCLK_FREQ_675_617:
6672 WARN(1, "Unknown cd freq selection\n");
6676 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6677 case CDCLK_FREQ_450_432:
6679 case CDCLK_FREQ_337_308:
6681 case CDCLK_FREQ_675_617:
6684 WARN(1, "Unknown cd freq selection\n");
6688 /* error case, do as if DPLL0 isn't enabled */
6692 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 uint32_t lcpll = I915_READ(LCPLL_CTL);
6696 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6698 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6702 else if (freq == LCPLL_CLK_FREQ_450)
6704 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6706 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6712 static int haswell_get_display_clock_speed(struct drm_device *dev)
6714 struct drm_i915_private *dev_priv = dev->dev_private;
6715 uint32_t lcpll = I915_READ(LCPLL_CTL);
6716 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6718 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6720 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6722 else if (freq == LCPLL_CLK_FREQ_450)
6724 else if (IS_HSW_ULT(dev))
6730 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6736 if (dev_priv->hpll_freq == 0)
6737 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6739 mutex_lock(&dev_priv->sb_lock);
6740 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6741 mutex_unlock(&dev_priv->sb_lock);
6743 divider = val & DISPLAY_FREQUENCY_VALUES;
6745 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6746 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6747 "cdclk change in progress\n");
6749 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6752 static int ilk_get_display_clock_speed(struct drm_device *dev)
6757 static int i945_get_display_clock_speed(struct drm_device *dev)
6762 static int i915_get_display_clock_speed(struct drm_device *dev)
6767 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6772 static int pnv_get_display_clock_speed(struct drm_device *dev)
6776 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6778 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6779 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6781 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6783 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6785 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6788 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6789 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6791 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6796 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6800 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6802 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6805 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6806 case GC_DISPLAY_CLOCK_333_MHZ:
6809 case GC_DISPLAY_CLOCK_190_200_MHZ:
6815 static int i865_get_display_clock_speed(struct drm_device *dev)
6820 static int i85x_get_display_clock_speed(struct drm_device *dev)
6825 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6826 * encoding is different :(
6827 * FIXME is this the right way to detect 852GM/852GMV?
6829 if (dev->pdev->revision == 0x1)
6832 pci_bus_read_config_word(dev->pdev->bus,
6833 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6835 /* Assume that the hardware is in the high speed state. This
6836 * should be the default.
6838 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6839 case GC_CLOCK_133_200:
6840 case GC_CLOCK_133_200_2:
6841 case GC_CLOCK_100_200:
6843 case GC_CLOCK_166_250:
6845 case GC_CLOCK_100_133:
6847 case GC_CLOCK_133_266:
6848 case GC_CLOCK_133_266_2:
6849 case GC_CLOCK_166_266:
6853 /* Shouldn't happen */
6857 static int i830_get_display_clock_speed(struct drm_device *dev)
6862 static unsigned int intel_hpll_vco(struct drm_device *dev)
6864 struct drm_i915_private *dev_priv = dev->dev_private;
6865 static const unsigned int blb_vco[8] = {
6872 static const unsigned int pnv_vco[8] = {
6879 static const unsigned int cl_vco[8] = {
6888 static const unsigned int elk_vco[8] = {
6894 static const unsigned int ctg_vco[8] = {
6902 const unsigned int *vco_table;
6906 /* FIXME other chipsets? */
6908 vco_table = ctg_vco;
6909 else if (IS_G4X(dev))
6910 vco_table = elk_vco;
6911 else if (IS_CRESTLINE(dev))
6913 else if (IS_PINEVIEW(dev))
6914 vco_table = pnv_vco;
6915 else if (IS_G33(dev))
6916 vco_table = blb_vco;
6920 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6922 vco = vco_table[tmp & 0x7];
6924 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6926 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6931 static int gm45_get_display_clock_speed(struct drm_device *dev)
6933 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6936 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6938 cdclk_sel = (tmp >> 12) & 0x1;
6944 return cdclk_sel ? 333333 : 222222;
6946 return cdclk_sel ? 320000 : 228571;
6948 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6953 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6955 static const uint8_t div_3200[] = { 16, 10, 8 };
6956 static const uint8_t div_4000[] = { 20, 12, 10 };
6957 static const uint8_t div_5333[] = { 24, 16, 14 };
6958 const uint8_t *div_table;
6959 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6962 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6964 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6966 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6971 div_table = div_3200;
6974 div_table = div_4000;
6977 div_table = div_5333;
6983 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6986 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6990 static int g33_get_display_clock_speed(struct drm_device *dev)
6992 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6993 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6994 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6995 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6996 const uint8_t *div_table;
6997 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7000 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7002 cdclk_sel = (tmp >> 4) & 0x7;
7004 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7009 div_table = div_3200;
7012 div_table = div_4000;
7015 div_table = div_4800;
7018 div_table = div_5333;
7024 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7027 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7032 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7034 while (*num > DATA_LINK_M_N_MASK ||
7035 *den > DATA_LINK_M_N_MASK) {
7041 static void compute_m_n(unsigned int m, unsigned int n,
7042 uint32_t *ret_m, uint32_t *ret_n)
7044 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7045 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7046 intel_reduce_m_n_ratio(ret_m, ret_n);
7050 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7051 int pixel_clock, int link_clock,
7052 struct intel_link_m_n *m_n)
7056 compute_m_n(bits_per_pixel * pixel_clock,
7057 link_clock * nlanes * 8,
7058 &m_n->gmch_m, &m_n->gmch_n);
7060 compute_m_n(pixel_clock, link_clock,
7061 &m_n->link_m, &m_n->link_n);
7064 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7066 if (i915.panel_use_ssc >= 0)
7067 return i915.panel_use_ssc != 0;
7068 return dev_priv->vbt.lvds_use_ssc
7069 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7072 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7075 struct drm_device *dev = crtc_state->base.crtc->dev;
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7079 WARN_ON(!crtc_state->base.state);
7081 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7083 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7084 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7085 refclk = dev_priv->vbt.lvds_ssc_freq;
7086 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7087 } else if (!IS_GEN2(dev)) {
7096 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7098 return (1 << dpll->n) << 16 | dpll->m2;
7101 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7103 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7106 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7107 struct intel_crtc_state *crtc_state,
7108 intel_clock_t *reduced_clock)
7110 struct drm_device *dev = crtc->base.dev;
7113 if (IS_PINEVIEW(dev)) {
7114 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7116 fp2 = pnv_dpll_compute_fp(reduced_clock);
7118 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7120 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7123 crtc_state->dpll_hw_state.fp0 = fp;
7125 crtc->lowfreq_avail = false;
7126 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7128 crtc_state->dpll_hw_state.fp1 = fp2;
7129 crtc->lowfreq_avail = true;
7131 crtc_state->dpll_hw_state.fp1 = fp;
7135 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7141 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7142 * and set it to a reasonable value instead.
7144 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145 reg_val &= 0xffffff00;
7146 reg_val |= 0x00000030;
7147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7149 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7150 reg_val &= 0x8cffffff;
7151 reg_val = 0x8c000000;
7152 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7154 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7155 reg_val &= 0xffffff00;
7156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7158 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7159 reg_val &= 0x00ffffff;
7160 reg_val |= 0xb0000000;
7161 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7164 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7165 struct intel_link_m_n *m_n)
7167 struct drm_device *dev = crtc->base.dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 int pipe = crtc->pipe;
7171 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7173 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7174 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7177 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7178 struct intel_link_m_n *m_n,
7179 struct intel_link_m_n *m2_n2)
7181 struct drm_device *dev = crtc->base.dev;
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 int pipe = crtc->pipe;
7184 enum transcoder transcoder = crtc->config->cpu_transcoder;
7186 if (INTEL_INFO(dev)->gen >= 5) {
7187 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7188 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7189 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7190 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7191 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7192 * for gen < 8) and if DRRS is supported (to make sure the
7193 * registers are not unnecessarily accessed).
7195 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7196 crtc->config->has_drrs) {
7197 I915_WRITE(PIPE_DATA_M2(transcoder),
7198 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7199 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7200 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7201 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7204 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7205 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7206 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7207 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7211 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7213 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7216 dp_m_n = &crtc->config->dp_m_n;
7217 dp_m2_n2 = &crtc->config->dp_m2_n2;
7218 } else if (m_n == M2_N2) {
7221 * M2_N2 registers are not supported. Hence m2_n2 divider value
7222 * needs to be programmed into M1_N1.
7224 dp_m_n = &crtc->config->dp_m2_n2;
7226 DRM_ERROR("Unsupported divider value\n");
7230 if (crtc->config->has_pch_encoder)
7231 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7233 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7236 static void vlv_update_pll(struct intel_crtc *crtc,
7237 struct intel_crtc_state *pipe_config)
7242 * Enable DPIO clock input. We should never disable the reference
7243 * clock for pipe B, since VGA hotplug / manual detection depends
7246 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7247 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7248 /* We should never disable this, set it here for state tracking */
7249 if (crtc->pipe == PIPE_B)
7250 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7251 dpll |= DPLL_VCO_ENABLE;
7252 pipe_config->dpll_hw_state.dpll = dpll;
7254 dpll_md = (pipe_config->pixel_multiplier - 1)
7255 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7256 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7259 static void vlv_prepare_pll(struct intel_crtc *crtc,
7260 const struct intel_crtc_state *pipe_config)
7262 struct drm_device *dev = crtc->base.dev;
7263 struct drm_i915_private *dev_priv = dev->dev_private;
7264 int pipe = crtc->pipe;
7266 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7267 u32 coreclk, reg_val;
7269 mutex_lock(&dev_priv->sb_lock);
7271 bestn = pipe_config->dpll.n;
7272 bestm1 = pipe_config->dpll.m1;
7273 bestm2 = pipe_config->dpll.m2;
7274 bestp1 = pipe_config->dpll.p1;
7275 bestp2 = pipe_config->dpll.p2;
7277 /* See eDP HDMI DPIO driver vbios notes doc */
7279 /* PLL B needs special handling */
7281 vlv_pllb_recal_opamp(dev_priv, pipe);
7283 /* Set up Tx target for periodic Rcomp update */
7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7286 /* Disable target IRef on PLL */
7287 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7288 reg_val &= 0x00ffffff;
7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7291 /* Disable fast lock */
7292 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7294 /* Set idtafcrecal before PLL is enabled */
7295 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7296 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7297 mdiv |= ((bestn << DPIO_N_SHIFT));
7298 mdiv |= (1 << DPIO_K_SHIFT);
7301 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7302 * but we don't support that).
7303 * Note: don't use the DAC post divider as it seems unstable.
7305 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7308 mdiv |= DPIO_ENABLE_CALIBRATION;
7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7311 /* Set HBR and RBR LPF coefficients */
7312 if (pipe_config->port_clock == 162000 ||
7313 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7314 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7321 if (pipe_config->has_dp_encoder) {
7322 /* Use SSC source */
7324 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7329 } else { /* HDMI or VGA */
7330 /* Use bend source */
7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7335 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7339 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7340 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7341 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7342 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7343 coreclk |= 0x01000000;
7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7347 mutex_unlock(&dev_priv->sb_lock);
7350 static void chv_update_pll(struct intel_crtc *crtc,
7351 struct intel_crtc_state *pipe_config)
7353 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7354 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7356 if (crtc->pipe != PIPE_A)
7357 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7359 pipe_config->dpll_hw_state.dpll_md =
7360 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7363 static void chv_prepare_pll(struct intel_crtc *crtc,
7364 const struct intel_crtc_state *pipe_config)
7366 struct drm_device *dev = crtc->base.dev;
7367 struct drm_i915_private *dev_priv = dev->dev_private;
7368 int pipe = crtc->pipe;
7369 int dpll_reg = DPLL(crtc->pipe);
7370 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7371 u32 loopfilter, tribuf_calcntr;
7372 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7376 bestn = pipe_config->dpll.n;
7377 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7378 bestm1 = pipe_config->dpll.m1;
7379 bestm2 = pipe_config->dpll.m2 >> 22;
7380 bestp1 = pipe_config->dpll.p1;
7381 bestp2 = pipe_config->dpll.p2;
7382 vco = pipe_config->dpll.vco;
7387 * Enable Refclk and SSC
7389 I915_WRITE(dpll_reg,
7390 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7392 mutex_lock(&dev_priv->sb_lock);
7394 /* p1 and p2 divider */
7395 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7396 5 << DPIO_CHV_S1_DIV_SHIFT |
7397 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7398 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7399 1 << DPIO_CHV_K_DIV_SHIFT);
7401 /* Feedback post-divider - m2 */
7402 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7404 /* Feedback refclk divider - n and m1 */
7405 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7406 DPIO_CHV_M1_DIV_BY_2 |
7407 1 << DPIO_CHV_N_DIV_SHIFT);
7409 /* M2 fraction division */
7411 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7413 /* M2 fraction division enable */
7414 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7415 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7416 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7418 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7419 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7421 /* Program digital lock detect threshold */
7422 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7423 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7424 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7425 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7427 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7431 if (vco == 5400000) {
7432 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7433 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7434 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435 tribuf_calcntr = 0x9;
7436 } else if (vco <= 6200000) {
7437 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7438 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7439 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440 tribuf_calcntr = 0x9;
7441 } else if (vco <= 6480000) {
7442 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7443 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7444 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445 tribuf_calcntr = 0x8;
7447 /* Not supported. Apply the same limits as in the max case */
7448 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7449 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7450 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7455 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7456 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7457 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7462 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7465 mutex_unlock(&dev_priv->sb_lock);
7469 * vlv_force_pll_on - forcibly enable just the PLL
7470 * @dev_priv: i915 private structure
7471 * @pipe: pipe PLL to enable
7472 * @dpll: PLL configuration
7474 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7475 * in cases where we need the PLL enabled even when @pipe is not going to
7478 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7479 const struct dpll *dpll)
7481 struct intel_crtc *crtc =
7482 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7483 struct intel_crtc_state pipe_config = {
7484 .base.crtc = &crtc->base,
7485 .pixel_multiplier = 1,
7489 if (IS_CHERRYVIEW(dev)) {
7490 chv_update_pll(crtc, &pipe_config);
7491 chv_prepare_pll(crtc, &pipe_config);
7492 chv_enable_pll(crtc, &pipe_config);
7494 vlv_update_pll(crtc, &pipe_config);
7495 vlv_prepare_pll(crtc, &pipe_config);
7496 vlv_enable_pll(crtc, &pipe_config);
7501 * vlv_force_pll_off - forcibly disable just the PLL
7502 * @dev_priv: i915 private structure
7503 * @pipe: pipe PLL to disable
7505 * Disable the PLL for @pipe. To be used in cases where we need
7506 * the PLL enabled even when @pipe is not going to be enabled.
7508 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7510 if (IS_CHERRYVIEW(dev))
7511 chv_disable_pll(to_i915(dev), pipe);
7513 vlv_disable_pll(to_i915(dev), pipe);
7516 static void i9xx_update_pll(struct intel_crtc *crtc,
7517 struct intel_crtc_state *crtc_state,
7518 intel_clock_t *reduced_clock,
7521 struct drm_device *dev = crtc->base.dev;
7522 struct drm_i915_private *dev_priv = dev->dev_private;
7525 struct dpll *clock = &crtc_state->dpll;
7527 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7529 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7530 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7532 dpll = DPLL_VGA_MODE_DIS;
7534 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7535 dpll |= DPLLB_MODE_LVDS;
7537 dpll |= DPLLB_MODE_DAC_SERIAL;
7539 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7540 dpll |= (crtc_state->pixel_multiplier - 1)
7541 << SDVO_MULTIPLIER_SHIFT_HIRES;
7545 dpll |= DPLL_SDVO_HIGH_SPEED;
7547 if (crtc_state->has_dp_encoder)
7548 dpll |= DPLL_SDVO_HIGH_SPEED;
7550 /* compute bitmask from p1 value */
7551 if (IS_PINEVIEW(dev))
7552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7555 if (IS_G4X(dev) && reduced_clock)
7556 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7558 switch (clock->p2) {
7560 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7563 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7566 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7569 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7572 if (INTEL_INFO(dev)->gen >= 4)
7573 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7575 if (crtc_state->sdvo_tv_clock)
7576 dpll |= PLL_REF_INPUT_TVCLKINBC;
7577 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7578 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7581 dpll |= PLL_REF_INPUT_DREFCLK;
7583 dpll |= DPLL_VCO_ENABLE;
7584 crtc_state->dpll_hw_state.dpll = dpll;
7586 if (INTEL_INFO(dev)->gen >= 4) {
7587 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7589 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7593 static void i8xx_update_pll(struct intel_crtc *crtc,
7594 struct intel_crtc_state *crtc_state,
7595 intel_clock_t *reduced_clock,
7598 struct drm_device *dev = crtc->base.dev;
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7601 struct dpll *clock = &crtc_state->dpll;
7603 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7605 dpll = DPLL_VGA_MODE_DIS;
7607 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7608 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611 dpll |= PLL_P1_DIVIDE_BY_TWO;
7613 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7615 dpll |= PLL_P2_DIVIDE_BY_4;
7618 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7619 dpll |= DPLL_DVO_2X_MODE;
7621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7622 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7623 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7625 dpll |= PLL_REF_INPUT_DREFCLK;
7627 dpll |= DPLL_VCO_ENABLE;
7628 crtc_state->dpll_hw_state.dpll = dpll;
7631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7633 struct drm_device *dev = intel_crtc->base.dev;
7634 struct drm_i915_private *dev_priv = dev->dev_private;
7635 enum pipe pipe = intel_crtc->pipe;
7636 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7637 struct drm_display_mode *adjusted_mode =
7638 &intel_crtc->config->base.adjusted_mode;
7639 uint32_t crtc_vtotal, crtc_vblank_end;
7642 /* We need to be careful not to changed the adjusted mode, for otherwise
7643 * the hw state checker will get angry at the mismatch. */
7644 crtc_vtotal = adjusted_mode->crtc_vtotal;
7645 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7647 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7648 /* the chip adds 2 halflines automatically */
7650 crtc_vblank_end -= 1;
7652 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7653 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7655 vsyncshift = adjusted_mode->crtc_hsync_start -
7656 adjusted_mode->crtc_htotal / 2;
7658 vsyncshift += adjusted_mode->crtc_htotal;
7661 if (INTEL_INFO(dev)->gen > 3)
7662 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7664 I915_WRITE(HTOTAL(cpu_transcoder),
7665 (adjusted_mode->crtc_hdisplay - 1) |
7666 ((adjusted_mode->crtc_htotal - 1) << 16));
7667 I915_WRITE(HBLANK(cpu_transcoder),
7668 (adjusted_mode->crtc_hblank_start - 1) |
7669 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7670 I915_WRITE(HSYNC(cpu_transcoder),
7671 (adjusted_mode->crtc_hsync_start - 1) |
7672 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7674 I915_WRITE(VTOTAL(cpu_transcoder),
7675 (adjusted_mode->crtc_vdisplay - 1) |
7676 ((crtc_vtotal - 1) << 16));
7677 I915_WRITE(VBLANK(cpu_transcoder),
7678 (adjusted_mode->crtc_vblank_start - 1) |
7679 ((crtc_vblank_end - 1) << 16));
7680 I915_WRITE(VSYNC(cpu_transcoder),
7681 (adjusted_mode->crtc_vsync_start - 1) |
7682 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7684 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7685 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7686 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7688 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7689 (pipe == PIPE_B || pipe == PIPE_C))
7690 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7692 /* pipesrc controls the size that is scaled from, which should
7693 * always be the user's requested size.
7695 I915_WRITE(PIPESRC(pipe),
7696 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7697 (intel_crtc->config->pipe_src_h - 1));
7700 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7701 struct intel_crtc_state *pipe_config)
7703 struct drm_device *dev = crtc->base.dev;
7704 struct drm_i915_private *dev_priv = dev->dev_private;
7705 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7708 tmp = I915_READ(HTOTAL(cpu_transcoder));
7709 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7710 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7711 tmp = I915_READ(HBLANK(cpu_transcoder));
7712 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7713 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7714 tmp = I915_READ(HSYNC(cpu_transcoder));
7715 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7716 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7718 tmp = I915_READ(VTOTAL(cpu_transcoder));
7719 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7720 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7721 tmp = I915_READ(VBLANK(cpu_transcoder));
7722 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7723 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7724 tmp = I915_READ(VSYNC(cpu_transcoder));
7725 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7726 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7728 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7729 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7730 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7731 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7734 tmp = I915_READ(PIPESRC(crtc->pipe));
7735 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7736 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7738 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7739 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7742 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7743 struct intel_crtc_state *pipe_config)
7745 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7746 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7747 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7748 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7750 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7751 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7752 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7753 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7755 mode->flags = pipe_config->base.adjusted_mode.flags;
7757 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7758 mode->flags |= pipe_config->base.adjusted_mode.flags;
7761 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7763 struct drm_device *dev = intel_crtc->base.dev;
7764 struct drm_i915_private *dev_priv = dev->dev_private;
7769 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7770 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7771 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7773 if (intel_crtc->config->double_wide)
7774 pipeconf |= PIPECONF_DOUBLE_WIDE;
7776 /* only g4x and later have fancy bpc/dither controls */
7777 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7778 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7779 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7780 pipeconf |= PIPECONF_DITHER_EN |
7781 PIPECONF_DITHER_TYPE_SP;
7783 switch (intel_crtc->config->pipe_bpp) {
7785 pipeconf |= PIPECONF_6BPC;
7788 pipeconf |= PIPECONF_8BPC;
7791 pipeconf |= PIPECONF_10BPC;
7794 /* Case prevented by intel_choose_pipe_bpp_dither. */
7799 if (HAS_PIPE_CXSR(dev)) {
7800 if (intel_crtc->lowfreq_avail) {
7801 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7802 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7804 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7808 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7809 if (INTEL_INFO(dev)->gen < 4 ||
7810 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7811 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7813 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7815 pipeconf |= PIPECONF_PROGRESSIVE;
7817 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7818 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7820 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7821 POSTING_READ(PIPECONF(intel_crtc->pipe));
7824 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7825 struct intel_crtc_state *crtc_state)
7827 struct drm_device *dev = crtc->base.dev;
7828 struct drm_i915_private *dev_priv = dev->dev_private;
7829 int refclk, num_connectors = 0;
7830 intel_clock_t clock, reduced_clock;
7831 bool ok, has_reduced_clock = false;
7832 bool is_lvds = false, is_dsi = false;
7833 struct intel_encoder *encoder;
7834 const intel_limit_t *limit;
7835 struct drm_atomic_state *state = crtc_state->base.state;
7836 struct drm_connector *connector;
7837 struct drm_connector_state *connector_state;
7840 memset(&crtc_state->dpll_hw_state, 0,
7841 sizeof(crtc_state->dpll_hw_state));
7843 for_each_connector_in_state(state, connector, connector_state, i) {
7844 if (connector_state->crtc != &crtc->base)
7847 encoder = to_intel_encoder(connector_state->best_encoder);
7849 switch (encoder->type) {
7850 case INTEL_OUTPUT_LVDS:
7853 case INTEL_OUTPUT_DSI:
7866 if (!crtc_state->clock_set) {
7867 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7870 * Returns a set of divisors for the desired target clock with
7871 * the given refclk, or FALSE. The returned values represent
7872 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7875 limit = intel_limit(crtc_state, refclk);
7876 ok = dev_priv->display.find_dpll(limit, crtc_state,
7877 crtc_state->port_clock,
7878 refclk, NULL, &clock);
7880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7884 if (is_lvds && dev_priv->lvds_downclock_avail) {
7886 * Ensure we match the reduced clock's P to the target
7887 * clock. If the clocks don't match, we can't switch
7888 * the display clock by using the FP0/FP1. In such case
7889 * we will disable the LVDS downclock feature.
7892 dev_priv->display.find_dpll(limit, crtc_state,
7893 dev_priv->lvds_downclock,
7897 /* Compat-code for transition, will disappear. */
7898 crtc_state->dpll.n = clock.n;
7899 crtc_state->dpll.m1 = clock.m1;
7900 crtc_state->dpll.m2 = clock.m2;
7901 crtc_state->dpll.p1 = clock.p1;
7902 crtc_state->dpll.p2 = clock.p2;
7906 i8xx_update_pll(crtc, crtc_state,
7907 has_reduced_clock ? &reduced_clock : NULL,
7909 } else if (IS_CHERRYVIEW(dev)) {
7910 chv_update_pll(crtc, crtc_state);
7911 } else if (IS_VALLEYVIEW(dev)) {
7912 vlv_update_pll(crtc, crtc_state);
7914 i9xx_update_pll(crtc, crtc_state,
7915 has_reduced_clock ? &reduced_clock : NULL,
7922 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7923 struct intel_crtc_state *pipe_config)
7925 struct drm_device *dev = crtc->base.dev;
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7929 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7932 tmp = I915_READ(PFIT_CONTROL);
7933 if (!(tmp & PFIT_ENABLE))
7936 /* Check whether the pfit is attached to our pipe. */
7937 if (INTEL_INFO(dev)->gen < 4) {
7938 if (crtc->pipe != PIPE_B)
7941 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7945 pipe_config->gmch_pfit.control = tmp;
7946 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7947 if (INTEL_INFO(dev)->gen < 5)
7948 pipe_config->gmch_pfit.lvds_border_bits =
7949 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7952 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7953 struct intel_crtc_state *pipe_config)
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 int pipe = pipe_config->cpu_transcoder;
7958 intel_clock_t clock;
7960 int refclk = 100000;
7962 /* In case of MIPI DPLL will not even be used */
7963 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7966 mutex_lock(&dev_priv->sb_lock);
7967 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7968 mutex_unlock(&dev_priv->sb_lock);
7970 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7971 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7972 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7973 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7974 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7976 vlv_clock(refclk, &clock);
7978 /* clock.dot is the fast clock */
7979 pipe_config->port_clock = clock.dot / 5;
7983 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7984 struct intel_initial_plane_config *plane_config)
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 u32 val, base, offset;
7989 int pipe = crtc->pipe, plane = crtc->plane;
7990 int fourcc, pixel_format;
7991 unsigned int aligned_height;
7992 struct drm_framebuffer *fb;
7993 struct intel_framebuffer *intel_fb;
7995 val = I915_READ(DSPCNTR(plane));
7996 if (!(val & DISPLAY_PLANE_ENABLE))
7999 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8001 DRM_DEBUG_KMS("failed to alloc fb\n");
8005 fb = &intel_fb->base;
8007 if (INTEL_INFO(dev)->gen >= 4) {
8008 if (val & DISPPLANE_TILED) {
8009 plane_config->tiling = I915_TILING_X;
8010 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8014 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8015 fourcc = i9xx_format_to_fourcc(pixel_format);
8016 fb->pixel_format = fourcc;
8017 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8019 if (INTEL_INFO(dev)->gen >= 4) {
8020 if (plane_config->tiling)
8021 offset = I915_READ(DSPTILEOFF(plane));
8023 offset = I915_READ(DSPLINOFF(plane));
8024 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8026 base = I915_READ(DSPADDR(plane));
8028 plane_config->base = base;
8030 val = I915_READ(PIPESRC(pipe));
8031 fb->width = ((val >> 16) & 0xfff) + 1;
8032 fb->height = ((val >> 0) & 0xfff) + 1;
8034 val = I915_READ(DSPSTRIDE(pipe));
8035 fb->pitches[0] = val & 0xffffffc0;
8037 aligned_height = intel_fb_align_height(dev, fb->height,
8041 plane_config->size = fb->pitches[0] * aligned_height;
8043 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8044 pipe_name(pipe), plane, fb->width, fb->height,
8045 fb->bits_per_pixel, base, fb->pitches[0],
8046 plane_config->size);
8048 plane_config->fb = intel_fb;
8051 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8052 struct intel_crtc_state *pipe_config)
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 int pipe = pipe_config->cpu_transcoder;
8057 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8058 intel_clock_t clock;
8059 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8060 int refclk = 100000;
8062 mutex_lock(&dev_priv->sb_lock);
8063 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8064 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8065 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8066 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8067 mutex_unlock(&dev_priv->sb_lock);
8069 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8070 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8071 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8072 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8073 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8075 chv_clock(refclk, &clock);
8077 /* clock.dot is the fast clock */
8078 pipe_config->port_clock = clock.dot / 5;
8081 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8082 struct intel_crtc_state *pipe_config)
8084 struct drm_device *dev = crtc->base.dev;
8085 struct drm_i915_private *dev_priv = dev->dev_private;
8088 if (!intel_display_power_is_enabled(dev_priv,
8089 POWER_DOMAIN_PIPE(crtc->pipe)))
8092 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8093 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8095 tmp = I915_READ(PIPECONF(crtc->pipe));
8096 if (!(tmp & PIPECONF_ENABLE))
8099 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8100 switch (tmp & PIPECONF_BPC_MASK) {
8102 pipe_config->pipe_bpp = 18;
8105 pipe_config->pipe_bpp = 24;
8107 case PIPECONF_10BPC:
8108 pipe_config->pipe_bpp = 30;
8115 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8116 pipe_config->limited_color_range = true;
8118 if (INTEL_INFO(dev)->gen < 4)
8119 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8121 intel_get_pipe_timings(crtc, pipe_config);
8123 i9xx_get_pfit_config(crtc, pipe_config);
8125 if (INTEL_INFO(dev)->gen >= 4) {
8126 tmp = I915_READ(DPLL_MD(crtc->pipe));
8127 pipe_config->pixel_multiplier =
8128 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8129 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8130 pipe_config->dpll_hw_state.dpll_md = tmp;
8131 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8132 tmp = I915_READ(DPLL(crtc->pipe));
8133 pipe_config->pixel_multiplier =
8134 ((tmp & SDVO_MULTIPLIER_MASK)
8135 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8137 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8138 * port and will be fixed up in the encoder->get_config
8140 pipe_config->pixel_multiplier = 1;
8142 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8143 if (!IS_VALLEYVIEW(dev)) {
8145 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8146 * on 830. Filter it out here so that we don't
8147 * report errors due to that.
8150 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8152 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8153 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8155 /* Mask out read-only status bits. */
8156 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8157 DPLL_PORTC_READY_MASK |
8158 DPLL_PORTB_READY_MASK);
8161 if (IS_CHERRYVIEW(dev))
8162 chv_crtc_clock_get(crtc, pipe_config);
8163 else if (IS_VALLEYVIEW(dev))
8164 vlv_crtc_clock_get(crtc, pipe_config);
8166 i9xx_crtc_clock_get(crtc, pipe_config);
8171 static void ironlake_init_pch_refclk(struct drm_device *dev)
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 struct intel_encoder *encoder;
8176 bool has_lvds = false;
8177 bool has_cpu_edp = false;
8178 bool has_panel = false;
8179 bool has_ck505 = false;
8180 bool can_ssc = false;
8182 /* We need to take the global config into account */
8183 for_each_intel_encoder(dev, encoder) {
8184 switch (encoder->type) {
8185 case INTEL_OUTPUT_LVDS:
8189 case INTEL_OUTPUT_EDP:
8191 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8199 if (HAS_PCH_IBX(dev)) {
8200 has_ck505 = dev_priv->vbt.display_clock_mode;
8201 can_ssc = has_ck505;
8207 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208 has_panel, has_lvds, has_ck505);
8210 /* Ironlake: try to setup display ref clock before DPLL
8211 * enabling. This is only under driver's control after
8212 * PCH B stepping, previous chipset stepping should be
8213 * ignoring this setting.
8215 val = I915_READ(PCH_DREF_CONTROL);
8217 /* As we must carefully and slowly disable/enable each source in turn,
8218 * compute the final state we want first and check if we need to
8219 * make any changes at all.
8222 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8224 final |= DREF_NONSPREAD_CK505_ENABLE;
8226 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8228 final &= ~DREF_SSC_SOURCE_MASK;
8229 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230 final &= ~DREF_SSC1_ENABLE;
8233 final |= DREF_SSC_SOURCE_ENABLE;
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236 final |= DREF_SSC1_ENABLE;
8239 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8242 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8244 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8246 final |= DREF_SSC_SOURCE_DISABLE;
8247 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253 /* Always enable nonspread source */
8254 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8257 val |= DREF_NONSPREAD_CK505_ENABLE;
8259 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8262 val &= ~DREF_SSC_SOURCE_MASK;
8263 val |= DREF_SSC_SOURCE_ENABLE;
8265 /* SSC must be turned on before enabling the CPU output */
8266 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8267 DRM_DEBUG_KMS("Using SSC on panel\n");
8268 val |= DREF_SSC1_ENABLE;
8270 val &= ~DREF_SSC1_ENABLE;
8272 /* Get SSC going before enabling the outputs */
8273 I915_WRITE(PCH_DREF_CONTROL, val);
8274 POSTING_READ(PCH_DREF_CONTROL);
8277 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8279 /* Enable CPU source on CPU attached eDP */
8281 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8282 DRM_DEBUG_KMS("Using SSC on eDP\n");
8283 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8285 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8287 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8289 I915_WRITE(PCH_DREF_CONTROL, val);
8290 POSTING_READ(PCH_DREF_CONTROL);
8293 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8295 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297 /* Turn off CPU output */
8298 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8300 I915_WRITE(PCH_DREF_CONTROL, val);
8301 POSTING_READ(PCH_DREF_CONTROL);
8304 /* Turn off the SSC source */
8305 val &= ~DREF_SSC_SOURCE_MASK;
8306 val |= DREF_SSC_SOURCE_DISABLE;
8309 val &= ~DREF_SSC1_ENABLE;
8311 I915_WRITE(PCH_DREF_CONTROL, val);
8312 POSTING_READ(PCH_DREF_CONTROL);
8316 BUG_ON(val != final);
8319 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8323 tmp = I915_READ(SOUTH_CHICKEN2);
8324 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325 I915_WRITE(SOUTH_CHICKEN2, tmp);
8327 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329 DRM_ERROR("FDI mPHY reset assert timeout\n");
8331 tmp = I915_READ(SOUTH_CHICKEN2);
8332 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333 I915_WRITE(SOUTH_CHICKEN2, tmp);
8335 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8340 /* WaMPhyProgramming:hsw */
8341 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8345 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346 tmp &= ~(0xFF << 24);
8347 tmp |= (0x12 << 24);
8348 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8350 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8352 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8354 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8356 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8358 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8362 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8366 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8369 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8371 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8374 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8376 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8379 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8381 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8384 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8386 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387 tmp &= ~(0xFF << 16);
8388 tmp |= (0x1C << 16);
8389 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8391 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392 tmp &= ~(0xFF << 16);
8393 tmp |= (0x1C << 16);
8394 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8396 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8398 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8400 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8402 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8404 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405 tmp &= ~(0xF << 28);
8407 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8409 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410 tmp &= ~(0xF << 28);
8412 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8415 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8416 * Programming" based on the parameters passed:
8417 * - Sequence to enable CLKOUT_DP
8418 * - Sequence to enable CLKOUT_DP without spread
8419 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8421 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8424 struct drm_i915_private *dev_priv = dev->dev_private;
8427 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8429 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8430 with_fdi, "LP PCH doesn't have FDI\n"))
8433 mutex_lock(&dev_priv->sb_lock);
8435 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8436 tmp &= ~SBI_SSCCTL_DISABLE;
8437 tmp |= SBI_SSCCTL_PATHALT;
8438 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8443 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8444 tmp &= ~SBI_SSCCTL_PATHALT;
8445 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8448 lpt_reset_fdi_mphy(dev_priv);
8449 lpt_program_fdi_mphy(dev_priv);
8453 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8454 SBI_GEN0 : SBI_DBUFF0;
8455 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8459 mutex_unlock(&dev_priv->sb_lock);
8462 /* Sequence to disable CLKOUT_DP */
8463 static void lpt_disable_clkout_dp(struct drm_device *dev)
8465 struct drm_i915_private *dev_priv = dev->dev_private;
8468 mutex_lock(&dev_priv->sb_lock);
8470 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8471 SBI_GEN0 : SBI_DBUFF0;
8472 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8473 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8474 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8476 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8477 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8478 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8479 tmp |= SBI_SSCCTL_PATHALT;
8480 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8483 tmp |= SBI_SSCCTL_DISABLE;
8484 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8487 mutex_unlock(&dev_priv->sb_lock);
8490 static void lpt_init_pch_refclk(struct drm_device *dev)
8492 struct intel_encoder *encoder;
8493 bool has_vga = false;
8495 for_each_intel_encoder(dev, encoder) {
8496 switch (encoder->type) {
8497 case INTEL_OUTPUT_ANALOG:
8506 lpt_enable_clkout_dp(dev, true, true);
8508 lpt_disable_clkout_dp(dev);
8512 * Initialize reference clocks when the driver loads
8514 void intel_init_pch_refclk(struct drm_device *dev)
8516 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8517 ironlake_init_pch_refclk(dev);
8518 else if (HAS_PCH_LPT(dev))
8519 lpt_init_pch_refclk(dev);
8522 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8524 struct drm_device *dev = crtc_state->base.crtc->dev;
8525 struct drm_i915_private *dev_priv = dev->dev_private;
8526 struct drm_atomic_state *state = crtc_state->base.state;
8527 struct drm_connector *connector;
8528 struct drm_connector_state *connector_state;
8529 struct intel_encoder *encoder;
8530 int num_connectors = 0, i;
8531 bool is_lvds = false;
8533 for_each_connector_in_state(state, connector, connector_state, i) {
8534 if (connector_state->crtc != crtc_state->base.crtc)
8537 encoder = to_intel_encoder(connector_state->best_encoder);
8539 switch (encoder->type) {
8540 case INTEL_OUTPUT_LVDS:
8549 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8550 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8551 dev_priv->vbt.lvds_ssc_freq);
8552 return dev_priv->vbt.lvds_ssc_freq;
8558 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8560 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8562 int pipe = intel_crtc->pipe;
8567 switch (intel_crtc->config->pipe_bpp) {
8569 val |= PIPECONF_6BPC;
8572 val |= PIPECONF_8BPC;
8575 val |= PIPECONF_10BPC;
8578 val |= PIPECONF_12BPC;
8581 /* Case prevented by intel_choose_pipe_bpp_dither. */
8585 if (intel_crtc->config->dither)
8586 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8588 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8589 val |= PIPECONF_INTERLACED_ILK;
8591 val |= PIPECONF_PROGRESSIVE;
8593 if (intel_crtc->config->limited_color_range)
8594 val |= PIPECONF_COLOR_RANGE_SELECT;
8596 I915_WRITE(PIPECONF(pipe), val);
8597 POSTING_READ(PIPECONF(pipe));
8601 * Set up the pipe CSC unit.
8603 * Currently only full range RGB to limited range RGB conversion
8604 * is supported, but eventually this should handle various
8605 * RGB<->YCbCr scenarios as well.
8607 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8609 struct drm_device *dev = crtc->dev;
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612 int pipe = intel_crtc->pipe;
8613 uint16_t coeff = 0x7800; /* 1.0 */
8616 * TODO: Check what kind of values actually come out of the pipe
8617 * with these coeff/postoff values and adjust to get the best
8618 * accuracy. Perhaps we even need to take the bpc value into
8622 if (intel_crtc->config->limited_color_range)
8623 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8626 * GY/GU and RY/RU should be the other way around according
8627 * to BSpec, but reality doesn't agree. Just set them up in
8628 * a way that results in the correct picture.
8630 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8631 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8633 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8634 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8636 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8637 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8639 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8640 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8641 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8643 if (INTEL_INFO(dev)->gen > 6) {
8644 uint16_t postoff = 0;
8646 if (intel_crtc->config->limited_color_range)
8647 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8649 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8650 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8651 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8653 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8655 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8657 if (intel_crtc->config->limited_color_range)
8658 mode |= CSC_BLACK_SCREEN_OFFSET;
8660 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8664 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8666 struct drm_device *dev = crtc->dev;
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8669 enum pipe pipe = intel_crtc->pipe;
8670 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8675 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8676 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8678 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8679 val |= PIPECONF_INTERLACED_ILK;
8681 val |= PIPECONF_PROGRESSIVE;
8683 I915_WRITE(PIPECONF(cpu_transcoder), val);
8684 POSTING_READ(PIPECONF(cpu_transcoder));
8686 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8687 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8689 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8692 switch (intel_crtc->config->pipe_bpp) {
8694 val |= PIPEMISC_DITHER_6_BPC;
8697 val |= PIPEMISC_DITHER_8_BPC;
8700 val |= PIPEMISC_DITHER_10_BPC;
8703 val |= PIPEMISC_DITHER_12_BPC;
8706 /* Case prevented by pipe_config_set_bpp. */
8710 if (intel_crtc->config->dither)
8711 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8713 I915_WRITE(PIPEMISC(pipe), val);
8717 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8718 struct intel_crtc_state *crtc_state,
8719 intel_clock_t *clock,
8720 bool *has_reduced_clock,
8721 intel_clock_t *reduced_clock)
8723 struct drm_device *dev = crtc->dev;
8724 struct drm_i915_private *dev_priv = dev->dev_private;
8726 const intel_limit_t *limit;
8727 bool ret, is_lvds = false;
8729 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8731 refclk = ironlake_get_refclk(crtc_state);
8734 * Returns a set of divisors for the desired target clock with the given
8735 * refclk, or FALSE. The returned values represent the clock equation:
8736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8738 limit = intel_limit(crtc_state, refclk);
8739 ret = dev_priv->display.find_dpll(limit, crtc_state,
8740 crtc_state->port_clock,
8741 refclk, NULL, clock);
8745 if (is_lvds && dev_priv->lvds_downclock_avail) {
8747 * Ensure we match the reduced clock's P to the target clock.
8748 * If the clocks don't match, we can't switch the display clock
8749 * by using the FP0/FP1. In such case we will disable the LVDS
8750 * downclock feature.
8752 *has_reduced_clock =
8753 dev_priv->display.find_dpll(limit, crtc_state,
8754 dev_priv->lvds_downclock,
8762 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8765 * Account for spread spectrum to avoid
8766 * oversubscribing the link. Max center spread
8767 * is 2.5%; use 5% for safety's sake.
8769 u32 bps = target_clock * bpp * 21 / 20;
8770 return DIV_ROUND_UP(bps, link_bw * 8);
8773 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8775 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8778 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8779 struct intel_crtc_state *crtc_state,
8781 intel_clock_t *reduced_clock, u32 *fp2)
8783 struct drm_crtc *crtc = &intel_crtc->base;
8784 struct drm_device *dev = crtc->dev;
8785 struct drm_i915_private *dev_priv = dev->dev_private;
8786 struct drm_atomic_state *state = crtc_state->base.state;
8787 struct drm_connector *connector;
8788 struct drm_connector_state *connector_state;
8789 struct intel_encoder *encoder;
8791 int factor, num_connectors = 0, i;
8792 bool is_lvds = false, is_sdvo = false;
8794 for_each_connector_in_state(state, connector, connector_state, i) {
8795 if (connector_state->crtc != crtc_state->base.crtc)
8798 encoder = to_intel_encoder(connector_state->best_encoder);
8800 switch (encoder->type) {
8801 case INTEL_OUTPUT_LVDS:
8804 case INTEL_OUTPUT_SDVO:
8805 case INTEL_OUTPUT_HDMI:
8815 /* Enable autotuning of the PLL clock (if permissible) */
8818 if ((intel_panel_use_ssc(dev_priv) &&
8819 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8820 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8822 } else if (crtc_state->sdvo_tv_clock)
8825 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8828 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8834 dpll |= DPLLB_MODE_LVDS;
8836 dpll |= DPLLB_MODE_DAC_SERIAL;
8838 dpll |= (crtc_state->pixel_multiplier - 1)
8839 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8842 dpll |= DPLL_SDVO_HIGH_SPEED;
8843 if (crtc_state->has_dp_encoder)
8844 dpll |= DPLL_SDVO_HIGH_SPEED;
8846 /* compute bitmask from p1 value */
8847 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8849 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8851 switch (crtc_state->dpll.p2) {
8853 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8856 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8859 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8862 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8866 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8867 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8869 dpll |= PLL_REF_INPUT_DREFCLK;
8871 return dpll | DPLL_VCO_ENABLE;
8874 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8875 struct intel_crtc_state *crtc_state)
8877 struct drm_device *dev = crtc->base.dev;
8878 intel_clock_t clock, reduced_clock;
8879 u32 dpll = 0, fp = 0, fp2 = 0;
8880 bool ok, has_reduced_clock = false;
8881 bool is_lvds = false;
8882 struct intel_shared_dpll *pll;
8884 memset(&crtc_state->dpll_hw_state, 0,
8885 sizeof(crtc_state->dpll_hw_state));
8887 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8889 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8890 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8892 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8893 &has_reduced_clock, &reduced_clock);
8894 if (!ok && !crtc_state->clock_set) {
8895 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8898 /* Compat-code for transition, will disappear. */
8899 if (!crtc_state->clock_set) {
8900 crtc_state->dpll.n = clock.n;
8901 crtc_state->dpll.m1 = clock.m1;
8902 crtc_state->dpll.m2 = clock.m2;
8903 crtc_state->dpll.p1 = clock.p1;
8904 crtc_state->dpll.p2 = clock.p2;
8907 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8908 if (crtc_state->has_pch_encoder) {
8909 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8910 if (has_reduced_clock)
8911 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8913 dpll = ironlake_compute_dpll(crtc, crtc_state,
8914 &fp, &reduced_clock,
8915 has_reduced_clock ? &fp2 : NULL);
8917 crtc_state->dpll_hw_state.dpll = dpll;
8918 crtc_state->dpll_hw_state.fp0 = fp;
8919 if (has_reduced_clock)
8920 crtc_state->dpll_hw_state.fp1 = fp2;
8922 crtc_state->dpll_hw_state.fp1 = fp;
8924 pll = intel_get_shared_dpll(crtc, crtc_state);
8926 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8927 pipe_name(crtc->pipe));
8932 if (is_lvds && has_reduced_clock)
8933 crtc->lowfreq_avail = true;
8935 crtc->lowfreq_avail = false;
8940 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8941 struct intel_link_m_n *m_n)
8943 struct drm_device *dev = crtc->base.dev;
8944 struct drm_i915_private *dev_priv = dev->dev_private;
8945 enum pipe pipe = crtc->pipe;
8947 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8948 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8949 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8951 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8952 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8953 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8956 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8957 enum transcoder transcoder,
8958 struct intel_link_m_n *m_n,
8959 struct intel_link_m_n *m2_n2)
8961 struct drm_device *dev = crtc->base.dev;
8962 struct drm_i915_private *dev_priv = dev->dev_private;
8963 enum pipe pipe = crtc->pipe;
8965 if (INTEL_INFO(dev)->gen >= 5) {
8966 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8967 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8968 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8970 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8971 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8972 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8973 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8974 * gen < 8) and if DRRS is supported (to make sure the
8975 * registers are not unnecessarily read).
8977 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8978 crtc->config->has_drrs) {
8979 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8980 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8981 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8983 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8984 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8985 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8988 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8989 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8990 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8992 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8993 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8994 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8998 void intel_dp_get_m_n(struct intel_crtc *crtc,
8999 struct intel_crtc_state *pipe_config)
9001 if (pipe_config->has_pch_encoder)
9002 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9004 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9005 &pipe_config->dp_m_n,
9006 &pipe_config->dp_m2_n2);
9009 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9010 struct intel_crtc_state *pipe_config)
9012 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9013 &pipe_config->fdi_m_n, NULL);
9016 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9017 struct intel_crtc_state *pipe_config)
9019 struct drm_device *dev = crtc->base.dev;
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9022 uint32_t ps_ctrl = 0;
9026 /* find scaler attached to this pipe */
9027 for (i = 0; i < crtc->num_scalers; i++) {
9028 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9029 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9031 pipe_config->pch_pfit.enabled = true;
9032 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9033 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9038 scaler_state->scaler_id = id;
9040 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9042 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9047 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9048 struct intel_initial_plane_config *plane_config)
9050 struct drm_device *dev = crtc->base.dev;
9051 struct drm_i915_private *dev_priv = dev->dev_private;
9052 u32 val, base, offset, stride_mult, tiling;
9053 int pipe = crtc->pipe;
9054 int fourcc, pixel_format;
9055 unsigned int aligned_height;
9056 struct drm_framebuffer *fb;
9057 struct intel_framebuffer *intel_fb;
9059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9061 DRM_DEBUG_KMS("failed to alloc fb\n");
9065 fb = &intel_fb->base;
9067 val = I915_READ(PLANE_CTL(pipe, 0));
9068 if (!(val & PLANE_CTL_ENABLE))
9071 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9072 fourcc = skl_format_to_fourcc(pixel_format,
9073 val & PLANE_CTL_ORDER_RGBX,
9074 val & PLANE_CTL_ALPHA_MASK);
9075 fb->pixel_format = fourcc;
9076 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9078 tiling = val & PLANE_CTL_TILED_MASK;
9080 case PLANE_CTL_TILED_LINEAR:
9081 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9083 case PLANE_CTL_TILED_X:
9084 plane_config->tiling = I915_TILING_X;
9085 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9087 case PLANE_CTL_TILED_Y:
9088 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9090 case PLANE_CTL_TILED_YF:
9091 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9094 MISSING_CASE(tiling);
9098 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9099 plane_config->base = base;
9101 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9103 val = I915_READ(PLANE_SIZE(pipe, 0));
9104 fb->height = ((val >> 16) & 0xfff) + 1;
9105 fb->width = ((val >> 0) & 0x1fff) + 1;
9107 val = I915_READ(PLANE_STRIDE(pipe, 0));
9108 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9110 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9112 aligned_height = intel_fb_align_height(dev, fb->height,
9116 plane_config->size = fb->pitches[0] * aligned_height;
9118 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9119 pipe_name(pipe), fb->width, fb->height,
9120 fb->bits_per_pixel, base, fb->pitches[0],
9121 plane_config->size);
9123 plane_config->fb = intel_fb;
9130 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9131 struct intel_crtc_state *pipe_config)
9133 struct drm_device *dev = crtc->base.dev;
9134 struct drm_i915_private *dev_priv = dev->dev_private;
9137 tmp = I915_READ(PF_CTL(crtc->pipe));
9139 if (tmp & PF_ENABLE) {
9140 pipe_config->pch_pfit.enabled = true;
9141 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9142 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9144 /* We currently do not free assignements of panel fitters on
9145 * ivb/hsw (since we don't use the higher upscaling modes which
9146 * differentiates them) so just WARN about this case for now. */
9148 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9149 PF_PIPE_SEL_IVB(crtc->pipe));
9155 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9156 struct intel_initial_plane_config *plane_config)
9158 struct drm_device *dev = crtc->base.dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 u32 val, base, offset;
9161 int pipe = crtc->pipe;
9162 int fourcc, pixel_format;
9163 unsigned int aligned_height;
9164 struct drm_framebuffer *fb;
9165 struct intel_framebuffer *intel_fb;
9167 val = I915_READ(DSPCNTR(pipe));
9168 if (!(val & DISPLAY_PLANE_ENABLE))
9171 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9173 DRM_DEBUG_KMS("failed to alloc fb\n");
9177 fb = &intel_fb->base;
9179 if (INTEL_INFO(dev)->gen >= 4) {
9180 if (val & DISPPLANE_TILED) {
9181 plane_config->tiling = I915_TILING_X;
9182 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9186 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9187 fourcc = i9xx_format_to_fourcc(pixel_format);
9188 fb->pixel_format = fourcc;
9189 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9191 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9192 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9193 offset = I915_READ(DSPOFFSET(pipe));
9195 if (plane_config->tiling)
9196 offset = I915_READ(DSPTILEOFF(pipe));
9198 offset = I915_READ(DSPLINOFF(pipe));
9200 plane_config->base = base;
9202 val = I915_READ(PIPESRC(pipe));
9203 fb->width = ((val >> 16) & 0xfff) + 1;
9204 fb->height = ((val >> 0) & 0xfff) + 1;
9206 val = I915_READ(DSPSTRIDE(pipe));
9207 fb->pitches[0] = val & 0xffffffc0;
9209 aligned_height = intel_fb_align_height(dev, fb->height,
9213 plane_config->size = fb->pitches[0] * aligned_height;
9215 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9216 pipe_name(pipe), fb->width, fb->height,
9217 fb->bits_per_pixel, base, fb->pitches[0],
9218 plane_config->size);
9220 plane_config->fb = intel_fb;
9223 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9224 struct intel_crtc_state *pipe_config)
9226 struct drm_device *dev = crtc->base.dev;
9227 struct drm_i915_private *dev_priv = dev->dev_private;
9230 if (!intel_display_power_is_enabled(dev_priv,
9231 POWER_DOMAIN_PIPE(crtc->pipe)))
9234 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9235 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9237 tmp = I915_READ(PIPECONF(crtc->pipe));
9238 if (!(tmp & PIPECONF_ENABLE))
9241 switch (tmp & PIPECONF_BPC_MASK) {
9243 pipe_config->pipe_bpp = 18;
9246 pipe_config->pipe_bpp = 24;
9248 case PIPECONF_10BPC:
9249 pipe_config->pipe_bpp = 30;
9251 case PIPECONF_12BPC:
9252 pipe_config->pipe_bpp = 36;
9258 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9259 pipe_config->limited_color_range = true;
9261 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9262 struct intel_shared_dpll *pll;
9264 pipe_config->has_pch_encoder = true;
9266 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9267 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9268 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9270 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9272 if (HAS_PCH_IBX(dev_priv->dev)) {
9273 pipe_config->shared_dpll =
9274 (enum intel_dpll_id) crtc->pipe;
9276 tmp = I915_READ(PCH_DPLL_SEL);
9277 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9278 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9280 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9283 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9285 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9286 &pipe_config->dpll_hw_state));
9288 tmp = pipe_config->dpll_hw_state.dpll;
9289 pipe_config->pixel_multiplier =
9290 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9291 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9293 ironlake_pch_clock_get(crtc, pipe_config);
9295 pipe_config->pixel_multiplier = 1;
9298 intel_get_pipe_timings(crtc, pipe_config);
9300 ironlake_get_pfit_config(crtc, pipe_config);
9305 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9307 struct drm_device *dev = dev_priv->dev;
9308 struct intel_crtc *crtc;
9310 for_each_intel_crtc(dev, crtc)
9311 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9312 pipe_name(crtc->pipe));
9314 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9315 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9316 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9317 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9318 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9319 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9320 "CPU PWM1 enabled\n");
9321 if (IS_HASWELL(dev))
9322 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9323 "CPU PWM2 enabled\n");
9324 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9325 "PCH PWM1 enabled\n");
9326 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9327 "Utility pin enabled\n");
9328 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9331 * In theory we can still leave IRQs enabled, as long as only the HPD
9332 * interrupts remain enabled. We used to check for that, but since it's
9333 * gen-specific and since we only disable LCPLL after we fully disable
9334 * the interrupts, the check below should be enough.
9336 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9339 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9341 struct drm_device *dev = dev_priv->dev;
9343 if (IS_HASWELL(dev))
9344 return I915_READ(D_COMP_HSW);
9346 return I915_READ(D_COMP_BDW);
9349 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9351 struct drm_device *dev = dev_priv->dev;
9353 if (IS_HASWELL(dev)) {
9354 mutex_lock(&dev_priv->rps.hw_lock);
9355 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9357 DRM_ERROR("Failed to write to D_COMP\n");
9358 mutex_unlock(&dev_priv->rps.hw_lock);
9360 I915_WRITE(D_COMP_BDW, val);
9361 POSTING_READ(D_COMP_BDW);
9366 * This function implements pieces of two sequences from BSpec:
9367 * - Sequence for display software to disable LCPLL
9368 * - Sequence for display software to allow package C8+
9369 * The steps implemented here are just the steps that actually touch the LCPLL
9370 * register. Callers should take care of disabling all the display engine
9371 * functions, doing the mode unset, fixing interrupts, etc.
9373 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9374 bool switch_to_fclk, bool allow_power_down)
9378 assert_can_disable_lcpll(dev_priv);
9380 val = I915_READ(LCPLL_CTL);
9382 if (switch_to_fclk) {
9383 val |= LCPLL_CD_SOURCE_FCLK;
9384 I915_WRITE(LCPLL_CTL, val);
9386 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9387 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9388 DRM_ERROR("Switching to FCLK failed\n");
9390 val = I915_READ(LCPLL_CTL);
9393 val |= LCPLL_PLL_DISABLE;
9394 I915_WRITE(LCPLL_CTL, val);
9395 POSTING_READ(LCPLL_CTL);
9397 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9398 DRM_ERROR("LCPLL still locked\n");
9400 val = hsw_read_dcomp(dev_priv);
9401 val |= D_COMP_COMP_DISABLE;
9402 hsw_write_dcomp(dev_priv, val);
9405 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9407 DRM_ERROR("D_COMP RCOMP still in progress\n");
9409 if (allow_power_down) {
9410 val = I915_READ(LCPLL_CTL);
9411 val |= LCPLL_POWER_DOWN_ALLOW;
9412 I915_WRITE(LCPLL_CTL, val);
9413 POSTING_READ(LCPLL_CTL);
9418 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9421 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9425 val = I915_READ(LCPLL_CTL);
9427 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9428 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9432 * Make sure we're not on PC8 state before disabling PC8, otherwise
9433 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9435 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9437 if (val & LCPLL_POWER_DOWN_ALLOW) {
9438 val &= ~LCPLL_POWER_DOWN_ALLOW;
9439 I915_WRITE(LCPLL_CTL, val);
9440 POSTING_READ(LCPLL_CTL);
9443 val = hsw_read_dcomp(dev_priv);
9444 val |= D_COMP_COMP_FORCE;
9445 val &= ~D_COMP_COMP_DISABLE;
9446 hsw_write_dcomp(dev_priv, val);
9448 val = I915_READ(LCPLL_CTL);
9449 val &= ~LCPLL_PLL_DISABLE;
9450 I915_WRITE(LCPLL_CTL, val);
9452 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9453 DRM_ERROR("LCPLL not locked yet\n");
9455 if (val & LCPLL_CD_SOURCE_FCLK) {
9456 val = I915_READ(LCPLL_CTL);
9457 val &= ~LCPLL_CD_SOURCE_FCLK;
9458 I915_WRITE(LCPLL_CTL, val);
9460 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9461 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9462 DRM_ERROR("Switching back to LCPLL failed\n");
9465 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9466 intel_update_cdclk(dev_priv->dev);
9470 * Package states C8 and deeper are really deep PC states that can only be
9471 * reached when all the devices on the system allow it, so even if the graphics
9472 * device allows PC8+, it doesn't mean the system will actually get to these
9473 * states. Our driver only allows PC8+ when going into runtime PM.
9475 * The requirements for PC8+ are that all the outputs are disabled, the power
9476 * well is disabled and most interrupts are disabled, and these are also
9477 * requirements for runtime PM. When these conditions are met, we manually do
9478 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9479 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9482 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9483 * the state of some registers, so when we come back from PC8+ we need to
9484 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9485 * need to take care of the registers kept by RC6. Notice that this happens even
9486 * if we don't put the device in PCI D3 state (which is what currently happens
9487 * because of the runtime PM support).
9489 * For more, read "Display Sequences for Package C8" on the hardware
9492 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9494 struct drm_device *dev = dev_priv->dev;
9497 DRM_DEBUG_KMS("Enabling package C8+\n");
9499 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9500 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9501 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9502 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9505 lpt_disable_clkout_dp(dev);
9506 hsw_disable_lcpll(dev_priv, true, true);
9509 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9511 struct drm_device *dev = dev_priv->dev;
9514 DRM_DEBUG_KMS("Disabling package C8+\n");
9516 hsw_restore_lcpll(dev_priv);
9517 lpt_init_pch_refclk(dev);
9519 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9520 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9521 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9522 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9525 intel_prepare_ddi(dev);
9528 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9530 struct drm_device *dev = old_state->dev;
9531 struct drm_i915_private *dev_priv = dev->dev_private;
9532 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9535 /* see the comment in valleyview_modeset_global_resources */
9536 if (WARN_ON(max_pixclk < 0))
9539 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9541 if (req_cdclk != dev_priv->cdclk_freq)
9542 broxton_set_cdclk(dev, req_cdclk);
9545 /* compute the max rate for new configuration */
9546 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9548 struct drm_device *dev = dev_priv->dev;
9549 struct intel_crtc *intel_crtc;
9550 struct drm_crtc *crtc;
9551 int max_pixel_rate = 0;
9554 for_each_crtc(dev, crtc) {
9555 if (!crtc->state->enable)
9558 intel_crtc = to_intel_crtc(crtc);
9559 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9561 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9562 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9563 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9565 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9568 return max_pixel_rate;
9571 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9573 struct drm_i915_private *dev_priv = dev->dev_private;
9577 if (WARN((I915_READ(LCPLL_CTL) &
9578 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9579 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9580 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9581 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9582 "trying to change cdclk frequency with cdclk not enabled\n"))
9585 mutex_lock(&dev_priv->rps.hw_lock);
9586 ret = sandybridge_pcode_write(dev_priv,
9587 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9588 mutex_unlock(&dev_priv->rps.hw_lock);
9590 DRM_ERROR("failed to inform pcode about cdclk change\n");
9594 val = I915_READ(LCPLL_CTL);
9595 val |= LCPLL_CD_SOURCE_FCLK;
9596 I915_WRITE(LCPLL_CTL, val);
9598 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9599 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9600 DRM_ERROR("Switching to FCLK failed\n");
9602 val = I915_READ(LCPLL_CTL);
9603 val &= ~LCPLL_CLK_FREQ_MASK;
9607 val |= LCPLL_CLK_FREQ_450;
9611 val |= LCPLL_CLK_FREQ_54O_BDW;
9615 val |= LCPLL_CLK_FREQ_337_5_BDW;
9619 val |= LCPLL_CLK_FREQ_675_BDW;
9623 WARN(1, "invalid cdclk frequency\n");
9627 I915_WRITE(LCPLL_CTL, val);
9629 val = I915_READ(LCPLL_CTL);
9630 val &= ~LCPLL_CD_SOURCE_FCLK;
9631 I915_WRITE(LCPLL_CTL, val);
9633 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9634 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9635 DRM_ERROR("Switching back to LCPLL failed\n");
9637 mutex_lock(&dev_priv->rps.hw_lock);
9638 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9639 mutex_unlock(&dev_priv->rps.hw_lock);
9641 intel_update_cdclk(dev);
9643 WARN(cdclk != dev_priv->cdclk_freq,
9644 "cdclk requested %d kHz but got %d kHz\n",
9645 cdclk, dev_priv->cdclk_freq);
9648 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9654 * FIXME should also account for plane ratio
9655 * once 64bpp pixel formats are supported.
9657 if (max_pixel_rate > 540000)
9659 else if (max_pixel_rate > 450000)
9661 else if (max_pixel_rate > 337500)
9667 * FIXME move the cdclk caclulation to
9668 * compute_config() so we can fail gracegully.
9670 if (cdclk > dev_priv->max_cdclk_freq) {
9671 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9672 cdclk, dev_priv->max_cdclk_freq);
9673 cdclk = dev_priv->max_cdclk_freq;
9679 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9681 struct drm_i915_private *dev_priv = to_i915(state->dev);
9682 struct drm_crtc *crtc;
9683 struct drm_crtc_state *crtc_state;
9684 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9687 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9689 if (cdclk == dev_priv->cdclk_freq)
9692 /* add all active pipes to the state */
9693 for_each_crtc(state->dev, crtc) {
9694 if (!crtc->state->enable)
9697 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9698 if (IS_ERR(crtc_state))
9699 return PTR_ERR(crtc_state);
9702 /* disable/enable all currently active pipes while we change cdclk */
9703 for_each_crtc_in_state(state, crtc, crtc_state, i)
9704 if (crtc_state->enable)
9705 crtc_state->mode_changed = true;
9710 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9712 struct drm_device *dev = state->dev;
9713 struct drm_i915_private *dev_priv = dev->dev_private;
9714 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9715 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9717 if (req_cdclk != dev_priv->cdclk_freq)
9718 broadwell_set_cdclk(dev, req_cdclk);
9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9722 struct intel_crtc_state *crtc_state)
9724 if (!intel_ddi_pll_select(crtc, crtc_state))
9727 crtc->lowfreq_avail = false;
9732 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9734 struct intel_crtc_state *pipe_config)
9738 pipe_config->ddi_pll_sel = SKL_DPLL0;
9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9742 pipe_config->ddi_pll_sel = SKL_DPLL1;
9743 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9746 pipe_config->ddi_pll_sel = SKL_DPLL2;
9747 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9750 DRM_ERROR("Incorrect port type\n");
9754 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9756 struct intel_crtc_state *pipe_config)
9758 u32 temp, dpll_ctl1;
9760 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9761 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9763 switch (pipe_config->ddi_pll_sel) {
9766 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9767 * of the shared DPLL framework and thus needs to be read out
9770 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9771 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9774 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9777 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9780 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9785 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9787 struct intel_crtc_state *pipe_config)
9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9791 switch (pipe_config->ddi_pll_sel) {
9792 case PORT_CLK_SEL_WRPLL1:
9793 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9795 case PORT_CLK_SEL_WRPLL2:
9796 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9801 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9802 struct intel_crtc_state *pipe_config)
9804 struct drm_device *dev = crtc->base.dev;
9805 struct drm_i915_private *dev_priv = dev->dev_private;
9806 struct intel_shared_dpll *pll;
9810 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9812 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9814 if (IS_SKYLAKE(dev))
9815 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9816 else if (IS_BROXTON(dev))
9817 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9819 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9821 if (pipe_config->shared_dpll >= 0) {
9822 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9824 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9825 &pipe_config->dpll_hw_state));
9829 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9830 * DDI E. So just check whether this pipe is wired to DDI E and whether
9831 * the PCH transcoder is on.
9833 if (INTEL_INFO(dev)->gen < 9 &&
9834 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9835 pipe_config->has_pch_encoder = true;
9837 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9838 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9839 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9841 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9845 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9846 struct intel_crtc_state *pipe_config)
9848 struct drm_device *dev = crtc->base.dev;
9849 struct drm_i915_private *dev_priv = dev->dev_private;
9850 enum intel_display_power_domain pfit_domain;
9853 if (!intel_display_power_is_enabled(dev_priv,
9854 POWER_DOMAIN_PIPE(crtc->pipe)))
9857 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9858 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9860 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9861 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9862 enum pipe trans_edp_pipe;
9863 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9865 WARN(1, "unknown pipe linked to edp transcoder\n");
9866 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9867 case TRANS_DDI_EDP_INPUT_A_ON:
9868 trans_edp_pipe = PIPE_A;
9870 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9871 trans_edp_pipe = PIPE_B;
9873 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9874 trans_edp_pipe = PIPE_C;
9878 if (trans_edp_pipe == crtc->pipe)
9879 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9882 if (!intel_display_power_is_enabled(dev_priv,
9883 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9886 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9887 if (!(tmp & PIPECONF_ENABLE))
9890 haswell_get_ddi_port_state(crtc, pipe_config);
9892 intel_get_pipe_timings(crtc, pipe_config);
9894 if (INTEL_INFO(dev)->gen >= 9) {
9895 skl_init_scalers(dev, crtc, pipe_config);
9898 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9900 if (INTEL_INFO(dev)->gen >= 9) {
9901 pipe_config->scaler_state.scaler_id = -1;
9902 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9905 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9906 if (INTEL_INFO(dev)->gen == 9)
9907 skylake_get_pfit_config(crtc, pipe_config);
9908 else if (INTEL_INFO(dev)->gen < 9)
9909 ironlake_get_pfit_config(crtc, pipe_config);
9911 MISSING_CASE(INTEL_INFO(dev)->gen);
9914 if (IS_HASWELL(dev))
9915 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9916 (I915_READ(IPS_CTL) & IPS_ENABLE);
9918 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9919 pipe_config->pixel_multiplier =
9920 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9922 pipe_config->pixel_multiplier = 1;
9928 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9930 struct drm_device *dev = crtc->dev;
9931 struct drm_i915_private *dev_priv = dev->dev_private;
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933 uint32_t cntl = 0, size = 0;
9936 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9937 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9938 unsigned int stride = roundup_pow_of_two(width) * 4;
9942 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9953 cntl |= CURSOR_ENABLE |
9954 CURSOR_GAMMA_ENABLE |
9955 CURSOR_FORMAT_ARGB |
9956 CURSOR_STRIDE(stride);
9958 size = (height << 12) | width;
9961 if (intel_crtc->cursor_cntl != 0 &&
9962 (intel_crtc->cursor_base != base ||
9963 intel_crtc->cursor_size != size ||
9964 intel_crtc->cursor_cntl != cntl)) {
9965 /* On these chipsets we can only modify the base/size/stride
9966 * whilst the cursor is disabled.
9968 I915_WRITE(_CURACNTR, 0);
9969 POSTING_READ(_CURACNTR);
9970 intel_crtc->cursor_cntl = 0;
9973 if (intel_crtc->cursor_base != base) {
9974 I915_WRITE(_CURABASE, base);
9975 intel_crtc->cursor_base = base;
9978 if (intel_crtc->cursor_size != size) {
9979 I915_WRITE(CURSIZE, size);
9980 intel_crtc->cursor_size = size;
9983 if (intel_crtc->cursor_cntl != cntl) {
9984 I915_WRITE(_CURACNTR, cntl);
9985 POSTING_READ(_CURACNTR);
9986 intel_crtc->cursor_cntl = cntl;
9990 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9992 struct drm_device *dev = crtc->dev;
9993 struct drm_i915_private *dev_priv = dev->dev_private;
9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9995 int pipe = intel_crtc->pipe;
10000 cntl = MCURSOR_GAMMA_ENABLE;
10001 switch (intel_crtc->base.cursor->state->crtc_w) {
10003 cntl |= CURSOR_MODE_64_ARGB_AX;
10006 cntl |= CURSOR_MODE_128_ARGB_AX;
10009 cntl |= CURSOR_MODE_256_ARGB_AX;
10012 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10015 cntl |= pipe << 28; /* Connect to correct pipe */
10017 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10018 cntl |= CURSOR_PIPE_CSC_ENABLE;
10021 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10022 cntl |= CURSOR_ROTATE_180;
10024 if (intel_crtc->cursor_cntl != cntl) {
10025 I915_WRITE(CURCNTR(pipe), cntl);
10026 POSTING_READ(CURCNTR(pipe));
10027 intel_crtc->cursor_cntl = cntl;
10030 /* and commit changes on next vblank */
10031 I915_WRITE(CURBASE(pipe), base);
10032 POSTING_READ(CURBASE(pipe));
10034 intel_crtc->cursor_base = base;
10037 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10038 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10041 struct drm_device *dev = crtc->dev;
10042 struct drm_i915_private *dev_priv = dev->dev_private;
10043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10044 int pipe = intel_crtc->pipe;
10045 int x = crtc->cursor_x;
10046 int y = crtc->cursor_y;
10047 u32 base = 0, pos = 0;
10050 base = intel_crtc->cursor_addr;
10052 if (x >= intel_crtc->config->pipe_src_w)
10055 if (y >= intel_crtc->config->pipe_src_h)
10059 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10062 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10065 pos |= x << CURSOR_X_SHIFT;
10068 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10071 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10074 pos |= y << CURSOR_Y_SHIFT;
10076 if (base == 0 && intel_crtc->cursor_base == 0)
10079 I915_WRITE(CURPOS(pipe), pos);
10081 /* ILK+ do this automagically */
10082 if (HAS_GMCH_DISPLAY(dev) &&
10083 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10084 base += (intel_crtc->base.cursor->state->crtc_h *
10085 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10088 if (IS_845G(dev) || IS_I865G(dev))
10089 i845_update_cursor(crtc, base);
10091 i9xx_update_cursor(crtc, base);
10094 static bool cursor_size_ok(struct drm_device *dev,
10095 uint32_t width, uint32_t height)
10097 if (width == 0 || height == 0)
10101 * 845g/865g are special in that they are only limited by
10102 * the width of their cursors, the height is arbitrary up to
10103 * the precision of the register. Everything else requires
10104 * square cursors, limited to a few power-of-two sizes.
10106 if (IS_845G(dev) || IS_I865G(dev)) {
10107 if ((width & 63) != 0)
10110 if (width > (IS_845G(dev) ? 64 : 512))
10116 switch (width | height) {
10131 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10132 u16 *blue, uint32_t start, uint32_t size)
10134 int end = (start + size > 256) ? 256 : start + size, i;
10135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10137 for (i = start; i < end; i++) {
10138 intel_crtc->lut_r[i] = red[i] >> 8;
10139 intel_crtc->lut_g[i] = green[i] >> 8;
10140 intel_crtc->lut_b[i] = blue[i] >> 8;
10143 intel_crtc_load_lut(crtc);
10146 /* VESA 640x480x72Hz mode to set on the pipe */
10147 static struct drm_display_mode load_detect_mode = {
10148 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10149 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10152 struct drm_framebuffer *
10153 __intel_framebuffer_create(struct drm_device *dev,
10154 struct drm_mode_fb_cmd2 *mode_cmd,
10155 struct drm_i915_gem_object *obj)
10157 struct intel_framebuffer *intel_fb;
10160 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10162 drm_gem_object_unreference(&obj->base);
10163 return ERR_PTR(-ENOMEM);
10166 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10170 return &intel_fb->base;
10172 drm_gem_object_unreference(&obj->base);
10175 return ERR_PTR(ret);
10178 static struct drm_framebuffer *
10179 intel_framebuffer_create(struct drm_device *dev,
10180 struct drm_mode_fb_cmd2 *mode_cmd,
10181 struct drm_i915_gem_object *obj)
10183 struct drm_framebuffer *fb;
10186 ret = i915_mutex_lock_interruptible(dev);
10188 return ERR_PTR(ret);
10189 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10190 mutex_unlock(&dev->struct_mutex);
10196 intel_framebuffer_pitch_for_width(int width, int bpp)
10198 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10199 return ALIGN(pitch, 64);
10203 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10205 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10206 return PAGE_ALIGN(pitch * mode->vdisplay);
10209 static struct drm_framebuffer *
10210 intel_framebuffer_create_for_mode(struct drm_device *dev,
10211 struct drm_display_mode *mode,
10212 int depth, int bpp)
10214 struct drm_i915_gem_object *obj;
10215 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10217 obj = i915_gem_alloc_object(dev,
10218 intel_framebuffer_size_for_mode(mode, bpp));
10220 return ERR_PTR(-ENOMEM);
10222 mode_cmd.width = mode->hdisplay;
10223 mode_cmd.height = mode->vdisplay;
10224 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10226 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10228 return intel_framebuffer_create(dev, &mode_cmd, obj);
10231 static struct drm_framebuffer *
10232 mode_fits_in_fbdev(struct drm_device *dev,
10233 struct drm_display_mode *mode)
10235 #ifdef CONFIG_DRM_I915_FBDEV
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 struct drm_i915_gem_object *obj;
10238 struct drm_framebuffer *fb;
10240 if (!dev_priv->fbdev)
10243 if (!dev_priv->fbdev->fb)
10246 obj = dev_priv->fbdev->fb->obj;
10249 fb = &dev_priv->fbdev->fb->base;
10250 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10251 fb->bits_per_pixel))
10254 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10263 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10264 struct drm_crtc *crtc,
10265 struct drm_display_mode *mode,
10266 struct drm_framebuffer *fb,
10269 struct drm_plane_state *plane_state;
10270 int hdisplay, vdisplay;
10273 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10274 if (IS_ERR(plane_state))
10275 return PTR_ERR(plane_state);
10278 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10280 hdisplay = vdisplay = 0;
10282 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10285 drm_atomic_set_fb_for_plane(plane_state, fb);
10286 plane_state->crtc_x = 0;
10287 plane_state->crtc_y = 0;
10288 plane_state->crtc_w = hdisplay;
10289 plane_state->crtc_h = vdisplay;
10290 plane_state->src_x = x << 16;
10291 plane_state->src_y = y << 16;
10292 plane_state->src_w = hdisplay << 16;
10293 plane_state->src_h = vdisplay << 16;
10298 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10299 struct drm_display_mode *mode,
10300 struct intel_load_detect_pipe *old,
10301 struct drm_modeset_acquire_ctx *ctx)
10303 struct intel_crtc *intel_crtc;
10304 struct intel_encoder *intel_encoder =
10305 intel_attached_encoder(connector);
10306 struct drm_crtc *possible_crtc;
10307 struct drm_encoder *encoder = &intel_encoder->base;
10308 struct drm_crtc *crtc = NULL;
10309 struct drm_device *dev = encoder->dev;
10310 struct drm_framebuffer *fb;
10311 struct drm_mode_config *config = &dev->mode_config;
10312 struct drm_atomic_state *state = NULL;
10313 struct drm_connector_state *connector_state;
10314 struct intel_crtc_state *crtc_state;
10317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10318 connector->base.id, connector->name,
10319 encoder->base.id, encoder->name);
10322 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10327 * Algorithm gets a little messy:
10329 * - if the connector already has an assigned crtc, use it (but make
10330 * sure it's on first)
10332 * - try to find the first unused crtc that can drive this connector,
10333 * and use that if we find one
10336 /* See if we already have a CRTC for this connector */
10337 if (encoder->crtc) {
10338 crtc = encoder->crtc;
10340 ret = drm_modeset_lock(&crtc->mutex, ctx);
10343 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10347 old->dpms_mode = connector->dpms;
10348 old->load_detect_temp = false;
10350 /* Make sure the crtc and connector are running */
10351 if (connector->dpms != DRM_MODE_DPMS_ON)
10352 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10357 /* Find an unused one (if possible) */
10358 for_each_crtc(dev, possible_crtc) {
10360 if (!(encoder->possible_crtcs & (1 << i)))
10362 if (possible_crtc->state->enable)
10364 /* This can occur when applying the pipe A quirk on resume. */
10365 if (to_intel_crtc(possible_crtc)->new_enabled)
10368 crtc = possible_crtc;
10373 * If we didn't find an unused CRTC, don't use any.
10376 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10380 ret = drm_modeset_lock(&crtc->mutex, ctx);
10383 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10386 intel_encoder->new_crtc = to_intel_crtc(crtc);
10387 to_intel_connector(connector)->new_encoder = intel_encoder;
10389 intel_crtc = to_intel_crtc(crtc);
10390 intel_crtc->new_enabled = true;
10391 old->dpms_mode = connector->dpms;
10392 old->load_detect_temp = true;
10393 old->release_fb = NULL;
10395 state = drm_atomic_state_alloc(dev);
10399 state->acquire_ctx = ctx;
10401 connector_state = drm_atomic_get_connector_state(state, connector);
10402 if (IS_ERR(connector_state)) {
10403 ret = PTR_ERR(connector_state);
10407 connector_state->crtc = crtc;
10408 connector_state->best_encoder = &intel_encoder->base;
10410 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10411 if (IS_ERR(crtc_state)) {
10412 ret = PTR_ERR(crtc_state);
10416 crtc_state->base.active = crtc_state->base.enable = true;
10419 mode = &load_detect_mode;
10421 /* We need a framebuffer large enough to accommodate all accesses
10422 * that the plane may generate whilst we perform load detection.
10423 * We can not rely on the fbcon either being present (we get called
10424 * during its initialisation to detect all boot displays, or it may
10425 * not even exist) or that it is large enough to satisfy the
10428 fb = mode_fits_in_fbdev(dev, mode);
10430 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10431 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10432 old->release_fb = fb;
10434 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10436 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10440 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10444 drm_mode_copy(&crtc_state->base.mode, mode);
10446 if (intel_set_mode(state)) {
10447 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10448 if (old->release_fb)
10449 old->release_fb->funcs->destroy(old->release_fb);
10452 crtc->primary->crtc = crtc;
10454 /* let the connector get through one full cycle before testing */
10455 intel_wait_for_vblank(dev, intel_crtc->pipe);
10459 intel_crtc->new_enabled = crtc->state->enable;
10461 drm_atomic_state_free(state);
10464 if (ret == -EDEADLK) {
10465 drm_modeset_backoff(ctx);
10472 void intel_release_load_detect_pipe(struct drm_connector *connector,
10473 struct intel_load_detect_pipe *old,
10474 struct drm_modeset_acquire_ctx *ctx)
10476 struct drm_device *dev = connector->dev;
10477 struct intel_encoder *intel_encoder =
10478 intel_attached_encoder(connector);
10479 struct drm_encoder *encoder = &intel_encoder->base;
10480 struct drm_crtc *crtc = encoder->crtc;
10481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10482 struct drm_atomic_state *state;
10483 struct drm_connector_state *connector_state;
10484 struct intel_crtc_state *crtc_state;
10487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10488 connector->base.id, connector->name,
10489 encoder->base.id, encoder->name);
10491 if (old->load_detect_temp) {
10492 state = drm_atomic_state_alloc(dev);
10496 state->acquire_ctx = ctx;
10498 connector_state = drm_atomic_get_connector_state(state, connector);
10499 if (IS_ERR(connector_state))
10502 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10503 if (IS_ERR(crtc_state))
10506 to_intel_connector(connector)->new_encoder = NULL;
10507 intel_encoder->new_crtc = NULL;
10508 intel_crtc->new_enabled = false;
10510 connector_state->best_encoder = NULL;
10511 connector_state->crtc = NULL;
10513 crtc_state->base.enable = crtc_state->base.active = false;
10515 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10520 ret = intel_set_mode(state);
10524 if (old->release_fb) {
10525 drm_framebuffer_unregister_private(old->release_fb);
10526 drm_framebuffer_unreference(old->release_fb);
10532 /* Switch crtc and encoder back off if necessary */
10533 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10534 connector->funcs->dpms(connector, old->dpms_mode);
10538 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10539 drm_atomic_state_free(state);
10542 static int i9xx_pll_refclk(struct drm_device *dev,
10543 const struct intel_crtc_state *pipe_config)
10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 u32 dpll = pipe_config->dpll_hw_state.dpll;
10548 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10549 return dev_priv->vbt.lvds_ssc_freq;
10550 else if (HAS_PCH_SPLIT(dev))
10552 else if (!IS_GEN2(dev))
10558 /* Returns the clock of the currently programmed mode of the given pipe. */
10559 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10560 struct intel_crtc_state *pipe_config)
10562 struct drm_device *dev = crtc->base.dev;
10563 struct drm_i915_private *dev_priv = dev->dev_private;
10564 int pipe = pipe_config->cpu_transcoder;
10565 u32 dpll = pipe_config->dpll_hw_state.dpll;
10567 intel_clock_t clock;
10568 int refclk = i9xx_pll_refclk(dev, pipe_config);
10570 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10571 fp = pipe_config->dpll_hw_state.fp0;
10573 fp = pipe_config->dpll_hw_state.fp1;
10575 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10576 if (IS_PINEVIEW(dev)) {
10577 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10578 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10580 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10581 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10584 if (!IS_GEN2(dev)) {
10585 if (IS_PINEVIEW(dev))
10586 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10587 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10590 DPLL_FPA01_P1_POST_DIV_SHIFT);
10592 switch (dpll & DPLL_MODE_MASK) {
10593 case DPLLB_MODE_DAC_SERIAL:
10594 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10597 case DPLLB_MODE_LVDS:
10598 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10602 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10603 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10607 if (IS_PINEVIEW(dev))
10608 pineview_clock(refclk, &clock);
10610 i9xx_clock(refclk, &clock);
10612 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10613 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10616 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10617 DPLL_FPA01_P1_POST_DIV_SHIFT);
10619 if (lvds & LVDS_CLKB_POWER_UP)
10624 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10627 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10628 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10630 if (dpll & PLL_P2_DIVIDE_BY_4)
10636 i9xx_clock(refclk, &clock);
10640 * This value includes pixel_multiplier. We will use
10641 * port_clock to compute adjusted_mode.crtc_clock in the
10642 * encoder's get_config() function.
10644 pipe_config->port_clock = clock.dot;
10647 int intel_dotclock_calculate(int link_freq,
10648 const struct intel_link_m_n *m_n)
10651 * The calculation for the data clock is:
10652 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10653 * But we want to avoid losing precison if possible, so:
10654 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10656 * and the link clock is simpler:
10657 * link_clock = (m * link_clock) / n
10663 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10666 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10667 struct intel_crtc_state *pipe_config)
10669 struct drm_device *dev = crtc->base.dev;
10671 /* read out port_clock from the DPLL */
10672 i9xx_crtc_clock_get(crtc, pipe_config);
10675 * This value does not include pixel_multiplier.
10676 * We will check that port_clock and adjusted_mode.crtc_clock
10677 * agree once we know their relationship in the encoder's
10678 * get_config() function.
10680 pipe_config->base.adjusted_mode.crtc_clock =
10681 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10682 &pipe_config->fdi_m_n);
10685 /** Returns the currently programmed mode of the given pipe. */
10686 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10687 struct drm_crtc *crtc)
10689 struct drm_i915_private *dev_priv = dev->dev_private;
10690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10691 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10692 struct drm_display_mode *mode;
10693 struct intel_crtc_state pipe_config;
10694 int htot = I915_READ(HTOTAL(cpu_transcoder));
10695 int hsync = I915_READ(HSYNC(cpu_transcoder));
10696 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10697 int vsync = I915_READ(VSYNC(cpu_transcoder));
10698 enum pipe pipe = intel_crtc->pipe;
10700 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10705 * Construct a pipe_config sufficient for getting the clock info
10706 * back out of crtc_clock_get.
10708 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10709 * to use a real value here instead.
10711 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10712 pipe_config.pixel_multiplier = 1;
10713 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10714 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10715 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10716 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10718 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10719 mode->hdisplay = (htot & 0xffff) + 1;
10720 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10721 mode->hsync_start = (hsync & 0xffff) + 1;
10722 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10723 mode->vdisplay = (vtot & 0xffff) + 1;
10724 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10725 mode->vsync_start = (vsync & 0xffff) + 1;
10726 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10728 drm_mode_set_name(mode);
10733 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10735 struct drm_device *dev = crtc->dev;
10736 struct drm_i915_private *dev_priv = dev->dev_private;
10737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10739 if (!HAS_GMCH_DISPLAY(dev))
10742 if (!dev_priv->lvds_downclock_avail)
10746 * Since this is called by a timer, we should never get here in
10749 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10750 int pipe = intel_crtc->pipe;
10751 int dpll_reg = DPLL(pipe);
10754 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10756 assert_panel_unlocked(dev_priv, pipe);
10758 dpll = I915_READ(dpll_reg);
10759 dpll |= DISPLAY_RATE_SELECT_FPA1;
10760 I915_WRITE(dpll_reg, dpll);
10761 intel_wait_for_vblank(dev, pipe);
10762 dpll = I915_READ(dpll_reg);
10763 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10764 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10769 void intel_mark_busy(struct drm_device *dev)
10771 struct drm_i915_private *dev_priv = dev->dev_private;
10773 if (dev_priv->mm.busy)
10776 intel_runtime_pm_get(dev_priv);
10777 i915_update_gfx_val(dev_priv);
10778 if (INTEL_INFO(dev)->gen >= 6)
10779 gen6_rps_busy(dev_priv);
10780 dev_priv->mm.busy = true;
10783 void intel_mark_idle(struct drm_device *dev)
10785 struct drm_i915_private *dev_priv = dev->dev_private;
10786 struct drm_crtc *crtc;
10788 if (!dev_priv->mm.busy)
10791 dev_priv->mm.busy = false;
10793 for_each_crtc(dev, crtc) {
10794 if (!crtc->primary->fb)
10797 intel_decrease_pllclock(crtc);
10800 if (INTEL_INFO(dev)->gen >= 6)
10801 gen6_rps_idle(dev->dev_private);
10803 intel_runtime_pm_put(dev_priv);
10806 static void intel_crtc_destroy(struct drm_crtc *crtc)
10808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10809 struct drm_device *dev = crtc->dev;
10810 struct intel_unpin_work *work;
10812 spin_lock_irq(&dev->event_lock);
10813 work = intel_crtc->unpin_work;
10814 intel_crtc->unpin_work = NULL;
10815 spin_unlock_irq(&dev->event_lock);
10818 cancel_work_sync(&work->work);
10822 drm_crtc_cleanup(crtc);
10827 static void intel_unpin_work_fn(struct work_struct *__work)
10829 struct intel_unpin_work *work =
10830 container_of(__work, struct intel_unpin_work, work);
10831 struct drm_device *dev = work->crtc->dev;
10832 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10834 mutex_lock(&dev->struct_mutex);
10835 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10836 drm_gem_object_unreference(&work->pending_flip_obj->base);
10838 intel_fbc_update(dev);
10840 if (work->flip_queued_req)
10841 i915_gem_request_assign(&work->flip_queued_req, NULL);
10842 mutex_unlock(&dev->struct_mutex);
10844 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10845 drm_framebuffer_unreference(work->old_fb);
10847 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10848 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10853 static void do_intel_finish_page_flip(struct drm_device *dev,
10854 struct drm_crtc *crtc)
10856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857 struct intel_unpin_work *work;
10858 unsigned long flags;
10860 /* Ignore early vblank irqs */
10861 if (intel_crtc == NULL)
10865 * This is called both by irq handlers and the reset code (to complete
10866 * lost pageflips) so needs the full irqsave spinlocks.
10868 spin_lock_irqsave(&dev->event_lock, flags);
10869 work = intel_crtc->unpin_work;
10871 /* Ensure we don't miss a work->pending update ... */
10874 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10875 spin_unlock_irqrestore(&dev->event_lock, flags);
10879 page_flip_completed(intel_crtc);
10881 spin_unlock_irqrestore(&dev->event_lock, flags);
10884 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10886 struct drm_i915_private *dev_priv = dev->dev_private;
10887 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10889 do_intel_finish_page_flip(dev, crtc);
10892 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10894 struct drm_i915_private *dev_priv = dev->dev_private;
10895 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10897 do_intel_finish_page_flip(dev, crtc);
10900 /* Is 'a' after or equal to 'b'? */
10901 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10903 return !((a - b) & 0x80000000);
10906 static bool page_flip_finished(struct intel_crtc *crtc)
10908 struct drm_device *dev = crtc->base.dev;
10909 struct drm_i915_private *dev_priv = dev->dev_private;
10911 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10912 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10916 * The relevant registers doen't exist on pre-ctg.
10917 * As the flip done interrupt doesn't trigger for mmio
10918 * flips on gmch platforms, a flip count check isn't
10919 * really needed there. But since ctg has the registers,
10920 * include it in the check anyway.
10922 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10926 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10927 * used the same base address. In that case the mmio flip might
10928 * have completed, but the CS hasn't even executed the flip yet.
10930 * A flip count check isn't enough as the CS might have updated
10931 * the base address just after start of vblank, but before we
10932 * managed to process the interrupt. This means we'd complete the
10933 * CS flip too soon.
10935 * Combining both checks should get us a good enough result. It may
10936 * still happen that the CS flip has been executed, but has not
10937 * yet actually completed. But in case the base address is the same
10938 * anyway, we don't really care.
10940 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10941 crtc->unpin_work->gtt_offset &&
10942 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10943 crtc->unpin_work->flip_count);
10946 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10948 struct drm_i915_private *dev_priv = dev->dev_private;
10949 struct intel_crtc *intel_crtc =
10950 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10951 unsigned long flags;
10955 * This is called both by irq handlers and the reset code (to complete
10956 * lost pageflips) so needs the full irqsave spinlocks.
10958 * NB: An MMIO update of the plane base pointer will also
10959 * generate a page-flip completion irq, i.e. every modeset
10960 * is also accompanied by a spurious intel_prepare_page_flip().
10962 spin_lock_irqsave(&dev->event_lock, flags);
10963 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10964 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10965 spin_unlock_irqrestore(&dev->event_lock, flags);
10968 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10970 /* Ensure that the work item is consistent when activating it ... */
10972 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10973 /* and that it is marked active as soon as the irq could fire. */
10977 static int intel_gen2_queue_flip(struct drm_device *dev,
10978 struct drm_crtc *crtc,
10979 struct drm_framebuffer *fb,
10980 struct drm_i915_gem_object *obj,
10981 struct intel_engine_cs *ring,
10984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10988 ret = intel_ring_begin(ring, 6);
10992 /* Can't queue multiple flips, so wait for the previous
10993 * one to finish before executing the next.
10995 if (intel_crtc->plane)
10996 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10998 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10999 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11000 intel_ring_emit(ring, MI_NOOP);
11001 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11002 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11003 intel_ring_emit(ring, fb->pitches[0]);
11004 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11005 intel_ring_emit(ring, 0); /* aux display base address, unused */
11007 intel_mark_page_flip_active(intel_crtc);
11008 __intel_ring_advance(ring);
11012 static int intel_gen3_queue_flip(struct drm_device *dev,
11013 struct drm_crtc *crtc,
11014 struct drm_framebuffer *fb,
11015 struct drm_i915_gem_object *obj,
11016 struct intel_engine_cs *ring,
11019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11023 ret = intel_ring_begin(ring, 6);
11027 if (intel_crtc->plane)
11028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11031 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11032 intel_ring_emit(ring, MI_NOOP);
11033 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11035 intel_ring_emit(ring, fb->pitches[0]);
11036 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11037 intel_ring_emit(ring, MI_NOOP);
11039 intel_mark_page_flip_active(intel_crtc);
11040 __intel_ring_advance(ring);
11044 static int intel_gen4_queue_flip(struct drm_device *dev,
11045 struct drm_crtc *crtc,
11046 struct drm_framebuffer *fb,
11047 struct drm_i915_gem_object *obj,
11048 struct intel_engine_cs *ring,
11051 struct drm_i915_private *dev_priv = dev->dev_private;
11052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053 uint32_t pf, pipesrc;
11056 ret = intel_ring_begin(ring, 4);
11060 /* i965+ uses the linear or tiled offsets from the
11061 * Display Registers (which do not change across a page-flip)
11062 * so we need only reprogram the base address.
11064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066 intel_ring_emit(ring, fb->pitches[0]);
11067 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11070 /* XXX Enabling the panel-fitter across page-flip is so far
11071 * untested on non-native modes, so ignore it for now.
11072 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11075 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11076 intel_ring_emit(ring, pf | pipesrc);
11078 intel_mark_page_flip_active(intel_crtc);
11079 __intel_ring_advance(ring);
11083 static int intel_gen6_queue_flip(struct drm_device *dev,
11084 struct drm_crtc *crtc,
11085 struct drm_framebuffer *fb,
11086 struct drm_i915_gem_object *obj,
11087 struct intel_engine_cs *ring,
11090 struct drm_i915_private *dev_priv = dev->dev_private;
11091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092 uint32_t pf, pipesrc;
11095 ret = intel_ring_begin(ring, 4);
11099 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11100 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11101 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11102 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11104 /* Contrary to the suggestions in the documentation,
11105 * "Enable Panel Fitter" does not seem to be required when page
11106 * flipping with a non-native mode, and worse causes a normal
11108 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11111 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11112 intel_ring_emit(ring, pf | pipesrc);
11114 intel_mark_page_flip_active(intel_crtc);
11115 __intel_ring_advance(ring);
11119 static int intel_gen7_queue_flip(struct drm_device *dev,
11120 struct drm_crtc *crtc,
11121 struct drm_framebuffer *fb,
11122 struct drm_i915_gem_object *obj,
11123 struct intel_engine_cs *ring,
11126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11127 uint32_t plane_bit = 0;
11130 switch (intel_crtc->plane) {
11132 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11135 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11138 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11141 WARN_ONCE(1, "unknown plane in flip command\n");
11146 if (ring->id == RCS) {
11149 * On Gen 8, SRM is now taking an extra dword to accommodate
11150 * 48bits addresses, and we need a NOOP for the batch size to
11158 * BSpec MI_DISPLAY_FLIP for IVB:
11159 * "The full packet must be contained within the same cache line."
11161 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11162 * cacheline, if we ever start emitting more commands before
11163 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11164 * then do the cacheline alignment, and finally emit the
11167 ret = intel_ring_cacheline_align(ring);
11171 ret = intel_ring_begin(ring, len);
11175 /* Unmask the flip-done completion message. Note that the bspec says that
11176 * we should do this for both the BCS and RCS, and that we must not unmask
11177 * more than one flip event at any time (or ensure that one flip message
11178 * can be sent by waiting for flip-done prior to queueing new flips).
11179 * Experimentation says that BCS works despite DERRMR masking all
11180 * flip-done completion events and that unmasking all planes at once
11181 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11182 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11184 if (ring->id == RCS) {
11185 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11186 intel_ring_emit(ring, DERRMR);
11187 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11188 DERRMR_PIPEB_PRI_FLIP_DONE |
11189 DERRMR_PIPEC_PRI_FLIP_DONE));
11191 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11192 MI_SRM_LRM_GLOBAL_GTT);
11194 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11195 MI_SRM_LRM_GLOBAL_GTT);
11196 intel_ring_emit(ring, DERRMR);
11197 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11198 if (IS_GEN8(dev)) {
11199 intel_ring_emit(ring, 0);
11200 intel_ring_emit(ring, MI_NOOP);
11204 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11205 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11206 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11207 intel_ring_emit(ring, (MI_NOOP));
11209 intel_mark_page_flip_active(intel_crtc);
11210 __intel_ring_advance(ring);
11214 static bool use_mmio_flip(struct intel_engine_cs *ring,
11215 struct drm_i915_gem_object *obj)
11218 * This is not being used for older platforms, because
11219 * non-availability of flip done interrupt forces us to use
11220 * CS flips. Older platforms derive flip done using some clever
11221 * tricks involving the flip_pending status bits and vblank irqs.
11222 * So using MMIO flips there would disrupt this mechanism.
11228 if (INTEL_INFO(ring->dev)->gen < 5)
11231 if (i915.use_mmio_flip < 0)
11233 else if (i915.use_mmio_flip > 0)
11235 else if (i915.enable_execlists)
11238 return ring != i915_gem_request_get_ring(obj->last_write_req);
11241 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11243 struct drm_device *dev = intel_crtc->base.dev;
11244 struct drm_i915_private *dev_priv = dev->dev_private;
11245 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11246 const enum pipe pipe = intel_crtc->pipe;
11249 ctl = I915_READ(PLANE_CTL(pipe, 0));
11250 ctl &= ~PLANE_CTL_TILED_MASK;
11251 switch (fb->modifier[0]) {
11252 case DRM_FORMAT_MOD_NONE:
11254 case I915_FORMAT_MOD_X_TILED:
11255 ctl |= PLANE_CTL_TILED_X;
11257 case I915_FORMAT_MOD_Y_TILED:
11258 ctl |= PLANE_CTL_TILED_Y;
11260 case I915_FORMAT_MOD_Yf_TILED:
11261 ctl |= PLANE_CTL_TILED_YF;
11264 MISSING_CASE(fb->modifier[0]);
11268 * The stride is either expressed as a multiple of 64 bytes chunks for
11269 * linear buffers or in number of tiles for tiled buffers.
11271 stride = fb->pitches[0] /
11272 intel_fb_stride_alignment(dev, fb->modifier[0],
11276 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11277 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11279 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11280 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11282 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11283 POSTING_READ(PLANE_SURF(pipe, 0));
11286 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11288 struct drm_device *dev = intel_crtc->base.dev;
11289 struct drm_i915_private *dev_priv = dev->dev_private;
11290 struct intel_framebuffer *intel_fb =
11291 to_intel_framebuffer(intel_crtc->base.primary->fb);
11292 struct drm_i915_gem_object *obj = intel_fb->obj;
11296 reg = DSPCNTR(intel_crtc->plane);
11297 dspcntr = I915_READ(reg);
11299 if (obj->tiling_mode != I915_TILING_NONE)
11300 dspcntr |= DISPPLANE_TILED;
11302 dspcntr &= ~DISPPLANE_TILED;
11304 I915_WRITE(reg, dspcntr);
11306 I915_WRITE(DSPSURF(intel_crtc->plane),
11307 intel_crtc->unpin_work->gtt_offset);
11308 POSTING_READ(DSPSURF(intel_crtc->plane));
11313 * XXX: This is the temporary way to update the plane registers until we get
11314 * around to using the usual plane update functions for MMIO flips
11316 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11318 struct drm_device *dev = intel_crtc->base.dev;
11319 bool atomic_update;
11320 u32 start_vbl_count;
11322 intel_mark_page_flip_active(intel_crtc);
11324 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11326 if (INTEL_INFO(dev)->gen >= 9)
11327 skl_do_mmio_flip(intel_crtc);
11329 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11330 ilk_do_mmio_flip(intel_crtc);
11333 intel_pipe_update_end(intel_crtc, start_vbl_count);
11336 static void intel_mmio_flip_work_func(struct work_struct *work)
11338 struct intel_mmio_flip *mmio_flip =
11339 container_of(work, struct intel_mmio_flip, work);
11341 if (mmio_flip->req)
11342 WARN_ON(__i915_wait_request(mmio_flip->req,
11343 mmio_flip->crtc->reset_counter,
11345 &mmio_flip->i915->rps.mmioflips));
11347 intel_do_mmio_flip(mmio_flip->crtc);
11349 i915_gem_request_unreference__unlocked(mmio_flip->req);
11353 static int intel_queue_mmio_flip(struct drm_device *dev,
11354 struct drm_crtc *crtc,
11355 struct drm_framebuffer *fb,
11356 struct drm_i915_gem_object *obj,
11357 struct intel_engine_cs *ring,
11360 struct intel_mmio_flip *mmio_flip;
11362 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11363 if (mmio_flip == NULL)
11366 mmio_flip->i915 = to_i915(dev);
11367 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11368 mmio_flip->crtc = to_intel_crtc(crtc);
11370 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11371 schedule_work(&mmio_flip->work);
11376 static int intel_default_queue_flip(struct drm_device *dev,
11377 struct drm_crtc *crtc,
11378 struct drm_framebuffer *fb,
11379 struct drm_i915_gem_object *obj,
11380 struct intel_engine_cs *ring,
11386 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11387 struct drm_crtc *crtc)
11389 struct drm_i915_private *dev_priv = dev->dev_private;
11390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11391 struct intel_unpin_work *work = intel_crtc->unpin_work;
11394 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11397 if (!work->enable_stall_check)
11400 if (work->flip_ready_vblank == 0) {
11401 if (work->flip_queued_req &&
11402 !i915_gem_request_completed(work->flip_queued_req, true))
11405 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11408 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11411 /* Potential stall - if we see that the flip has happened,
11412 * assume a missed interrupt. */
11413 if (INTEL_INFO(dev)->gen >= 4)
11414 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11416 addr = I915_READ(DSPADDR(intel_crtc->plane));
11418 /* There is a potential issue here with a false positive after a flip
11419 * to the same address. We could address this by checking for a
11420 * non-incrementing frame counter.
11422 return addr == work->gtt_offset;
11425 void intel_check_page_flip(struct drm_device *dev, int pipe)
11427 struct drm_i915_private *dev_priv = dev->dev_private;
11428 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11430 struct intel_unpin_work *work;
11432 WARN_ON(!in_interrupt());
11437 spin_lock(&dev->event_lock);
11438 work = intel_crtc->unpin_work;
11439 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11440 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11441 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11442 page_flip_completed(intel_crtc);
11445 if (work != NULL &&
11446 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11447 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11448 spin_unlock(&dev->event_lock);
11451 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11452 struct drm_framebuffer *fb,
11453 struct drm_pending_vblank_event *event,
11454 uint32_t page_flip_flags)
11456 struct drm_device *dev = crtc->dev;
11457 struct drm_i915_private *dev_priv = dev->dev_private;
11458 struct drm_framebuffer *old_fb = crtc->primary->fb;
11459 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11461 struct drm_plane *primary = crtc->primary;
11462 enum pipe pipe = intel_crtc->pipe;
11463 struct intel_unpin_work *work;
11464 struct intel_engine_cs *ring;
11469 * drm_mode_page_flip_ioctl() should already catch this, but double
11470 * check to be safe. In the future we may enable pageflipping from
11471 * a disabled primary plane.
11473 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11476 /* Can't change pixel format via MI display flips. */
11477 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11481 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11482 * Note that pitch changes could also affect these register.
11484 if (INTEL_INFO(dev)->gen > 3 &&
11485 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11486 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11489 if (i915_terminally_wedged(&dev_priv->gpu_error))
11492 work = kzalloc(sizeof(*work), GFP_KERNEL);
11496 work->event = event;
11498 work->old_fb = old_fb;
11499 INIT_WORK(&work->work, intel_unpin_work_fn);
11501 ret = drm_crtc_vblank_get(crtc);
11505 /* We borrow the event spin lock for protecting unpin_work */
11506 spin_lock_irq(&dev->event_lock);
11507 if (intel_crtc->unpin_work) {
11508 /* Before declaring the flip queue wedged, check if
11509 * the hardware completed the operation behind our backs.
11511 if (__intel_pageflip_stall_check(dev, crtc)) {
11512 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11513 page_flip_completed(intel_crtc);
11515 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11516 spin_unlock_irq(&dev->event_lock);
11518 drm_crtc_vblank_put(crtc);
11523 intel_crtc->unpin_work = work;
11524 spin_unlock_irq(&dev->event_lock);
11526 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11527 flush_workqueue(dev_priv->wq);
11529 /* Reference the objects for the scheduled work. */
11530 drm_framebuffer_reference(work->old_fb);
11531 drm_gem_object_reference(&obj->base);
11533 crtc->primary->fb = fb;
11534 update_state_fb(crtc->primary);
11536 work->pending_flip_obj = obj;
11538 ret = i915_mutex_lock_interruptible(dev);
11542 atomic_inc(&intel_crtc->unpin_work_count);
11543 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11545 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11546 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11548 if (IS_VALLEYVIEW(dev)) {
11549 ring = &dev_priv->ring[BCS];
11550 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11551 /* vlv: DISPLAY_FLIP fails to change tiling */
11553 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11554 ring = &dev_priv->ring[BCS];
11555 } else if (INTEL_INFO(dev)->gen >= 7) {
11556 ring = i915_gem_request_get_ring(obj->last_write_req);
11557 if (ring == NULL || ring->id != RCS)
11558 ring = &dev_priv->ring[BCS];
11560 ring = &dev_priv->ring[RCS];
11563 mmio_flip = use_mmio_flip(ring, obj);
11565 /* When using CS flips, we want to emit semaphores between rings.
11566 * However, when using mmio flips we will create a task to do the
11567 * synchronisation, so all we want here is to pin the framebuffer
11568 * into the display plane and skip any waits.
11570 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11571 crtc->primary->state,
11572 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11574 goto cleanup_pending;
11576 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11577 + intel_crtc->dspaddr_offset;
11580 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11583 goto cleanup_unpin;
11585 i915_gem_request_assign(&work->flip_queued_req,
11586 obj->last_write_req);
11588 if (obj->last_write_req) {
11589 ret = i915_gem_check_olr(obj->last_write_req);
11591 goto cleanup_unpin;
11594 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11597 goto cleanup_unpin;
11599 i915_gem_request_assign(&work->flip_queued_req,
11600 intel_ring_get_request(ring));
11603 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11604 work->enable_stall_check = true;
11606 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11607 INTEL_FRONTBUFFER_PRIMARY(pipe));
11609 intel_fbc_disable(dev);
11610 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11611 mutex_unlock(&dev->struct_mutex);
11613 trace_i915_flip_request(intel_crtc->plane, obj);
11618 intel_unpin_fb_obj(fb, crtc->primary->state);
11620 atomic_dec(&intel_crtc->unpin_work_count);
11621 mutex_unlock(&dev->struct_mutex);
11623 crtc->primary->fb = old_fb;
11624 update_state_fb(crtc->primary);
11626 drm_gem_object_unreference_unlocked(&obj->base);
11627 drm_framebuffer_unreference(work->old_fb);
11629 spin_lock_irq(&dev->event_lock);
11630 intel_crtc->unpin_work = NULL;
11631 spin_unlock_irq(&dev->event_lock);
11633 drm_crtc_vblank_put(crtc);
11638 struct drm_atomic_state *state;
11639 struct drm_plane_state *plane_state;
11642 state = drm_atomic_state_alloc(dev);
11645 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11648 plane_state = drm_atomic_get_plane_state(state, primary);
11649 ret = PTR_ERR_OR_ZERO(plane_state);
11651 drm_atomic_set_fb_for_plane(plane_state, fb);
11653 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11655 ret = drm_atomic_commit(state);
11658 if (ret == -EDEADLK) {
11659 drm_modeset_backoff(state->acquire_ctx);
11660 drm_atomic_state_clear(state);
11665 drm_atomic_state_free(state);
11667 if (ret == 0 && event) {
11668 spin_lock_irq(&dev->event_lock);
11669 drm_send_vblank_event(dev, pipe, event);
11670 spin_unlock_irq(&dev->event_lock);
11676 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11677 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11678 .load_lut = intel_crtc_load_lut,
11679 .atomic_begin = intel_begin_crtc_commit,
11680 .atomic_flush = intel_finish_crtc_commit,
11684 * intel_modeset_update_staged_output_state
11686 * Updates the staged output configuration state, e.g. after we've read out the
11687 * current hw state.
11689 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11691 struct intel_crtc *crtc;
11692 struct intel_encoder *encoder;
11693 struct intel_connector *connector;
11695 for_each_intel_connector(dev, connector) {
11696 connector->new_encoder =
11697 to_intel_encoder(connector->base.encoder);
11700 for_each_intel_encoder(dev, encoder) {
11701 encoder->new_crtc =
11702 to_intel_crtc(encoder->base.crtc);
11705 for_each_intel_crtc(dev, crtc) {
11706 crtc->new_enabled = crtc->base.state->enable;
11710 /* Transitional helper to copy current connector/encoder state to
11711 * connector->state. This is needed so that code that is partially
11712 * converted to atomic does the right thing.
11714 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11716 struct intel_connector *connector;
11718 for_each_intel_connector(dev, connector) {
11719 if (connector->base.encoder) {
11720 connector->base.state->best_encoder =
11721 connector->base.encoder;
11722 connector->base.state->crtc =
11723 connector->base.encoder->crtc;
11725 connector->base.state->best_encoder = NULL;
11726 connector->base.state->crtc = NULL;
11732 connected_sink_compute_bpp(struct intel_connector *connector,
11733 struct intel_crtc_state *pipe_config)
11735 int bpp = pipe_config->pipe_bpp;
11737 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11738 connector->base.base.id,
11739 connector->base.name);
11741 /* Don't use an invalid EDID bpc value */
11742 if (connector->base.display_info.bpc &&
11743 connector->base.display_info.bpc * 3 < bpp) {
11744 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11745 bpp, connector->base.display_info.bpc*3);
11746 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11749 /* Clamp bpp to 8 on screens without EDID 1.4 */
11750 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11751 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11753 pipe_config->pipe_bpp = 24;
11758 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11759 struct intel_crtc_state *pipe_config)
11761 struct drm_device *dev = crtc->base.dev;
11762 struct drm_atomic_state *state;
11763 struct drm_connector *connector;
11764 struct drm_connector_state *connector_state;
11767 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11769 else if (INTEL_INFO(dev)->gen >= 5)
11775 pipe_config->pipe_bpp = bpp;
11777 state = pipe_config->base.state;
11779 /* Clamp display bpp to EDID value */
11780 for_each_connector_in_state(state, connector, connector_state, i) {
11781 if (connector_state->crtc != &crtc->base)
11784 connected_sink_compute_bpp(to_intel_connector(connector),
11791 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11793 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11794 "type: 0x%x flags: 0x%x\n",
11796 mode->crtc_hdisplay, mode->crtc_hsync_start,
11797 mode->crtc_hsync_end, mode->crtc_htotal,
11798 mode->crtc_vdisplay, mode->crtc_vsync_start,
11799 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11802 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11803 struct intel_crtc_state *pipe_config,
11804 const char *context)
11806 struct drm_device *dev = crtc->base.dev;
11807 struct drm_plane *plane;
11808 struct intel_plane *intel_plane;
11809 struct intel_plane_state *state;
11810 struct drm_framebuffer *fb;
11812 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11813 context, pipe_config, pipe_name(crtc->pipe));
11815 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11816 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11817 pipe_config->pipe_bpp, pipe_config->dither);
11818 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11819 pipe_config->has_pch_encoder,
11820 pipe_config->fdi_lanes,
11821 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11822 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11823 pipe_config->fdi_m_n.tu);
11824 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11825 pipe_config->has_dp_encoder,
11826 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11827 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11828 pipe_config->dp_m_n.tu);
11830 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11831 pipe_config->has_dp_encoder,
11832 pipe_config->dp_m2_n2.gmch_m,
11833 pipe_config->dp_m2_n2.gmch_n,
11834 pipe_config->dp_m2_n2.link_m,
11835 pipe_config->dp_m2_n2.link_n,
11836 pipe_config->dp_m2_n2.tu);
11838 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11839 pipe_config->has_audio,
11840 pipe_config->has_infoframe);
11842 DRM_DEBUG_KMS("requested mode:\n");
11843 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11844 DRM_DEBUG_KMS("adjusted mode:\n");
11845 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11846 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11847 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11848 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11849 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11850 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11852 pipe_config->scaler_state.scaler_users,
11853 pipe_config->scaler_state.scaler_id);
11854 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11855 pipe_config->gmch_pfit.control,
11856 pipe_config->gmch_pfit.pgm_ratios,
11857 pipe_config->gmch_pfit.lvds_border_bits);
11858 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11859 pipe_config->pch_pfit.pos,
11860 pipe_config->pch_pfit.size,
11861 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11862 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11863 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11865 if (IS_BROXTON(dev)) {
11866 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11867 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11868 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11869 pipe_config->ddi_pll_sel,
11870 pipe_config->dpll_hw_state.ebb0,
11871 pipe_config->dpll_hw_state.pll0,
11872 pipe_config->dpll_hw_state.pll1,
11873 pipe_config->dpll_hw_state.pll2,
11874 pipe_config->dpll_hw_state.pll3,
11875 pipe_config->dpll_hw_state.pll6,
11876 pipe_config->dpll_hw_state.pll8,
11877 pipe_config->dpll_hw_state.pcsdw12);
11878 } else if (IS_SKYLAKE(dev)) {
11879 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11880 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11881 pipe_config->ddi_pll_sel,
11882 pipe_config->dpll_hw_state.ctrl1,
11883 pipe_config->dpll_hw_state.cfgcr1,
11884 pipe_config->dpll_hw_state.cfgcr2);
11885 } else if (HAS_DDI(dev)) {
11886 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11887 pipe_config->ddi_pll_sel,
11888 pipe_config->dpll_hw_state.wrpll);
11890 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11891 "fp0: 0x%x, fp1: 0x%x\n",
11892 pipe_config->dpll_hw_state.dpll,
11893 pipe_config->dpll_hw_state.dpll_md,
11894 pipe_config->dpll_hw_state.fp0,
11895 pipe_config->dpll_hw_state.fp1);
11898 DRM_DEBUG_KMS("planes on this crtc\n");
11899 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11900 intel_plane = to_intel_plane(plane);
11901 if (intel_plane->pipe != crtc->pipe)
11904 state = to_intel_plane_state(plane->state);
11905 fb = state->base.fb;
11907 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11908 "disabled, scaler_id = %d\n",
11909 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11910 plane->base.id, intel_plane->pipe,
11911 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11912 drm_plane_index(plane), state->scaler_id);
11916 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11917 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11918 plane->base.id, intel_plane->pipe,
11919 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11920 drm_plane_index(plane));
11921 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11922 fb->base.id, fb->width, fb->height, fb->pixel_format);
11923 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11925 state->src.x1 >> 16, state->src.y1 >> 16,
11926 drm_rect_width(&state->src) >> 16,
11927 drm_rect_height(&state->src) >> 16,
11928 state->dst.x1, state->dst.y1,
11929 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11933 static bool encoders_cloneable(const struct intel_encoder *a,
11934 const struct intel_encoder *b)
11936 /* masks could be asymmetric, so check both ways */
11937 return a == b || (a->cloneable & (1 << b->type) &&
11938 b->cloneable & (1 << a->type));
11941 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11942 struct intel_crtc *crtc,
11943 struct intel_encoder *encoder)
11945 struct intel_encoder *source_encoder;
11946 struct drm_connector *connector;
11947 struct drm_connector_state *connector_state;
11950 for_each_connector_in_state(state, connector, connector_state, i) {
11951 if (connector_state->crtc != &crtc->base)
11955 to_intel_encoder(connector_state->best_encoder);
11956 if (!encoders_cloneable(encoder, source_encoder))
11963 static bool check_encoder_cloning(struct drm_atomic_state *state,
11964 struct intel_crtc *crtc)
11966 struct intel_encoder *encoder;
11967 struct drm_connector *connector;
11968 struct drm_connector_state *connector_state;
11971 for_each_connector_in_state(state, connector, connector_state, i) {
11972 if (connector_state->crtc != &crtc->base)
11975 encoder = to_intel_encoder(connector_state->best_encoder);
11976 if (!check_single_encoder_cloning(state, crtc, encoder))
11983 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11985 struct drm_device *dev = state->dev;
11986 struct intel_encoder *encoder;
11987 struct drm_connector *connector;
11988 struct drm_connector_state *connector_state;
11989 unsigned int used_ports = 0;
11993 * Walk the connector list instead of the encoder
11994 * list to detect the problem on ddi platforms
11995 * where there's just one encoder per digital port.
11997 for_each_connector_in_state(state, connector, connector_state, i) {
11998 if (!connector_state->best_encoder)
12001 encoder = to_intel_encoder(connector_state->best_encoder);
12003 WARN_ON(!connector_state->crtc);
12005 switch (encoder->type) {
12006 unsigned int port_mask;
12007 case INTEL_OUTPUT_UNKNOWN:
12008 if (WARN_ON(!HAS_DDI(dev)))
12010 case INTEL_OUTPUT_DISPLAYPORT:
12011 case INTEL_OUTPUT_HDMI:
12012 case INTEL_OUTPUT_EDP:
12013 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12015 /* the same port mustn't appear more than once */
12016 if (used_ports & port_mask)
12019 used_ports |= port_mask;
12029 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12031 struct drm_crtc_state tmp_state;
12032 struct intel_crtc_scaler_state scaler_state;
12033 struct intel_dpll_hw_state dpll_hw_state;
12034 enum intel_dpll_id shared_dpll;
12035 uint32_t ddi_pll_sel;
12037 /* FIXME: before the switch to atomic started, a new pipe_config was
12038 * kzalloc'd. Code that depends on any field being zero should be
12039 * fixed, so that the crtc_state can be safely duplicated. For now,
12040 * only fields that are know to not cause problems are preserved. */
12042 tmp_state = crtc_state->base;
12043 scaler_state = crtc_state->scaler_state;
12044 shared_dpll = crtc_state->shared_dpll;
12045 dpll_hw_state = crtc_state->dpll_hw_state;
12046 ddi_pll_sel = crtc_state->ddi_pll_sel;
12048 memset(crtc_state, 0, sizeof *crtc_state);
12050 crtc_state->base = tmp_state;
12051 crtc_state->scaler_state = scaler_state;
12052 crtc_state->shared_dpll = shared_dpll;
12053 crtc_state->dpll_hw_state = dpll_hw_state;
12054 crtc_state->ddi_pll_sel = ddi_pll_sel;
12058 intel_modeset_pipe_config(struct drm_crtc *crtc,
12059 struct drm_atomic_state *state)
12061 struct drm_crtc_state *crtc_state;
12062 struct intel_crtc_state *pipe_config;
12063 struct intel_encoder *encoder;
12064 struct drm_connector *connector;
12065 struct drm_connector_state *connector_state;
12066 int base_bpp, ret = -EINVAL;
12070 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
12071 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12075 if (!check_digital_port_conflicts(state)) {
12076 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12080 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12081 if (WARN_ON(!crtc_state))
12084 pipe_config = to_intel_crtc_state(crtc_state);
12087 * XXX: Add all connectors to make the crtc state match the encoders.
12089 if (!needs_modeset(&pipe_config->base)) {
12090 ret = drm_atomic_add_affected_connectors(state, crtc);
12095 clear_intel_crtc_state(pipe_config);
12097 pipe_config->cpu_transcoder =
12098 (enum transcoder) to_intel_crtc(crtc)->pipe;
12101 * Sanitize sync polarity flags based on requested ones. If neither
12102 * positive or negative polarity is requested, treat this as meaning
12103 * negative polarity.
12105 if (!(pipe_config->base.adjusted_mode.flags &
12106 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12107 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12109 if (!(pipe_config->base.adjusted_mode.flags &
12110 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12111 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12113 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12114 * plane pixel format and any sink constraints into account. Returns the
12115 * source plane bpp so that dithering can be selected on mismatches
12116 * after encoders and crtc also have had their say. */
12117 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12123 * Determine the real pipe dimensions. Note that stereo modes can
12124 * increase the actual pipe size due to the frame doubling and
12125 * insertion of additional space for blanks between the frame. This
12126 * is stored in the crtc timings. We use the requested mode to do this
12127 * computation to clearly distinguish it from the adjusted mode, which
12128 * can be changed by the connectors in the below retry loop.
12130 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12131 &pipe_config->pipe_src_w,
12132 &pipe_config->pipe_src_h);
12135 /* Ensure the port clock defaults are reset when retrying. */
12136 pipe_config->port_clock = 0;
12137 pipe_config->pixel_multiplier = 1;
12139 /* Fill in default crtc timings, allow encoders to overwrite them. */
12140 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12141 CRTC_STEREO_DOUBLE);
12143 /* Pass our mode to the connectors and the CRTC to give them a chance to
12144 * adjust it according to limitations or connector properties, and also
12145 * a chance to reject the mode entirely.
12147 for_each_connector_in_state(state, connector, connector_state, i) {
12148 if (connector_state->crtc != crtc)
12151 encoder = to_intel_encoder(connector_state->best_encoder);
12153 if (!(encoder->compute_config(encoder, pipe_config))) {
12154 DRM_DEBUG_KMS("Encoder config failure\n");
12159 /* Set default port clock if not overwritten by the encoder. Needs to be
12160 * done afterwards in case the encoder adjusts the mode. */
12161 if (!pipe_config->port_clock)
12162 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12163 * pipe_config->pixel_multiplier;
12165 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12167 DRM_DEBUG_KMS("CRTC fixup failed\n");
12171 if (ret == RETRY) {
12172 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12177 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12179 goto encoder_retry;
12182 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12183 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12184 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12186 /* Check if we need to force a modeset */
12187 if (pipe_config->has_audio !=
12188 to_intel_crtc_state(crtc->state)->has_audio) {
12189 pipe_config->base.mode_changed = true;
12190 ret = drm_atomic_add_affected_planes(state, crtc);
12194 * Note we have an issue here with infoframes: current code
12195 * only updates them on the full mode set path per hw
12196 * requirements. So here we should be checking for any
12197 * required changes and forcing a mode set.
12203 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12205 struct drm_encoder *encoder;
12206 struct drm_device *dev = crtc->dev;
12208 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12209 if (encoder->crtc == crtc)
12216 intel_modeset_update_state(struct drm_atomic_state *state)
12218 struct drm_device *dev = state->dev;
12219 struct intel_encoder *intel_encoder;
12220 struct drm_crtc *crtc;
12221 struct drm_crtc_state *crtc_state;
12222 struct drm_connector *connector;
12224 intel_shared_dpll_commit(state);
12226 for_each_intel_encoder(dev, intel_encoder) {
12227 if (!intel_encoder->base.crtc)
12230 crtc = intel_encoder->base.crtc;
12231 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12232 if (!crtc_state || !needs_modeset(crtc->state))
12235 intel_encoder->connectors_active = false;
12238 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12239 intel_modeset_update_staged_output_state(state->dev);
12241 /* Double check state. */
12242 for_each_crtc(dev, crtc) {
12243 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12245 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12247 /* Update hwmode for vblank functions */
12248 if (crtc->state->active)
12249 crtc->hwmode = crtc->state->adjusted_mode;
12251 crtc->hwmode.crtc_clock = 0;
12254 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12255 if (!connector->encoder || !connector->encoder->crtc)
12258 crtc = connector->encoder->crtc;
12259 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12260 if (!crtc_state || !needs_modeset(crtc->state))
12263 if (crtc->state->active) {
12264 struct drm_property *dpms_property =
12265 dev->mode_config.dpms_property;
12267 connector->dpms = DRM_MODE_DPMS_ON;
12268 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12270 intel_encoder = to_intel_encoder(connector->encoder);
12271 intel_encoder->connectors_active = true;
12273 connector->dpms = DRM_MODE_DPMS_OFF;
12277 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12281 if (clock1 == clock2)
12284 if (!clock1 || !clock2)
12287 diff = abs(clock1 - clock2);
12289 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12295 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12296 list_for_each_entry((intel_crtc), \
12297 &(dev)->mode_config.crtc_list, \
12299 if (mask & (1 <<(intel_crtc)->pipe))
12302 intel_pipe_config_compare(struct drm_device *dev,
12303 struct intel_crtc_state *current_config,
12304 struct intel_crtc_state *pipe_config)
12306 #define PIPE_CONF_CHECK_X(name) \
12307 if (current_config->name != pipe_config->name) { \
12308 DRM_ERROR("mismatch in " #name " " \
12309 "(expected 0x%08x, found 0x%08x)\n", \
12310 current_config->name, \
12311 pipe_config->name); \
12315 #define PIPE_CONF_CHECK_I(name) \
12316 if (current_config->name != pipe_config->name) { \
12317 DRM_ERROR("mismatch in " #name " " \
12318 "(expected %i, found %i)\n", \
12319 current_config->name, \
12320 pipe_config->name); \
12324 /* This is required for BDW+ where there is only one set of registers for
12325 * switching between high and low RR.
12326 * This macro can be used whenever a comparison has to be made between one
12327 * hw state and multiple sw state variables.
12329 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12330 if ((current_config->name != pipe_config->name) && \
12331 (current_config->alt_name != pipe_config->name)) { \
12332 DRM_ERROR("mismatch in " #name " " \
12333 "(expected %i or %i, found %i)\n", \
12334 current_config->name, \
12335 current_config->alt_name, \
12336 pipe_config->name); \
12340 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12341 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12342 DRM_ERROR("mismatch in " #name "(" #mask ") " \
12343 "(expected %i, found %i)\n", \
12344 current_config->name & (mask), \
12345 pipe_config->name & (mask)); \
12349 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12350 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12351 DRM_ERROR("mismatch in " #name " " \
12352 "(expected %i, found %i)\n", \
12353 current_config->name, \
12354 pipe_config->name); \
12358 #define PIPE_CONF_QUIRK(quirk) \
12359 ((current_config->quirks | pipe_config->quirks) & (quirk))
12361 PIPE_CONF_CHECK_I(cpu_transcoder);
12363 PIPE_CONF_CHECK_I(has_pch_encoder);
12364 PIPE_CONF_CHECK_I(fdi_lanes);
12365 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12366 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12367 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12368 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12369 PIPE_CONF_CHECK_I(fdi_m_n.tu);
12371 PIPE_CONF_CHECK_I(has_dp_encoder);
12373 if (INTEL_INFO(dev)->gen < 8) {
12374 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12375 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12376 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12377 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12378 PIPE_CONF_CHECK_I(dp_m_n.tu);
12380 if (current_config->has_drrs) {
12381 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12382 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12383 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12384 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12385 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12388 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12389 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12390 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12391 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12392 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12395 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12396 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12397 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12398 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12399 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12400 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12409 PIPE_CONF_CHECK_I(pixel_multiplier);
12410 PIPE_CONF_CHECK_I(has_hdmi_sink);
12411 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12412 IS_VALLEYVIEW(dev))
12413 PIPE_CONF_CHECK_I(limited_color_range);
12414 PIPE_CONF_CHECK_I(has_infoframe);
12416 PIPE_CONF_CHECK_I(has_audio);
12418 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12419 DRM_MODE_FLAG_INTERLACE);
12421 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12422 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12423 DRM_MODE_FLAG_PHSYNC);
12424 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12425 DRM_MODE_FLAG_NHSYNC);
12426 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12427 DRM_MODE_FLAG_PVSYNC);
12428 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12429 DRM_MODE_FLAG_NVSYNC);
12432 PIPE_CONF_CHECK_I(pipe_src_w);
12433 PIPE_CONF_CHECK_I(pipe_src_h);
12436 * FIXME: BIOS likes to set up a cloned config with lvds+external
12437 * screen. Since we don't yet re-compute the pipe config when moving
12438 * just the lvds port away to another pipe the sw tracking won't match.
12440 * Proper atomic modesets with recomputed global state will fix this.
12441 * Until then just don't check gmch state for inherited modes.
12443 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12444 PIPE_CONF_CHECK_I(gmch_pfit.control);
12445 /* pfit ratios are autocomputed by the hw on gen4+ */
12446 if (INTEL_INFO(dev)->gen < 4)
12447 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12448 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12451 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12452 if (current_config->pch_pfit.enabled) {
12453 PIPE_CONF_CHECK_I(pch_pfit.pos);
12454 PIPE_CONF_CHECK_I(pch_pfit.size);
12457 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12459 /* BDW+ don't expose a synchronous way to read the state */
12460 if (IS_HASWELL(dev))
12461 PIPE_CONF_CHECK_I(ips_enabled);
12463 PIPE_CONF_CHECK_I(double_wide);
12465 PIPE_CONF_CHECK_X(ddi_pll_sel);
12467 PIPE_CONF_CHECK_I(shared_dpll);
12468 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12469 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12470 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12471 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12472 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12473 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12474 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12475 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12477 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12478 PIPE_CONF_CHECK_I(pipe_bpp);
12480 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12481 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12483 #undef PIPE_CONF_CHECK_X
12484 #undef PIPE_CONF_CHECK_I
12485 #undef PIPE_CONF_CHECK_I_ALT
12486 #undef PIPE_CONF_CHECK_FLAGS
12487 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12488 #undef PIPE_CONF_QUIRK
12493 static void check_wm_state(struct drm_device *dev)
12495 struct drm_i915_private *dev_priv = dev->dev_private;
12496 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12497 struct intel_crtc *intel_crtc;
12500 if (INTEL_INFO(dev)->gen < 9)
12503 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12504 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12506 for_each_intel_crtc(dev, intel_crtc) {
12507 struct skl_ddb_entry *hw_entry, *sw_entry;
12508 const enum pipe pipe = intel_crtc->pipe;
12510 if (!intel_crtc->active)
12514 for_each_plane(dev_priv, pipe, plane) {
12515 hw_entry = &hw_ddb.plane[pipe][plane];
12516 sw_entry = &sw_ddb->plane[pipe][plane];
12518 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12521 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12522 "(expected (%u,%u), found (%u,%u))\n",
12523 pipe_name(pipe), plane + 1,
12524 sw_entry->start, sw_entry->end,
12525 hw_entry->start, hw_entry->end);
12529 hw_entry = &hw_ddb.cursor[pipe];
12530 sw_entry = &sw_ddb->cursor[pipe];
12532 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12535 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12536 "(expected (%u,%u), found (%u,%u))\n",
12538 sw_entry->start, sw_entry->end,
12539 hw_entry->start, hw_entry->end);
12544 check_connector_state(struct drm_device *dev)
12546 struct intel_connector *connector;
12548 for_each_intel_connector(dev, connector) {
12549 /* This also checks the encoder/connector hw state with the
12550 * ->get_hw_state callbacks. */
12551 intel_connector_check_state(connector);
12553 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12554 "connector's staged encoder doesn't match current encoder\n");
12559 check_encoder_state(struct drm_device *dev)
12561 struct intel_encoder *encoder;
12562 struct intel_connector *connector;
12564 for_each_intel_encoder(dev, encoder) {
12565 bool enabled = false;
12566 bool active = false;
12567 enum pipe pipe, tracked_pipe;
12569 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12570 encoder->base.base.id,
12571 encoder->base.name);
12573 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12574 "encoder's stage crtc doesn't match current crtc\n");
12575 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12576 "encoder's active_connectors set, but no crtc\n");
12578 for_each_intel_connector(dev, connector) {
12579 if (connector->base.encoder != &encoder->base)
12582 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12586 * for MST connectors if we unplug the connector is gone
12587 * away but the encoder is still connected to a crtc
12588 * until a modeset happens in response to the hotplug.
12590 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12593 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12594 "encoder's enabled state mismatch "
12595 "(expected %i, found %i)\n",
12596 !!encoder->base.crtc, enabled);
12597 I915_STATE_WARN(active && !encoder->base.crtc,
12598 "active encoder with no crtc\n");
12600 I915_STATE_WARN(encoder->connectors_active != active,
12601 "encoder's computed active state doesn't match tracked active state "
12602 "(expected %i, found %i)\n", active, encoder->connectors_active);
12604 active = encoder->get_hw_state(encoder, &pipe);
12605 I915_STATE_WARN(active != encoder->connectors_active,
12606 "encoder's hw state doesn't match sw tracking "
12607 "(expected %i, found %i)\n",
12608 encoder->connectors_active, active);
12610 if (!encoder->base.crtc)
12613 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12614 I915_STATE_WARN(active && pipe != tracked_pipe,
12615 "active encoder's pipe doesn't match"
12616 "(expected %i, found %i)\n",
12617 tracked_pipe, pipe);
12623 check_crtc_state(struct drm_device *dev)
12625 struct drm_i915_private *dev_priv = dev->dev_private;
12626 struct intel_crtc *crtc;
12627 struct intel_encoder *encoder;
12628 struct intel_crtc_state pipe_config;
12630 for_each_intel_crtc(dev, crtc) {
12631 bool enabled = false;
12632 bool active = false;
12634 memset(&pipe_config, 0, sizeof(pipe_config));
12636 DRM_DEBUG_KMS("[CRTC:%d]\n",
12637 crtc->base.base.id);
12639 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12640 "active crtc, but not enabled in sw tracking\n");
12642 for_each_intel_encoder(dev, encoder) {
12643 if (encoder->base.crtc != &crtc->base)
12646 if (encoder->connectors_active)
12650 I915_STATE_WARN(active != crtc->active,
12651 "crtc's computed active state doesn't match tracked active state "
12652 "(expected %i, found %i)\n", active, crtc->active);
12653 I915_STATE_WARN(enabled != crtc->base.state->enable,
12654 "crtc's computed enabled state doesn't match tracked enabled state "
12655 "(expected %i, found %i)\n", enabled,
12656 crtc->base.state->enable);
12658 active = dev_priv->display.get_pipe_config(crtc,
12661 /* hw state is inconsistent with the pipe quirk */
12662 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12663 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12664 active = crtc->active;
12666 for_each_intel_encoder(dev, encoder) {
12668 if (encoder->base.crtc != &crtc->base)
12670 if (encoder->get_hw_state(encoder, &pipe))
12671 encoder->get_config(encoder, &pipe_config);
12674 I915_STATE_WARN(crtc->active != active,
12675 "crtc active state doesn't match with hw state "
12676 "(expected %i, found %i)\n", crtc->active, active);
12678 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12679 "transitional active state does not match atomic hw state "
12680 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12683 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12684 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12685 intel_dump_pipe_config(crtc, &pipe_config,
12687 intel_dump_pipe_config(crtc, crtc->config,
12694 check_shared_dpll_state(struct drm_device *dev)
12696 struct drm_i915_private *dev_priv = dev->dev_private;
12697 struct intel_crtc *crtc;
12698 struct intel_dpll_hw_state dpll_hw_state;
12701 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12702 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12703 int enabled_crtcs = 0, active_crtcs = 0;
12706 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12708 DRM_DEBUG_KMS("%s\n", pll->name);
12710 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12712 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12713 "more active pll users than references: %i vs %i\n",
12714 pll->active, hweight32(pll->config.crtc_mask));
12715 I915_STATE_WARN(pll->active && !pll->on,
12716 "pll in active use but not on in sw tracking\n");
12717 I915_STATE_WARN(pll->on && !pll->active,
12718 "pll in on but not on in use in sw tracking\n");
12719 I915_STATE_WARN(pll->on != active,
12720 "pll on state mismatch (expected %i, found %i)\n",
12723 for_each_intel_crtc(dev, crtc) {
12724 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12726 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12729 I915_STATE_WARN(pll->active != active_crtcs,
12730 "pll active crtcs mismatch (expected %i, found %i)\n",
12731 pll->active, active_crtcs);
12732 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12733 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12734 hweight32(pll->config.crtc_mask), enabled_crtcs);
12736 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12737 sizeof(dpll_hw_state)),
12738 "pll hw state mismatch\n");
12743 intel_modeset_check_state(struct drm_device *dev)
12745 check_wm_state(dev);
12746 check_connector_state(dev);
12747 check_encoder_state(dev);
12748 check_crtc_state(dev);
12749 check_shared_dpll_state(dev);
12752 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12756 * FDI already provided one idea for the dotclock.
12757 * Yell if the encoder disagrees.
12759 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12760 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12761 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12764 static void update_scanline_offset(struct intel_crtc *crtc)
12766 struct drm_device *dev = crtc->base.dev;
12769 * The scanline counter increments at the leading edge of hsync.
12771 * On most platforms it starts counting from vtotal-1 on the
12772 * first active line. That means the scanline counter value is
12773 * always one less than what we would expect. Ie. just after
12774 * start of vblank, which also occurs at start of hsync (on the
12775 * last active line), the scanline counter will read vblank_start-1.
12777 * On gen2 the scanline counter starts counting from 1 instead
12778 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12779 * to keep the value positive), instead of adding one.
12781 * On HSW+ the behaviour of the scanline counter depends on the output
12782 * type. For DP ports it behaves like most other platforms, but on HDMI
12783 * there's an extra 1 line difference. So we need to add two instead of
12784 * one to the value.
12786 if (IS_GEN2(dev)) {
12787 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12790 vtotal = mode->crtc_vtotal;
12791 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12794 crtc->scanline_offset = vtotal - 1;
12795 } else if (HAS_DDI(dev) &&
12796 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12797 crtc->scanline_offset = 2;
12799 crtc->scanline_offset = 1;
12802 static int intel_modeset_setup_plls(struct drm_atomic_state *state)
12804 struct drm_device *dev = state->dev;
12805 struct drm_i915_private *dev_priv = to_i915(dev);
12806 unsigned clear_pipes = 0;
12807 struct intel_crtc *intel_crtc;
12808 struct intel_crtc_state *intel_crtc_state;
12809 struct drm_crtc *crtc;
12810 struct drm_crtc_state *crtc_state;
12814 if (!dev_priv->display.crtc_compute_clock)
12817 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12818 intel_crtc = to_intel_crtc(crtc);
12819 intel_crtc_state = to_intel_crtc_state(crtc_state);
12821 if (needs_modeset(crtc_state)) {
12822 clear_pipes |= 1 << intel_crtc->pipe;
12823 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12828 struct intel_shared_dpll_config *shared_dpll =
12829 intel_atomic_get_shared_dpll_state(state);
12831 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12832 shared_dpll[i].crtc_mask &= ~clear_pipes;
12835 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12836 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12839 intel_crtc = to_intel_crtc(crtc);
12840 intel_crtc_state = to_intel_crtc_state(crtc_state);
12842 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12852 * This implements the workaround described in the "notes" section of the mode
12853 * set sequence documentation. When going from no pipes or single pipe to
12854 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12855 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12857 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12859 struct drm_crtc_state *crtc_state;
12860 struct intel_crtc *intel_crtc;
12861 struct drm_crtc *crtc;
12862 struct intel_crtc_state *first_crtc_state = NULL;
12863 struct intel_crtc_state *other_crtc_state = NULL;
12864 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12867 /* look at all crtc's that are going to be enabled in during modeset */
12868 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12869 intel_crtc = to_intel_crtc(crtc);
12871 if (!crtc_state->active || !needs_modeset(crtc_state))
12874 if (first_crtc_state) {
12875 other_crtc_state = to_intel_crtc_state(crtc_state);
12878 first_crtc_state = to_intel_crtc_state(crtc_state);
12879 first_pipe = intel_crtc->pipe;
12883 /* No workaround needed? */
12884 if (!first_crtc_state)
12887 /* w/a possibly needed, check how many crtc's are already enabled. */
12888 for_each_intel_crtc(state->dev, intel_crtc) {
12889 struct intel_crtc_state *pipe_config;
12891 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12892 if (IS_ERR(pipe_config))
12893 return PTR_ERR(pipe_config);
12895 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12897 if (!pipe_config->base.active ||
12898 needs_modeset(&pipe_config->base))
12901 /* 2 or more enabled crtcs means no need for w/a */
12902 if (enabled_pipe != INVALID_PIPE)
12905 enabled_pipe = intel_crtc->pipe;
12908 if (enabled_pipe != INVALID_PIPE)
12909 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12910 else if (other_crtc_state)
12911 other_crtc_state->hsw_workaround_pipe = first_pipe;
12916 /* Code that should eventually be part of atomic_check() */
12917 static int intel_modeset_checks(struct drm_atomic_state *state)
12919 struct drm_device *dev = state->dev;
12923 * See if the config requires any additional preparation, e.g.
12924 * to adjust global state with pipes off. We need to do this
12925 * here so we can get the modeset_pipe updated config for the new
12926 * mode set on this crtc. For other crtcs we need to use the
12927 * adjusted_mode bits in the crtc directly.
12929 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12930 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12931 ret = valleyview_modeset_global_pipes(state);
12933 ret = broadwell_modeset_global_pipes(state);
12939 ret = intel_modeset_setup_plls(state);
12943 if (IS_HASWELL(dev))
12944 ret = haswell_mode_set_planes_workaround(state);
12950 intel_modeset_compute_config(struct drm_atomic_state *state)
12952 struct drm_crtc *crtc;
12953 struct drm_crtc_state *crtc_state;
12956 ret = drm_atomic_helper_check_modeset(state->dev, state);
12960 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12961 if (!crtc_state->enable &&
12962 WARN_ON(crtc_state->active))
12963 crtc_state->active = false;
12965 if (!crtc_state->enable)
12968 ret = intel_modeset_pipe_config(crtc, state);
12972 intel_dump_pipe_config(to_intel_crtc(crtc),
12973 to_intel_crtc_state(crtc_state),
12977 ret = intel_modeset_checks(state);
12981 return drm_atomic_helper_check_planes(state->dev, state);
12984 static int __intel_set_mode(struct drm_atomic_state *state)
12986 struct drm_device *dev = state->dev;
12987 struct drm_i915_private *dev_priv = dev->dev_private;
12988 struct drm_crtc *crtc;
12989 struct drm_crtc_state *crtc_state;
12993 ret = drm_atomic_helper_prepare_planes(dev, state);
12997 drm_atomic_helper_swap_state(dev, state);
12999 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13000 if (!needs_modeset(crtc->state) || !crtc_state->active)
13003 intel_crtc_disable_planes(crtc);
13004 dev_priv->display.crtc_disable(crtc);
13007 /* Only after disabling all output pipelines that will be changed can we
13008 * update the the output configuration. */
13009 intel_modeset_update_state(state);
13011 /* The state has been swaped above, so state actually contains the
13012 * old state now. */
13014 modeset_update_crtc_power_domains(state);
13016 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13017 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13018 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13020 if (!needs_modeset(crtc->state) || !crtc->state->active)
13023 update_scanline_offset(to_intel_crtc(crtc));
13025 dev_priv->display.crtc_enable(crtc);
13026 intel_crtc_enable_planes(crtc);
13029 /* FIXME: add subpixel order */
13031 drm_atomic_helper_cleanup_planes(dev, state);
13033 drm_atomic_state_free(state);
13038 static int intel_set_mode_checked(struct drm_atomic_state *state)
13040 struct drm_device *dev = state->dev;
13043 ret = __intel_set_mode(state);
13045 intel_modeset_check_state(dev);
13050 static int intel_set_mode(struct drm_atomic_state *state)
13054 ret = intel_modeset_compute_config(state);
13058 return intel_set_mode_checked(state);
13061 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13063 struct drm_device *dev = crtc->dev;
13064 struct drm_atomic_state *state;
13065 struct intel_crtc *intel_crtc;
13066 struct intel_encoder *encoder;
13067 struct intel_connector *connector;
13068 struct drm_connector_state *connector_state;
13069 struct intel_crtc_state *crtc_state;
13072 state = drm_atomic_state_alloc(dev);
13074 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13079 state->acquire_ctx = dev->mode_config.acquire_ctx;
13081 /* The force restore path in the HW readout code relies on the staged
13082 * config still keeping the user requested config while the actual
13083 * state has been overwritten by the configuration read from HW. We
13084 * need to copy the staged config to the atomic state, otherwise the
13085 * mode set will just reapply the state the HW is already in. */
13086 for_each_intel_encoder(dev, encoder) {
13087 if (&encoder->new_crtc->base != crtc)
13090 for_each_intel_connector(dev, connector) {
13091 if (connector->new_encoder != encoder)
13094 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13095 if (IS_ERR(connector_state)) {
13096 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13097 connector->base.base.id,
13098 connector->base.name,
13099 PTR_ERR(connector_state));
13103 connector_state->crtc = crtc;
13104 connector_state->best_encoder = &encoder->base;
13108 for_each_intel_crtc(dev, intel_crtc) {
13109 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13112 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13113 if (IS_ERR(crtc_state)) {
13114 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13115 intel_crtc->base.base.id,
13116 PTR_ERR(crtc_state));
13120 crtc_state->base.active = crtc_state->base.enable =
13121 intel_crtc->new_enabled;
13123 if (&intel_crtc->base == crtc)
13124 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13127 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13128 crtc->primary->fb, crtc->x, crtc->y);
13130 ret = intel_set_mode(state);
13132 drm_atomic_state_free(state);
13135 #undef for_each_intel_crtc_masked
13137 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13138 struct drm_mode_set *set)
13142 for (ro = 0; ro < set->num_connectors; ro++)
13143 if (set->connectors[ro] == &connector->base)
13150 intel_modeset_stage_output_state(struct drm_device *dev,
13151 struct drm_mode_set *set,
13152 struct drm_atomic_state *state)
13154 struct intel_connector *connector;
13155 struct drm_connector *drm_connector;
13156 struct drm_connector_state *connector_state;
13157 struct drm_crtc *crtc;
13158 struct drm_crtc_state *crtc_state;
13161 /* The upper layers ensure that we either disable a crtc or have a list
13162 * of connectors. For paranoia, double-check this. */
13163 WARN_ON(!set->fb && (set->num_connectors != 0));
13164 WARN_ON(set->fb && (set->num_connectors == 0));
13166 for_each_intel_connector(dev, connector) {
13167 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13169 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13173 drm_atomic_get_connector_state(state, &connector->base);
13174 if (IS_ERR(connector_state))
13175 return PTR_ERR(connector_state);
13178 int pipe = to_intel_crtc(set->crtc)->pipe;
13179 connector_state->best_encoder =
13180 &intel_find_encoder(connector, pipe)->base;
13183 if (connector->base.state->crtc != set->crtc)
13186 /* If we disable the crtc, disable all its connectors. Also, if
13187 * the connector is on the changing crtc but not on the new
13188 * connector list, disable it. */
13189 if (!set->fb || !in_mode_set) {
13190 connector_state->best_encoder = NULL;
13192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13193 connector->base.base.id,
13194 connector->base.name);
13197 /* connector->new_encoder is now updated for all connectors. */
13199 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13200 connector = to_intel_connector(drm_connector);
13202 if (!connector_state->best_encoder) {
13203 ret = drm_atomic_set_crtc_for_connector(connector_state,
13211 if (intel_connector_in_mode_set(connector, set)) {
13212 struct drm_crtc *crtc = connector->base.state->crtc;
13214 /* If this connector was in a previous crtc, add it
13215 * to the state. We might need to disable it. */
13218 drm_atomic_get_crtc_state(state, crtc);
13219 if (IS_ERR(crtc_state))
13220 return PTR_ERR(crtc_state);
13223 ret = drm_atomic_set_crtc_for_connector(connector_state,
13229 /* Make sure the new CRTC will work with the encoder */
13230 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13231 connector_state->crtc)) {
13235 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13236 connector->base.base.id,
13237 connector->base.name,
13238 connector_state->crtc->base.id);
13240 if (connector_state->best_encoder != &connector->encoder->base)
13241 connector->encoder =
13242 to_intel_encoder(connector_state->best_encoder);
13245 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13246 bool has_connectors;
13248 ret = drm_atomic_add_affected_connectors(state, crtc);
13252 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13253 if (has_connectors != crtc_state->enable)
13254 crtc_state->enable =
13255 crtc_state->active = has_connectors;
13258 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13259 set->fb, set->x, set->y);
13263 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13264 if (IS_ERR(crtc_state))
13265 return PTR_ERR(crtc_state);
13267 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13271 if (set->num_connectors)
13272 crtc_state->active = true;
13277 static int intel_crtc_set_config(struct drm_mode_set *set)
13279 struct drm_device *dev;
13280 struct drm_atomic_state *state = NULL;
13284 BUG_ON(!set->crtc);
13285 BUG_ON(!set->crtc->helper_private);
13287 /* Enforce sane interface api - has been abused by the fb helper. */
13288 BUG_ON(!set->mode && set->fb);
13289 BUG_ON(set->fb && set->num_connectors == 0);
13292 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13293 set->crtc->base.id, set->fb->base.id,
13294 (int)set->num_connectors, set->x, set->y);
13296 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13299 dev = set->crtc->dev;
13301 state = drm_atomic_state_alloc(dev);
13305 state->acquire_ctx = dev->mode_config.acquire_ctx;
13307 ret = intel_modeset_stage_output_state(dev, set, state);
13311 ret = intel_modeset_compute_config(state);
13315 intel_update_pipe_size(to_intel_crtc(set->crtc));
13317 ret = intel_set_mode_checked(state);
13319 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13320 set->crtc->base.id, ret);
13325 drm_atomic_state_free(state);
13329 static const struct drm_crtc_funcs intel_crtc_funcs = {
13330 .gamma_set = intel_crtc_gamma_set,
13331 .set_config = intel_crtc_set_config,
13332 .destroy = intel_crtc_destroy,
13333 .page_flip = intel_crtc_page_flip,
13334 .atomic_duplicate_state = intel_crtc_duplicate_state,
13335 .atomic_destroy_state = intel_crtc_destroy_state,
13338 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13339 struct intel_shared_dpll *pll,
13340 struct intel_dpll_hw_state *hw_state)
13344 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13347 val = I915_READ(PCH_DPLL(pll->id));
13348 hw_state->dpll = val;
13349 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13350 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13352 return val & DPLL_VCO_ENABLE;
13355 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13356 struct intel_shared_dpll *pll)
13358 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13359 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13362 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13363 struct intel_shared_dpll *pll)
13365 /* PCH refclock must be enabled first */
13366 ibx_assert_pch_refclk_enabled(dev_priv);
13368 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13370 /* Wait for the clocks to stabilize. */
13371 POSTING_READ(PCH_DPLL(pll->id));
13374 /* The pixel multiplier can only be updated once the
13375 * DPLL is enabled and the clocks are stable.
13377 * So write it again.
13379 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13380 POSTING_READ(PCH_DPLL(pll->id));
13384 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13385 struct intel_shared_dpll *pll)
13387 struct drm_device *dev = dev_priv->dev;
13388 struct intel_crtc *crtc;
13390 /* Make sure no transcoder isn't still depending on us. */
13391 for_each_intel_crtc(dev, crtc) {
13392 if (intel_crtc_to_shared_dpll(crtc) == pll)
13393 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13396 I915_WRITE(PCH_DPLL(pll->id), 0);
13397 POSTING_READ(PCH_DPLL(pll->id));
13401 static char *ibx_pch_dpll_names[] = {
13406 static void ibx_pch_dpll_init(struct drm_device *dev)
13408 struct drm_i915_private *dev_priv = dev->dev_private;
13411 dev_priv->num_shared_dpll = 2;
13413 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13414 dev_priv->shared_dplls[i].id = i;
13415 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13416 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13417 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13418 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13419 dev_priv->shared_dplls[i].get_hw_state =
13420 ibx_pch_dpll_get_hw_state;
13424 static void intel_shared_dpll_init(struct drm_device *dev)
13426 struct drm_i915_private *dev_priv = dev->dev_private;
13428 intel_update_cdclk(dev);
13431 intel_ddi_pll_init(dev);
13432 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13433 ibx_pch_dpll_init(dev);
13435 dev_priv->num_shared_dpll = 0;
13437 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13441 * intel_wm_need_update - Check whether watermarks need updating
13442 * @plane: drm plane
13443 * @state: new plane state
13445 * Check current plane state versus the new one to determine whether
13446 * watermarks need to be recalculated.
13448 * Returns true or false.
13450 bool intel_wm_need_update(struct drm_plane *plane,
13451 struct drm_plane_state *state)
13453 /* Update watermarks on tiling changes. */
13454 if (!plane->state->fb || !state->fb ||
13455 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13456 plane->state->rotation != state->rotation)
13463 * intel_prepare_plane_fb - Prepare fb for usage on plane
13464 * @plane: drm plane to prepare for
13465 * @fb: framebuffer to prepare for presentation
13467 * Prepares a framebuffer for usage on a display plane. Generally this
13468 * involves pinning the underlying object and updating the frontbuffer tracking
13469 * bits. Some older platforms need special physical address handling for
13472 * Returns 0 on success, negative error code on failure.
13475 intel_prepare_plane_fb(struct drm_plane *plane,
13476 struct drm_framebuffer *fb,
13477 const struct drm_plane_state *new_state)
13479 struct drm_device *dev = plane->dev;
13480 struct intel_plane *intel_plane = to_intel_plane(plane);
13481 enum pipe pipe = intel_plane->pipe;
13482 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13483 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13484 unsigned frontbuffer_bits = 0;
13490 switch (plane->type) {
13491 case DRM_PLANE_TYPE_PRIMARY:
13492 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13494 case DRM_PLANE_TYPE_CURSOR:
13495 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13497 case DRM_PLANE_TYPE_OVERLAY:
13498 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13502 mutex_lock(&dev->struct_mutex);
13504 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13505 INTEL_INFO(dev)->cursor_needs_physical) {
13506 int align = IS_I830(dev) ? 16 * 1024 : 256;
13507 ret = i915_gem_object_attach_phys(obj, align);
13509 DRM_DEBUG_KMS("failed to attach phys object\n");
13511 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13515 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13517 mutex_unlock(&dev->struct_mutex);
13523 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13524 * @plane: drm plane to clean up for
13525 * @fb: old framebuffer that was on plane
13527 * Cleans up a framebuffer that has just been removed from a plane.
13530 intel_cleanup_plane_fb(struct drm_plane *plane,
13531 struct drm_framebuffer *fb,
13532 const struct drm_plane_state *old_state)
13534 struct drm_device *dev = plane->dev;
13535 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13540 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13541 !INTEL_INFO(dev)->cursor_needs_physical) {
13542 mutex_lock(&dev->struct_mutex);
13543 intel_unpin_fb_obj(fb, old_state);
13544 mutex_unlock(&dev->struct_mutex);
13549 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13552 struct drm_device *dev;
13553 struct drm_i915_private *dev_priv;
13554 int crtc_clock, cdclk;
13556 if (!intel_crtc || !crtc_state)
13557 return DRM_PLANE_HELPER_NO_SCALING;
13559 dev = intel_crtc->base.dev;
13560 dev_priv = dev->dev_private;
13561 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13562 cdclk = dev_priv->display.get_display_clock_speed(dev);
13564 if (!crtc_clock || !cdclk)
13565 return DRM_PLANE_HELPER_NO_SCALING;
13568 * skl max scale is lower of:
13569 * close to 3 but not 3, -1 is for that purpose
13573 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13579 intel_check_primary_plane(struct drm_plane *plane,
13580 struct intel_plane_state *state)
13582 struct drm_device *dev = plane->dev;
13583 struct drm_i915_private *dev_priv = dev->dev_private;
13584 struct drm_crtc *crtc = state->base.crtc;
13585 struct intel_crtc *intel_crtc;
13586 struct intel_crtc_state *crtc_state;
13587 struct drm_framebuffer *fb = state->base.fb;
13588 struct drm_rect *dest = &state->dst;
13589 struct drm_rect *src = &state->src;
13590 const struct drm_rect *clip = &state->clip;
13591 bool can_position = false;
13592 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13593 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13596 crtc = crtc ? crtc : plane->crtc;
13597 intel_crtc = to_intel_crtc(crtc);
13598 crtc_state = state->base.state ?
13599 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13601 if (INTEL_INFO(dev)->gen >= 9) {
13602 /* use scaler when colorkey is not required */
13603 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13605 max_scale = skl_max_scale(intel_crtc, crtc_state);
13607 can_position = true;
13610 ret = drm_plane_helper_check_update(plane, crtc, fb,
13614 can_position, true,
13619 if (intel_crtc->active) {
13620 struct intel_plane_state *old_state =
13621 to_intel_plane_state(plane->state);
13623 intel_crtc->atomic.wait_for_flips = true;
13626 * FBC does not work on some platforms for rotated
13627 * planes, so disable it when rotation is not 0 and
13628 * update it when rotation is set back to 0.
13630 * FIXME: This is redundant with the fbc update done in
13631 * the primary plane enable function except that that
13632 * one is done too late. We eventually need to unify
13635 if (state->visible &&
13636 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13637 dev_priv->fbc.crtc == intel_crtc &&
13638 state->base.rotation != BIT(DRM_ROTATE_0)) {
13639 intel_crtc->atomic.disable_fbc = true;
13642 if (state->visible && !old_state->visible) {
13644 * BDW signals flip done immediately if the plane
13645 * is disabled, even if the plane enable is already
13646 * armed to occur at the next vblank :(
13648 if (IS_BROADWELL(dev))
13649 intel_crtc->atomic.wait_vblank = true;
13651 if (crtc_state && !needs_modeset(&crtc_state->base))
13652 intel_crtc->atomic.post_enable_primary = true;
13655 if (!state->visible && old_state->visible &&
13656 crtc_state && !needs_modeset(&crtc_state->base))
13657 intel_crtc->atomic.pre_disable_primary = true;
13659 intel_crtc->atomic.fb_bits |=
13660 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13662 intel_crtc->atomic.update_fbc = true;
13664 if (intel_wm_need_update(plane, &state->base))
13665 intel_crtc->atomic.update_wm = true;
13668 if (INTEL_INFO(dev)->gen >= 9) {
13669 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13670 to_intel_plane(plane), state, 0);
13679 intel_commit_primary_plane(struct drm_plane *plane,
13680 struct intel_plane_state *state)
13682 struct drm_crtc *crtc = state->base.crtc;
13683 struct drm_framebuffer *fb = state->base.fb;
13684 struct drm_device *dev = plane->dev;
13685 struct drm_i915_private *dev_priv = dev->dev_private;
13686 struct intel_crtc *intel_crtc;
13687 struct drm_rect *src = &state->src;
13689 crtc = crtc ? crtc : plane->crtc;
13690 intel_crtc = to_intel_crtc(crtc);
13693 crtc->x = src->x1 >> 16;
13694 crtc->y = src->y1 >> 16;
13696 if (intel_crtc->active) {
13697 if (state->visible)
13698 /* FIXME: kill this fastboot hack */
13699 intel_update_pipe_size(intel_crtc);
13701 dev_priv->display.update_primary_plane(crtc, plane->fb,
13707 intel_disable_primary_plane(struct drm_plane *plane,
13708 struct drm_crtc *crtc,
13711 struct drm_device *dev = plane->dev;
13712 struct drm_i915_private *dev_priv = dev->dev_private;
13714 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13717 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13719 struct drm_device *dev = crtc->dev;
13720 struct drm_i915_private *dev_priv = dev->dev_private;
13721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13722 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
13723 struct intel_plane *intel_plane;
13724 struct drm_plane *p;
13725 unsigned fb_bits = 0;
13727 /* Track fb's for any planes being disabled */
13728 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13729 intel_plane = to_intel_plane(p);
13731 if (intel_crtc->atomic.disabled_planes &
13732 (1 << drm_plane_index(p))) {
13734 case DRM_PLANE_TYPE_PRIMARY:
13735 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13737 case DRM_PLANE_TYPE_CURSOR:
13738 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13740 case DRM_PLANE_TYPE_OVERLAY:
13741 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13745 mutex_lock(&dev->struct_mutex);
13746 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13747 mutex_unlock(&dev->struct_mutex);
13751 if (intel_crtc->atomic.wait_for_flips)
13752 intel_crtc_wait_for_pending_flips(crtc);
13754 if (intel_crtc->atomic.disable_fbc)
13755 intel_fbc_disable(dev);
13757 if (intel_crtc->atomic.pre_disable_primary)
13758 intel_pre_disable_primary(crtc);
13760 if (intel_crtc->atomic.update_wm)
13761 intel_update_watermarks(crtc);
13763 intel_runtime_pm_get(dev_priv);
13765 /* Perform vblank evasion around commit operation */
13766 if (crtc_state->active && !needs_modeset(crtc_state))
13767 intel_crtc->atomic.evade =
13768 intel_pipe_update_start(intel_crtc,
13769 &intel_crtc->atomic.start_vbl_count);
13772 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13774 struct drm_device *dev = crtc->dev;
13775 struct drm_i915_private *dev_priv = dev->dev_private;
13776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13777 struct drm_plane *p;
13779 if (intel_crtc->atomic.evade)
13780 intel_pipe_update_end(intel_crtc,
13781 intel_crtc->atomic.start_vbl_count);
13783 intel_runtime_pm_put(dev_priv);
13785 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13786 intel_wait_for_vblank(dev, intel_crtc->pipe);
13788 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13790 if (intel_crtc->atomic.update_fbc) {
13791 mutex_lock(&dev->struct_mutex);
13792 intel_fbc_update(dev);
13793 mutex_unlock(&dev->struct_mutex);
13796 if (intel_crtc->atomic.post_enable_primary)
13797 intel_post_enable_primary(crtc);
13799 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13800 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13801 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13804 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13808 * intel_plane_destroy - destroy a plane
13809 * @plane: plane to destroy
13811 * Common destruction function for all types of planes (primary, cursor,
13814 void intel_plane_destroy(struct drm_plane *plane)
13816 struct intel_plane *intel_plane = to_intel_plane(plane);
13817 drm_plane_cleanup(plane);
13818 kfree(intel_plane);
13821 const struct drm_plane_funcs intel_plane_funcs = {
13822 .update_plane = drm_atomic_helper_update_plane,
13823 .disable_plane = drm_atomic_helper_disable_plane,
13824 .destroy = intel_plane_destroy,
13825 .set_property = drm_atomic_helper_plane_set_property,
13826 .atomic_get_property = intel_plane_atomic_get_property,
13827 .atomic_set_property = intel_plane_atomic_set_property,
13828 .atomic_duplicate_state = intel_plane_duplicate_state,
13829 .atomic_destroy_state = intel_plane_destroy_state,
13833 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13836 struct intel_plane *primary;
13837 struct intel_plane_state *state;
13838 const uint32_t *intel_primary_formats;
13841 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13842 if (primary == NULL)
13845 state = intel_create_plane_state(&primary->base);
13850 primary->base.state = &state->base;
13852 primary->can_scale = false;
13853 primary->max_downscale = 1;
13854 if (INTEL_INFO(dev)->gen >= 9) {
13855 primary->can_scale = true;
13856 state->scaler_id = -1;
13858 primary->pipe = pipe;
13859 primary->plane = pipe;
13860 primary->check_plane = intel_check_primary_plane;
13861 primary->commit_plane = intel_commit_primary_plane;
13862 primary->disable_plane = intel_disable_primary_plane;
13863 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13864 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13865 primary->plane = !pipe;
13867 if (INTEL_INFO(dev)->gen >= 9) {
13868 intel_primary_formats = skl_primary_formats;
13869 num_formats = ARRAY_SIZE(skl_primary_formats);
13870 } else if (INTEL_INFO(dev)->gen >= 4) {
13871 intel_primary_formats = i965_primary_formats;
13872 num_formats = ARRAY_SIZE(i965_primary_formats);
13874 intel_primary_formats = i8xx_primary_formats;
13875 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13878 drm_universal_plane_init(dev, &primary->base, 0,
13879 &intel_plane_funcs,
13880 intel_primary_formats, num_formats,
13881 DRM_PLANE_TYPE_PRIMARY);
13883 if (INTEL_INFO(dev)->gen >= 4)
13884 intel_create_rotation_property(dev, primary);
13886 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13888 return &primary->base;
13891 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13893 if (!dev->mode_config.rotation_property) {
13894 unsigned long flags = BIT(DRM_ROTATE_0) |
13895 BIT(DRM_ROTATE_180);
13897 if (INTEL_INFO(dev)->gen >= 9)
13898 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13900 dev->mode_config.rotation_property =
13901 drm_mode_create_rotation_property(dev, flags);
13903 if (dev->mode_config.rotation_property)
13904 drm_object_attach_property(&plane->base.base,
13905 dev->mode_config.rotation_property,
13906 plane->base.state->rotation);
13910 intel_check_cursor_plane(struct drm_plane *plane,
13911 struct intel_plane_state *state)
13913 struct drm_crtc *crtc = state->base.crtc;
13914 struct drm_device *dev = plane->dev;
13915 struct drm_framebuffer *fb = state->base.fb;
13916 struct drm_rect *dest = &state->dst;
13917 struct drm_rect *src = &state->src;
13918 const struct drm_rect *clip = &state->clip;
13919 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13920 struct intel_crtc *intel_crtc;
13924 crtc = crtc ? crtc : plane->crtc;
13925 intel_crtc = to_intel_crtc(crtc);
13927 ret = drm_plane_helper_check_update(plane, crtc, fb,
13929 DRM_PLANE_HELPER_NO_SCALING,
13930 DRM_PLANE_HELPER_NO_SCALING,
13931 true, true, &state->visible);
13936 /* if we want to turn off the cursor ignore width and height */
13940 /* Check for which cursor types we support */
13941 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13942 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13943 state->base.crtc_w, state->base.crtc_h);
13947 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13948 if (obj->base.size < stride * state->base.crtc_h) {
13949 DRM_DEBUG_KMS("buffer is too small\n");
13953 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13954 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13959 if (intel_crtc->active) {
13960 if (plane->state->crtc_w != state->base.crtc_w)
13961 intel_crtc->atomic.update_wm = true;
13963 intel_crtc->atomic.fb_bits |=
13964 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13971 intel_disable_cursor_plane(struct drm_plane *plane,
13972 struct drm_crtc *crtc,
13975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13979 intel_crtc->cursor_bo = NULL;
13980 intel_crtc->cursor_addr = 0;
13983 intel_crtc_update_cursor(crtc, false);
13987 intel_commit_cursor_plane(struct drm_plane *plane,
13988 struct intel_plane_state *state)
13990 struct drm_crtc *crtc = state->base.crtc;
13991 struct drm_device *dev = plane->dev;
13992 struct intel_crtc *intel_crtc;
13993 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13996 crtc = crtc ? crtc : plane->crtc;
13997 intel_crtc = to_intel_crtc(crtc);
13999 plane->fb = state->base.fb;
14000 crtc->cursor_x = state->base.crtc_x;
14001 crtc->cursor_y = state->base.crtc_y;
14003 if (intel_crtc->cursor_bo == obj)
14008 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14009 addr = i915_gem_obj_ggtt_offset(obj);
14011 addr = obj->phys_handle->busaddr;
14013 intel_crtc->cursor_addr = addr;
14014 intel_crtc->cursor_bo = obj;
14017 if (intel_crtc->active)
14018 intel_crtc_update_cursor(crtc, state->visible);
14021 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14024 struct intel_plane *cursor;
14025 struct intel_plane_state *state;
14027 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14028 if (cursor == NULL)
14031 state = intel_create_plane_state(&cursor->base);
14036 cursor->base.state = &state->base;
14038 cursor->can_scale = false;
14039 cursor->max_downscale = 1;
14040 cursor->pipe = pipe;
14041 cursor->plane = pipe;
14042 cursor->check_plane = intel_check_cursor_plane;
14043 cursor->commit_plane = intel_commit_cursor_plane;
14044 cursor->disable_plane = intel_disable_cursor_plane;
14046 drm_universal_plane_init(dev, &cursor->base, 0,
14047 &intel_plane_funcs,
14048 intel_cursor_formats,
14049 ARRAY_SIZE(intel_cursor_formats),
14050 DRM_PLANE_TYPE_CURSOR);
14052 if (INTEL_INFO(dev)->gen >= 4) {
14053 if (!dev->mode_config.rotation_property)
14054 dev->mode_config.rotation_property =
14055 drm_mode_create_rotation_property(dev,
14056 BIT(DRM_ROTATE_0) |
14057 BIT(DRM_ROTATE_180));
14058 if (dev->mode_config.rotation_property)
14059 drm_object_attach_property(&cursor->base.base,
14060 dev->mode_config.rotation_property,
14061 state->base.rotation);
14064 if (INTEL_INFO(dev)->gen >=9)
14065 state->scaler_id = -1;
14067 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14069 return &cursor->base;
14072 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14073 struct intel_crtc_state *crtc_state)
14076 struct intel_scaler *intel_scaler;
14077 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14079 for (i = 0; i < intel_crtc->num_scalers; i++) {
14080 intel_scaler = &scaler_state->scalers[i];
14081 intel_scaler->in_use = 0;
14082 intel_scaler->id = i;
14084 intel_scaler->mode = PS_SCALER_MODE_DYN;
14087 scaler_state->scaler_id = -1;
14090 static void intel_crtc_init(struct drm_device *dev, int pipe)
14092 struct drm_i915_private *dev_priv = dev->dev_private;
14093 struct intel_crtc *intel_crtc;
14094 struct intel_crtc_state *crtc_state = NULL;
14095 struct drm_plane *primary = NULL;
14096 struct drm_plane *cursor = NULL;
14099 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14100 if (intel_crtc == NULL)
14103 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14106 intel_crtc->config = crtc_state;
14107 intel_crtc->base.state = &crtc_state->base;
14108 crtc_state->base.crtc = &intel_crtc->base;
14110 /* initialize shared scalers */
14111 if (INTEL_INFO(dev)->gen >= 9) {
14112 if (pipe == PIPE_C)
14113 intel_crtc->num_scalers = 1;
14115 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14117 skl_init_scalers(dev, intel_crtc, crtc_state);
14120 primary = intel_primary_plane_create(dev, pipe);
14124 cursor = intel_cursor_plane_create(dev, pipe);
14128 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14129 cursor, &intel_crtc_funcs);
14133 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14134 for (i = 0; i < 256; i++) {
14135 intel_crtc->lut_r[i] = i;
14136 intel_crtc->lut_g[i] = i;
14137 intel_crtc->lut_b[i] = i;
14141 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14142 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14144 intel_crtc->pipe = pipe;
14145 intel_crtc->plane = pipe;
14146 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14147 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14148 intel_crtc->plane = !pipe;
14151 intel_crtc->cursor_base = ~0;
14152 intel_crtc->cursor_cntl = ~0;
14153 intel_crtc->cursor_size = ~0;
14155 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14156 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14157 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14158 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14160 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14162 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14167 drm_plane_cleanup(primary);
14169 drm_plane_cleanup(cursor);
14174 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14176 struct drm_encoder *encoder = connector->base.encoder;
14177 struct drm_device *dev = connector->base.dev;
14179 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14181 if (!encoder || WARN_ON(!encoder->crtc))
14182 return INVALID_PIPE;
14184 return to_intel_crtc(encoder->crtc)->pipe;
14187 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14188 struct drm_file *file)
14190 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14191 struct drm_crtc *drmmode_crtc;
14192 struct intel_crtc *crtc;
14194 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14196 if (!drmmode_crtc) {
14197 DRM_ERROR("no such CRTC id\n");
14201 crtc = to_intel_crtc(drmmode_crtc);
14202 pipe_from_crtc_id->pipe = crtc->pipe;
14207 static int intel_encoder_clones(struct intel_encoder *encoder)
14209 struct drm_device *dev = encoder->base.dev;
14210 struct intel_encoder *source_encoder;
14211 int index_mask = 0;
14214 for_each_intel_encoder(dev, source_encoder) {
14215 if (encoders_cloneable(encoder, source_encoder))
14216 index_mask |= (1 << entry);
14224 static bool has_edp_a(struct drm_device *dev)
14226 struct drm_i915_private *dev_priv = dev->dev_private;
14228 if (!IS_MOBILE(dev))
14231 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14234 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14240 static bool intel_crt_present(struct drm_device *dev)
14242 struct drm_i915_private *dev_priv = dev->dev_private;
14244 if (INTEL_INFO(dev)->gen >= 9)
14247 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14250 if (IS_CHERRYVIEW(dev))
14253 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14259 static void intel_setup_outputs(struct drm_device *dev)
14261 struct drm_i915_private *dev_priv = dev->dev_private;
14262 struct intel_encoder *encoder;
14263 bool dpd_is_edp = false;
14265 intel_lvds_init(dev);
14267 if (intel_crt_present(dev))
14268 intel_crt_init(dev);
14270 if (IS_BROXTON(dev)) {
14272 * FIXME: Broxton doesn't support port detection via the
14273 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14274 * detect the ports.
14276 intel_ddi_init(dev, PORT_A);
14277 intel_ddi_init(dev, PORT_B);
14278 intel_ddi_init(dev, PORT_C);
14279 } else if (HAS_DDI(dev)) {
14283 * Haswell uses DDI functions to detect digital outputs.
14284 * On SKL pre-D0 the strap isn't connected, so we assume
14287 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14288 /* WaIgnoreDDIAStrap: skl */
14290 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14291 intel_ddi_init(dev, PORT_A);
14293 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14295 found = I915_READ(SFUSE_STRAP);
14297 if (found & SFUSE_STRAP_DDIB_DETECTED)
14298 intel_ddi_init(dev, PORT_B);
14299 if (found & SFUSE_STRAP_DDIC_DETECTED)
14300 intel_ddi_init(dev, PORT_C);
14301 if (found & SFUSE_STRAP_DDID_DETECTED)
14302 intel_ddi_init(dev, PORT_D);
14303 } else if (HAS_PCH_SPLIT(dev)) {
14305 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14307 if (has_edp_a(dev))
14308 intel_dp_init(dev, DP_A, PORT_A);
14310 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14311 /* PCH SDVOB multiplex with HDMIB */
14312 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14314 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14315 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14316 intel_dp_init(dev, PCH_DP_B, PORT_B);
14319 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14320 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14322 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14323 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14325 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14326 intel_dp_init(dev, PCH_DP_C, PORT_C);
14328 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14329 intel_dp_init(dev, PCH_DP_D, PORT_D);
14330 } else if (IS_VALLEYVIEW(dev)) {
14332 * The DP_DETECTED bit is the latched state of the DDC
14333 * SDA pin at boot. However since eDP doesn't require DDC
14334 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14335 * eDP ports may have been muxed to an alternate function.
14336 * Thus we can't rely on the DP_DETECTED bit alone to detect
14337 * eDP ports. Consult the VBT as well as DP_DETECTED to
14338 * detect eDP ports.
14340 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14341 !intel_dp_is_edp(dev, PORT_B))
14342 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14344 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14345 intel_dp_is_edp(dev, PORT_B))
14346 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14348 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14349 !intel_dp_is_edp(dev, PORT_C))
14350 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14352 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14353 intel_dp_is_edp(dev, PORT_C))
14354 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14356 if (IS_CHERRYVIEW(dev)) {
14357 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14358 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14360 /* eDP not supported on port D, so don't check VBT */
14361 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14362 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14365 intel_dsi_init(dev);
14366 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14367 bool found = false;
14369 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14370 DRM_DEBUG_KMS("probing SDVOB\n");
14371 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14372 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14373 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14374 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14377 if (!found && SUPPORTS_INTEGRATED_DP(dev))
14378 intel_dp_init(dev, DP_B, PORT_B);
14381 /* Before G4X SDVOC doesn't have its own detect register */
14383 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14384 DRM_DEBUG_KMS("probing SDVOC\n");
14385 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14388 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14390 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14391 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14392 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14394 if (SUPPORTS_INTEGRATED_DP(dev))
14395 intel_dp_init(dev, DP_C, PORT_C);
14398 if (SUPPORTS_INTEGRATED_DP(dev) &&
14399 (I915_READ(DP_D) & DP_DETECTED))
14400 intel_dp_init(dev, DP_D, PORT_D);
14401 } else if (IS_GEN2(dev))
14402 intel_dvo_init(dev);
14404 if (SUPPORTS_TV(dev))
14405 intel_tv_init(dev);
14407 intel_psr_init(dev);
14409 for_each_intel_encoder(dev, encoder) {
14410 encoder->base.possible_crtcs = encoder->crtc_mask;
14411 encoder->base.possible_clones =
14412 intel_encoder_clones(encoder);
14415 intel_init_pch_refclk(dev);
14417 drm_helper_move_panel_connectors_to_head(dev);
14420 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14422 struct drm_device *dev = fb->dev;
14423 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14425 drm_framebuffer_cleanup(fb);
14426 mutex_lock(&dev->struct_mutex);
14427 WARN_ON(!intel_fb->obj->framebuffer_references--);
14428 drm_gem_object_unreference(&intel_fb->obj->base);
14429 mutex_unlock(&dev->struct_mutex);
14433 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14434 struct drm_file *file,
14435 unsigned int *handle)
14437 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14438 struct drm_i915_gem_object *obj = intel_fb->obj;
14440 return drm_gem_handle_create(file, &obj->base, handle);
14443 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14444 .destroy = intel_user_framebuffer_destroy,
14445 .create_handle = intel_user_framebuffer_create_handle,
14449 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14450 uint32_t pixel_format)
14452 u32 gen = INTEL_INFO(dev)->gen;
14455 /* "The stride in bytes must not exceed the of the size of 8K
14456 * pixels and 32K bytes."
14458 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14459 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14461 } else if (gen >= 4) {
14462 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14466 } else if (gen >= 3) {
14467 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14472 /* XXX DSPC is limited to 4k tiled */
14477 static int intel_framebuffer_init(struct drm_device *dev,
14478 struct intel_framebuffer *intel_fb,
14479 struct drm_mode_fb_cmd2 *mode_cmd,
14480 struct drm_i915_gem_object *obj)
14482 unsigned int aligned_height;
14484 u32 pitch_limit, stride_alignment;
14486 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14488 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14489 /* Enforce that fb modifier and tiling mode match, but only for
14490 * X-tiled. This is needed for FBC. */
14491 if (!!(obj->tiling_mode == I915_TILING_X) !=
14492 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14493 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14497 if (obj->tiling_mode == I915_TILING_X)
14498 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14499 else if (obj->tiling_mode == I915_TILING_Y) {
14500 DRM_DEBUG("No Y tiling for legacy addfb\n");
14505 /* Passed in modifier sanity checking. */
14506 switch (mode_cmd->modifier[0]) {
14507 case I915_FORMAT_MOD_Y_TILED:
14508 case I915_FORMAT_MOD_Yf_TILED:
14509 if (INTEL_INFO(dev)->gen < 9) {
14510 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14511 mode_cmd->modifier[0]);
14514 case DRM_FORMAT_MOD_NONE:
14515 case I915_FORMAT_MOD_X_TILED:
14518 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14519 mode_cmd->modifier[0]);
14523 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14524 mode_cmd->pixel_format);
14525 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14526 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14527 mode_cmd->pitches[0], stride_alignment);
14531 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14532 mode_cmd->pixel_format);
14533 if (mode_cmd->pitches[0] > pitch_limit) {
14534 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14535 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14536 "tiled" : "linear",
14537 mode_cmd->pitches[0], pitch_limit);
14541 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14542 mode_cmd->pitches[0] != obj->stride) {
14543 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14544 mode_cmd->pitches[0], obj->stride);
14548 /* Reject formats not supported by any plane early. */
14549 switch (mode_cmd->pixel_format) {
14550 case DRM_FORMAT_C8:
14551 case DRM_FORMAT_RGB565:
14552 case DRM_FORMAT_XRGB8888:
14553 case DRM_FORMAT_ARGB8888:
14555 case DRM_FORMAT_XRGB1555:
14556 if (INTEL_INFO(dev)->gen > 3) {
14557 DRM_DEBUG("unsupported pixel format: %s\n",
14558 drm_get_format_name(mode_cmd->pixel_format));
14562 case DRM_FORMAT_ABGR8888:
14563 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14564 DRM_DEBUG("unsupported pixel format: %s\n",
14565 drm_get_format_name(mode_cmd->pixel_format));
14569 case DRM_FORMAT_XBGR8888:
14570 case DRM_FORMAT_XRGB2101010:
14571 case DRM_FORMAT_XBGR2101010:
14572 if (INTEL_INFO(dev)->gen < 4) {
14573 DRM_DEBUG("unsupported pixel format: %s\n",
14574 drm_get_format_name(mode_cmd->pixel_format));
14578 case DRM_FORMAT_ABGR2101010:
14579 if (!IS_VALLEYVIEW(dev)) {
14580 DRM_DEBUG("unsupported pixel format: %s\n",
14581 drm_get_format_name(mode_cmd->pixel_format));
14585 case DRM_FORMAT_YUYV:
14586 case DRM_FORMAT_UYVY:
14587 case DRM_FORMAT_YVYU:
14588 case DRM_FORMAT_VYUY:
14589 if (INTEL_INFO(dev)->gen < 5) {
14590 DRM_DEBUG("unsupported pixel format: %s\n",
14591 drm_get_format_name(mode_cmd->pixel_format));
14596 DRM_DEBUG("unsupported pixel format: %s\n",
14597 drm_get_format_name(mode_cmd->pixel_format));
14601 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14602 if (mode_cmd->offsets[0] != 0)
14605 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14606 mode_cmd->pixel_format,
14607 mode_cmd->modifier[0]);
14608 /* FIXME drm helper for size checks (especially planar formats)? */
14609 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14612 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14613 intel_fb->obj = obj;
14614 intel_fb->obj->framebuffer_references++;
14616 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14618 DRM_ERROR("framebuffer init failed %d\n", ret);
14625 static struct drm_framebuffer *
14626 intel_user_framebuffer_create(struct drm_device *dev,
14627 struct drm_file *filp,
14628 struct drm_mode_fb_cmd2 *mode_cmd)
14630 struct drm_i915_gem_object *obj;
14632 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14633 mode_cmd->handles[0]));
14634 if (&obj->base == NULL)
14635 return ERR_PTR(-ENOENT);
14637 return intel_framebuffer_create(dev, mode_cmd, obj);
14640 #ifndef CONFIG_DRM_I915_FBDEV
14641 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14646 static const struct drm_mode_config_funcs intel_mode_funcs = {
14647 .fb_create = intel_user_framebuffer_create,
14648 .output_poll_changed = intel_fbdev_output_poll_changed,
14649 .atomic_check = intel_atomic_check,
14650 .atomic_commit = intel_atomic_commit,
14651 .atomic_state_alloc = intel_atomic_state_alloc,
14652 .atomic_state_clear = intel_atomic_state_clear,
14655 /* Set up chip specific display functions */
14656 static void intel_init_display(struct drm_device *dev)
14658 struct drm_i915_private *dev_priv = dev->dev_private;
14660 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14661 dev_priv->display.find_dpll = g4x_find_best_dpll;
14662 else if (IS_CHERRYVIEW(dev))
14663 dev_priv->display.find_dpll = chv_find_best_dpll;
14664 else if (IS_VALLEYVIEW(dev))
14665 dev_priv->display.find_dpll = vlv_find_best_dpll;
14666 else if (IS_PINEVIEW(dev))
14667 dev_priv->display.find_dpll = pnv_find_best_dpll;
14669 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14671 if (INTEL_INFO(dev)->gen >= 9) {
14672 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14673 dev_priv->display.get_initial_plane_config =
14674 skylake_get_initial_plane_config;
14675 dev_priv->display.crtc_compute_clock =
14676 haswell_crtc_compute_clock;
14677 dev_priv->display.crtc_enable = haswell_crtc_enable;
14678 dev_priv->display.crtc_disable = haswell_crtc_disable;
14679 dev_priv->display.update_primary_plane =
14680 skylake_update_primary_plane;
14681 } else if (HAS_DDI(dev)) {
14682 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14683 dev_priv->display.get_initial_plane_config =
14684 ironlake_get_initial_plane_config;
14685 dev_priv->display.crtc_compute_clock =
14686 haswell_crtc_compute_clock;
14687 dev_priv->display.crtc_enable = haswell_crtc_enable;
14688 dev_priv->display.crtc_disable = haswell_crtc_disable;
14689 dev_priv->display.update_primary_plane =
14690 ironlake_update_primary_plane;
14691 } else if (HAS_PCH_SPLIT(dev)) {
14692 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14693 dev_priv->display.get_initial_plane_config =
14694 ironlake_get_initial_plane_config;
14695 dev_priv->display.crtc_compute_clock =
14696 ironlake_crtc_compute_clock;
14697 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14698 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14699 dev_priv->display.update_primary_plane =
14700 ironlake_update_primary_plane;
14701 } else if (IS_VALLEYVIEW(dev)) {
14702 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14703 dev_priv->display.get_initial_plane_config =
14704 i9xx_get_initial_plane_config;
14705 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14706 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14707 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14708 dev_priv->display.update_primary_plane =
14709 i9xx_update_primary_plane;
14711 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14712 dev_priv->display.get_initial_plane_config =
14713 i9xx_get_initial_plane_config;
14714 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14715 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14716 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14717 dev_priv->display.update_primary_plane =
14718 i9xx_update_primary_plane;
14721 /* Returns the core display clock speed */
14722 if (IS_SKYLAKE(dev))
14723 dev_priv->display.get_display_clock_speed =
14724 skylake_get_display_clock_speed;
14725 else if (IS_BROADWELL(dev))
14726 dev_priv->display.get_display_clock_speed =
14727 broadwell_get_display_clock_speed;
14728 else if (IS_HASWELL(dev))
14729 dev_priv->display.get_display_clock_speed =
14730 haswell_get_display_clock_speed;
14731 else if (IS_VALLEYVIEW(dev))
14732 dev_priv->display.get_display_clock_speed =
14733 valleyview_get_display_clock_speed;
14734 else if (IS_GEN5(dev))
14735 dev_priv->display.get_display_clock_speed =
14736 ilk_get_display_clock_speed;
14737 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14738 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14739 dev_priv->display.get_display_clock_speed =
14740 i945_get_display_clock_speed;
14741 else if (IS_GM45(dev))
14742 dev_priv->display.get_display_clock_speed =
14743 gm45_get_display_clock_speed;
14744 else if (IS_CRESTLINE(dev))
14745 dev_priv->display.get_display_clock_speed =
14746 i965gm_get_display_clock_speed;
14747 else if (IS_PINEVIEW(dev))
14748 dev_priv->display.get_display_clock_speed =
14749 pnv_get_display_clock_speed;
14750 else if (IS_G33(dev) || IS_G4X(dev))
14751 dev_priv->display.get_display_clock_speed =
14752 g33_get_display_clock_speed;
14753 else if (IS_I915G(dev))
14754 dev_priv->display.get_display_clock_speed =
14755 i915_get_display_clock_speed;
14756 else if (IS_I945GM(dev) || IS_845G(dev))
14757 dev_priv->display.get_display_clock_speed =
14758 i9xx_misc_get_display_clock_speed;
14759 else if (IS_PINEVIEW(dev))
14760 dev_priv->display.get_display_clock_speed =
14761 pnv_get_display_clock_speed;
14762 else if (IS_I915GM(dev))
14763 dev_priv->display.get_display_clock_speed =
14764 i915gm_get_display_clock_speed;
14765 else if (IS_I865G(dev))
14766 dev_priv->display.get_display_clock_speed =
14767 i865_get_display_clock_speed;
14768 else if (IS_I85X(dev))
14769 dev_priv->display.get_display_clock_speed =
14770 i85x_get_display_clock_speed;
14772 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14773 dev_priv->display.get_display_clock_speed =
14774 i830_get_display_clock_speed;
14777 if (IS_GEN5(dev)) {
14778 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14779 } else if (IS_GEN6(dev)) {
14780 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14781 } else if (IS_IVYBRIDGE(dev)) {
14782 /* FIXME: detect B0+ stepping and use auto training */
14783 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14784 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14785 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14786 if (IS_BROADWELL(dev))
14787 dev_priv->display.modeset_global_resources =
14788 broadwell_modeset_global_resources;
14789 } else if (IS_VALLEYVIEW(dev)) {
14790 dev_priv->display.modeset_global_resources =
14791 valleyview_modeset_global_resources;
14792 } else if (IS_BROXTON(dev)) {
14793 dev_priv->display.modeset_global_resources =
14794 broxton_modeset_global_resources;
14797 switch (INTEL_INFO(dev)->gen) {
14799 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14803 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14808 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14812 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14815 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14816 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14819 /* Drop through - unsupported since execlist only. */
14821 /* Default just returns -ENODEV to indicate unsupported */
14822 dev_priv->display.queue_flip = intel_default_queue_flip;
14825 intel_panel_init_backlight_funcs(dev);
14827 mutex_init(&dev_priv->pps_mutex);
14831 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14832 * resume, or other times. This quirk makes sure that's the case for
14833 * affected systems.
14835 static void quirk_pipea_force(struct drm_device *dev)
14837 struct drm_i915_private *dev_priv = dev->dev_private;
14839 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14840 DRM_INFO("applying pipe a force quirk\n");
14843 static void quirk_pipeb_force(struct drm_device *dev)
14845 struct drm_i915_private *dev_priv = dev->dev_private;
14847 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14848 DRM_INFO("applying pipe b force quirk\n");
14852 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14854 static void quirk_ssc_force_disable(struct drm_device *dev)
14856 struct drm_i915_private *dev_priv = dev->dev_private;
14857 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14858 DRM_INFO("applying lvds SSC disable quirk\n");
14862 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14865 static void quirk_invert_brightness(struct drm_device *dev)
14867 struct drm_i915_private *dev_priv = dev->dev_private;
14868 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14869 DRM_INFO("applying inverted panel brightness quirk\n");
14872 /* Some VBT's incorrectly indicate no backlight is present */
14873 static void quirk_backlight_present(struct drm_device *dev)
14875 struct drm_i915_private *dev_priv = dev->dev_private;
14876 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14877 DRM_INFO("applying backlight present quirk\n");
14880 struct intel_quirk {
14882 int subsystem_vendor;
14883 int subsystem_device;
14884 void (*hook)(struct drm_device *dev);
14887 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14888 struct intel_dmi_quirk {
14889 void (*hook)(struct drm_device *dev);
14890 const struct dmi_system_id (*dmi_id_list)[];
14893 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14895 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14899 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14901 .dmi_id_list = &(const struct dmi_system_id[]) {
14903 .callback = intel_dmi_reverse_brightness,
14904 .ident = "NCR Corporation",
14905 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14906 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14909 { } /* terminating entry */
14911 .hook = quirk_invert_brightness,
14915 static struct intel_quirk intel_quirks[] = {
14916 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14917 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14919 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14920 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14922 /* 830 needs to leave pipe A & dpll A up */
14923 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14925 /* 830 needs to leave pipe B & dpll B up */
14926 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14928 /* Lenovo U160 cannot use SSC on LVDS */
14929 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14931 /* Sony Vaio Y cannot use SSC on LVDS */
14932 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14934 /* Acer Aspire 5734Z must invert backlight brightness */
14935 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14937 /* Acer/eMachines G725 */
14938 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14940 /* Acer/eMachines e725 */
14941 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14943 /* Acer/Packard Bell NCL20 */
14944 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14946 /* Acer Aspire 4736Z */
14947 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14949 /* Acer Aspire 5336 */
14950 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14952 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14953 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14955 /* Acer C720 Chromebook (Core i3 4005U) */
14956 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14958 /* Apple Macbook 2,1 (Core 2 T7400) */
14959 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14961 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14962 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14964 /* HP Chromebook 14 (Celeron 2955U) */
14965 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14967 /* Dell Chromebook 11 */
14968 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14971 static void intel_init_quirks(struct drm_device *dev)
14973 struct pci_dev *d = dev->pdev;
14976 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14977 struct intel_quirk *q = &intel_quirks[i];
14979 if (d->device == q->device &&
14980 (d->subsystem_vendor == q->subsystem_vendor ||
14981 q->subsystem_vendor == PCI_ANY_ID) &&
14982 (d->subsystem_device == q->subsystem_device ||
14983 q->subsystem_device == PCI_ANY_ID))
14986 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14987 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14988 intel_dmi_quirks[i].hook(dev);
14992 /* Disable the VGA plane that we never use */
14993 static void i915_disable_vga(struct drm_device *dev)
14995 struct drm_i915_private *dev_priv = dev->dev_private;
14997 u32 vga_reg = i915_vgacntrl_reg(dev);
14999 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15000 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15001 outb(SR01, VGA_SR_INDEX);
15002 sr1 = inb(VGA_SR_DATA);
15003 outb(sr1 | 1<<5, VGA_SR_DATA);
15004 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15007 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15008 POSTING_READ(vga_reg);
15011 void intel_modeset_init_hw(struct drm_device *dev)
15013 intel_update_cdclk(dev);
15014 intel_prepare_ddi(dev);
15015 intel_init_clock_gating(dev);
15016 intel_enable_gt_powersave(dev);
15019 void intel_modeset_init(struct drm_device *dev)
15021 struct drm_i915_private *dev_priv = dev->dev_private;
15024 struct intel_crtc *crtc;
15026 drm_mode_config_init(dev);
15028 dev->mode_config.min_width = 0;
15029 dev->mode_config.min_height = 0;
15031 dev->mode_config.preferred_depth = 24;
15032 dev->mode_config.prefer_shadow = 1;
15034 dev->mode_config.allow_fb_modifiers = true;
15036 dev->mode_config.funcs = &intel_mode_funcs;
15038 intel_init_quirks(dev);
15040 intel_init_pm(dev);
15042 if (INTEL_INFO(dev)->num_pipes == 0)
15045 intel_init_display(dev);
15046 intel_init_audio(dev);
15048 if (IS_GEN2(dev)) {
15049 dev->mode_config.max_width = 2048;
15050 dev->mode_config.max_height = 2048;
15051 } else if (IS_GEN3(dev)) {
15052 dev->mode_config.max_width = 4096;
15053 dev->mode_config.max_height = 4096;
15055 dev->mode_config.max_width = 8192;
15056 dev->mode_config.max_height = 8192;
15059 if (IS_845G(dev) || IS_I865G(dev)) {
15060 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15061 dev->mode_config.cursor_height = 1023;
15062 } else if (IS_GEN2(dev)) {
15063 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15064 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15066 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15067 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15070 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15072 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15073 INTEL_INFO(dev)->num_pipes,
15074 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15076 for_each_pipe(dev_priv, pipe) {
15077 intel_crtc_init(dev, pipe);
15078 for_each_sprite(dev_priv, pipe, sprite) {
15079 ret = intel_plane_init(dev, pipe, sprite);
15081 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15082 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15086 intel_init_dpio(dev);
15088 intel_shared_dpll_init(dev);
15090 /* Just disable it once at startup */
15091 i915_disable_vga(dev);
15092 intel_setup_outputs(dev);
15094 /* Just in case the BIOS is doing something questionable. */
15095 intel_fbc_disable(dev);
15097 drm_modeset_lock_all(dev);
15098 intel_modeset_setup_hw_state(dev, false);
15099 drm_modeset_unlock_all(dev);
15101 for_each_intel_crtc(dev, crtc) {
15106 * Note that reserving the BIOS fb up front prevents us
15107 * from stuffing other stolen allocations like the ring
15108 * on top. This prevents some ugliness at boot time, and
15109 * can even allow for smooth boot transitions if the BIOS
15110 * fb is large enough for the active pipe configuration.
15112 if (dev_priv->display.get_initial_plane_config) {
15113 dev_priv->display.get_initial_plane_config(crtc,
15114 &crtc->plane_config);
15116 * If the fb is shared between multiple heads, we'll
15117 * just get the first one.
15119 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15124 static void intel_enable_pipe_a(struct drm_device *dev)
15126 struct intel_connector *connector;
15127 struct drm_connector *crt = NULL;
15128 struct intel_load_detect_pipe load_detect_temp;
15129 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15131 /* We can't just switch on the pipe A, we need to set things up with a
15132 * proper mode and output configuration. As a gross hack, enable pipe A
15133 * by enabling the load detect pipe once. */
15134 for_each_intel_connector(dev, connector) {
15135 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15136 crt = &connector->base;
15144 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15145 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15149 intel_check_plane_mapping(struct intel_crtc *crtc)
15151 struct drm_device *dev = crtc->base.dev;
15152 struct drm_i915_private *dev_priv = dev->dev_private;
15155 if (INTEL_INFO(dev)->num_pipes == 1)
15158 reg = DSPCNTR(!crtc->plane);
15159 val = I915_READ(reg);
15161 if ((val & DISPLAY_PLANE_ENABLE) &&
15162 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15168 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15170 struct drm_device *dev = crtc->base.dev;
15171 struct drm_i915_private *dev_priv = dev->dev_private;
15172 struct intel_encoder *encoder;
15176 /* Clear any frame start delays used for debugging left by the BIOS */
15177 reg = PIPECONF(crtc->config->cpu_transcoder);
15178 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15180 /* restore vblank interrupts to correct state */
15181 drm_crtc_vblank_reset(&crtc->base);
15182 if (crtc->active) {
15183 update_scanline_offset(crtc);
15184 drm_crtc_vblank_on(&crtc->base);
15187 /* We need to sanitize the plane -> pipe mapping first because this will
15188 * disable the crtc (and hence change the state) if it is wrong. Note
15189 * that gen4+ has a fixed plane -> pipe mapping. */
15190 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15193 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15194 crtc->base.base.id);
15196 /* Pipe has the wrong plane attached and the plane is active.
15197 * Temporarily change the plane mapping and disable everything
15199 plane = crtc->plane;
15200 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15201 crtc->plane = !plane;
15202 intel_crtc_disable_noatomic(&crtc->base);
15203 crtc->plane = plane;
15206 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15207 crtc->pipe == PIPE_A && !crtc->active) {
15208 /* BIOS forgot to enable pipe A, this mostly happens after
15209 * resume. Force-enable the pipe to fix this, the update_dpms
15210 * call below we restore the pipe to the right state, but leave
15211 * the required bits on. */
15212 intel_enable_pipe_a(dev);
15215 /* Adjust the state of the output pipe according to whether we
15216 * have active connectors/encoders. */
15218 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15219 enable |= encoder->connectors_active;
15222 intel_crtc_disable_noatomic(&crtc->base);
15224 if (crtc->active != crtc->base.state->active) {
15226 /* This can happen either due to bugs in the get_hw_state
15227 * functions or because of calls to intel_crtc_disable_noatomic,
15228 * or because the pipe is force-enabled due to the
15230 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15231 crtc->base.base.id,
15232 crtc->base.state->enable ? "enabled" : "disabled",
15233 crtc->active ? "enabled" : "disabled");
15235 crtc->base.state->enable = crtc->active;
15236 crtc->base.state->active = crtc->active;
15237 crtc->base.enabled = crtc->active;
15239 /* Because we only establish the connector -> encoder ->
15240 * crtc links if something is active, this means the
15241 * crtc is now deactivated. Break the links. connector
15242 * -> encoder links are only establish when things are
15243 * actually up, hence no need to break them. */
15244 WARN_ON(crtc->active);
15246 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15247 WARN_ON(encoder->connectors_active);
15248 encoder->base.crtc = NULL;
15252 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15254 * We start out with underrun reporting disabled to avoid races.
15255 * For correct bookkeeping mark this on active crtcs.
15257 * Also on gmch platforms we dont have any hardware bits to
15258 * disable the underrun reporting. Which means we need to start
15259 * out with underrun reporting disabled also on inactive pipes,
15260 * since otherwise we'll complain about the garbage we read when
15261 * e.g. coming up after runtime pm.
15263 * No protection against concurrent access is required - at
15264 * worst a fifo underrun happens which also sets this to false.
15266 crtc->cpu_fifo_underrun_disabled = true;
15267 crtc->pch_fifo_underrun_disabled = true;
15271 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15273 struct intel_connector *connector;
15274 struct drm_device *dev = encoder->base.dev;
15276 /* We need to check both for a crtc link (meaning that the
15277 * encoder is active and trying to read from a pipe) and the
15278 * pipe itself being active. */
15279 bool has_active_crtc = encoder->base.crtc &&
15280 to_intel_crtc(encoder->base.crtc)->active;
15282 if (encoder->connectors_active && !has_active_crtc) {
15283 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15284 encoder->base.base.id,
15285 encoder->base.name);
15287 /* Connector is active, but has no active pipe. This is
15288 * fallout from our resume register restoring. Disable
15289 * the encoder manually again. */
15290 if (encoder->base.crtc) {
15291 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15292 encoder->base.base.id,
15293 encoder->base.name);
15294 encoder->disable(encoder);
15295 if (encoder->post_disable)
15296 encoder->post_disable(encoder);
15298 encoder->base.crtc = NULL;
15299 encoder->connectors_active = false;
15301 /* Inconsistent output/port/pipe state happens presumably due to
15302 * a bug in one of the get_hw_state functions. Or someplace else
15303 * in our code, like the register restore mess on resume. Clamp
15304 * things to off as a safer default. */
15305 for_each_intel_connector(dev, connector) {
15306 if (connector->encoder != encoder)
15308 connector->base.dpms = DRM_MODE_DPMS_OFF;
15309 connector->base.encoder = NULL;
15312 /* Enabled encoders without active connectors will be fixed in
15313 * the crtc fixup. */
15316 void i915_redisable_vga_power_on(struct drm_device *dev)
15318 struct drm_i915_private *dev_priv = dev->dev_private;
15319 u32 vga_reg = i915_vgacntrl_reg(dev);
15321 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15322 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15323 i915_disable_vga(dev);
15327 void i915_redisable_vga(struct drm_device *dev)
15329 struct drm_i915_private *dev_priv = dev->dev_private;
15331 /* This function can be called both from intel_modeset_setup_hw_state or
15332 * at a very early point in our resume sequence, where the power well
15333 * structures are not yet restored. Since this function is at a very
15334 * paranoid "someone might have enabled VGA while we were not looking"
15335 * level, just check if the power well is enabled instead of trying to
15336 * follow the "don't touch the power well if we don't need it" policy
15337 * the rest of the driver uses. */
15338 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15341 i915_redisable_vga_power_on(dev);
15344 static bool primary_get_hw_state(struct intel_crtc *crtc)
15346 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15351 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15354 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15356 struct drm_i915_private *dev_priv = dev->dev_private;
15358 struct intel_crtc *crtc;
15359 struct intel_encoder *encoder;
15360 struct intel_connector *connector;
15363 for_each_intel_crtc(dev, crtc) {
15364 struct drm_plane *primary = crtc->base.primary;
15365 struct intel_plane_state *plane_state;
15367 memset(crtc->config, 0, sizeof(*crtc->config));
15368 crtc->config->base.crtc = &crtc->base;
15370 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15372 crtc->active = dev_priv->display.get_pipe_config(crtc,
15375 crtc->base.state->enable = crtc->active;
15376 crtc->base.state->active = crtc->active;
15377 crtc->base.enabled = crtc->active;
15378 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15380 plane_state = to_intel_plane_state(primary->state);
15381 plane_state->visible = primary_get_hw_state(crtc);
15383 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15384 crtc->base.base.id,
15385 crtc->active ? "enabled" : "disabled");
15388 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15389 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15391 pll->on = pll->get_hw_state(dev_priv, pll,
15392 &pll->config.hw_state);
15394 pll->config.crtc_mask = 0;
15395 for_each_intel_crtc(dev, crtc) {
15396 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15398 pll->config.crtc_mask |= 1 << crtc->pipe;
15402 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15403 pll->name, pll->config.crtc_mask, pll->on);
15405 if (pll->config.crtc_mask)
15406 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15409 for_each_intel_encoder(dev, encoder) {
15412 if (encoder->get_hw_state(encoder, &pipe)) {
15413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15414 encoder->base.crtc = &crtc->base;
15415 encoder->get_config(encoder, crtc->config);
15417 encoder->base.crtc = NULL;
15420 encoder->connectors_active = false;
15421 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15422 encoder->base.base.id,
15423 encoder->base.name,
15424 encoder->base.crtc ? "enabled" : "disabled",
15428 for_each_intel_connector(dev, connector) {
15429 if (connector->get_hw_state(connector)) {
15430 connector->base.dpms = DRM_MODE_DPMS_ON;
15431 connector->encoder->connectors_active = true;
15432 connector->base.encoder = &connector->encoder->base;
15434 connector->base.dpms = DRM_MODE_DPMS_OFF;
15435 connector->base.encoder = NULL;
15437 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15438 connector->base.base.id,
15439 connector->base.name,
15440 connector->base.encoder ? "enabled" : "disabled");
15444 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15445 * and i915 state tracking structures. */
15446 void intel_modeset_setup_hw_state(struct drm_device *dev,
15447 bool force_restore)
15449 struct drm_i915_private *dev_priv = dev->dev_private;
15451 struct intel_crtc *crtc;
15452 struct intel_encoder *encoder;
15455 intel_modeset_readout_hw_state(dev);
15458 * Now that we have the config, copy it to each CRTC struct
15459 * Note that this could go away if we move to using crtc_config
15460 * checking everywhere.
15462 for_each_intel_crtc(dev, crtc) {
15463 if (crtc->active && i915.fastboot) {
15464 intel_mode_from_pipe_config(&crtc->base.mode,
15466 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15467 crtc->base.base.id);
15468 drm_mode_debug_printmodeline(&crtc->base.mode);
15472 /* HW state is read out, now we need to sanitize this mess. */
15473 for_each_intel_encoder(dev, encoder) {
15474 intel_sanitize_encoder(encoder);
15477 for_each_pipe(dev_priv, pipe) {
15478 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15479 intel_sanitize_crtc(crtc);
15480 intel_dump_pipe_config(crtc, crtc->config,
15481 "[setup_hw_state]");
15484 intel_modeset_update_connector_atomic_state(dev);
15486 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15487 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15489 if (!pll->on || pll->active)
15492 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15494 pll->disable(dev_priv, pll);
15499 skl_wm_get_hw_state(dev);
15500 else if (HAS_PCH_SPLIT(dev))
15501 ilk_wm_get_hw_state(dev);
15503 if (force_restore) {
15504 i915_redisable_vga(dev);
15507 * We need to use raw interfaces for restoring state to avoid
15508 * checking (bogus) intermediate states.
15510 for_each_pipe(dev_priv, pipe) {
15511 struct drm_crtc *crtc =
15512 dev_priv->pipe_to_crtc_mapping[pipe];
15514 intel_crtc_restore_mode(crtc);
15517 intel_modeset_update_staged_output_state(dev);
15520 intel_modeset_check_state(dev);
15523 void intel_modeset_gem_init(struct drm_device *dev)
15525 struct drm_i915_private *dev_priv = dev->dev_private;
15526 struct drm_crtc *c;
15527 struct drm_i915_gem_object *obj;
15530 mutex_lock(&dev->struct_mutex);
15531 intel_init_gt_powersave(dev);
15532 mutex_unlock(&dev->struct_mutex);
15535 * There may be no VBT; and if the BIOS enabled SSC we can
15536 * just keep using it to avoid unnecessary flicker. Whereas if the
15537 * BIOS isn't using it, don't assume it will work even if the VBT
15538 * indicates as much.
15540 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15541 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15544 intel_modeset_init_hw(dev);
15546 intel_setup_overlay(dev);
15549 * Make sure any fbs we allocated at startup are properly
15550 * pinned & fenced. When we do the allocation it's too early
15553 for_each_crtc(dev, c) {
15554 obj = intel_fb_obj(c->primary->fb);
15558 mutex_lock(&dev->struct_mutex);
15559 ret = intel_pin_and_fence_fb_obj(c->primary,
15563 mutex_unlock(&dev->struct_mutex);
15565 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15566 to_intel_crtc(c)->pipe);
15567 drm_framebuffer_unreference(c->primary->fb);
15568 c->primary->fb = NULL;
15569 c->primary->crtc = c->primary->state->crtc = NULL;
15570 update_state_fb(c->primary);
15571 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15575 intel_backlight_register(dev);
15578 void intel_connector_unregister(struct intel_connector *intel_connector)
15580 struct drm_connector *connector = &intel_connector->base;
15582 intel_panel_destroy_backlight(connector);
15583 drm_connector_unregister(connector);
15586 void intel_modeset_cleanup(struct drm_device *dev)
15588 struct drm_i915_private *dev_priv = dev->dev_private;
15589 struct drm_connector *connector;
15591 intel_disable_gt_powersave(dev);
15593 intel_backlight_unregister(dev);
15596 * Interrupts and polling as the first thing to avoid creating havoc.
15597 * Too much stuff here (turning of connectors, ...) would
15598 * experience fancy races otherwise.
15600 intel_irq_uninstall(dev_priv);
15603 * Due to the hpd irq storm handling the hotplug work can re-arm the
15604 * poll handlers. Hence disable polling after hpd handling is shut down.
15606 drm_kms_helper_poll_fini(dev);
15608 mutex_lock(&dev->struct_mutex);
15610 intel_unregister_dsm_handler();
15612 intel_fbc_disable(dev);
15614 mutex_unlock(&dev->struct_mutex);
15616 /* flush any delayed tasks or pending work */
15617 flush_scheduled_work();
15619 /* destroy the backlight and sysfs files before encoders/connectors */
15620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15621 struct intel_connector *intel_connector;
15623 intel_connector = to_intel_connector(connector);
15624 intel_connector->unregister(intel_connector);
15627 drm_mode_config_cleanup(dev);
15629 intel_cleanup_overlay(dev);
15631 mutex_lock(&dev->struct_mutex);
15632 intel_cleanup_gt_powersave(dev);
15633 mutex_unlock(&dev->struct_mutex);
15637 * Return which encoder is currently attached for connector.
15639 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15641 return &intel_attached_encoder(connector)->base;
15644 void intel_connector_attach_encoder(struct intel_connector *connector,
15645 struct intel_encoder *encoder)
15647 connector->encoder = encoder;
15648 drm_mode_connector_attach_encoder(&connector->base,
15653 * set vga decode state - true == enable VGA decode
15655 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15657 struct drm_i915_private *dev_priv = dev->dev_private;
15658 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15661 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15662 DRM_ERROR("failed to read control word\n");
15666 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15670 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15672 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15674 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15675 DRM_ERROR("failed to write control word\n");
15682 struct intel_display_error_state {
15684 u32 power_well_driver;
15686 int num_transcoders;
15688 struct intel_cursor_error_state {
15693 } cursor[I915_MAX_PIPES];
15695 struct intel_pipe_error_state {
15696 bool power_domain_on;
15699 } pipe[I915_MAX_PIPES];
15701 struct intel_plane_error_state {
15709 } plane[I915_MAX_PIPES];
15711 struct intel_transcoder_error_state {
15712 bool power_domain_on;
15713 enum transcoder cpu_transcoder;
15726 struct intel_display_error_state *
15727 intel_display_capture_error_state(struct drm_device *dev)
15729 struct drm_i915_private *dev_priv = dev->dev_private;
15730 struct intel_display_error_state *error;
15731 int transcoders[] = {
15739 if (INTEL_INFO(dev)->num_pipes == 0)
15742 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15746 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15747 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15749 for_each_pipe(dev_priv, i) {
15750 error->pipe[i].power_domain_on =
15751 __intel_display_power_is_enabled(dev_priv,
15752 POWER_DOMAIN_PIPE(i));
15753 if (!error->pipe[i].power_domain_on)
15756 error->cursor[i].control = I915_READ(CURCNTR(i));
15757 error->cursor[i].position = I915_READ(CURPOS(i));
15758 error->cursor[i].base = I915_READ(CURBASE(i));
15760 error->plane[i].control = I915_READ(DSPCNTR(i));
15761 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15762 if (INTEL_INFO(dev)->gen <= 3) {
15763 error->plane[i].size = I915_READ(DSPSIZE(i));
15764 error->plane[i].pos = I915_READ(DSPPOS(i));
15766 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15767 error->plane[i].addr = I915_READ(DSPADDR(i));
15768 if (INTEL_INFO(dev)->gen >= 4) {
15769 error->plane[i].surface = I915_READ(DSPSURF(i));
15770 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15773 error->pipe[i].source = I915_READ(PIPESRC(i));
15775 if (HAS_GMCH_DISPLAY(dev))
15776 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15779 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15780 if (HAS_DDI(dev_priv->dev))
15781 error->num_transcoders++; /* Account for eDP. */
15783 for (i = 0; i < error->num_transcoders; i++) {
15784 enum transcoder cpu_transcoder = transcoders[i];
15786 error->transcoder[i].power_domain_on =
15787 __intel_display_power_is_enabled(dev_priv,
15788 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15789 if (!error->transcoder[i].power_domain_on)
15792 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15794 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15795 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15796 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15797 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15798 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15799 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15800 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15806 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15809 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15810 struct drm_device *dev,
15811 struct intel_display_error_state *error)
15813 struct drm_i915_private *dev_priv = dev->dev_private;
15819 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15820 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15821 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15822 error->power_well_driver);
15823 for_each_pipe(dev_priv, i) {
15824 err_printf(m, "Pipe [%d]:\n", i);
15825 err_printf(m, " Power: %s\n",
15826 error->pipe[i].power_domain_on ? "on" : "off");
15827 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15828 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15830 err_printf(m, "Plane [%d]:\n", i);
15831 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15832 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15833 if (INTEL_INFO(dev)->gen <= 3) {
15834 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15835 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15837 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15838 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15839 if (INTEL_INFO(dev)->gen >= 4) {
15840 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15841 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15844 err_printf(m, "Cursor [%d]:\n", i);
15845 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15846 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15847 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15850 for (i = 0; i < error->num_transcoders; i++) {
15851 err_printf(m, "CPU transcoder: %c\n",
15852 transcoder_name(error->transcoder[i].cpu_transcoder));
15853 err_printf(m, " Power: %s\n",
15854 error->transcoder[i].power_domain_on ? "on" : "off");
15855 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15856 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15857 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15858 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15859 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15860 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15861 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15865 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15867 struct intel_crtc *crtc;
15869 for_each_intel_crtc(dev, crtc) {
15870 struct intel_unpin_work *work;
15872 spin_lock_irq(&dev->event_lock);
15874 work = crtc->unpin_work;
15876 if (work && work->event &&
15877 work->event->base.file_priv == file) {
15878 kfree(work->event);
15879 work->event = NULL;
15882 spin_unlock_irq(&dev->event_lock);