drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
 113 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
 114
 115 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 116 {
 117         if (!connector->mst_port)
 118                 return connector->encoder;
 119         else
 120                 return &connector->mst_port->mst_encoders[pipe]->base;
 121 }
 122
 123 typedef struct {
 124         int     min, max;
 125 } intel_range_t;
 126
 127 typedef struct {
 128         int     dot_limit;
 129         int     p2_slow, p2_fast;
 130 } intel_p2_t;
 131
 132 typedef struct intel_limit intel_limit_t;
 133 struct intel_limit {
 134         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 135         intel_p2_t          p2;
 136 };
 137
 138 int
 139 intel_pch_rawclk(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142
 143         WARN_ON(!HAS_PCH_SPLIT(dev));
 144
 145         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 146 }
 147
 148 static inline u32 /* units of 100MHz */
 149 intel_fdi_link_freq(struct drm_device *dev)
 150 {
 151         if (IS_GEN5(dev)) {
 152                 struct drm_i915_private *dev_priv = dev->dev_private;
 153                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 154         } else
 155                 return 27;
 156 }
 157
 158 static const intel_limit_t intel_limits_i8xx_dac = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 2 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_dvo = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 2, .max = 33 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 4, .p2_fast = 4 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i8xx_lvds = {
 185         .dot = { .min = 25000, .max = 350000 },
 186         .vco = { .min = 908000, .max = 1512000 },
 187         .n = { .min = 2, .max = 16 },
 188         .m = { .min = 96, .max = 140 },
 189         .m1 = { .min = 18, .max = 26 },
 190         .m2 = { .min = 6, .max = 16 },
 191         .p = { .min = 4, .max = 128 },
 192         .p1 = { .min = 1, .max = 6 },
 193         .p2 = { .dot_limit = 165000,
 194                 .p2_slow = 14, .p2_fast = 7 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_sdvo = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 200000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208 };
 209
 210 static const intel_limit_t intel_limits_i9xx_lvds = {
 211         .dot = { .min = 20000, .max = 400000 },
 212         .vco = { .min = 1400000, .max = 2800000 },
 213         .n = { .min = 1, .max = 6 },
 214         .m = { .min = 70, .max = 120 },
 215         .m1 = { .min = 8, .max = 18 },
 216         .m2 = { .min = 3, .max = 7 },
 217         .p = { .min = 7, .max = 98 },
 218         .p1 = { .min = 1, .max = 8 },
 219         .p2 = { .dot_limit = 112000,
 220                 .p2_slow = 14, .p2_fast = 7 },
 221 };
 222
 223
 224 static const intel_limit_t intel_limits_g4x_sdvo = {
 225         .dot = { .min = 25000, .max = 270000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 4 },
 228         .m = { .min = 104, .max = 138 },
 229         .m1 = { .min = 17, .max = 23 },
 230         .m2 = { .min = 5, .max = 11 },
 231         .p = { .min = 10, .max = 30 },
 232         .p1 = { .min = 1, .max = 3},
 233         .p2 = { .dot_limit = 270000,
 234                 .p2_slow = 10,
 235                 .p2_fast = 10
 236         },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_hdmi = {
 240         .dot = { .min = 22000, .max = 400000 },
 241         .vco = { .min = 1750000, .max = 3500000},
 242         .n = { .min = 1, .max = 4 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 16, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 5, .max = 80 },
 247         .p1 = { .min = 1, .max = 8},
 248         .p2 = { .dot_limit = 165000,
 249                 .p2_slow = 10, .p2_fast = 5 },
 250 };
 251
 252 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 253         .dot = { .min = 20000, .max = 115000 },
 254         .vco = { .min = 1750000, .max = 3500000 },
 255         .n = { .min = 1, .max = 3 },
 256         .m = { .min = 104, .max = 138 },
 257         .m1 = { .min = 17, .max = 23 },
 258         .m2 = { .min = 5, .max = 11 },
 259         .p = { .min = 28, .max = 112 },
 260         .p1 = { .min = 2, .max = 8 },
 261         .p2 = { .dot_limit = 0,
 262                 .p2_slow = 14, .p2_fast = 14
 263         },
 264 };
 265
 266 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 267         .dot = { .min = 80000, .max = 224000 },
 268         .vco = { .min = 1750000, .max = 3500000 },
 269         .n = { .min = 1, .max = 3 },
 270         .m = { .min = 104, .max = 138 },
 271         .m1 = { .min = 17, .max = 23 },
 272         .m2 = { .min = 5, .max = 11 },
 273         .p = { .min = 14, .max = 42 },
 274         .p1 = { .min = 2, .max = 6 },
 275         .p2 = { .dot_limit = 0,
 276                 .p2_slow = 7, .p2_fast = 7
 277         },
 278 };
 279
 280 static const intel_limit_t intel_limits_pineview_sdvo = {
 281         .dot = { .min = 20000, .max = 400000},
 282         .vco = { .min = 1700000, .max = 3500000 },
 283         /* Pineview's Ncounter is a ring counter */
 284         .n = { .min = 3, .max = 6 },
 285         .m = { .min = 2, .max = 256 },
 286         /* Pineview only has one combined m divider, which we treat as m2. */
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 200000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293 };
 294
 295 static const intel_limit_t intel_limits_pineview_lvds = {
 296         .dot = { .min = 20000, .max = 400000 },
 297         .vco = { .min = 1700000, .max = 3500000 },
 298         .n = { .min = 3, .max = 6 },
 299         .m = { .min = 2, .max = 256 },
 300         .m1 = { .min = 0, .max = 0 },
 301         .m2 = { .min = 0, .max = 254 },
 302         .p = { .min = 7, .max = 112 },
 303         .p1 = { .min = 1, .max = 8 },
 304         .p2 = { .dot_limit = 112000,
 305                 .p2_slow = 14, .p2_fast = 14 },
 306 };
 307
 308 /* Ironlake / Sandybridge
 309  *
 310  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 311  * the range value for them is (actual_value - 2).
 312  */
 313 static const intel_limit_t intel_limits_ironlake_dac = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 5 },
 317         .m = { .min = 79, .max = 127 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 5, .max = 80 },
 321         .p1 = { .min = 1, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 10, .p2_fast = 5 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 118 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 28, .max = 112 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 14, .p2_fast = 14 },
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 127 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 56 },
 347         .p1 = { .min = 2, .max = 8 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350 };
 351
 352 /* LVDS 100mhz refclk limits. */
 353 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 28, .max = 112 },
 361         .p1 = { .min = 2, .max = 8 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 14, .p2_fast = 14 },
 364 };
 365
 366 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 367         .dot = { .min = 25000, .max = 350000 },
 368         .vco = { .min = 1760000, .max = 3510000 },
 369         .n = { .min = 1, .max = 3 },
 370         .m = { .min = 79, .max = 126 },
 371         .m1 = { .min = 12, .max = 22 },
 372         .m2 = { .min = 5, .max = 9 },
 373         .p = { .min = 14, .max = 42 },
 374         .p1 = { .min = 2, .max = 6 },
 375         .p2 = { .dot_limit = 225000,
 376                 .p2_slow = 7, .p2_fast = 7 },
 377 };
 378
 379 static const intel_limit_t intel_limits_vlv = {
 380          /*
 381           * These are the data rate limits (measured in fast clocks)
 382           * since those are the strictest limits we have. The fast
 383           * clock and actual rate limits are more relaxed, so checking
 384           * them would make no difference.
 385           */
 386         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 387         .vco = { .min = 4000000, .max = 6000000 },
 388         .n = { .min = 1, .max = 7 },
 389         .m1 = { .min = 2, .max = 3 },
 390         .m2 = { .min = 11, .max = 156 },
 391         .p1 = { .min = 2, .max = 3 },
 392         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 393 };
 394
 395 static const intel_limit_t intel_limits_chv = {
 396         /*
 397          * These are the data rate limits (measured in fast clocks)
 398          * since those are the strictest limits we have.  The fast
 399          * clock and actual rate limits are more relaxed, so checking
 400          * them would make no difference.
 401          */
 402         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 403         .vco = { .min = 4800000, .max = 6480000 },
 404         .n = { .min = 1, .max = 1 },
 405         .m1 = { .min = 2, .max = 2 },
 406         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 407         .p1 = { .min = 2, .max = 4 },
 408         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 409 };
 410
 411 static const intel_limit_t intel_limits_bxt = {
 412         /* FIXME: find real dot limits */
 413         .dot = { .min = 0, .max = INT_MAX },
 414         .vco = { .min = 4800000, .max = 6480000 },
 415         .n = { .min = 1, .max = 1 },
 416         .m1 = { .min = 2, .max = 2 },
 417         /* FIXME: find real m2 limits */
 418         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 419         .p1 = { .min = 2, .max = 4 },
 420         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 421 };
 422
 423 static void vlv_clock(int refclk, intel_clock_t *clock)
 424 {
 425         clock->m = clock->m1 * clock->m2;
 426         clock->p = clock->p1 * clock->p2;
 427         if (WARN_ON(clock->n == 0 || clock->p == 0))
 428                 return;
 429         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 430         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 431 }
 432
 433 static bool
 434 needs_modeset(struct drm_crtc_state *state)
 435 {
 436         return state->mode_changed || state->active_changed;
 437 }
 438
 439 /**
 440  * Returns whether any output on the specified pipe is of the specified type
 441  */
 442 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         struct intel_encoder *encoder;
 446
 447         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 448                 if (encoder->type == type)
 449                         return true;
 450
 451         return false;
 452 }
 453
 454 /**
 455  * Returns whether any output on the specified pipe will have the specified
 456  * type after a staged modeset is complete, i.e., the same as
 457  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 458  * encoder->crtc.
 459  */
 460 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 461                                       int type)
 462 {
 463         struct drm_atomic_state *state = crtc_state->base.state;
 464         struct drm_connector *connector;
 465         struct drm_connector_state *connector_state;
 466         struct intel_encoder *encoder;
 467         int i, num_connectors = 0;
 468
 469         for_each_connector_in_state(state, connector, connector_state, i) {
 470                 if (connector_state->crtc != crtc_state->base.crtc)
 471                         continue;
 472
 473                 num_connectors++;
 474
 475                 encoder = to_intel_encoder(connector_state->best_encoder);
 476                 if (encoder->type == type)
 477                         return true;
 478         }
 479
 480         WARN_ON(num_connectors == 0);
 481
 482         return false;
 483 }
 484
 485 static const intel_limit_t *
 486 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 487 {
 488         struct drm_device *dev = crtc_state->base.crtc->dev;
 489         const intel_limit_t *limit;
 490
 491         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 492                 if (intel_is_dual_link_lvds(dev)) {
 493                         if (refclk == 100000)
 494                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 495                         else
 496                                 limit = &intel_limits_ironlake_dual_lvds;
 497                 } else {
 498                         if (refclk == 100000)
 499                                 limit = &intel_limits_ironlake_single_lvds_100m;
 500                         else
 501                                 limit = &intel_limits_ironlake_single_lvds;
 502                 }
 503         } else
 504                 limit = &intel_limits_ironlake_dac;
 505
 506         return limit;
 507 }
 508
 509 static const intel_limit_t *
 510 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 511 {
 512         struct drm_device *dev = crtc_state->base.crtc->dev;
 513         const intel_limit_t *limit;
 514
 515         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 516                 if (intel_is_dual_link_lvds(dev))
 517                         limit = &intel_limits_g4x_dual_channel_lvds;
 518                 else
 519                         limit = &intel_limits_g4x_single_channel_lvds;
 520         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 521                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 522                 limit = &intel_limits_g4x_hdmi;
 523         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 524                 limit = &intel_limits_g4x_sdvo;
 525         } else /* The option is for other outputs */
 526                 limit = &intel_limits_i9xx_sdvo;
 527
 528         return limit;
 529 }
 530
 531 static const intel_limit_t *
 532 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 533 {
 534         struct drm_device *dev = crtc_state->base.crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (IS_BROXTON(dev))
 538                 limit = &intel_limits_bxt;
 539         else if (HAS_PCH_SPLIT(dev))
 540                 limit = intel_ironlake_limit(crtc_state, refclk);
 541         else if (IS_G4X(dev)) {
 542                 limit = intel_g4x_limit(crtc_state);
 543         } else if (IS_PINEVIEW(dev)) {
 544                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 545                         limit = &intel_limits_pineview_lvds;
 546                 else
 547                         limit = &intel_limits_pineview_sdvo;
 548         } else if (IS_CHERRYVIEW(dev)) {
 549                 limit = &intel_limits_chv;
 550         } else if (IS_VALLEYVIEW(dev)) {
 551                 limit = &intel_limits_vlv;
 552         } else if (!IS_GEN2(dev)) {
 553                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 554                         limit = &intel_limits_i9xx_lvds;
 555                 else
 556                         limit = &intel_limits_i9xx_sdvo;
 557         } else {
 558                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 559                         limit = &intel_limits_i8xx_lvds;
 560                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 561                         limit = &intel_limits_i8xx_dvo;
 562                 else
 563                         limit = &intel_limits_i8xx_dac;
 564         }
 565         return limit;
 566 }
 567
 568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 569 static void pineview_clock(int refclk, intel_clock_t *clock)
 570 {
 571         clock->m = clock->m2 + 2;
 572         clock->p = clock->p1 * clock->p2;
 573         if (WARN_ON(clock->n == 0 || clock->p == 0))
 574                 return;
 575         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 576         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 577 }
 578
 579 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 580 {
 581         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 582 }
 583
 584 static void i9xx_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = i9xx_dpll_compute_m(clock);
 587         clock->p = clock->p1 * clock->p2;
 588         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 589                 return;
 590         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 591         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 592 }
 593
 594 static void chv_clock(int refclk, intel_clock_t *clock)
 595 {
 596         clock->m = clock->m1 * clock->m2;
 597         clock->p = clock->p1 * clock->p2;
 598         if (WARN_ON(clock->n == 0 || clock->p == 0))
 599                 return;
 600         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 601                         clock->n << 22);
 602         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 603 }
 604
 605 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 606 /**
 607  * Returns whether the given set of divisors are valid for a given refclk with
 608  * the given connectors.
 609  */
 610
 611 static bool intel_PLL_is_valid(struct drm_device *dev,
 612                                const intel_limit_t *limit,
 613                                const intel_clock_t *clock)
 614 {
 615         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 616                 INTELPllInvalid("n out of range\n");
 617         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 618                 INTELPllInvalid("p1 out of range\n");
 619         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 620                 INTELPllInvalid("m2 out of range\n");
 621         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 622                 INTELPllInvalid("m1 out of range\n");
 623
 624         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 625                 if (clock->m1 <= clock->m2)
 626                         INTELPllInvalid("m1 <= m2\n");
 627
 628         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 629                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 630                         INTELPllInvalid("p out of range\n");
 631                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 632                         INTELPllInvalid("m out of range\n");
 633         }
 634
 635         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 636                 INTELPllInvalid("vco out of range\n");
 637         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 638          * connector, etc., rather than just a single range.
 639          */
 640         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 641                 INTELPllInvalid("dot out of range\n");
 642
 643         return true;
 644 }
 645
 646 static bool
 647 i9xx_find_best_dpll(const intel_limit_t *limit,
 648                     struct intel_crtc_state *crtc_state,
 649                     int target, int refclk, intel_clock_t *match_clock,
 650                     intel_clock_t *best_clock)
 651 {
 652         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 653         struct drm_device *dev = crtc->base.dev;
 654         intel_clock_t clock;
 655         int err = target;
 656
 657         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 658                 /*
 659                  * For LVDS just rely on its current settings for dual-channel.
 660                  * We haven't figured out how to reliably set up different
 661                  * single/dual channel state, if we even can.
 662                  */
 663                 if (intel_is_dual_link_lvds(dev))
 664                         clock.p2 = limit->p2.p2_fast;
 665                 else
 666                         clock.p2 = limit->p2.p2_slow;
 667         } else {
 668                 if (target < limit->p2.dot_limit)
 669                         clock.p2 = limit->p2.p2_slow;
 670                 else
 671                         clock.p2 = limit->p2.p2_fast;
 672         }
 673
 674         memset(best_clock, 0, sizeof(*best_clock));
 675
 676         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 677              clock.m1++) {
 678                 for (clock.m2 = limit->m2.min;
 679                      clock.m2 <= limit->m2.max; clock.m2++) {
 680                         if (clock.m2 >= clock.m1)
 681                                 break;
 682                         for (clock.n = limit->n.min;
 683                              clock.n <= limit->n.max; clock.n++) {
 684                                 for (clock.p1 = limit->p1.min;
 685                                         clock.p1 <= limit->p1.max; clock.p1++) {
 686                                         int this_err;
 687
 688                                         i9xx_clock(refclk, &clock);
 689                                         if (!intel_PLL_is_valid(dev, limit,
 690                                                                 &clock))
 691                                                 continue;
 692                                         if (match_clock &&
 693                                             clock.p != match_clock->p)
 694                                                 continue;
 695
 696                                         this_err = abs(clock.dot - target);
 697                                         if (this_err < err) {
 698                                                 *best_clock = clock;
 699                                                 err = this_err;
 700                                         }
 701                                 }
 702                         }
 703                 }
 704         }
 705
 706         return (err != target);
 707 }
 708
 709 static bool
 710 pnv_find_best_dpll(const intel_limit_t *limit,
 711                    struct intel_crtc_state *crtc_state,
 712                    int target, int refclk, intel_clock_t *match_clock,
 713                    intel_clock_t *best_clock)
 714 {
 715         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 716         struct drm_device *dev = crtc->base.dev;
 717         intel_clock_t clock;
 718         int err = target;
 719
 720         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 721                 /*
 722                  * For LVDS just rely on its current settings for dual-channel.
 723                  * We haven't figured out how to reliably set up different
 724                  * single/dual channel state, if we even can.
 725                  */
 726                 if (intel_is_dual_link_lvds(dev))
 727                         clock.p2 = limit->p2.p2_fast;
 728                 else
 729                         clock.p2 = limit->p2.p2_slow;
 730         } else {
 731                 if (target < limit->p2.dot_limit)
 732                         clock.p2 = limit->p2.p2_slow;
 733                 else
 734                         clock.p2 = limit->p2.p2_fast;
 735         }
 736
 737         memset(best_clock, 0, sizeof(*best_clock));
 738
 739         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 740              clock.m1++) {
 741                 for (clock.m2 = limit->m2.min;
 742                      clock.m2 <= limit->m2.max; clock.m2++) {
 743                         for (clock.n = limit->n.min;
 744                              clock.n <= limit->n.max; clock.n++) {
 745                                 for (clock.p1 = limit->p1.min;
 746                                         clock.p1 <= limit->p1.max; clock.p1++) {
 747                                         int this_err;
 748
 749                                         pineview_clock(refclk, &clock);
 750                                         if (!intel_PLL_is_valid(dev, limit,
 751                                                                 &clock))
 752                                                 continue;
 753                                         if (match_clock &&
 754                                             clock.p != match_clock->p)
 755                                                 continue;
 756
 757                                         this_err = abs(clock.dot - target);
 758                                         if (this_err < err) {
 759                                                 *best_clock = clock;
 760                                                 err = this_err;
 761                                         }
 762                                 }
 763                         }
 764                 }
 765         }
 766
 767         return (err != target);
 768 }
 769
 770 static bool
 771 g4x_find_best_dpll(const intel_limit_t *limit,
 772                    struct intel_crtc_state *crtc_state,
 773                    int target, int refclk, intel_clock_t *match_clock,
 774                    intel_clock_t *best_clock)
 775 {
 776         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 777         struct drm_device *dev = crtc->base.dev;
 778         intel_clock_t clock;
 779         int max_n;
 780         bool found;
 781         /* approximately equals target * 0.00585 */
 782         int err_most = (target >> 8) + (target >> 9);
 783         found = false;
 784
 785         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 786                 if (intel_is_dual_link_lvds(dev))
 787                         clock.p2 = limit->p2.p2_fast;
 788                 else
 789                         clock.p2 = limit->p2.p2_slow;
 790         } else {
 791                 if (target < limit->p2.dot_limit)
 792                         clock.p2 = limit->p2.p2_slow;
 793                 else
 794                         clock.p2 = limit->p2.p2_fast;
 795         }
 796
 797         memset(best_clock, 0, sizeof(*best_clock));
 798         max_n = limit->n.max;
 799         /* based on hardware requirement, prefer smaller n to precision */
 800         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 801                 /* based on hardware requirement, prefere larger m1,m2 */
 802                 for (clock.m1 = limit->m1.max;
 803                      clock.m1 >= limit->m1.min; clock.m1--) {
 804                         for (clock.m2 = limit->m2.max;
 805                              clock.m2 >= limit->m2.min; clock.m2--) {
 806                                 for (clock.p1 = limit->p1.max;
 807                                      clock.p1 >= limit->p1.min; clock.p1--) {
 808                                         int this_err;
 809
 810                                         i9xx_clock(refclk, &clock);
 811                                         if (!intel_PLL_is_valid(dev, limit,
 812                                                                 &clock))
 813                                                 continue;
 814
 815                                         this_err = abs(clock.dot - target);
 816                                         if (this_err < err_most) {
 817                                                 *best_clock = clock;
 818                                                 err_most = this_err;
 819                                                 max_n = clock.n;
 820                                                 found = true;
 821                                         }
 822                                 }
 823                         }
 824                 }
 825         }
 826         return found;
 827 }
 828
 829 /*
 830  * Check if the calculated PLL configuration is more optimal compared to the
 831  * best configuration and error found so far. Return the calculated error.
 832  */
 833 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 834                                const intel_clock_t *calculated_clock,
 835                                const intel_clock_t *best_clock,
 836                                unsigned int best_error_ppm,
 837                                unsigned int *error_ppm)
 838 {
 839         /*
 840          * For CHV ignore the error and consider only the P value.
 841          * Prefer a bigger P value based on HW requirements.
 842          */
 843         if (IS_CHERRYVIEW(dev)) {
 844                 *error_ppm = 0;
 845
 846                 return calculated_clock->p > best_clock->p;
 847         }
 848
 849         if (WARN_ON_ONCE(!target_freq))
 850                 return false;
 851
 852         *error_ppm = div_u64(1000000ULL *
 853                                 abs(target_freq - calculated_clock->dot),
 854                              target_freq);
 855         /*
 856          * Prefer a better P value over a better (smaller) error if the error
 857          * is small. Ensure this preference for future configurations too by
 858          * setting the error to 0.
 859          */
 860         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 861                 *error_ppm = 0;
 862
 863                 return true;
 864         }
 865
 866         return *error_ppm + 10 < best_error_ppm;
 867 }
 868
 869 static bool
 870 vlv_find_best_dpll(const intel_limit_t *limit,
 871                    struct intel_crtc_state *crtc_state,
 872                    int target, int refclk, intel_clock_t *match_clock,
 873                    intel_clock_t *best_clock)
 874 {
 875         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 876         struct drm_device *dev = crtc->base.dev;
 877         intel_clock_t clock;
 878         unsigned int bestppm = 1000000;
 879         /* min update 19.2 MHz */
 880         int max_n = min(limit->n.max, refclk / 19200);
 881         bool found = false;
 882
 883         target *= 5; /* fast clock */
 884
 885         memset(best_clock, 0, sizeof(*best_clock));
 886
 887         /* based on hardware requirement, prefer smaller n to precision */
 888         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 889                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 890                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 891                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 892                                 clock.p = clock.p1 * clock.p2;
 893                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 894                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 895                                         unsigned int ppm;
 896
 897                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 898                                                                      refclk * clock.m1);
 899
 900                                         vlv_clock(refclk, &clock);
 901
 902                                         if (!intel_PLL_is_valid(dev, limit,
 903                                                                 &clock))
 904                                                 continue;
 905
 906                                         if (!vlv_PLL_is_optimal(dev, target,
 907                                                                 &clock,
 908                                                                 best_clock,
 909                                                                 bestppm, &ppm))
 910                                                 continue;
 911
 912                                         *best_clock = clock;
 913                                         bestppm = ppm;
 914                                         found = true;
 915                                 }
 916                         }
 917                 }
 918         }
 919
 920         return found;
 921 }
 922
 923 static bool
 924 chv_find_best_dpll(const intel_limit_t *limit,
 925                    struct intel_crtc_state *crtc_state,
 926                    int target, int refclk, intel_clock_t *match_clock,
 927                    intel_clock_t *best_clock)
 928 {
 929         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 930         struct drm_device *dev = crtc->base.dev;
 931         unsigned int best_error_ppm;
 932         intel_clock_t clock;
 933         uint64_t m2;
 934         int found = false;
 935
 936         memset(best_clock, 0, sizeof(*best_clock));
 937         best_error_ppm = 1000000;
 938
 939         /*
 940          * Based on hardware doc, the n always set to 1, and m1 always
 941          * set to 2.  If requires to support 200Mhz refclk, we need to
 942          * revisit this because n may not 1 anymore.
 943          */
 944         clock.n = 1, clock.m1 = 2;
 945         target *= 5;    /* fast clock */
 946
 947         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 948                 for (clock.p2 = limit->p2.p2_fast;
 949                                 clock.p2 >= limit->p2.p2_slow;
 950                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 951                         unsigned int error_ppm;
 952
 953                         clock.p = clock.p1 * clock.p2;
 954
 955                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 956                                         clock.n) << 22, refclk * clock.m1);
 957
 958                         if (m2 > INT_MAX/clock.m1)
 959                                 continue;
 960
 961                         clock.m2 = m2;
 962
 963                         chv_clock(refclk, &clock);
 964
 965                         if (!intel_PLL_is_valid(dev, limit, &clock))
 966                                 continue;
 967
 968                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 969                                                 best_error_ppm, &error_ppm))
 970                                 continue;
 971
 972                         *best_clock = clock;
 973                         best_error_ppm = error_ppm;
 974                         found = true;
 975                 }
 976         }
 977
 978         return found;
 979 }
 980
 981 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 982                         intel_clock_t *best_clock)
 983 {
 984         int refclk = i9xx_get_refclk(crtc_state, 0);
 985
 986         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 987                                   target_clock, refclk, NULL, best_clock);
 988 }
 989
 990 bool intel_crtc_active(struct drm_crtc *crtc)
 991 {
 992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 993
 994         /* Be paranoid as we can arrive here with only partial
 995          * state retrieved from the hardware during setup.
 996          *
 997          * We can ditch the adjusted_mode.crtc_clock check as soon
 998          * as Haswell has gained clock readout/fastboot support.
 999          *
1000          * We can ditch the crtc->primary->fb check as soon as we can
1001          * properly reconstruct framebuffers.
1002          *
1003          * FIXME: The intel_crtc->active here should be switched to
1004          * crtc->state->active once we have proper CRTC states wired up
1005          * for atomic.
1006          */
1007         return intel_crtc->active && crtc->primary->state->fb &&
1008                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1009 }
1010
1011 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012                                              enum pipe pipe)
1013 {
1014         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
1017         return intel_crtc->config->cpu_transcoder;
1018 }
1019
1020 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021 {
1022         struct drm_i915_private *dev_priv = dev->dev_private;
1023         u32 reg = PIPEDSL(pipe);
1024         u32 line1, line2;
1025         u32 line_mask;
1026
1027         if (IS_GEN2(dev))
1028                 line_mask = DSL_LINEMASK_GEN2;
1029         else
1030                 line_mask = DSL_LINEMASK_GEN3;
1031
1032         line1 = I915_READ(reg) & line_mask;
1033         mdelay(5);
1034         line2 = I915_READ(reg) & line_mask;
1035
1036         return line1 == line2;
1037 }
1038
1039 /*
1040  * intel_wait_for_pipe_off - wait for pipe to turn off
1041  * @crtc: crtc whose pipe to wait for
1042  *
1043  * After disabling a pipe, we can't wait for vblank in the usual way,
1044  * spinning on the vblank interrupt status bit, since we won't actually
1045  * see an interrupt when the pipe is disabled.
1046  *
1047  * On Gen4 and above:
1048  *   wait for the pipe register state bit to turn off
1049  *
1050  * Otherwise:
1051  *   wait for the display line value to settle (it usually
1052  *   ends up stopping at the start of the next frame).
1053  *
1054  */
1055 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1056 {
1057         struct drm_device *dev = crtc->base.dev;
1058         struct drm_i915_private *dev_priv = dev->dev_private;
1059         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1060         enum pipe pipe = crtc->pipe;
1061
1062         if (INTEL_INFO(dev)->gen >= 4) {
1063                 int reg = PIPECONF(cpu_transcoder);
1064
1065                 /* Wait for the Pipe State to go off */
1066                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067                              100))
1068                         WARN(1, "pipe_off wait timed out\n");
1069         } else {
1070                 /* Wait for the display line to settle */
1071                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1072                         WARN(1, "pipe_off wait timed out\n");
1073         }
1074 }
1075
1076 /*
1077  * ibx_digital_port_connected - is the specified port connected?
1078  * @dev_priv: i915 private structure
1079  * @port: the port to test
1080  *
1081  * Returns true if @port is connected, false otherwise.
1082  */
1083 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084                                 struct intel_digital_port *port)
1085 {
1086         u32 bit;
1087
1088         if (HAS_PCH_IBX(dev_priv->dev)) {
1089                 switch (port->port) {
1090                 case PORT_B:
1091                         bit = SDE_PORTB_HOTPLUG;
1092                         break;
1093                 case PORT_C:
1094                         bit = SDE_PORTC_HOTPLUG;
1095                         break;
1096                 case PORT_D:
1097                         bit = SDE_PORTD_HOTPLUG;
1098                         break;
1099                 default:
1100                         return true;
1101                 }
1102         } else {
1103                 switch (port->port) {
1104                 case PORT_B:
1105                         bit = SDE_PORTB_HOTPLUG_CPT;
1106                         break;
1107                 case PORT_C:
1108                         bit = SDE_PORTC_HOTPLUG_CPT;
1109                         break;
1110                 case PORT_D:
1111                         bit = SDE_PORTD_HOTPLUG_CPT;
1112                         break;
1113                 default:
1114                         return true;
1115                 }
1116         }
1117
1118         return I915_READ(SDEISR) & bit;
1119 }
1120
1121 static const char *state_string(bool enabled)
1122 {
1123         return enabled ? "on" : "off";
1124 }
1125
1126 /* Only for pre-ILK configs */
1127 void assert_pll(struct drm_i915_private *dev_priv,
1128                 enum pipe pipe, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133
1134         reg = DPLL(pipe);
1135         val = I915_READ(reg);
1136         cur_state = !!(val & DPLL_VCO_ENABLE);
1137         I915_STATE_WARN(cur_state != state,
1138              "PLL state assertion failure (expected %s, current %s)\n",
1139              state_string(state), state_string(cur_state));
1140 }
1141
1142 /* XXX: the dsi pll is shared between MIPI DSI ports */
1143 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144 {
1145         u32 val;
1146         bool cur_state;
1147
1148         mutex_lock(&dev_priv->sb_lock);
1149         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1150         mutex_unlock(&dev_priv->sb_lock);
1151
1152         cur_state = val & DSI_PLL_VCO_EN;
1153         I915_STATE_WARN(cur_state != state,
1154              "DSI PLL state assertion failure (expected %s, current %s)\n",
1155              state_string(state), state_string(cur_state));
1156 }
1157 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
1160 struct intel_shared_dpll *
1161 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162 {
1163         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
1165         if (crtc->config->shared_dpll < 0)
1166                 return NULL;
1167
1168         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1169 }
1170
1171 /* For ILK+ */
1172 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173                         struct intel_shared_dpll *pll,
1174                         bool state)
1175 {
1176         bool cur_state;
1177         struct intel_dpll_hw_state hw_state;
1178
1179         if (WARN (!pll,
1180                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1181                 return;
1182
1183         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1184         I915_STATE_WARN(cur_state != state,
1185              "%s assertion failure (expected %s, current %s)\n",
1186              pll->name, state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190                           enum pipe pipe, bool state)
1191 {
1192         int reg;
1193         u32 val;
1194         bool cur_state;
1195         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196                                                                       pipe);
1197
1198         if (HAS_DDI(dev_priv->dev)) {
1199                 /* DDI does not have a specific FDI_TX register */
1200                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1201                 val = I915_READ(reg);
1202                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1203         } else {
1204                 reg = FDI_TX_CTL(pipe);
1205                 val = I915_READ(reg);
1206                 cur_state = !!(val & FDI_TX_ENABLE);
1207         }
1208         I915_STATE_WARN(cur_state != state,
1209              "FDI TX state assertion failure (expected %s, current %s)\n",
1210              state_string(state), state_string(cur_state));
1211 }
1212 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216                           enum pipe pipe, bool state)
1217 {
1218         int reg;
1219         u32 val;
1220         bool cur_state;
1221
1222         reg = FDI_RX_CTL(pipe);
1223         val = I915_READ(reg);
1224         cur_state = !!(val & FDI_RX_ENABLE);
1225         I915_STATE_WARN(cur_state != state,
1226              "FDI RX state assertion failure (expected %s, current %s)\n",
1227              state_string(state), state_string(cur_state));
1228 }
1229 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233                                       enum pipe pipe)
1234 {
1235         int reg;
1236         u32 val;
1237
1238         /* ILK FDI PLL is always enabled */
1239         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1240                 return;
1241
1242         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1243         if (HAS_DDI(dev_priv->dev))
1244                 return;
1245
1246         reg = FDI_TX_CTL(pipe);
1247         val = I915_READ(reg);
1248         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1249 }
1250
1251 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252                        enum pipe pipe, bool state)
1253 {
1254         int reg;
1255         u32 val;
1256         bool cur_state;
1257
1258         reg = FDI_RX_CTL(pipe);
1259         val = I915_READ(reg);
1260         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1261         I915_STATE_WARN(cur_state != state,
1262              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263              state_string(state), state_string(cur_state));
1264 }
1265
1266 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267                            enum pipe pipe)
1268 {
1269         struct drm_device *dev = dev_priv->dev;
1270         int pp_reg;
1271         u32 val;
1272         enum pipe panel_pipe = PIPE_A;
1273         bool locked = true;
1274
1275         if (WARN_ON(HAS_DDI(dev)))
1276                 return;
1277
1278         if (HAS_PCH_SPLIT(dev)) {
1279                 u32 port_sel;
1280
1281                 pp_reg = PCH_PP_CONTROL;
1282                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286                         panel_pipe = PIPE_B;
1287                 /* XXX: else fix for eDP */
1288         } else if (IS_VALLEYVIEW(dev)) {
1289                 /* presumably write lock depends on pipe, not port select */
1290                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291                 panel_pipe = pipe;
1292         } else {
1293                 pp_reg = PP_CONTROL;
1294                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295                         panel_pipe = PIPE_B;
1296         }
1297
1298         val = I915_READ(pp_reg);
1299         if (!(val & PANEL_POWER_ON) ||
1300             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1301                 locked = false;
1302
1303         I915_STATE_WARN(panel_pipe == pipe && locked,
1304              "panel assertion failure, pipe %c regs locked\n",
1305              pipe_name(pipe));
1306 }
1307
1308 static void assert_cursor(struct drm_i915_private *dev_priv,
1309                           enum pipe pipe, bool state)
1310 {
1311         struct drm_device *dev = dev_priv->dev;
1312         bool cur_state;
1313
1314         if (IS_845G(dev) || IS_I865G(dev))
1315                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1316         else
1317                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1318
1319         I915_STATE_WARN(cur_state != state,
1320              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321              pipe_name(pipe), state_string(state), state_string(cur_state));
1322 }
1323 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
1326 void assert_pipe(struct drm_i915_private *dev_priv,
1327                  enum pipe pipe, bool state)
1328 {
1329         int reg;
1330         u32 val;
1331         bool cur_state;
1332         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333                                                                       pipe);
1334
1335         /* if we need the pipe quirk it must be always on */
1336         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1338                 state = true;
1339
1340         if (!intel_display_power_is_enabled(dev_priv,
1341                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1342                 cur_state = false;
1343         } else {
1344                 reg = PIPECONF(cpu_transcoder);
1345                 val = I915_READ(reg);
1346                 cur_state = !!(val & PIPECONF_ENABLE);
1347         }
1348
1349         I915_STATE_WARN(cur_state != state,
1350              "pipe %c assertion failure (expected %s, current %s)\n",
1351              pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353
1354 static void assert_plane(struct drm_i915_private *dev_priv,
1355                          enum plane plane, bool state)
1356 {
1357         int reg;
1358         u32 val;
1359         bool cur_state;
1360
1361         reg = DSPCNTR(plane);
1362         val = I915_READ(reg);
1363         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1364         I915_STATE_WARN(cur_state != state,
1365              "plane %c assertion failure (expected %s, current %s)\n",
1366              plane_name(plane), state_string(state), state_string(cur_state));
1367 }
1368
1369 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
1372 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373                                    enum pipe pipe)
1374 {
1375         struct drm_device *dev = dev_priv->dev;
1376         int reg, i;
1377         u32 val;
1378         int cur_pipe;
1379
1380         /* Primary planes are fixed to pipes on gen4+ */
1381         if (INTEL_INFO(dev)->gen >= 4) {
1382                 reg = DSPCNTR(pipe);
1383                 val = I915_READ(reg);
1384                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1385                      "plane %c assertion failure, should be disabled but not\n",
1386                      plane_name(pipe));
1387                 return;
1388         }
1389
1390         /* Need to check both planes against the pipe */
1391         for_each_pipe(dev_priv, i) {
1392                 reg = DSPCNTR(i);
1393                 val = I915_READ(reg);
1394                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395                         DISPPLANE_SEL_PIPE_SHIFT;
1396                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1397                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398                      plane_name(i), pipe_name(pipe));
1399         }
1400 }
1401
1402 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403                                     enum pipe pipe)
1404 {
1405         struct drm_device *dev = dev_priv->dev;
1406         int reg, sprite;
1407         u32 val;
1408
1409         if (INTEL_INFO(dev)->gen >= 9) {
1410                 for_each_sprite(dev_priv, pipe, sprite) {
1411                         val = I915_READ(PLANE_CTL(pipe, sprite));
1412                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1413                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414                              sprite, pipe_name(pipe));
1415                 }
1416         } else if (IS_VALLEYVIEW(dev)) {
1417                 for_each_sprite(dev_priv, pipe, sprite) {
1418                         reg = SPCNTR(pipe, sprite);
1419                         val = I915_READ(reg);
1420                         I915_STATE_WARN(val & SP_ENABLE,
1421                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite_name(pipe, sprite), pipe_name(pipe));
1423                 }
1424         } else if (INTEL_INFO(dev)->gen >= 7) {
1425                 reg = SPRCTL(pipe);
1426                 val = I915_READ(reg);
1427                 I915_STATE_WARN(val & SPRITE_ENABLE,
1428                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                      plane_name(pipe), pipe_name(pipe));
1430         } else if (INTEL_INFO(dev)->gen >= 5) {
1431                 reg = DVSCNTR(pipe);
1432                 val = I915_READ(reg);
1433                 I915_STATE_WARN(val & DVS_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         }
1437 }
1438
1439 static void assert_vblank_disabled(struct drm_crtc *crtc)
1440 {
1441         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1442                 drm_crtc_vblank_put(crtc);
1443 }
1444
1445 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1446 {
1447         u32 val;
1448         bool enabled;
1449
1450         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1451
1452         val = I915_READ(PCH_DREF_CONTROL);
1453         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454                             DREF_SUPERSPREAD_SOURCE_MASK));
1455         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1456 }
1457
1458 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459                                            enum pipe pipe)
1460 {
1461         int reg;
1462         u32 val;
1463         bool enabled;
1464
1465         reg = PCH_TRANSCONF(pipe);
1466         val = I915_READ(reg);
1467         enabled = !!(val & TRANS_ENABLE);
1468         I915_STATE_WARN(enabled,
1469              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470              pipe_name(pipe));
1471 }
1472
1473 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474                             enum pipe pipe, u32 port_sel, u32 val)
1475 {
1476         if ((val & DP_PORT_EN) == 0)
1477                 return false;
1478
1479         if (HAS_PCH_CPT(dev_priv->dev)) {
1480                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483                         return false;
1484         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486                         return false;
1487         } else {
1488                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489                         return false;
1490         }
1491         return true;
1492 }
1493
1494 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495                               enum pipe pipe, u32 val)
1496 {
1497         if ((val & SDVO_ENABLE) == 0)
1498                 return false;
1499
1500         if (HAS_PCH_CPT(dev_priv->dev)) {
1501                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1502                         return false;
1503         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505                         return false;
1506         } else {
1507                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1508                         return false;
1509         }
1510         return true;
1511 }
1512
1513 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514                               enum pipe pipe, u32 val)
1515 {
1516         if ((val & LVDS_PORT_EN) == 0)
1517                 return false;
1518
1519         if (HAS_PCH_CPT(dev_priv->dev)) {
1520                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521                         return false;
1522         } else {
1523                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524                         return false;
1525         }
1526         return true;
1527 }
1528
1529 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530                               enum pipe pipe, u32 val)
1531 {
1532         if ((val & ADPA_DAC_ENABLE) == 0)
1533                 return false;
1534         if (HAS_PCH_CPT(dev_priv->dev)) {
1535                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536                         return false;
1537         } else {
1538                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539                         return false;
1540         }
1541         return true;
1542 }
1543
1544 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1545                                    enum pipe pipe, int reg, u32 port_sel)
1546 {
1547         u32 val = I915_READ(reg);
1548         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1549              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1550              reg, pipe_name(pipe));
1551
1552         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1553              && (val & DP_PIPEB_SELECT),
1554              "IBX PCH dp port still using transcoder B\n");
1555 }
1556
1557 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558                                      enum pipe pipe, int reg)
1559 {
1560         u32 val = I915_READ(reg);
1561         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1562              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1563              reg, pipe_name(pipe));
1564
1565         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1566              && (val & SDVO_PIPE_B_SELECT),
1567              "IBX PCH hdmi port still using transcoder B\n");
1568 }
1569
1570 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571                                       enum pipe pipe)
1572 {
1573         int reg;
1574         u32 val;
1575
1576         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1579
1580         reg = PCH_ADPA;
1581         val = I915_READ(reg);
1582         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1583              "PCH VGA enabled on transcoder %c, should be disabled\n",
1584              pipe_name(pipe));
1585
1586         reg = PCH_LVDS;
1587         val = I915_READ(reg);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void intel_init_dpio(struct drm_device *dev)
1598 {
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601         if (!IS_VALLEYVIEW(dev))
1602                 return;
1603
1604         /*
1605          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606          * CHV x1 PHY (DP/HDMI D)
1607          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608          */
1609         if (IS_CHERRYVIEW(dev)) {
1610                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612         } else {
1613                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614         }
1615 }
1616
1617 static void vlv_enable_pll(struct intel_crtc *crtc,
1618                            const struct intel_crtc_state *pipe_config)
1619 {
1620         struct drm_device *dev = crtc->base.dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         int reg = DPLL(crtc->pipe);
1623         u32 dpll = pipe_config->dpll_hw_state.dpll;
1624
1625         assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627         /* No really, not for ILK+ */
1628         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630         /* PLL is protected by panel, make sure we can write it */
1631         if (IS_MOBILE(dev_priv->dev))
1632                 assert_panel_unlocked(dev_priv, crtc->pipe);
1633
1634         I915_WRITE(reg, dpll);
1635         POSTING_READ(reg);
1636         udelay(150);
1637
1638         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
1641         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1642         POSTING_READ(DPLL_MD(crtc->pipe));
1643
1644         /* We do this three times for luck */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651         I915_WRITE(reg, dpll);
1652         POSTING_READ(reg);
1653         udelay(150); /* wait for warmup */
1654 }
1655
1656 static void chv_enable_pll(struct intel_crtc *crtc,
1657                            const struct intel_crtc_state *pipe_config)
1658 {
1659         struct drm_device *dev = crtc->base.dev;
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         int pipe = crtc->pipe;
1662         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1663         u32 tmp;
1664
1665         assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
1669         mutex_lock(&dev_priv->sb_lock);
1670
1671         /* Enable back the 10bit clock to display controller */
1672         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673         tmp |= DPIO_DCLKP_EN;
1674         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
1676         mutex_unlock(&dev_priv->sb_lock);
1677
1678         /*
1679          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680          */
1681         udelay(1);
1682
1683         /* Enable PLL */
1684         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1685
1686         /* Check PLL is locked */
1687         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1688                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
1690         /* not sure when this should be written */
1691         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1692         POSTING_READ(DPLL_MD(pipe));
1693 }
1694
1695 static int intel_num_dvo_pipes(struct drm_device *dev)
1696 {
1697         struct intel_crtc *crtc;
1698         int count = 0;
1699
1700         for_each_intel_crtc(dev, crtc)
1701                 count += crtc->base.state->active &&
1702                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1703
1704         return count;
1705 }
1706
1707 static void i9xx_enable_pll(struct intel_crtc *crtc)
1708 {
1709         struct drm_device *dev = crtc->base.dev;
1710         struct drm_i915_private *dev_priv = dev->dev_private;
1711         int reg = DPLL(crtc->pipe);
1712         u32 dpll = crtc->config->dpll_hw_state.dpll;
1713
1714         assert_pipe_disabled(dev_priv, crtc->pipe);
1715
1716         /* No really, not for ILK+ */
1717         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1718
1719         /* PLL is protected by panel, make sure we can write it */
1720         if (IS_MOBILE(dev) && !IS_I830(dev))
1721                 assert_panel_unlocked(dev_priv, crtc->pipe);
1722
1723         /* Enable DVO 2x clock on both PLLs if necessary */
1724         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725                 /*
1726                  * It appears to be important that we don't enable this
1727                  * for the current pipe before otherwise configuring the
1728                  * PLL. No idea how this should be handled if multiple
1729                  * DVO outputs are enabled simultaneosly.
1730                  */
1731                 dpll |= DPLL_DVO_2X_MODE;
1732                 I915_WRITE(DPLL(!crtc->pipe),
1733                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734         }
1735
1736         /* Wait for the clocks to stabilize. */
1737         POSTING_READ(reg);
1738         udelay(150);
1739
1740         if (INTEL_INFO(dev)->gen >= 4) {
1741                 I915_WRITE(DPLL_MD(crtc->pipe),
1742                            crtc->config->dpll_hw_state.dpll_md);
1743         } else {
1744                 /* The pixel multiplier can only be updated once the
1745                  * DPLL is enabled and the clocks are stable.
1746                  *
1747                  * So write it again.
1748                  */
1749                 I915_WRITE(reg, dpll);
1750         }
1751
1752         /* We do this three times for luck */
1753         I915_WRITE(reg, dpll);
1754         POSTING_READ(reg);
1755         udelay(150); /* wait for warmup */
1756         I915_WRITE(reg, dpll);
1757         POSTING_READ(reg);
1758         udelay(150); /* wait for warmup */
1759         I915_WRITE(reg, dpll);
1760         POSTING_READ(reg);
1761         udelay(150); /* wait for warmup */
1762 }
1763
1764 /**
1765  * i9xx_disable_pll - disable a PLL
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe PLL to disable
1768  *
1769  * Disable the PLL for @pipe, making sure the pipe is off first.
1770  *
1771  * Note!  This is for pre-ILK only.
1772  */
1773 static void i9xx_disable_pll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         enum pipe pipe = crtc->pipe;
1778
1779         /* Disable DVO 2x clock on both PLLs if necessary */
1780         if (IS_I830(dev) &&
1781             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1782             !intel_num_dvo_pipes(dev)) {
1783                 I915_WRITE(DPLL(PIPE_B),
1784                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785                 I915_WRITE(DPLL(PIPE_A),
1786                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787         }
1788
1789         /* Don't disable pipe or pipe PLLs if needed */
1790         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1792                 return;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         I915_WRITE(DPLL(pipe), 0);
1798         POSTING_READ(DPLL(pipe));
1799 }
1800
1801 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802 {
1803         u32 val = 0;
1804
1805         /* Make sure the pipe isn't still relying on us */
1806         assert_pipe_disabled(dev_priv, pipe);
1807
1808         /*
1809          * Leave integrated clock source and reference clock enabled for pipe B.
1810          * The latter is needed for VGA hotplug / manual detection.
1811          */
1812         if (pipe == PIPE_B)
1813                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1814         I915_WRITE(DPLL(pipe), val);
1815         POSTING_READ(DPLL(pipe));
1816
1817 }
1818
1819 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820 {
1821         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1822         u32 val;
1823
1824         /* Make sure the pipe isn't still relying on us */
1825         assert_pipe_disabled(dev_priv, pipe);
1826
1827         /* Set PLL en = 0 */
1828         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1829         if (pipe != PIPE_A)
1830                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831         I915_WRITE(DPLL(pipe), val);
1832         POSTING_READ(DPLL(pipe));
1833
1834         mutex_lock(&dev_priv->sb_lock);
1835
1836         /* Disable 10bit clock to display controller */
1837         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838         val &= ~DPIO_DCLKP_EN;
1839         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
1841         /* disable left/right clock distribution */
1842         if (pipe != PIPE_B) {
1843                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846         } else {
1847                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850         }
1851
1852         mutex_unlock(&dev_priv->sb_lock);
1853 }
1854
1855 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1856                          struct intel_digital_port *dport,
1857                          unsigned int expected_mask)
1858 {
1859         u32 port_mask;
1860         int dpll_reg;
1861
1862         switch (dport->port) {
1863         case PORT_B:
1864                 port_mask = DPLL_PORTB_READY_MASK;
1865                 dpll_reg = DPLL(0);
1866                 break;
1867         case PORT_C:
1868                 port_mask = DPLL_PORTC_READY_MASK;
1869                 dpll_reg = DPLL(0);
1870                 expected_mask <<= 4;
1871                 break;
1872         case PORT_D:
1873                 port_mask = DPLL_PORTD_READY_MASK;
1874                 dpll_reg = DPIO_PHY_STATUS;
1875                 break;
1876         default:
1877                 BUG();
1878         }
1879
1880         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1883 }
1884
1885 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886 {
1887         struct drm_device *dev = crtc->base.dev;
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
1891         if (WARN_ON(pll == NULL))
1892                 return;
1893
1894         WARN_ON(!pll->config.crtc_mask);
1895         if (pll->active == 0) {
1896                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897                 WARN_ON(pll->on);
1898                 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900                 pll->mode_set(dev_priv, pll);
1901         }
1902 }
1903
1904 /**
1905  * intel_enable_shared_dpll - enable PCH PLL
1906  * @dev_priv: i915 private structure
1907  * @pipe: pipe PLL to enable
1908  *
1909  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910  * drives the transcoder clock.
1911  */
1912 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1913 {
1914         struct drm_device *dev = crtc->base.dev;
1915         struct drm_i915_private *dev_priv = dev->dev_private;
1916         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1917
1918         if (WARN_ON(pll == NULL))
1919                 return;
1920
1921         if (WARN_ON(pll->config.crtc_mask == 0))
1922                 return;
1923
1924         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1925                       pll->name, pll->active, pll->on,
1926                       crtc->base.base.id);
1927
1928         if (pll->active++) {
1929                 WARN_ON(!pll->on);
1930                 assert_shared_dpll_enabled(dev_priv, pll);
1931                 return;
1932         }
1933         WARN_ON(pll->on);
1934
1935         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
1937         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1938         pll->enable(dev_priv, pll);
1939         pll->on = true;
1940 }
1941
1942 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1943 {
1944         struct drm_device *dev = crtc->base.dev;
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1947
1948         /* PCH only available on ILK+ */
1949         BUG_ON(INTEL_INFO(dev)->gen < 5);
1950         if (WARN_ON(pll == NULL))
1951                return;
1952
1953         if (WARN_ON(pll->config.crtc_mask == 0))
1954                 return;
1955
1956         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957                       pll->name, pll->active, pll->on,
1958                       crtc->base.base.id);
1959
1960         if (WARN_ON(pll->active == 0)) {
1961                 assert_shared_dpll_disabled(dev_priv, pll);
1962                 return;
1963         }
1964
1965         assert_shared_dpll_enabled(dev_priv, pll);
1966         WARN_ON(!pll->on);
1967         if (--pll->active)
1968                 return;
1969
1970         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1971         pll->disable(dev_priv, pll);
1972         pll->on = false;
1973
1974         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1975 }
1976
1977 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978                                            enum pipe pipe)
1979 {
1980         struct drm_device *dev = dev_priv->dev;
1981         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         uint32_t reg, val, pipeconf_val;
1984
1985         /* PCH only available on ILK+ */
1986         BUG_ON(!HAS_PCH_SPLIT(dev));
1987
1988         /* Make sure PCH DPLL is enabled */
1989         assert_shared_dpll_enabled(dev_priv,
1990                                    intel_crtc_to_shared_dpll(intel_crtc));
1991
1992         /* FDI must be feeding us bits for PCH ports */
1993         assert_fdi_tx_enabled(dev_priv, pipe);
1994         assert_fdi_rx_enabled(dev_priv, pipe);
1995
1996         if (HAS_PCH_CPT(dev)) {
1997                 /* Workaround: Set the timing override bit before enabling the
1998                  * pch transcoder. */
1999                 reg = TRANS_CHICKEN2(pipe);
2000                 val = I915_READ(reg);
2001                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002                 I915_WRITE(reg, val);
2003         }
2004
2005         reg = PCH_TRANSCONF(pipe);
2006         val = I915_READ(reg);
2007         pipeconf_val = I915_READ(PIPECONF(pipe));
2008
2009         if (HAS_PCH_IBX(dev_priv->dev)) {
2010                 /*
2011                  * Make the BPC in transcoder be consistent with
2012                  * that in pipeconf reg. For HDMI we must use 8bpc
2013                  * here for both 8bpc and 12bpc.
2014                  */
2015                 val &= ~PIPECONF_BPC_MASK;
2016                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017                         val |= PIPECONF_8BPC;
2018                 else
2019                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2020         }
2021
2022         val &= ~TRANS_INTERLACE_MASK;
2023         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2024                 if (HAS_PCH_IBX(dev_priv->dev) &&
2025                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2026                         val |= TRANS_LEGACY_INTERLACED_ILK;
2027                 else
2028                         val |= TRANS_INTERLACED;
2029         else
2030                 val |= TRANS_PROGRESSIVE;
2031
2032         I915_WRITE(reg, val | TRANS_ENABLE);
2033         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2034                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2035 }
2036
2037 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2038                                       enum transcoder cpu_transcoder)
2039 {
2040         u32 val, pipeconf_val;
2041
2042         /* PCH only available on ILK+ */
2043         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2044
2045         /* FDI must be feeding us bits for PCH ports */
2046         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2047         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2048
2049         /* Workaround: set timing override bit. */
2050         val = I915_READ(_TRANSA_CHICKEN2);
2051         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2052         I915_WRITE(_TRANSA_CHICKEN2, val);
2053
2054         val = TRANS_ENABLE;
2055         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2056
2057         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058             PIPECONF_INTERLACED_ILK)
2059                 val |= TRANS_INTERLACED;
2060         else
2061                 val |= TRANS_PROGRESSIVE;
2062
2063         I915_WRITE(LPT_TRANSCONF, val);
2064         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2065                 DRM_ERROR("Failed to enable PCH transcoder\n");
2066 }
2067
2068 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2069                                             enum pipe pipe)
2070 {
2071         struct drm_device *dev = dev_priv->dev;
2072         uint32_t reg, val;
2073
2074         /* FDI relies on the transcoder */
2075         assert_fdi_tx_disabled(dev_priv, pipe);
2076         assert_fdi_rx_disabled(dev_priv, pipe);
2077
2078         /* Ports must be off as well */
2079         assert_pch_ports_disabled(dev_priv, pipe);
2080
2081         reg = PCH_TRANSCONF(pipe);
2082         val = I915_READ(reg);
2083         val &= ~TRANS_ENABLE;
2084         I915_WRITE(reg, val);
2085         /* wait for PCH transcoder off, transcoder state */
2086         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2087                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2088
2089         if (!HAS_PCH_IBX(dev)) {
2090                 /* Workaround: Clear the timing override chicken bit again. */
2091                 reg = TRANS_CHICKEN2(pipe);
2092                 val = I915_READ(reg);
2093                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094                 I915_WRITE(reg, val);
2095         }
2096 }
2097
2098 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2099 {
2100         u32 val;
2101
2102         val = I915_READ(LPT_TRANSCONF);
2103         val &= ~TRANS_ENABLE;
2104         I915_WRITE(LPT_TRANSCONF, val);
2105         /* wait for PCH transcoder off, transcoder state */
2106         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2107                 DRM_ERROR("Failed to disable PCH transcoder\n");
2108
2109         /* Workaround: clear timing override bit. */
2110         val = I915_READ(_TRANSA_CHICKEN2);
2111         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2112         I915_WRITE(_TRANSA_CHICKEN2, val);
2113 }
2114
2115 /**
2116  * intel_enable_pipe - enable a pipe, asserting requirements
2117  * @crtc: crtc responsible for the pipe
2118  *
2119  * Enable @crtc's pipe, making sure that various hardware specific requirements
2120  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2121  */
2122 static void intel_enable_pipe(struct intel_crtc *crtc)
2123 {
2124         struct drm_device *dev = crtc->base.dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126         enum pipe pipe = crtc->pipe;
2127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2128                                                                       pipe);
2129         enum pipe pch_transcoder;
2130         int reg;
2131         u32 val;
2132
2133         assert_planes_disabled(dev_priv, pipe);
2134         assert_cursor_disabled(dev_priv, pipe);
2135         assert_sprites_disabled(dev_priv, pipe);
2136
2137         if (HAS_PCH_LPT(dev_priv->dev))
2138                 pch_transcoder = TRANSCODER_A;
2139         else
2140                 pch_transcoder = pipe;
2141
2142         /*
2143          * A pipe without a PLL won't actually be able to drive bits from
2144          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2145          * need the check.
2146          */
2147         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2148                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2149                         assert_dsi_pll_enabled(dev_priv);
2150                 else
2151                         assert_pll_enabled(dev_priv, pipe);
2152         else {
2153                 if (crtc->config->has_pch_encoder) {
2154                         /* if driving the PCH, we need FDI enabled */
2155                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2156                         assert_fdi_tx_pll_enabled(dev_priv,
2157                                                   (enum pipe) cpu_transcoder);
2158                 }
2159                 /* FIXME: assert CPU port conditions for SNB+ */
2160         }
2161
2162         reg = PIPECONF(cpu_transcoder);
2163         val = I915_READ(reg);
2164         if (val & PIPECONF_ENABLE) {
2165                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2167                 return;
2168         }
2169
2170         I915_WRITE(reg, val | PIPECONF_ENABLE);
2171         POSTING_READ(reg);
2172 }
2173
2174 /**
2175  * intel_disable_pipe - disable a pipe, asserting requirements
2176  * @crtc: crtc whose pipes is to be disabled
2177  *
2178  * Disable the pipe of @crtc, making sure that various hardware
2179  * specific requirements are met, if applicable, e.g. plane
2180  * disabled, panel fitter off, etc.
2181  *
2182  * Will wait until the pipe has shut down before returning.
2183  */
2184 static void intel_disable_pipe(struct intel_crtc *crtc)
2185 {
2186         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2187         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2188         enum pipe pipe = crtc->pipe;
2189         int reg;
2190         u32 val;
2191
2192         /*
2193          * Make sure planes won't keep trying to pump pixels to us,
2194          * or we might hang the display.
2195          */
2196         assert_planes_disabled(dev_priv, pipe);
2197         assert_cursor_disabled(dev_priv, pipe);
2198         assert_sprites_disabled(dev_priv, pipe);
2199
2200         reg = PIPECONF(cpu_transcoder);
2201         val = I915_READ(reg);
2202         if ((val & PIPECONF_ENABLE) == 0)
2203                 return;
2204
2205         /*
2206          * Double wide has implications for planes
2207          * so best keep it disabled when not needed.
2208          */
2209         if (crtc->config->double_wide)
2210                 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212         /* Don't disable pipe or pipe PLLs if needed */
2213         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2215                 val &= ~PIPECONF_ENABLE;
2216
2217         I915_WRITE(reg, val);
2218         if ((val & PIPECONF_ENABLE) == 0)
2219                 intel_wait_for_pipe_off(crtc);
2220 }
2221
2222 /**
2223  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224  * @plane:  plane to be enabled
2225  * @crtc: crtc for the plane
2226  *
2227  * Enable @plane on @crtc, making sure that the pipe is running first.
2228  */
2229 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230                                           struct drm_crtc *crtc)
2231 {
2232         struct drm_device *dev = plane->dev;
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235
2236         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2238         to_intel_plane_state(plane->state)->visible = true;
2239
2240         dev_priv->display.update_primary_plane(crtc, plane->fb,
2241                                                crtc->x, crtc->y);
2242 }
2243
2244 static bool need_vtd_wa(struct drm_device *dev)
2245 {
2246 #ifdef CONFIG_INTEL_IOMMU
2247         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248                 return true;
2249 #endif
2250         return false;
2251 }
2252
2253 unsigned int
2254 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255                   uint64_t fb_format_modifier)
2256 {
2257         unsigned int tile_height;
2258         uint32_t pixel_bytes;
2259
2260         switch (fb_format_modifier) {
2261         case DRM_FORMAT_MOD_NONE:
2262                 tile_height = 1;
2263                 break;
2264         case I915_FORMAT_MOD_X_TILED:
2265                 tile_height = IS_GEN2(dev) ? 16 : 8;
2266                 break;
2267         case I915_FORMAT_MOD_Y_TILED:
2268                 tile_height = 32;
2269                 break;
2270         case I915_FORMAT_MOD_Yf_TILED:
2271                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272                 switch (pixel_bytes) {
2273                 default:
2274                 case 1:
2275                         tile_height = 64;
2276                         break;
2277                 case 2:
2278                 case 4:
2279                         tile_height = 32;
2280                         break;
2281                 case 8:
2282                         tile_height = 16;
2283                         break;
2284                 case 16:
2285                         WARN_ONCE(1,
2286                                   "128-bit pixels are not supported for display!");
2287                         tile_height = 16;
2288                         break;
2289                 }
2290                 break;
2291         default:
2292                 MISSING_CASE(fb_format_modifier);
2293                 tile_height = 1;
2294                 break;
2295         }
2296
2297         return tile_height;
2298 }
2299
2300 unsigned int
2301 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302                       uint32_t pixel_format, uint64_t fb_format_modifier)
2303 {
2304         return ALIGN(height, intel_tile_height(dev, pixel_format,
2305                                                fb_format_modifier));
2306 }
2307
2308 static int
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310                         const struct drm_plane_state *plane_state)
2311 {
2312         struct intel_rotation_info *info = &view->rotation_info;
2313
2314         *view = i915_ggtt_view_normal;
2315
2316         if (!plane_state)
2317                 return 0;
2318
2319         if (!intel_rotation_90_or_270(plane_state->rotation))
2320                 return 0;
2321
2322         *view = i915_ggtt_view_rotated;
2323
2324         info->height = fb->height;
2325         info->pixel_format = fb->pixel_format;
2326         info->pitch = fb->pitches[0];
2327         info->fb_modifier = fb->modifier[0];
2328
2329         return 0;
2330 }
2331
2332 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2333 {
2334         if (INTEL_INFO(dev_priv)->gen >= 9)
2335                 return 256 * 1024;
2336         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337                  IS_VALLEYVIEW(dev_priv))
2338                 return 128 * 1024;
2339         else if (INTEL_INFO(dev_priv)->gen >= 4)
2340                 return 4 * 1024;
2341         else
2342                 return 0;
2343 }
2344
2345 int
2346 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347                            struct drm_framebuffer *fb,
2348                            const struct drm_plane_state *plane_state,
2349                            struct intel_engine_cs *pipelined)
2350 {
2351         struct drm_device *dev = fb->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2354         struct i915_ggtt_view view;
2355         u32 alignment;
2356         int ret;
2357
2358         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
2360         switch (fb->modifier[0]) {
2361         case DRM_FORMAT_MOD_NONE:
2362                 alignment = intel_linear_alignment(dev_priv);
2363                 break;
2364         case I915_FORMAT_MOD_X_TILED:
2365                 if (INTEL_INFO(dev)->gen >= 9)
2366                         alignment = 256 * 1024;
2367                 else {
2368                         /* pin() will align the object as required by fence */
2369                         alignment = 0;
2370                 }
2371                 break;
2372         case I915_FORMAT_MOD_Y_TILED:
2373         case I915_FORMAT_MOD_Yf_TILED:
2374                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375                           "Y tiling bo slipped through, driver bug!\n"))
2376                         return -EINVAL;
2377                 alignment = 1 * 1024 * 1024;
2378                 break;
2379         default:
2380                 MISSING_CASE(fb->modifier[0]);
2381                 return -EINVAL;
2382         }
2383
2384         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2385         if (ret)
2386                 return ret;
2387
2388         /* Note that the w/a also requires 64 PTE of padding following the
2389          * bo. We currently fill all unused PTE with the shadow page and so
2390          * we should always have valid PTE following the scanout preventing
2391          * the VT-d warning.
2392          */
2393         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394                 alignment = 256 * 1024;
2395
2396         /*
2397          * Global gtt pte registers are special registers which actually forward
2398          * writes to a chunk of system memory. Which means that there is no risk
2399          * that the register values disappear as soon as we call
2400          * intel_runtime_pm_put(), so it is correct to wrap only the
2401          * pin/unpin/fence and not more.
2402          */
2403         intel_runtime_pm_get(dev_priv);
2404
2405         dev_priv->mm.interruptible = false;
2406         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2407                                                    &view);
2408         if (ret)
2409                 goto err_interruptible;
2410
2411         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412          * fence, whereas 965+ only requires a fence if using
2413          * framebuffer compression.  For simplicity, we always install
2414          * a fence as the cost is not that onerous.
2415          */
2416         ret = i915_gem_object_get_fence(obj);
2417         if (ret)
2418                 goto err_unpin;
2419
2420         i915_gem_object_pin_fence(obj);
2421
2422         dev_priv->mm.interruptible = true;
2423         intel_runtime_pm_put(dev_priv);
2424         return 0;
2425
2426 err_unpin:
2427         i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_interruptible:
2429         dev_priv->mm.interruptible = true;
2430         intel_runtime_pm_put(dev_priv);
2431         return ret;
2432 }
2433
2434 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435                                const struct drm_plane_state *plane_state)
2436 {
2437         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2438         struct i915_ggtt_view view;
2439         int ret;
2440
2441         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2442
2443         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444         WARN_ONCE(ret, "Couldn't get view from plane state!");
2445
2446         i915_gem_object_unpin_fence(obj);
2447         i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451  * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453                                              int *x, int *y,
2454                                              unsigned int tiling_mode,
2455                                              unsigned int cpp,
2456                                              unsigned int pitch)
2457 {
2458         if (tiling_mode != I915_TILING_NONE) {
2459                 unsigned int tile_rows, tiles;
2460
2461                 tile_rows = *y / 8;
2462                 *y %= 8;
2463
2464                 tiles = *x / (512/cpp);
2465                 *x %= 512/cpp;
2466
2467                 return tile_rows * pitch * 8 + tiles * 4096;
2468         } else {
2469                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470                 unsigned int offset;
2471
2472                 offset = *y * pitch + *x * cpp;
2473                 *y = (offset & alignment) / pitch;
2474                 *x = ((offset & alignment) - *y * pitch) / cpp;
2475                 return offset & ~alignment;
2476         }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481         switch (format) {
2482         case DISPPLANE_8BPP:
2483                 return DRM_FORMAT_C8;
2484         case DISPPLANE_BGRX555:
2485                 return DRM_FORMAT_XRGB1555;
2486         case DISPPLANE_BGRX565:
2487                 return DRM_FORMAT_RGB565;
2488         default:
2489         case DISPPLANE_BGRX888:
2490                 return DRM_FORMAT_XRGB8888;
2491         case DISPPLANE_RGBX888:
2492                 return DRM_FORMAT_XBGR8888;
2493         case DISPPLANE_BGRX101010:
2494                 return DRM_FORMAT_XRGB2101010;
2495         case DISPPLANE_RGBX101010:
2496                 return DRM_FORMAT_XBGR2101010;
2497         }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502         switch (format) {
2503         case PLANE_CTL_FORMAT_RGB_565:
2504                 return DRM_FORMAT_RGB565;
2505         default:
2506         case PLANE_CTL_FORMAT_XRGB_8888:
2507                 if (rgb_order) {
2508                         if (alpha)
2509                                 return DRM_FORMAT_ABGR8888;
2510                         else
2511                                 return DRM_FORMAT_XBGR8888;
2512                 } else {
2513                         if (alpha)
2514                                 return DRM_FORMAT_ARGB8888;
2515                         else
2516                                 return DRM_FORMAT_XRGB8888;
2517                 }
2518         case PLANE_CTL_FORMAT_XRGB_2101010:
2519                 if (rgb_order)
2520                         return DRM_FORMAT_XBGR2101010;
2521                 else
2522                         return DRM_FORMAT_XRGB2101010;
2523         }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528                               struct intel_initial_plane_config *plane_config)
2529 {
2530         struct drm_device *dev = crtc->base.dev;
2531         struct drm_i915_gem_object *obj = NULL;
2532         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2533         struct drm_framebuffer *fb = &plane_config->fb->base;
2534         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2536                                     PAGE_SIZE);
2537
2538         size_aligned -= base_aligned;
2539
2540         if (plane_config->size == 0)
2541                 return false;
2542
2543         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544                                                              base_aligned,
2545                                                              base_aligned,
2546                                                              size_aligned);
2547         if (!obj)
2548                 return false;
2549
2550         obj->tiling_mode = plane_config->tiling;
2551         if (obj->tiling_mode == I915_TILING_X)
2552                 obj->stride = fb->pitches[0];
2553
2554         mode_cmd.pixel_format = fb->pixel_format;
2555         mode_cmd.width = fb->width;
2556         mode_cmd.height = fb->height;
2557         mode_cmd.pitches[0] = fb->pitches[0];
2558         mode_cmd.modifier[0] = fb->modifier[0];
2559         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2560
2561         mutex_lock(&dev->struct_mutex);
2562         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2563                                    &mode_cmd, obj)) {
2564                 DRM_DEBUG_KMS("intel fb init failed\n");
2565                 goto out_unref_obj;
2566         }
2567         mutex_unlock(&dev->struct_mutex);
2568
2569         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2570         return true;
2571
2572 out_unref_obj:
2573         drm_gem_object_unreference(&obj->base);
2574         mutex_unlock(&dev->struct_mutex);
2575         return false;
2576 }
2577
2578 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2579 static void
2580 update_state_fb(struct drm_plane *plane)
2581 {
2582         if (plane->fb == plane->state->fb)
2583                 return;
2584
2585         if (plane->state->fb)
2586                 drm_framebuffer_unreference(plane->state->fb);
2587         plane->state->fb = plane->fb;
2588         if (plane->state->fb)
2589                 drm_framebuffer_reference(plane->state->fb);
2590 }
2591
2592 static void
2593 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594                              struct intel_initial_plane_config *plane_config)
2595 {
2596         struct drm_device *dev = intel_crtc->base.dev;
2597         struct drm_i915_private *dev_priv = dev->dev_private;
2598         struct drm_crtc *c;
2599         struct intel_crtc *i;
2600         struct drm_i915_gem_object *obj;
2601         struct drm_plane *primary = intel_crtc->base.primary;
2602         struct drm_framebuffer *fb;
2603
2604         if (!plane_config->fb)
2605                 return;
2606
2607         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608                 fb = &plane_config->fb->base;
2609                 goto valid_fb;
2610         }
2611
2612         kfree(plane_config->fb);
2613
2614         /*
2615          * Failed to alloc the obj, check to see if we should share
2616          * an fb with another CRTC instead
2617          */
2618         for_each_crtc(dev, c) {
2619                 i = to_intel_crtc(c);
2620
2621                 if (c == &intel_crtc->base)
2622                         continue;
2623
2624                 if (!i->active)
2625                         continue;
2626
2627                 fb = c->primary->fb;
2628                 if (!fb)
2629                         continue;
2630
2631                 obj = intel_fb_obj(fb);
2632                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633                         drm_framebuffer_reference(fb);
2634                         goto valid_fb;
2635                 }
2636         }
2637
2638         return;
2639
2640 valid_fb:
2641         obj = intel_fb_obj(fb);
2642         if (obj->tiling_mode != I915_TILING_NONE)
2643                 dev_priv->preserve_bios_swizzle = true;
2644
2645         primary->fb = fb;
2646         primary->crtc = primary->state->crtc = &intel_crtc->base;
2647         update_state_fb(primary);
2648         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2649         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2650 }
2651
2652 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653                                       struct drm_framebuffer *fb,
2654                                       int x, int y)
2655 {
2656         struct drm_device *dev = crtc->dev;
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2659         struct drm_plane *primary = crtc->primary;
2660         bool visible = to_intel_plane_state(primary->state)->visible;
2661         struct drm_i915_gem_object *obj;
2662         int plane = intel_crtc->plane;
2663         unsigned long linear_offset;
2664         u32 dspcntr;
2665         u32 reg = DSPCNTR(plane);
2666         int pixel_size;
2667
2668         if (!visible || !fb) {
2669                 I915_WRITE(reg, 0);
2670                 if (INTEL_INFO(dev)->gen >= 4)
2671                         I915_WRITE(DSPSURF(plane), 0);
2672                 else
2673                         I915_WRITE(DSPADDR(plane), 0);
2674                 POSTING_READ(reg);
2675                 return;
2676         }
2677
2678         obj = intel_fb_obj(fb);
2679         if (WARN_ON(obj == NULL))
2680                 return;
2681
2682         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
2684         dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
2686         dspcntr |= DISPLAY_PLANE_ENABLE;
2687
2688         if (INTEL_INFO(dev)->gen < 4) {
2689                 if (intel_crtc->pipe == PIPE_B)
2690                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692                 /* pipesrc and dspsize control the size that is scaled from,
2693                  * which should always be the user's requested size.
2694                  */
2695                 I915_WRITE(DSPSIZE(plane),
2696                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697                            (intel_crtc->config->pipe_src_w - 1));
2698                 I915_WRITE(DSPPOS(plane), 0);
2699         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700                 I915_WRITE(PRIMSIZE(plane),
2701                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702                            (intel_crtc->config->pipe_src_w - 1));
2703                 I915_WRITE(PRIMPOS(plane), 0);
2704                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2705         }
2706
2707         switch (fb->pixel_format) {
2708         case DRM_FORMAT_C8:
2709                 dspcntr |= DISPPLANE_8BPP;
2710                 break;
2711         case DRM_FORMAT_XRGB1555:
2712                 dspcntr |= DISPPLANE_BGRX555;
2713                 break;
2714         case DRM_FORMAT_RGB565:
2715                 dspcntr |= DISPPLANE_BGRX565;
2716                 break;
2717         case DRM_FORMAT_XRGB8888:
2718                 dspcntr |= DISPPLANE_BGRX888;
2719                 break;
2720         case DRM_FORMAT_XBGR8888:
2721                 dspcntr |= DISPPLANE_RGBX888;
2722                 break;
2723         case DRM_FORMAT_XRGB2101010:
2724                 dspcntr |= DISPPLANE_BGRX101010;
2725                 break;
2726         case DRM_FORMAT_XBGR2101010:
2727                 dspcntr |= DISPPLANE_RGBX101010;
2728                 break;
2729         default:
2730                 BUG();
2731         }
2732
2733         if (INTEL_INFO(dev)->gen >= 4 &&
2734             obj->tiling_mode != I915_TILING_NONE)
2735                 dspcntr |= DISPPLANE_TILED;
2736
2737         if (IS_G4X(dev))
2738                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
2740         linear_offset = y * fb->pitches[0] + x * pixel_size;
2741
2742         if (INTEL_INFO(dev)->gen >= 4) {
2743                 intel_crtc->dspaddr_offset =
2744                         intel_gen4_compute_page_offset(dev_priv,
2745                                                        &x, &y, obj->tiling_mode,
2746                                                        pixel_size,
2747                                                        fb->pitches[0]);
2748                 linear_offset -= intel_crtc->dspaddr_offset;
2749         } else {
2750                 intel_crtc->dspaddr_offset = linear_offset;
2751         }
2752
2753         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2754                 dspcntr |= DISPPLANE_ROTATE_180;
2755
2756                 x += (intel_crtc->config->pipe_src_w - 1);
2757                 y += (intel_crtc->config->pipe_src_h - 1);
2758
2759                 /* Finding the last pixel of the last line of the display
2760                 data and adding to linear_offset*/
2761                 linear_offset +=
2762                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2764         }
2765
2766         I915_WRITE(reg, dspcntr);
2767
2768         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769         if (INTEL_INFO(dev)->gen >= 4) {
2770                 I915_WRITE(DSPSURF(plane),
2771                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2772                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2773                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2774         } else
2775                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2776         POSTING_READ(reg);
2777 }
2778
2779 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780                                           struct drm_framebuffer *fb,
2781                                           int x, int y)
2782 {
2783         struct drm_device *dev = crtc->dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2786         struct drm_plane *primary = crtc->primary;
2787         bool visible = to_intel_plane_state(primary->state)->visible;
2788         struct drm_i915_gem_object *obj;
2789         int plane = intel_crtc->plane;
2790         unsigned long linear_offset;
2791         u32 dspcntr;
2792         u32 reg = DSPCNTR(plane);
2793         int pixel_size;
2794
2795         if (!visible || !fb) {
2796                 I915_WRITE(reg, 0);
2797                 I915_WRITE(DSPSURF(plane), 0);
2798                 POSTING_READ(reg);
2799                 return;
2800         }
2801
2802         obj = intel_fb_obj(fb);
2803         if (WARN_ON(obj == NULL))
2804                 return;
2805
2806         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
2808         dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
2810         dspcntr |= DISPLAY_PLANE_ENABLE;
2811
2812         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2814
2815         switch (fb->pixel_format) {
2816         case DRM_FORMAT_C8:
2817                 dspcntr |= DISPPLANE_8BPP;
2818                 break;
2819         case DRM_FORMAT_RGB565:
2820                 dspcntr |= DISPPLANE_BGRX565;
2821                 break;
2822         case DRM_FORMAT_XRGB8888:
2823                 dspcntr |= DISPPLANE_BGRX888;
2824                 break;
2825         case DRM_FORMAT_XBGR8888:
2826                 dspcntr |= DISPPLANE_RGBX888;
2827                 break;
2828         case DRM_FORMAT_XRGB2101010:
2829                 dspcntr |= DISPPLANE_BGRX101010;
2830                 break;
2831         case DRM_FORMAT_XBGR2101010:
2832                 dspcntr |= DISPPLANE_RGBX101010;
2833                 break;
2834         default:
2835                 BUG();
2836         }
2837
2838         if (obj->tiling_mode != I915_TILING_NONE)
2839                 dspcntr |= DISPPLANE_TILED;
2840
2841         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2842                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2843
2844         linear_offset = y * fb->pitches[0] + x * pixel_size;
2845         intel_crtc->dspaddr_offset =
2846                 intel_gen4_compute_page_offset(dev_priv,
2847                                                &x, &y, obj->tiling_mode,
2848                                                pixel_size,
2849                                                fb->pitches[0]);
2850         linear_offset -= intel_crtc->dspaddr_offset;
2851         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852                 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855                         x += (intel_crtc->config->pipe_src_w - 1);
2856                         y += (intel_crtc->config->pipe_src_h - 1);
2857
2858                         /* Finding the last pixel of the last line of the display
2859                         data and adding to linear_offset*/
2860                         linear_offset +=
2861                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863                 }
2864         }
2865
2866         I915_WRITE(reg, dspcntr);
2867
2868         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869         I915_WRITE(DSPSURF(plane),
2870                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873         } else {
2874                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876         }
2877         POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881                               uint32_t pixel_format)
2882 {
2883         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885         /*
2886          * The stride is either expressed as a multiple of 64 bytes
2887          * chunks for linear buffers or in number of tiles for tiled
2888          * buffers.
2889          */
2890         switch (fb_modifier) {
2891         case DRM_FORMAT_MOD_NONE:
2892                 return 64;
2893         case I915_FORMAT_MOD_X_TILED:
2894                 if (INTEL_INFO(dev)->gen == 2)
2895                         return 128;
2896                 return 512;
2897         case I915_FORMAT_MOD_Y_TILED:
2898                 /* No need to check for old gens and Y tiling since this is
2899                  * about the display engine and those will be blocked before
2900                  * we get here.
2901                  */
2902                 return 128;
2903         case I915_FORMAT_MOD_Yf_TILED:
2904                 if (bits_per_pixel == 8)
2905                         return 64;
2906                 else
2907                         return 128;
2908         default:
2909                 MISSING_CASE(fb_modifier);
2910                 return 64;
2911         }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915                                      struct drm_i915_gem_object *obj)
2916 {
2917         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920                 view = &i915_ggtt_view_rotated;
2921
2922         return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926  * This function detaches (aka. unbinds) unused scalers in hardware
2927  */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930         struct drm_device *dev;
2931         struct drm_i915_private *dev_priv;
2932         struct intel_crtc_scaler_state *scaler_state;
2933         int i;
2934
2935         if (!intel_crtc || !intel_crtc->config)
2936                 return;
2937
2938         dev = intel_crtc->base.dev;
2939         dev_priv = dev->dev_private;
2940         scaler_state = &intel_crtc->config->scaler_state;
2941
2942         /* loop through and disable scalers that aren't in use */
2943         for (i = 0; i < intel_crtc->num_scalers; i++) {
2944                 if (!scaler_state->scalers[i].in_use) {
2945                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950                 }
2951         }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956         switch (pixel_format) {
2957         case DRM_FORMAT_C8:
2958                 return PLANE_CTL_FORMAT_INDEXED;
2959         case DRM_FORMAT_RGB565:
2960                 return PLANE_CTL_FORMAT_RGB_565;
2961         case DRM_FORMAT_XBGR8888:
2962                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963         case DRM_FORMAT_XRGB8888:
2964                 return PLANE_CTL_FORMAT_XRGB_8888;
2965         /*
2966          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967          * to be already pre-multiplied. We need to add a knob (or a different
2968          * DRM_FORMAT) for user-space to configure that.
2969          */
2970         case DRM_FORMAT_ABGR8888:
2971                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2972                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2973         case DRM_FORMAT_ARGB8888:
2974                 return PLANE_CTL_FORMAT_XRGB_8888 |
2975                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976         case DRM_FORMAT_XRGB2101010:
2977                 return PLANE_CTL_FORMAT_XRGB_2101010;
2978         case DRM_FORMAT_XBGR2101010:
2979                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2980         case DRM_FORMAT_YUYV:
2981                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2982         case DRM_FORMAT_YVYU:
2983                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2984         case DRM_FORMAT_UYVY:
2985                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2986         case DRM_FORMAT_VYUY:
2987                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2988         default:
2989                 MISSING_CASE(pixel_format);
2990         }
2991
2992         return 0;
2993 }
2994
2995 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2996 {
2997         switch (fb_modifier) {
2998         case DRM_FORMAT_MOD_NONE:
2999                 break;
3000         case I915_FORMAT_MOD_X_TILED:
3001                 return PLANE_CTL_TILED_X;
3002         case I915_FORMAT_MOD_Y_TILED:
3003                 return PLANE_CTL_TILED_Y;
3004         case I915_FORMAT_MOD_Yf_TILED:
3005                 return PLANE_CTL_TILED_YF;
3006         default:
3007                 MISSING_CASE(fb_modifier);
3008         }
3009
3010         return 0;
3011 }
3012
3013 u32 skl_plane_ctl_rotation(unsigned int rotation)
3014 {
3015         switch (rotation) {
3016         case BIT(DRM_ROTATE_0):
3017                 break;
3018         /*
3019          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3020          * while i915 HW rotation is clockwise, thats why this swapping.
3021          */
3022         case BIT(DRM_ROTATE_90):
3023                 return PLANE_CTL_ROTATE_270;
3024         case BIT(DRM_ROTATE_180):
3025                 return PLANE_CTL_ROTATE_180;
3026         case BIT(DRM_ROTATE_270):
3027                 return PLANE_CTL_ROTATE_90;
3028         default:
3029                 MISSING_CASE(rotation);
3030         }
3031
3032         return 0;
3033 }
3034
3035 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3036                                          struct drm_framebuffer *fb,
3037                                          int x, int y)
3038 {
3039         struct drm_device *dev = crtc->dev;
3040         struct drm_i915_private *dev_priv = dev->dev_private;
3041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3042         struct drm_plane *plane = crtc->primary;
3043         bool visible = to_intel_plane_state(plane->state)->visible;
3044         struct drm_i915_gem_object *obj;
3045         int pipe = intel_crtc->pipe;
3046         u32 plane_ctl, stride_div, stride;
3047         u32 tile_height, plane_offset, plane_size;
3048         unsigned int rotation;
3049         int x_offset, y_offset;
3050         unsigned long surf_addr;
3051         struct intel_crtc_state *crtc_state = intel_crtc->config;
3052         struct intel_plane_state *plane_state;
3053         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3054         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3055         int scaler_id = -1;
3056
3057         plane_state = to_intel_plane_state(plane->state);
3058
3059         if (!visible || !fb) {
3060                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3061                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3062                 POSTING_READ(PLANE_CTL(pipe, 0));
3063                 return;
3064         }
3065
3066         plane_ctl = PLANE_CTL_ENABLE |
3067                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3068                     PLANE_CTL_PIPE_CSC_ENABLE;
3069
3070         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3071         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3072         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3073
3074         rotation = plane->state->rotation;
3075         plane_ctl |= skl_plane_ctl_rotation(rotation);
3076
3077         obj = intel_fb_obj(fb);
3078         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3079                                                fb->pixel_format);
3080         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3081
3082         /*
3083          * FIXME: intel_plane_state->src, dst aren't set when transitional
3084          * update_plane helpers are called from legacy paths.
3085          * Once full atomic crtc is available, below check can be avoided.
3086          */
3087         if (drm_rect_width(&plane_state->src)) {
3088                 scaler_id = plane_state->scaler_id;
3089                 src_x = plane_state->src.x1 >> 16;
3090                 src_y = plane_state->src.y1 >> 16;
3091                 src_w = drm_rect_width(&plane_state->src) >> 16;
3092                 src_h = drm_rect_height(&plane_state->src) >> 16;
3093                 dst_x = plane_state->dst.x1;
3094                 dst_y = plane_state->dst.y1;
3095                 dst_w = drm_rect_width(&plane_state->dst);
3096                 dst_h = drm_rect_height(&plane_state->dst);
3097
3098                 WARN_ON(x != src_x || y != src_y);
3099         } else {
3100                 src_w = intel_crtc->config->pipe_src_w;
3101                 src_h = intel_crtc->config->pipe_src_h;
3102         }
3103
3104         if (intel_rotation_90_or_270(rotation)) {
3105                 /* stride = Surface height in tiles */
3106                 tile_height = intel_tile_height(dev, fb->pixel_format,
3107                                                 fb->modifier[0]);
3108                 stride = DIV_ROUND_UP(fb->height, tile_height);
3109                 x_offset = stride * tile_height - y - src_h;
3110                 y_offset = x;
3111                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3112         } else {
3113                 stride = fb->pitches[0] / stride_div;
3114                 x_offset = x;
3115                 y_offset = y;
3116                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3117         }
3118         plane_offset = y_offset << 16 | x_offset;
3119
3120         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3121         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3122         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3123         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3124
3125         if (scaler_id >= 0) {
3126                 uint32_t ps_ctrl = 0;
3127
3128                 WARN_ON(!dst_w || !dst_h);
3129                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3130                         crtc_state->scaler_state.scalers[scaler_id].mode;
3131                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3132                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3133                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3134                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3135                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3136         } else {
3137                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3138         }
3139
3140         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3141
3142         POSTING_READ(PLANE_SURF(pipe, 0));
3143 }
3144
3145 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3146 static int
3147 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3148                            int x, int y, enum mode_set_atomic state)
3149 {
3150         struct drm_device *dev = crtc->dev;
3151         struct drm_i915_private *dev_priv = dev->dev_private;
3152
3153         if (dev_priv->display.disable_fbc)
3154                 dev_priv->display.disable_fbc(dev);
3155
3156         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3157
3158         return 0;
3159 }
3160
3161 static void intel_complete_page_flips(struct drm_device *dev)
3162 {
3163         struct drm_crtc *crtc;
3164
3165         for_each_crtc(dev, crtc) {
3166                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167                 enum plane plane = intel_crtc->plane;
3168
3169                 intel_prepare_page_flip(dev, plane);
3170                 intel_finish_page_flip_plane(dev, plane);
3171         }
3172 }
3173
3174 static void intel_update_primary_planes(struct drm_device *dev)
3175 {
3176         struct drm_i915_private *dev_priv = dev->dev_private;
3177         struct drm_crtc *crtc;
3178
3179         for_each_crtc(dev, crtc) {
3180                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181
3182                 drm_modeset_lock(&crtc->mutex, NULL);
3183                 /*
3184                  * FIXME: Once we have proper support for primary planes (and
3185                  * disabling them without disabling the entire crtc) allow again
3186                  * a NULL crtc->primary->fb.
3187                  */
3188                 if (intel_crtc->active && crtc->primary->fb)
3189                         dev_priv->display.update_primary_plane(crtc,
3190                                                                crtc->primary->fb,
3191                                                                crtc->x,
3192                                                                crtc->y);
3193                 drm_modeset_unlock(&crtc->mutex);
3194         }
3195 }
3196
3197 void intel_prepare_reset(struct drm_device *dev)
3198 {
3199         /* no reset support for gen2 */
3200         if (IS_GEN2(dev))
3201                 return;
3202
3203         /* reset doesn't touch the display */
3204         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3205                 return;
3206
3207         drm_modeset_lock_all(dev);
3208         /*
3209          * Disabling the crtcs gracefully seems nicer. Also the
3210          * g33 docs say we should at least disable all the planes.
3211          */
3212         intel_display_suspend(dev);
3213 }
3214
3215 void intel_finish_reset(struct drm_device *dev)
3216 {
3217         struct drm_i915_private *dev_priv = to_i915(dev);
3218
3219         /*
3220          * Flips in the rings will be nuked by the reset,
3221          * so complete all pending flips so that user space
3222          * will get its events and not get stuck.
3223          */
3224         intel_complete_page_flips(dev);
3225
3226         /* no reset support for gen2 */
3227         if (IS_GEN2(dev))
3228                 return;
3229
3230         /* reset doesn't touch the display */
3231         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3232                 /*
3233                  * Flips in the rings have been nuked by the reset,
3234                  * so update the base address of all primary
3235                  * planes to the the last fb to make sure we're
3236                  * showing the correct fb after a reset.
3237                  */
3238                 intel_update_primary_planes(dev);
3239                 return;
3240         }
3241
3242         /*
3243          * The display has been reset as well,
3244          * so need a full re-initialization.
3245          */
3246         intel_runtime_pm_disable_interrupts(dev_priv);
3247         intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249         intel_modeset_init_hw(dev);
3250
3251         spin_lock_irq(&dev_priv->irq_lock);
3252         if (dev_priv->display.hpd_irq_setup)
3253                 dev_priv->display.hpd_irq_setup(dev);
3254         spin_unlock_irq(&dev_priv->irq_lock);
3255
3256         intel_modeset_setup_hw_state(dev, true);
3257
3258         intel_hpd_init(dev_priv);
3259
3260         drm_modeset_unlock_all(dev);
3261 }
3262
3263 static void
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3265 {
3266         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268         bool was_interruptible = dev_priv->mm.interruptible;
3269         int ret;
3270
3271         /* Big Hammer, we also need to ensure that any pending
3272          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273          * current scanout is retired before unpinning the old
3274          * framebuffer. Note that we rely on userspace rendering
3275          * into the buffer attached to the pipe they are waiting
3276          * on. If not, userspace generates a GPU hang with IPEHR
3277          * point to the MI_WAIT_FOR_EVENT.
3278          *
3279          * This should only fail upon a hung GPU, in which case we
3280          * can safely continue.
3281          */
3282         dev_priv->mm.interruptible = false;
3283         ret = i915_gem_object_wait_rendering(obj, true);
3284         dev_priv->mm.interruptible = was_interruptible;
3285
3286         WARN_ON(ret);
3287 }
3288
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290 {
3291         struct drm_device *dev = crtc->dev;
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3294         bool pending;
3295
3296         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298                 return false;
3299
3300         spin_lock_irq(&dev->event_lock);
3301         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302         spin_unlock_irq(&dev->event_lock);
3303
3304         return pending;
3305 }
3306
3307 static void intel_update_pipe_size(struct intel_crtc *crtc)
3308 {
3309         struct drm_device *dev = crtc->base.dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311         const struct drm_display_mode *adjusted_mode;
3312
3313         if (!i915.fastboot)
3314                 return;
3315
3316         /*
3317          * Update pipe size and adjust fitter if needed: the reason for this is
3318          * that in compute_mode_changes we check the native mode (not the pfit
3319          * mode) to see if we can flip rather than do a full mode set. In the
3320          * fastboot case, we'll flip, but if we don't update the pipesrc and
3321          * pfit state, we'll end up with a big fb scanned out into the wrong
3322          * sized surface.
3323          *
3324          * To fix this properly, we need to hoist the checks up into
3325          * compute_mode_changes (or above), check the actual pfit state and
3326          * whether the platform allows pfit disable with pipe active, and only
3327          * then update the pipesrc and pfit state, even on the flip path.
3328          */
3329
3330         adjusted_mode = &crtc->config->base.adjusted_mode;
3331
3332         I915_WRITE(PIPESRC(crtc->pipe),
3333                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3334                    (adjusted_mode->crtc_vdisplay - 1));
3335         if (!crtc->config->pch_pfit.enabled &&
3336             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3337              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3338                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3339                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3340                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3341         }
3342         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3343         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3344 }
3345
3346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         int pipe = intel_crtc->pipe;
3352         u32 reg, temp;
3353
3354         /* enable normal train */
3355         reg = FDI_TX_CTL(pipe);
3356         temp = I915_READ(reg);
3357         if (IS_IVYBRIDGE(dev)) {
3358                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3359                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3360         } else {
3361                 temp &= ~FDI_LINK_TRAIN_NONE;
3362                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3363         }
3364         I915_WRITE(reg, temp);
3365
3366         reg = FDI_RX_CTL(pipe);
3367         temp = I915_READ(reg);
3368         if (HAS_PCH_CPT(dev)) {
3369                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3370                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3371         } else {
3372                 temp &= ~FDI_LINK_TRAIN_NONE;
3373                 temp |= FDI_LINK_TRAIN_NONE;
3374         }
3375         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3376
3377         /* wait one idle pattern time */
3378         POSTING_READ(reg);
3379         udelay(1000);
3380
3381         /* IVB wants error correction enabled */
3382         if (IS_IVYBRIDGE(dev))
3383                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3384                            FDI_FE_ERRC_ENABLE);
3385 }
3386
3387 /* The FDI link training functions for ILK/Ibexpeak. */
3388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3389 {
3390         struct drm_device *dev = crtc->dev;
3391         struct drm_i915_private *dev_priv = dev->dev_private;
3392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393         int pipe = intel_crtc->pipe;
3394         u32 reg, temp, tries;
3395
3396         /* FDI needs bits from pipe first */
3397         assert_pipe_enabled(dev_priv, pipe);
3398
3399         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3400            for train result */
3401         reg = FDI_RX_IMR(pipe);
3402         temp = I915_READ(reg);
3403         temp &= ~FDI_RX_SYMBOL_LOCK;
3404         temp &= ~FDI_RX_BIT_LOCK;
3405         I915_WRITE(reg, temp);
3406         I915_READ(reg);
3407         udelay(150);
3408
3409         /* enable CPU FDI TX and PCH FDI RX */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3413         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3414         temp &= ~FDI_LINK_TRAIN_NONE;
3415         temp |= FDI_LINK_TRAIN_PATTERN_1;
3416         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3417
3418         reg = FDI_RX_CTL(pipe);
3419         temp = I915_READ(reg);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3423
3424         POSTING_READ(reg);
3425         udelay(150);
3426
3427         /* Ironlake workaround, enable clock pointer after FDI enable*/
3428         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3429         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3430                    FDI_RX_PHASE_SYNC_POINTER_EN);
3431
3432         reg = FDI_RX_IIR(pipe);
3433         for (tries = 0; tries < 5; tries++) {
3434                 temp = I915_READ(reg);
3435                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3436
3437                 if ((temp & FDI_RX_BIT_LOCK)) {
3438                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3439                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3440                         break;
3441                 }
3442         }
3443         if (tries == 5)
3444                 DRM_ERROR("FDI train 1 fail!\n");
3445
3446         /* Train 2 */
3447         reg = FDI_TX_CTL(pipe);
3448         temp = I915_READ(reg);
3449         temp &= ~FDI_LINK_TRAIN_NONE;
3450         temp |= FDI_LINK_TRAIN_PATTERN_2;
3451         I915_WRITE(reg, temp);
3452
3453         reg = FDI_RX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         POSTING_READ(reg);
3460         udelay(150);
3461
3462         reg = FDI_RX_IIR(pipe);
3463         for (tries = 0; tries < 5; tries++) {
3464                 temp = I915_READ(reg);
3465                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467                 if (temp & FDI_RX_SYMBOL_LOCK) {
3468                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3469                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3470                         break;
3471                 }
3472         }
3473         if (tries == 5)
3474                 DRM_ERROR("FDI train 2 fail!\n");
3475
3476         DRM_DEBUG_KMS("FDI train done\n");
3477
3478 }
3479
3480 static const int snb_b_fdi_train_param[] = {
3481         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3482         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3483         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3484         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3485 };
3486
3487 /* The FDI link training functions for SNB/Cougarpoint. */
3488 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3489 {
3490         struct drm_device *dev = crtc->dev;
3491         struct drm_i915_private *dev_priv = dev->dev_private;
3492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493         int pipe = intel_crtc->pipe;
3494         u32 reg, temp, i, retry;
3495
3496         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3497            for train result */
3498         reg = FDI_RX_IMR(pipe);
3499         temp = I915_READ(reg);
3500         temp &= ~FDI_RX_SYMBOL_LOCK;
3501         temp &= ~FDI_RX_BIT_LOCK;
3502         I915_WRITE(reg, temp);
3503
3504         POSTING_READ(reg);
3505         udelay(150);
3506
3507         /* enable CPU FDI TX and PCH FDI RX */
3508         reg = FDI_TX_CTL(pipe);
3509         temp = I915_READ(reg);
3510         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3511         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3512         temp &= ~FDI_LINK_TRAIN_NONE;
3513         temp |= FDI_LINK_TRAIN_PATTERN_1;
3514         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3515         /* SNB-B */
3516         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3517         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3518
3519         I915_WRITE(FDI_RX_MISC(pipe),
3520                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3521
3522         reg = FDI_RX_CTL(pipe);
3523         temp = I915_READ(reg);
3524         if (HAS_PCH_CPT(dev)) {
3525                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3527         } else {
3528                 temp &= ~FDI_LINK_TRAIN_NONE;
3529                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3530         }
3531         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3532
3533         POSTING_READ(reg);
3534         udelay(150);
3535
3536         for (i = 0; i < 4; i++) {
3537                 reg = FDI_TX_CTL(pipe);
3538                 temp = I915_READ(reg);
3539                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540                 temp |= snb_b_fdi_train_param[i];
3541                 I915_WRITE(reg, temp);
3542
3543                 POSTING_READ(reg);
3544                 udelay(500);
3545
3546                 for (retry = 0; retry < 5; retry++) {
3547                         reg = FDI_RX_IIR(pipe);
3548                         temp = I915_READ(reg);
3549                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550                         if (temp & FDI_RX_BIT_LOCK) {
3551                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3553                                 break;
3554                         }
3555                         udelay(50);
3556                 }
3557                 if (retry < 5)
3558                         break;
3559         }
3560         if (i == 4)
3561                 DRM_ERROR("FDI train 1 fail!\n");
3562
3563         /* Train 2 */
3564         reg = FDI_TX_CTL(pipe);
3565         temp = I915_READ(reg);
3566         temp &= ~FDI_LINK_TRAIN_NONE;
3567         temp |= FDI_LINK_TRAIN_PATTERN_2;
3568         if (IS_GEN6(dev)) {
3569                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570                 /* SNB-B */
3571                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3572         }
3573         I915_WRITE(reg, temp);
3574
3575         reg = FDI_RX_CTL(pipe);
3576         temp = I915_READ(reg);
3577         if (HAS_PCH_CPT(dev)) {
3578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3580         } else {
3581                 temp &= ~FDI_LINK_TRAIN_NONE;
3582                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3583         }
3584         I915_WRITE(reg, temp);
3585
3586         POSTING_READ(reg);
3587         udelay(150);
3588
3589         for (i = 0; i < 4; i++) {
3590                 reg = FDI_TX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593                 temp |= snb_b_fdi_train_param[i];
3594                 I915_WRITE(reg, temp);
3595
3596                 POSTING_READ(reg);
3597                 udelay(500);
3598
3599                 for (retry = 0; retry < 5; retry++) {
3600                         reg = FDI_RX_IIR(pipe);
3601                         temp = I915_READ(reg);
3602                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603                         if (temp & FDI_RX_SYMBOL_LOCK) {
3604                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3605                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3606                                 break;
3607                         }
3608                         udelay(50);
3609                 }
3610                 if (retry < 5)
3611                         break;
3612         }
3613         if (i == 4)
3614                 DRM_ERROR("FDI train 2 fail!\n");
3615
3616         DRM_DEBUG_KMS("FDI train done.\n");
3617 }
3618
3619 /* Manual link training for Ivy Bridge A0 parts */
3620 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625         int pipe = intel_crtc->pipe;
3626         u32 reg, temp, i, j;
3627
3628         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3629            for train result */
3630         reg = FDI_RX_IMR(pipe);
3631         temp = I915_READ(reg);
3632         temp &= ~FDI_RX_SYMBOL_LOCK;
3633         temp &= ~FDI_RX_BIT_LOCK;
3634         I915_WRITE(reg, temp);
3635
3636         POSTING_READ(reg);
3637         udelay(150);
3638
3639         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3640                       I915_READ(FDI_RX_IIR(pipe)));
3641
3642         /* Try each vswing and preemphasis setting twice before moving on */
3643         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3644                 /* disable first in case we need to retry */
3645                 reg = FDI_TX_CTL(pipe);
3646                 temp = I915_READ(reg);
3647                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3648                 temp &= ~FDI_TX_ENABLE;
3649                 I915_WRITE(reg, temp);
3650
3651                 reg = FDI_RX_CTL(pipe);
3652                 temp = I915_READ(reg);
3653                 temp &= ~FDI_LINK_TRAIN_AUTO;
3654                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3655                 temp &= ~FDI_RX_ENABLE;
3656                 I915_WRITE(reg, temp);
3657
3658                 /* enable CPU FDI TX and PCH FDI RX */
3659                 reg = FDI_TX_CTL(pipe);
3660                 temp = I915_READ(reg);
3661                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3662                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3663                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3664                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3665                 temp |= snb_b_fdi_train_param[j/2];
3666                 temp |= FDI_COMPOSITE_SYNC;
3667                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3668
3669                 I915_WRITE(FDI_RX_MISC(pipe),
3670                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3671
3672                 reg = FDI_RX_CTL(pipe);
3673                 temp = I915_READ(reg);
3674                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3675                 temp |= FDI_COMPOSITE_SYNC;
3676                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3677
3678                 POSTING_READ(reg);
3679                 udelay(1); /* should be 0.5us */
3680
3681                 for (i = 0; i < 4; i++) {
3682                         reg = FDI_RX_IIR(pipe);
3683                         temp = I915_READ(reg);
3684                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3685
3686                         if (temp & FDI_RX_BIT_LOCK ||
3687                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3688                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3689                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3690                                               i);
3691                                 break;
3692                         }
3693                         udelay(1); /* should be 0.5us */
3694                 }
3695                 if (i == 4) {
3696                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3697                         continue;
3698                 }
3699
3700                 /* Train 2 */
3701                 reg = FDI_TX_CTL(pipe);
3702                 temp = I915_READ(reg);
3703                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3704                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3705                 I915_WRITE(reg, temp);
3706
3707                 reg = FDI_RX_CTL(pipe);
3708                 temp = I915_READ(reg);
3709                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3710                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3711                 I915_WRITE(reg, temp);
3712
3713                 POSTING_READ(reg);
3714                 udelay(2); /* should be 1.5us */
3715
3716                 for (i = 0; i < 4; i++) {
3717                         reg = FDI_RX_IIR(pipe);
3718                         temp = I915_READ(reg);
3719                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3720
3721                         if (temp & FDI_RX_SYMBOL_LOCK ||
3722                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3723                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3724                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3725                                               i);
3726                                 goto train_done;
3727                         }
3728                         udelay(2); /* should be 1.5us */
3729                 }
3730                 if (i == 4)
3731                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3732         }
3733
3734 train_done:
3735         DRM_DEBUG_KMS("FDI train done.\n");
3736 }
3737
3738 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3739 {
3740         struct drm_device *dev = intel_crtc->base.dev;
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745
3746         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3747         reg = FDI_RX_CTL(pipe);
3748         temp = I915_READ(reg);
3749         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3750         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3751         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3752         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3753
3754         POSTING_READ(reg);
3755         udelay(200);
3756
3757         /* Switch from Rawclk to PCDclk */
3758         temp = I915_READ(reg);
3759         I915_WRITE(reg, temp | FDI_PCDCLK);
3760
3761         POSTING_READ(reg);
3762         udelay(200);
3763
3764         /* Enable CPU FDI TX PLL, always on for Ironlake */
3765         reg = FDI_TX_CTL(pipe);
3766         temp = I915_READ(reg);
3767         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3768                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3769
3770                 POSTING_READ(reg);
3771                 udelay(100);
3772         }
3773 }
3774
3775 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3776 {
3777         struct drm_device *dev = intel_crtc->base.dev;
3778         struct drm_i915_private *dev_priv = dev->dev_private;
3779         int pipe = intel_crtc->pipe;
3780         u32 reg, temp;
3781
3782         /* Switch from PCDclk to Rawclk */
3783         reg = FDI_RX_CTL(pipe);
3784         temp = I915_READ(reg);
3785         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3786
3787         /* Disable CPU FDI TX PLL */
3788         reg = FDI_TX_CTL(pipe);
3789         temp = I915_READ(reg);
3790         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3791
3792         POSTING_READ(reg);
3793         udelay(100);
3794
3795         reg = FDI_RX_CTL(pipe);
3796         temp = I915_READ(reg);
3797         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3798
3799         /* Wait for the clocks to turn off. */
3800         POSTING_READ(reg);
3801         udelay(100);
3802 }
3803
3804 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3805 {
3806         struct drm_device *dev = crtc->dev;
3807         struct drm_i915_private *dev_priv = dev->dev_private;
3808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809         int pipe = intel_crtc->pipe;
3810         u32 reg, temp;
3811
3812         /* disable CPU FDI tx and PCH FDI rx */
3813         reg = FDI_TX_CTL(pipe);
3814         temp = I915_READ(reg);
3815         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3816         POSTING_READ(reg);
3817
3818         reg = FDI_RX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         temp &= ~(0x7 << 16);
3821         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3822         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3823
3824         POSTING_READ(reg);
3825         udelay(100);
3826
3827         /* Ironlake workaround, disable clock pointer after downing FDI */
3828         if (HAS_PCH_IBX(dev))
3829                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3830
3831         /* still set train pattern 1 */
3832         reg = FDI_TX_CTL(pipe);
3833         temp = I915_READ(reg);
3834         temp &= ~FDI_LINK_TRAIN_NONE;
3835         temp |= FDI_LINK_TRAIN_PATTERN_1;
3836         I915_WRITE(reg, temp);
3837
3838         reg = FDI_RX_CTL(pipe);
3839         temp = I915_READ(reg);
3840         if (HAS_PCH_CPT(dev)) {
3841                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3842                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3843         } else {
3844                 temp &= ~FDI_LINK_TRAIN_NONE;
3845                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3846         }
3847         /* BPC in FDI rx is consistent with that in PIPECONF */
3848         temp &= ~(0x07 << 16);
3849         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3850         I915_WRITE(reg, temp);
3851
3852         POSTING_READ(reg);
3853         udelay(100);
3854 }
3855
3856 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3857 {
3858         struct intel_crtc *crtc;
3859
3860         /* Note that we don't need to be called with mode_config.lock here
3861          * as our list of CRTC objects is static for the lifetime of the
3862          * device and so cannot disappear as we iterate. Similarly, we can
3863          * happily treat the predicates as racy, atomic checks as userspace
3864          * cannot claim and pin a new fb without at least acquring the
3865          * struct_mutex and so serialising with us.
3866          */
3867         for_each_intel_crtc(dev, crtc) {
3868                 if (atomic_read(&crtc->unpin_work_count) == 0)
3869                         continue;
3870
3871                 if (crtc->unpin_work)
3872                         intel_wait_for_vblank(dev, crtc->pipe);
3873
3874                 return true;
3875         }
3876
3877         return false;
3878 }
3879
3880 static void page_flip_completed(struct intel_crtc *intel_crtc)
3881 {
3882         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3883         struct intel_unpin_work *work = intel_crtc->unpin_work;
3884
3885         /* ensure that the unpin work is consistent wrt ->pending. */
3886         smp_rmb();
3887         intel_crtc->unpin_work = NULL;
3888
3889         if (work->event)
3890                 drm_send_vblank_event(intel_crtc->base.dev,
3891                                       intel_crtc->pipe,
3892                                       work->event);
3893
3894         drm_crtc_vblank_put(&intel_crtc->base);
3895
3896         wake_up_all(&dev_priv->pending_flip_queue);
3897         queue_work(dev_priv->wq, &work->work);
3898
3899         trace_i915_flip_complete(intel_crtc->plane,
3900                                  work->pending_flip_obj);
3901 }
3902
3903 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3904 {
3905         struct drm_device *dev = crtc->dev;
3906         struct drm_i915_private *dev_priv = dev->dev_private;
3907
3908         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3909         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3910                                        !intel_crtc_has_pending_flip(crtc),
3911                                        60*HZ) == 0)) {
3912                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3913
3914                 spin_lock_irq(&dev->event_lock);
3915                 if (intel_crtc->unpin_work) {
3916                         WARN_ONCE(1, "Removing stuck page flip\n");
3917                         page_flip_completed(intel_crtc);
3918                 }
3919                 spin_unlock_irq(&dev->event_lock);
3920         }
3921
3922         if (crtc->primary->fb) {
3923                 mutex_lock(&dev->struct_mutex);
3924                 intel_finish_fb(crtc->primary->fb);
3925                 mutex_unlock(&dev->struct_mutex);
3926         }
3927 }
3928
3929 /* Program iCLKIP clock to the desired frequency */
3930 static void lpt_program_iclkip(struct drm_crtc *crtc)
3931 {
3932         struct drm_device *dev = crtc->dev;
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3935         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3936         u32 temp;
3937
3938         mutex_lock(&dev_priv->sb_lock);
3939
3940         /* It is necessary to ungate the pixclk gate prior to programming
3941          * the divisors, and gate it back when it is done.
3942          */
3943         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3944
3945         /* Disable SSCCTL */
3946         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3947                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3948                                 SBI_SSCCTL_DISABLE,
3949                         SBI_ICLK);
3950
3951         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3952         if (clock == 20000) {
3953                 auxdiv = 1;
3954                 divsel = 0x41;
3955                 phaseinc = 0x20;
3956         } else {
3957                 /* The iCLK virtual clock root frequency is in MHz,
3958                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3959                  * divisors, it is necessary to divide one by another, so we
3960                  * convert the virtual clock precision to KHz here for higher
3961                  * precision.
3962                  */
3963                 u32 iclk_virtual_root_freq = 172800 * 1000;
3964                 u32 iclk_pi_range = 64;
3965                 u32 desired_divisor, msb_divisor_value, pi_value;
3966
3967                 desired_divisor = (iclk_virtual_root_freq / clock);
3968                 msb_divisor_value = desired_divisor / iclk_pi_range;
3969                 pi_value = desired_divisor % iclk_pi_range;
3970
3971                 auxdiv = 0;
3972                 divsel = msb_divisor_value - 2;
3973                 phaseinc = pi_value;
3974         }
3975
3976         /* This should not happen with any sane values */
3977         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3978                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3979         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3980                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3981
3982         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3983                         clock,
3984                         auxdiv,
3985                         divsel,
3986                         phasedir,
3987                         phaseinc);
3988
3989         /* Program SSCDIVINTPHASE6 */
3990         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3991         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3992         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3993         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3994         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3995         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3996         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3997         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3998
3999         /* Program SSCAUXDIV */
4000         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4001         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4002         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4003         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4004
4005         /* Enable modulator and associated divider */
4006         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4007         temp &= ~SBI_SSCCTL_DISABLE;
4008         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4009
4010         /* Wait for initialization time */
4011         udelay(24);
4012
4013         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4014
4015         mutex_unlock(&dev_priv->sb_lock);
4016 }
4017
4018 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4019                                                 enum pipe pch_transcoder)
4020 {
4021         struct drm_device *dev = crtc->base.dev;
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4024
4025         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4026                    I915_READ(HTOTAL(cpu_transcoder)));
4027         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4028                    I915_READ(HBLANK(cpu_transcoder)));
4029         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4030                    I915_READ(HSYNC(cpu_transcoder)));
4031
4032         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4033                    I915_READ(VTOTAL(cpu_transcoder)));
4034         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4035                    I915_READ(VBLANK(cpu_transcoder)));
4036         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4037                    I915_READ(VSYNC(cpu_transcoder)));
4038         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4039                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4040 }
4041
4042 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4043 {
4044         struct drm_i915_private *dev_priv = dev->dev_private;
4045         uint32_t temp;
4046
4047         temp = I915_READ(SOUTH_CHICKEN1);
4048         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4049                 return;
4050
4051         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4052         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4053
4054         temp &= ~FDI_BC_BIFURCATION_SELECT;
4055         if (enable)
4056                 temp |= FDI_BC_BIFURCATION_SELECT;
4057
4058         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4059         I915_WRITE(SOUTH_CHICKEN1, temp);
4060         POSTING_READ(SOUTH_CHICKEN1);
4061 }
4062
4063 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4064 {
4065         struct drm_device *dev = intel_crtc->base.dev;
4066
4067         switch (intel_crtc->pipe) {
4068         case PIPE_A:
4069                 break;
4070         case PIPE_B:
4071                 if (intel_crtc->config->fdi_lanes > 2)
4072                         cpt_set_fdi_bc_bifurcation(dev, false);
4073                 else
4074                         cpt_set_fdi_bc_bifurcation(dev, true);
4075
4076                 break;
4077         case PIPE_C:
4078                 cpt_set_fdi_bc_bifurcation(dev, true);
4079
4080                 break;
4081         default:
4082                 BUG();
4083         }
4084 }
4085
4086 /*
4087  * Enable PCH resources required for PCH ports:
4088  *   - PCH PLLs
4089  *   - FDI training & RX/TX
4090  *   - update transcoder timings
4091  *   - DP transcoding bits
4092  *   - transcoder
4093  */
4094 static void ironlake_pch_enable(struct drm_crtc *crtc)
4095 {
4096         struct drm_device *dev = crtc->dev;
4097         struct drm_i915_private *dev_priv = dev->dev_private;
4098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4099         int pipe = intel_crtc->pipe;
4100         u32 reg, temp;
4101
4102         assert_pch_transcoder_disabled(dev_priv, pipe);
4103
4104         if (IS_IVYBRIDGE(dev))
4105                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4106
4107         /* Write the TU size bits before fdi link training, so that error
4108          * detection works. */
4109         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4110                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4111
4112         /* For PCH output, training FDI link */
4113         dev_priv->display.fdi_link_train(crtc);
4114
4115         /* We need to program the right clock selection before writing the pixel
4116          * mutliplier into the DPLL. */
4117         if (HAS_PCH_CPT(dev)) {
4118                 u32 sel;
4119
4120                 temp = I915_READ(PCH_DPLL_SEL);
4121                 temp |= TRANS_DPLL_ENABLE(pipe);
4122                 sel = TRANS_DPLLB_SEL(pipe);
4123                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4124                         temp |= sel;
4125                 else
4126                         temp &= ~sel;
4127                 I915_WRITE(PCH_DPLL_SEL, temp);
4128         }
4129
4130         /* XXX: pch pll's can be enabled any time before we enable the PCH
4131          * transcoder, and we actually should do this to not upset any PCH
4132          * transcoder that already use the clock when we share it.
4133          *
4134          * Note that enable_shared_dpll tries to do the right thing, but
4135          * get_shared_dpll unconditionally resets the pll - we need that to have
4136          * the right LVDS enable sequence. */
4137         intel_enable_shared_dpll(intel_crtc);
4138
4139         /* set transcoder timing, panel must allow it */
4140         assert_panel_unlocked(dev_priv, pipe);
4141         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4142
4143         intel_fdi_normal_train(crtc);
4144
4145         /* For PCH DP, enable TRANS_DP_CTL */
4146         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4147                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4148                 reg = TRANS_DP_CTL(pipe);
4149                 temp = I915_READ(reg);
4150                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4151                           TRANS_DP_SYNC_MASK |
4152                           TRANS_DP_BPC_MASK);
4153                 temp |= TRANS_DP_OUTPUT_ENABLE;
4154                 temp |= bpc << 9; /* same format but at 11:9 */
4155
4156                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4157                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4158                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4159                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4160
4161                 switch (intel_trans_dp_port_sel(crtc)) {
4162                 case PCH_DP_B:
4163                         temp |= TRANS_DP_PORT_SEL_B;
4164                         break;
4165                 case PCH_DP_C:
4166                         temp |= TRANS_DP_PORT_SEL_C;
4167                         break;
4168                 case PCH_DP_D:
4169                         temp |= TRANS_DP_PORT_SEL_D;
4170                         break;
4171                 default:
4172                         BUG();
4173                 }
4174
4175                 I915_WRITE(reg, temp);
4176         }
4177
4178         ironlake_enable_pch_transcoder(dev_priv, pipe);
4179 }
4180
4181 static void lpt_pch_enable(struct drm_crtc *crtc)
4182 {
4183         struct drm_device *dev = crtc->dev;
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4187
4188         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4189
4190         lpt_program_iclkip(crtc);
4191
4192         /* Set transcoder timing. */
4193         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4194
4195         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4196 }
4197
4198 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4199                                                 struct intel_crtc_state *crtc_state)
4200 {
4201         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4202         struct intel_shared_dpll *pll;
4203         struct intel_shared_dpll_config *shared_dpll;
4204         enum intel_dpll_id i;
4205
4206         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4207
4208         if (HAS_PCH_IBX(dev_priv->dev)) {
4209                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4210                 i = (enum intel_dpll_id) crtc->pipe;
4211                 pll = &dev_priv->shared_dplls[i];
4212
4213                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4214                               crtc->base.base.id, pll->name);
4215
4216                 WARN_ON(shared_dpll[i].crtc_mask);
4217
4218                 goto found;
4219         }
4220
4221         if (IS_BROXTON(dev_priv->dev)) {
4222                 /* PLL is attached to port in bxt */
4223                 struct intel_encoder *encoder;
4224                 struct intel_digital_port *intel_dig_port;
4225
4226                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4227                 if (WARN_ON(!encoder))
4228                         return NULL;
4229
4230                 intel_dig_port = enc_to_dig_port(&encoder->base);
4231                 /* 1:1 mapping between ports and PLLs */
4232                 i = (enum intel_dpll_id)intel_dig_port->port;
4233                 pll = &dev_priv->shared_dplls[i];
4234                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4235                         crtc->base.base.id, pll->name);
4236                 WARN_ON(shared_dpll[i].crtc_mask);
4237
4238                 goto found;
4239         }
4240
4241         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4242                 pll = &dev_priv->shared_dplls[i];
4243
4244                 /* Only want to check enabled timings first */
4245                 if (shared_dpll[i].crtc_mask == 0)
4246                         continue;
4247
4248                 if (memcmp(&crtc_state->dpll_hw_state,
4249                            &shared_dpll[i].hw_state,
4250                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4251                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4252                                       crtc->base.base.id, pll->name,
4253                                       shared_dpll[i].crtc_mask,
4254                                       pll->active);
4255                         goto found;
4256                 }
4257         }
4258
4259         /* Ok no matching timings, maybe there's a free one? */
4260         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261                 pll = &dev_priv->shared_dplls[i];
4262                 if (shared_dpll[i].crtc_mask == 0) {
4263                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4264                                       crtc->base.base.id, pll->name);
4265                         goto found;
4266                 }
4267         }
4268
4269         return NULL;
4270
4271 found:
4272         if (shared_dpll[i].crtc_mask == 0)
4273                 shared_dpll[i].hw_state =
4274                         crtc_state->dpll_hw_state;
4275
4276         crtc_state->shared_dpll = i;
4277         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4278                          pipe_name(crtc->pipe));
4279
4280         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4281
4282         return pll;
4283 }
4284
4285 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4286 {
4287         struct drm_i915_private *dev_priv = to_i915(state->dev);
4288         struct intel_shared_dpll_config *shared_dpll;
4289         struct intel_shared_dpll *pll;
4290         enum intel_dpll_id i;
4291
4292         if (!to_intel_atomic_state(state)->dpll_set)
4293                 return;
4294
4295         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4296         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297                 pll = &dev_priv->shared_dplls[i];
4298                 pll->config = shared_dpll[i];
4299         }
4300 }
4301
4302 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4303 {
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         int dslreg = PIPEDSL(pipe);
4306         u32 temp;
4307
4308         temp = I915_READ(dslreg);
4309         udelay(500);
4310         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4311                 if (wait_for(I915_READ(dslreg) != temp, 5))
4312                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4313         }
4314 }
4315
4316 /**
4317  * skl_update_scaler_users - Stages update to crtc's scaler state
4318  * @intel_crtc: crtc
4319  * @crtc_state: crtc_state
4320  * @plane: plane (NULL indicates crtc is requesting update)
4321  * @plane_state: plane's state
4322  * @force_detach: request unconditional detachment of scaler
4323  *
4324  * This function updates scaler state for requested plane or crtc.
4325  * To request scaler usage update for a plane, caller shall pass plane pointer.
4326  * To request scaler usage update for crtc, caller shall pass plane pointer
4327  * as NULL.
4328  *
4329  * Return
4330  *     0 - scaler_usage updated successfully
4331  *    error - requested scaling cannot be supported or other error condition
4332  */
4333 int
4334 skl_update_scaler_users(
4335         struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4336         struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4337         int force_detach)
4338 {
4339         int need_scaling;
4340         int idx;
4341         int src_w, src_h, dst_w, dst_h;
4342         int *scaler_id;
4343         struct drm_framebuffer *fb;
4344         struct intel_crtc_scaler_state *scaler_state;
4345         unsigned int rotation;
4346
4347         if (!intel_crtc || !crtc_state)
4348                 return 0;
4349
4350         scaler_state = &crtc_state->scaler_state;
4351
4352         idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4353         fb = intel_plane ? plane_state->base.fb : NULL;
4354
4355         if (intel_plane) {
4356                 src_w = drm_rect_width(&plane_state->src) >> 16;
4357                 src_h = drm_rect_height(&plane_state->src) >> 16;
4358                 dst_w = drm_rect_width(&plane_state->dst);
4359                 dst_h = drm_rect_height(&plane_state->dst);
4360                 scaler_id = &plane_state->scaler_id;
4361                 rotation = plane_state->base.rotation;
4362         } else {
4363                 struct drm_display_mode *adjusted_mode =
4364                         &crtc_state->base.adjusted_mode;
4365                 src_w = crtc_state->pipe_src_w;
4366                 src_h = crtc_state->pipe_src_h;
4367                 dst_w = adjusted_mode->hdisplay;
4368                 dst_h = adjusted_mode->vdisplay;
4369                 scaler_id = &scaler_state->scaler_id;
4370                 rotation = DRM_ROTATE_0;
4371         }
4372
4373         need_scaling = intel_rotation_90_or_270(rotation) ?
4374                 (src_h != dst_w || src_w != dst_h):
4375                 (src_w != dst_w || src_h != dst_h);
4376
4377         /*
4378          * if plane is being disabled or scaler is no more required or force detach
4379          *  - free scaler binded to this plane/crtc
4380          *  - in order to do this, update crtc->scaler_usage
4381          *
4382          * Here scaler state in crtc_state is set free so that
4383          * scaler can be assigned to other user. Actual register
4384          * update to free the scaler is done in plane/panel-fit programming.
4385          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386          */
4387         if (force_detach || !need_scaling || (intel_plane &&
4388                 (!fb || !plane_state->visible))) {
4389                 if (*scaler_id >= 0) {
4390                         scaler_state->scaler_users &= ~(1 << idx);
4391                         scaler_state->scalers[*scaler_id].in_use = 0;
4392
4393                         DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4394                                 "crtc_state = %p scaler_users = 0x%x\n",
4395                                 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4396                                 intel_plane ? intel_plane->base.base.id :
4397                                 intel_crtc->base.base.id, crtc_state,
4398                                 scaler_state->scaler_users);
4399                         *scaler_id = -1;
4400                 }
4401                 return 0;
4402         }
4403
4404         /* range checks */
4405         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4406                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4407
4408                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4409                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4410                 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4411                         "size is out of scaler range\n",
4412                         intel_plane ? "PLANE" : "CRTC",
4413                         intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4414                         intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4415                 return -EINVAL;
4416         }
4417
4418         /* check colorkey */
4419         if (WARN_ON(intel_plane &&
4420                 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4421                 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4422                         intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
4423                 return -EINVAL;
4424         }
4425
4426         /* Check src format */
4427         if (intel_plane) {
4428                 switch (fb->pixel_format) {
4429                 case DRM_FORMAT_RGB565:
4430                 case DRM_FORMAT_XBGR8888:
4431                 case DRM_FORMAT_XRGB8888:
4432                 case DRM_FORMAT_ABGR8888:
4433                 case DRM_FORMAT_ARGB8888:
4434                 case DRM_FORMAT_XRGB2101010:
4435                 case DRM_FORMAT_XBGR2101010:
4436                 case DRM_FORMAT_YUYV:
4437                 case DRM_FORMAT_YVYU:
4438                 case DRM_FORMAT_UYVY:
4439                 case DRM_FORMAT_VYUY:
4440                         break;
4441                 default:
4442                         DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4443                                 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4444                         return -EINVAL;
4445                 }
4446         }
4447
4448         /* mark this plane as a scaler user in crtc_state */
4449         scaler_state->scaler_users |= (1 << idx);
4450         DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4451                 "crtc_state = %p scaler_users = 0x%x\n",
4452                 intel_plane ? "PLANE" : "CRTC",
4453                 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4454                 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4455         return 0;
4456 }
4457
4458 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4459 {
4460         struct drm_device *dev = crtc->base.dev;
4461         struct drm_i915_private *dev_priv = dev->dev_private;
4462         int pipe = crtc->pipe;
4463         struct intel_crtc_scaler_state *scaler_state =
4464                 &crtc->config->scaler_state;
4465
4466         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4467
4468         /* To update pfit, first update scaler state */
4469         skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4470         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4471         skl_detach_scalers(crtc);
4472         if (!enable)
4473                 return;
4474
4475         if (crtc->config->pch_pfit.enabled) {
4476                 int id;
4477
4478                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4479                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4480                         return;
4481                 }
4482
4483                 id = scaler_state->scaler_id;
4484                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4485                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4486                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4487                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4488
4489                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4490         }
4491 }
4492
4493 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4494 {
4495         struct drm_device *dev = crtc->base.dev;
4496         struct drm_i915_private *dev_priv = dev->dev_private;
4497         int pipe = crtc->pipe;
4498
4499         if (crtc->config->pch_pfit.enabled) {
4500                 /* Force use of hard-coded filter coefficients
4501                  * as some pre-programmed values are broken,
4502                  * e.g. x201.
4503                  */
4504                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4505                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4506                                                  PF_PIPE_SEL_IVB(pipe));
4507                 else
4508                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4509                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4510                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4511         }
4512 }
4513
4514 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4515 {
4516         struct drm_device *dev = crtc->dev;
4517         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4518         struct drm_plane *plane;
4519         struct intel_plane *intel_plane;
4520
4521         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4522                 intel_plane = to_intel_plane(plane);
4523                 if (intel_plane->pipe == pipe)
4524                         intel_plane_restore(&intel_plane->base);
4525         }
4526 }
4527
4528 void hsw_enable_ips(struct intel_crtc *crtc)
4529 {
4530         struct drm_device *dev = crtc->base.dev;
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532
4533         if (!crtc->config->ips_enabled)
4534                 return;
4535
4536         /* We can only enable IPS after we enable a plane and wait for a vblank */
4537         intel_wait_for_vblank(dev, crtc->pipe);
4538
4539         assert_plane_enabled(dev_priv, crtc->plane);
4540         if (IS_BROADWELL(dev)) {
4541                 mutex_lock(&dev_priv->rps.hw_lock);
4542                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4543                 mutex_unlock(&dev_priv->rps.hw_lock);
4544                 /* Quoting Art Runyan: "its not safe to expect any particular
4545                  * value in IPS_CTL bit 31 after enabling IPS through the
4546                  * mailbox." Moreover, the mailbox may return a bogus state,
4547                  * so we need to just enable it and continue on.
4548                  */
4549         } else {
4550                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4551                 /* The bit only becomes 1 in the next vblank, so this wait here
4552                  * is essentially intel_wait_for_vblank. If we don't have this
4553                  * and don't wait for vblanks until the end of crtc_enable, then
4554                  * the HW state readout code will complain that the expected
4555                  * IPS_CTL value is not the one we read. */
4556                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4557                         DRM_ERROR("Timed out waiting for IPS enable\n");
4558         }
4559 }
4560
4561 void hsw_disable_ips(struct intel_crtc *crtc)
4562 {
4563         struct drm_device *dev = crtc->base.dev;
4564         struct drm_i915_private *dev_priv = dev->dev_private;
4565
4566         if (!crtc->config->ips_enabled)
4567                 return;
4568
4569         assert_plane_enabled(dev_priv, crtc->plane);
4570         if (IS_BROADWELL(dev)) {
4571                 mutex_lock(&dev_priv->rps.hw_lock);
4572                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4573                 mutex_unlock(&dev_priv->rps.hw_lock);
4574                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4575                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4576                         DRM_ERROR("Timed out waiting for IPS disable\n");
4577         } else {
4578                 I915_WRITE(IPS_CTL, 0);
4579                 POSTING_READ(IPS_CTL);
4580         }
4581
4582         /* We need to wait for a vblank before we can disable the plane. */
4583         intel_wait_for_vblank(dev, crtc->pipe);
4584 }
4585
4586 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4587 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4588 {
4589         struct drm_device *dev = crtc->dev;
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592         enum pipe pipe = intel_crtc->pipe;
4593         int palreg = PALETTE(pipe);
4594         int i;
4595         bool reenable_ips = false;
4596
4597         /* The clocks have to be on to load the palette. */
4598         if (!crtc->state->active)
4599                 return;
4600
4601         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4602                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4603                         assert_dsi_pll_enabled(dev_priv);
4604                 else
4605                         assert_pll_enabled(dev_priv, pipe);
4606         }
4607
4608         /* use legacy palette for Ironlake */
4609         if (!HAS_GMCH_DISPLAY(dev))
4610                 palreg = LGC_PALETTE(pipe);
4611
4612         /* Workaround : Do not read or write the pipe palette/gamma data while
4613          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4614          */
4615         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4616             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4617              GAMMA_MODE_MODE_SPLIT)) {
4618                 hsw_disable_ips(intel_crtc);
4619                 reenable_ips = true;
4620         }
4621
4622         for (i = 0; i < 256; i++) {
4623                 I915_WRITE(palreg + 4 * i,
4624                            (intel_crtc->lut_r[i] << 16) |
4625                            (intel_crtc->lut_g[i] << 8) |
4626                            intel_crtc->lut_b[i]);
4627         }
4628
4629         if (reenable_ips)
4630                 hsw_enable_ips(intel_crtc);
4631 }
4632
4633 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4634 {
4635         if (intel_crtc->overlay) {
4636                 struct drm_device *dev = intel_crtc->base.dev;
4637                 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639                 mutex_lock(&dev->struct_mutex);
4640                 dev_priv->mm.interruptible = false;
4641                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4642                 dev_priv->mm.interruptible = true;
4643                 mutex_unlock(&dev->struct_mutex);
4644         }
4645
4646         /* Let userspace switch the overlay on again. In most cases userspace
4647          * has to recompute where to put it anyway.
4648          */
4649 }
4650
4651 /**
4652  * intel_post_enable_primary - Perform operations after enabling primary plane
4653  * @crtc: the CRTC whose primary plane was just enabled
4654  *
4655  * Performs potentially sleeping operations that must be done after the primary
4656  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4657  * called due to an explicit primary plane update, or due to an implicit
4658  * re-enable that is caused when a sprite plane is updated to no longer
4659  * completely hide the primary plane.
4660  */
4661 static void
4662 intel_post_enable_primary(struct drm_crtc *crtc)
4663 {
4664         struct drm_device *dev = crtc->dev;
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4667         int pipe = intel_crtc->pipe;
4668
4669         /*
4670          * BDW signals flip done immediately if the plane
4671          * is disabled, even if the plane enable is already
4672          * armed to occur at the next vblank :(
4673          */
4674         if (IS_BROADWELL(dev))
4675                 intel_wait_for_vblank(dev, pipe);
4676
4677         /*
4678          * FIXME IPS should be fine as long as one plane is
4679          * enabled, but in practice it seems to have problems
4680          * when going from primary only to sprite only and vice
4681          * versa.
4682          */
4683         hsw_enable_ips(intel_crtc);
4684
4685         mutex_lock(&dev->struct_mutex);
4686         intel_fbc_update(dev);
4687         mutex_unlock(&dev->struct_mutex);
4688
4689         /*
4690          * Gen2 reports pipe underruns whenever all planes are disabled.
4691          * So don't enable underrun reporting before at least some planes
4692          * are enabled.
4693          * FIXME: Need to fix the logic to work when we turn off all planes
4694          * but leave the pipe running.
4695          */
4696         if (IS_GEN2(dev))
4697                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699         /* Underruns don't raise interrupts, so check manually. */
4700         if (HAS_GMCH_DISPLAY(dev))
4701                 i9xx_check_fifo_underruns(dev_priv);
4702 }
4703
4704 /**
4705  * intel_pre_disable_primary - Perform operations before disabling primary plane
4706  * @crtc: the CRTC whose primary plane is to be disabled
4707  *
4708  * Performs potentially sleeping operations that must be done before the
4709  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4710  * be called due to an explicit primary plane update, or due to an implicit
4711  * disable that is caused when a sprite plane completely hides the primary
4712  * plane.
4713  */
4714 static void
4715 intel_pre_disable_primary(struct drm_crtc *crtc)
4716 {
4717         struct drm_device *dev = crtc->dev;
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720         int pipe = intel_crtc->pipe;
4721
4722         /*
4723          * Gen2 reports pipe underruns whenever all planes are disabled.
4724          * So diasble underrun reporting before all the planes get disabled.
4725          * FIXME: Need to fix the logic to work when we turn off all planes
4726          * but leave the pipe running.
4727          */
4728         if (IS_GEN2(dev))
4729                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4730
4731         /*
4732          * Vblank time updates from the shadow to live plane control register
4733          * are blocked if the memory self-refresh mode is active at that
4734          * moment. So to make sure the plane gets truly disabled, disable
4735          * first the self-refresh mode. The self-refresh enable bit in turn
4736          * will be checked/applied by the HW only at the next frame start
4737          * event which is after the vblank start event, so we need to have a
4738          * wait-for-vblank between disabling the plane and the pipe.
4739          */
4740         if (HAS_GMCH_DISPLAY(dev))
4741                 intel_set_memory_cxsr(dev_priv, false);
4742
4743         mutex_lock(&dev->struct_mutex);
4744         if (dev_priv->fbc.crtc == intel_crtc)
4745                 intel_fbc_disable(dev);
4746         mutex_unlock(&dev->struct_mutex);
4747
4748         /*
4749          * FIXME IPS should be fine as long as one plane is
4750          * enabled, but in practice it seems to have problems
4751          * when going from primary only to sprite only and vice
4752          * versa.
4753          */
4754         hsw_disable_ips(intel_crtc);
4755 }
4756
4757 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4758 {
4759         struct drm_device *dev = crtc->dev;
4760         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4761         int pipe = intel_crtc->pipe;
4762
4763         intel_enable_primary_hw_plane(crtc->primary, crtc);
4764         intel_enable_sprite_planes(crtc);
4765         if (to_intel_plane_state(crtc->cursor->state)->visible)
4766                 intel_crtc_update_cursor(crtc, true);
4767
4768         intel_post_enable_primary(crtc);
4769
4770         /*
4771          * FIXME: Once we grow proper nuclear flip support out of this we need
4772          * to compute the mask of flip planes precisely. For the time being
4773          * consider this a flip to a NULL plane.
4774          */
4775         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4776 }
4777
4778 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782         struct intel_plane *intel_plane;
4783         int pipe = intel_crtc->pipe;
4784
4785         intel_crtc_wait_for_pending_flips(crtc);
4786
4787         intel_pre_disable_primary(crtc);
4788
4789         intel_crtc_dpms_overlay_disable(intel_crtc);
4790         for_each_intel_plane(dev, intel_plane) {
4791                 if (intel_plane->pipe == pipe) {
4792                         struct drm_crtc *from = intel_plane->base.crtc;
4793
4794                         intel_plane->disable_plane(&intel_plane->base,
4795                                                    from ?: crtc, true);
4796                 }
4797         }
4798
4799         /*
4800          * FIXME: Once we grow proper nuclear flip support out of this we need
4801          * to compute the mask of flip planes precisely. For the time being
4802          * consider this a flip to a NULL plane.
4803          */
4804         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4805 }
4806
4807 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4808 {
4809         struct drm_device *dev = crtc->dev;
4810         struct drm_i915_private *dev_priv = dev->dev_private;
4811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812         struct intel_encoder *encoder;
4813         int pipe = intel_crtc->pipe;
4814
4815         if (WARN_ON(intel_crtc->active))
4816                 return;
4817
4818         if (intel_crtc->config->has_pch_encoder)
4819                 intel_prepare_shared_dpll(intel_crtc);
4820
4821         if (intel_crtc->config->has_dp_encoder)
4822                 intel_dp_set_m_n(intel_crtc, M1_N1);
4823
4824         intel_set_pipe_timings(intel_crtc);
4825
4826         if (intel_crtc->config->has_pch_encoder) {
4827                 intel_cpu_transcoder_set_m_n(intel_crtc,
4828                                      &intel_crtc->config->fdi_m_n, NULL);
4829         }
4830
4831         ironlake_set_pipeconf(crtc);
4832
4833         intel_crtc->active = true;
4834
4835         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4836         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4837
4838         for_each_encoder_on_crtc(dev, crtc, encoder)
4839                 if (encoder->pre_enable)
4840                         encoder->pre_enable(encoder);
4841
4842         if (intel_crtc->config->has_pch_encoder) {
4843                 /* Note: FDI PLL enabling _must_ be done before we enable the
4844                  * cpu pipes, hence this is separate from all the other fdi/pch
4845                  * enabling. */
4846                 ironlake_fdi_pll_enable(intel_crtc);
4847         } else {
4848                 assert_fdi_tx_disabled(dev_priv, pipe);
4849                 assert_fdi_rx_disabled(dev_priv, pipe);
4850         }
4851
4852         ironlake_pfit_enable(intel_crtc);
4853
4854         /*
4855          * On ILK+ LUT must be loaded before the pipe is running but with
4856          * clocks enabled
4857          */
4858         intel_crtc_load_lut(crtc);
4859
4860         intel_update_watermarks(crtc);
4861         intel_enable_pipe(intel_crtc);
4862
4863         if (intel_crtc->config->has_pch_encoder)
4864                 ironlake_pch_enable(crtc);
4865
4866         assert_vblank_disabled(crtc);
4867         drm_crtc_vblank_on(crtc);
4868
4869         for_each_encoder_on_crtc(dev, crtc, encoder)
4870                 encoder->enable(encoder);
4871
4872         if (HAS_PCH_CPT(dev))
4873                 cpt_verify_modeset(dev, intel_crtc->pipe);
4874 }
4875
4876 /* IPS only exists on ULT machines and is tied to pipe A. */
4877 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4878 {
4879         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4880 }
4881
4882 static void haswell_crtc_enable(struct drm_crtc *crtc)
4883 {
4884         struct drm_device *dev = crtc->dev;
4885         struct drm_i915_private *dev_priv = dev->dev_private;
4886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887         struct intel_encoder *encoder;
4888         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4889         struct intel_crtc_state *pipe_config =
4890                 to_intel_crtc_state(crtc->state);
4891
4892         if (WARN_ON(intel_crtc->active))
4893                 return;
4894
4895         if (intel_crtc_to_shared_dpll(intel_crtc))
4896                 intel_enable_shared_dpll(intel_crtc);
4897
4898         if (intel_crtc->config->has_dp_encoder)
4899                 intel_dp_set_m_n(intel_crtc, M1_N1);
4900
4901         intel_set_pipe_timings(intel_crtc);
4902
4903         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4904                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4905                            intel_crtc->config->pixel_multiplier - 1);
4906         }
4907
4908         if (intel_crtc->config->has_pch_encoder) {
4909                 intel_cpu_transcoder_set_m_n(intel_crtc,
4910                                      &intel_crtc->config->fdi_m_n, NULL);
4911         }
4912
4913         haswell_set_pipeconf(crtc);
4914
4915         intel_set_pipe_csc(crtc);
4916
4917         intel_crtc->active = true;
4918
4919         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4920         for_each_encoder_on_crtc(dev, crtc, encoder)
4921                 if (encoder->pre_enable)
4922                         encoder->pre_enable(encoder);
4923
4924         if (intel_crtc->config->has_pch_encoder) {
4925                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4926                                                       true);
4927                 dev_priv->display.fdi_link_train(crtc);
4928         }
4929
4930         intel_ddi_enable_pipe_clock(intel_crtc);
4931
4932         if (INTEL_INFO(dev)->gen == 9)
4933                 skylake_pfit_update(intel_crtc, 1);
4934         else if (INTEL_INFO(dev)->gen < 9)
4935                 ironlake_pfit_enable(intel_crtc);
4936         else
4937                 MISSING_CASE(INTEL_INFO(dev)->gen);
4938
4939         /*
4940          * On ILK+ LUT must be loaded before the pipe is running but with
4941          * clocks enabled
4942          */
4943         intel_crtc_load_lut(crtc);
4944
4945         intel_ddi_set_pipe_settings(crtc);
4946         intel_ddi_enable_transcoder_func(crtc);
4947
4948         intel_update_watermarks(crtc);
4949         intel_enable_pipe(intel_crtc);
4950
4951         if (intel_crtc->config->has_pch_encoder)
4952                 lpt_pch_enable(crtc);
4953
4954         if (intel_crtc->config->dp_encoder_is_mst)
4955                 intel_ddi_set_vc_payload_alloc(crtc, true);
4956
4957         assert_vblank_disabled(crtc);
4958         drm_crtc_vblank_on(crtc);
4959
4960         for_each_encoder_on_crtc(dev, crtc, encoder) {
4961                 encoder->enable(encoder);
4962                 intel_opregion_notify_encoder(encoder, true);
4963         }
4964
4965         /* If we change the relative order between pipe/planes enabling, we need
4966          * to change the workaround. */
4967         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4968         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4969                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4971         }
4972 }
4973
4974 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4975 {
4976         struct drm_device *dev = crtc->base.dev;
4977         struct drm_i915_private *dev_priv = dev->dev_private;
4978         int pipe = crtc->pipe;
4979
4980         /* To avoid upsetting the power well on haswell only disable the pfit if
4981          * it's in use. The hw state code will make sure we get this right. */
4982         if (crtc->config->pch_pfit.enabled) {
4983                 I915_WRITE(PF_CTL(pipe), 0);
4984                 I915_WRITE(PF_WIN_POS(pipe), 0);
4985                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4986         }
4987 }
4988
4989 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4990 {
4991         struct drm_device *dev = crtc->dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994         struct intel_encoder *encoder;
4995         int pipe = intel_crtc->pipe;
4996         u32 reg, temp;
4997
4998         if (WARN_ON(!intel_crtc->active))
4999                 return;
5000
5001         for_each_encoder_on_crtc(dev, crtc, encoder)
5002                 encoder->disable(encoder);
5003
5004         drm_crtc_vblank_off(crtc);
5005         assert_vblank_disabled(crtc);
5006
5007         if (intel_crtc->config->has_pch_encoder)
5008                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5009
5010         intel_disable_pipe(intel_crtc);
5011
5012         ironlake_pfit_disable(intel_crtc);
5013
5014         if (intel_crtc->config->has_pch_encoder)
5015                 ironlake_fdi_disable(crtc);
5016
5017         for_each_encoder_on_crtc(dev, crtc, encoder)
5018                 if (encoder->post_disable)
5019                         encoder->post_disable(encoder);
5020
5021         if (intel_crtc->config->has_pch_encoder) {
5022                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5023
5024                 if (HAS_PCH_CPT(dev)) {
5025                         /* disable TRANS_DP_CTL */
5026                         reg = TRANS_DP_CTL(pipe);
5027                         temp = I915_READ(reg);
5028                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5029                                   TRANS_DP_PORT_SEL_MASK);
5030                         temp |= TRANS_DP_PORT_SEL_NONE;
5031                         I915_WRITE(reg, temp);
5032
5033                         /* disable DPLL_SEL */
5034                         temp = I915_READ(PCH_DPLL_SEL);
5035                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5036                         I915_WRITE(PCH_DPLL_SEL, temp);
5037                 }
5038
5039                 /* disable PCH DPLL */
5040                 intel_disable_shared_dpll(intel_crtc);
5041
5042                 ironlake_fdi_pll_disable(intel_crtc);
5043         }
5044
5045         intel_crtc->active = false;
5046         intel_update_watermarks(crtc);
5047
5048         mutex_lock(&dev->struct_mutex);
5049         intel_fbc_update(dev);
5050         mutex_unlock(&dev->struct_mutex);
5051 }
5052
5053 static void haswell_crtc_disable(struct drm_crtc *crtc)
5054 {
5055         struct drm_device *dev = crtc->dev;
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058         struct intel_encoder *encoder;
5059         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5060
5061         if (WARN_ON(!intel_crtc->active))
5062                 return;
5063
5064         for_each_encoder_on_crtc(dev, crtc, encoder) {
5065                 intel_opregion_notify_encoder(encoder, false);
5066                 encoder->disable(encoder);
5067         }
5068
5069         drm_crtc_vblank_off(crtc);
5070         assert_vblank_disabled(crtc);
5071
5072         if (intel_crtc->config->has_pch_encoder)
5073                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5074                                                       false);
5075         intel_disable_pipe(intel_crtc);
5076
5077         if (intel_crtc->config->dp_encoder_is_mst)
5078                 intel_ddi_set_vc_payload_alloc(crtc, false);
5079
5080         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5081
5082         if (INTEL_INFO(dev)->gen == 9)
5083                 skylake_pfit_update(intel_crtc, 0);
5084         else if (INTEL_INFO(dev)->gen < 9)
5085                 ironlake_pfit_disable(intel_crtc);
5086         else
5087                 MISSING_CASE(INTEL_INFO(dev)->gen);
5088
5089         intel_ddi_disable_pipe_clock(intel_crtc);
5090
5091         if (intel_crtc->config->has_pch_encoder) {
5092                 lpt_disable_pch_transcoder(dev_priv);
5093                 intel_ddi_fdi_disable(crtc);
5094         }
5095
5096         for_each_encoder_on_crtc(dev, crtc, encoder)
5097                 if (encoder->post_disable)
5098                         encoder->post_disable(encoder);
5099
5100         intel_crtc->active = false;
5101         intel_update_watermarks(crtc);
5102
5103         mutex_lock(&dev->struct_mutex);
5104         intel_fbc_update(dev);
5105         mutex_unlock(&dev->struct_mutex);
5106
5107         if (intel_crtc_to_shared_dpll(intel_crtc))
5108                 intel_disable_shared_dpll(intel_crtc);
5109 }
5110
5111 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5112 {
5113         struct drm_device *dev = crtc->base.dev;
5114         struct drm_i915_private *dev_priv = dev->dev_private;
5115         struct intel_crtc_state *pipe_config = crtc->config;
5116
5117         if (!pipe_config->gmch_pfit.control)
5118                 return;
5119
5120         /*
5121          * The panel fitter should only be adjusted whilst the pipe is disabled,
5122          * according to register description and PRM.
5123          */
5124         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125         assert_pipe_disabled(dev_priv, crtc->pipe);
5126
5127         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5129
5130         /* Border color in case we don't scale up to the full screen. Black by
5131          * default, change to something else for debugging. */
5132         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 }
5134
5135 static enum intel_display_power_domain port_to_power_domain(enum port port)
5136 {
5137         switch (port) {
5138         case PORT_A:
5139                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5140         case PORT_B:
5141                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5142         case PORT_C:
5143                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5144         case PORT_D:
5145                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146         default:
5147                 WARN_ON_ONCE(1);
5148                 return POWER_DOMAIN_PORT_OTHER;
5149         }
5150 }
5151
5152 #define for_each_power_domain(domain, mask)                             \
5153         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5154                 if ((1 << (domain)) & (mask))
5155
5156 enum intel_display_power_domain
5157 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5158 {
5159         struct drm_device *dev = intel_encoder->base.dev;
5160         struct intel_digital_port *intel_dig_port;
5161
5162         switch (intel_encoder->type) {
5163         case INTEL_OUTPUT_UNKNOWN:
5164                 /* Only DDI platforms should ever use this output type */
5165                 WARN_ON_ONCE(!HAS_DDI(dev));
5166         case INTEL_OUTPUT_DISPLAYPORT:
5167         case INTEL_OUTPUT_HDMI:
5168         case INTEL_OUTPUT_EDP:
5169                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170                 return port_to_power_domain(intel_dig_port->port);
5171         case INTEL_OUTPUT_DP_MST:
5172                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173                 return port_to_power_domain(intel_dig_port->port);
5174         case INTEL_OUTPUT_ANALOG:
5175                 return POWER_DOMAIN_PORT_CRT;
5176         case INTEL_OUTPUT_DSI:
5177                 return POWER_DOMAIN_PORT_DSI;
5178         default:
5179                 return POWER_DOMAIN_PORT_OTHER;
5180         }
5181 }
5182
5183 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5184 {
5185         struct drm_device *dev = crtc->dev;
5186         struct intel_encoder *intel_encoder;
5187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188         enum pipe pipe = intel_crtc->pipe;
5189         unsigned long mask;
5190         enum transcoder transcoder;
5191
5192         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5193
5194         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5196         if (intel_crtc->config->pch_pfit.enabled ||
5197             intel_crtc->config->pch_pfit.force_thru)
5198                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5199
5200         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5201                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5202
5203         return mask;
5204 }
5205
5206 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5207 {
5208         struct drm_device *dev = state->dev;
5209         struct drm_i915_private *dev_priv = dev->dev_private;
5210         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5211         struct intel_crtc *crtc;
5212
5213         /*
5214          * First get all needed power domains, then put all unneeded, to avoid
5215          * any unnecessary toggling of the power wells.
5216          */
5217         for_each_intel_crtc(dev, crtc) {
5218                 enum intel_display_power_domain domain;
5219
5220                 if (!crtc->base.state->enable)
5221                         continue;
5222
5223                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5224
5225                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5226                         intel_display_power_get(dev_priv, domain);
5227         }
5228
5229         if (dev_priv->display.modeset_global_resources)
5230                 dev_priv->display.modeset_global_resources(state);
5231
5232         for_each_intel_crtc(dev, crtc) {
5233                 enum intel_display_power_domain domain;
5234
5235                 for_each_power_domain(domain, crtc->enabled_power_domains)
5236                         intel_display_power_put(dev_priv, domain);
5237
5238                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5239         }
5240
5241         intel_display_set_init_power(dev_priv, false);
5242 }
5243
5244 static void intel_update_max_cdclk(struct drm_device *dev)
5245 {
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248         if (IS_SKYLAKE(dev)) {
5249                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5250
5251                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5252                         dev_priv->max_cdclk_freq = 675000;
5253                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5254                         dev_priv->max_cdclk_freq = 540000;
5255                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5256                         dev_priv->max_cdclk_freq = 450000;
5257                 else
5258                         dev_priv->max_cdclk_freq = 337500;
5259         } else if (IS_BROADWELL(dev))  {
5260                 /*
5261                  * FIXME with extra cooling we can allow
5262                  * 540 MHz for ULX and 675 Mhz for ULT.
5263                  * How can we know if extra cooling is
5264                  * available? PCI ID, VTB, something else?
5265                  */
5266                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5267                         dev_priv->max_cdclk_freq = 450000;
5268                 else if (IS_BDW_ULX(dev))
5269                         dev_priv->max_cdclk_freq = 450000;
5270                 else if (IS_BDW_ULT(dev))
5271                         dev_priv->max_cdclk_freq = 540000;
5272                 else
5273                         dev_priv->max_cdclk_freq = 675000;
5274         } else if (IS_CHERRYVIEW(dev)) {
5275                 dev_priv->max_cdclk_freq = 320000;
5276         } else if (IS_VALLEYVIEW(dev)) {
5277                 dev_priv->max_cdclk_freq = 400000;
5278         } else {
5279                 /* otherwise assume cdclk is fixed */
5280                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5281         }
5282
5283         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5284                          dev_priv->max_cdclk_freq);
5285 }
5286
5287 static void intel_update_cdclk(struct drm_device *dev)
5288 {
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290
5291         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5292         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5293                          dev_priv->cdclk_freq);
5294
5295         /*
5296          * Program the gmbus_freq based on the cdclk frequency.
5297          * BSpec erroneously claims we should aim for 4MHz, but
5298          * in fact 1MHz is the correct frequency.
5299          */
5300         if (IS_VALLEYVIEW(dev)) {
5301                 /*
5302                  * Program the gmbus_freq based on the cdclk frequency.
5303                  * BSpec erroneously claims we should aim for 4MHz, but
5304                  * in fact 1MHz is the correct frequency.
5305                  */
5306                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5307         }
5308
5309         if (dev_priv->max_cdclk_freq == 0)
5310                 intel_update_max_cdclk(dev);
5311 }
5312
5313 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5314 {
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         uint32_t divider;
5317         uint32_t ratio;
5318         uint32_t current_freq;
5319         int ret;
5320
5321         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5322         switch (frequency) {
5323         case 144000:
5324                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5325                 ratio = BXT_DE_PLL_RATIO(60);
5326                 break;
5327         case 288000:
5328                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5329                 ratio = BXT_DE_PLL_RATIO(60);
5330                 break;
5331         case 384000:
5332                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5333                 ratio = BXT_DE_PLL_RATIO(60);
5334                 break;
5335         case 576000:
5336                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5337                 ratio = BXT_DE_PLL_RATIO(60);
5338                 break;
5339         case 624000:
5340                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5341                 ratio = BXT_DE_PLL_RATIO(65);
5342                 break;
5343         case 19200:
5344                 /*
5345                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5346                  * to suppress GCC warning.
5347                  */
5348                 ratio = 0;
5349                 divider = 0;
5350                 break;
5351         default:
5352                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5353
5354                 return;
5355         }
5356
5357         mutex_lock(&dev_priv->rps.hw_lock);
5358         /* Inform power controller of upcoming frequency change */
5359         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5360                                       0x80000000);
5361         mutex_unlock(&dev_priv->rps.hw_lock);
5362
5363         if (ret) {
5364                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5365                           ret, frequency);
5366                 return;
5367         }
5368
5369         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5370         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5371         current_freq = current_freq * 500 + 1000;
5372
5373         /*
5374          * DE PLL has to be disabled when
5375          * - setting to 19.2MHz (bypass, PLL isn't used)
5376          * - before setting to 624MHz (PLL needs toggling)
5377          * - before setting to any frequency from 624MHz (PLL needs toggling)
5378          */
5379         if (frequency == 19200 || frequency == 624000 ||
5380             current_freq == 624000) {
5381                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5382                 /* Timeout 200us */
5383                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5384                              1))
5385                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5386         }
5387
5388         if (frequency != 19200) {
5389                 uint32_t val;
5390
5391                 val = I915_READ(BXT_DE_PLL_CTL);
5392                 val &= ~BXT_DE_PLL_RATIO_MASK;
5393                 val |= ratio;
5394                 I915_WRITE(BXT_DE_PLL_CTL, val);
5395
5396                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5397                 /* Timeout 200us */
5398                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5399                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5400
5401                 val = I915_READ(CDCLK_CTL);
5402                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5403                 val |= divider;
5404                 /*
5405                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5406                  * enable otherwise.
5407                  */
5408                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409                 if (frequency >= 500000)
5410                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5411
5412                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5413                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5414                 val |= (frequency - 1000) / 500;
5415                 I915_WRITE(CDCLK_CTL, val);
5416         }
5417
5418         mutex_lock(&dev_priv->rps.hw_lock);
5419         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5420                                       DIV_ROUND_UP(frequency, 25000));
5421         mutex_unlock(&dev_priv->rps.hw_lock);
5422
5423         if (ret) {
5424                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5425                           ret, frequency);
5426                 return;
5427         }
5428
5429         intel_update_cdclk(dev);
5430 }
5431
5432 void broxton_init_cdclk(struct drm_device *dev)
5433 {
5434         struct drm_i915_private *dev_priv = dev->dev_private;
5435         uint32_t val;
5436
5437         /*
5438          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5439          * or else the reset will hang because there is no PCH to respond.
5440          * Move the handshake programming to initialization sequence.
5441          * Previously was left up to BIOS.
5442          */
5443         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5444         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5445         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5446
5447         /* Enable PG1 for cdclk */
5448         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5449
5450         /* check if cd clock is enabled */
5451         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5452                 DRM_DEBUG_KMS("Display already initialized\n");
5453                 return;
5454         }
5455
5456         /*
5457          * FIXME:
5458          * - The initial CDCLK needs to be read from VBT.
5459          *   Need to make this change after VBT has changes for BXT.
5460          * - check if setting the max (or any) cdclk freq is really necessary
5461          *   here, it belongs to modeset time
5462          */
5463         broxton_set_cdclk(dev, 624000);
5464
5465         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5466         POSTING_READ(DBUF_CTL);
5467
5468         udelay(10);
5469
5470         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5471                 DRM_ERROR("DBuf power enable timeout!\n");
5472 }
5473
5474 void broxton_uninit_cdclk(struct drm_device *dev)
5475 {
5476         struct drm_i915_private *dev_priv = dev->dev_private;
5477
5478         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5479         POSTING_READ(DBUF_CTL);
5480
5481         udelay(10);
5482
5483         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5484                 DRM_ERROR("DBuf power disable timeout!\n");
5485
5486         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5487         broxton_set_cdclk(dev, 19200);
5488
5489         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5490 }
5491
5492 static const struct skl_cdclk_entry {
5493         unsigned int freq;
5494         unsigned int vco;
5495 } skl_cdclk_frequencies[] = {
5496         { .freq = 308570, .vco = 8640 },
5497         { .freq = 337500, .vco = 8100 },
5498         { .freq = 432000, .vco = 8640 },
5499         { .freq = 450000, .vco = 8100 },
5500         { .freq = 540000, .vco = 8100 },
5501         { .freq = 617140, .vco = 8640 },
5502         { .freq = 675000, .vco = 8100 },
5503 };
5504
5505 static unsigned int skl_cdclk_decimal(unsigned int freq)
5506 {
5507         return (freq - 1000) / 500;
5508 }
5509
5510 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5511 {
5512         unsigned int i;
5513
5514         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5515                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5516
5517                 if (e->freq == freq)
5518                         return e->vco;
5519         }
5520
5521         return 8100;
5522 }
5523
5524 static void
5525 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5526 {
5527         unsigned int min_freq;
5528         u32 val;
5529
5530         /* select the minimum CDCLK before enabling DPLL 0 */
5531         val = I915_READ(CDCLK_CTL);
5532         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5533         val |= CDCLK_FREQ_337_308;
5534
5535         if (required_vco == 8640)
5536                 min_freq = 308570;
5537         else
5538                 min_freq = 337500;
5539
5540         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5541
5542         I915_WRITE(CDCLK_CTL, val);
5543         POSTING_READ(CDCLK_CTL);
5544
5545         /*
5546          * We always enable DPLL0 with the lowest link rate possible, but still
5547          * taking into account the VCO required to operate the eDP panel at the
5548          * desired frequency. The usual DP link rates operate with a VCO of
5549          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5550          * The modeset code is responsible for the selection of the exact link
5551          * rate later on, with the constraint of choosing a frequency that
5552          * works with required_vco.
5553          */
5554         val = I915_READ(DPLL_CTRL1);
5555
5556         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5557                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5558         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5559         if (required_vco == 8640)
5560                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5561                                             SKL_DPLL0);
5562         else
5563                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5564                                             SKL_DPLL0);
5565
5566         I915_WRITE(DPLL_CTRL1, val);
5567         POSTING_READ(DPLL_CTRL1);
5568
5569         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5570
5571         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5572                 DRM_ERROR("DPLL0 not locked\n");
5573 }
5574
5575 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5576 {
5577         int ret;
5578         u32 val;
5579
5580         /* inform PCU we want to change CDCLK */
5581         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5582         mutex_lock(&dev_priv->rps.hw_lock);
5583         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5584         mutex_unlock(&dev_priv->rps.hw_lock);
5585
5586         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5587 }
5588
5589 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5590 {
5591         unsigned int i;
5592
5593         for (i = 0; i < 15; i++) {
5594                 if (skl_cdclk_pcu_ready(dev_priv))
5595                         return true;
5596                 udelay(10);
5597         }
5598
5599         return false;
5600 }
5601
5602 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5603 {
5604         struct drm_device *dev = dev_priv->dev;
5605         u32 freq_select, pcu_ack;
5606
5607         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5608
5609         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5610                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5611                 return;
5612         }
5613
5614         /* set CDCLK_CTL */
5615         switch(freq) {
5616         case 450000:
5617         case 432000:
5618                 freq_select = CDCLK_FREQ_450_432;
5619                 pcu_ack = 1;
5620                 break;
5621         case 540000:
5622                 freq_select = CDCLK_FREQ_540;
5623                 pcu_ack = 2;
5624                 break;
5625         case 308570:
5626         case 337500:
5627         default:
5628                 freq_select = CDCLK_FREQ_337_308;
5629                 pcu_ack = 0;
5630                 break;
5631         case 617140:
5632         case 675000:
5633                 freq_select = CDCLK_FREQ_675_617;
5634                 pcu_ack = 3;
5635                 break;
5636         }
5637
5638         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5639         POSTING_READ(CDCLK_CTL);
5640
5641         /* inform PCU of the change */
5642         mutex_lock(&dev_priv->rps.hw_lock);
5643         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5644         mutex_unlock(&dev_priv->rps.hw_lock);
5645
5646         intel_update_cdclk(dev);
5647 }
5648
5649 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5650 {
5651         /* disable DBUF power */
5652         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5653         POSTING_READ(DBUF_CTL);
5654
5655         udelay(10);
5656
5657         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5658                 DRM_ERROR("DBuf power disable timeout\n");
5659
5660         /* disable DPLL0 */
5661         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5662         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5663                 DRM_ERROR("Couldn't disable DPLL0\n");
5664
5665         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5666 }
5667
5668 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5669 {
5670         u32 val;
5671         unsigned int required_vco;
5672
5673         /* enable PCH reset handshake */
5674         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5675         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5676
5677         /* enable PG1 and Misc I/O */
5678         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5679
5680         /* DPLL0 already enabed !? */
5681         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5682                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5683                 return;
5684         }
5685
5686         /* enable DPLL0 */
5687         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5688         skl_dpll0_enable(dev_priv, required_vco);
5689
5690         /* set CDCLK to the frequency the BIOS chose */
5691         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5692
5693         /* enable DBUF power */
5694         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5695         POSTING_READ(DBUF_CTL);
5696
5697         udelay(10);
5698
5699         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5700                 DRM_ERROR("DBuf power enable timeout\n");
5701 }
5702
5703 /* returns HPLL frequency in kHz */
5704 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5705 {
5706         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5707
5708         /* Obtain SKU information */
5709         mutex_lock(&dev_priv->sb_lock);
5710         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5711                 CCK_FUSE_HPLL_FREQ_MASK;
5712         mutex_unlock(&dev_priv->sb_lock);
5713
5714         return vco_freq[hpll_freq] * 1000;
5715 }
5716
5717 /* Adjust CDclk dividers to allow high res or save power if possible */
5718 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5719 {
5720         struct drm_i915_private *dev_priv = dev->dev_private;
5721         u32 val, cmd;
5722
5723         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5724                                         != dev_priv->cdclk_freq);
5725
5726         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5727                 cmd = 2;
5728         else if (cdclk == 266667)
5729                 cmd = 1;
5730         else
5731                 cmd = 0;
5732
5733         mutex_lock(&dev_priv->rps.hw_lock);
5734         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5735         val &= ~DSPFREQGUAR_MASK;
5736         val |= (cmd << DSPFREQGUAR_SHIFT);
5737         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5738         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5739                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5740                      50)) {
5741                 DRM_ERROR("timed out waiting for CDclk change\n");
5742         }
5743         mutex_unlock(&dev_priv->rps.hw_lock);
5744
5745         mutex_lock(&dev_priv->sb_lock);
5746
5747         if (cdclk == 400000) {
5748                 u32 divider;
5749
5750                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5751
5752                 /* adjust cdclk divider */
5753                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5754                 val &= ~DISPLAY_FREQUENCY_VALUES;
5755                 val |= divider;
5756                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5757
5758                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5759                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5760                              50))
5761                         DRM_ERROR("timed out waiting for CDclk change\n");
5762         }
5763
5764         /* adjust self-refresh exit latency value */
5765         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5766         val &= ~0x7f;
5767
5768         /*
5769          * For high bandwidth configs, we set a higher latency in the bunit
5770          * so that the core display fetch happens in time to avoid underruns.
5771          */
5772         if (cdclk == 400000)
5773                 val |= 4500 / 250; /* 4.5 usec */
5774         else
5775                 val |= 3000 / 250; /* 3.0 usec */
5776         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5777
5778         mutex_unlock(&dev_priv->sb_lock);
5779
5780         intel_update_cdclk(dev);
5781 }
5782
5783 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5784 {
5785         struct drm_i915_private *dev_priv = dev->dev_private;
5786         u32 val, cmd;
5787
5788         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5789                                                 != dev_priv->cdclk_freq);
5790
5791         switch (cdclk) {
5792         case 333333:
5793         case 320000:
5794         case 266667:
5795         case 200000:
5796                 break;
5797         default:
5798                 MISSING_CASE(cdclk);
5799                 return;
5800         }
5801
5802         /*
5803          * Specs are full of misinformation, but testing on actual
5804          * hardware has shown that we just need to write the desired
5805          * CCK divider into the Punit register.
5806          */
5807         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5808
5809         mutex_lock(&dev_priv->rps.hw_lock);
5810         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5811         val &= ~DSPFREQGUAR_MASK_CHV;
5812         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5813         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5814         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5815                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5816                      50)) {
5817                 DRM_ERROR("timed out waiting for CDclk change\n");
5818         }
5819         mutex_unlock(&dev_priv->rps.hw_lock);
5820
5821         intel_update_cdclk(dev);
5822 }
5823
5824 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5825                                  int max_pixclk)
5826 {
5827         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5828         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5829
5830         /*
5831          * Really only a few cases to deal with, as only 4 CDclks are supported:
5832          *   200MHz
5833          *   267MHz
5834          *   320/333MHz (depends on HPLL freq)
5835          *   400MHz (VLV only)
5836          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5837          * of the lower bin and adjust if needed.
5838          *
5839          * We seem to get an unstable or solid color picture at 200MHz.
5840          * Not sure what's wrong. For now use 200MHz only when all pipes
5841          * are off.
5842          */
5843         if (!IS_CHERRYVIEW(dev_priv) &&
5844             max_pixclk > freq_320*limit/100)
5845                 return 400000;
5846         else if (max_pixclk > 266667*limit/100)
5847                 return freq_320;
5848         else if (max_pixclk > 0)
5849                 return 266667;
5850         else
5851                 return 200000;
5852 }
5853
5854 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5855                               int max_pixclk)
5856 {
5857         /*
5858          * FIXME:
5859          * - remove the guardband, it's not needed on BXT
5860          * - set 19.2MHz bypass frequency if there are no active pipes
5861          */
5862         if (max_pixclk > 576000*9/10)
5863                 return 624000;
5864         else if (max_pixclk > 384000*9/10)
5865                 return 576000;
5866         else if (max_pixclk > 288000*9/10)
5867                 return 384000;
5868         else if (max_pixclk > 144000*9/10)
5869                 return 288000;
5870         else
5871                 return 144000;
5872 }
5873
5874 /* Compute the max pixel clock for new configuration. Uses atomic state if
5875  * that's non-NULL, look at current state otherwise. */
5876 static int intel_mode_max_pixclk(struct drm_device *dev,
5877                                  struct drm_atomic_state *state)
5878 {
5879         struct intel_crtc *intel_crtc;
5880         struct intel_crtc_state *crtc_state;
5881         int max_pixclk = 0;
5882
5883         for_each_intel_crtc(dev, intel_crtc) {
5884                 if (state)
5885                         crtc_state =
5886                                 intel_atomic_get_crtc_state(state, intel_crtc);
5887                 else
5888                         crtc_state = intel_crtc->config;
5889                 if (IS_ERR(crtc_state))
5890                         return PTR_ERR(crtc_state);
5891
5892                 if (!crtc_state->base.enable)
5893                         continue;
5894
5895                 max_pixclk = max(max_pixclk,
5896                                  crtc_state->base.adjusted_mode.crtc_clock);
5897         }
5898
5899         return max_pixclk;
5900 }
5901
5902 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5903 {
5904         struct drm_i915_private *dev_priv = to_i915(state->dev);
5905         struct drm_crtc *crtc;
5906         struct drm_crtc_state *crtc_state;
5907         int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5908         int cdclk, ret = 0;
5909
5910         if (max_pixclk < 0)
5911                 return max_pixclk;
5912
5913         if (IS_VALLEYVIEW(dev_priv))
5914                 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5915         else
5916                 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5917
5918         if (cdclk == dev_priv->cdclk_freq)
5919                 return 0;
5920
5921         /* add all active pipes to the state */
5922         for_each_crtc(state->dev, crtc) {
5923                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5924                 if (IS_ERR(crtc_state))
5925                         return PTR_ERR(crtc_state);
5926
5927                 if (!crtc_state->active || needs_modeset(crtc_state))
5928                         continue;
5929
5930                 crtc_state->mode_changed = true;
5931
5932                 ret = drm_atomic_add_affected_connectors(state, crtc);
5933                 if (ret)
5934                         break;
5935
5936                 ret = drm_atomic_add_affected_planes(state, crtc);
5937                 if (ret)
5938                         break;
5939         }
5940
5941         return ret;
5942 }
5943
5944 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5945 {
5946         unsigned int credits, default_credits;
5947
5948         if (IS_CHERRYVIEW(dev_priv))
5949                 default_credits = PFI_CREDIT(12);
5950         else
5951                 default_credits = PFI_CREDIT(8);
5952
5953         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5954                 /* CHV suggested value is 31 or 63 */
5955                 if (IS_CHERRYVIEW(dev_priv))
5956                         credits = PFI_CREDIT_63;
5957                 else
5958                         credits = PFI_CREDIT(15);
5959         } else {
5960                 credits = default_credits;
5961         }
5962
5963         /*
5964          * WA - write default credits before re-programming
5965          * FIXME: should we also set the resend bit here?
5966          */
5967         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5968                    default_credits);
5969
5970         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5971                    credits | PFI_CREDIT_RESEND);
5972
5973         /*
5974          * FIXME is this guaranteed to clear
5975          * immediately or should we poll for it?
5976          */
5977         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5978 }
5979
5980 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5981 {
5982         struct drm_device *dev = old_state->dev;
5983         struct drm_i915_private *dev_priv = dev->dev_private;
5984         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5985         int req_cdclk;
5986
5987         /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5988          * never fail. */
5989         if (WARN_ON(max_pixclk < 0))
5990                 return;
5991
5992         req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5993
5994         if (req_cdclk != dev_priv->cdclk_freq) {
5995                 /*
5996                  * FIXME: We can end up here with all power domains off, yet
5997                  * with a CDCLK frequency other than the minimum. To account
5998                  * for this take the PIPE-A power domain, which covers the HW
5999                  * blocks needed for the following programming. This can be
6000                  * removed once it's guaranteed that we get here either with
6001                  * the minimum CDCLK set, or the required power domains
6002                  * enabled.
6003                  */
6004                 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6005
6006                 if (IS_CHERRYVIEW(dev))
6007                         cherryview_set_cdclk(dev, req_cdclk);
6008                 else
6009                         valleyview_set_cdclk(dev, req_cdclk);
6010
6011                 vlv_program_pfi_credits(dev_priv);
6012
6013                 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6014         }
6015 }
6016
6017 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6018 {
6019         struct drm_device *dev = crtc->dev;
6020         struct drm_i915_private *dev_priv = to_i915(dev);
6021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6022         struct intel_encoder *encoder;
6023         int pipe = intel_crtc->pipe;
6024         bool is_dsi;
6025
6026         if (WARN_ON(intel_crtc->active))
6027                 return;
6028
6029         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6030
6031         if (!is_dsi) {
6032                 if (IS_CHERRYVIEW(dev))
6033                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6034                 else
6035                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6036         }
6037
6038         if (intel_crtc->config->has_dp_encoder)
6039                 intel_dp_set_m_n(intel_crtc, M1_N1);
6040
6041         intel_set_pipe_timings(intel_crtc);
6042
6043         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6044                 struct drm_i915_private *dev_priv = dev->dev_private;
6045
6046                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6047                 I915_WRITE(CHV_CANVAS(pipe), 0);
6048         }
6049
6050         i9xx_set_pipeconf(intel_crtc);
6051
6052         intel_crtc->active = true;
6053
6054         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6055
6056         for_each_encoder_on_crtc(dev, crtc, encoder)
6057                 if (encoder->pre_pll_enable)
6058                         encoder->pre_pll_enable(encoder);
6059
6060         if (!is_dsi) {
6061                 if (IS_CHERRYVIEW(dev))
6062                         chv_enable_pll(intel_crtc, intel_crtc->config);
6063                 else
6064                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6065         }
6066
6067         for_each_encoder_on_crtc(dev, crtc, encoder)
6068                 if (encoder->pre_enable)
6069                         encoder->pre_enable(encoder);
6070
6071         i9xx_pfit_enable(intel_crtc);
6072
6073         intel_crtc_load_lut(crtc);
6074
6075         intel_update_watermarks(crtc);
6076         intel_enable_pipe(intel_crtc);
6077
6078         assert_vblank_disabled(crtc);
6079         drm_crtc_vblank_on(crtc);
6080
6081         for_each_encoder_on_crtc(dev, crtc, encoder)
6082                 encoder->enable(encoder);
6083 }
6084
6085 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6086 {
6087         struct drm_device *dev = crtc->base.dev;
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089
6090         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6091         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6092 }
6093
6094 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6095 {
6096         struct drm_device *dev = crtc->dev;
6097         struct drm_i915_private *dev_priv = to_i915(dev);
6098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099         struct intel_encoder *encoder;
6100         int pipe = intel_crtc->pipe;
6101
6102         if (WARN_ON(intel_crtc->active))
6103                 return;
6104
6105         i9xx_set_pll_dividers(intel_crtc);
6106
6107         if (intel_crtc->config->has_dp_encoder)
6108                 intel_dp_set_m_n(intel_crtc, M1_N1);
6109
6110         intel_set_pipe_timings(intel_crtc);
6111
6112         i9xx_set_pipeconf(intel_crtc);
6113
6114         intel_crtc->active = true;
6115
6116         if (!IS_GEN2(dev))
6117                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6118
6119         for_each_encoder_on_crtc(dev, crtc, encoder)
6120                 if (encoder->pre_enable)
6121                         encoder->pre_enable(encoder);
6122
6123         i9xx_enable_pll(intel_crtc);
6124
6125         i9xx_pfit_enable(intel_crtc);
6126
6127         intel_crtc_load_lut(crtc);
6128
6129         intel_update_watermarks(crtc);
6130         intel_enable_pipe(intel_crtc);
6131
6132         assert_vblank_disabled(crtc);
6133         drm_crtc_vblank_on(crtc);
6134
6135         for_each_encoder_on_crtc(dev, crtc, encoder)
6136                 encoder->enable(encoder);
6137 }
6138
6139 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6140 {
6141         struct drm_device *dev = crtc->base.dev;
6142         struct drm_i915_private *dev_priv = dev->dev_private;
6143
6144         if (!crtc->config->gmch_pfit.control)
6145                 return;
6146
6147         assert_pipe_disabled(dev_priv, crtc->pipe);
6148
6149         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6150                          I915_READ(PFIT_CONTROL));
6151         I915_WRITE(PFIT_CONTROL, 0);
6152 }
6153
6154 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6155 {
6156         struct drm_device *dev = crtc->dev;
6157         struct drm_i915_private *dev_priv = dev->dev_private;
6158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159         struct intel_encoder *encoder;
6160         int pipe = intel_crtc->pipe;
6161
6162         if (WARN_ON(!intel_crtc->active))
6163                 return;
6164
6165         /*
6166          * On gen2 planes are double buffered but the pipe isn't, so we must
6167          * wait for planes to fully turn off before disabling the pipe.
6168          * We also need to wait on all gmch platforms because of the
6169          * self-refresh mode constraint explained above.
6170          */
6171         intel_wait_for_vblank(dev, pipe);
6172
6173         for_each_encoder_on_crtc(dev, crtc, encoder)
6174                 encoder->disable(encoder);
6175
6176         drm_crtc_vblank_off(crtc);
6177         assert_vblank_disabled(crtc);
6178
6179         intel_disable_pipe(intel_crtc);
6180
6181         i9xx_pfit_disable(intel_crtc);
6182
6183         for_each_encoder_on_crtc(dev, crtc, encoder)
6184                 if (encoder->post_disable)
6185                         encoder->post_disable(encoder);
6186
6187         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6188                 if (IS_CHERRYVIEW(dev))
6189                         chv_disable_pll(dev_priv, pipe);
6190                 else if (IS_VALLEYVIEW(dev))
6191                         vlv_disable_pll(dev_priv, pipe);
6192                 else
6193                         i9xx_disable_pll(intel_crtc);
6194         }
6195
6196         if (!IS_GEN2(dev))
6197                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6198
6199         intel_crtc->active = false;
6200         intel_update_watermarks(crtc);
6201
6202         mutex_lock(&dev->struct_mutex);
6203         intel_fbc_update(dev);
6204         mutex_unlock(&dev->struct_mutex);
6205 }
6206
6207 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6208 {
6209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6211         enum intel_display_power_domain domain;
6212         unsigned long domains;
6213
6214         if (!intel_crtc->active)
6215                 return;
6216
6217         intel_crtc_disable_planes(crtc);
6218         dev_priv->display.crtc_disable(crtc);
6219
6220         domains = intel_crtc->enabled_power_domains;
6221         for_each_power_domain(domain, domains)
6222                 intel_display_power_put(dev_priv, domain);
6223         intel_crtc->enabled_power_domains = 0;
6224 }
6225
6226 /*
6227  * turn all crtc's off, but do not adjust state
6228  * This has to be paired with a call to intel_modeset_setup_hw_state.
6229  */
6230 void intel_display_suspend(struct drm_device *dev)
6231 {
6232         struct drm_crtc *crtc;
6233
6234         for_each_crtc(dev, crtc)
6235                 intel_crtc_disable_noatomic(crtc);
6236 }
6237
6238 /* Master function to enable/disable CRTC and corresponding power wells */
6239 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6240 {
6241         struct drm_device *dev = crtc->dev;
6242         struct drm_mode_config *config = &dev->mode_config;
6243         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6245         struct intel_crtc_state *pipe_config;
6246         struct drm_atomic_state *state;
6247         int ret;
6248
6249         if (enable == intel_crtc->active)
6250                 return 0;
6251
6252         if (enable && !crtc->state->enable)
6253                 return 0;
6254
6255         /* this function should be called with drm_modeset_lock_all for now */
6256         if (WARN_ON(!ctx))
6257                 return -EIO;
6258         lockdep_assert_held(&ctx->ww_ctx);
6259
6260         state = drm_atomic_state_alloc(dev);
6261         if (WARN_ON(!state))
6262                 return -ENOMEM;
6263
6264         state->acquire_ctx = ctx;
6265         state->allow_modeset = true;
6266
6267         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6268         if (IS_ERR(pipe_config)) {
6269                 ret = PTR_ERR(pipe_config);
6270                 goto err;
6271         }
6272         pipe_config->base.active = enable;
6273
6274         ret = intel_set_mode(state);
6275         if (!ret)
6276                 return ret;
6277
6278 err:
6279         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6280         drm_atomic_state_free(state);
6281         return ret;
6282 }
6283
6284 /**
6285  * Sets the power management mode of the pipe and plane.
6286  */
6287 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6288 {
6289         struct drm_device *dev = crtc->dev;
6290         struct intel_encoder *intel_encoder;
6291         bool enable = false;
6292
6293         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6294                 enable |= intel_encoder->connectors_active;
6295
6296         intel_crtc_control(crtc, enable);
6297 }
6298
6299 void intel_encoder_destroy(struct drm_encoder *encoder)
6300 {
6301         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6302
6303         drm_encoder_cleanup(encoder);
6304         kfree(intel_encoder);
6305 }
6306
6307 /* Simple dpms helper for encoders with just one connector, no cloning and only
6308  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6309  * state of the entire output pipe. */
6310 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6311 {
6312         if (mode == DRM_MODE_DPMS_ON) {
6313                 encoder->connectors_active = true;
6314
6315                 intel_crtc_update_dpms(encoder->base.crtc);
6316         } else {
6317                 encoder->connectors_active = false;
6318
6319                 intel_crtc_update_dpms(encoder->base.crtc);
6320         }
6321 }
6322
6323 /* Cross check the actual hw state with our own modeset state tracking (and it's
6324  * internal consistency). */
6325 static void intel_connector_check_state(struct intel_connector *connector)
6326 {
6327         if (connector->get_hw_state(connector)) {
6328                 struct intel_encoder *encoder = connector->encoder;
6329                 struct drm_crtc *crtc;
6330                 bool encoder_enabled;
6331                 enum pipe pipe;
6332
6333                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6334                               connector->base.base.id,
6335                               connector->base.name);
6336
6337                 /* there is no real hw state for MST connectors */
6338                 if (connector->mst_port)
6339                         return;
6340
6341                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6342                      "wrong connector dpms state\n");
6343                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6344                      "active connector not linked to encoder\n");
6345
6346                 if (encoder) {
6347                         I915_STATE_WARN(!encoder->connectors_active,
6348                              "encoder->connectors_active not set\n");
6349
6350                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6351                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6352                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6353                                 return;
6354
6355                         crtc = encoder->base.crtc;
6356
6357                         I915_STATE_WARN(!crtc->state->enable,
6358                                         "crtc not enabled\n");
6359                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6360                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6361                              "encoder active on the wrong pipe\n");
6362                 }
6363         }
6364 }
6365
6366 int intel_connector_init(struct intel_connector *connector)
6367 {
6368         struct drm_connector_state *connector_state;
6369
6370         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6371         if (!connector_state)
6372                 return -ENOMEM;
6373
6374         connector->base.state = connector_state;
6375         return 0;
6376 }
6377
6378 struct intel_connector *intel_connector_alloc(void)
6379 {
6380         struct intel_connector *connector;
6381
6382         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6383         if (!connector)
6384                 return NULL;
6385
6386         if (intel_connector_init(connector) < 0) {
6387                 kfree(connector);
6388                 return NULL;
6389         }
6390
6391         return connector;
6392 }
6393
6394 /* Even simpler default implementation, if there's really no special case to
6395  * consider. */
6396 void intel_connector_dpms(struct drm_connector *connector, int mode)
6397 {
6398         /* All the simple cases only support two dpms states. */
6399         if (mode != DRM_MODE_DPMS_ON)
6400                 mode = DRM_MODE_DPMS_OFF;
6401
6402         if (mode == connector->dpms)
6403                 return;
6404
6405         connector->dpms = mode;
6406
6407         /* Only need to change hw state when actually enabled */
6408         if (connector->encoder)
6409                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6410
6411         intel_modeset_check_state(connector->dev);
6412 }
6413
6414 /* Simple connector->get_hw_state implementation for encoders that support only
6415  * one connector and no cloning and hence the encoder state determines the state
6416  * of the connector. */
6417 bool intel_connector_get_hw_state(struct intel_connector *connector)
6418 {
6419         enum pipe pipe = 0;
6420         struct intel_encoder *encoder = connector->encoder;
6421
6422         return encoder->get_hw_state(encoder, &pipe);
6423 }
6424
6425 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6426 {
6427         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6428                 return crtc_state->fdi_lanes;
6429
6430         return 0;
6431 }
6432
6433 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6434                                      struct intel_crtc_state *pipe_config)
6435 {
6436         struct drm_atomic_state *state = pipe_config->base.state;
6437         struct intel_crtc *other_crtc;
6438         struct intel_crtc_state *other_crtc_state;
6439
6440         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6441                       pipe_name(pipe), pipe_config->fdi_lanes);
6442         if (pipe_config->fdi_lanes > 4) {
6443                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6444                               pipe_name(pipe), pipe_config->fdi_lanes);
6445                 return -EINVAL;
6446         }
6447
6448         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6449                 if (pipe_config->fdi_lanes > 2) {
6450                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6451                                       pipe_config->fdi_lanes);
6452                         return -EINVAL;
6453                 } else {
6454                         return 0;
6455                 }
6456         }
6457
6458         if (INTEL_INFO(dev)->num_pipes == 2)
6459                 return 0;
6460
6461         /* Ivybridge 3 pipe is really complicated */
6462         switch (pipe) {
6463         case PIPE_A:
6464                 return 0;
6465         case PIPE_B:
6466                 if (pipe_config->fdi_lanes <= 2)
6467                         return 0;
6468
6469                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6470                 other_crtc_state =
6471                         intel_atomic_get_crtc_state(state, other_crtc);
6472                 if (IS_ERR(other_crtc_state))
6473                         return PTR_ERR(other_crtc_state);
6474
6475                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6476                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6477                                       pipe_name(pipe), pipe_config->fdi_lanes);
6478                         return -EINVAL;
6479                 }
6480                 return 0;
6481         case PIPE_C:
6482                 if (pipe_config->fdi_lanes > 2) {
6483                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6484                                       pipe_name(pipe), pipe_config->fdi_lanes);
6485                         return -EINVAL;
6486                 }
6487
6488                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6489                 other_crtc_state =
6490                         intel_atomic_get_crtc_state(state, other_crtc);
6491                 if (IS_ERR(other_crtc_state))
6492                         return PTR_ERR(other_crtc_state);
6493
6494                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6495                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6496                         return -EINVAL;
6497                 }
6498                 return 0;
6499         default:
6500                 BUG();
6501         }
6502 }
6503
6504 #define RETRY 1
6505 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6506                                        struct intel_crtc_state *pipe_config)
6507 {
6508         struct drm_device *dev = intel_crtc->base.dev;
6509         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6510         int lane, link_bw, fdi_dotclock, ret;
6511         bool needs_recompute = false;
6512
6513 retry:
6514         /* FDI is a binary signal running at ~2.7GHz, encoding
6515          * each output octet as 10 bits. The actual frequency
6516          * is stored as a divider into a 100MHz clock, and the
6517          * mode pixel clock is stored in units of 1KHz.
6518          * Hence the bw of each lane in terms of the mode signal
6519          * is:
6520          */
6521         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6522
6523         fdi_dotclock = adjusted_mode->crtc_clock;
6524
6525         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6526                                            pipe_config->pipe_bpp);
6527
6528         pipe_config->fdi_lanes = lane;
6529
6530         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6531                                link_bw, &pipe_config->fdi_m_n);
6532
6533         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6534                                        intel_crtc->pipe, pipe_config);
6535         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6536                 pipe_config->pipe_bpp -= 2*3;
6537                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6538                               pipe_config->pipe_bpp);
6539                 needs_recompute = true;
6540                 pipe_config->bw_constrained = true;
6541
6542                 goto retry;
6543         }
6544
6545         if (needs_recompute)
6546                 return RETRY;
6547
6548         return ret;
6549 }
6550
6551 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6552                                      struct intel_crtc_state *pipe_config)
6553 {
6554         if (pipe_config->pipe_bpp > 24)
6555                 return false;
6556
6557         /* HSW can handle pixel rate up to cdclk? */
6558         if (IS_HASWELL(dev_priv->dev))
6559                 return true;
6560
6561         /*
6562          * We compare against max which means we must take
6563          * the increased cdclk requirement into account when
6564          * calculating the new cdclk.
6565          *
6566          * Should measure whether using a lower cdclk w/o IPS
6567          */
6568         return ilk_pipe_pixel_rate(pipe_config) <=
6569                 dev_priv->max_cdclk_freq * 95 / 100;
6570 }
6571
6572 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6573                                    struct intel_crtc_state *pipe_config)
6574 {
6575         struct drm_device *dev = crtc->base.dev;
6576         struct drm_i915_private *dev_priv = dev->dev_private;
6577
6578         pipe_config->ips_enabled = i915.enable_ips &&
6579                 hsw_crtc_supports_ips(crtc) &&
6580                 pipe_config_supports_ips(dev_priv, pipe_config);
6581 }
6582
6583 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6584                                      struct intel_crtc_state *pipe_config)
6585 {
6586         struct drm_device *dev = crtc->base.dev;
6587         struct drm_i915_private *dev_priv = dev->dev_private;
6588         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6589         int ret;
6590
6591         /* FIXME should check pixel clock limits on all platforms */
6592         if (INTEL_INFO(dev)->gen < 4) {
6593                 int clock_limit = dev_priv->max_cdclk_freq;
6594
6595                 /*
6596                  * Enable pixel doubling when the dot clock
6597                  * is > 90% of the (display) core speed.
6598                  *
6599                  * GDG double wide on either pipe,
6600                  * otherwise pipe A only.
6601                  */
6602                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6603                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6604                         clock_limit *= 2;
6605                         pipe_config->double_wide = true;
6606                 }
6607
6608                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6609                         return -EINVAL;
6610         }
6611
6612         /*
6613          * Pipe horizontal size must be even in:
6614          * - DVO ganged mode
6615          * - LVDS dual channel mode
6616          * - Double wide pipe
6617          */
6618         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6619              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6620                 pipe_config->pipe_src_w &= ~1;
6621
6622         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6623          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6624          */
6625         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6626                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6627                 return -EINVAL;
6628
6629         if (HAS_IPS(dev))
6630                 hsw_compute_ips_config(crtc, pipe_config);
6631
6632         if (pipe_config->has_pch_encoder)
6633                 return ironlake_fdi_compute_config(crtc, pipe_config);
6634
6635         /* FIXME: remove below call once atomic mode set is place and all crtc
6636          * related checks called from atomic_crtc_check function */
6637         ret = 0;
6638         DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6639                 crtc, pipe_config->base.state);
6640         ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6641
6642         return ret;
6643 }
6644
6645 static int skylake_get_display_clock_speed(struct drm_device *dev)
6646 {
6647         struct drm_i915_private *dev_priv = to_i915(dev);
6648         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6649         uint32_t cdctl = I915_READ(CDCLK_CTL);
6650         uint32_t linkrate;
6651
6652         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6653                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6654
6655         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6656                 return 540000;
6657
6658         linkrate = (I915_READ(DPLL_CTRL1) &
6659                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6660
6661         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6662             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6663                 /* vco 8640 */
6664                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6665                 case CDCLK_FREQ_450_432:
6666                         return 432000;
6667                 case CDCLK_FREQ_337_308:
6668                         return 308570;
6669                 case CDCLK_FREQ_675_617:
6670                         return 617140;
6671                 default:
6672                         WARN(1, "Unknown cd freq selection\n");
6673                 }
6674         } else {
6675                 /* vco 8100 */
6676                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6677                 case CDCLK_FREQ_450_432:
6678                         return 450000;
6679                 case CDCLK_FREQ_337_308:
6680                         return 337500;
6681                 case CDCLK_FREQ_675_617:
6682                         return 675000;
6683                 default:
6684                         WARN(1, "Unknown cd freq selection\n");
6685                 }
6686         }
6687
6688         /* error case, do as if DPLL0 isn't enabled */
6689         return 24000;
6690 }
6691
6692 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6693 {
6694         struct drm_i915_private *dev_priv = dev->dev_private;
6695         uint32_t lcpll = I915_READ(LCPLL_CTL);
6696         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6697
6698         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6699                 return 800000;
6700         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6701                 return 450000;
6702         else if (freq == LCPLL_CLK_FREQ_450)
6703                 return 450000;
6704         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6705                 return 540000;
6706         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6707                 return 337500;
6708         else
6709                 return 675000;
6710 }
6711
6712 static int haswell_get_display_clock_speed(struct drm_device *dev)
6713 {
6714         struct drm_i915_private *dev_priv = dev->dev_private;
6715         uint32_t lcpll = I915_READ(LCPLL_CTL);
6716         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6717
6718         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6719                 return 800000;
6720         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6721                 return 450000;
6722         else if (freq == LCPLL_CLK_FREQ_450)
6723                 return 450000;
6724         else if (IS_HSW_ULT(dev))
6725                 return 337500;
6726         else
6727                 return 540000;
6728 }
6729
6730 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6731 {
6732         struct drm_i915_private *dev_priv = dev->dev_private;
6733         u32 val;
6734         int divider;
6735
6736         if (dev_priv->hpll_freq == 0)
6737                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6738
6739         mutex_lock(&dev_priv->sb_lock);
6740         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6741         mutex_unlock(&dev_priv->sb_lock);
6742
6743         divider = val & DISPLAY_FREQUENCY_VALUES;
6744
6745         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6746              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6747              "cdclk change in progress\n");
6748
6749         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6750 }
6751
6752 static int ilk_get_display_clock_speed(struct drm_device *dev)
6753 {
6754         return 450000;
6755 }
6756
6757 static int i945_get_display_clock_speed(struct drm_device *dev)
6758 {
6759         return 400000;
6760 }
6761
6762 static int i915_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         return 333333;
6765 }
6766
6767 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6768 {
6769         return 200000;
6770 }
6771
6772 static int pnv_get_display_clock_speed(struct drm_device *dev)
6773 {
6774         u16 gcfgc = 0;
6775
6776         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6777
6778         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6779         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6780                 return 266667;
6781         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6782                 return 333333;
6783         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6784                 return 444444;
6785         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6786                 return 200000;
6787         default:
6788                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6789         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6790                 return 133333;
6791         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6792                 return 166667;
6793         }
6794 }
6795
6796 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6797 {
6798         u16 gcfgc = 0;
6799
6800         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6801
6802         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6803                 return 133333;
6804         else {
6805                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6806                 case GC_DISPLAY_CLOCK_333_MHZ:
6807                         return 333333;
6808                 default:
6809                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6810                         return 190000;
6811                 }
6812         }
6813 }
6814
6815 static int i865_get_display_clock_speed(struct drm_device *dev)
6816 {
6817         return 266667;
6818 }
6819
6820 static int i85x_get_display_clock_speed(struct drm_device *dev)
6821 {
6822         u16 hpllcc = 0;
6823
6824         /*
6825          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6826          * encoding is different :(
6827          * FIXME is this the right way to detect 852GM/852GMV?
6828          */
6829         if (dev->pdev->revision == 0x1)
6830                 return 133333;
6831
6832         pci_bus_read_config_word(dev->pdev->bus,
6833                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6834
6835         /* Assume that the hardware is in the high speed state.  This
6836          * should be the default.
6837          */
6838         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6839         case GC_CLOCK_133_200:
6840         case GC_CLOCK_133_200_2:
6841         case GC_CLOCK_100_200:
6842                 return 200000;
6843         case GC_CLOCK_166_250:
6844                 return 250000;
6845         case GC_CLOCK_100_133:
6846                 return 133333;
6847         case GC_CLOCK_133_266:
6848         case GC_CLOCK_133_266_2:
6849         case GC_CLOCK_166_266:
6850                 return 266667;
6851         }
6852
6853         /* Shouldn't happen */
6854         return 0;
6855 }
6856
6857 static int i830_get_display_clock_speed(struct drm_device *dev)
6858 {
6859         return 133333;
6860 }
6861
6862 static unsigned int intel_hpll_vco(struct drm_device *dev)
6863 {
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         static const unsigned int blb_vco[8] = {
6866                 [0] = 3200000,
6867                 [1] = 4000000,
6868                 [2] = 5333333,
6869                 [3] = 4800000,
6870                 [4] = 6400000,
6871         };
6872         static const unsigned int pnv_vco[8] = {
6873                 [0] = 3200000,
6874                 [1] = 4000000,
6875                 [2] = 5333333,
6876                 [3] = 4800000,
6877                 [4] = 2666667,
6878         };
6879         static const unsigned int cl_vco[8] = {
6880                 [0] = 3200000,
6881                 [1] = 4000000,
6882                 [2] = 5333333,
6883                 [3] = 6400000,
6884                 [4] = 3333333,
6885                 [5] = 3566667,
6886                 [6] = 4266667,
6887         };
6888         static const unsigned int elk_vco[8] = {
6889                 [0] = 3200000,
6890                 [1] = 4000000,
6891                 [2] = 5333333,
6892                 [3] = 4800000,
6893         };
6894         static const unsigned int ctg_vco[8] = {
6895                 [0] = 3200000,
6896                 [1] = 4000000,
6897                 [2] = 5333333,
6898                 [3] = 6400000,
6899                 [4] = 2666667,
6900                 [5] = 4266667,
6901         };
6902         const unsigned int *vco_table;
6903         unsigned int vco;
6904         uint8_t tmp = 0;
6905
6906         /* FIXME other chipsets? */
6907         if (IS_GM45(dev))
6908                 vco_table = ctg_vco;
6909         else if (IS_G4X(dev))
6910                 vco_table = elk_vco;
6911         else if (IS_CRESTLINE(dev))
6912                 vco_table = cl_vco;
6913         else if (IS_PINEVIEW(dev))
6914                 vco_table = pnv_vco;
6915         else if (IS_G33(dev))
6916                 vco_table = blb_vco;
6917         else
6918                 return 0;
6919
6920         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6921
6922         vco = vco_table[tmp & 0x7];
6923         if (vco == 0)
6924                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6925         else
6926                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6927
6928         return vco;
6929 }
6930
6931 static int gm45_get_display_clock_speed(struct drm_device *dev)
6932 {
6933         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6934         uint16_t tmp = 0;
6935
6936         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6937
6938         cdclk_sel = (tmp >> 12) & 0x1;
6939
6940         switch (vco) {
6941         case 2666667:
6942         case 4000000:
6943         case 5333333:
6944                 return cdclk_sel ? 333333 : 222222;
6945         case 3200000:
6946                 return cdclk_sel ? 320000 : 228571;
6947         default:
6948                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6949                 return 222222;
6950         }
6951 }
6952
6953 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6954 {
6955         static const uint8_t div_3200[] = { 16, 10,  8 };
6956         static const uint8_t div_4000[] = { 20, 12, 10 };
6957         static const uint8_t div_5333[] = { 24, 16, 14 };
6958         const uint8_t *div_table;
6959         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6960         uint16_t tmp = 0;
6961
6962         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6963
6964         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6965
6966         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6967                 goto fail;
6968
6969         switch (vco) {
6970         case 3200000:
6971                 div_table = div_3200;
6972                 break;
6973         case 4000000:
6974                 div_table = div_4000;
6975                 break;
6976         case 5333333:
6977                 div_table = div_5333;
6978                 break;
6979         default:
6980                 goto fail;
6981         }
6982
6983         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6984
6985 fail:
6986         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6987         return 200000;
6988 }
6989
6990 static int g33_get_display_clock_speed(struct drm_device *dev)
6991 {
6992         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6993         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6994         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6995         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6996         const uint8_t *div_table;
6997         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6998         uint16_t tmp = 0;
6999
7000         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7001
7002         cdclk_sel = (tmp >> 4) & 0x7;
7003
7004         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7005                 goto fail;
7006
7007         switch (vco) {
7008         case 3200000:
7009                 div_table = div_3200;
7010                 break;
7011         case 4000000:
7012                 div_table = div_4000;
7013                 break;
7014         case 4800000:
7015                 div_table = div_4800;
7016                 break;
7017         case 5333333:
7018                 div_table = div_5333;
7019                 break;
7020         default:
7021                 goto fail;
7022         }
7023
7024         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7025
7026 fail:
7027         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7028         return 190476;
7029 }
7030
7031 static void
7032 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7033 {
7034         while (*num > DATA_LINK_M_N_MASK ||
7035                *den > DATA_LINK_M_N_MASK) {
7036                 *num >>= 1;
7037                 *den >>= 1;
7038         }
7039 }
7040
7041 static void compute_m_n(unsigned int m, unsigned int n,
7042                         uint32_t *ret_m, uint32_t *ret_n)
7043 {
7044         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7045         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7046         intel_reduce_m_n_ratio(ret_m, ret_n);
7047 }
7048
7049 void
7050 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7051                        int pixel_clock, int link_clock,
7052                        struct intel_link_m_n *m_n)
7053 {
7054         m_n->tu = 64;
7055
7056         compute_m_n(bits_per_pixel * pixel_clock,
7057                     link_clock * nlanes * 8,
7058                     &m_n->gmch_m, &m_n->gmch_n);
7059
7060         compute_m_n(pixel_clock, link_clock,
7061                     &m_n->link_m, &m_n->link_n);
7062 }
7063
7064 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7065 {
7066         if (i915.panel_use_ssc >= 0)
7067                 return i915.panel_use_ssc != 0;
7068         return dev_priv->vbt.lvds_use_ssc
7069                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7070 }
7071
7072 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7073                            int num_connectors)
7074 {
7075         struct drm_device *dev = crtc_state->base.crtc->dev;
7076         struct drm_i915_private *dev_priv = dev->dev_private;
7077         int refclk;
7078
7079         WARN_ON(!crtc_state->base.state);
7080
7081         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7082                 refclk = 100000;
7083         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7084             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7085                 refclk = dev_priv->vbt.lvds_ssc_freq;
7086                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7087         } else if (!IS_GEN2(dev)) {
7088                 refclk = 96000;
7089         } else {
7090                 refclk = 48000;
7091         }
7092
7093         return refclk;
7094 }
7095
7096 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7097 {
7098         return (1 << dpll->n) << 16 | dpll->m2;
7099 }
7100
7101 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7102 {
7103         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7104 }
7105
7106 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7107                                      struct intel_crtc_state *crtc_state,
7108                                      intel_clock_t *reduced_clock)
7109 {
7110         struct drm_device *dev = crtc->base.dev;
7111         u32 fp, fp2 = 0;
7112
7113         if (IS_PINEVIEW(dev)) {
7114                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7115                 if (reduced_clock)
7116                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7117         } else {
7118                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7119                 if (reduced_clock)
7120                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7121         }
7122
7123         crtc_state->dpll_hw_state.fp0 = fp;
7124
7125         crtc->lowfreq_avail = false;
7126         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7127             reduced_clock) {
7128                 crtc_state->dpll_hw_state.fp1 = fp2;
7129                 crtc->lowfreq_avail = true;
7130         } else {
7131                 crtc_state->dpll_hw_state.fp1 = fp;
7132         }
7133 }
7134
7135 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7136                 pipe)
7137 {
7138         u32 reg_val;
7139
7140         /*
7141          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7142          * and set it to a reasonable value instead.
7143          */
7144         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145         reg_val &= 0xffffff00;
7146         reg_val |= 0x00000030;
7147         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7148
7149         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7150         reg_val &= 0x8cffffff;
7151         reg_val = 0x8c000000;
7152         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7153
7154         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7155         reg_val &= 0xffffff00;
7156         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7157
7158         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7159         reg_val &= 0x00ffffff;
7160         reg_val |= 0xb0000000;
7161         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7162 }
7163
7164 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7165                                          struct intel_link_m_n *m_n)
7166 {
7167         struct drm_device *dev = crtc->base.dev;
7168         struct drm_i915_private *dev_priv = dev->dev_private;
7169         int pipe = crtc->pipe;
7170
7171         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7173         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7174         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7175 }
7176
7177 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7178                                          struct intel_link_m_n *m_n,
7179                                          struct intel_link_m_n *m2_n2)
7180 {
7181         struct drm_device *dev = crtc->base.dev;
7182         struct drm_i915_private *dev_priv = dev->dev_private;
7183         int pipe = crtc->pipe;
7184         enum transcoder transcoder = crtc->config->cpu_transcoder;
7185
7186         if (INTEL_INFO(dev)->gen >= 5) {
7187                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7188                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7189                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7190                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7191                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7192                  * for gen < 8) and if DRRS is supported (to make sure the
7193                  * registers are not unnecessarily accessed).
7194                  */
7195                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7196                         crtc->config->has_drrs) {
7197                         I915_WRITE(PIPE_DATA_M2(transcoder),
7198                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7199                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7200                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7201                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7202                 }
7203         } else {
7204                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7205                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7206                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7207                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7208         }
7209 }
7210
7211 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7212 {
7213         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7214
7215         if (m_n == M1_N1) {
7216                 dp_m_n = &crtc->config->dp_m_n;
7217                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7218         } else if (m_n == M2_N2) {
7219
7220                 /*
7221                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7222                  * needs to be programmed into M1_N1.
7223                  */
7224                 dp_m_n = &crtc->config->dp_m2_n2;
7225         } else {
7226                 DRM_ERROR("Unsupported divider value\n");
7227                 return;
7228         }
7229
7230         if (crtc->config->has_pch_encoder)
7231                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7232         else
7233                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7234 }
7235
7236 static void vlv_update_pll(struct intel_crtc *crtc,
7237                            struct intel_crtc_state *pipe_config)
7238 {
7239         u32 dpll, dpll_md;
7240
7241         /*
7242          * Enable DPIO clock input. We should never disable the reference
7243          * clock for pipe B, since VGA hotplug / manual detection depends
7244          * on it.
7245          */
7246         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7247                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7248         /* We should never disable this, set it here for state tracking */
7249         if (crtc->pipe == PIPE_B)
7250                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7251         dpll |= DPLL_VCO_ENABLE;
7252         pipe_config->dpll_hw_state.dpll = dpll;
7253
7254         dpll_md = (pipe_config->pixel_multiplier - 1)
7255                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7256         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7257 }
7258
7259 static void vlv_prepare_pll(struct intel_crtc *crtc,
7260                             const struct intel_crtc_state *pipe_config)
7261 {
7262         struct drm_device *dev = crtc->base.dev;
7263         struct drm_i915_private *dev_priv = dev->dev_private;
7264         int pipe = crtc->pipe;
7265         u32 mdiv;
7266         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7267         u32 coreclk, reg_val;
7268
7269         mutex_lock(&dev_priv->sb_lock);
7270
7271         bestn = pipe_config->dpll.n;
7272         bestm1 = pipe_config->dpll.m1;
7273         bestm2 = pipe_config->dpll.m2;
7274         bestp1 = pipe_config->dpll.p1;
7275         bestp2 = pipe_config->dpll.p2;
7276
7277         /* See eDP HDMI DPIO driver vbios notes doc */
7278
7279         /* PLL B needs special handling */
7280         if (pipe == PIPE_B)
7281                 vlv_pllb_recal_opamp(dev_priv, pipe);
7282
7283         /* Set up Tx target for periodic Rcomp update */
7284         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7285
7286         /* Disable target IRef on PLL */
7287         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7288         reg_val &= 0x00ffffff;
7289         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7290
7291         /* Disable fast lock */
7292         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7293
7294         /* Set idtafcrecal before PLL is enabled */
7295         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7296         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7297         mdiv |= ((bestn << DPIO_N_SHIFT));
7298         mdiv |= (1 << DPIO_K_SHIFT);
7299
7300         /*
7301          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7302          * but we don't support that).
7303          * Note: don't use the DAC post divider as it seems unstable.
7304          */
7305         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7306         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7307
7308         mdiv |= DPIO_ENABLE_CALIBRATION;
7309         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7310
7311         /* Set HBR and RBR LPF coefficients */
7312         if (pipe_config->port_clock == 162000 ||
7313             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7314             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7315                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7316                                  0x009f0003);
7317         else
7318                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7319                                  0x00d0000f);
7320
7321         if (pipe_config->has_dp_encoder) {
7322                 /* Use SSC source */
7323                 if (pipe == PIPE_A)
7324                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7325                                          0x0df40000);
7326                 else
7327                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7328                                          0x0df70000);
7329         } else { /* HDMI or VGA */
7330                 /* Use bend source */
7331                 if (pipe == PIPE_A)
7332                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7333                                          0x0df70000);
7334                 else
7335                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7336                                          0x0df40000);
7337         }
7338
7339         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7340         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7341         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7342             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7343                 coreclk |= 0x01000000;
7344         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7345
7346         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7347         mutex_unlock(&dev_priv->sb_lock);
7348 }
7349
7350 static void chv_update_pll(struct intel_crtc *crtc,
7351                            struct intel_crtc_state *pipe_config)
7352 {
7353         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7354                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7355                 DPLL_VCO_ENABLE;
7356         if (crtc->pipe != PIPE_A)
7357                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7358
7359         pipe_config->dpll_hw_state.dpll_md =
7360                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7361 }
7362
7363 static void chv_prepare_pll(struct intel_crtc *crtc,
7364                             const struct intel_crtc_state *pipe_config)
7365 {
7366         struct drm_device *dev = crtc->base.dev;
7367         struct drm_i915_private *dev_priv = dev->dev_private;
7368         int pipe = crtc->pipe;
7369         int dpll_reg = DPLL(crtc->pipe);
7370         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7371         u32 loopfilter, tribuf_calcntr;
7372         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7373         u32 dpio_val;
7374         int vco;
7375
7376         bestn = pipe_config->dpll.n;
7377         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7378         bestm1 = pipe_config->dpll.m1;
7379         bestm2 = pipe_config->dpll.m2 >> 22;
7380         bestp1 = pipe_config->dpll.p1;
7381         bestp2 = pipe_config->dpll.p2;
7382         vco = pipe_config->dpll.vco;
7383         dpio_val = 0;
7384         loopfilter = 0;
7385
7386         /*
7387          * Enable Refclk and SSC
7388          */
7389         I915_WRITE(dpll_reg,
7390                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7391
7392         mutex_lock(&dev_priv->sb_lock);
7393
7394         /* p1 and p2 divider */
7395         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7396                         5 << DPIO_CHV_S1_DIV_SHIFT |
7397                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7398                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7399                         1 << DPIO_CHV_K_DIV_SHIFT);
7400
7401         /* Feedback post-divider - m2 */
7402         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7403
7404         /* Feedback refclk divider - n and m1 */
7405         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7406                         DPIO_CHV_M1_DIV_BY_2 |
7407                         1 << DPIO_CHV_N_DIV_SHIFT);
7408
7409         /* M2 fraction division */
7410         if (bestm2_frac)
7411                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7412
7413         /* M2 fraction division enable */
7414         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7415         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7416         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7417         if (bestm2_frac)
7418                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7419         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7420
7421         /* Program digital lock detect threshold */
7422         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7423         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7424                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7425         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7426         if (!bestm2_frac)
7427                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7428         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7429
7430         /* Loop filter */
7431         if (vco == 5400000) {
7432                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7433                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7434                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435                 tribuf_calcntr = 0x9;
7436         } else if (vco <= 6200000) {
7437                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7438                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7439                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440                 tribuf_calcntr = 0x9;
7441         } else if (vco <= 6480000) {
7442                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7443                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7444                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445                 tribuf_calcntr = 0x8;
7446         } else {
7447                 /* Not supported. Apply the same limits as in the max case */
7448                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7449                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7450                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7451                 tribuf_calcntr = 0;
7452         }
7453         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7454
7455         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7456         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7457         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7458         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7459
7460         /* AFC Recal */
7461         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7462                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7463                         DPIO_AFC_RECAL);
7464
7465         mutex_unlock(&dev_priv->sb_lock);
7466 }
7467
7468 /**
7469  * vlv_force_pll_on - forcibly enable just the PLL
7470  * @dev_priv: i915 private structure
7471  * @pipe: pipe PLL to enable
7472  * @dpll: PLL configuration
7473  *
7474  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7475  * in cases where we need the PLL enabled even when @pipe is not going to
7476  * be enabled.
7477  */
7478 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7479                       const struct dpll *dpll)
7480 {
7481         struct intel_crtc *crtc =
7482                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7483         struct intel_crtc_state pipe_config = {
7484                 .base.crtc = &crtc->base,
7485                 .pixel_multiplier = 1,
7486                 .dpll = *dpll,
7487         };
7488
7489         if (IS_CHERRYVIEW(dev)) {
7490                 chv_update_pll(crtc, &pipe_config);
7491                 chv_prepare_pll(crtc, &pipe_config);
7492                 chv_enable_pll(crtc, &pipe_config);
7493         } else {
7494                 vlv_update_pll(crtc, &pipe_config);
7495                 vlv_prepare_pll(crtc, &pipe_config);
7496                 vlv_enable_pll(crtc, &pipe_config);
7497         }
7498 }
7499
7500 /**
7501  * vlv_force_pll_off - forcibly disable just the PLL
7502  * @dev_priv: i915 private structure
7503  * @pipe: pipe PLL to disable
7504  *
7505  * Disable the PLL for @pipe. To be used in cases where we need
7506  * the PLL enabled even when @pipe is not going to be enabled.
7507  */
7508 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7509 {
7510         if (IS_CHERRYVIEW(dev))
7511                 chv_disable_pll(to_i915(dev), pipe);
7512         else
7513                 vlv_disable_pll(to_i915(dev), pipe);
7514 }
7515
7516 static void i9xx_update_pll(struct intel_crtc *crtc,
7517                             struct intel_crtc_state *crtc_state,
7518                             intel_clock_t *reduced_clock,
7519                             int num_connectors)
7520 {
7521         struct drm_device *dev = crtc->base.dev;
7522         struct drm_i915_private *dev_priv = dev->dev_private;
7523         u32 dpll;
7524         bool is_sdvo;
7525         struct dpll *clock = &crtc_state->dpll;
7526
7527         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7528
7529         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7530                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7531
7532         dpll = DPLL_VGA_MODE_DIS;
7533
7534         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7535                 dpll |= DPLLB_MODE_LVDS;
7536         else
7537                 dpll |= DPLLB_MODE_DAC_SERIAL;
7538
7539         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7540                 dpll |= (crtc_state->pixel_multiplier - 1)
7541                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7542         }
7543
7544         if (is_sdvo)
7545                 dpll |= DPLL_SDVO_HIGH_SPEED;
7546
7547         if (crtc_state->has_dp_encoder)
7548                 dpll |= DPLL_SDVO_HIGH_SPEED;
7549
7550         /* compute bitmask from p1 value */
7551         if (IS_PINEVIEW(dev))
7552                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7553         else {
7554                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7555                 if (IS_G4X(dev) && reduced_clock)
7556                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7557         }
7558         switch (clock->p2) {
7559         case 5:
7560                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7561                 break;
7562         case 7:
7563                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7564                 break;
7565         case 10:
7566                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7567                 break;
7568         case 14:
7569                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7570                 break;
7571         }
7572         if (INTEL_INFO(dev)->gen >= 4)
7573                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7574
7575         if (crtc_state->sdvo_tv_clock)
7576                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7577         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7578                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7579                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7580         else
7581                 dpll |= PLL_REF_INPUT_DREFCLK;
7582
7583         dpll |= DPLL_VCO_ENABLE;
7584         crtc_state->dpll_hw_state.dpll = dpll;
7585
7586         if (INTEL_INFO(dev)->gen >= 4) {
7587                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7588                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7589                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7590         }
7591 }
7592
7593 static void i8xx_update_pll(struct intel_crtc *crtc,
7594                             struct intel_crtc_state *crtc_state,
7595                             intel_clock_t *reduced_clock,
7596                             int num_connectors)
7597 {
7598         struct drm_device *dev = crtc->base.dev;
7599         struct drm_i915_private *dev_priv = dev->dev_private;
7600         u32 dpll;
7601         struct dpll *clock = &crtc_state->dpll;
7602
7603         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7604
7605         dpll = DPLL_VGA_MODE_DIS;
7606
7607         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7608                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7609         } else {
7610                 if (clock->p1 == 2)
7611                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7612                 else
7613                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7614                 if (clock->p2 == 4)
7615                         dpll |= PLL_P2_DIVIDE_BY_4;
7616         }
7617
7618         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7619                 dpll |= DPLL_DVO_2X_MODE;
7620
7621         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7622                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7623                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7624         else
7625                 dpll |= PLL_REF_INPUT_DREFCLK;
7626
7627         dpll |= DPLL_VCO_ENABLE;
7628         crtc_state->dpll_hw_state.dpll = dpll;
7629 }
7630
7631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7632 {
7633         struct drm_device *dev = intel_crtc->base.dev;
7634         struct drm_i915_private *dev_priv = dev->dev_private;
7635         enum pipe pipe = intel_crtc->pipe;
7636         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7637         struct drm_display_mode *adjusted_mode =
7638                 &intel_crtc->config->base.adjusted_mode;
7639         uint32_t crtc_vtotal, crtc_vblank_end;
7640         int vsyncshift = 0;
7641
7642         /* We need to be careful not to changed the adjusted mode, for otherwise
7643          * the hw state checker will get angry at the mismatch. */
7644         crtc_vtotal = adjusted_mode->crtc_vtotal;
7645         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7646
7647         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7648                 /* the chip adds 2 halflines automatically */
7649                 crtc_vtotal -= 1;
7650                 crtc_vblank_end -= 1;
7651
7652                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7653                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7654                 else
7655                         vsyncshift = adjusted_mode->crtc_hsync_start -
7656                                 adjusted_mode->crtc_htotal / 2;
7657                 if (vsyncshift < 0)
7658                         vsyncshift += adjusted_mode->crtc_htotal;
7659         }
7660
7661         if (INTEL_INFO(dev)->gen > 3)
7662                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7663
7664         I915_WRITE(HTOTAL(cpu_transcoder),
7665                    (adjusted_mode->crtc_hdisplay - 1) |
7666                    ((adjusted_mode->crtc_htotal - 1) << 16));
7667         I915_WRITE(HBLANK(cpu_transcoder),
7668                    (adjusted_mode->crtc_hblank_start - 1) |
7669                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7670         I915_WRITE(HSYNC(cpu_transcoder),
7671                    (adjusted_mode->crtc_hsync_start - 1) |
7672                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7673
7674         I915_WRITE(VTOTAL(cpu_transcoder),
7675                    (adjusted_mode->crtc_vdisplay - 1) |
7676                    ((crtc_vtotal - 1) << 16));
7677         I915_WRITE(VBLANK(cpu_transcoder),
7678                    (adjusted_mode->crtc_vblank_start - 1) |
7679                    ((crtc_vblank_end - 1) << 16));
7680         I915_WRITE(VSYNC(cpu_transcoder),
7681                    (adjusted_mode->crtc_vsync_start - 1) |
7682                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7683
7684         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7685          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7686          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7687          * bits. */
7688         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7689             (pipe == PIPE_B || pipe == PIPE_C))
7690                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7691
7692         /* pipesrc controls the size that is scaled from, which should
7693          * always be the user's requested size.
7694          */
7695         I915_WRITE(PIPESRC(pipe),
7696                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7697                    (intel_crtc->config->pipe_src_h - 1));
7698 }
7699
7700 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7701                                    struct intel_crtc_state *pipe_config)
7702 {
7703         struct drm_device *dev = crtc->base.dev;
7704         struct drm_i915_private *dev_priv = dev->dev_private;
7705         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7706         uint32_t tmp;
7707
7708         tmp = I915_READ(HTOTAL(cpu_transcoder));
7709         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7710         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7711         tmp = I915_READ(HBLANK(cpu_transcoder));
7712         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7713         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7714         tmp = I915_READ(HSYNC(cpu_transcoder));
7715         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7716         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7717
7718         tmp = I915_READ(VTOTAL(cpu_transcoder));
7719         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7720         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7721         tmp = I915_READ(VBLANK(cpu_transcoder));
7722         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7723         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7724         tmp = I915_READ(VSYNC(cpu_transcoder));
7725         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7726         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7727
7728         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7729                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7730                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7731                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7732         }
7733
7734         tmp = I915_READ(PIPESRC(crtc->pipe));
7735         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7736         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7737
7738         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7739         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7740 }
7741
7742 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7743                                  struct intel_crtc_state *pipe_config)
7744 {
7745         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7746         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7747         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7748         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7749
7750         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7751         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7752         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7753         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7754
7755         mode->flags = pipe_config->base.adjusted_mode.flags;
7756
7757         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7758         mode->flags |= pipe_config->base.adjusted_mode.flags;
7759 }
7760
7761 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7762 {
7763         struct drm_device *dev = intel_crtc->base.dev;
7764         struct drm_i915_private *dev_priv = dev->dev_private;
7765         uint32_t pipeconf;
7766
7767         pipeconf = 0;
7768
7769         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7770             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7771                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7772
7773         if (intel_crtc->config->double_wide)
7774                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7775
7776         /* only g4x and later have fancy bpc/dither controls */
7777         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7778                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7779                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7780                         pipeconf |= PIPECONF_DITHER_EN |
7781                                     PIPECONF_DITHER_TYPE_SP;
7782
7783                 switch (intel_crtc->config->pipe_bpp) {
7784                 case 18:
7785                         pipeconf |= PIPECONF_6BPC;
7786                         break;
7787                 case 24:
7788                         pipeconf |= PIPECONF_8BPC;
7789                         break;
7790                 case 30:
7791                         pipeconf |= PIPECONF_10BPC;
7792                         break;
7793                 default:
7794                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7795                         BUG();
7796                 }
7797         }
7798
7799         if (HAS_PIPE_CXSR(dev)) {
7800                 if (intel_crtc->lowfreq_avail) {
7801                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7802                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7803                 } else {
7804                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7805                 }
7806         }
7807
7808         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7809                 if (INTEL_INFO(dev)->gen < 4 ||
7810                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7811                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7812                 else
7813                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7814         } else
7815                 pipeconf |= PIPECONF_PROGRESSIVE;
7816
7817         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7818                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7819
7820         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7821         POSTING_READ(PIPECONF(intel_crtc->pipe));
7822 }
7823
7824 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7825                                    struct intel_crtc_state *crtc_state)
7826 {
7827         struct drm_device *dev = crtc->base.dev;
7828         struct drm_i915_private *dev_priv = dev->dev_private;
7829         int refclk, num_connectors = 0;
7830         intel_clock_t clock, reduced_clock;
7831         bool ok, has_reduced_clock = false;
7832         bool is_lvds = false, is_dsi = false;
7833         struct intel_encoder *encoder;
7834         const intel_limit_t *limit;
7835         struct drm_atomic_state *state = crtc_state->base.state;
7836         struct drm_connector *connector;
7837         struct drm_connector_state *connector_state;
7838         int i;
7839
7840         memset(&crtc_state->dpll_hw_state, 0,
7841                sizeof(crtc_state->dpll_hw_state));
7842
7843         for_each_connector_in_state(state, connector, connector_state, i) {
7844                 if (connector_state->crtc != &crtc->base)
7845                         continue;
7846
7847                 encoder = to_intel_encoder(connector_state->best_encoder);
7848
7849                 switch (encoder->type) {
7850                 case INTEL_OUTPUT_LVDS:
7851                         is_lvds = true;
7852                         break;
7853                 case INTEL_OUTPUT_DSI:
7854                         is_dsi = true;
7855                         break;
7856                 default:
7857                         break;
7858                 }
7859
7860                 num_connectors++;
7861         }
7862
7863         if (is_dsi)
7864                 return 0;
7865
7866         if (!crtc_state->clock_set) {
7867                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7868
7869                 /*
7870                  * Returns a set of divisors for the desired target clock with
7871                  * the given refclk, or FALSE.  The returned values represent
7872                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7873                  * 2) / p1 / p2.
7874                  */
7875                 limit = intel_limit(crtc_state, refclk);
7876                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7877                                                  crtc_state->port_clock,
7878                                                  refclk, NULL, &clock);
7879                 if (!ok) {
7880                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7881                         return -EINVAL;
7882                 }
7883
7884                 if (is_lvds && dev_priv->lvds_downclock_avail) {
7885                         /*
7886                          * Ensure we match the reduced clock's P to the target
7887                          * clock.  If the clocks don't match, we can't switch
7888                          * the display clock by using the FP0/FP1. In such case
7889                          * we will disable the LVDS downclock feature.
7890                          */
7891                         has_reduced_clock =
7892                                 dev_priv->display.find_dpll(limit, crtc_state,
7893                                                             dev_priv->lvds_downclock,
7894                                                             refclk, &clock,
7895                                                             &reduced_clock);
7896                 }
7897                 /* Compat-code for transition, will disappear. */
7898                 crtc_state->dpll.n = clock.n;
7899                 crtc_state->dpll.m1 = clock.m1;
7900                 crtc_state->dpll.m2 = clock.m2;
7901                 crtc_state->dpll.p1 = clock.p1;
7902                 crtc_state->dpll.p2 = clock.p2;
7903         }
7904
7905         if (IS_GEN2(dev)) {
7906                 i8xx_update_pll(crtc, crtc_state,
7907                                 has_reduced_clock ? &reduced_clock : NULL,
7908                                 num_connectors);
7909         } else if (IS_CHERRYVIEW(dev)) {
7910                 chv_update_pll(crtc, crtc_state);
7911         } else if (IS_VALLEYVIEW(dev)) {
7912                 vlv_update_pll(crtc, crtc_state);
7913         } else {
7914                 i9xx_update_pll(crtc, crtc_state,
7915                                 has_reduced_clock ? &reduced_clock : NULL,
7916                                 num_connectors);
7917         }
7918
7919         return 0;
7920 }
7921
7922 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7923                                  struct intel_crtc_state *pipe_config)
7924 {
7925         struct drm_device *dev = crtc->base.dev;
7926         struct drm_i915_private *dev_priv = dev->dev_private;
7927         uint32_t tmp;
7928
7929         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7930                 return;
7931
7932         tmp = I915_READ(PFIT_CONTROL);
7933         if (!(tmp & PFIT_ENABLE))
7934                 return;
7935
7936         /* Check whether the pfit is attached to our pipe. */
7937         if (INTEL_INFO(dev)->gen < 4) {
7938                 if (crtc->pipe != PIPE_B)
7939                         return;
7940         } else {
7941                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7942                         return;
7943         }
7944
7945         pipe_config->gmch_pfit.control = tmp;
7946         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7947         if (INTEL_INFO(dev)->gen < 5)
7948                 pipe_config->gmch_pfit.lvds_border_bits =
7949                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7950 }
7951
7952 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7953                                struct intel_crtc_state *pipe_config)
7954 {
7955         struct drm_device *dev = crtc->base.dev;
7956         struct drm_i915_private *dev_priv = dev->dev_private;
7957         int pipe = pipe_config->cpu_transcoder;
7958         intel_clock_t clock;
7959         u32 mdiv;
7960         int refclk = 100000;
7961
7962         /* In case of MIPI DPLL will not even be used */
7963         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7964                 return;
7965
7966         mutex_lock(&dev_priv->sb_lock);
7967         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7968         mutex_unlock(&dev_priv->sb_lock);
7969
7970         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7971         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7972         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7973         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7974         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7975
7976         vlv_clock(refclk, &clock);
7977
7978         /* clock.dot is the fast clock */
7979         pipe_config->port_clock = clock.dot / 5;
7980 }
7981
7982 static void
7983 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7984                               struct intel_initial_plane_config *plane_config)
7985 {
7986         struct drm_device *dev = crtc->base.dev;
7987         struct drm_i915_private *dev_priv = dev->dev_private;
7988         u32 val, base, offset;
7989         int pipe = crtc->pipe, plane = crtc->plane;
7990         int fourcc, pixel_format;
7991         unsigned int aligned_height;
7992         struct drm_framebuffer *fb;
7993         struct intel_framebuffer *intel_fb;
7994
7995         val = I915_READ(DSPCNTR(plane));
7996         if (!(val & DISPLAY_PLANE_ENABLE))
7997                 return;
7998
7999         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8000         if (!intel_fb) {
8001                 DRM_DEBUG_KMS("failed to alloc fb\n");
8002                 return;
8003         }
8004
8005         fb = &intel_fb->base;
8006
8007         if (INTEL_INFO(dev)->gen >= 4) {
8008                 if (val & DISPPLANE_TILED) {
8009                         plane_config->tiling = I915_TILING_X;
8010                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8011                 }
8012         }
8013
8014         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8015         fourcc = i9xx_format_to_fourcc(pixel_format);
8016         fb->pixel_format = fourcc;
8017         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8018
8019         if (INTEL_INFO(dev)->gen >= 4) {
8020                 if (plane_config->tiling)
8021                         offset = I915_READ(DSPTILEOFF(plane));
8022                 else
8023                         offset = I915_READ(DSPLINOFF(plane));
8024                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8025         } else {
8026                 base = I915_READ(DSPADDR(plane));
8027         }
8028         plane_config->base = base;
8029
8030         val = I915_READ(PIPESRC(pipe));
8031         fb->width = ((val >> 16) & 0xfff) + 1;
8032         fb->height = ((val >> 0) & 0xfff) + 1;
8033
8034         val = I915_READ(DSPSTRIDE(pipe));
8035         fb->pitches[0] = val & 0xffffffc0;
8036
8037         aligned_height = intel_fb_align_height(dev, fb->height,
8038                                                fb->pixel_format,
8039                                                fb->modifier[0]);
8040
8041         plane_config->size = fb->pitches[0] * aligned_height;
8042
8043         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8044                       pipe_name(pipe), plane, fb->width, fb->height,
8045                       fb->bits_per_pixel, base, fb->pitches[0],
8046                       plane_config->size);
8047
8048         plane_config->fb = intel_fb;
8049 }
8050
8051 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8052                                struct intel_crtc_state *pipe_config)
8053 {
8054         struct drm_device *dev = crtc->base.dev;
8055         struct drm_i915_private *dev_priv = dev->dev_private;
8056         int pipe = pipe_config->cpu_transcoder;
8057         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8058         intel_clock_t clock;
8059         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8060         int refclk = 100000;
8061
8062         mutex_lock(&dev_priv->sb_lock);
8063         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8064         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8065         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8066         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8067         mutex_unlock(&dev_priv->sb_lock);
8068
8069         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8070         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8071         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8072         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8073         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8074
8075         chv_clock(refclk, &clock);
8076
8077         /* clock.dot is the fast clock */
8078         pipe_config->port_clock = clock.dot / 5;
8079 }
8080
8081 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8082                                  struct intel_crtc_state *pipe_config)
8083 {
8084         struct drm_device *dev = crtc->base.dev;
8085         struct drm_i915_private *dev_priv = dev->dev_private;
8086         uint32_t tmp;
8087
8088         if (!intel_display_power_is_enabled(dev_priv,
8089                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8090                 return false;
8091
8092         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8093         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8094
8095         tmp = I915_READ(PIPECONF(crtc->pipe));
8096         if (!(tmp & PIPECONF_ENABLE))
8097                 return false;
8098
8099         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8100                 switch (tmp & PIPECONF_BPC_MASK) {
8101                 case PIPECONF_6BPC:
8102                         pipe_config->pipe_bpp = 18;
8103                         break;
8104                 case PIPECONF_8BPC:
8105                         pipe_config->pipe_bpp = 24;
8106                         break;
8107                 case PIPECONF_10BPC:
8108                         pipe_config->pipe_bpp = 30;
8109                         break;
8110                 default:
8111                         break;
8112                 }
8113         }
8114
8115         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8116                 pipe_config->limited_color_range = true;
8117
8118         if (INTEL_INFO(dev)->gen < 4)
8119                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8120
8121         intel_get_pipe_timings(crtc, pipe_config);
8122
8123         i9xx_get_pfit_config(crtc, pipe_config);
8124
8125         if (INTEL_INFO(dev)->gen >= 4) {
8126                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8127                 pipe_config->pixel_multiplier =
8128                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8129                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8130                 pipe_config->dpll_hw_state.dpll_md = tmp;
8131         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8132                 tmp = I915_READ(DPLL(crtc->pipe));
8133                 pipe_config->pixel_multiplier =
8134                         ((tmp & SDVO_MULTIPLIER_MASK)
8135                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8136         } else {
8137                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8138                  * port and will be fixed up in the encoder->get_config
8139                  * function. */
8140                 pipe_config->pixel_multiplier = 1;
8141         }
8142         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8143         if (!IS_VALLEYVIEW(dev)) {
8144                 /*
8145                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8146                  * on 830. Filter it out here so that we don't
8147                  * report errors due to that.
8148                  */
8149                 if (IS_I830(dev))
8150                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8151
8152                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8153                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8154         } else {
8155                 /* Mask out read-only status bits. */
8156                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8157                                                      DPLL_PORTC_READY_MASK |
8158                                                      DPLL_PORTB_READY_MASK);
8159         }
8160
8161         if (IS_CHERRYVIEW(dev))
8162                 chv_crtc_clock_get(crtc, pipe_config);
8163         else if (IS_VALLEYVIEW(dev))
8164                 vlv_crtc_clock_get(crtc, pipe_config);
8165         else
8166                 i9xx_crtc_clock_get(crtc, pipe_config);
8167
8168         return true;
8169 }
8170
8171 static void ironlake_init_pch_refclk(struct drm_device *dev)
8172 {
8173         struct drm_i915_private *dev_priv = dev->dev_private;
8174         struct intel_encoder *encoder;
8175         u32 val, final;
8176         bool has_lvds = false;
8177         bool has_cpu_edp = false;
8178         bool has_panel = false;
8179         bool has_ck505 = false;
8180         bool can_ssc = false;
8181
8182         /* We need to take the global config into account */
8183         for_each_intel_encoder(dev, encoder) {
8184                 switch (encoder->type) {
8185                 case INTEL_OUTPUT_LVDS:
8186                         has_panel = true;
8187                         has_lvds = true;
8188                         break;
8189                 case INTEL_OUTPUT_EDP:
8190                         has_panel = true;
8191                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8192                                 has_cpu_edp = true;
8193                         break;
8194                 default:
8195                         break;
8196                 }
8197         }
8198
8199         if (HAS_PCH_IBX(dev)) {
8200                 has_ck505 = dev_priv->vbt.display_clock_mode;
8201                 can_ssc = has_ck505;
8202         } else {
8203                 has_ck505 = false;
8204                 can_ssc = true;
8205         }
8206
8207         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208                       has_panel, has_lvds, has_ck505);
8209
8210         /* Ironlake: try to setup display ref clock before DPLL
8211          * enabling. This is only under driver's control after
8212          * PCH B stepping, previous chipset stepping should be
8213          * ignoring this setting.
8214          */
8215         val = I915_READ(PCH_DREF_CONTROL);
8216
8217         /* As we must carefully and slowly disable/enable each source in turn,
8218          * compute the final state we want first and check if we need to
8219          * make any changes at all.
8220          */
8221         final = val;
8222         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8223         if (has_ck505)
8224                 final |= DREF_NONSPREAD_CK505_ENABLE;
8225         else
8226                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8227
8228         final &= ~DREF_SSC_SOURCE_MASK;
8229         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230         final &= ~DREF_SSC1_ENABLE;
8231
8232         if (has_panel) {
8233                 final |= DREF_SSC_SOURCE_ENABLE;
8234
8235                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236                         final |= DREF_SSC1_ENABLE;
8237
8238                 if (has_cpu_edp) {
8239                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8241                         else
8242                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8243                 } else
8244                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8245         } else {
8246                 final |= DREF_SSC_SOURCE_DISABLE;
8247                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248         }
8249
8250         if (final == val)
8251                 return;
8252
8253         /* Always enable nonspread source */
8254         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8255
8256         if (has_ck505)
8257                 val |= DREF_NONSPREAD_CK505_ENABLE;
8258         else
8259                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8260
8261         if (has_panel) {
8262                 val &= ~DREF_SSC_SOURCE_MASK;
8263                 val |= DREF_SSC_SOURCE_ENABLE;
8264
8265                 /* SSC must be turned on before enabling the CPU output  */
8266                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8267                         DRM_DEBUG_KMS("Using SSC on panel\n");
8268                         val |= DREF_SSC1_ENABLE;
8269                 } else
8270                         val &= ~DREF_SSC1_ENABLE;
8271
8272                 /* Get SSC going before enabling the outputs */
8273                 I915_WRITE(PCH_DREF_CONTROL, val);
8274                 POSTING_READ(PCH_DREF_CONTROL);
8275                 udelay(200);
8276
8277                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8278
8279                 /* Enable CPU source on CPU attached eDP */
8280                 if (has_cpu_edp) {
8281                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8282                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8283                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8284                         } else
8285                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8286                 } else
8287                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288
8289                 I915_WRITE(PCH_DREF_CONTROL, val);
8290                 POSTING_READ(PCH_DREF_CONTROL);
8291                 udelay(200);
8292         } else {
8293                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8294
8295                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8296
8297                 /* Turn off CPU output */
8298                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8299
8300                 I915_WRITE(PCH_DREF_CONTROL, val);
8301                 POSTING_READ(PCH_DREF_CONTROL);
8302                 udelay(200);
8303
8304                 /* Turn off the SSC source */
8305                 val &= ~DREF_SSC_SOURCE_MASK;
8306                 val |= DREF_SSC_SOURCE_DISABLE;
8307
8308                 /* Turn off SSC1 */
8309                 val &= ~DREF_SSC1_ENABLE;
8310
8311                 I915_WRITE(PCH_DREF_CONTROL, val);
8312                 POSTING_READ(PCH_DREF_CONTROL);
8313                 udelay(200);
8314         }
8315
8316         BUG_ON(val != final);
8317 }
8318
8319 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8320 {
8321         uint32_t tmp;
8322
8323         tmp = I915_READ(SOUTH_CHICKEN2);
8324         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325         I915_WRITE(SOUTH_CHICKEN2, tmp);
8326
8327         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8330
8331         tmp = I915_READ(SOUTH_CHICKEN2);
8332         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333         I915_WRITE(SOUTH_CHICKEN2, tmp);
8334
8335         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8338 }
8339
8340 /* WaMPhyProgramming:hsw */
8341 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8342 {
8343         uint32_t tmp;
8344
8345         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346         tmp &= ~(0xFF << 24);
8347         tmp |= (0x12 << 24);
8348         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8349
8350         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8351         tmp |= (1 << 11);
8352         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8353
8354         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8355         tmp |= (1 << 11);
8356         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8357
8358         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8367         tmp &= ~(7 << 13);
8368         tmp |= (5 << 13);
8369         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8370
8371         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8372         tmp &= ~(7 << 13);
8373         tmp |= (5 << 13);
8374         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8375
8376         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8377         tmp &= ~0xFF;
8378         tmp |= 0x1C;
8379         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8380
8381         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8382         tmp &= ~0xFF;
8383         tmp |= 0x1C;
8384         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8385
8386         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387         tmp &= ~(0xFF << 16);
8388         tmp |= (0x1C << 16);
8389         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8390
8391         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392         tmp &= ~(0xFF << 16);
8393         tmp |= (0x1C << 16);
8394         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8395
8396         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8397         tmp |= (1 << 27);
8398         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8399
8400         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8401         tmp |= (1 << 27);
8402         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8403
8404         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405         tmp &= ~(0xF << 28);
8406         tmp |= (4 << 28);
8407         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8408
8409         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410         tmp &= ~(0xF << 28);
8411         tmp |= (4 << 28);
8412         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8413 }
8414
8415 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8416  * Programming" based on the parameters passed:
8417  * - Sequence to enable CLKOUT_DP
8418  * - Sequence to enable CLKOUT_DP without spread
8419  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8420  */
8421 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8422                                  bool with_fdi)
8423 {
8424         struct drm_i915_private *dev_priv = dev->dev_private;
8425         uint32_t reg, tmp;
8426
8427         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8428                 with_spread = true;
8429         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8430                  with_fdi, "LP PCH doesn't have FDI\n"))
8431                 with_fdi = false;
8432
8433         mutex_lock(&dev_priv->sb_lock);
8434
8435         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8436         tmp &= ~SBI_SSCCTL_DISABLE;
8437         tmp |= SBI_SSCCTL_PATHALT;
8438         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8439
8440         udelay(24);
8441
8442         if (with_spread) {
8443                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8444                 tmp &= ~SBI_SSCCTL_PATHALT;
8445                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8446
8447                 if (with_fdi) {
8448                         lpt_reset_fdi_mphy(dev_priv);
8449                         lpt_program_fdi_mphy(dev_priv);
8450                 }
8451         }
8452
8453         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8454                SBI_GEN0 : SBI_DBUFF0;
8455         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8458
8459         mutex_unlock(&dev_priv->sb_lock);
8460 }
8461
8462 /* Sequence to disable CLKOUT_DP */
8463 static void lpt_disable_clkout_dp(struct drm_device *dev)
8464 {
8465         struct drm_i915_private *dev_priv = dev->dev_private;
8466         uint32_t reg, tmp;
8467
8468         mutex_lock(&dev_priv->sb_lock);
8469
8470         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8471                SBI_GEN0 : SBI_DBUFF0;
8472         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8473         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8474         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8475
8476         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8477         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8478                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8479                         tmp |= SBI_SSCCTL_PATHALT;
8480                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8481                         udelay(32);
8482                 }
8483                 tmp |= SBI_SSCCTL_DISABLE;
8484                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8485         }
8486
8487         mutex_unlock(&dev_priv->sb_lock);
8488 }
8489
8490 static void lpt_init_pch_refclk(struct drm_device *dev)
8491 {
8492         struct intel_encoder *encoder;
8493         bool has_vga = false;
8494
8495         for_each_intel_encoder(dev, encoder) {
8496                 switch (encoder->type) {
8497                 case INTEL_OUTPUT_ANALOG:
8498                         has_vga = true;
8499                         break;
8500                 default:
8501                         break;
8502                 }
8503         }
8504
8505         if (has_vga)
8506                 lpt_enable_clkout_dp(dev, true, true);
8507         else
8508                 lpt_disable_clkout_dp(dev);
8509 }
8510
8511 /*
8512  * Initialize reference clocks when the driver loads
8513  */
8514 void intel_init_pch_refclk(struct drm_device *dev)
8515 {
8516         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8517                 ironlake_init_pch_refclk(dev);
8518         else if (HAS_PCH_LPT(dev))
8519                 lpt_init_pch_refclk(dev);
8520 }
8521
8522 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8523 {
8524         struct drm_device *dev = crtc_state->base.crtc->dev;
8525         struct drm_i915_private *dev_priv = dev->dev_private;
8526         struct drm_atomic_state *state = crtc_state->base.state;
8527         struct drm_connector *connector;
8528         struct drm_connector_state *connector_state;
8529         struct intel_encoder *encoder;
8530         int num_connectors = 0, i;
8531         bool is_lvds = false;
8532
8533         for_each_connector_in_state(state, connector, connector_state, i) {
8534                 if (connector_state->crtc != crtc_state->base.crtc)
8535                         continue;
8536
8537                 encoder = to_intel_encoder(connector_state->best_encoder);
8538
8539                 switch (encoder->type) {
8540                 case INTEL_OUTPUT_LVDS:
8541                         is_lvds = true;
8542                         break;
8543                 default:
8544                         break;
8545                 }
8546                 num_connectors++;
8547         }
8548
8549         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8550                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8551                               dev_priv->vbt.lvds_ssc_freq);
8552                 return dev_priv->vbt.lvds_ssc_freq;
8553         }
8554
8555         return 120000;
8556 }
8557
8558 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8559 {
8560         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8562         int pipe = intel_crtc->pipe;
8563         uint32_t val;
8564
8565         val = 0;
8566
8567         switch (intel_crtc->config->pipe_bpp) {
8568         case 18:
8569                 val |= PIPECONF_6BPC;
8570                 break;
8571         case 24:
8572                 val |= PIPECONF_8BPC;
8573                 break;
8574         case 30:
8575                 val |= PIPECONF_10BPC;
8576                 break;
8577         case 36:
8578                 val |= PIPECONF_12BPC;
8579                 break;
8580         default:
8581                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8582                 BUG();
8583         }
8584
8585         if (intel_crtc->config->dither)
8586                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8587
8588         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8589                 val |= PIPECONF_INTERLACED_ILK;
8590         else
8591                 val |= PIPECONF_PROGRESSIVE;
8592
8593         if (intel_crtc->config->limited_color_range)
8594                 val |= PIPECONF_COLOR_RANGE_SELECT;
8595
8596         I915_WRITE(PIPECONF(pipe), val);
8597         POSTING_READ(PIPECONF(pipe));
8598 }
8599
8600 /*
8601  * Set up the pipe CSC unit.
8602  *
8603  * Currently only full range RGB to limited range RGB conversion
8604  * is supported, but eventually this should handle various
8605  * RGB<->YCbCr scenarios as well.
8606  */
8607 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8608 {
8609         struct drm_device *dev = crtc->dev;
8610         struct drm_i915_private *dev_priv = dev->dev_private;
8611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612         int pipe = intel_crtc->pipe;
8613         uint16_t coeff = 0x7800; /* 1.0 */
8614
8615         /*
8616          * TODO: Check what kind of values actually come out of the pipe
8617          * with these coeff/postoff values and adjust to get the best
8618          * accuracy. Perhaps we even need to take the bpc value into
8619          * consideration.
8620          */
8621
8622         if (intel_crtc->config->limited_color_range)
8623                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8624
8625         /*
8626          * GY/GU and RY/RU should be the other way around according
8627          * to BSpec, but reality doesn't agree. Just set them up in
8628          * a way that results in the correct picture.
8629          */
8630         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8631         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8632
8633         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8634         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8635
8636         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8637         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8638
8639         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8640         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8641         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8642
8643         if (INTEL_INFO(dev)->gen > 6) {
8644                 uint16_t postoff = 0;
8645
8646                 if (intel_crtc->config->limited_color_range)
8647                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8648
8649                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8650                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8651                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8652
8653                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8654         } else {
8655                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8656
8657                 if (intel_crtc->config->limited_color_range)
8658                         mode |= CSC_BLACK_SCREEN_OFFSET;
8659
8660                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8661         }
8662 }
8663
8664 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8665 {
8666         struct drm_device *dev = crtc->dev;
8667         struct drm_i915_private *dev_priv = dev->dev_private;
8668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8669         enum pipe pipe = intel_crtc->pipe;
8670         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8671         uint32_t val;
8672
8673         val = 0;
8674
8675         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8676                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8677
8678         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8679                 val |= PIPECONF_INTERLACED_ILK;
8680         else
8681                 val |= PIPECONF_PROGRESSIVE;
8682
8683         I915_WRITE(PIPECONF(cpu_transcoder), val);
8684         POSTING_READ(PIPECONF(cpu_transcoder));
8685
8686         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8687         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8688
8689         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8690                 val = 0;
8691
8692                 switch (intel_crtc->config->pipe_bpp) {
8693                 case 18:
8694                         val |= PIPEMISC_DITHER_6_BPC;
8695                         break;
8696                 case 24:
8697                         val |= PIPEMISC_DITHER_8_BPC;
8698                         break;
8699                 case 30:
8700                         val |= PIPEMISC_DITHER_10_BPC;
8701                         break;
8702                 case 36:
8703                         val |= PIPEMISC_DITHER_12_BPC;
8704                         break;
8705                 default:
8706                         /* Case prevented by pipe_config_set_bpp. */
8707                         BUG();
8708                 }
8709
8710                 if (intel_crtc->config->dither)
8711                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8712
8713                 I915_WRITE(PIPEMISC(pipe), val);
8714         }
8715 }
8716
8717 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8718                                     struct intel_crtc_state *crtc_state,
8719                                     intel_clock_t *clock,
8720                                     bool *has_reduced_clock,
8721                                     intel_clock_t *reduced_clock)
8722 {
8723         struct drm_device *dev = crtc->dev;
8724         struct drm_i915_private *dev_priv = dev->dev_private;
8725         int refclk;
8726         const intel_limit_t *limit;
8727         bool ret, is_lvds = false;
8728
8729         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8730
8731         refclk = ironlake_get_refclk(crtc_state);
8732
8733         /*
8734          * Returns a set of divisors for the desired target clock with the given
8735          * refclk, or FALSE.  The returned values represent the clock equation:
8736          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8737          */
8738         limit = intel_limit(crtc_state, refclk);
8739         ret = dev_priv->display.find_dpll(limit, crtc_state,
8740                                           crtc_state->port_clock,
8741                                           refclk, NULL, clock);
8742         if (!ret)
8743                 return false;
8744
8745         if (is_lvds && dev_priv->lvds_downclock_avail) {
8746                 /*
8747                  * Ensure we match the reduced clock's P to the target clock.
8748                  * If the clocks don't match, we can't switch the display clock
8749                  * by using the FP0/FP1. In such case we will disable the LVDS
8750                  * downclock feature.
8751                 */
8752                 *has_reduced_clock =
8753                         dev_priv->display.find_dpll(limit, crtc_state,
8754                                                     dev_priv->lvds_downclock,
8755                                                     refclk, clock,
8756                                                     reduced_clock);
8757         }
8758
8759         return true;
8760 }
8761
8762 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8763 {
8764         /*
8765          * Account for spread spectrum to avoid
8766          * oversubscribing the link. Max center spread
8767          * is 2.5%; use 5% for safety's sake.
8768          */
8769         u32 bps = target_clock * bpp * 21 / 20;
8770         return DIV_ROUND_UP(bps, link_bw * 8);
8771 }
8772
8773 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8774 {
8775         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8776 }
8777
8778 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8779                                       struct intel_crtc_state *crtc_state,
8780                                       u32 *fp,
8781                                       intel_clock_t *reduced_clock, u32 *fp2)
8782 {
8783         struct drm_crtc *crtc = &intel_crtc->base;
8784         struct drm_device *dev = crtc->dev;
8785         struct drm_i915_private *dev_priv = dev->dev_private;
8786         struct drm_atomic_state *state = crtc_state->base.state;
8787         struct drm_connector *connector;
8788         struct drm_connector_state *connector_state;
8789         struct intel_encoder *encoder;
8790         uint32_t dpll;
8791         int factor, num_connectors = 0, i;
8792         bool is_lvds = false, is_sdvo = false;
8793
8794         for_each_connector_in_state(state, connector, connector_state, i) {
8795                 if (connector_state->crtc != crtc_state->base.crtc)
8796                         continue;
8797
8798                 encoder = to_intel_encoder(connector_state->best_encoder);
8799
8800                 switch (encoder->type) {
8801                 case INTEL_OUTPUT_LVDS:
8802                         is_lvds = true;
8803                         break;
8804                 case INTEL_OUTPUT_SDVO:
8805                 case INTEL_OUTPUT_HDMI:
8806                         is_sdvo = true;
8807                         break;
8808                 default:
8809                         break;
8810                 }
8811
8812                 num_connectors++;
8813         }
8814
8815         /* Enable autotuning of the PLL clock (if permissible) */
8816         factor = 21;
8817         if (is_lvds) {
8818                 if ((intel_panel_use_ssc(dev_priv) &&
8819                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8820                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8821                         factor = 25;
8822         } else if (crtc_state->sdvo_tv_clock)
8823                 factor = 20;
8824
8825         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8826                 *fp |= FP_CB_TUNE;
8827
8828         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8829                 *fp2 |= FP_CB_TUNE;
8830
8831         dpll = 0;
8832
8833         if (is_lvds)
8834                 dpll |= DPLLB_MODE_LVDS;
8835         else
8836                 dpll |= DPLLB_MODE_DAC_SERIAL;
8837
8838         dpll |= (crtc_state->pixel_multiplier - 1)
8839                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8840
8841         if (is_sdvo)
8842                 dpll |= DPLL_SDVO_HIGH_SPEED;
8843         if (crtc_state->has_dp_encoder)
8844                 dpll |= DPLL_SDVO_HIGH_SPEED;
8845
8846         /* compute bitmask from p1 value */
8847         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8848         /* also FPA1 */
8849         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8850
8851         switch (crtc_state->dpll.p2) {
8852         case 5:
8853                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8854                 break;
8855         case 7:
8856                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8857                 break;
8858         case 10:
8859                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8860                 break;
8861         case 14:
8862                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8863                 break;
8864         }
8865
8866         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8867                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8868         else
8869                 dpll |= PLL_REF_INPUT_DREFCLK;
8870
8871         return dpll | DPLL_VCO_ENABLE;
8872 }
8873
8874 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8875                                        struct intel_crtc_state *crtc_state)
8876 {
8877         struct drm_device *dev = crtc->base.dev;
8878         intel_clock_t clock, reduced_clock;
8879         u32 dpll = 0, fp = 0, fp2 = 0;
8880         bool ok, has_reduced_clock = false;
8881         bool is_lvds = false;
8882         struct intel_shared_dpll *pll;
8883
8884         memset(&crtc_state->dpll_hw_state, 0,
8885                sizeof(crtc_state->dpll_hw_state));
8886
8887         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8888
8889         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8890              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8891
8892         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8893                                      &has_reduced_clock, &reduced_clock);
8894         if (!ok && !crtc_state->clock_set) {
8895                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8896                 return -EINVAL;
8897         }
8898         /* Compat-code for transition, will disappear. */
8899         if (!crtc_state->clock_set) {
8900                 crtc_state->dpll.n = clock.n;
8901                 crtc_state->dpll.m1 = clock.m1;
8902                 crtc_state->dpll.m2 = clock.m2;
8903                 crtc_state->dpll.p1 = clock.p1;
8904                 crtc_state->dpll.p2 = clock.p2;
8905         }
8906
8907         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8908         if (crtc_state->has_pch_encoder) {
8909                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8910                 if (has_reduced_clock)
8911                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8912
8913                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8914                                              &fp, &reduced_clock,
8915                                              has_reduced_clock ? &fp2 : NULL);
8916
8917                 crtc_state->dpll_hw_state.dpll = dpll;
8918                 crtc_state->dpll_hw_state.fp0 = fp;
8919                 if (has_reduced_clock)
8920                         crtc_state->dpll_hw_state.fp1 = fp2;
8921                 else
8922                         crtc_state->dpll_hw_state.fp1 = fp;
8923
8924                 pll = intel_get_shared_dpll(crtc, crtc_state);
8925                 if (pll == NULL) {
8926                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8927                                          pipe_name(crtc->pipe));
8928                         return -EINVAL;
8929                 }
8930         }
8931
8932         if (is_lvds && has_reduced_clock)
8933                 crtc->lowfreq_avail = true;
8934         else
8935                 crtc->lowfreq_avail = false;
8936
8937         return 0;
8938 }
8939
8940 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8941                                          struct intel_link_m_n *m_n)
8942 {
8943         struct drm_device *dev = crtc->base.dev;
8944         struct drm_i915_private *dev_priv = dev->dev_private;
8945         enum pipe pipe = crtc->pipe;
8946
8947         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8948         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8949         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8950                 & ~TU_SIZE_MASK;
8951         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8952         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8953                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954 }
8955
8956 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8957                                          enum transcoder transcoder,
8958                                          struct intel_link_m_n *m_n,
8959                                          struct intel_link_m_n *m2_n2)
8960 {
8961         struct drm_device *dev = crtc->base.dev;
8962         struct drm_i915_private *dev_priv = dev->dev_private;
8963         enum pipe pipe = crtc->pipe;
8964
8965         if (INTEL_INFO(dev)->gen >= 5) {
8966                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8967                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8968                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8969                         & ~TU_SIZE_MASK;
8970                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8971                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8972                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8973                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8974                  * gen < 8) and if DRRS is supported (to make sure the
8975                  * registers are not unnecessarily read).
8976                  */
8977                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8978                         crtc->config->has_drrs) {
8979                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8980                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8981                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8982                                         & ~TU_SIZE_MASK;
8983                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8984                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8985                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8986                 }
8987         } else {
8988                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8989                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8990                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8991                         & ~TU_SIZE_MASK;
8992                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8993                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8994                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8995         }
8996 }
8997
8998 void intel_dp_get_m_n(struct intel_crtc *crtc,
8999                       struct intel_crtc_state *pipe_config)
9000 {
9001         if (pipe_config->has_pch_encoder)
9002                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9003         else
9004                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9005                                              &pipe_config->dp_m_n,
9006                                              &pipe_config->dp_m2_n2);
9007 }
9008
9009 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9010                                         struct intel_crtc_state *pipe_config)
9011 {
9012         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9013                                      &pipe_config->fdi_m_n, NULL);
9014 }
9015
9016 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9017                                     struct intel_crtc_state *pipe_config)
9018 {
9019         struct drm_device *dev = crtc->base.dev;
9020         struct drm_i915_private *dev_priv = dev->dev_private;
9021         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9022         uint32_t ps_ctrl = 0;
9023         int id = -1;
9024         int i;
9025
9026         /* find scaler attached to this pipe */
9027         for (i = 0; i < crtc->num_scalers; i++) {
9028                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9029                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9030                         id = i;
9031                         pipe_config->pch_pfit.enabled = true;
9032                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9033                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9034                         break;
9035                 }
9036         }
9037
9038         scaler_state->scaler_id = id;
9039         if (id >= 0) {
9040                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9041         } else {
9042                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9043         }
9044 }
9045
9046 static void
9047 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9048                                  struct intel_initial_plane_config *plane_config)
9049 {
9050         struct drm_device *dev = crtc->base.dev;
9051         struct drm_i915_private *dev_priv = dev->dev_private;
9052         u32 val, base, offset, stride_mult, tiling;
9053         int pipe = crtc->pipe;
9054         int fourcc, pixel_format;
9055         unsigned int aligned_height;
9056         struct drm_framebuffer *fb;
9057         struct intel_framebuffer *intel_fb;
9058
9059         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9060         if (!intel_fb) {
9061                 DRM_DEBUG_KMS("failed to alloc fb\n");
9062                 return;
9063         }
9064
9065         fb = &intel_fb->base;
9066
9067         val = I915_READ(PLANE_CTL(pipe, 0));
9068         if (!(val & PLANE_CTL_ENABLE))
9069                 goto error;
9070
9071         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9072         fourcc = skl_format_to_fourcc(pixel_format,
9073                                       val & PLANE_CTL_ORDER_RGBX,
9074                                       val & PLANE_CTL_ALPHA_MASK);
9075         fb->pixel_format = fourcc;
9076         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9077
9078         tiling = val & PLANE_CTL_TILED_MASK;
9079         switch (tiling) {
9080         case PLANE_CTL_TILED_LINEAR:
9081                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9082                 break;
9083         case PLANE_CTL_TILED_X:
9084                 plane_config->tiling = I915_TILING_X;
9085                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9086                 break;
9087         case PLANE_CTL_TILED_Y:
9088                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9089                 break;
9090         case PLANE_CTL_TILED_YF:
9091                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9092                 break;
9093         default:
9094                 MISSING_CASE(tiling);
9095                 goto error;
9096         }
9097
9098         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9099         plane_config->base = base;
9100
9101         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9102
9103         val = I915_READ(PLANE_SIZE(pipe, 0));
9104         fb->height = ((val >> 16) & 0xfff) + 1;
9105         fb->width = ((val >> 0) & 0x1fff) + 1;
9106
9107         val = I915_READ(PLANE_STRIDE(pipe, 0));
9108         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9109                                                 fb->pixel_format);
9110         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9111
9112         aligned_height = intel_fb_align_height(dev, fb->height,
9113                                                fb->pixel_format,
9114                                                fb->modifier[0]);
9115
9116         plane_config->size = fb->pitches[0] * aligned_height;
9117
9118         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9119                       pipe_name(pipe), fb->width, fb->height,
9120                       fb->bits_per_pixel, base, fb->pitches[0],
9121                       plane_config->size);
9122
9123         plane_config->fb = intel_fb;
9124         return;
9125
9126 error:
9127         kfree(fb);
9128 }
9129
9130 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9131                                      struct intel_crtc_state *pipe_config)
9132 {
9133         struct drm_device *dev = crtc->base.dev;
9134         struct drm_i915_private *dev_priv = dev->dev_private;
9135         uint32_t tmp;
9136
9137         tmp = I915_READ(PF_CTL(crtc->pipe));
9138
9139         if (tmp & PF_ENABLE) {
9140                 pipe_config->pch_pfit.enabled = true;
9141                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9142                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9143
9144                 /* We currently do not free assignements of panel fitters on
9145                  * ivb/hsw (since we don't use the higher upscaling modes which
9146                  * differentiates them) so just WARN about this case for now. */
9147                 if (IS_GEN7(dev)) {
9148                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9149                                 PF_PIPE_SEL_IVB(crtc->pipe));
9150                 }
9151         }
9152 }
9153
9154 static void
9155 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9156                                   struct intel_initial_plane_config *plane_config)
9157 {
9158         struct drm_device *dev = crtc->base.dev;
9159         struct drm_i915_private *dev_priv = dev->dev_private;
9160         u32 val, base, offset;
9161         int pipe = crtc->pipe;
9162         int fourcc, pixel_format;
9163         unsigned int aligned_height;
9164         struct drm_framebuffer *fb;
9165         struct intel_framebuffer *intel_fb;
9166
9167         val = I915_READ(DSPCNTR(pipe));
9168         if (!(val & DISPLAY_PLANE_ENABLE))
9169                 return;
9170
9171         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9172         if (!intel_fb) {
9173                 DRM_DEBUG_KMS("failed to alloc fb\n");
9174                 return;
9175         }
9176
9177         fb = &intel_fb->base;
9178
9179         if (INTEL_INFO(dev)->gen >= 4) {
9180                 if (val & DISPPLANE_TILED) {
9181                         plane_config->tiling = I915_TILING_X;
9182                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9183                 }
9184         }
9185
9186         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9187         fourcc = i9xx_format_to_fourcc(pixel_format);
9188         fb->pixel_format = fourcc;
9189         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9190
9191         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9192         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9193                 offset = I915_READ(DSPOFFSET(pipe));
9194         } else {
9195                 if (plane_config->tiling)
9196                         offset = I915_READ(DSPTILEOFF(pipe));
9197                 else
9198                         offset = I915_READ(DSPLINOFF(pipe));
9199         }
9200         plane_config->base = base;
9201
9202         val = I915_READ(PIPESRC(pipe));
9203         fb->width = ((val >> 16) & 0xfff) + 1;
9204         fb->height = ((val >> 0) & 0xfff) + 1;
9205
9206         val = I915_READ(DSPSTRIDE(pipe));
9207         fb->pitches[0] = val & 0xffffffc0;
9208
9209         aligned_height = intel_fb_align_height(dev, fb->height,
9210                                                fb->pixel_format,
9211                                                fb->modifier[0]);
9212
9213         plane_config->size = fb->pitches[0] * aligned_height;
9214
9215         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9216                       pipe_name(pipe), fb->width, fb->height,
9217                       fb->bits_per_pixel, base, fb->pitches[0],
9218                       plane_config->size);
9219
9220         plane_config->fb = intel_fb;
9221 }
9222
9223 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9224                                      struct intel_crtc_state *pipe_config)
9225 {
9226         struct drm_device *dev = crtc->base.dev;
9227         struct drm_i915_private *dev_priv = dev->dev_private;
9228         uint32_t tmp;
9229
9230         if (!intel_display_power_is_enabled(dev_priv,
9231                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9232                 return false;
9233
9234         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9235         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9236
9237         tmp = I915_READ(PIPECONF(crtc->pipe));
9238         if (!(tmp & PIPECONF_ENABLE))
9239                 return false;
9240
9241         switch (tmp & PIPECONF_BPC_MASK) {
9242         case PIPECONF_6BPC:
9243                 pipe_config->pipe_bpp = 18;
9244                 break;
9245         case PIPECONF_8BPC:
9246                 pipe_config->pipe_bpp = 24;
9247                 break;
9248         case PIPECONF_10BPC:
9249                 pipe_config->pipe_bpp = 30;
9250                 break;
9251         case PIPECONF_12BPC:
9252                 pipe_config->pipe_bpp = 36;
9253                 break;
9254         default:
9255                 break;
9256         }
9257
9258         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9259                 pipe_config->limited_color_range = true;
9260
9261         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9262                 struct intel_shared_dpll *pll;
9263
9264                 pipe_config->has_pch_encoder = true;
9265
9266                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9267                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9268                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9269
9270                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9271
9272                 if (HAS_PCH_IBX(dev_priv->dev)) {
9273                         pipe_config->shared_dpll =
9274                                 (enum intel_dpll_id) crtc->pipe;
9275                 } else {
9276                         tmp = I915_READ(PCH_DPLL_SEL);
9277                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9278                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9279                         else
9280                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9281                 }
9282
9283                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9284
9285                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9286                                            &pipe_config->dpll_hw_state));
9287
9288                 tmp = pipe_config->dpll_hw_state.dpll;
9289                 pipe_config->pixel_multiplier =
9290                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9291                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9292
9293                 ironlake_pch_clock_get(crtc, pipe_config);
9294         } else {
9295                 pipe_config->pixel_multiplier = 1;
9296         }
9297
9298         intel_get_pipe_timings(crtc, pipe_config);
9299
9300         ironlake_get_pfit_config(crtc, pipe_config);
9301
9302         return true;
9303 }
9304
9305 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9306 {
9307         struct drm_device *dev = dev_priv->dev;
9308         struct intel_crtc *crtc;
9309
9310         for_each_intel_crtc(dev, crtc)
9311                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9312                      pipe_name(crtc->pipe));
9313
9314         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9315         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9316         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9317         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9318         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9319         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9320              "CPU PWM1 enabled\n");
9321         if (IS_HASWELL(dev))
9322                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9323                      "CPU PWM2 enabled\n");
9324         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9325              "PCH PWM1 enabled\n");
9326         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9327              "Utility pin enabled\n");
9328         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9329
9330         /*
9331          * In theory we can still leave IRQs enabled, as long as only the HPD
9332          * interrupts remain enabled. We used to check for that, but since it's
9333          * gen-specific and since we only disable LCPLL after we fully disable
9334          * the interrupts, the check below should be enough.
9335          */
9336         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9337 }
9338
9339 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9340 {
9341         struct drm_device *dev = dev_priv->dev;
9342
9343         if (IS_HASWELL(dev))
9344                 return I915_READ(D_COMP_HSW);
9345         else
9346                 return I915_READ(D_COMP_BDW);
9347 }
9348
9349 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9350 {
9351         struct drm_device *dev = dev_priv->dev;
9352
9353         if (IS_HASWELL(dev)) {
9354                 mutex_lock(&dev_priv->rps.hw_lock);
9355                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9356                                             val))
9357                         DRM_ERROR("Failed to write to D_COMP\n");
9358                 mutex_unlock(&dev_priv->rps.hw_lock);
9359         } else {
9360                 I915_WRITE(D_COMP_BDW, val);
9361                 POSTING_READ(D_COMP_BDW);
9362         }
9363 }
9364
9365 /*
9366  * This function implements pieces of two sequences from BSpec:
9367  * - Sequence for display software to disable LCPLL
9368  * - Sequence for display software to allow package C8+
9369  * The steps implemented here are just the steps that actually touch the LCPLL
9370  * register. Callers should take care of disabling all the display engine
9371  * functions, doing the mode unset, fixing interrupts, etc.
9372  */
9373 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9374                               bool switch_to_fclk, bool allow_power_down)
9375 {
9376         uint32_t val;
9377
9378         assert_can_disable_lcpll(dev_priv);
9379
9380         val = I915_READ(LCPLL_CTL);
9381
9382         if (switch_to_fclk) {
9383                 val |= LCPLL_CD_SOURCE_FCLK;
9384                 I915_WRITE(LCPLL_CTL, val);
9385
9386                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9387                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9388                         DRM_ERROR("Switching to FCLK failed\n");
9389
9390                 val = I915_READ(LCPLL_CTL);
9391         }
9392
9393         val |= LCPLL_PLL_DISABLE;
9394         I915_WRITE(LCPLL_CTL, val);
9395         POSTING_READ(LCPLL_CTL);
9396
9397         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9398                 DRM_ERROR("LCPLL still locked\n");
9399
9400         val = hsw_read_dcomp(dev_priv);
9401         val |= D_COMP_COMP_DISABLE;
9402         hsw_write_dcomp(dev_priv, val);
9403         ndelay(100);
9404
9405         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9406                      1))
9407                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9408
9409         if (allow_power_down) {
9410                 val = I915_READ(LCPLL_CTL);
9411                 val |= LCPLL_POWER_DOWN_ALLOW;
9412                 I915_WRITE(LCPLL_CTL, val);
9413                 POSTING_READ(LCPLL_CTL);
9414         }
9415 }
9416
9417 /*
9418  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9419  * source.
9420  */
9421 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9422 {
9423         uint32_t val;
9424
9425         val = I915_READ(LCPLL_CTL);
9426
9427         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9428                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9429                 return;
9430
9431         /*
9432          * Make sure we're not on PC8 state before disabling PC8, otherwise
9433          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9434          */
9435         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9436
9437         if (val & LCPLL_POWER_DOWN_ALLOW) {
9438                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9439                 I915_WRITE(LCPLL_CTL, val);
9440                 POSTING_READ(LCPLL_CTL);
9441         }
9442
9443         val = hsw_read_dcomp(dev_priv);
9444         val |= D_COMP_COMP_FORCE;
9445         val &= ~D_COMP_COMP_DISABLE;
9446         hsw_write_dcomp(dev_priv, val);
9447
9448         val = I915_READ(LCPLL_CTL);
9449         val &= ~LCPLL_PLL_DISABLE;
9450         I915_WRITE(LCPLL_CTL, val);
9451
9452         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9453                 DRM_ERROR("LCPLL not locked yet\n");
9454
9455         if (val & LCPLL_CD_SOURCE_FCLK) {
9456                 val = I915_READ(LCPLL_CTL);
9457                 val &= ~LCPLL_CD_SOURCE_FCLK;
9458                 I915_WRITE(LCPLL_CTL, val);
9459
9460                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9461                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9462                         DRM_ERROR("Switching back to LCPLL failed\n");
9463         }
9464
9465         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9466         intel_update_cdclk(dev_priv->dev);
9467 }
9468
9469 /*
9470  * Package states C8 and deeper are really deep PC states that can only be
9471  * reached when all the devices on the system allow it, so even if the graphics
9472  * device allows PC8+, it doesn't mean the system will actually get to these
9473  * states. Our driver only allows PC8+ when going into runtime PM.
9474  *
9475  * The requirements for PC8+ are that all the outputs are disabled, the power
9476  * well is disabled and most interrupts are disabled, and these are also
9477  * requirements for runtime PM. When these conditions are met, we manually do
9478  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9479  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9480  * hang the machine.
9481  *
9482  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9483  * the state of some registers, so when we come back from PC8+ we need to
9484  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9485  * need to take care of the registers kept by RC6. Notice that this happens even
9486  * if we don't put the device in PCI D3 state (which is what currently happens
9487  * because of the runtime PM support).
9488  *
9489  * For more, read "Display Sequences for Package C8" on the hardware
9490  * documentation.
9491  */
9492 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9493 {
9494         struct drm_device *dev = dev_priv->dev;
9495         uint32_t val;
9496
9497         DRM_DEBUG_KMS("Enabling package C8+\n");
9498
9499         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9500                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9501                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9502                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9503         }
9504
9505         lpt_disable_clkout_dp(dev);
9506         hsw_disable_lcpll(dev_priv, true, true);
9507 }
9508
9509 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9510 {
9511         struct drm_device *dev = dev_priv->dev;
9512         uint32_t val;
9513
9514         DRM_DEBUG_KMS("Disabling package C8+\n");
9515
9516         hsw_restore_lcpll(dev_priv);
9517         lpt_init_pch_refclk(dev);
9518
9519         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9520                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9521                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9522                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9523         }
9524
9525         intel_prepare_ddi(dev);
9526 }
9527
9528 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9529 {
9530         struct drm_device *dev = old_state->dev;
9531         struct drm_i915_private *dev_priv = dev->dev_private;
9532         int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9533         int req_cdclk;
9534
9535         /* see the comment in valleyview_modeset_global_resources */
9536         if (WARN_ON(max_pixclk < 0))
9537                 return;
9538
9539         req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9540
9541         if (req_cdclk != dev_priv->cdclk_freq)
9542                 broxton_set_cdclk(dev, req_cdclk);
9543 }
9544
9545 /* compute the max rate for new configuration */
9546 static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9547 {
9548         struct drm_device *dev = dev_priv->dev;
9549         struct intel_crtc *intel_crtc;
9550         struct drm_crtc *crtc;
9551         int max_pixel_rate = 0;
9552         int pixel_rate;
9553
9554         for_each_crtc(dev, crtc) {
9555                 if (!crtc->state->enable)
9556                         continue;
9557
9558                 intel_crtc = to_intel_crtc(crtc);
9559                 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9560
9561                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9562                 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9563                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9564
9565                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9566         }
9567
9568         return max_pixel_rate;
9569 }
9570
9571 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9572 {
9573         struct drm_i915_private *dev_priv = dev->dev_private;
9574         uint32_t val, data;
9575         int ret;
9576
9577         if (WARN((I915_READ(LCPLL_CTL) &
9578                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9579                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9580                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9581                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9582                  "trying to change cdclk frequency with cdclk not enabled\n"))
9583                 return;
9584
9585         mutex_lock(&dev_priv->rps.hw_lock);
9586         ret = sandybridge_pcode_write(dev_priv,
9587                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9588         mutex_unlock(&dev_priv->rps.hw_lock);
9589         if (ret) {
9590                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9591                 return;
9592         }
9593
9594         val = I915_READ(LCPLL_CTL);
9595         val |= LCPLL_CD_SOURCE_FCLK;
9596         I915_WRITE(LCPLL_CTL, val);
9597
9598         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9599                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9600                 DRM_ERROR("Switching to FCLK failed\n");
9601
9602         val = I915_READ(LCPLL_CTL);
9603         val &= ~LCPLL_CLK_FREQ_MASK;
9604
9605         switch (cdclk) {
9606         case 450000:
9607                 val |= LCPLL_CLK_FREQ_450;
9608                 data = 0;
9609                 break;
9610         case 540000:
9611                 val |= LCPLL_CLK_FREQ_54O_BDW;
9612                 data = 1;
9613                 break;
9614         case 337500:
9615                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9616                 data = 2;
9617                 break;
9618         case 675000:
9619                 val |= LCPLL_CLK_FREQ_675_BDW;
9620                 data = 3;
9621                 break;
9622         default:
9623                 WARN(1, "invalid cdclk frequency\n");
9624                 return;
9625         }
9626
9627         I915_WRITE(LCPLL_CTL, val);
9628
9629         val = I915_READ(LCPLL_CTL);
9630         val &= ~LCPLL_CD_SOURCE_FCLK;
9631         I915_WRITE(LCPLL_CTL, val);
9632
9633         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9634                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9635                 DRM_ERROR("Switching back to LCPLL failed\n");
9636
9637         mutex_lock(&dev_priv->rps.hw_lock);
9638         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9639         mutex_unlock(&dev_priv->rps.hw_lock);
9640
9641         intel_update_cdclk(dev);
9642
9643         WARN(cdclk != dev_priv->cdclk_freq,
9644              "cdclk requested %d kHz but got %d kHz\n",
9645              cdclk, dev_priv->cdclk_freq);
9646 }
9647
9648 static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9649                               int max_pixel_rate)
9650 {
9651         int cdclk;
9652
9653         /*
9654          * FIXME should also account for plane ratio
9655          * once 64bpp pixel formats are supported.
9656          */
9657         if (max_pixel_rate > 540000)
9658                 cdclk = 675000;
9659         else if (max_pixel_rate > 450000)
9660                 cdclk = 540000;
9661         else if (max_pixel_rate > 337500)
9662                 cdclk = 450000;
9663         else
9664                 cdclk = 337500;
9665
9666         /*
9667          * FIXME move the cdclk caclulation to
9668          * compute_config() so we can fail gracegully.
9669          */
9670         if (cdclk > dev_priv->max_cdclk_freq) {
9671                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9672                           cdclk, dev_priv->max_cdclk_freq);
9673                 cdclk = dev_priv->max_cdclk_freq;
9674         }
9675
9676         return cdclk;
9677 }
9678
9679 static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9680 {
9681         struct drm_i915_private *dev_priv = to_i915(state->dev);
9682         struct drm_crtc *crtc;
9683         struct drm_crtc_state *crtc_state;
9684         int max_pixclk = ilk_max_pixel_rate(dev_priv);
9685         int cdclk, i;
9686
9687         cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9688
9689         if (cdclk == dev_priv->cdclk_freq)
9690                 return 0;
9691
9692         /* add all active pipes to the state */
9693         for_each_crtc(state->dev, crtc) {
9694                 if (!crtc->state->enable)
9695                         continue;
9696
9697                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9698                 if (IS_ERR(crtc_state))
9699                         return PTR_ERR(crtc_state);
9700         }
9701
9702         /* disable/enable all currently active pipes while we change cdclk */
9703         for_each_crtc_in_state(state, crtc, crtc_state, i)
9704                 if (crtc_state->enable)
9705                         crtc_state->mode_changed = true;
9706
9707         return 0;
9708 }
9709
9710 static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9711 {
9712         struct drm_device *dev = state->dev;
9713         struct drm_i915_private *dev_priv = dev->dev_private;
9714         int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9715         int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9716
9717         if (req_cdclk != dev_priv->cdclk_freq)
9718                 broadwell_set_cdclk(dev, req_cdclk);
9719 }
9720
9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9722                                       struct intel_crtc_state *crtc_state)
9723 {
9724         if (!intel_ddi_pll_select(crtc, crtc_state))
9725                 return -EINVAL;
9726
9727         crtc->lowfreq_avail = false;
9728
9729         return 0;
9730 }
9731
9732 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9733                                 enum port port,
9734                                 struct intel_crtc_state *pipe_config)
9735 {
9736         switch (port) {
9737         case PORT_A:
9738                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9739                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9740                 break;
9741         case PORT_B:
9742                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9743                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9744                 break;
9745         case PORT_C:
9746                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9747                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9748                 break;
9749         default:
9750                 DRM_ERROR("Incorrect port type\n");
9751         }
9752 }
9753
9754 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9755                                 enum port port,
9756                                 struct intel_crtc_state *pipe_config)
9757 {
9758         u32 temp, dpll_ctl1;
9759
9760         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9761         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9762
9763         switch (pipe_config->ddi_pll_sel) {
9764         case SKL_DPLL0:
9765                 /*
9766                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9767                  * of the shared DPLL framework and thus needs to be read out
9768                  * separately
9769                  */
9770                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9771                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9772                 break;
9773         case SKL_DPLL1:
9774                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9775                 break;
9776         case SKL_DPLL2:
9777                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9778                 break;
9779         case SKL_DPLL3:
9780                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9781                 break;
9782         }
9783 }
9784
9785 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9786                                 enum port port,
9787                                 struct intel_crtc_state *pipe_config)
9788 {
9789         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9790
9791         switch (pipe_config->ddi_pll_sel) {
9792         case PORT_CLK_SEL_WRPLL1:
9793                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9794                 break;
9795         case PORT_CLK_SEL_WRPLL2:
9796                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9797                 break;
9798         }
9799 }
9800
9801 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9802                                        struct intel_crtc_state *pipe_config)
9803 {
9804         struct drm_device *dev = crtc->base.dev;
9805         struct drm_i915_private *dev_priv = dev->dev_private;
9806         struct intel_shared_dpll *pll;
9807         enum port port;
9808         uint32_t tmp;
9809
9810         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9811
9812         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9813
9814         if (IS_SKYLAKE(dev))
9815                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9816         else if (IS_BROXTON(dev))
9817                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9818         else
9819                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9820
9821         if (pipe_config->shared_dpll >= 0) {
9822                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9823
9824                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9825                                            &pipe_config->dpll_hw_state));
9826         }
9827
9828         /*
9829          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9830          * DDI E. So just check whether this pipe is wired to DDI E and whether
9831          * the PCH transcoder is on.
9832          */
9833         if (INTEL_INFO(dev)->gen < 9 &&
9834             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9835                 pipe_config->has_pch_encoder = true;
9836
9837                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9838                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9839                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9840
9841                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9842         }
9843 }
9844
9845 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9846                                     struct intel_crtc_state *pipe_config)
9847 {
9848         struct drm_device *dev = crtc->base.dev;
9849         struct drm_i915_private *dev_priv = dev->dev_private;
9850         enum intel_display_power_domain pfit_domain;
9851         uint32_t tmp;
9852
9853         if (!intel_display_power_is_enabled(dev_priv,
9854                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9855                 return false;
9856
9857         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9858         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9859
9860         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9861         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9862                 enum pipe trans_edp_pipe;
9863                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9864                 default:
9865                         WARN(1, "unknown pipe linked to edp transcoder\n");
9866                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9867                 case TRANS_DDI_EDP_INPUT_A_ON:
9868                         trans_edp_pipe = PIPE_A;
9869                         break;
9870                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9871                         trans_edp_pipe = PIPE_B;
9872                         break;
9873                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9874                         trans_edp_pipe = PIPE_C;
9875                         break;
9876                 }
9877
9878                 if (trans_edp_pipe == crtc->pipe)
9879                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9880         }
9881
9882         if (!intel_display_power_is_enabled(dev_priv,
9883                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9884                 return false;
9885
9886         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9887         if (!(tmp & PIPECONF_ENABLE))
9888                 return false;
9889
9890         haswell_get_ddi_port_state(crtc, pipe_config);
9891
9892         intel_get_pipe_timings(crtc, pipe_config);
9893
9894         if (INTEL_INFO(dev)->gen >= 9) {
9895                 skl_init_scalers(dev, crtc, pipe_config);
9896         }
9897
9898         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9899
9900         if (INTEL_INFO(dev)->gen >= 9) {
9901                 pipe_config->scaler_state.scaler_id = -1;
9902                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9903         }
9904
9905         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9906                 if (INTEL_INFO(dev)->gen == 9)
9907                         skylake_get_pfit_config(crtc, pipe_config);
9908                 else if (INTEL_INFO(dev)->gen < 9)
9909                         ironlake_get_pfit_config(crtc, pipe_config);
9910                 else
9911                         MISSING_CASE(INTEL_INFO(dev)->gen);
9912         }
9913
9914         if (IS_HASWELL(dev))
9915                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9916                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9917
9918         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9919                 pipe_config->pixel_multiplier =
9920                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9921         } else {
9922                 pipe_config->pixel_multiplier = 1;
9923         }
9924
9925         return true;
9926 }
9927
9928 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9929 {
9930         struct drm_device *dev = crtc->dev;
9931         struct drm_i915_private *dev_priv = dev->dev_private;
9932         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933         uint32_t cntl = 0, size = 0;
9934
9935         if (base) {
9936                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9937                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9938                 unsigned int stride = roundup_pow_of_two(width) * 4;
9939
9940                 switch (stride) {
9941                 default:
9942                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9943                                   width, stride);
9944                         stride = 256;
9945                         /* fallthrough */
9946                 case 256:
9947                 case 512:
9948                 case 1024:
9949                 case 2048:
9950                         break;
9951                 }
9952
9953                 cntl |= CURSOR_ENABLE |
9954                         CURSOR_GAMMA_ENABLE |
9955                         CURSOR_FORMAT_ARGB |
9956                         CURSOR_STRIDE(stride);
9957
9958                 size = (height << 12) | width;
9959         }
9960
9961         if (intel_crtc->cursor_cntl != 0 &&
9962             (intel_crtc->cursor_base != base ||
9963              intel_crtc->cursor_size != size ||
9964              intel_crtc->cursor_cntl != cntl)) {
9965                 /* On these chipsets we can only modify the base/size/stride
9966                  * whilst the cursor is disabled.
9967                  */
9968                 I915_WRITE(_CURACNTR, 0);
9969                 POSTING_READ(_CURACNTR);
9970                 intel_crtc->cursor_cntl = 0;
9971         }
9972
9973         if (intel_crtc->cursor_base != base) {
9974                 I915_WRITE(_CURABASE, base);
9975                 intel_crtc->cursor_base = base;
9976         }
9977
9978         if (intel_crtc->cursor_size != size) {
9979                 I915_WRITE(CURSIZE, size);
9980                 intel_crtc->cursor_size = size;
9981         }
9982
9983         if (intel_crtc->cursor_cntl != cntl) {
9984                 I915_WRITE(_CURACNTR, cntl);
9985                 POSTING_READ(_CURACNTR);
9986                 intel_crtc->cursor_cntl = cntl;
9987         }
9988 }
9989
9990 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9991 {
9992         struct drm_device *dev = crtc->dev;
9993         struct drm_i915_private *dev_priv = dev->dev_private;
9994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9995         int pipe = intel_crtc->pipe;
9996         uint32_t cntl;
9997
9998         cntl = 0;
9999         if (base) {
10000                 cntl = MCURSOR_GAMMA_ENABLE;
10001                 switch (intel_crtc->base.cursor->state->crtc_w) {
10002                         case 64:
10003                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10004                                 break;
10005                         case 128:
10006                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10007                                 break;
10008                         case 256:
10009                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10010                                 break;
10011                         default:
10012                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10013                                 return;
10014                 }
10015                 cntl |= pipe << 28; /* Connect to correct pipe */
10016
10017                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10018                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10019         }
10020
10021         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10022                 cntl |= CURSOR_ROTATE_180;
10023
10024         if (intel_crtc->cursor_cntl != cntl) {
10025                 I915_WRITE(CURCNTR(pipe), cntl);
10026                 POSTING_READ(CURCNTR(pipe));
10027                 intel_crtc->cursor_cntl = cntl;
10028         }
10029
10030         /* and commit changes on next vblank */
10031         I915_WRITE(CURBASE(pipe), base);
10032         POSTING_READ(CURBASE(pipe));
10033
10034         intel_crtc->cursor_base = base;
10035 }
10036
10037 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10038 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10039                                      bool on)
10040 {
10041         struct drm_device *dev = crtc->dev;
10042         struct drm_i915_private *dev_priv = dev->dev_private;
10043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10044         int pipe = intel_crtc->pipe;
10045         int x = crtc->cursor_x;
10046         int y = crtc->cursor_y;
10047         u32 base = 0, pos = 0;
10048
10049         if (on)
10050                 base = intel_crtc->cursor_addr;
10051
10052         if (x >= intel_crtc->config->pipe_src_w)
10053                 base = 0;
10054
10055         if (y >= intel_crtc->config->pipe_src_h)
10056                 base = 0;
10057
10058         if (x < 0) {
10059                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10060                         base = 0;
10061
10062                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10063                 x = -x;
10064         }
10065         pos |= x << CURSOR_X_SHIFT;
10066
10067         if (y < 0) {
10068                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10069                         base = 0;
10070
10071                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10072                 y = -y;
10073         }
10074         pos |= y << CURSOR_Y_SHIFT;
10075
10076         if (base == 0 && intel_crtc->cursor_base == 0)
10077                 return;
10078
10079         I915_WRITE(CURPOS(pipe), pos);
10080
10081         /* ILK+ do this automagically */
10082         if (HAS_GMCH_DISPLAY(dev) &&
10083             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10084                 base += (intel_crtc->base.cursor->state->crtc_h *
10085                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10086         }
10087
10088         if (IS_845G(dev) || IS_I865G(dev))
10089                 i845_update_cursor(crtc, base);
10090         else
10091                 i9xx_update_cursor(crtc, base);
10092 }
10093
10094 static bool cursor_size_ok(struct drm_device *dev,
10095                            uint32_t width, uint32_t height)
10096 {
10097         if (width == 0 || height == 0)
10098                 return false;
10099
10100         /*
10101          * 845g/865g are special in that they are only limited by
10102          * the width of their cursors, the height is arbitrary up to
10103          * the precision of the register. Everything else requires
10104          * square cursors, limited to a few power-of-two sizes.
10105          */
10106         if (IS_845G(dev) || IS_I865G(dev)) {
10107                 if ((width & 63) != 0)
10108                         return false;
10109
10110                 if (width > (IS_845G(dev) ? 64 : 512))
10111                         return false;
10112
10113                 if (height > 1023)
10114                         return false;
10115         } else {
10116                 switch (width | height) {
10117                 case 256:
10118                 case 128:
10119                         if (IS_GEN2(dev))
10120                                 return false;
10121                 case 64:
10122                         break;
10123                 default:
10124                         return false;
10125                 }
10126         }
10127
10128         return true;
10129 }
10130
10131 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10132                                  u16 *blue, uint32_t start, uint32_t size)
10133 {
10134         int end = (start + size > 256) ? 256 : start + size, i;
10135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10136
10137         for (i = start; i < end; i++) {
10138                 intel_crtc->lut_r[i] = red[i] >> 8;
10139                 intel_crtc->lut_g[i] = green[i] >> 8;
10140                 intel_crtc->lut_b[i] = blue[i] >> 8;
10141         }
10142
10143         intel_crtc_load_lut(crtc);
10144 }
10145
10146 /* VESA 640x480x72Hz mode to set on the pipe */
10147 static struct drm_display_mode load_detect_mode = {
10148         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10149                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10150 };
10151
10152 struct drm_framebuffer *
10153 __intel_framebuffer_create(struct drm_device *dev,
10154                            struct drm_mode_fb_cmd2 *mode_cmd,
10155                            struct drm_i915_gem_object *obj)
10156 {
10157         struct intel_framebuffer *intel_fb;
10158         int ret;
10159
10160         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10161         if (!intel_fb) {
10162                 drm_gem_object_unreference(&obj->base);
10163                 return ERR_PTR(-ENOMEM);
10164         }
10165
10166         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10167         if (ret)
10168                 goto err;
10169
10170         return &intel_fb->base;
10171 err:
10172         drm_gem_object_unreference(&obj->base);
10173         kfree(intel_fb);
10174
10175         return ERR_PTR(ret);
10176 }
10177
10178 static struct drm_framebuffer *
10179 intel_framebuffer_create(struct drm_device *dev,
10180                          struct drm_mode_fb_cmd2 *mode_cmd,
10181                          struct drm_i915_gem_object *obj)
10182 {
10183         struct drm_framebuffer *fb;
10184         int ret;
10185
10186         ret = i915_mutex_lock_interruptible(dev);
10187         if (ret)
10188                 return ERR_PTR(ret);
10189         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10190         mutex_unlock(&dev->struct_mutex);
10191
10192         return fb;
10193 }
10194
10195 static u32
10196 intel_framebuffer_pitch_for_width(int width, int bpp)
10197 {
10198         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10199         return ALIGN(pitch, 64);
10200 }
10201
10202 static u32
10203 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10204 {
10205         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10206         return PAGE_ALIGN(pitch * mode->vdisplay);
10207 }
10208
10209 static struct drm_framebuffer *
10210 intel_framebuffer_create_for_mode(struct drm_device *dev,
10211                                   struct drm_display_mode *mode,
10212                                   int depth, int bpp)
10213 {
10214         struct drm_i915_gem_object *obj;
10215         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10216
10217         obj = i915_gem_alloc_object(dev,
10218                                     intel_framebuffer_size_for_mode(mode, bpp));
10219         if (obj == NULL)
10220                 return ERR_PTR(-ENOMEM);
10221
10222         mode_cmd.width = mode->hdisplay;
10223         mode_cmd.height = mode->vdisplay;
10224         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10225                                                                 bpp);
10226         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10227
10228         return intel_framebuffer_create(dev, &mode_cmd, obj);
10229 }
10230
10231 static struct drm_framebuffer *
10232 mode_fits_in_fbdev(struct drm_device *dev,
10233                    struct drm_display_mode *mode)
10234 {
10235 #ifdef CONFIG_DRM_I915_FBDEV
10236         struct drm_i915_private *dev_priv = dev->dev_private;
10237         struct drm_i915_gem_object *obj;
10238         struct drm_framebuffer *fb;
10239
10240         if (!dev_priv->fbdev)
10241                 return NULL;
10242
10243         if (!dev_priv->fbdev->fb)
10244                 return NULL;
10245
10246         obj = dev_priv->fbdev->fb->obj;
10247         BUG_ON(!obj);
10248
10249         fb = &dev_priv->fbdev->fb->base;
10250         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10251                                                                fb->bits_per_pixel))
10252                 return NULL;
10253
10254         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10255                 return NULL;
10256
10257         return fb;
10258 #else
10259         return NULL;
10260 #endif
10261 }
10262
10263 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10264                                            struct drm_crtc *crtc,
10265                                            struct drm_display_mode *mode,
10266                                            struct drm_framebuffer *fb,
10267                                            int x, int y)
10268 {
10269         struct drm_plane_state *plane_state;
10270         int hdisplay, vdisplay;
10271         int ret;
10272
10273         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10274         if (IS_ERR(plane_state))
10275                 return PTR_ERR(plane_state);
10276
10277         if (mode)
10278                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10279         else
10280                 hdisplay = vdisplay = 0;
10281
10282         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10283         if (ret)
10284                 return ret;
10285         drm_atomic_set_fb_for_plane(plane_state, fb);
10286         plane_state->crtc_x = 0;
10287         plane_state->crtc_y = 0;
10288         plane_state->crtc_w = hdisplay;
10289         plane_state->crtc_h = vdisplay;
10290         plane_state->src_x = x << 16;
10291         plane_state->src_y = y << 16;
10292         plane_state->src_w = hdisplay << 16;
10293         plane_state->src_h = vdisplay << 16;
10294
10295         return 0;
10296 }
10297
10298 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10299                                 struct drm_display_mode *mode,
10300                                 struct intel_load_detect_pipe *old,
10301                                 struct drm_modeset_acquire_ctx *ctx)
10302 {
10303         struct intel_crtc *intel_crtc;
10304         struct intel_encoder *intel_encoder =
10305                 intel_attached_encoder(connector);
10306         struct drm_crtc *possible_crtc;
10307         struct drm_encoder *encoder = &intel_encoder->base;
10308         struct drm_crtc *crtc = NULL;
10309         struct drm_device *dev = encoder->dev;
10310         struct drm_framebuffer *fb;
10311         struct drm_mode_config *config = &dev->mode_config;
10312         struct drm_atomic_state *state = NULL;
10313         struct drm_connector_state *connector_state;
10314         struct intel_crtc_state *crtc_state;
10315         int ret, i = -1;
10316
10317         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10318                       connector->base.id, connector->name,
10319                       encoder->base.id, encoder->name);
10320
10321 retry:
10322         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10323         if (ret)
10324                 goto fail_unlock;
10325
10326         /*
10327          * Algorithm gets a little messy:
10328          *
10329          *   - if the connector already has an assigned crtc, use it (but make
10330          *     sure it's on first)
10331          *
10332          *   - try to find the first unused crtc that can drive this connector,
10333          *     and use that if we find one
10334          */
10335
10336         /* See if we already have a CRTC for this connector */
10337         if (encoder->crtc) {
10338                 crtc = encoder->crtc;
10339
10340                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10341                 if (ret)
10342                         goto fail_unlock;
10343                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10344                 if (ret)
10345                         goto fail_unlock;
10346
10347                 old->dpms_mode = connector->dpms;
10348                 old->load_detect_temp = false;
10349
10350                 /* Make sure the crtc and connector are running */
10351                 if (connector->dpms != DRM_MODE_DPMS_ON)
10352                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10353
10354                 return true;
10355         }
10356
10357         /* Find an unused one (if possible) */
10358         for_each_crtc(dev, possible_crtc) {
10359                 i++;
10360                 if (!(encoder->possible_crtcs & (1 << i)))
10361                         continue;
10362                 if (possible_crtc->state->enable)
10363                         continue;
10364                 /* This can occur when applying the pipe A quirk on resume. */
10365                 if (to_intel_crtc(possible_crtc)->new_enabled)
10366                         continue;
10367
10368                 crtc = possible_crtc;
10369                 break;
10370         }
10371
10372         /*
10373          * If we didn't find an unused CRTC, don't use any.
10374          */
10375         if (!crtc) {
10376                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10377                 goto fail_unlock;
10378         }
10379
10380         ret = drm_modeset_lock(&crtc->mutex, ctx);
10381         if (ret)
10382                 goto fail_unlock;
10383         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10384         if (ret)
10385                 goto fail_unlock;
10386         intel_encoder->new_crtc = to_intel_crtc(crtc);
10387         to_intel_connector(connector)->new_encoder = intel_encoder;
10388
10389         intel_crtc = to_intel_crtc(crtc);
10390         intel_crtc->new_enabled = true;
10391         old->dpms_mode = connector->dpms;
10392         old->load_detect_temp = true;
10393         old->release_fb = NULL;
10394
10395         state = drm_atomic_state_alloc(dev);
10396         if (!state)
10397                 return false;
10398
10399         state->acquire_ctx = ctx;
10400
10401         connector_state = drm_atomic_get_connector_state(state, connector);
10402         if (IS_ERR(connector_state)) {
10403                 ret = PTR_ERR(connector_state);
10404                 goto fail;
10405         }
10406
10407         connector_state->crtc = crtc;
10408         connector_state->best_encoder = &intel_encoder->base;
10409
10410         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10411         if (IS_ERR(crtc_state)) {
10412                 ret = PTR_ERR(crtc_state);
10413                 goto fail;
10414         }
10415
10416         crtc_state->base.active = crtc_state->base.enable = true;
10417
10418         if (!mode)
10419                 mode = &load_detect_mode;
10420
10421         /* We need a framebuffer large enough to accommodate all accesses
10422          * that the plane may generate whilst we perform load detection.
10423          * We can not rely on the fbcon either being present (we get called
10424          * during its initialisation to detect all boot displays, or it may
10425          * not even exist) or that it is large enough to satisfy the
10426          * requested mode.
10427          */
10428         fb = mode_fits_in_fbdev(dev, mode);
10429         if (fb == NULL) {
10430                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10431                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10432                 old->release_fb = fb;
10433         } else
10434                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10435         if (IS_ERR(fb)) {
10436                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10437                 goto fail;
10438         }
10439
10440         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10441         if (ret)
10442                 goto fail;
10443
10444         drm_mode_copy(&crtc_state->base.mode, mode);
10445
10446         if (intel_set_mode(state)) {
10447                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10448                 if (old->release_fb)
10449                         old->release_fb->funcs->destroy(old->release_fb);
10450                 goto fail;
10451         }
10452         crtc->primary->crtc = crtc;
10453
10454         /* let the connector get through one full cycle before testing */
10455         intel_wait_for_vblank(dev, intel_crtc->pipe);
10456         return true;
10457
10458  fail:
10459         intel_crtc->new_enabled = crtc->state->enable;
10460 fail_unlock:
10461         drm_atomic_state_free(state);
10462         state = NULL;
10463
10464         if (ret == -EDEADLK) {
10465                 drm_modeset_backoff(ctx);
10466                 goto retry;
10467         }
10468
10469         return false;
10470 }
10471
10472 void intel_release_load_detect_pipe(struct drm_connector *connector,
10473                                     struct intel_load_detect_pipe *old,
10474                                     struct drm_modeset_acquire_ctx *ctx)
10475 {
10476         struct drm_device *dev = connector->dev;
10477         struct intel_encoder *intel_encoder =
10478                 intel_attached_encoder(connector);
10479         struct drm_encoder *encoder = &intel_encoder->base;
10480         struct drm_crtc *crtc = encoder->crtc;
10481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10482         struct drm_atomic_state *state;
10483         struct drm_connector_state *connector_state;
10484         struct intel_crtc_state *crtc_state;
10485         int ret;
10486
10487         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10488                       connector->base.id, connector->name,
10489                       encoder->base.id, encoder->name);
10490
10491         if (old->load_detect_temp) {
10492                 state = drm_atomic_state_alloc(dev);
10493                 if (!state)
10494                         goto fail;
10495
10496                 state->acquire_ctx = ctx;
10497
10498                 connector_state = drm_atomic_get_connector_state(state, connector);
10499                 if (IS_ERR(connector_state))
10500                         goto fail;
10501
10502                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10503                 if (IS_ERR(crtc_state))
10504                         goto fail;
10505
10506                 to_intel_connector(connector)->new_encoder = NULL;
10507                 intel_encoder->new_crtc = NULL;
10508                 intel_crtc->new_enabled = false;
10509
10510                 connector_state->best_encoder = NULL;
10511                 connector_state->crtc = NULL;
10512
10513                 crtc_state->base.enable = crtc_state->base.active = false;
10514
10515                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10516                                                       0, 0);
10517                 if (ret)
10518                         goto fail;
10519
10520                 ret = intel_set_mode(state);
10521                 if (ret)
10522                         goto fail;
10523
10524                 if (old->release_fb) {
10525                         drm_framebuffer_unregister_private(old->release_fb);
10526                         drm_framebuffer_unreference(old->release_fb);
10527                 }
10528
10529                 return;
10530         }
10531
10532         /* Switch crtc and encoder back off if necessary */
10533         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10534                 connector->funcs->dpms(connector, old->dpms_mode);
10535
10536         return;
10537 fail:
10538         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10539         drm_atomic_state_free(state);
10540 }
10541
10542 static int i9xx_pll_refclk(struct drm_device *dev,
10543                            const struct intel_crtc_state *pipe_config)
10544 {
10545         struct drm_i915_private *dev_priv = dev->dev_private;
10546         u32 dpll = pipe_config->dpll_hw_state.dpll;
10547
10548         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10549                 return dev_priv->vbt.lvds_ssc_freq;
10550         else if (HAS_PCH_SPLIT(dev))
10551                 return 120000;
10552         else if (!IS_GEN2(dev))
10553                 return 96000;
10554         else
10555                 return 48000;
10556 }
10557
10558 /* Returns the clock of the currently programmed mode of the given pipe. */
10559 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10560                                 struct intel_crtc_state *pipe_config)
10561 {
10562         struct drm_device *dev = crtc->base.dev;
10563         struct drm_i915_private *dev_priv = dev->dev_private;
10564         int pipe = pipe_config->cpu_transcoder;
10565         u32 dpll = pipe_config->dpll_hw_state.dpll;
10566         u32 fp;
10567         intel_clock_t clock;
10568         int refclk = i9xx_pll_refclk(dev, pipe_config);
10569
10570         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10571                 fp = pipe_config->dpll_hw_state.fp0;
10572         else
10573                 fp = pipe_config->dpll_hw_state.fp1;
10574
10575         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10576         if (IS_PINEVIEW(dev)) {
10577                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10578                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10579         } else {
10580                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10581                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10582         }
10583
10584         if (!IS_GEN2(dev)) {
10585                 if (IS_PINEVIEW(dev))
10586                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10587                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10588                 else
10589                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10590                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10591
10592                 switch (dpll & DPLL_MODE_MASK) {
10593                 case DPLLB_MODE_DAC_SERIAL:
10594                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10595                                 5 : 10;
10596                         break;
10597                 case DPLLB_MODE_LVDS:
10598                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10599                                 7 : 14;
10600                         break;
10601                 default:
10602                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10603                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10604                         return;
10605                 }
10606
10607                 if (IS_PINEVIEW(dev))
10608                         pineview_clock(refclk, &clock);
10609                 else
10610                         i9xx_clock(refclk, &clock);
10611         } else {
10612                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10613                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10614
10615                 if (is_lvds) {
10616                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10617                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10618
10619                         if (lvds & LVDS_CLKB_POWER_UP)
10620                                 clock.p2 = 7;
10621                         else
10622                                 clock.p2 = 14;
10623                 } else {
10624                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10625                                 clock.p1 = 2;
10626                         else {
10627                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10628                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10629                         }
10630                         if (dpll & PLL_P2_DIVIDE_BY_4)
10631                                 clock.p2 = 4;
10632                         else
10633                                 clock.p2 = 2;
10634                 }
10635
10636                 i9xx_clock(refclk, &clock);
10637         }
10638
10639         /*
10640          * This value includes pixel_multiplier. We will use
10641          * port_clock to compute adjusted_mode.crtc_clock in the
10642          * encoder's get_config() function.
10643          */
10644         pipe_config->port_clock = clock.dot;
10645 }
10646
10647 int intel_dotclock_calculate(int link_freq,
10648                              const struct intel_link_m_n *m_n)
10649 {
10650         /*
10651          * The calculation for the data clock is:
10652          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10653          * But we want to avoid losing precison if possible, so:
10654          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10655          *
10656          * and the link clock is simpler:
10657          * link_clock = (m * link_clock) / n
10658          */
10659
10660         if (!m_n->link_n)
10661                 return 0;
10662
10663         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10664 }
10665
10666 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10667                                    struct intel_crtc_state *pipe_config)
10668 {
10669         struct drm_device *dev = crtc->base.dev;
10670
10671         /* read out port_clock from the DPLL */
10672         i9xx_crtc_clock_get(crtc, pipe_config);
10673
10674         /*
10675          * This value does not include pixel_multiplier.
10676          * We will check that port_clock and adjusted_mode.crtc_clock
10677          * agree once we know their relationship in the encoder's
10678          * get_config() function.
10679          */
10680         pipe_config->base.adjusted_mode.crtc_clock =
10681                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10682                                          &pipe_config->fdi_m_n);
10683 }
10684
10685 /** Returns the currently programmed mode of the given pipe. */
10686 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10687                                              struct drm_crtc *crtc)
10688 {
10689         struct drm_i915_private *dev_priv = dev->dev_private;
10690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10691         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10692         struct drm_display_mode *mode;
10693         struct intel_crtc_state pipe_config;
10694         int htot = I915_READ(HTOTAL(cpu_transcoder));
10695         int hsync = I915_READ(HSYNC(cpu_transcoder));
10696         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10697         int vsync = I915_READ(VSYNC(cpu_transcoder));
10698         enum pipe pipe = intel_crtc->pipe;
10699
10700         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10701         if (!mode)
10702                 return NULL;
10703
10704         /*
10705          * Construct a pipe_config sufficient for getting the clock info
10706          * back out of crtc_clock_get.
10707          *
10708          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10709          * to use a real value here instead.
10710          */
10711         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10712         pipe_config.pixel_multiplier = 1;
10713         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10714         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10715         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10716         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10717
10718         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10719         mode->hdisplay = (htot & 0xffff) + 1;
10720         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10721         mode->hsync_start = (hsync & 0xffff) + 1;
10722         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10723         mode->vdisplay = (vtot & 0xffff) + 1;
10724         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10725         mode->vsync_start = (vsync & 0xffff) + 1;
10726         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10727
10728         drm_mode_set_name(mode);
10729
10730         return mode;
10731 }
10732
10733 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10734 {
10735         struct drm_device *dev = crtc->dev;
10736         struct drm_i915_private *dev_priv = dev->dev_private;
10737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10738
10739         if (!HAS_GMCH_DISPLAY(dev))
10740                 return;
10741
10742         if (!dev_priv->lvds_downclock_avail)
10743                 return;
10744
10745         /*
10746          * Since this is called by a timer, we should never get here in
10747          * the manual case.
10748          */
10749         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10750                 int pipe = intel_crtc->pipe;
10751                 int dpll_reg = DPLL(pipe);
10752                 int dpll;
10753
10754                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10755
10756                 assert_panel_unlocked(dev_priv, pipe);
10757
10758                 dpll = I915_READ(dpll_reg);
10759                 dpll |= DISPLAY_RATE_SELECT_FPA1;
10760                 I915_WRITE(dpll_reg, dpll);
10761                 intel_wait_for_vblank(dev, pipe);
10762                 dpll = I915_READ(dpll_reg);
10763                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10764                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10765         }
10766
10767 }
10768
10769 void intel_mark_busy(struct drm_device *dev)
10770 {
10771         struct drm_i915_private *dev_priv = dev->dev_private;
10772
10773         if (dev_priv->mm.busy)
10774                 return;
10775
10776         intel_runtime_pm_get(dev_priv);
10777         i915_update_gfx_val(dev_priv);
10778         if (INTEL_INFO(dev)->gen >= 6)
10779                 gen6_rps_busy(dev_priv);
10780         dev_priv->mm.busy = true;
10781 }
10782
10783 void intel_mark_idle(struct drm_device *dev)
10784 {
10785         struct drm_i915_private *dev_priv = dev->dev_private;
10786         struct drm_crtc *crtc;
10787
10788         if (!dev_priv->mm.busy)
10789                 return;
10790
10791         dev_priv->mm.busy = false;
10792
10793         for_each_crtc(dev, crtc) {
10794                 if (!crtc->primary->fb)
10795                         continue;
10796
10797                 intel_decrease_pllclock(crtc);
10798         }
10799
10800         if (INTEL_INFO(dev)->gen >= 6)
10801                 gen6_rps_idle(dev->dev_private);
10802
10803         intel_runtime_pm_put(dev_priv);
10804 }
10805
10806 static void intel_crtc_destroy(struct drm_crtc *crtc)
10807 {
10808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10809         struct drm_device *dev = crtc->dev;
10810         struct intel_unpin_work *work;
10811
10812         spin_lock_irq(&dev->event_lock);
10813         work = intel_crtc->unpin_work;
10814         intel_crtc->unpin_work = NULL;
10815         spin_unlock_irq(&dev->event_lock);
10816
10817         if (work) {
10818                 cancel_work_sync(&work->work);
10819                 kfree(work);
10820         }
10821
10822         drm_crtc_cleanup(crtc);
10823
10824         kfree(intel_crtc);
10825 }
10826
10827 static void intel_unpin_work_fn(struct work_struct *__work)
10828 {
10829         struct intel_unpin_work *work =
10830                 container_of(__work, struct intel_unpin_work, work);
10831         struct drm_device *dev = work->crtc->dev;
10832         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10833
10834         mutex_lock(&dev->struct_mutex);
10835         intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10836         drm_gem_object_unreference(&work->pending_flip_obj->base);
10837
10838         intel_fbc_update(dev);
10839
10840         if (work->flip_queued_req)
10841                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10842         mutex_unlock(&dev->struct_mutex);
10843
10844         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10845         drm_framebuffer_unreference(work->old_fb);
10846
10847         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10848         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10849
10850         kfree(work);
10851 }
10852
10853 static void do_intel_finish_page_flip(struct drm_device *dev,
10854                                       struct drm_crtc *crtc)
10855 {
10856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857         struct intel_unpin_work *work;
10858         unsigned long flags;
10859
10860         /* Ignore early vblank irqs */
10861         if (intel_crtc == NULL)
10862                 return;
10863
10864         /*
10865          * This is called both by irq handlers and the reset code (to complete
10866          * lost pageflips) so needs the full irqsave spinlocks.
10867          */
10868         spin_lock_irqsave(&dev->event_lock, flags);
10869         work = intel_crtc->unpin_work;
10870
10871         /* Ensure we don't miss a work->pending update ... */
10872         smp_rmb();
10873
10874         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10875                 spin_unlock_irqrestore(&dev->event_lock, flags);
10876                 return;
10877         }
10878
10879         page_flip_completed(intel_crtc);
10880
10881         spin_unlock_irqrestore(&dev->event_lock, flags);
10882 }
10883
10884 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10885 {
10886         struct drm_i915_private *dev_priv = dev->dev_private;
10887         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10888
10889         do_intel_finish_page_flip(dev, crtc);
10890 }
10891
10892 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10893 {
10894         struct drm_i915_private *dev_priv = dev->dev_private;
10895         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10896
10897         do_intel_finish_page_flip(dev, crtc);
10898 }
10899
10900 /* Is 'a' after or equal to 'b'? */
10901 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10902 {
10903         return !((a - b) & 0x80000000);
10904 }
10905
10906 static bool page_flip_finished(struct intel_crtc *crtc)
10907 {
10908         struct drm_device *dev = crtc->base.dev;
10909         struct drm_i915_private *dev_priv = dev->dev_private;
10910
10911         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10912             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10913                 return true;
10914
10915         /*
10916          * The relevant registers doen't exist on pre-ctg.
10917          * As the flip done interrupt doesn't trigger for mmio
10918          * flips on gmch platforms, a flip count check isn't
10919          * really needed there. But since ctg has the registers,
10920          * include it in the check anyway.
10921          */
10922         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10923                 return true;
10924
10925         /*
10926          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10927          * used the same base address. In that case the mmio flip might
10928          * have completed, but the CS hasn't even executed the flip yet.
10929          *
10930          * A flip count check isn't enough as the CS might have updated
10931          * the base address just after start of vblank, but before we
10932          * managed to process the interrupt. This means we'd complete the
10933          * CS flip too soon.
10934          *
10935          * Combining both checks should get us a good enough result. It may
10936          * still happen that the CS flip has been executed, but has not
10937          * yet actually completed. But in case the base address is the same
10938          * anyway, we don't really care.
10939          */
10940         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10941                 crtc->unpin_work->gtt_offset &&
10942                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10943                                     crtc->unpin_work->flip_count);
10944 }
10945
10946 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10947 {
10948         struct drm_i915_private *dev_priv = dev->dev_private;
10949         struct intel_crtc *intel_crtc =
10950                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10951         unsigned long flags;
10952
10953
10954         /*
10955          * This is called both by irq handlers and the reset code (to complete
10956          * lost pageflips) so needs the full irqsave spinlocks.
10957          *
10958          * NB: An MMIO update of the plane base pointer will also
10959          * generate a page-flip completion irq, i.e. every modeset
10960          * is also accompanied by a spurious intel_prepare_page_flip().
10961          */
10962         spin_lock_irqsave(&dev->event_lock, flags);
10963         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10964                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10965         spin_unlock_irqrestore(&dev->event_lock, flags);
10966 }
10967
10968 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10969 {
10970         /* Ensure that the work item is consistent when activating it ... */
10971         smp_wmb();
10972         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10973         /* and that it is marked active as soon as the irq could fire. */
10974         smp_wmb();
10975 }
10976
10977 static int intel_gen2_queue_flip(struct drm_device *dev,
10978                                  struct drm_crtc *crtc,
10979                                  struct drm_framebuffer *fb,
10980                                  struct drm_i915_gem_object *obj,
10981                                  struct intel_engine_cs *ring,
10982                                  uint32_t flags)
10983 {
10984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10985         u32 flip_mask;
10986         int ret;
10987
10988         ret = intel_ring_begin(ring, 6);
10989         if (ret)
10990                 return ret;
10991
10992         /* Can't queue multiple flips, so wait for the previous
10993          * one to finish before executing the next.
10994          */
10995         if (intel_crtc->plane)
10996                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10997         else
10998                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10999         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11000         intel_ring_emit(ring, MI_NOOP);
11001         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11002                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11003         intel_ring_emit(ring, fb->pitches[0]);
11004         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11005         intel_ring_emit(ring, 0); /* aux display base address, unused */
11006
11007         intel_mark_page_flip_active(intel_crtc);
11008         __intel_ring_advance(ring);
11009         return 0;
11010 }
11011
11012 static int intel_gen3_queue_flip(struct drm_device *dev,
11013                                  struct drm_crtc *crtc,
11014                                  struct drm_framebuffer *fb,
11015                                  struct drm_i915_gem_object *obj,
11016                                  struct intel_engine_cs *ring,
11017                                  uint32_t flags)
11018 {
11019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11020         u32 flip_mask;
11021         int ret;
11022
11023         ret = intel_ring_begin(ring, 6);
11024         if (ret)
11025                 return ret;
11026
11027         if (intel_crtc->plane)
11028                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11029         else
11030                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11031         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11032         intel_ring_emit(ring, MI_NOOP);
11033         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11034                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11035         intel_ring_emit(ring, fb->pitches[0]);
11036         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11037         intel_ring_emit(ring, MI_NOOP);
11038
11039         intel_mark_page_flip_active(intel_crtc);
11040         __intel_ring_advance(ring);
11041         return 0;
11042 }
11043
11044 static int intel_gen4_queue_flip(struct drm_device *dev,
11045                                  struct drm_crtc *crtc,
11046                                  struct drm_framebuffer *fb,
11047                                  struct drm_i915_gem_object *obj,
11048                                  struct intel_engine_cs *ring,
11049                                  uint32_t flags)
11050 {
11051         struct drm_i915_private *dev_priv = dev->dev_private;
11052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053         uint32_t pf, pipesrc;
11054         int ret;
11055
11056         ret = intel_ring_begin(ring, 4);
11057         if (ret)
11058                 return ret;
11059
11060         /* i965+ uses the linear or tiled offsets from the
11061          * Display Registers (which do not change across a page-flip)
11062          * so we need only reprogram the base address.
11063          */
11064         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11065                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066         intel_ring_emit(ring, fb->pitches[0]);
11067         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11068                         obj->tiling_mode);
11069
11070         /* XXX Enabling the panel-fitter across page-flip is so far
11071          * untested on non-native modes, so ignore it for now.
11072          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11073          */
11074         pf = 0;
11075         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11076         intel_ring_emit(ring, pf | pipesrc);
11077
11078         intel_mark_page_flip_active(intel_crtc);
11079         __intel_ring_advance(ring);
11080         return 0;
11081 }
11082
11083 static int intel_gen6_queue_flip(struct drm_device *dev,
11084                                  struct drm_crtc *crtc,
11085                                  struct drm_framebuffer *fb,
11086                                  struct drm_i915_gem_object *obj,
11087                                  struct intel_engine_cs *ring,
11088                                  uint32_t flags)
11089 {
11090         struct drm_i915_private *dev_priv = dev->dev_private;
11091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092         uint32_t pf, pipesrc;
11093         int ret;
11094
11095         ret = intel_ring_begin(ring, 4);
11096         if (ret)
11097                 return ret;
11098
11099         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11100                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11101         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11102         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11103
11104         /* Contrary to the suggestions in the documentation,
11105          * "Enable Panel Fitter" does not seem to be required when page
11106          * flipping with a non-native mode, and worse causes a normal
11107          * modeset to fail.
11108          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11109          */
11110         pf = 0;
11111         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11112         intel_ring_emit(ring, pf | pipesrc);
11113
11114         intel_mark_page_flip_active(intel_crtc);
11115         __intel_ring_advance(ring);
11116         return 0;
11117 }
11118
11119 static int intel_gen7_queue_flip(struct drm_device *dev,
11120                                  struct drm_crtc *crtc,
11121                                  struct drm_framebuffer *fb,
11122                                  struct drm_i915_gem_object *obj,
11123                                  struct intel_engine_cs *ring,
11124                                  uint32_t flags)
11125 {
11126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11127         uint32_t plane_bit = 0;
11128         int len, ret;
11129
11130         switch (intel_crtc->plane) {
11131         case PLANE_A:
11132                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11133                 break;
11134         case PLANE_B:
11135                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11136                 break;
11137         case PLANE_C:
11138                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11139                 break;
11140         default:
11141                 WARN_ONCE(1, "unknown plane in flip command\n");
11142                 return -ENODEV;
11143         }
11144
11145         len = 4;
11146         if (ring->id == RCS) {
11147                 len += 6;
11148                 /*
11149                  * On Gen 8, SRM is now taking an extra dword to accommodate
11150                  * 48bits addresses, and we need a NOOP for the batch size to
11151                  * stay even.
11152                  */
11153                 if (IS_GEN8(dev))
11154                         len += 2;
11155         }
11156
11157         /*
11158          * BSpec MI_DISPLAY_FLIP for IVB:
11159          * "The full packet must be contained within the same cache line."
11160          *
11161          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11162          * cacheline, if we ever start emitting more commands before
11163          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11164          * then do the cacheline alignment, and finally emit the
11165          * MI_DISPLAY_FLIP.
11166          */
11167         ret = intel_ring_cacheline_align(ring);
11168         if (ret)
11169                 return ret;
11170
11171         ret = intel_ring_begin(ring, len);
11172         if (ret)
11173                 return ret;
11174
11175         /* Unmask the flip-done completion message. Note that the bspec says that
11176          * we should do this for both the BCS and RCS, and that we must not unmask
11177          * more than one flip event at any time (or ensure that one flip message
11178          * can be sent by waiting for flip-done prior to queueing new flips).
11179          * Experimentation says that BCS works despite DERRMR masking all
11180          * flip-done completion events and that unmasking all planes at once
11181          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11182          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11183          */
11184         if (ring->id == RCS) {
11185                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11186                 intel_ring_emit(ring, DERRMR);
11187                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11188                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11189                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11190                 if (IS_GEN8(dev))
11191                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11192                                               MI_SRM_LRM_GLOBAL_GTT);
11193                 else
11194                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11195                                               MI_SRM_LRM_GLOBAL_GTT);
11196                 intel_ring_emit(ring, DERRMR);
11197                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11198                 if (IS_GEN8(dev)) {
11199                         intel_ring_emit(ring, 0);
11200                         intel_ring_emit(ring, MI_NOOP);
11201                 }
11202         }
11203
11204         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11205         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11206         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11207         intel_ring_emit(ring, (MI_NOOP));
11208
11209         intel_mark_page_flip_active(intel_crtc);
11210         __intel_ring_advance(ring);
11211         return 0;
11212 }
11213
11214 static bool use_mmio_flip(struct intel_engine_cs *ring,
11215                           struct drm_i915_gem_object *obj)
11216 {
11217         /*
11218          * This is not being used for older platforms, because
11219          * non-availability of flip done interrupt forces us to use
11220          * CS flips. Older platforms derive flip done using some clever
11221          * tricks involving the flip_pending status bits and vblank irqs.
11222          * So using MMIO flips there would disrupt this mechanism.
11223          */
11224
11225         if (ring == NULL)
11226                 return true;
11227
11228         if (INTEL_INFO(ring->dev)->gen < 5)
11229                 return false;
11230
11231         if (i915.use_mmio_flip < 0)
11232                 return false;
11233         else if (i915.use_mmio_flip > 0)
11234                 return true;
11235         else if (i915.enable_execlists)
11236                 return true;
11237         else
11238                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11239 }
11240
11241 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11242 {
11243         struct drm_device *dev = intel_crtc->base.dev;
11244         struct drm_i915_private *dev_priv = dev->dev_private;
11245         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11246         const enum pipe pipe = intel_crtc->pipe;
11247         u32 ctl, stride;
11248
11249         ctl = I915_READ(PLANE_CTL(pipe, 0));
11250         ctl &= ~PLANE_CTL_TILED_MASK;
11251         switch (fb->modifier[0]) {
11252         case DRM_FORMAT_MOD_NONE:
11253                 break;
11254         case I915_FORMAT_MOD_X_TILED:
11255                 ctl |= PLANE_CTL_TILED_X;
11256                 break;
11257         case I915_FORMAT_MOD_Y_TILED:
11258                 ctl |= PLANE_CTL_TILED_Y;
11259                 break;
11260         case I915_FORMAT_MOD_Yf_TILED:
11261                 ctl |= PLANE_CTL_TILED_YF;
11262                 break;
11263         default:
11264                 MISSING_CASE(fb->modifier[0]);
11265         }
11266
11267         /*
11268          * The stride is either expressed as a multiple of 64 bytes chunks for
11269          * linear buffers or in number of tiles for tiled buffers.
11270          */
11271         stride = fb->pitches[0] /
11272                  intel_fb_stride_alignment(dev, fb->modifier[0],
11273                                            fb->pixel_format);
11274
11275         /*
11276          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11277          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11278          */
11279         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11280         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11281
11282         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11283         POSTING_READ(PLANE_SURF(pipe, 0));
11284 }
11285
11286 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11287 {
11288         struct drm_device *dev = intel_crtc->base.dev;
11289         struct drm_i915_private *dev_priv = dev->dev_private;
11290         struct intel_framebuffer *intel_fb =
11291                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11292         struct drm_i915_gem_object *obj = intel_fb->obj;
11293         u32 dspcntr;
11294         u32 reg;
11295
11296         reg = DSPCNTR(intel_crtc->plane);
11297         dspcntr = I915_READ(reg);
11298
11299         if (obj->tiling_mode != I915_TILING_NONE)
11300                 dspcntr |= DISPPLANE_TILED;
11301         else
11302                 dspcntr &= ~DISPPLANE_TILED;
11303
11304         I915_WRITE(reg, dspcntr);
11305
11306         I915_WRITE(DSPSURF(intel_crtc->plane),
11307                    intel_crtc->unpin_work->gtt_offset);
11308         POSTING_READ(DSPSURF(intel_crtc->plane));
11309
11310 }
11311
11312 /*
11313  * XXX: This is the temporary way to update the plane registers until we get
11314  * around to using the usual plane update functions for MMIO flips
11315  */
11316 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11317 {
11318         struct drm_device *dev = intel_crtc->base.dev;
11319         bool atomic_update;
11320         u32 start_vbl_count;
11321
11322         intel_mark_page_flip_active(intel_crtc);
11323
11324         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11325
11326         if (INTEL_INFO(dev)->gen >= 9)
11327                 skl_do_mmio_flip(intel_crtc);
11328         else
11329                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11330                 ilk_do_mmio_flip(intel_crtc);
11331
11332         if (atomic_update)
11333                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11334 }
11335
11336 static void intel_mmio_flip_work_func(struct work_struct *work)
11337 {
11338         struct intel_mmio_flip *mmio_flip =
11339                 container_of(work, struct intel_mmio_flip, work);
11340
11341         if (mmio_flip->req)
11342                 WARN_ON(__i915_wait_request(mmio_flip->req,
11343                                             mmio_flip->crtc->reset_counter,
11344                                             false, NULL,
11345                                             &mmio_flip->i915->rps.mmioflips));
11346
11347         intel_do_mmio_flip(mmio_flip->crtc);
11348
11349         i915_gem_request_unreference__unlocked(mmio_flip->req);
11350         kfree(mmio_flip);
11351 }
11352
11353 static int intel_queue_mmio_flip(struct drm_device *dev,
11354                                  struct drm_crtc *crtc,
11355                                  struct drm_framebuffer *fb,
11356                                  struct drm_i915_gem_object *obj,
11357                                  struct intel_engine_cs *ring,
11358                                  uint32_t flags)
11359 {
11360         struct intel_mmio_flip *mmio_flip;
11361
11362         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11363         if (mmio_flip == NULL)
11364                 return -ENOMEM;
11365
11366         mmio_flip->i915 = to_i915(dev);
11367         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11368         mmio_flip->crtc = to_intel_crtc(crtc);
11369
11370         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11371         schedule_work(&mmio_flip->work);
11372
11373         return 0;
11374 }
11375
11376 static int intel_default_queue_flip(struct drm_device *dev,
11377                                     struct drm_crtc *crtc,
11378                                     struct drm_framebuffer *fb,
11379                                     struct drm_i915_gem_object *obj,
11380                                     struct intel_engine_cs *ring,
11381                                     uint32_t flags)
11382 {
11383         return -ENODEV;
11384 }
11385
11386 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11387                                          struct drm_crtc *crtc)
11388 {
11389         struct drm_i915_private *dev_priv = dev->dev_private;
11390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11391         struct intel_unpin_work *work = intel_crtc->unpin_work;
11392         u32 addr;
11393
11394         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11395                 return true;
11396
11397         if (!work->enable_stall_check)
11398                 return false;
11399
11400         if (work->flip_ready_vblank == 0) {
11401                 if (work->flip_queued_req &&
11402                     !i915_gem_request_completed(work->flip_queued_req, true))
11403                         return false;
11404
11405                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11406         }
11407
11408         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11409                 return false;
11410
11411         /* Potential stall - if we see that the flip has happened,
11412          * assume a missed interrupt. */
11413         if (INTEL_INFO(dev)->gen >= 4)
11414                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11415         else
11416                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11417
11418         /* There is a potential issue here with a false positive after a flip
11419          * to the same address. We could address this by checking for a
11420          * non-incrementing frame counter.
11421          */
11422         return addr == work->gtt_offset;
11423 }
11424
11425 void intel_check_page_flip(struct drm_device *dev, int pipe)
11426 {
11427         struct drm_i915_private *dev_priv = dev->dev_private;
11428         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11430         struct intel_unpin_work *work;
11431
11432         WARN_ON(!in_interrupt());
11433
11434         if (crtc == NULL)
11435                 return;
11436
11437         spin_lock(&dev->event_lock);
11438         work = intel_crtc->unpin_work;
11439         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11440                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11441                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11442                 page_flip_completed(intel_crtc);
11443                 work = NULL;
11444         }
11445         if (work != NULL &&
11446             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11447                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11448         spin_unlock(&dev->event_lock);
11449 }
11450
11451 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11452                                 struct drm_framebuffer *fb,
11453                                 struct drm_pending_vblank_event *event,
11454                                 uint32_t page_flip_flags)
11455 {
11456         struct drm_device *dev = crtc->dev;
11457         struct drm_i915_private *dev_priv = dev->dev_private;
11458         struct drm_framebuffer *old_fb = crtc->primary->fb;
11459         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11461         struct drm_plane *primary = crtc->primary;
11462         enum pipe pipe = intel_crtc->pipe;
11463         struct intel_unpin_work *work;
11464         struct intel_engine_cs *ring;
11465         bool mmio_flip;
11466         int ret;
11467
11468         /*
11469          * drm_mode_page_flip_ioctl() should already catch this, but double
11470          * check to be safe.  In the future we may enable pageflipping from
11471          * a disabled primary plane.
11472          */
11473         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11474                 return -EBUSY;
11475
11476         /* Can't change pixel format via MI display flips. */
11477         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11478                 return -EINVAL;
11479
11480         /*
11481          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11482          * Note that pitch changes could also affect these register.
11483          */
11484         if (INTEL_INFO(dev)->gen > 3 &&
11485             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11486              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11487                 return -EINVAL;
11488
11489         if (i915_terminally_wedged(&dev_priv->gpu_error))
11490                 goto out_hang;
11491
11492         work = kzalloc(sizeof(*work), GFP_KERNEL);
11493         if (work == NULL)
11494                 return -ENOMEM;
11495
11496         work->event = event;
11497         work->crtc = crtc;
11498         work->old_fb = old_fb;
11499         INIT_WORK(&work->work, intel_unpin_work_fn);
11500
11501         ret = drm_crtc_vblank_get(crtc);
11502         if (ret)
11503                 goto free_work;
11504
11505         /* We borrow the event spin lock for protecting unpin_work */
11506         spin_lock_irq(&dev->event_lock);
11507         if (intel_crtc->unpin_work) {
11508                 /* Before declaring the flip queue wedged, check if
11509                  * the hardware completed the operation behind our backs.
11510                  */
11511                 if (__intel_pageflip_stall_check(dev, crtc)) {
11512                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11513                         page_flip_completed(intel_crtc);
11514                 } else {
11515                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11516                         spin_unlock_irq(&dev->event_lock);
11517
11518                         drm_crtc_vblank_put(crtc);
11519                         kfree(work);
11520                         return -EBUSY;
11521                 }
11522         }
11523         intel_crtc->unpin_work = work;
11524         spin_unlock_irq(&dev->event_lock);
11525
11526         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11527                 flush_workqueue(dev_priv->wq);
11528
11529         /* Reference the objects for the scheduled work. */
11530         drm_framebuffer_reference(work->old_fb);
11531         drm_gem_object_reference(&obj->base);
11532
11533         crtc->primary->fb = fb;
11534         update_state_fb(crtc->primary);
11535
11536         work->pending_flip_obj = obj;
11537
11538         ret = i915_mutex_lock_interruptible(dev);
11539         if (ret)
11540                 goto cleanup;
11541
11542         atomic_inc(&intel_crtc->unpin_work_count);
11543         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11544
11545         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11546                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11547
11548         if (IS_VALLEYVIEW(dev)) {
11549                 ring = &dev_priv->ring[BCS];
11550                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11551                         /* vlv: DISPLAY_FLIP fails to change tiling */
11552                         ring = NULL;
11553         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11554                 ring = &dev_priv->ring[BCS];
11555         } else if (INTEL_INFO(dev)->gen >= 7) {
11556                 ring = i915_gem_request_get_ring(obj->last_write_req);
11557                 if (ring == NULL || ring->id != RCS)
11558                         ring = &dev_priv->ring[BCS];
11559         } else {
11560                 ring = &dev_priv->ring[RCS];
11561         }
11562
11563         mmio_flip = use_mmio_flip(ring, obj);
11564
11565         /* When using CS flips, we want to emit semaphores between rings.
11566          * However, when using mmio flips we will create a task to do the
11567          * synchronisation, so all we want here is to pin the framebuffer
11568          * into the display plane and skip any waits.
11569          */
11570         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11571                                          crtc->primary->state,
11572                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11573         if (ret)
11574                 goto cleanup_pending;
11575
11576         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11577                                                   + intel_crtc->dspaddr_offset;
11578
11579         if (mmio_flip) {
11580                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11581                                             page_flip_flags);
11582                 if (ret)
11583                         goto cleanup_unpin;
11584
11585                 i915_gem_request_assign(&work->flip_queued_req,
11586                                         obj->last_write_req);
11587         } else {
11588                 if (obj->last_write_req) {
11589                         ret = i915_gem_check_olr(obj->last_write_req);
11590                         if (ret)
11591                                 goto cleanup_unpin;
11592                 }
11593
11594                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11595                                                    page_flip_flags);
11596                 if (ret)
11597                         goto cleanup_unpin;
11598
11599                 i915_gem_request_assign(&work->flip_queued_req,
11600                                         intel_ring_get_request(ring));
11601         }
11602
11603         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11604         work->enable_stall_check = true;
11605
11606         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11607                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11608
11609         intel_fbc_disable(dev);
11610         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11611         mutex_unlock(&dev->struct_mutex);
11612
11613         trace_i915_flip_request(intel_crtc->plane, obj);
11614
11615         return 0;
11616
11617 cleanup_unpin:
11618         intel_unpin_fb_obj(fb, crtc->primary->state);
11619 cleanup_pending:
11620         atomic_dec(&intel_crtc->unpin_work_count);
11621         mutex_unlock(&dev->struct_mutex);
11622 cleanup:
11623         crtc->primary->fb = old_fb;
11624         update_state_fb(crtc->primary);
11625
11626         drm_gem_object_unreference_unlocked(&obj->base);
11627         drm_framebuffer_unreference(work->old_fb);
11628
11629         spin_lock_irq(&dev->event_lock);
11630         intel_crtc->unpin_work = NULL;
11631         spin_unlock_irq(&dev->event_lock);
11632
11633         drm_crtc_vblank_put(crtc);
11634 free_work:
11635         kfree(work);
11636
11637         if (ret == -EIO) {
11638                 struct drm_atomic_state *state;
11639                 struct drm_plane_state *plane_state;
11640
11641 out_hang:
11642                 state = drm_atomic_state_alloc(dev);
11643                 if (!state)
11644                         return -ENOMEM;
11645                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11646
11647 retry:
11648                 plane_state = drm_atomic_get_plane_state(state, primary);
11649                 ret = PTR_ERR_OR_ZERO(plane_state);
11650                 if (!ret) {
11651                         drm_atomic_set_fb_for_plane(plane_state, fb);
11652
11653                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11654                         if (!ret)
11655                                 ret = drm_atomic_commit(state);
11656                 }
11657
11658                 if (ret == -EDEADLK) {
11659                         drm_modeset_backoff(state->acquire_ctx);
11660                         drm_atomic_state_clear(state);
11661                         goto retry;
11662                 }
11663
11664                 if (ret)
11665                         drm_atomic_state_free(state);
11666
11667                 if (ret == 0 && event) {
11668                         spin_lock_irq(&dev->event_lock);
11669                         drm_send_vblank_event(dev, pipe, event);
11670                         spin_unlock_irq(&dev->event_lock);
11671                 }
11672         }
11673         return ret;
11674 }
11675
11676 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11677         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11678         .load_lut = intel_crtc_load_lut,
11679         .atomic_begin = intel_begin_crtc_commit,
11680         .atomic_flush = intel_finish_crtc_commit,
11681 };
11682
11683 /**
11684  * intel_modeset_update_staged_output_state
11685  *
11686  * Updates the staged output configuration state, e.g. after we've read out the
11687  * current hw state.
11688  */
11689 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11690 {
11691         struct intel_crtc *crtc;
11692         struct intel_encoder *encoder;
11693         struct intel_connector *connector;
11694
11695         for_each_intel_connector(dev, connector) {
11696                 connector->new_encoder =
11697                         to_intel_encoder(connector->base.encoder);
11698         }
11699
11700         for_each_intel_encoder(dev, encoder) {
11701                 encoder->new_crtc =
11702                         to_intel_crtc(encoder->base.crtc);
11703         }
11704
11705         for_each_intel_crtc(dev, crtc) {
11706                 crtc->new_enabled = crtc->base.state->enable;
11707         }
11708 }
11709
11710 /* Transitional helper to copy current connector/encoder state to
11711  * connector->state. This is needed so that code that is partially
11712  * converted to atomic does the right thing.
11713  */
11714 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11715 {
11716         struct intel_connector *connector;
11717
11718         for_each_intel_connector(dev, connector) {
11719                 if (connector->base.encoder) {
11720                         connector->base.state->best_encoder =
11721                                 connector->base.encoder;
11722                         connector->base.state->crtc =
11723                                 connector->base.encoder->crtc;
11724                 } else {
11725                         connector->base.state->best_encoder = NULL;
11726                         connector->base.state->crtc = NULL;
11727                 }
11728         }
11729 }
11730
11731 static void
11732 connected_sink_compute_bpp(struct intel_connector *connector,
11733                            struct intel_crtc_state *pipe_config)
11734 {
11735         int bpp = pipe_config->pipe_bpp;
11736
11737         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11738                 connector->base.base.id,
11739                 connector->base.name);
11740
11741         /* Don't use an invalid EDID bpc value */
11742         if (connector->base.display_info.bpc &&
11743             connector->base.display_info.bpc * 3 < bpp) {
11744                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11745                               bpp, connector->base.display_info.bpc*3);
11746                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11747         }
11748
11749         /* Clamp bpp to 8 on screens without EDID 1.4 */
11750         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11751                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11752                               bpp);
11753                 pipe_config->pipe_bpp = 24;
11754         }
11755 }
11756
11757 static int
11758 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11759                           struct intel_crtc_state *pipe_config)
11760 {
11761         struct drm_device *dev = crtc->base.dev;
11762         struct drm_atomic_state *state;
11763         struct drm_connector *connector;
11764         struct drm_connector_state *connector_state;
11765         int bpp, i;
11766
11767         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11768                 bpp = 10*3;
11769         else if (INTEL_INFO(dev)->gen >= 5)
11770                 bpp = 12*3;
11771         else
11772                 bpp = 8*3;
11773
11774
11775         pipe_config->pipe_bpp = bpp;
11776
11777         state = pipe_config->base.state;
11778
11779         /* Clamp display bpp to EDID value */
11780         for_each_connector_in_state(state, connector, connector_state, i) {
11781                 if (connector_state->crtc != &crtc->base)
11782                         continue;
11783
11784                 connected_sink_compute_bpp(to_intel_connector(connector),
11785                                            pipe_config);
11786         }
11787
11788         return bpp;
11789 }
11790
11791 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11792 {
11793         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11794                         "type: 0x%x flags: 0x%x\n",
11795                 mode->crtc_clock,
11796                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11797                 mode->crtc_hsync_end, mode->crtc_htotal,
11798                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11799                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11800 }
11801
11802 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11803                                    struct intel_crtc_state *pipe_config,
11804                                    const char *context)
11805 {
11806         struct drm_device *dev = crtc->base.dev;
11807         struct drm_plane *plane;
11808         struct intel_plane *intel_plane;
11809         struct intel_plane_state *state;
11810         struct drm_framebuffer *fb;
11811
11812         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11813                       context, pipe_config, pipe_name(crtc->pipe));
11814
11815         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11816         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11817                       pipe_config->pipe_bpp, pipe_config->dither);
11818         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11819                       pipe_config->has_pch_encoder,
11820                       pipe_config->fdi_lanes,
11821                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11822                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11823                       pipe_config->fdi_m_n.tu);
11824         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11825                       pipe_config->has_dp_encoder,
11826                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11827                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11828                       pipe_config->dp_m_n.tu);
11829
11830         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11831                       pipe_config->has_dp_encoder,
11832                       pipe_config->dp_m2_n2.gmch_m,
11833                       pipe_config->dp_m2_n2.gmch_n,
11834                       pipe_config->dp_m2_n2.link_m,
11835                       pipe_config->dp_m2_n2.link_n,
11836                       pipe_config->dp_m2_n2.tu);
11837
11838         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11839                       pipe_config->has_audio,
11840                       pipe_config->has_infoframe);
11841
11842         DRM_DEBUG_KMS("requested mode:\n");
11843         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11844         DRM_DEBUG_KMS("adjusted mode:\n");
11845         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11846         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11847         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11848         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11849                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11850         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11851                       crtc->num_scalers,
11852                       pipe_config->scaler_state.scaler_users,
11853                       pipe_config->scaler_state.scaler_id);
11854         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11855                       pipe_config->gmch_pfit.control,
11856                       pipe_config->gmch_pfit.pgm_ratios,
11857                       pipe_config->gmch_pfit.lvds_border_bits);
11858         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11859                       pipe_config->pch_pfit.pos,
11860                       pipe_config->pch_pfit.size,
11861                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11862         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11863         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11864
11865         if (IS_BROXTON(dev)) {
11866                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11867                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11868                               "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11869                               pipe_config->ddi_pll_sel,
11870                               pipe_config->dpll_hw_state.ebb0,
11871                               pipe_config->dpll_hw_state.pll0,
11872                               pipe_config->dpll_hw_state.pll1,
11873                               pipe_config->dpll_hw_state.pll2,
11874                               pipe_config->dpll_hw_state.pll3,
11875                               pipe_config->dpll_hw_state.pll6,
11876                               pipe_config->dpll_hw_state.pll8,
11877                               pipe_config->dpll_hw_state.pcsdw12);
11878         } else if (IS_SKYLAKE(dev)) {
11879                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11880                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11881                               pipe_config->ddi_pll_sel,
11882                               pipe_config->dpll_hw_state.ctrl1,
11883                               pipe_config->dpll_hw_state.cfgcr1,
11884                               pipe_config->dpll_hw_state.cfgcr2);
11885         } else if (HAS_DDI(dev)) {
11886                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11887                               pipe_config->ddi_pll_sel,
11888                               pipe_config->dpll_hw_state.wrpll);
11889         } else {
11890                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11891                               "fp0: 0x%x, fp1: 0x%x\n",
11892                               pipe_config->dpll_hw_state.dpll,
11893                               pipe_config->dpll_hw_state.dpll_md,
11894                               pipe_config->dpll_hw_state.fp0,
11895                               pipe_config->dpll_hw_state.fp1);
11896         }
11897
11898         DRM_DEBUG_KMS("planes on this crtc\n");
11899         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11900                 intel_plane = to_intel_plane(plane);
11901                 if (intel_plane->pipe != crtc->pipe)
11902                         continue;
11903
11904                 state = to_intel_plane_state(plane->state);
11905                 fb = state->base.fb;
11906                 if (!fb) {
11907                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11908                                 "disabled, scaler_id = %d\n",
11909                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11910                                 plane->base.id, intel_plane->pipe,
11911                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11912                                 drm_plane_index(plane), state->scaler_id);
11913                         continue;
11914                 }
11915
11916                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11917                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11918                         plane->base.id, intel_plane->pipe,
11919                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11920                         drm_plane_index(plane));
11921                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11922                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11923                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11924                         state->scaler_id,
11925                         state->src.x1 >> 16, state->src.y1 >> 16,
11926                         drm_rect_width(&state->src) >> 16,
11927                         drm_rect_height(&state->src) >> 16,
11928                         state->dst.x1, state->dst.y1,
11929                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11930         }
11931 }
11932
11933 static bool encoders_cloneable(const struct intel_encoder *a,
11934                                const struct intel_encoder *b)
11935 {
11936         /* masks could be asymmetric, so check both ways */
11937         return a == b || (a->cloneable & (1 << b->type) &&
11938                           b->cloneable & (1 << a->type));
11939 }
11940
11941 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11942                                          struct intel_crtc *crtc,
11943                                          struct intel_encoder *encoder)
11944 {
11945         struct intel_encoder *source_encoder;
11946         struct drm_connector *connector;
11947         struct drm_connector_state *connector_state;
11948         int i;
11949
11950         for_each_connector_in_state(state, connector, connector_state, i) {
11951                 if (connector_state->crtc != &crtc->base)
11952                         continue;
11953
11954                 source_encoder =
11955                         to_intel_encoder(connector_state->best_encoder);
11956                 if (!encoders_cloneable(encoder, source_encoder))
11957                         return false;
11958         }
11959
11960         return true;
11961 }
11962
11963 static bool check_encoder_cloning(struct drm_atomic_state *state,
11964                                   struct intel_crtc *crtc)
11965 {
11966         struct intel_encoder *encoder;
11967         struct drm_connector *connector;
11968         struct drm_connector_state *connector_state;
11969         int i;
11970
11971         for_each_connector_in_state(state, connector, connector_state, i) {
11972                 if (connector_state->crtc != &crtc->base)
11973                         continue;
11974
11975                 encoder = to_intel_encoder(connector_state->best_encoder);
11976                 if (!check_single_encoder_cloning(state, crtc, encoder))
11977                         return false;
11978         }
11979
11980         return true;
11981 }
11982
11983 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11984 {
11985         struct drm_device *dev = state->dev;
11986         struct intel_encoder *encoder;
11987         struct drm_connector *connector;
11988         struct drm_connector_state *connector_state;
11989         unsigned int used_ports = 0;
11990         int i;
11991
11992         /*
11993          * Walk the connector list instead of the encoder
11994          * list to detect the problem on ddi platforms
11995          * where there's just one encoder per digital port.
11996          */
11997         for_each_connector_in_state(state, connector, connector_state, i) {
11998                 if (!connector_state->best_encoder)
11999                         continue;
12000
12001                 encoder = to_intel_encoder(connector_state->best_encoder);
12002
12003                 WARN_ON(!connector_state->crtc);
12004
12005                 switch (encoder->type) {
12006                         unsigned int port_mask;
12007                 case INTEL_OUTPUT_UNKNOWN:
12008                         if (WARN_ON(!HAS_DDI(dev)))
12009                                 break;
12010                 case INTEL_OUTPUT_DISPLAYPORT:
12011                 case INTEL_OUTPUT_HDMI:
12012                 case INTEL_OUTPUT_EDP:
12013                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12014
12015                         /* the same port mustn't appear more than once */
12016                         if (used_ports & port_mask)
12017                                 return false;
12018
12019                         used_ports |= port_mask;
12020                 default:
12021                         break;
12022                 }
12023         }
12024
12025         return true;
12026 }
12027
12028 static void
12029 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12030 {
12031         struct drm_crtc_state tmp_state;
12032         struct intel_crtc_scaler_state scaler_state;
12033         struct intel_dpll_hw_state dpll_hw_state;
12034         enum intel_dpll_id shared_dpll;
12035         uint32_t ddi_pll_sel;
12036
12037         /* FIXME: before the switch to atomic started, a new pipe_config was
12038          * kzalloc'd. Code that depends on any field being zero should be
12039          * fixed, so that the crtc_state can be safely duplicated. For now,
12040          * only fields that are know to not cause problems are preserved. */
12041
12042         tmp_state = crtc_state->base;
12043         scaler_state = crtc_state->scaler_state;
12044         shared_dpll = crtc_state->shared_dpll;
12045         dpll_hw_state = crtc_state->dpll_hw_state;
12046         ddi_pll_sel = crtc_state->ddi_pll_sel;
12047
12048         memset(crtc_state, 0, sizeof *crtc_state);
12049
12050         crtc_state->base = tmp_state;
12051         crtc_state->scaler_state = scaler_state;
12052         crtc_state->shared_dpll = shared_dpll;
12053         crtc_state->dpll_hw_state = dpll_hw_state;
12054         crtc_state->ddi_pll_sel = ddi_pll_sel;
12055 }
12056
12057 static int
12058 intel_modeset_pipe_config(struct drm_crtc *crtc,
12059                           struct intel_crtc_state *pipe_config)
12060 {
12061         struct drm_atomic_state *state = pipe_config->base.state;
12062         struct intel_encoder *encoder;
12063         struct drm_connector *connector;
12064         struct drm_connector_state *connector_state;
12065         int base_bpp, ret = -EINVAL;
12066         int i;
12067         bool retry = true;
12068
12069         if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
12070                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12071                 return -EINVAL;
12072         }
12073
12074         clear_intel_crtc_state(pipe_config);
12075
12076         pipe_config->cpu_transcoder =
12077                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12078
12079         /*
12080          * Sanitize sync polarity flags based on requested ones. If neither
12081          * positive or negative polarity is requested, treat this as meaning
12082          * negative polarity.
12083          */
12084         if (!(pipe_config->base.adjusted_mode.flags &
12085               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12086                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12087
12088         if (!(pipe_config->base.adjusted_mode.flags &
12089               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12090                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12091
12092         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12093          * plane pixel format and any sink constraints into account. Returns the
12094          * source plane bpp so that dithering can be selected on mismatches
12095          * after encoders and crtc also have had their say. */
12096         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12097                                              pipe_config);
12098         if (base_bpp < 0)
12099                 goto fail;
12100
12101         /*
12102          * Determine the real pipe dimensions. Note that stereo modes can
12103          * increase the actual pipe size due to the frame doubling and
12104          * insertion of additional space for blanks between the frame. This
12105          * is stored in the crtc timings. We use the requested mode to do this
12106          * computation to clearly distinguish it from the adjusted mode, which
12107          * can be changed by the connectors in the below retry loop.
12108          */
12109         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12110                                &pipe_config->pipe_src_w,
12111                                &pipe_config->pipe_src_h);
12112
12113 encoder_retry:
12114         /* Ensure the port clock defaults are reset when retrying. */
12115         pipe_config->port_clock = 0;
12116         pipe_config->pixel_multiplier = 1;
12117
12118         /* Fill in default crtc timings, allow encoders to overwrite them. */
12119         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12120                               CRTC_STEREO_DOUBLE);
12121
12122         /* Pass our mode to the connectors and the CRTC to give them a chance to
12123          * adjust it according to limitations or connector properties, and also
12124          * a chance to reject the mode entirely.
12125          */
12126         for_each_connector_in_state(state, connector, connector_state, i) {
12127                 if (connector_state->crtc != crtc)
12128                         continue;
12129
12130                 encoder = to_intel_encoder(connector_state->best_encoder);
12131
12132                 if (!(encoder->compute_config(encoder, pipe_config))) {
12133                         DRM_DEBUG_KMS("Encoder config failure\n");
12134                         goto fail;
12135                 }
12136         }
12137
12138         /* Set default port clock if not overwritten by the encoder. Needs to be
12139          * done afterwards in case the encoder adjusts the mode. */
12140         if (!pipe_config->port_clock)
12141                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12142                         * pipe_config->pixel_multiplier;
12143
12144         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12145         if (ret < 0) {
12146                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12147                 goto fail;
12148         }
12149
12150         if (ret == RETRY) {
12151                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12152                         ret = -EINVAL;
12153                         goto fail;
12154                 }
12155
12156                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12157                 retry = false;
12158                 goto encoder_retry;
12159         }
12160
12161         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12162         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12163                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12164
12165         /* Check if we need to force a modeset */
12166         if (pipe_config->has_audio !=
12167             to_intel_crtc_state(crtc->state)->has_audio) {
12168                 pipe_config->base.mode_changed = true;
12169                 ret = drm_atomic_add_affected_planes(state, crtc);
12170         }
12171
12172         /*
12173          * Note we have an issue here with infoframes: current code
12174          * only updates them on the full mode set path per hw
12175          * requirements.  So here we should be checking for any
12176          * required changes and forcing a mode set.
12177          */
12178 fail:
12179         return ret;
12180 }
12181
12182 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12183 {
12184         struct drm_encoder *encoder;
12185         struct drm_device *dev = crtc->dev;
12186
12187         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12188                 if (encoder->crtc == crtc)
12189                         return true;
12190
12191         return false;
12192 }
12193
12194 static void
12195 intel_modeset_update_state(struct drm_atomic_state *state)
12196 {
12197         struct drm_device *dev = state->dev;
12198         struct intel_encoder *intel_encoder;
12199         struct drm_crtc *crtc;
12200         struct drm_crtc_state *crtc_state;
12201         struct drm_connector *connector;
12202
12203         intel_shared_dpll_commit(state);
12204
12205         for_each_intel_encoder(dev, intel_encoder) {
12206                 if (!intel_encoder->base.crtc)
12207                         continue;
12208
12209                 crtc = intel_encoder->base.crtc;
12210                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12211                 if (!crtc_state || !needs_modeset(crtc->state))
12212                         continue;
12213
12214                 intel_encoder->connectors_active = false;
12215         }
12216
12217         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12218         intel_modeset_update_staged_output_state(state->dev);
12219
12220         /* Double check state. */
12221         for_each_crtc(dev, crtc) {
12222                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12223
12224                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12225
12226                 /* Update hwmode for vblank functions */
12227                 if (crtc->state->active)
12228                         crtc->hwmode = crtc->state->adjusted_mode;
12229                 else
12230                         crtc->hwmode.crtc_clock = 0;
12231         }
12232
12233         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12234                 if (!connector->encoder || !connector->encoder->crtc)
12235                         continue;
12236
12237                 crtc = connector->encoder->crtc;
12238                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12239                 if (!crtc_state || !needs_modeset(crtc->state))
12240                         continue;
12241
12242                 if (crtc->state->active) {
12243                         struct drm_property *dpms_property =
12244                                 dev->mode_config.dpms_property;
12245
12246                         connector->dpms = DRM_MODE_DPMS_ON;
12247                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12248
12249                         intel_encoder = to_intel_encoder(connector->encoder);
12250                         intel_encoder->connectors_active = true;
12251                 } else
12252                         connector->dpms = DRM_MODE_DPMS_OFF;
12253         }
12254 }
12255
12256 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12257 {
12258         int diff;
12259
12260         if (clock1 == clock2)
12261                 return true;
12262
12263         if (!clock1 || !clock2)
12264                 return false;
12265
12266         diff = abs(clock1 - clock2);
12267
12268         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12269                 return true;
12270
12271         return false;
12272 }
12273
12274 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12275         list_for_each_entry((intel_crtc), \
12276                             &(dev)->mode_config.crtc_list, \
12277                             base.head) \
12278                 if (mask & (1 <<(intel_crtc)->pipe))
12279
12280 static bool
12281 intel_pipe_config_compare(struct drm_device *dev,
12282                           struct intel_crtc_state *current_config,
12283                           struct intel_crtc_state *pipe_config)
12284 {
12285 #define PIPE_CONF_CHECK_X(name) \
12286         if (current_config->name != pipe_config->name) { \
12287                 DRM_ERROR("mismatch in " #name " " \
12288                           "(expected 0x%08x, found 0x%08x)\n", \
12289                           current_config->name, \
12290                           pipe_config->name); \
12291                 return false; \
12292         }
12293
12294 #define PIPE_CONF_CHECK_I(name) \
12295         if (current_config->name != pipe_config->name) { \
12296                 DRM_ERROR("mismatch in " #name " " \
12297                           "(expected %i, found %i)\n", \
12298                           current_config->name, \
12299                           pipe_config->name); \
12300                 return false; \
12301         }
12302
12303 /* This is required for BDW+ where there is only one set of registers for
12304  * switching between high and low RR.
12305  * This macro can be used whenever a comparison has to be made between one
12306  * hw state and multiple sw state variables.
12307  */
12308 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12309         if ((current_config->name != pipe_config->name) && \
12310                 (current_config->alt_name != pipe_config->name)) { \
12311                         DRM_ERROR("mismatch in " #name " " \
12312                                   "(expected %i or %i, found %i)\n", \
12313                                   current_config->name, \
12314                                   current_config->alt_name, \
12315                                   pipe_config->name); \
12316                         return false; \
12317         }
12318
12319 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12320         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12321                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
12322                           "(expected %i, found %i)\n", \
12323                           current_config->name & (mask), \
12324                           pipe_config->name & (mask)); \
12325                 return false; \
12326         }
12327
12328 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12329         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12330                 DRM_ERROR("mismatch in " #name " " \
12331                           "(expected %i, found %i)\n", \
12332                           current_config->name, \
12333                           pipe_config->name); \
12334                 return false; \
12335         }
12336
12337 #define PIPE_CONF_QUIRK(quirk)  \
12338         ((current_config->quirks | pipe_config->quirks) & (quirk))
12339
12340         PIPE_CONF_CHECK_I(cpu_transcoder);
12341
12342         PIPE_CONF_CHECK_I(has_pch_encoder);
12343         PIPE_CONF_CHECK_I(fdi_lanes);
12344         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12345         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12346         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12347         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12348         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12349
12350         PIPE_CONF_CHECK_I(has_dp_encoder);
12351
12352         if (INTEL_INFO(dev)->gen < 8) {
12353                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12354                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12355                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12356                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12357                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12358
12359                 if (current_config->has_drrs) {
12360                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12361                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12362                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12363                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12364                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12365                 }
12366         } else {
12367                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12368                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12369                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12370                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12371                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12372         }
12373
12374         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12375         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12376         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12377         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12378         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12379         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12380
12381         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12382         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12383         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12384         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12385         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12386         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12387
12388         PIPE_CONF_CHECK_I(pixel_multiplier);
12389         PIPE_CONF_CHECK_I(has_hdmi_sink);
12390         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12391             IS_VALLEYVIEW(dev))
12392                 PIPE_CONF_CHECK_I(limited_color_range);
12393         PIPE_CONF_CHECK_I(has_infoframe);
12394
12395         PIPE_CONF_CHECK_I(has_audio);
12396
12397         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12398                               DRM_MODE_FLAG_INTERLACE);
12399
12400         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12401                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12402                                       DRM_MODE_FLAG_PHSYNC);
12403                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12404                                       DRM_MODE_FLAG_NHSYNC);
12405                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12406                                       DRM_MODE_FLAG_PVSYNC);
12407                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12408                                       DRM_MODE_FLAG_NVSYNC);
12409         }
12410
12411         PIPE_CONF_CHECK_I(pipe_src_w);
12412         PIPE_CONF_CHECK_I(pipe_src_h);
12413
12414         /*
12415          * FIXME: BIOS likes to set up a cloned config with lvds+external
12416          * screen. Since we don't yet re-compute the pipe config when moving
12417          * just the lvds port away to another pipe the sw tracking won't match.
12418          *
12419          * Proper atomic modesets with recomputed global state will fix this.
12420          * Until then just don't check gmch state for inherited modes.
12421          */
12422         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12423                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12424                 /* pfit ratios are autocomputed by the hw on gen4+ */
12425                 if (INTEL_INFO(dev)->gen < 4)
12426                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12427                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12428         }
12429
12430         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12431         if (current_config->pch_pfit.enabled) {
12432                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12433                 PIPE_CONF_CHECK_I(pch_pfit.size);
12434         }
12435
12436         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12437
12438         /* BDW+ don't expose a synchronous way to read the state */
12439         if (IS_HASWELL(dev))
12440                 PIPE_CONF_CHECK_I(ips_enabled);
12441
12442         PIPE_CONF_CHECK_I(double_wide);
12443
12444         PIPE_CONF_CHECK_X(ddi_pll_sel);
12445
12446         PIPE_CONF_CHECK_I(shared_dpll);
12447         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12448         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12449         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12450         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12451         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12452         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12453         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12454         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12455
12456         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12457                 PIPE_CONF_CHECK_I(pipe_bpp);
12458
12459         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12460         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12461
12462 #undef PIPE_CONF_CHECK_X
12463 #undef PIPE_CONF_CHECK_I
12464 #undef PIPE_CONF_CHECK_I_ALT
12465 #undef PIPE_CONF_CHECK_FLAGS
12466 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12467 #undef PIPE_CONF_QUIRK
12468
12469         return true;
12470 }
12471
12472 static void check_wm_state(struct drm_device *dev)
12473 {
12474         struct drm_i915_private *dev_priv = dev->dev_private;
12475         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12476         struct intel_crtc *intel_crtc;
12477         int plane;
12478
12479         if (INTEL_INFO(dev)->gen < 9)
12480                 return;
12481
12482         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12483         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12484
12485         for_each_intel_crtc(dev, intel_crtc) {
12486                 struct skl_ddb_entry *hw_entry, *sw_entry;
12487                 const enum pipe pipe = intel_crtc->pipe;
12488
12489                 if (!intel_crtc->active)
12490                         continue;
12491
12492                 /* planes */
12493                 for_each_plane(dev_priv, pipe, plane) {
12494                         hw_entry = &hw_ddb.plane[pipe][plane];
12495                         sw_entry = &sw_ddb->plane[pipe][plane];
12496
12497                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12498                                 continue;
12499
12500                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12501                                   "(expected (%u,%u), found (%u,%u))\n",
12502                                   pipe_name(pipe), plane + 1,
12503                                   sw_entry->start, sw_entry->end,
12504                                   hw_entry->start, hw_entry->end);
12505                 }
12506
12507                 /* cursor */
12508                 hw_entry = &hw_ddb.cursor[pipe];
12509                 sw_entry = &sw_ddb->cursor[pipe];
12510
12511                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12512                         continue;
12513
12514                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12515                           "(expected (%u,%u), found (%u,%u))\n",
12516                           pipe_name(pipe),
12517                           sw_entry->start, sw_entry->end,
12518                           hw_entry->start, hw_entry->end);
12519         }
12520 }
12521
12522 static void
12523 check_connector_state(struct drm_device *dev)
12524 {
12525         struct intel_connector *connector;
12526
12527         for_each_intel_connector(dev, connector) {
12528                 /* This also checks the encoder/connector hw state with the
12529                  * ->get_hw_state callbacks. */
12530                 intel_connector_check_state(connector);
12531
12532                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12533                      "connector's staged encoder doesn't match current encoder\n");
12534         }
12535 }
12536
12537 static void
12538 check_encoder_state(struct drm_device *dev)
12539 {
12540         struct intel_encoder *encoder;
12541         struct intel_connector *connector;
12542
12543         for_each_intel_encoder(dev, encoder) {
12544                 bool enabled = false;
12545                 bool active = false;
12546                 enum pipe pipe, tracked_pipe;
12547
12548                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12549                               encoder->base.base.id,
12550                               encoder->base.name);
12551
12552                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12553                      "encoder's stage crtc doesn't match current crtc\n");
12554                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12555                      "encoder's active_connectors set, but no crtc\n");
12556
12557                 for_each_intel_connector(dev, connector) {
12558                         if (connector->base.encoder != &encoder->base)
12559                                 continue;
12560                         enabled = true;
12561                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12562                                 active = true;
12563                 }
12564                 /*
12565                  * for MST connectors if we unplug the connector is gone
12566                  * away but the encoder is still connected to a crtc
12567                  * until a modeset happens in response to the hotplug.
12568                  */
12569                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12570                         continue;
12571
12572                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12573                      "encoder's enabled state mismatch "
12574                      "(expected %i, found %i)\n",
12575                      !!encoder->base.crtc, enabled);
12576                 I915_STATE_WARN(active && !encoder->base.crtc,
12577                      "active encoder with no crtc\n");
12578
12579                 I915_STATE_WARN(encoder->connectors_active != active,
12580                      "encoder's computed active state doesn't match tracked active state "
12581                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12582
12583                 active = encoder->get_hw_state(encoder, &pipe);
12584                 I915_STATE_WARN(active != encoder->connectors_active,
12585                      "encoder's hw state doesn't match sw tracking "
12586                      "(expected %i, found %i)\n",
12587                      encoder->connectors_active, active);
12588
12589                 if (!encoder->base.crtc)
12590                         continue;
12591
12592                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12593                 I915_STATE_WARN(active && pipe != tracked_pipe,
12594                      "active encoder's pipe doesn't match"
12595                      "(expected %i, found %i)\n",
12596                      tracked_pipe, pipe);
12597
12598         }
12599 }
12600
12601 static void
12602 check_crtc_state(struct drm_device *dev)
12603 {
12604         struct drm_i915_private *dev_priv = dev->dev_private;
12605         struct intel_crtc *crtc;
12606         struct intel_encoder *encoder;
12607         struct intel_crtc_state pipe_config;
12608
12609         for_each_intel_crtc(dev, crtc) {
12610                 bool enabled = false;
12611                 bool active = false;
12612
12613                 memset(&pipe_config, 0, sizeof(pipe_config));
12614
12615                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12616                               crtc->base.base.id);
12617
12618                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12619                      "active crtc, but not enabled in sw tracking\n");
12620
12621                 for_each_intel_encoder(dev, encoder) {
12622                         if (encoder->base.crtc != &crtc->base)
12623                                 continue;
12624                         enabled = true;
12625                         if (encoder->connectors_active)
12626                                 active = true;
12627                 }
12628
12629                 I915_STATE_WARN(active != crtc->active,
12630                      "crtc's computed active state doesn't match tracked active state "
12631                      "(expected %i, found %i)\n", active, crtc->active);
12632                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12633                      "crtc's computed enabled state doesn't match tracked enabled state "
12634                      "(expected %i, found %i)\n", enabled,
12635                                 crtc->base.state->enable);
12636
12637                 active = dev_priv->display.get_pipe_config(crtc,
12638                                                            &pipe_config);
12639
12640                 /* hw state is inconsistent with the pipe quirk */
12641                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12642                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12643                         active = crtc->active;
12644
12645                 for_each_intel_encoder(dev, encoder) {
12646                         enum pipe pipe;
12647                         if (encoder->base.crtc != &crtc->base)
12648                                 continue;
12649                         if (encoder->get_hw_state(encoder, &pipe))
12650                                 encoder->get_config(encoder, &pipe_config);
12651                 }
12652
12653                 I915_STATE_WARN(crtc->active != active,
12654                      "crtc active state doesn't match with hw state "
12655                      "(expected %i, found %i)\n", crtc->active, active);
12656
12657                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12658                      "transitional active state does not match atomic hw state "
12659                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12660
12661                 if (active &&
12662                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12663                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12664                         intel_dump_pipe_config(crtc, &pipe_config,
12665                                                "[hw state]");
12666                         intel_dump_pipe_config(crtc, crtc->config,
12667                                                "[sw state]");
12668                 }
12669         }
12670 }
12671
12672 static void
12673 check_shared_dpll_state(struct drm_device *dev)
12674 {
12675         struct drm_i915_private *dev_priv = dev->dev_private;
12676         struct intel_crtc *crtc;
12677         struct intel_dpll_hw_state dpll_hw_state;
12678         int i;
12679
12680         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12681                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12682                 int enabled_crtcs = 0, active_crtcs = 0;
12683                 bool active;
12684
12685                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12686
12687                 DRM_DEBUG_KMS("%s\n", pll->name);
12688
12689                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12690
12691                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12692                      "more active pll users than references: %i vs %i\n",
12693                      pll->active, hweight32(pll->config.crtc_mask));
12694                 I915_STATE_WARN(pll->active && !pll->on,
12695                      "pll in active use but not on in sw tracking\n");
12696                 I915_STATE_WARN(pll->on && !pll->active,
12697                      "pll in on but not on in use in sw tracking\n");
12698                 I915_STATE_WARN(pll->on != active,
12699                      "pll on state mismatch (expected %i, found %i)\n",
12700                      pll->on, active);
12701
12702                 for_each_intel_crtc(dev, crtc) {
12703                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12704                                 enabled_crtcs++;
12705                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12706                                 active_crtcs++;
12707                 }
12708                 I915_STATE_WARN(pll->active != active_crtcs,
12709                      "pll active crtcs mismatch (expected %i, found %i)\n",
12710                      pll->active, active_crtcs);
12711                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12712                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12713                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12714
12715                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12716                                        sizeof(dpll_hw_state)),
12717                      "pll hw state mismatch\n");
12718         }
12719 }
12720
12721 void
12722 intel_modeset_check_state(struct drm_device *dev)
12723 {
12724         check_wm_state(dev);
12725         check_connector_state(dev);
12726         check_encoder_state(dev);
12727         check_crtc_state(dev);
12728         check_shared_dpll_state(dev);
12729 }
12730
12731 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12732                                      int dotclock)
12733 {
12734         /*
12735          * FDI already provided one idea for the dotclock.
12736          * Yell if the encoder disagrees.
12737          */
12738         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12739              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12740              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12741 }
12742
12743 static void update_scanline_offset(struct intel_crtc *crtc)
12744 {
12745         struct drm_device *dev = crtc->base.dev;
12746
12747         /*
12748          * The scanline counter increments at the leading edge of hsync.
12749          *
12750          * On most platforms it starts counting from vtotal-1 on the
12751          * first active line. That means the scanline counter value is
12752          * always one less than what we would expect. Ie. just after
12753          * start of vblank, which also occurs at start of hsync (on the
12754          * last active line), the scanline counter will read vblank_start-1.
12755          *
12756          * On gen2 the scanline counter starts counting from 1 instead
12757          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12758          * to keep the value positive), instead of adding one.
12759          *
12760          * On HSW+ the behaviour of the scanline counter depends on the output
12761          * type. For DP ports it behaves like most other platforms, but on HDMI
12762          * there's an extra 1 line difference. So we need to add two instead of
12763          * one to the value.
12764          */
12765         if (IS_GEN2(dev)) {
12766                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12767                 int vtotal;
12768
12769                 vtotal = mode->crtc_vtotal;
12770                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12771                         vtotal /= 2;
12772
12773                 crtc->scanline_offset = vtotal - 1;
12774         } else if (HAS_DDI(dev) &&
12775                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12776                 crtc->scanline_offset = 2;
12777         } else
12778                 crtc->scanline_offset = 1;
12779 }
12780
12781 static int intel_modeset_setup_plls(struct drm_atomic_state *state)
12782 {
12783         struct drm_device *dev = state->dev;
12784         struct drm_i915_private *dev_priv = to_i915(dev);
12785         unsigned clear_pipes = 0;
12786         struct intel_crtc *intel_crtc;
12787         struct intel_crtc_state *intel_crtc_state;
12788         struct drm_crtc *crtc;
12789         struct drm_crtc_state *crtc_state;
12790         int ret = 0;
12791         int i;
12792
12793         if (!dev_priv->display.crtc_compute_clock)
12794                 return 0;
12795
12796         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12797                 intel_crtc = to_intel_crtc(crtc);
12798                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12799
12800                 if (needs_modeset(crtc_state)) {
12801                         clear_pipes |= 1 << intel_crtc->pipe;
12802                         intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12803                 }
12804         }
12805
12806         if (clear_pipes) {
12807                 struct intel_shared_dpll_config *shared_dpll =
12808                         intel_atomic_get_shared_dpll_state(state);
12809
12810                 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12811                         shared_dpll[i].crtc_mask &= ~clear_pipes;
12812         }
12813
12814         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12815                 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12816                         continue;
12817
12818                 intel_crtc = to_intel_crtc(crtc);
12819                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12820
12821                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12822                                                            intel_crtc_state);
12823                 if (ret)
12824                         return ret;
12825         }
12826
12827         return ret;
12828 }
12829
12830 /*
12831  * This implements the workaround described in the "notes" section of the mode
12832  * set sequence documentation. When going from no pipes or single pipe to
12833  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12834  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12835  */
12836 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12837 {
12838         struct drm_crtc_state *crtc_state;
12839         struct intel_crtc *intel_crtc;
12840         struct drm_crtc *crtc;
12841         struct intel_crtc_state *first_crtc_state = NULL;
12842         struct intel_crtc_state *other_crtc_state = NULL;
12843         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12844         int i;
12845
12846         /* look at all crtc's that are going to be enabled in during modeset */
12847         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12848                 intel_crtc = to_intel_crtc(crtc);
12849
12850                 if (!crtc_state->active || !needs_modeset(crtc_state))
12851                         continue;
12852
12853                 if (first_crtc_state) {
12854                         other_crtc_state = to_intel_crtc_state(crtc_state);
12855                         break;
12856                 } else {
12857                         first_crtc_state = to_intel_crtc_state(crtc_state);
12858                         first_pipe = intel_crtc->pipe;
12859                 }
12860         }
12861
12862         /* No workaround needed? */
12863         if (!first_crtc_state)
12864                 return 0;
12865
12866         /* w/a possibly needed, check how many crtc's are already enabled. */
12867         for_each_intel_crtc(state->dev, intel_crtc) {
12868                 struct intel_crtc_state *pipe_config;
12869
12870                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12871                 if (IS_ERR(pipe_config))
12872                         return PTR_ERR(pipe_config);
12873
12874                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12875
12876                 if (!pipe_config->base.active ||
12877                     needs_modeset(&pipe_config->base))
12878                         continue;
12879
12880                 /* 2 or more enabled crtcs means no need for w/a */
12881                 if (enabled_pipe != INVALID_PIPE)
12882                         return 0;
12883
12884                 enabled_pipe = intel_crtc->pipe;
12885         }
12886
12887         if (enabled_pipe != INVALID_PIPE)
12888                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12889         else if (other_crtc_state)
12890                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12891
12892         return 0;
12893 }
12894
12895 /* Code that should eventually be part of atomic_check() */
12896 static int intel_modeset_checks(struct drm_atomic_state *state)
12897 {
12898         struct drm_device *dev = state->dev;
12899         int ret;
12900
12901         if (!check_digital_port_conflicts(state)) {
12902                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12903                 return -EINVAL;
12904         }
12905
12906         /*
12907          * See if the config requires any additional preparation, e.g.
12908          * to adjust global state with pipes off.  We need to do this
12909          * here so we can get the modeset_pipe updated config for the new
12910          * mode set on this crtc.  For other crtcs we need to use the
12911          * adjusted_mode bits in the crtc directly.
12912          */
12913         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12914                 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12915                         ret = valleyview_modeset_global_pipes(state);
12916                 else
12917                         ret = broadwell_modeset_global_pipes(state);
12918
12919                 if (ret)
12920                         return ret;
12921         }
12922
12923         ret = intel_modeset_setup_plls(state);
12924         if (ret)
12925                 return ret;
12926
12927         if (IS_HASWELL(dev))
12928                 ret = haswell_mode_set_planes_workaround(state);
12929
12930         return ret;
12931 }
12932
12933 static int
12934 intel_modeset_compute_config(struct drm_atomic_state *state)
12935 {
12936         struct drm_crtc *crtc;
12937         struct drm_crtc_state *crtc_state;
12938         int ret, i;
12939
12940         ret = drm_atomic_helper_check_modeset(state->dev, state);
12941         if (ret)
12942                 return ret;
12943
12944         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12945                 if (!crtc_state->enable &&
12946                     WARN_ON(crtc_state->active))
12947                         crtc_state->active = false;
12948
12949                 if (!crtc_state->enable)
12950                         continue;
12951
12952                 if (!needs_modeset(crtc_state)) {
12953                         ret = drm_atomic_add_affected_connectors(state, crtc);
12954                         if (ret)
12955                                 return ret;
12956                 }
12957
12958                 ret = intel_modeset_pipe_config(crtc,
12959                                         to_intel_crtc_state(crtc_state));
12960                 if (ret)
12961                         return ret;
12962
12963                 intel_dump_pipe_config(to_intel_crtc(crtc),
12964                                        to_intel_crtc_state(crtc_state),
12965                                        "[modeset]");
12966         }
12967
12968         ret = intel_modeset_checks(state);
12969         if (ret)
12970                 return ret;
12971
12972         return drm_atomic_helper_check_planes(state->dev, state);
12973 }
12974
12975 static int __intel_set_mode(struct drm_atomic_state *state)
12976 {
12977         struct drm_device *dev = state->dev;
12978         struct drm_i915_private *dev_priv = dev->dev_private;
12979         struct drm_crtc *crtc;
12980         struct drm_crtc_state *crtc_state;
12981         int ret = 0;
12982         int i;
12983
12984         ret = drm_atomic_helper_prepare_planes(dev, state);
12985         if (ret)
12986                 return ret;
12987
12988         drm_atomic_helper_swap_state(dev, state);
12989
12990         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12991                 if (!needs_modeset(crtc->state) || !crtc_state->active)
12992                         continue;
12993
12994                 intel_crtc_disable_planes(crtc);
12995                 dev_priv->display.crtc_disable(crtc);
12996         }
12997
12998         /* Only after disabling all output pipelines that will be changed can we
12999          * update the the output configuration. */
13000         intel_modeset_update_state(state);
13001
13002         /* The state has been swaped above, so state actually contains the
13003          * old state now. */
13004
13005         modeset_update_crtc_power_domains(state);
13006
13007         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13008         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13009                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13010
13011                 if (!needs_modeset(crtc->state) || !crtc->state->active)
13012                         continue;
13013
13014                 update_scanline_offset(to_intel_crtc(crtc));
13015
13016                 dev_priv->display.crtc_enable(crtc);
13017                 intel_crtc_enable_planes(crtc);
13018         }
13019
13020         /* FIXME: add subpixel order */
13021
13022         drm_atomic_helper_cleanup_planes(dev, state);
13023
13024         drm_atomic_state_free(state);
13025
13026         return 0;
13027 }
13028
13029 static int intel_set_mode_checked(struct drm_atomic_state *state)
13030 {
13031         struct drm_device *dev = state->dev;
13032         int ret;
13033
13034         ret = __intel_set_mode(state);
13035         if (ret == 0)
13036                 intel_modeset_check_state(dev);
13037
13038         return ret;
13039 }
13040
13041 static int intel_set_mode(struct drm_atomic_state *state)
13042 {
13043         int ret;
13044
13045         ret = intel_modeset_compute_config(state);
13046         if (ret)
13047                 return ret;
13048
13049         return intel_set_mode_checked(state);
13050 }
13051
13052 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13053 {
13054         struct drm_device *dev = crtc->dev;
13055         struct drm_atomic_state *state;
13056         struct intel_crtc *intel_crtc;
13057         struct intel_encoder *encoder;
13058         struct intel_connector *connector;
13059         struct drm_connector_state *connector_state;
13060         struct intel_crtc_state *crtc_state;
13061         int ret;
13062
13063         state = drm_atomic_state_alloc(dev);
13064         if (!state) {
13065                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13066                               crtc->base.id);
13067                 return;
13068         }
13069
13070         state->acquire_ctx = dev->mode_config.acquire_ctx;
13071
13072         /* The force restore path in the HW readout code relies on the staged
13073          * config still keeping the user requested config while the actual
13074          * state has been overwritten by the configuration read from HW. We
13075          * need to copy the staged config to the atomic state, otherwise the
13076          * mode set will just reapply the state the HW is already in. */
13077         for_each_intel_encoder(dev, encoder) {
13078                 if (&encoder->new_crtc->base != crtc)
13079                         continue;
13080
13081                 for_each_intel_connector(dev, connector) {
13082                         if (connector->new_encoder != encoder)
13083                                 continue;
13084
13085                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
13086                         if (IS_ERR(connector_state)) {
13087                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13088                                               connector->base.base.id,
13089                                               connector->base.name,
13090                                               PTR_ERR(connector_state));
13091                                 continue;
13092                         }
13093
13094                         connector_state->crtc = crtc;
13095                         connector_state->best_encoder = &encoder->base;
13096                 }
13097         }
13098
13099         for_each_intel_crtc(dev, intel_crtc) {
13100                 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13101                         continue;
13102
13103                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13104                 if (IS_ERR(crtc_state)) {
13105                         DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13106                                       intel_crtc->base.base.id,
13107                                       PTR_ERR(crtc_state));
13108                         continue;
13109                 }
13110
13111                 crtc_state->base.active = crtc_state->base.enable =
13112                         intel_crtc->new_enabled;
13113
13114                 if (&intel_crtc->base == crtc)
13115                         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13116         }
13117
13118         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13119                                         crtc->primary->fb, crtc->x, crtc->y);
13120
13121         ret = intel_set_mode(state);
13122         if (ret)
13123                 drm_atomic_state_free(state);
13124 }
13125
13126 #undef for_each_intel_crtc_masked
13127
13128 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13129                                         struct drm_mode_set *set)
13130 {
13131         int ro;
13132
13133         for (ro = 0; ro < set->num_connectors; ro++)
13134                 if (set->connectors[ro] == &connector->base)
13135                         return true;
13136
13137         return false;
13138 }
13139
13140 static int
13141 intel_modeset_stage_output_state(struct drm_device *dev,
13142                                  struct drm_mode_set *set,
13143                                  struct drm_atomic_state *state)
13144 {
13145         struct intel_connector *connector;
13146         struct drm_connector *drm_connector;
13147         struct drm_connector_state *connector_state;
13148         struct drm_crtc *crtc;
13149         struct drm_crtc_state *crtc_state;
13150         int i, ret;
13151
13152         /* The upper layers ensure that we either disable a crtc or have a list
13153          * of connectors. For paranoia, double-check this. */
13154         WARN_ON(!set->fb && (set->num_connectors != 0));
13155         WARN_ON(set->fb && (set->num_connectors == 0));
13156
13157         for_each_intel_connector(dev, connector) {
13158                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13159
13160                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13161                         continue;
13162
13163                 connector_state =
13164                         drm_atomic_get_connector_state(state, &connector->base);
13165                 if (IS_ERR(connector_state))
13166                         return PTR_ERR(connector_state);
13167
13168                 if (in_mode_set) {
13169                         int pipe = to_intel_crtc(set->crtc)->pipe;
13170                         connector_state->best_encoder =
13171                                 &intel_find_encoder(connector, pipe)->base;
13172                 }
13173
13174                 if (connector->base.state->crtc != set->crtc)
13175                         continue;
13176
13177                 /* If we disable the crtc, disable all its connectors. Also, if
13178                  * the connector is on the changing crtc but not on the new
13179                  * connector list, disable it. */
13180                 if (!set->fb || !in_mode_set) {
13181                         connector_state->best_encoder = NULL;
13182
13183                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13184                                 connector->base.base.id,
13185                                 connector->base.name);
13186                 }
13187         }
13188         /* connector->new_encoder is now updated for all connectors. */
13189
13190         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13191                 connector = to_intel_connector(drm_connector);
13192
13193                 if (!connector_state->best_encoder) {
13194                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13195                                                                 NULL);
13196                         if (ret)
13197                                 return ret;
13198
13199                         continue;
13200                 }
13201
13202                 if (intel_connector_in_mode_set(connector, set)) {
13203                         struct drm_crtc *crtc = connector->base.state->crtc;
13204
13205                         /* If this connector was in a previous crtc, add it
13206                          * to the state. We might need to disable it. */
13207                         if (crtc) {
13208                                 crtc_state =
13209                                         drm_atomic_get_crtc_state(state, crtc);
13210                                 if (IS_ERR(crtc_state))
13211                                         return PTR_ERR(crtc_state);
13212                         }
13213
13214                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13215                                                                 set->crtc);
13216                         if (ret)
13217                                 return ret;
13218                 }
13219
13220                 /* Make sure the new CRTC will work with the encoder */
13221                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13222                                          connector_state->crtc)) {
13223                         return -EINVAL;
13224                 }
13225
13226                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13227                         connector->base.base.id,
13228                         connector->base.name,
13229                         connector_state->crtc->base.id);
13230
13231                 if (connector_state->best_encoder != &connector->encoder->base)
13232                         connector->encoder =
13233                                 to_intel_encoder(connector_state->best_encoder);
13234         }
13235
13236         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13237                 bool has_connectors;
13238
13239                 ret = drm_atomic_add_affected_connectors(state, crtc);
13240                 if (ret)
13241                         return ret;
13242
13243                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13244                 if (has_connectors != crtc_state->enable)
13245                         crtc_state->enable =
13246                         crtc_state->active = has_connectors;
13247         }
13248
13249         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13250                                               set->fb, set->x, set->y);
13251         if (ret)
13252                 return ret;
13253
13254         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13255         if (IS_ERR(crtc_state))
13256                 return PTR_ERR(crtc_state);
13257
13258         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13259         if (ret)
13260                 return ret;
13261
13262         if (set->num_connectors)
13263                 crtc_state->active = true;
13264
13265         return 0;
13266 }
13267
13268 static int intel_crtc_set_config(struct drm_mode_set *set)
13269 {
13270         struct drm_device *dev;
13271         struct drm_atomic_state *state = NULL;
13272         int ret;
13273
13274         BUG_ON(!set);
13275         BUG_ON(!set->crtc);
13276         BUG_ON(!set->crtc->helper_private);
13277
13278         /* Enforce sane interface api - has been abused by the fb helper. */
13279         BUG_ON(!set->mode && set->fb);
13280         BUG_ON(set->fb && set->num_connectors == 0);
13281
13282         if (set->fb) {
13283                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13284                                 set->crtc->base.id, set->fb->base.id,
13285                                 (int)set->num_connectors, set->x, set->y);
13286         } else {
13287                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13288         }
13289
13290         dev = set->crtc->dev;
13291
13292         state = drm_atomic_state_alloc(dev);
13293         if (!state)
13294                 return -ENOMEM;
13295
13296         state->acquire_ctx = dev->mode_config.acquire_ctx;
13297
13298         ret = intel_modeset_stage_output_state(dev, set, state);
13299         if (ret)
13300                 goto out;
13301
13302         ret = intel_modeset_compute_config(state);
13303         if (ret)
13304                 goto out;
13305
13306         intel_update_pipe_size(to_intel_crtc(set->crtc));
13307
13308         ret = intel_set_mode_checked(state);
13309         if (ret) {
13310                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13311                               set->crtc->base.id, ret);
13312         }
13313
13314 out:
13315         if (ret)
13316                 drm_atomic_state_free(state);
13317         return ret;
13318 }
13319
13320 static const struct drm_crtc_funcs intel_crtc_funcs = {
13321         .gamma_set = intel_crtc_gamma_set,
13322         .set_config = intel_crtc_set_config,
13323         .destroy = intel_crtc_destroy,
13324         .page_flip = intel_crtc_page_flip,
13325         .atomic_duplicate_state = intel_crtc_duplicate_state,
13326         .atomic_destroy_state = intel_crtc_destroy_state,
13327 };
13328
13329 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13330                                       struct intel_shared_dpll *pll,
13331                                       struct intel_dpll_hw_state *hw_state)
13332 {
13333         uint32_t val;
13334
13335         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13336                 return false;
13337
13338         val = I915_READ(PCH_DPLL(pll->id));
13339         hw_state->dpll = val;
13340         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13341         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13342
13343         return val & DPLL_VCO_ENABLE;
13344 }
13345
13346 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13347                                   struct intel_shared_dpll *pll)
13348 {
13349         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13350         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13351 }
13352
13353 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13354                                 struct intel_shared_dpll *pll)
13355 {
13356         /* PCH refclock must be enabled first */
13357         ibx_assert_pch_refclk_enabled(dev_priv);
13358
13359         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13360
13361         /* Wait for the clocks to stabilize. */
13362         POSTING_READ(PCH_DPLL(pll->id));
13363         udelay(150);
13364
13365         /* The pixel multiplier can only be updated once the
13366          * DPLL is enabled and the clocks are stable.
13367          *
13368          * So write it again.
13369          */
13370         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13371         POSTING_READ(PCH_DPLL(pll->id));
13372         udelay(200);
13373 }
13374
13375 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13376                                  struct intel_shared_dpll *pll)
13377 {
13378         struct drm_device *dev = dev_priv->dev;
13379         struct intel_crtc *crtc;
13380
13381         /* Make sure no transcoder isn't still depending on us. */
13382         for_each_intel_crtc(dev, crtc) {
13383                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13384                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13385         }
13386
13387         I915_WRITE(PCH_DPLL(pll->id), 0);
13388         POSTING_READ(PCH_DPLL(pll->id));
13389         udelay(200);
13390 }
13391
13392 static char *ibx_pch_dpll_names[] = {
13393         "PCH DPLL A",
13394         "PCH DPLL B",
13395 };
13396
13397 static void ibx_pch_dpll_init(struct drm_device *dev)
13398 {
13399         struct drm_i915_private *dev_priv = dev->dev_private;
13400         int i;
13401
13402         dev_priv->num_shared_dpll = 2;
13403
13404         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13405                 dev_priv->shared_dplls[i].id = i;
13406                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13407                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13408                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13409                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13410                 dev_priv->shared_dplls[i].get_hw_state =
13411                         ibx_pch_dpll_get_hw_state;
13412         }
13413 }
13414
13415 static void intel_shared_dpll_init(struct drm_device *dev)
13416 {
13417         struct drm_i915_private *dev_priv = dev->dev_private;
13418
13419         intel_update_cdclk(dev);
13420
13421         if (HAS_DDI(dev))
13422                 intel_ddi_pll_init(dev);
13423         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13424                 ibx_pch_dpll_init(dev);
13425         else
13426                 dev_priv->num_shared_dpll = 0;
13427
13428         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13429 }
13430
13431 /**
13432  * intel_wm_need_update - Check whether watermarks need updating
13433  * @plane: drm plane
13434  * @state: new plane state
13435  *
13436  * Check current plane state versus the new one to determine whether
13437  * watermarks need to be recalculated.
13438  *
13439  * Returns true or false.
13440  */
13441 bool intel_wm_need_update(struct drm_plane *plane,
13442                           struct drm_plane_state *state)
13443 {
13444         /* Update watermarks on tiling changes. */
13445         if (!plane->state->fb || !state->fb ||
13446             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13447             plane->state->rotation != state->rotation)
13448                 return true;
13449
13450         return false;
13451 }
13452
13453 /**
13454  * intel_prepare_plane_fb - Prepare fb for usage on plane
13455  * @plane: drm plane to prepare for
13456  * @fb: framebuffer to prepare for presentation
13457  *
13458  * Prepares a framebuffer for usage on a display plane.  Generally this
13459  * involves pinning the underlying object and updating the frontbuffer tracking
13460  * bits.  Some older platforms need special physical address handling for
13461  * cursor planes.
13462  *
13463  * Returns 0 on success, negative error code on failure.
13464  */
13465 int
13466 intel_prepare_plane_fb(struct drm_plane *plane,
13467                        struct drm_framebuffer *fb,
13468                        const struct drm_plane_state *new_state)
13469 {
13470         struct drm_device *dev = plane->dev;
13471         struct intel_plane *intel_plane = to_intel_plane(plane);
13472         enum pipe pipe = intel_plane->pipe;
13473         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13474         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13475         unsigned frontbuffer_bits = 0;
13476         int ret = 0;
13477
13478         if (!obj)
13479                 return 0;
13480
13481         switch (plane->type) {
13482         case DRM_PLANE_TYPE_PRIMARY:
13483                 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13484                 break;
13485         case DRM_PLANE_TYPE_CURSOR:
13486                 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13487                 break;
13488         case DRM_PLANE_TYPE_OVERLAY:
13489                 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13490                 break;
13491         }
13492
13493         mutex_lock(&dev->struct_mutex);
13494
13495         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13496             INTEL_INFO(dev)->cursor_needs_physical) {
13497                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13498                 ret = i915_gem_object_attach_phys(obj, align);
13499                 if (ret)
13500                         DRM_DEBUG_KMS("failed to attach phys object\n");
13501         } else {
13502                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
13503         }
13504
13505         if (ret == 0)
13506                 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
13507
13508         mutex_unlock(&dev->struct_mutex);
13509
13510         return ret;
13511 }
13512
13513 /**
13514  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13515  * @plane: drm plane to clean up for
13516  * @fb: old framebuffer that was on plane
13517  *
13518  * Cleans up a framebuffer that has just been removed from a plane.
13519  */
13520 void
13521 intel_cleanup_plane_fb(struct drm_plane *plane,
13522                        struct drm_framebuffer *fb,
13523                        const struct drm_plane_state *old_state)
13524 {
13525         struct drm_device *dev = plane->dev;
13526         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13527
13528         if (WARN_ON(!obj))
13529                 return;
13530
13531         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13532             !INTEL_INFO(dev)->cursor_needs_physical) {
13533                 mutex_lock(&dev->struct_mutex);
13534                 intel_unpin_fb_obj(fb, old_state);
13535                 mutex_unlock(&dev->struct_mutex);
13536         }
13537 }
13538
13539 int
13540 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13541 {
13542         int max_scale;
13543         struct drm_device *dev;
13544         struct drm_i915_private *dev_priv;
13545         int crtc_clock, cdclk;
13546
13547         if (!intel_crtc || !crtc_state)
13548                 return DRM_PLANE_HELPER_NO_SCALING;
13549
13550         dev = intel_crtc->base.dev;
13551         dev_priv = dev->dev_private;
13552         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13553         cdclk = dev_priv->display.get_display_clock_speed(dev);
13554
13555         if (!crtc_clock || !cdclk)
13556                 return DRM_PLANE_HELPER_NO_SCALING;
13557
13558         /*
13559          * skl max scale is lower of:
13560          *    close to 3 but not 3, -1 is for that purpose
13561          *            or
13562          *    cdclk/crtc_clock
13563          */
13564         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13565
13566         return max_scale;
13567 }
13568
13569 static int
13570 intel_check_primary_plane(struct drm_plane *plane,
13571                           struct intel_plane_state *state)
13572 {
13573         struct drm_device *dev = plane->dev;
13574         struct drm_i915_private *dev_priv = dev->dev_private;
13575         struct drm_crtc *crtc = state->base.crtc;
13576         struct intel_crtc *intel_crtc;
13577         struct intel_crtc_state *crtc_state;
13578         struct drm_framebuffer *fb = state->base.fb;
13579         struct drm_rect *dest = &state->dst;
13580         struct drm_rect *src = &state->src;
13581         const struct drm_rect *clip = &state->clip;
13582         bool can_position = false;
13583         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13584         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13585         int ret;
13586
13587         crtc = crtc ? crtc : plane->crtc;
13588         intel_crtc = to_intel_crtc(crtc);
13589         crtc_state = state->base.state ?
13590                 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13591
13592         if (INTEL_INFO(dev)->gen >= 9) {
13593                 /* use scaler when colorkey is not required */
13594                 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13595                         min_scale = 1;
13596                         max_scale = skl_max_scale(intel_crtc, crtc_state);
13597                 }
13598                 can_position = true;
13599         }
13600
13601         ret = drm_plane_helper_check_update(plane, crtc, fb,
13602                                             src, dest, clip,
13603                                             min_scale,
13604                                             max_scale,
13605                                             can_position, true,
13606                                             &state->visible);
13607         if (ret)
13608                 return ret;
13609
13610         if (intel_crtc->active) {
13611                 struct intel_plane_state *old_state =
13612                         to_intel_plane_state(plane->state);
13613
13614                 intel_crtc->atomic.wait_for_flips = true;
13615
13616                 /*
13617                  * FBC does not work on some platforms for rotated
13618                  * planes, so disable it when rotation is not 0 and
13619                  * update it when rotation is set back to 0.
13620                  *
13621                  * FIXME: This is redundant with the fbc update done in
13622                  * the primary plane enable function except that that
13623                  * one is done too late. We eventually need to unify
13624                  * this.
13625                  */
13626                 if (state->visible &&
13627                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13628                     dev_priv->fbc.crtc == intel_crtc &&
13629                     state->base.rotation != BIT(DRM_ROTATE_0)) {
13630                         intel_crtc->atomic.disable_fbc = true;
13631                 }
13632
13633                 if (state->visible && !old_state->visible) {
13634                         /*
13635                          * BDW signals flip done immediately if the plane
13636                          * is disabled, even if the plane enable is already
13637                          * armed to occur at the next vblank :(
13638                          */
13639                         if (IS_BROADWELL(dev))
13640                                 intel_crtc->atomic.wait_vblank = true;
13641
13642                         if (crtc_state && !needs_modeset(&crtc_state->base))
13643                                 intel_crtc->atomic.post_enable_primary = true;
13644                 }
13645
13646                 if (!state->visible && old_state->visible &&
13647                     crtc_state && !needs_modeset(&crtc_state->base))
13648                         intel_crtc->atomic.pre_disable_primary = true;
13649
13650                 intel_crtc->atomic.fb_bits |=
13651                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13652
13653                 intel_crtc->atomic.update_fbc = true;
13654
13655                 if (intel_wm_need_update(plane, &state->base))
13656                         intel_crtc->atomic.update_wm = true;
13657         }
13658
13659         if (INTEL_INFO(dev)->gen >= 9) {
13660                 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13661                         to_intel_plane(plane), state, 0);
13662                 if (ret)
13663                         return ret;
13664         }
13665
13666         return 0;
13667 }
13668
13669 static void
13670 intel_commit_primary_plane(struct drm_plane *plane,
13671                            struct intel_plane_state *state)
13672 {
13673         struct drm_crtc *crtc = state->base.crtc;
13674         struct drm_framebuffer *fb = state->base.fb;
13675         struct drm_device *dev = plane->dev;
13676         struct drm_i915_private *dev_priv = dev->dev_private;
13677         struct intel_crtc *intel_crtc;
13678         struct drm_rect *src = &state->src;
13679
13680         crtc = crtc ? crtc : plane->crtc;
13681         intel_crtc = to_intel_crtc(crtc);
13682
13683         plane->fb = fb;
13684         crtc->x = src->x1 >> 16;
13685         crtc->y = src->y1 >> 16;
13686
13687         if (intel_crtc->active) {
13688                 if (state->visible)
13689                         /* FIXME: kill this fastboot hack */
13690                         intel_update_pipe_size(intel_crtc);
13691
13692                 dev_priv->display.update_primary_plane(crtc, plane->fb,
13693                                                        crtc->x, crtc->y);
13694         }
13695 }
13696
13697 static void
13698 intel_disable_primary_plane(struct drm_plane *plane,
13699                             struct drm_crtc *crtc,
13700                             bool force)
13701 {
13702         struct drm_device *dev = plane->dev;
13703         struct drm_i915_private *dev_priv = dev->dev_private;
13704
13705         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13706 }
13707
13708 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13709 {
13710         struct drm_device *dev = crtc->dev;
13711         struct drm_i915_private *dev_priv = dev->dev_private;
13712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13713         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
13714         struct intel_plane *intel_plane;
13715         struct drm_plane *p;
13716         unsigned fb_bits = 0;
13717
13718         /* Track fb's for any planes being disabled */
13719         list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13720                 intel_plane = to_intel_plane(p);
13721
13722                 if (intel_crtc->atomic.disabled_planes &
13723                     (1 << drm_plane_index(p))) {
13724                         switch (p->type) {
13725                         case DRM_PLANE_TYPE_PRIMARY:
13726                                 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13727                                 break;
13728                         case DRM_PLANE_TYPE_CURSOR:
13729                                 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13730                                 break;
13731                         case DRM_PLANE_TYPE_OVERLAY:
13732                                 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13733                                 break;
13734                         }
13735
13736                         mutex_lock(&dev->struct_mutex);
13737                         i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13738                         mutex_unlock(&dev->struct_mutex);
13739                 }
13740         }
13741
13742         if (intel_crtc->atomic.wait_for_flips)
13743                 intel_crtc_wait_for_pending_flips(crtc);
13744
13745         if (intel_crtc->atomic.disable_fbc)
13746                 intel_fbc_disable(dev);
13747
13748         if (intel_crtc->atomic.pre_disable_primary)
13749                 intel_pre_disable_primary(crtc);
13750
13751         if (intel_crtc->atomic.update_wm)
13752                 intel_update_watermarks(crtc);
13753
13754         intel_runtime_pm_get(dev_priv);
13755
13756         /* Perform vblank evasion around commit operation */
13757         if (crtc_state->active && !needs_modeset(crtc_state))
13758                 intel_crtc->atomic.evade =
13759                         intel_pipe_update_start(intel_crtc,
13760                                                 &intel_crtc->atomic.start_vbl_count);
13761 }
13762
13763 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13764 {
13765         struct drm_device *dev = crtc->dev;
13766         struct drm_i915_private *dev_priv = dev->dev_private;
13767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13768         struct drm_plane *p;
13769
13770         if (intel_crtc->atomic.evade)
13771                 intel_pipe_update_end(intel_crtc,
13772                                       intel_crtc->atomic.start_vbl_count);
13773
13774         intel_runtime_pm_put(dev_priv);
13775
13776         if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
13777                 intel_wait_for_vblank(dev, intel_crtc->pipe);
13778
13779         intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13780
13781         if (intel_crtc->atomic.update_fbc) {
13782                 mutex_lock(&dev->struct_mutex);
13783                 intel_fbc_update(dev);
13784                 mutex_unlock(&dev->struct_mutex);
13785         }
13786
13787         if (intel_crtc->atomic.post_enable_primary)
13788                 intel_post_enable_primary(crtc);
13789
13790         drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13791                 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13792                         intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13793                                                        false, false);
13794
13795         memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13796 }
13797
13798 /**
13799  * intel_plane_destroy - destroy a plane
13800  * @plane: plane to destroy
13801  *
13802  * Common destruction function for all types of planes (primary, cursor,
13803  * sprite).
13804  */
13805 void intel_plane_destroy(struct drm_plane *plane)
13806 {
13807         struct intel_plane *intel_plane = to_intel_plane(plane);
13808         drm_plane_cleanup(plane);
13809         kfree(intel_plane);
13810 }
13811
13812 const struct drm_plane_funcs intel_plane_funcs = {
13813         .update_plane = drm_atomic_helper_update_plane,
13814         .disable_plane = drm_atomic_helper_disable_plane,
13815         .destroy = intel_plane_destroy,
13816         .set_property = drm_atomic_helper_plane_set_property,
13817         .atomic_get_property = intel_plane_atomic_get_property,
13818         .atomic_set_property = intel_plane_atomic_set_property,
13819         .atomic_duplicate_state = intel_plane_duplicate_state,
13820         .atomic_destroy_state = intel_plane_destroy_state,
13821
13822 };
13823
13824 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13825                                                     int pipe)
13826 {
13827         struct intel_plane *primary;
13828         struct intel_plane_state *state;
13829         const uint32_t *intel_primary_formats;
13830         int num_formats;
13831
13832         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13833         if (primary == NULL)
13834                 return NULL;
13835
13836         state = intel_create_plane_state(&primary->base);
13837         if (!state) {
13838                 kfree(primary);
13839                 return NULL;
13840         }
13841         primary->base.state = &state->base;
13842
13843         primary->can_scale = false;
13844         primary->max_downscale = 1;
13845         if (INTEL_INFO(dev)->gen >= 9) {
13846                 primary->can_scale = true;
13847                 state->scaler_id = -1;
13848         }
13849         primary->pipe = pipe;
13850         primary->plane = pipe;
13851         primary->check_plane = intel_check_primary_plane;
13852         primary->commit_plane = intel_commit_primary_plane;
13853         primary->disable_plane = intel_disable_primary_plane;
13854         primary->ckey.flags = I915_SET_COLORKEY_NONE;
13855         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13856                 primary->plane = !pipe;
13857
13858         if (INTEL_INFO(dev)->gen >= 9) {
13859                 intel_primary_formats = skl_primary_formats;
13860                 num_formats = ARRAY_SIZE(skl_primary_formats);
13861         } else if (INTEL_INFO(dev)->gen >= 4) {
13862                 intel_primary_formats = i965_primary_formats;
13863                 num_formats = ARRAY_SIZE(i965_primary_formats);
13864         } else {
13865                 intel_primary_formats = i8xx_primary_formats;
13866                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13867         }
13868
13869         drm_universal_plane_init(dev, &primary->base, 0,
13870                                  &intel_plane_funcs,
13871                                  intel_primary_formats, num_formats,
13872                                  DRM_PLANE_TYPE_PRIMARY);
13873
13874         if (INTEL_INFO(dev)->gen >= 4)
13875                 intel_create_rotation_property(dev, primary);
13876
13877         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13878
13879         return &primary->base;
13880 }
13881
13882 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13883 {
13884         if (!dev->mode_config.rotation_property) {
13885                 unsigned long flags = BIT(DRM_ROTATE_0) |
13886                         BIT(DRM_ROTATE_180);
13887
13888                 if (INTEL_INFO(dev)->gen >= 9)
13889                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13890
13891                 dev->mode_config.rotation_property =
13892                         drm_mode_create_rotation_property(dev, flags);
13893         }
13894         if (dev->mode_config.rotation_property)
13895                 drm_object_attach_property(&plane->base.base,
13896                                 dev->mode_config.rotation_property,
13897                                 plane->base.state->rotation);
13898 }
13899
13900 static int
13901 intel_check_cursor_plane(struct drm_plane *plane,
13902                          struct intel_plane_state *state)
13903 {
13904         struct drm_crtc *crtc = state->base.crtc;
13905         struct drm_device *dev = plane->dev;
13906         struct drm_framebuffer *fb = state->base.fb;
13907         struct drm_rect *dest = &state->dst;
13908         struct drm_rect *src = &state->src;
13909         const struct drm_rect *clip = &state->clip;
13910         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13911         struct intel_crtc *intel_crtc;
13912         unsigned stride;
13913         int ret;
13914
13915         crtc = crtc ? crtc : plane->crtc;
13916         intel_crtc = to_intel_crtc(crtc);
13917
13918         ret = drm_plane_helper_check_update(plane, crtc, fb,
13919                                             src, dest, clip,
13920                                             DRM_PLANE_HELPER_NO_SCALING,
13921                                             DRM_PLANE_HELPER_NO_SCALING,
13922                                             true, true, &state->visible);
13923         if (ret)
13924                 return ret;
13925
13926
13927         /* if we want to turn off the cursor ignore width and height */
13928         if (!obj)
13929                 goto finish;
13930
13931         /* Check for which cursor types we support */
13932         if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13933                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13934                           state->base.crtc_w, state->base.crtc_h);
13935                 return -EINVAL;
13936         }
13937
13938         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13939         if (obj->base.size < stride * state->base.crtc_h) {
13940                 DRM_DEBUG_KMS("buffer is too small\n");
13941                 return -ENOMEM;
13942         }
13943
13944         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13945                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13946                 ret = -EINVAL;
13947         }
13948
13949 finish:
13950         if (intel_crtc->active) {
13951                 if (plane->state->crtc_w != state->base.crtc_w)
13952                         intel_crtc->atomic.update_wm = true;
13953
13954                 intel_crtc->atomic.fb_bits |=
13955                         INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13956         }
13957
13958         return ret;
13959 }
13960
13961 static void
13962 intel_disable_cursor_plane(struct drm_plane *plane,
13963                            struct drm_crtc *crtc,
13964                            bool force)
13965 {
13966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13967
13968         if (!force) {
13969                 plane->fb = NULL;
13970                 intel_crtc->cursor_bo = NULL;
13971                 intel_crtc->cursor_addr = 0;
13972         }
13973
13974         intel_crtc_update_cursor(crtc, false);
13975 }
13976
13977 static void
13978 intel_commit_cursor_plane(struct drm_plane *plane,
13979                           struct intel_plane_state *state)
13980 {
13981         struct drm_crtc *crtc = state->base.crtc;
13982         struct drm_device *dev = plane->dev;
13983         struct intel_crtc *intel_crtc;
13984         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13985         uint32_t addr;
13986
13987         crtc = crtc ? crtc : plane->crtc;
13988         intel_crtc = to_intel_crtc(crtc);
13989
13990         plane->fb = state->base.fb;
13991         crtc->cursor_x = state->base.crtc_x;
13992         crtc->cursor_y = state->base.crtc_y;
13993
13994         if (intel_crtc->cursor_bo == obj)
13995                 goto update;
13996
13997         if (!obj)
13998                 addr = 0;
13999         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14000                 addr = i915_gem_obj_ggtt_offset(obj);
14001         else
14002                 addr = obj->phys_handle->busaddr;
14003
14004         intel_crtc->cursor_addr = addr;
14005         intel_crtc->cursor_bo = obj;
14006 update:
14007
14008         if (intel_crtc->active)
14009                 intel_crtc_update_cursor(crtc, state->visible);
14010 }
14011
14012 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14013                                                    int pipe)
14014 {
14015         struct intel_plane *cursor;
14016         struct intel_plane_state *state;
14017
14018         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14019         if (cursor == NULL)
14020                 return NULL;
14021
14022         state = intel_create_plane_state(&cursor->base);
14023         if (!state) {
14024                 kfree(cursor);
14025                 return NULL;
14026         }
14027         cursor->base.state = &state->base;
14028
14029         cursor->can_scale = false;
14030         cursor->max_downscale = 1;
14031         cursor->pipe = pipe;
14032         cursor->plane = pipe;
14033         cursor->check_plane = intel_check_cursor_plane;
14034         cursor->commit_plane = intel_commit_cursor_plane;
14035         cursor->disable_plane = intel_disable_cursor_plane;
14036
14037         drm_universal_plane_init(dev, &cursor->base, 0,
14038                                  &intel_plane_funcs,
14039                                  intel_cursor_formats,
14040                                  ARRAY_SIZE(intel_cursor_formats),
14041                                  DRM_PLANE_TYPE_CURSOR);
14042
14043         if (INTEL_INFO(dev)->gen >= 4) {
14044                 if (!dev->mode_config.rotation_property)
14045                         dev->mode_config.rotation_property =
14046                                 drm_mode_create_rotation_property(dev,
14047                                                         BIT(DRM_ROTATE_0) |
14048                                                         BIT(DRM_ROTATE_180));
14049                 if (dev->mode_config.rotation_property)
14050                         drm_object_attach_property(&cursor->base.base,
14051                                 dev->mode_config.rotation_property,
14052                                 state->base.rotation);
14053         }
14054
14055         if (INTEL_INFO(dev)->gen >=9)
14056                 state->scaler_id = -1;
14057
14058         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14059
14060         return &cursor->base;
14061 }
14062
14063 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14064         struct intel_crtc_state *crtc_state)
14065 {
14066         int i;
14067         struct intel_scaler *intel_scaler;
14068         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14069
14070         for (i = 0; i < intel_crtc->num_scalers; i++) {
14071                 intel_scaler = &scaler_state->scalers[i];
14072                 intel_scaler->in_use = 0;
14073                 intel_scaler->id = i;
14074
14075                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14076         }
14077
14078         scaler_state->scaler_id = -1;
14079 }
14080
14081 static void intel_crtc_init(struct drm_device *dev, int pipe)
14082 {
14083         struct drm_i915_private *dev_priv = dev->dev_private;
14084         struct intel_crtc *intel_crtc;
14085         struct intel_crtc_state *crtc_state = NULL;
14086         struct drm_plane *primary = NULL;
14087         struct drm_plane *cursor = NULL;
14088         int i, ret;
14089
14090         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14091         if (intel_crtc == NULL)
14092                 return;
14093
14094         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14095         if (!crtc_state)
14096                 goto fail;
14097         intel_crtc->config = crtc_state;
14098         intel_crtc->base.state = &crtc_state->base;
14099         crtc_state->base.crtc = &intel_crtc->base;
14100
14101         /* initialize shared scalers */
14102         if (INTEL_INFO(dev)->gen >= 9) {
14103                 if (pipe == PIPE_C)
14104                         intel_crtc->num_scalers = 1;
14105                 else
14106                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14107
14108                 skl_init_scalers(dev, intel_crtc, crtc_state);
14109         }
14110
14111         primary = intel_primary_plane_create(dev, pipe);
14112         if (!primary)
14113                 goto fail;
14114
14115         cursor = intel_cursor_plane_create(dev, pipe);
14116         if (!cursor)
14117                 goto fail;
14118
14119         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14120                                         cursor, &intel_crtc_funcs);
14121         if (ret)
14122                 goto fail;
14123
14124         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14125         for (i = 0; i < 256; i++) {
14126                 intel_crtc->lut_r[i] = i;
14127                 intel_crtc->lut_g[i] = i;
14128                 intel_crtc->lut_b[i] = i;
14129         }
14130
14131         /*
14132          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14133          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14134          */
14135         intel_crtc->pipe = pipe;
14136         intel_crtc->plane = pipe;
14137         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14138                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14139                 intel_crtc->plane = !pipe;
14140         }
14141
14142         intel_crtc->cursor_base = ~0;
14143         intel_crtc->cursor_cntl = ~0;
14144         intel_crtc->cursor_size = ~0;
14145
14146         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14147                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14148         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14149         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14150
14151         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14152
14153         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14154         return;
14155
14156 fail:
14157         if (primary)
14158                 drm_plane_cleanup(primary);
14159         if (cursor)
14160                 drm_plane_cleanup(cursor);
14161         kfree(crtc_state);
14162         kfree(intel_crtc);
14163 }
14164
14165 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14166 {
14167         struct drm_encoder *encoder = connector->base.encoder;
14168         struct drm_device *dev = connector->base.dev;
14169
14170         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14171
14172         if (!encoder || WARN_ON(!encoder->crtc))
14173                 return INVALID_PIPE;
14174
14175         return to_intel_crtc(encoder->crtc)->pipe;
14176 }
14177
14178 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14179                                 struct drm_file *file)
14180 {
14181         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14182         struct drm_crtc *drmmode_crtc;
14183         struct intel_crtc *crtc;
14184
14185         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14186
14187         if (!drmmode_crtc) {
14188                 DRM_ERROR("no such CRTC id\n");
14189                 return -ENOENT;
14190         }
14191
14192         crtc = to_intel_crtc(drmmode_crtc);
14193         pipe_from_crtc_id->pipe = crtc->pipe;
14194
14195         return 0;
14196 }
14197
14198 static int intel_encoder_clones(struct intel_encoder *encoder)
14199 {
14200         struct drm_device *dev = encoder->base.dev;
14201         struct intel_encoder *source_encoder;
14202         int index_mask = 0;
14203         int entry = 0;
14204
14205         for_each_intel_encoder(dev, source_encoder) {
14206                 if (encoders_cloneable(encoder, source_encoder))
14207                         index_mask |= (1 << entry);
14208
14209                 entry++;
14210         }
14211
14212         return index_mask;
14213 }
14214
14215 static bool has_edp_a(struct drm_device *dev)
14216 {
14217         struct drm_i915_private *dev_priv = dev->dev_private;
14218
14219         if (!IS_MOBILE(dev))
14220                 return false;
14221
14222         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14223                 return false;
14224
14225         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14226                 return false;
14227
14228         return true;
14229 }
14230
14231 static bool intel_crt_present(struct drm_device *dev)
14232 {
14233         struct drm_i915_private *dev_priv = dev->dev_private;
14234
14235         if (INTEL_INFO(dev)->gen >= 9)
14236                 return false;
14237
14238         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14239                 return false;
14240
14241         if (IS_CHERRYVIEW(dev))
14242                 return false;
14243
14244         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14245                 return false;
14246
14247         return true;
14248 }
14249
14250 static void intel_setup_outputs(struct drm_device *dev)
14251 {
14252         struct drm_i915_private *dev_priv = dev->dev_private;
14253         struct intel_encoder *encoder;
14254         bool dpd_is_edp = false;
14255
14256         intel_lvds_init(dev);
14257
14258         if (intel_crt_present(dev))
14259                 intel_crt_init(dev);
14260
14261         if (IS_BROXTON(dev)) {
14262                 /*
14263                  * FIXME: Broxton doesn't support port detection via the
14264                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14265                  * detect the ports.
14266                  */
14267                 intel_ddi_init(dev, PORT_A);
14268                 intel_ddi_init(dev, PORT_B);
14269                 intel_ddi_init(dev, PORT_C);
14270         } else if (HAS_DDI(dev)) {
14271                 int found;
14272
14273                 /*
14274                  * Haswell uses DDI functions to detect digital outputs.
14275                  * On SKL pre-D0 the strap isn't connected, so we assume
14276                  * it's there.
14277                  */
14278                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14279                 /* WaIgnoreDDIAStrap: skl */
14280                 if (found ||
14281                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14282                         intel_ddi_init(dev, PORT_A);
14283
14284                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14285                  * register */
14286                 found = I915_READ(SFUSE_STRAP);
14287
14288                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14289                         intel_ddi_init(dev, PORT_B);
14290                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14291                         intel_ddi_init(dev, PORT_C);
14292                 if (found & SFUSE_STRAP_DDID_DETECTED)
14293                         intel_ddi_init(dev, PORT_D);
14294         } else if (HAS_PCH_SPLIT(dev)) {
14295                 int found;
14296                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14297
14298                 if (has_edp_a(dev))
14299                         intel_dp_init(dev, DP_A, PORT_A);
14300
14301                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14302                         /* PCH SDVOB multiplex with HDMIB */
14303                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14304                         if (!found)
14305                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14306                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14307                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14308                 }
14309
14310                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14311                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14312
14313                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14314                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14315
14316                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14317                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14318
14319                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14320                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14321         } else if (IS_VALLEYVIEW(dev)) {
14322                 /*
14323                  * The DP_DETECTED bit is the latched state of the DDC
14324                  * SDA pin at boot. However since eDP doesn't require DDC
14325                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14326                  * eDP ports may have been muxed to an alternate function.
14327                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14328                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14329                  * detect eDP ports.
14330                  */
14331                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14332                     !intel_dp_is_edp(dev, PORT_B))
14333                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14334                                         PORT_B);
14335                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14336                     intel_dp_is_edp(dev, PORT_B))
14337                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14338
14339                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14340                     !intel_dp_is_edp(dev, PORT_C))
14341                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14342                                         PORT_C);
14343                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14344                     intel_dp_is_edp(dev, PORT_C))
14345                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14346
14347                 if (IS_CHERRYVIEW(dev)) {
14348                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14349                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14350                                                 PORT_D);
14351                         /* eDP not supported on port D, so don't check VBT */
14352                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14353                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14354                 }
14355
14356                 intel_dsi_init(dev);
14357         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14358                 bool found = false;
14359
14360                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14361                         DRM_DEBUG_KMS("probing SDVOB\n");
14362                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14363                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14364                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14365                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14366                         }
14367
14368                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
14369                                 intel_dp_init(dev, DP_B, PORT_B);
14370                 }
14371
14372                 /* Before G4X SDVOC doesn't have its own detect register */
14373
14374                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14375                         DRM_DEBUG_KMS("probing SDVOC\n");
14376                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14377                 }
14378
14379                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14380
14381                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14382                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14383                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14384                         }
14385                         if (SUPPORTS_INTEGRATED_DP(dev))
14386                                 intel_dp_init(dev, DP_C, PORT_C);
14387                 }
14388
14389                 if (SUPPORTS_INTEGRATED_DP(dev) &&
14390                     (I915_READ(DP_D) & DP_DETECTED))
14391                         intel_dp_init(dev, DP_D, PORT_D);
14392         } else if (IS_GEN2(dev))
14393                 intel_dvo_init(dev);
14394
14395         if (SUPPORTS_TV(dev))
14396                 intel_tv_init(dev);
14397
14398         intel_psr_init(dev);
14399
14400         for_each_intel_encoder(dev, encoder) {
14401                 encoder->base.possible_crtcs = encoder->crtc_mask;
14402                 encoder->base.possible_clones =
14403                         intel_encoder_clones(encoder);
14404         }
14405
14406         intel_init_pch_refclk(dev);
14407
14408         drm_helper_move_panel_connectors_to_head(dev);
14409 }
14410
14411 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14412 {
14413         struct drm_device *dev = fb->dev;
14414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14415
14416         drm_framebuffer_cleanup(fb);
14417         mutex_lock(&dev->struct_mutex);
14418         WARN_ON(!intel_fb->obj->framebuffer_references--);
14419         drm_gem_object_unreference(&intel_fb->obj->base);
14420         mutex_unlock(&dev->struct_mutex);
14421         kfree(intel_fb);
14422 }
14423
14424 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14425                                                 struct drm_file *file,
14426                                                 unsigned int *handle)
14427 {
14428         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14429         struct drm_i915_gem_object *obj = intel_fb->obj;
14430
14431         return drm_gem_handle_create(file, &obj->base, handle);
14432 }
14433
14434 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14435         .destroy = intel_user_framebuffer_destroy,
14436         .create_handle = intel_user_framebuffer_create_handle,
14437 };
14438
14439 static
14440 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14441                          uint32_t pixel_format)
14442 {
14443         u32 gen = INTEL_INFO(dev)->gen;
14444
14445         if (gen >= 9) {
14446                 /* "The stride in bytes must not exceed the of the size of 8K
14447                  *  pixels and 32K bytes."
14448                  */
14449                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14450         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14451                 return 32*1024;
14452         } else if (gen >= 4) {
14453                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14454                         return 16*1024;
14455                 else
14456                         return 32*1024;
14457         } else if (gen >= 3) {
14458                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14459                         return 8*1024;
14460                 else
14461                         return 16*1024;
14462         } else {
14463                 /* XXX DSPC is limited to 4k tiled */
14464                 return 8*1024;
14465         }
14466 }
14467
14468 static int intel_framebuffer_init(struct drm_device *dev,
14469                                   struct intel_framebuffer *intel_fb,
14470                                   struct drm_mode_fb_cmd2 *mode_cmd,
14471                                   struct drm_i915_gem_object *obj)
14472 {
14473         unsigned int aligned_height;
14474         int ret;
14475         u32 pitch_limit, stride_alignment;
14476
14477         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14478
14479         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14480                 /* Enforce that fb modifier and tiling mode match, but only for
14481                  * X-tiled. This is needed for FBC. */
14482                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14483                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14484                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14485                         return -EINVAL;
14486                 }
14487         } else {
14488                 if (obj->tiling_mode == I915_TILING_X)
14489                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14490                 else if (obj->tiling_mode == I915_TILING_Y) {
14491                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14492                         return -EINVAL;
14493                 }
14494         }
14495
14496         /* Passed in modifier sanity checking. */
14497         switch (mode_cmd->modifier[0]) {
14498         case I915_FORMAT_MOD_Y_TILED:
14499         case I915_FORMAT_MOD_Yf_TILED:
14500                 if (INTEL_INFO(dev)->gen < 9) {
14501                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14502                                   mode_cmd->modifier[0]);
14503                         return -EINVAL;
14504                 }
14505         case DRM_FORMAT_MOD_NONE:
14506         case I915_FORMAT_MOD_X_TILED:
14507                 break;
14508         default:
14509                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14510                           mode_cmd->modifier[0]);
14511                 return -EINVAL;
14512         }
14513
14514         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14515                                                      mode_cmd->pixel_format);
14516         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14517                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14518                           mode_cmd->pitches[0], stride_alignment);
14519                 return -EINVAL;
14520         }
14521
14522         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14523                                            mode_cmd->pixel_format);
14524         if (mode_cmd->pitches[0] > pitch_limit) {
14525                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14526                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14527                           "tiled" : "linear",
14528                           mode_cmd->pitches[0], pitch_limit);
14529                 return -EINVAL;
14530         }
14531
14532         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14533             mode_cmd->pitches[0] != obj->stride) {
14534                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14535                           mode_cmd->pitches[0], obj->stride);
14536                 return -EINVAL;
14537         }
14538
14539         /* Reject formats not supported by any plane early. */
14540         switch (mode_cmd->pixel_format) {
14541         case DRM_FORMAT_C8:
14542         case DRM_FORMAT_RGB565:
14543         case DRM_FORMAT_XRGB8888:
14544         case DRM_FORMAT_ARGB8888:
14545                 break;
14546         case DRM_FORMAT_XRGB1555:
14547                 if (INTEL_INFO(dev)->gen > 3) {
14548                         DRM_DEBUG("unsupported pixel format: %s\n",
14549                                   drm_get_format_name(mode_cmd->pixel_format));
14550                         return -EINVAL;
14551                 }
14552                 break;
14553         case DRM_FORMAT_ABGR8888:
14554                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14555                         DRM_DEBUG("unsupported pixel format: %s\n",
14556                                   drm_get_format_name(mode_cmd->pixel_format));
14557                         return -EINVAL;
14558                 }
14559                 break;
14560         case DRM_FORMAT_XBGR8888:
14561         case DRM_FORMAT_XRGB2101010:
14562         case DRM_FORMAT_XBGR2101010:
14563                 if (INTEL_INFO(dev)->gen < 4) {
14564                         DRM_DEBUG("unsupported pixel format: %s\n",
14565                                   drm_get_format_name(mode_cmd->pixel_format));
14566                         return -EINVAL;
14567                 }
14568                 break;
14569         case DRM_FORMAT_ABGR2101010:
14570                 if (!IS_VALLEYVIEW(dev)) {
14571                         DRM_DEBUG("unsupported pixel format: %s\n",
14572                                   drm_get_format_name(mode_cmd->pixel_format));
14573                         return -EINVAL;
14574                 }
14575                 break;
14576         case DRM_FORMAT_YUYV:
14577         case DRM_FORMAT_UYVY:
14578         case DRM_FORMAT_YVYU:
14579         case DRM_FORMAT_VYUY:
14580                 if (INTEL_INFO(dev)->gen < 5) {
14581                         DRM_DEBUG("unsupported pixel format: %s\n",
14582                                   drm_get_format_name(mode_cmd->pixel_format));
14583                         return -EINVAL;
14584                 }
14585                 break;
14586         default:
14587                 DRM_DEBUG("unsupported pixel format: %s\n",
14588                           drm_get_format_name(mode_cmd->pixel_format));
14589                 return -EINVAL;
14590         }
14591
14592         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14593         if (mode_cmd->offsets[0] != 0)
14594                 return -EINVAL;
14595
14596         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14597                                                mode_cmd->pixel_format,
14598                                                mode_cmd->modifier[0]);
14599         /* FIXME drm helper for size checks (especially planar formats)? */
14600         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14601                 return -EINVAL;
14602
14603         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14604         intel_fb->obj = obj;
14605         intel_fb->obj->framebuffer_references++;
14606
14607         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14608         if (ret) {
14609                 DRM_ERROR("framebuffer init failed %d\n", ret);
14610                 return ret;
14611         }
14612
14613         return 0;
14614 }
14615
14616 static struct drm_framebuffer *
14617 intel_user_framebuffer_create(struct drm_device *dev,
14618                               struct drm_file *filp,
14619                               struct drm_mode_fb_cmd2 *mode_cmd)
14620 {
14621         struct drm_i915_gem_object *obj;
14622
14623         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14624                                                 mode_cmd->handles[0]));
14625         if (&obj->base == NULL)
14626                 return ERR_PTR(-ENOENT);
14627
14628         return intel_framebuffer_create(dev, mode_cmd, obj);
14629 }
14630
14631 #ifndef CONFIG_DRM_I915_FBDEV
14632 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14633 {
14634 }
14635 #endif
14636
14637 static const struct drm_mode_config_funcs intel_mode_funcs = {
14638         .fb_create = intel_user_framebuffer_create,
14639         .output_poll_changed = intel_fbdev_output_poll_changed,
14640         .atomic_check = intel_atomic_check,
14641         .atomic_commit = intel_atomic_commit,
14642         .atomic_state_alloc = intel_atomic_state_alloc,
14643         .atomic_state_clear = intel_atomic_state_clear,
14644 };
14645
14646 /* Set up chip specific display functions */
14647 static void intel_init_display(struct drm_device *dev)
14648 {
14649         struct drm_i915_private *dev_priv = dev->dev_private;
14650
14651         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14652                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14653         else if (IS_CHERRYVIEW(dev))
14654                 dev_priv->display.find_dpll = chv_find_best_dpll;
14655         else if (IS_VALLEYVIEW(dev))
14656                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14657         else if (IS_PINEVIEW(dev))
14658                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14659         else
14660                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14661
14662         if (INTEL_INFO(dev)->gen >= 9) {
14663                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14664                 dev_priv->display.get_initial_plane_config =
14665                         skylake_get_initial_plane_config;
14666                 dev_priv->display.crtc_compute_clock =
14667                         haswell_crtc_compute_clock;
14668                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14669                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14670                 dev_priv->display.update_primary_plane =
14671                         skylake_update_primary_plane;
14672         } else if (HAS_DDI(dev)) {
14673                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14674                 dev_priv->display.get_initial_plane_config =
14675                         ironlake_get_initial_plane_config;
14676                 dev_priv->display.crtc_compute_clock =
14677                         haswell_crtc_compute_clock;
14678                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14679                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14680                 dev_priv->display.update_primary_plane =
14681                         ironlake_update_primary_plane;
14682         } else if (HAS_PCH_SPLIT(dev)) {
14683                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14684                 dev_priv->display.get_initial_plane_config =
14685                         ironlake_get_initial_plane_config;
14686                 dev_priv->display.crtc_compute_clock =
14687                         ironlake_crtc_compute_clock;
14688                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14689                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14690                 dev_priv->display.update_primary_plane =
14691                         ironlake_update_primary_plane;
14692         } else if (IS_VALLEYVIEW(dev)) {
14693                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14694                 dev_priv->display.get_initial_plane_config =
14695                         i9xx_get_initial_plane_config;
14696                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14697                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14698                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14699                 dev_priv->display.update_primary_plane =
14700                         i9xx_update_primary_plane;
14701         } else {
14702                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14703                 dev_priv->display.get_initial_plane_config =
14704                         i9xx_get_initial_plane_config;
14705                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14706                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14707                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14708                 dev_priv->display.update_primary_plane =
14709                         i9xx_update_primary_plane;
14710         }
14711
14712         /* Returns the core display clock speed */
14713         if (IS_SKYLAKE(dev))
14714                 dev_priv->display.get_display_clock_speed =
14715                         skylake_get_display_clock_speed;
14716         else if (IS_BROADWELL(dev))
14717                 dev_priv->display.get_display_clock_speed =
14718                         broadwell_get_display_clock_speed;
14719         else if (IS_HASWELL(dev))
14720                 dev_priv->display.get_display_clock_speed =
14721                         haswell_get_display_clock_speed;
14722         else if (IS_VALLEYVIEW(dev))
14723                 dev_priv->display.get_display_clock_speed =
14724                         valleyview_get_display_clock_speed;
14725         else if (IS_GEN5(dev))
14726                 dev_priv->display.get_display_clock_speed =
14727                         ilk_get_display_clock_speed;
14728         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14729                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14730                 dev_priv->display.get_display_clock_speed =
14731                         i945_get_display_clock_speed;
14732         else if (IS_GM45(dev))
14733                 dev_priv->display.get_display_clock_speed =
14734                         gm45_get_display_clock_speed;
14735         else if (IS_CRESTLINE(dev))
14736                 dev_priv->display.get_display_clock_speed =
14737                         i965gm_get_display_clock_speed;
14738         else if (IS_PINEVIEW(dev))
14739                 dev_priv->display.get_display_clock_speed =
14740                         pnv_get_display_clock_speed;
14741         else if (IS_G33(dev) || IS_G4X(dev))
14742                 dev_priv->display.get_display_clock_speed =
14743                         g33_get_display_clock_speed;
14744         else if (IS_I915G(dev))
14745                 dev_priv->display.get_display_clock_speed =
14746                         i915_get_display_clock_speed;
14747         else if (IS_I945GM(dev) || IS_845G(dev))
14748                 dev_priv->display.get_display_clock_speed =
14749                         i9xx_misc_get_display_clock_speed;
14750         else if (IS_PINEVIEW(dev))
14751                 dev_priv->display.get_display_clock_speed =
14752                         pnv_get_display_clock_speed;
14753         else if (IS_I915GM(dev))
14754                 dev_priv->display.get_display_clock_speed =
14755                         i915gm_get_display_clock_speed;
14756         else if (IS_I865G(dev))
14757                 dev_priv->display.get_display_clock_speed =
14758                         i865_get_display_clock_speed;
14759         else if (IS_I85X(dev))
14760                 dev_priv->display.get_display_clock_speed =
14761                         i85x_get_display_clock_speed;
14762         else { /* 830 */
14763                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14764                 dev_priv->display.get_display_clock_speed =
14765                         i830_get_display_clock_speed;
14766         }
14767
14768         if (IS_GEN5(dev)) {
14769                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14770         } else if (IS_GEN6(dev)) {
14771                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14772         } else if (IS_IVYBRIDGE(dev)) {
14773                 /* FIXME: detect B0+ stepping and use auto training */
14774                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14775         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14776                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14777                 if (IS_BROADWELL(dev))
14778                         dev_priv->display.modeset_global_resources =
14779                                 broadwell_modeset_global_resources;
14780         } else if (IS_VALLEYVIEW(dev)) {
14781                 dev_priv->display.modeset_global_resources =
14782                         valleyview_modeset_global_resources;
14783         } else if (IS_BROXTON(dev)) {
14784                 dev_priv->display.modeset_global_resources =
14785                         broxton_modeset_global_resources;
14786         }
14787
14788         switch (INTEL_INFO(dev)->gen) {
14789         case 2:
14790                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14791                 break;
14792
14793         case 3:
14794                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14795                 break;
14796
14797         case 4:
14798         case 5:
14799                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14800                 break;
14801
14802         case 6:
14803                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14804                 break;
14805         case 7:
14806         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14807                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14808                 break;
14809         case 9:
14810                 /* Drop through - unsupported since execlist only. */
14811         default:
14812                 /* Default just returns -ENODEV to indicate unsupported */
14813                 dev_priv->display.queue_flip = intel_default_queue_flip;
14814         }
14815
14816         intel_panel_init_backlight_funcs(dev);
14817
14818         mutex_init(&dev_priv->pps_mutex);
14819 }
14820
14821 /*
14822  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14823  * resume, or other times.  This quirk makes sure that's the case for
14824  * affected systems.
14825  */
14826 static void quirk_pipea_force(struct drm_device *dev)
14827 {
14828         struct drm_i915_private *dev_priv = dev->dev_private;
14829
14830         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14831         DRM_INFO("applying pipe a force quirk\n");
14832 }
14833
14834 static void quirk_pipeb_force(struct drm_device *dev)
14835 {
14836         struct drm_i915_private *dev_priv = dev->dev_private;
14837
14838         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14839         DRM_INFO("applying pipe b force quirk\n");
14840 }
14841
14842 /*
14843  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14844  */
14845 static void quirk_ssc_force_disable(struct drm_device *dev)
14846 {
14847         struct drm_i915_private *dev_priv = dev->dev_private;
14848         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14849         DRM_INFO("applying lvds SSC disable quirk\n");
14850 }
14851
14852 /*
14853  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14854  * brightness value
14855  */
14856 static void quirk_invert_brightness(struct drm_device *dev)
14857 {
14858         struct drm_i915_private *dev_priv = dev->dev_private;
14859         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14860         DRM_INFO("applying inverted panel brightness quirk\n");
14861 }
14862
14863 /* Some VBT's incorrectly indicate no backlight is present */
14864 static void quirk_backlight_present(struct drm_device *dev)
14865 {
14866         struct drm_i915_private *dev_priv = dev->dev_private;
14867         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14868         DRM_INFO("applying backlight present quirk\n");
14869 }
14870
14871 struct intel_quirk {
14872         int device;
14873         int subsystem_vendor;
14874         int subsystem_device;
14875         void (*hook)(struct drm_device *dev);
14876 };
14877
14878 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14879 struct intel_dmi_quirk {
14880         void (*hook)(struct drm_device *dev);
14881         const struct dmi_system_id (*dmi_id_list)[];
14882 };
14883
14884 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14885 {
14886         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14887         return 1;
14888 }
14889
14890 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14891         {
14892                 .dmi_id_list = &(const struct dmi_system_id[]) {
14893                         {
14894                                 .callback = intel_dmi_reverse_brightness,
14895                                 .ident = "NCR Corporation",
14896                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14897                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14898                                 },
14899                         },
14900                         { }  /* terminating entry */
14901                 },
14902                 .hook = quirk_invert_brightness,
14903         },
14904 };
14905
14906 static struct intel_quirk intel_quirks[] = {
14907         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14908         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14909
14910         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14911         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14912
14913         /* 830 needs to leave pipe A & dpll A up */
14914         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14915
14916         /* 830 needs to leave pipe B & dpll B up */
14917         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14918
14919         /* Lenovo U160 cannot use SSC on LVDS */
14920         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14921
14922         /* Sony Vaio Y cannot use SSC on LVDS */
14923         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14924
14925         /* Acer Aspire 5734Z must invert backlight brightness */
14926         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14927
14928         /* Acer/eMachines G725 */
14929         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14930
14931         /* Acer/eMachines e725 */
14932         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14933
14934         /* Acer/Packard Bell NCL20 */
14935         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14936
14937         /* Acer Aspire 4736Z */
14938         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14939
14940         /* Acer Aspire 5336 */
14941         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14942
14943         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14944         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14945
14946         /* Acer C720 Chromebook (Core i3 4005U) */
14947         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14948
14949         /* Apple Macbook 2,1 (Core 2 T7400) */
14950         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14951
14952         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14953         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14954
14955         /* HP Chromebook 14 (Celeron 2955U) */
14956         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14957
14958         /* Dell Chromebook 11 */
14959         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14960 };
14961
14962 static void intel_init_quirks(struct drm_device *dev)
14963 {
14964         struct pci_dev *d = dev->pdev;
14965         int i;
14966
14967         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14968                 struct intel_quirk *q = &intel_quirks[i];
14969
14970                 if (d->device == q->device &&
14971                     (d->subsystem_vendor == q->subsystem_vendor ||
14972                      q->subsystem_vendor == PCI_ANY_ID) &&
14973                     (d->subsystem_device == q->subsystem_device ||
14974                      q->subsystem_device == PCI_ANY_ID))
14975                         q->hook(dev);
14976         }
14977         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14978                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14979                         intel_dmi_quirks[i].hook(dev);
14980         }
14981 }
14982
14983 /* Disable the VGA plane that we never use */
14984 static void i915_disable_vga(struct drm_device *dev)
14985 {
14986         struct drm_i915_private *dev_priv = dev->dev_private;
14987         u8 sr1;
14988         u32 vga_reg = i915_vgacntrl_reg(dev);
14989
14990         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14991         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14992         outb(SR01, VGA_SR_INDEX);
14993         sr1 = inb(VGA_SR_DATA);
14994         outb(sr1 | 1<<5, VGA_SR_DATA);
14995         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14996         udelay(300);
14997
14998         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14999         POSTING_READ(vga_reg);
15000 }
15001
15002 void intel_modeset_init_hw(struct drm_device *dev)
15003 {
15004         intel_update_cdclk(dev);
15005         intel_prepare_ddi(dev);
15006         intel_init_clock_gating(dev);
15007         intel_enable_gt_powersave(dev);
15008 }
15009
15010 void intel_modeset_init(struct drm_device *dev)
15011 {
15012         struct drm_i915_private *dev_priv = dev->dev_private;
15013         int sprite, ret;
15014         enum pipe pipe;
15015         struct intel_crtc *crtc;
15016
15017         drm_mode_config_init(dev);
15018
15019         dev->mode_config.min_width = 0;
15020         dev->mode_config.min_height = 0;
15021
15022         dev->mode_config.preferred_depth = 24;
15023         dev->mode_config.prefer_shadow = 1;
15024
15025         dev->mode_config.allow_fb_modifiers = true;
15026
15027         dev->mode_config.funcs = &intel_mode_funcs;
15028
15029         intel_init_quirks(dev);
15030
15031         intel_init_pm(dev);
15032
15033         if (INTEL_INFO(dev)->num_pipes == 0)
15034                 return;
15035
15036         intel_init_display(dev);
15037         intel_init_audio(dev);
15038
15039         if (IS_GEN2(dev)) {
15040                 dev->mode_config.max_width = 2048;
15041                 dev->mode_config.max_height = 2048;
15042         } else if (IS_GEN3(dev)) {
15043                 dev->mode_config.max_width = 4096;
15044                 dev->mode_config.max_height = 4096;
15045         } else {
15046                 dev->mode_config.max_width = 8192;
15047                 dev->mode_config.max_height = 8192;
15048         }
15049
15050         if (IS_845G(dev) || IS_I865G(dev)) {
15051                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15052                 dev->mode_config.cursor_height = 1023;
15053         } else if (IS_GEN2(dev)) {
15054                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15055                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15056         } else {
15057                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15058                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15059         }
15060
15061         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15062
15063         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15064                       INTEL_INFO(dev)->num_pipes,
15065                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15066
15067         for_each_pipe(dev_priv, pipe) {
15068                 intel_crtc_init(dev, pipe);
15069                 for_each_sprite(dev_priv, pipe, sprite) {
15070                         ret = intel_plane_init(dev, pipe, sprite);
15071                         if (ret)
15072                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15073                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15074                 }
15075         }
15076
15077         intel_init_dpio(dev);
15078
15079         intel_shared_dpll_init(dev);
15080
15081         /* Just disable it once at startup */
15082         i915_disable_vga(dev);
15083         intel_setup_outputs(dev);
15084
15085         /* Just in case the BIOS is doing something questionable. */
15086         intel_fbc_disable(dev);
15087
15088         drm_modeset_lock_all(dev);
15089         intel_modeset_setup_hw_state(dev, false);
15090         drm_modeset_unlock_all(dev);
15091
15092         for_each_intel_crtc(dev, crtc) {
15093                 if (!crtc->active)
15094                         continue;
15095
15096                 /*
15097                  * Note that reserving the BIOS fb up front prevents us
15098                  * from stuffing other stolen allocations like the ring
15099                  * on top.  This prevents some ugliness at boot time, and
15100                  * can even allow for smooth boot transitions if the BIOS
15101                  * fb is large enough for the active pipe configuration.
15102                  */
15103                 if (dev_priv->display.get_initial_plane_config) {
15104                         dev_priv->display.get_initial_plane_config(crtc,
15105                                                            &crtc->plane_config);
15106                         /*
15107                          * If the fb is shared between multiple heads, we'll
15108                          * just get the first one.
15109                          */
15110                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15111                 }
15112         }
15113 }
15114
15115 static void intel_enable_pipe_a(struct drm_device *dev)
15116 {
15117         struct intel_connector *connector;
15118         struct drm_connector *crt = NULL;
15119         struct intel_load_detect_pipe load_detect_temp;
15120         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15121
15122         /* We can't just switch on the pipe A, we need to set things up with a
15123          * proper mode and output configuration. As a gross hack, enable pipe A
15124          * by enabling the load detect pipe once. */
15125         for_each_intel_connector(dev, connector) {
15126                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15127                         crt = &connector->base;
15128                         break;
15129                 }
15130         }
15131
15132         if (!crt)
15133                 return;
15134
15135         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15136                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15137 }
15138
15139 static bool
15140 intel_check_plane_mapping(struct intel_crtc *crtc)
15141 {
15142         struct drm_device *dev = crtc->base.dev;
15143         struct drm_i915_private *dev_priv = dev->dev_private;
15144         u32 reg, val;
15145
15146         if (INTEL_INFO(dev)->num_pipes == 1)
15147                 return true;
15148
15149         reg = DSPCNTR(!crtc->plane);
15150         val = I915_READ(reg);
15151
15152         if ((val & DISPLAY_PLANE_ENABLE) &&
15153             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15154                 return false;
15155
15156         return true;
15157 }
15158
15159 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15160 {
15161         struct drm_device *dev = crtc->base.dev;
15162         struct drm_i915_private *dev_priv = dev->dev_private;
15163         struct intel_encoder *encoder;
15164         u32 reg;
15165         bool enable;
15166
15167         /* Clear any frame start delays used for debugging left by the BIOS */
15168         reg = PIPECONF(crtc->config->cpu_transcoder);
15169         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15170
15171         /* restore vblank interrupts to correct state */
15172         drm_crtc_vblank_reset(&crtc->base);
15173         if (crtc->active) {
15174                 update_scanline_offset(crtc);
15175                 drm_crtc_vblank_on(&crtc->base);
15176         }
15177
15178         /* We need to sanitize the plane -> pipe mapping first because this will
15179          * disable the crtc (and hence change the state) if it is wrong. Note
15180          * that gen4+ has a fixed plane -> pipe mapping.  */
15181         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15182                 bool plane;
15183
15184                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15185                               crtc->base.base.id);
15186
15187                 /* Pipe has the wrong plane attached and the plane is active.
15188                  * Temporarily change the plane mapping and disable everything
15189                  * ...  */
15190                 plane = crtc->plane;
15191                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15192                 crtc->plane = !plane;
15193                 intel_crtc_disable_noatomic(&crtc->base);
15194                 crtc->plane = plane;
15195         }
15196
15197         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15198             crtc->pipe == PIPE_A && !crtc->active) {
15199                 /* BIOS forgot to enable pipe A, this mostly happens after
15200                  * resume. Force-enable the pipe to fix this, the update_dpms
15201                  * call below we restore the pipe to the right state, but leave
15202                  * the required bits on. */
15203                 intel_enable_pipe_a(dev);
15204         }
15205
15206         /* Adjust the state of the output pipe according to whether we
15207          * have active connectors/encoders. */
15208         enable = false;
15209         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15210                 enable |= encoder->connectors_active;
15211
15212         if (!enable)
15213                 intel_crtc_disable_noatomic(&crtc->base);
15214
15215         if (crtc->active != crtc->base.state->active) {
15216
15217                 /* This can happen either due to bugs in the get_hw_state
15218                  * functions or because of calls to intel_crtc_disable_noatomic,
15219                  * or because the pipe is force-enabled due to the
15220                  * pipe A quirk. */
15221                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15222                               crtc->base.base.id,
15223                               crtc->base.state->enable ? "enabled" : "disabled",
15224                               crtc->active ? "enabled" : "disabled");
15225
15226                 crtc->base.state->enable = crtc->active;
15227                 crtc->base.state->active = crtc->active;
15228                 crtc->base.enabled = crtc->active;
15229
15230                 /* Because we only establish the connector -> encoder ->
15231                  * crtc links if something is active, this means the
15232                  * crtc is now deactivated. Break the links. connector
15233                  * -> encoder links are only establish when things are
15234                  *  actually up, hence no need to break them. */
15235                 WARN_ON(crtc->active);
15236
15237                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15238                         WARN_ON(encoder->connectors_active);
15239                         encoder->base.crtc = NULL;
15240                 }
15241         }
15242
15243         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15244                 /*
15245                  * We start out with underrun reporting disabled to avoid races.
15246                  * For correct bookkeeping mark this on active crtcs.
15247                  *
15248                  * Also on gmch platforms we dont have any hardware bits to
15249                  * disable the underrun reporting. Which means we need to start
15250                  * out with underrun reporting disabled also on inactive pipes,
15251                  * since otherwise we'll complain about the garbage we read when
15252                  * e.g. coming up after runtime pm.
15253                  *
15254                  * No protection against concurrent access is required - at
15255                  * worst a fifo underrun happens which also sets this to false.
15256                  */
15257                 crtc->cpu_fifo_underrun_disabled = true;
15258                 crtc->pch_fifo_underrun_disabled = true;
15259         }
15260 }
15261
15262 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15263 {
15264         struct intel_connector *connector;
15265         struct drm_device *dev = encoder->base.dev;
15266
15267         /* We need to check both for a crtc link (meaning that the
15268          * encoder is active and trying to read from a pipe) and the
15269          * pipe itself being active. */
15270         bool has_active_crtc = encoder->base.crtc &&
15271                 to_intel_crtc(encoder->base.crtc)->active;
15272
15273         if (encoder->connectors_active && !has_active_crtc) {
15274                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15275                               encoder->base.base.id,
15276                               encoder->base.name);
15277
15278                 /* Connector is active, but has no active pipe. This is
15279                  * fallout from our resume register restoring. Disable
15280                  * the encoder manually again. */
15281                 if (encoder->base.crtc) {
15282                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15283                                       encoder->base.base.id,
15284                                       encoder->base.name);
15285                         encoder->disable(encoder);
15286                         if (encoder->post_disable)
15287                                 encoder->post_disable(encoder);
15288                 }
15289                 encoder->base.crtc = NULL;
15290                 encoder->connectors_active = false;
15291
15292                 /* Inconsistent output/port/pipe state happens presumably due to
15293                  * a bug in one of the get_hw_state functions. Or someplace else
15294                  * in our code, like the register restore mess on resume. Clamp
15295                  * things to off as a safer default. */
15296                 for_each_intel_connector(dev, connector) {
15297                         if (connector->encoder != encoder)
15298                                 continue;
15299                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15300                         connector->base.encoder = NULL;
15301                 }
15302         }
15303         /* Enabled encoders without active connectors will be fixed in
15304          * the crtc fixup. */
15305 }
15306
15307 void i915_redisable_vga_power_on(struct drm_device *dev)
15308 {
15309         struct drm_i915_private *dev_priv = dev->dev_private;
15310         u32 vga_reg = i915_vgacntrl_reg(dev);
15311
15312         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15313                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15314                 i915_disable_vga(dev);
15315         }
15316 }
15317
15318 void i915_redisable_vga(struct drm_device *dev)
15319 {
15320         struct drm_i915_private *dev_priv = dev->dev_private;
15321
15322         /* This function can be called both from intel_modeset_setup_hw_state or
15323          * at a very early point in our resume sequence, where the power well
15324          * structures are not yet restored. Since this function is at a very
15325          * paranoid "someone might have enabled VGA while we were not looking"
15326          * level, just check if the power well is enabled instead of trying to
15327          * follow the "don't touch the power well if we don't need it" policy
15328          * the rest of the driver uses. */
15329         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15330                 return;
15331
15332         i915_redisable_vga_power_on(dev);
15333 }
15334
15335 static bool primary_get_hw_state(struct intel_crtc *crtc)
15336 {
15337         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15338
15339         if (!crtc->active)
15340                 return false;
15341
15342         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15343 }
15344
15345 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15346 {
15347         struct drm_i915_private *dev_priv = dev->dev_private;
15348         enum pipe pipe;
15349         struct intel_crtc *crtc;
15350         struct intel_encoder *encoder;
15351         struct intel_connector *connector;
15352         int i;
15353
15354         for_each_intel_crtc(dev, crtc) {
15355                 struct drm_plane *primary = crtc->base.primary;
15356                 struct intel_plane_state *plane_state;
15357
15358                 memset(crtc->config, 0, sizeof(*crtc->config));
15359                 crtc->config->base.crtc = &crtc->base;
15360
15361                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15362
15363                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15364                                                                  crtc->config);
15365
15366                 crtc->base.state->enable = crtc->active;
15367                 crtc->base.state->active = crtc->active;
15368                 crtc->base.enabled = crtc->active;
15369                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15370
15371                 plane_state = to_intel_plane_state(primary->state);
15372                 plane_state->visible = primary_get_hw_state(crtc);
15373
15374                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15375                               crtc->base.base.id,
15376                               crtc->active ? "enabled" : "disabled");
15377         }
15378
15379         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15380                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15381
15382                 pll->on = pll->get_hw_state(dev_priv, pll,
15383                                             &pll->config.hw_state);
15384                 pll->active = 0;
15385                 pll->config.crtc_mask = 0;
15386                 for_each_intel_crtc(dev, crtc) {
15387                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15388                                 pll->active++;
15389                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15390                         }
15391                 }
15392
15393                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15394                               pll->name, pll->config.crtc_mask, pll->on);
15395
15396                 if (pll->config.crtc_mask)
15397                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15398         }
15399
15400         for_each_intel_encoder(dev, encoder) {
15401                 pipe = 0;
15402
15403                 if (encoder->get_hw_state(encoder, &pipe)) {
15404                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15405                         encoder->base.crtc = &crtc->base;
15406                         encoder->get_config(encoder, crtc->config);
15407                 } else {
15408                         encoder->base.crtc = NULL;
15409                 }
15410
15411                 encoder->connectors_active = false;
15412                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15413                               encoder->base.base.id,
15414                               encoder->base.name,
15415                               encoder->base.crtc ? "enabled" : "disabled",
15416                               pipe_name(pipe));
15417         }
15418
15419         for_each_intel_connector(dev, connector) {
15420                 if (connector->get_hw_state(connector)) {
15421                         connector->base.dpms = DRM_MODE_DPMS_ON;
15422                         connector->encoder->connectors_active = true;
15423                         connector->base.encoder = &connector->encoder->base;
15424                 } else {
15425                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15426                         connector->base.encoder = NULL;
15427                 }
15428                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15429                               connector->base.base.id,
15430                               connector->base.name,
15431                               connector->base.encoder ? "enabled" : "disabled");
15432         }
15433 }
15434
15435 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15436  * and i915 state tracking structures. */
15437 void intel_modeset_setup_hw_state(struct drm_device *dev,
15438                                   bool force_restore)
15439 {
15440         struct drm_i915_private *dev_priv = dev->dev_private;
15441         enum pipe pipe;
15442         struct intel_crtc *crtc;
15443         struct intel_encoder *encoder;
15444         int i;
15445
15446         intel_modeset_readout_hw_state(dev);
15447
15448         /*
15449          * Now that we have the config, copy it to each CRTC struct
15450          * Note that this could go away if we move to using crtc_config
15451          * checking everywhere.
15452          */
15453         for_each_intel_crtc(dev, crtc) {
15454                 if (crtc->active && i915.fastboot) {
15455                         intel_mode_from_pipe_config(&crtc->base.mode,
15456                                                     crtc->config);
15457                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15458                                       crtc->base.base.id);
15459                         drm_mode_debug_printmodeline(&crtc->base.mode);
15460                 }
15461         }
15462
15463         /* HW state is read out, now we need to sanitize this mess. */
15464         for_each_intel_encoder(dev, encoder) {
15465                 intel_sanitize_encoder(encoder);
15466         }
15467
15468         for_each_pipe(dev_priv, pipe) {
15469                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15470                 intel_sanitize_crtc(crtc);
15471                 intel_dump_pipe_config(crtc, crtc->config,
15472                                        "[setup_hw_state]");
15473         }
15474
15475         intel_modeset_update_connector_atomic_state(dev);
15476
15477         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15478                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15479
15480                 if (!pll->on || pll->active)
15481                         continue;
15482
15483                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15484
15485                 pll->disable(dev_priv, pll);
15486                 pll->on = false;
15487         }
15488
15489         if (IS_GEN9(dev))
15490                 skl_wm_get_hw_state(dev);
15491         else if (HAS_PCH_SPLIT(dev))
15492                 ilk_wm_get_hw_state(dev);
15493
15494         if (force_restore) {
15495                 i915_redisable_vga(dev);
15496
15497                 /*
15498                  * We need to use raw interfaces for restoring state to avoid
15499                  * checking (bogus) intermediate states.
15500                  */
15501                 for_each_pipe(dev_priv, pipe) {
15502                         struct drm_crtc *crtc =
15503                                 dev_priv->pipe_to_crtc_mapping[pipe];
15504
15505                         intel_crtc_restore_mode(crtc);
15506                 }
15507         } else {
15508                 intel_modeset_update_staged_output_state(dev);
15509         }
15510
15511         intel_modeset_check_state(dev);
15512 }
15513
15514 void intel_modeset_gem_init(struct drm_device *dev)
15515 {
15516         struct drm_i915_private *dev_priv = dev->dev_private;
15517         struct drm_crtc *c;
15518         struct drm_i915_gem_object *obj;
15519         int ret;
15520
15521         mutex_lock(&dev->struct_mutex);
15522         intel_init_gt_powersave(dev);
15523         mutex_unlock(&dev->struct_mutex);
15524
15525         /*
15526          * There may be no VBT; and if the BIOS enabled SSC we can
15527          * just keep using it to avoid unnecessary flicker.  Whereas if the
15528          * BIOS isn't using it, don't assume it will work even if the VBT
15529          * indicates as much.
15530          */
15531         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15532                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15533                                                 DREF_SSC1_ENABLE);
15534
15535         intel_modeset_init_hw(dev);
15536
15537         intel_setup_overlay(dev);
15538
15539         /*
15540          * Make sure any fbs we allocated at startup are properly
15541          * pinned & fenced.  When we do the allocation it's too early
15542          * for this.
15543          */
15544         for_each_crtc(dev, c) {
15545                 obj = intel_fb_obj(c->primary->fb);
15546                 if (obj == NULL)
15547                         continue;
15548
15549                 mutex_lock(&dev->struct_mutex);
15550                 ret = intel_pin_and_fence_fb_obj(c->primary,
15551                                                  c->primary->fb,
15552                                                  c->primary->state,
15553                                                  NULL);
15554                 mutex_unlock(&dev->struct_mutex);
15555                 if (ret) {
15556                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15557                                   to_intel_crtc(c)->pipe);
15558                         drm_framebuffer_unreference(c->primary->fb);
15559                         c->primary->fb = NULL;
15560                         c->primary->crtc = c->primary->state->crtc = NULL;
15561                         update_state_fb(c->primary);
15562                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15563                 }
15564         }
15565
15566         intel_backlight_register(dev);
15567 }
15568
15569 void intel_connector_unregister(struct intel_connector *intel_connector)
15570 {
15571         struct drm_connector *connector = &intel_connector->base;
15572
15573         intel_panel_destroy_backlight(connector);
15574         drm_connector_unregister(connector);
15575 }
15576
15577 void intel_modeset_cleanup(struct drm_device *dev)
15578 {
15579         struct drm_i915_private *dev_priv = dev->dev_private;
15580         struct drm_connector *connector;
15581
15582         intel_disable_gt_powersave(dev);
15583
15584         intel_backlight_unregister(dev);
15585
15586         /*
15587          * Interrupts and polling as the first thing to avoid creating havoc.
15588          * Too much stuff here (turning of connectors, ...) would
15589          * experience fancy races otherwise.
15590          */
15591         intel_irq_uninstall(dev_priv);
15592
15593         /*
15594          * Due to the hpd irq storm handling the hotplug work can re-arm the
15595          * poll handlers. Hence disable polling after hpd handling is shut down.
15596          */
15597         drm_kms_helper_poll_fini(dev);
15598
15599         mutex_lock(&dev->struct_mutex);
15600
15601         intel_unregister_dsm_handler();
15602
15603         intel_fbc_disable(dev);
15604
15605         mutex_unlock(&dev->struct_mutex);
15606
15607         /* flush any delayed tasks or pending work */
15608         flush_scheduled_work();
15609
15610         /* destroy the backlight and sysfs files before encoders/connectors */
15611         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15612                 struct intel_connector *intel_connector;
15613
15614                 intel_connector = to_intel_connector(connector);
15615                 intel_connector->unregister(intel_connector);
15616         }
15617
15618         drm_mode_config_cleanup(dev);
15619
15620         intel_cleanup_overlay(dev);
15621
15622         mutex_lock(&dev->struct_mutex);
15623         intel_cleanup_gt_powersave(dev);
15624         mutex_unlock(&dev->struct_mutex);
15625 }
15626
15627 /*
15628  * Return which encoder is currently attached for connector.
15629  */
15630 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15631 {
15632         return &intel_attached_encoder(connector)->base;
15633 }
15634
15635 void intel_connector_attach_encoder(struct intel_connector *connector,
15636                                     struct intel_encoder *encoder)
15637 {
15638         connector->encoder = encoder;
15639         drm_mode_connector_attach_encoder(&connector->base,
15640                                           &encoder->base);
15641 }
15642
15643 /*
15644  * set vga decode state - true == enable VGA decode
15645  */
15646 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15647 {
15648         struct drm_i915_private *dev_priv = dev->dev_private;
15649         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15650         u16 gmch_ctrl;
15651
15652         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15653                 DRM_ERROR("failed to read control word\n");
15654                 return -EIO;
15655         }
15656
15657         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15658                 return 0;
15659
15660         if (state)
15661                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15662         else
15663                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15664
15665         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15666                 DRM_ERROR("failed to write control word\n");
15667                 return -EIO;
15668         }
15669
15670         return 0;
15671 }
15672
15673 struct intel_display_error_state {
15674
15675         u32 power_well_driver;
15676
15677         int num_transcoders;
15678
15679         struct intel_cursor_error_state {
15680                 u32 control;
15681                 u32 position;
15682                 u32 base;
15683                 u32 size;
15684         } cursor[I915_MAX_PIPES];
15685
15686         struct intel_pipe_error_state {
15687                 bool power_domain_on;
15688                 u32 source;
15689                 u32 stat;
15690         } pipe[I915_MAX_PIPES];
15691
15692         struct intel_plane_error_state {
15693                 u32 control;
15694                 u32 stride;
15695                 u32 size;
15696                 u32 pos;
15697                 u32 addr;
15698                 u32 surface;
15699                 u32 tile_offset;
15700         } plane[I915_MAX_PIPES];
15701
15702         struct intel_transcoder_error_state {
15703                 bool power_domain_on;
15704                 enum transcoder cpu_transcoder;
15705
15706                 u32 conf;
15707
15708                 u32 htotal;
15709                 u32 hblank;
15710                 u32 hsync;
15711                 u32 vtotal;
15712                 u32 vblank;
15713                 u32 vsync;
15714         } transcoder[4];
15715 };
15716
15717 struct intel_display_error_state *
15718 intel_display_capture_error_state(struct drm_device *dev)
15719 {
15720         struct drm_i915_private *dev_priv = dev->dev_private;
15721         struct intel_display_error_state *error;
15722         int transcoders[] = {
15723                 TRANSCODER_A,
15724                 TRANSCODER_B,
15725                 TRANSCODER_C,
15726                 TRANSCODER_EDP,
15727         };
15728         int i;
15729
15730         if (INTEL_INFO(dev)->num_pipes == 0)
15731                 return NULL;
15732
15733         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15734         if (error == NULL)
15735                 return NULL;
15736
15737         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15738                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15739
15740         for_each_pipe(dev_priv, i) {
15741                 error->pipe[i].power_domain_on =
15742                         __intel_display_power_is_enabled(dev_priv,
15743                                                          POWER_DOMAIN_PIPE(i));
15744                 if (!error->pipe[i].power_domain_on)
15745                         continue;
15746
15747                 error->cursor[i].control = I915_READ(CURCNTR(i));
15748                 error->cursor[i].position = I915_READ(CURPOS(i));
15749                 error->cursor[i].base = I915_READ(CURBASE(i));
15750
15751                 error->plane[i].control = I915_READ(DSPCNTR(i));
15752                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15753                 if (INTEL_INFO(dev)->gen <= 3) {
15754                         error->plane[i].size = I915_READ(DSPSIZE(i));
15755                         error->plane[i].pos = I915_READ(DSPPOS(i));
15756                 }
15757                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15758                         error->plane[i].addr = I915_READ(DSPADDR(i));
15759                 if (INTEL_INFO(dev)->gen >= 4) {
15760                         error->plane[i].surface = I915_READ(DSPSURF(i));
15761                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15762                 }
15763
15764                 error->pipe[i].source = I915_READ(PIPESRC(i));
15765
15766                 if (HAS_GMCH_DISPLAY(dev))
15767                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15768         }
15769
15770         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15771         if (HAS_DDI(dev_priv->dev))
15772                 error->num_transcoders++; /* Account for eDP. */
15773
15774         for (i = 0; i < error->num_transcoders; i++) {
15775                 enum transcoder cpu_transcoder = transcoders[i];
15776
15777                 error->transcoder[i].power_domain_on =
15778                         __intel_display_power_is_enabled(dev_priv,
15779                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15780                 if (!error->transcoder[i].power_domain_on)
15781                         continue;
15782
15783                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15784
15785                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15786                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15787                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15788                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15789                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15790                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15791                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15792         }
15793
15794         return error;
15795 }
15796
15797 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15798
15799 void
15800 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15801                                 struct drm_device *dev,
15802                                 struct intel_display_error_state *error)
15803 {
15804         struct drm_i915_private *dev_priv = dev->dev_private;
15805         int i;
15806
15807         if (!error)
15808                 return;
15809
15810         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15811         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15812                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15813                            error->power_well_driver);
15814         for_each_pipe(dev_priv, i) {
15815                 err_printf(m, "Pipe [%d]:\n", i);
15816                 err_printf(m, "  Power: %s\n",
15817                            error->pipe[i].power_domain_on ? "on" : "off");
15818                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15819                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15820
15821                 err_printf(m, "Plane [%d]:\n", i);
15822                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15823                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15824                 if (INTEL_INFO(dev)->gen <= 3) {
15825                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15826                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15827                 }
15828                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15829                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15830                 if (INTEL_INFO(dev)->gen >= 4) {
15831                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15832                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15833                 }
15834
15835                 err_printf(m, "Cursor [%d]:\n", i);
15836                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15837                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15838                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15839         }
15840
15841         for (i = 0; i < error->num_transcoders; i++) {
15842                 err_printf(m, "CPU transcoder: %c\n",
15843                            transcoder_name(error->transcoder[i].cpu_transcoder));
15844                 err_printf(m, "  Power: %s\n",
15845                            error->transcoder[i].power_domain_on ? "on" : "off");
15846                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15847                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15848                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15849                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15850                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15851                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15852                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15853         }
15854 }
15855
15856 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15857 {
15858         struct intel_crtc *crtc;
15859
15860         for_each_intel_crtc(dev, crtc) {
15861                 struct intel_unpin_work *work;
15862
15863                 spin_lock_irq(&dev->event_lock);
15864
15865                 work = crtc->unpin_work;
15866
15867                 if (work && work->event &&
15868                     work->event->base.file_priv == file) {
15869                         kfree(work->event);
15870                         work->event = NULL;
15871                 }
15872
15873                 spin_unlock_irq(&dev->event_lock);
15874         }
15875 }