drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 4000000, .max = 5994000},
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 25000, .max = 270000 },
 397         .vco = { .min = 4000000, .max = 6000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 22, .max = 450 },
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         WARN(1, "pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380              && (val & DP_PIPEB_SELECT),
1381              "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385                                      enum pipe pipe, int reg)
1386 {
1387         u32 val = I915_READ(reg);
1388         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390              reg, pipe_name(pipe));
1391
1392         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393              && (val & SDVO_PIPE_B_SELECT),
1394              "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398                                       enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407         reg = PCH_ADPA;
1408         val = I915_READ(reg);
1409         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410              "PCH VGA enabled on transcoder %c, should be disabled\n",
1411              pipe_name(pipe));
1412
1413         reg = PCH_LVDS;
1414         val = I915_READ(reg);
1415         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425  * intel_enable_pll - enable a PLL
1426  * @dev_priv: i915 private structure
1427  * @pipe: pipe PLL to enable
1428  *
1429  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1430  * make sure the PLL reg is writable first though, since the panel write
1431  * protect mechanism may be enabled.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  *
1435  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436  */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439         int reg;
1440         u32 val;
1441
1442         /* No really, not for ILK+ */
1443         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445         /* PLL is protected by panel, make sure we can write it */
1446         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447                 assert_panel_unlocked(dev_priv, pipe);
1448
1449         reg = DPLL(pipe);
1450         val = I915_READ(reg);
1451         val |= DPLL_VCO_ENABLE;
1452
1453         /* We do this three times for luck */
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         udelay(150); /* wait for warmup */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466  * intel_disable_pll - disable a PLL
1467  * @dev_priv: i915 private structure
1468  * @pipe: pipe PLL to disable
1469  *
1470  * Disable the PLL for @pipe, making sure the pipe is off first.
1471  *
1472  * Note!  This is for pre-ILK only.
1473  */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476         int reg;
1477         u32 val;
1478
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         reg = DPLL(pipe);
1487         val = I915_READ(reg);
1488         val &= ~DPLL_VCO_ENABLE;
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497         unsigned long flags;
1498
1499         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501                                 100)) {
1502                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503                 goto out_unlock;
1504         }
1505
1506         I915_WRITE(SBI_ADDR,
1507                         (reg << 16));
1508         I915_WRITE(SBI_DATA,
1509                         value);
1510         I915_WRITE(SBI_CTL_STAT,
1511                         SBI_BUSY |
1512                         SBI_CTL_OP_CRWR);
1513
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517                 goto out_unlock;
1518         }
1519
1520 out_unlock:
1521         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527         unsigned long flags;
1528         u32 value = 0;
1529
1530         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532                                 100)) {
1533                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534                 goto out_unlock;
1535         }
1536
1537         I915_WRITE(SBI_ADDR,
1538                         (reg << 16));
1539         I915_WRITE(SBI_CTL_STAT,
1540                         SBI_BUSY |
1541                         SBI_CTL_OP_CRRD);
1542
1543         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544                                 100)) {
1545                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546                 goto out_unlock;
1547         }
1548
1549         value = I915_READ(SBI_DATA);
1550
1551 out_unlock:
1552         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553         return value;
1554 }
1555
1556 /**
1557  * intel_enable_pch_pll - enable PCH PLL
1558  * @dev_priv: i915 private structure
1559  * @pipe: pipe PLL to enable
1560  *
1561  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562  * drives the transcoder clock.
1563  */
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567         struct intel_pch_pll *pll;
1568         int reg;
1569         u32 val;
1570
1571         /* PCH PLLs only available on ILK, SNB and IVB */
1572         BUG_ON(dev_priv->info->gen < 5);
1573         pll = intel_crtc->pch_pll;
1574         if (pll == NULL)
1575                 return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         /* PCH refclock must be enabled first */
1585         assert_pch_refclk_enabled(dev_priv);
1586
1587         if (pll->active++ && pll->on) {
1588                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1589                 return;
1590         }
1591
1592         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594         reg = pll->pll_reg;
1595         val = I915_READ(reg);
1596         val |= DPLL_VCO_ENABLE;
1597         I915_WRITE(reg, val);
1598         POSTING_READ(reg);
1599         udelay(200);
1600
1601         pll->on = true;
1602 }
1603
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608         int reg;
1609         u32 val;
1610
1611         /* PCH only available on ILK+ */
1612         BUG_ON(dev_priv->info->gen < 5);
1613         if (pll == NULL)
1614                return;
1615
1616         if (WARN_ON(pll->refcount == 0))
1617                 return;
1618
1619         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620                       pll->pll_reg, pll->active, pll->on,
1621                       intel_crtc->base.base.id);
1622
1623         if (WARN_ON(pll->active == 0)) {
1624                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1625                 return;
1626         }
1627
1628         if (--pll->active) {
1629                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1630                 return;
1631         }
1632
1633         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635         /* Make sure transcoder isn't still depending on us */
1636         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637
1638         reg = pll->pll_reg;
1639         val = I915_READ(reg);
1640         val &= ~DPLL_VCO_ENABLE;
1641         I915_WRITE(reg, val);
1642         POSTING_READ(reg);
1643         udelay(200);
1644
1645         pll->on = false;
1646 }
1647
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649                                     enum pipe pipe)
1650 {
1651         int reg;
1652         u32 val, pipeconf_val;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654
1655         /* PCH only available on ILK+ */
1656         BUG_ON(dev_priv->info->gen < 5);
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_pch_pll_enabled(dev_priv,
1660                                to_intel_crtc(crtc)->pch_pll,
1661                                to_intel_crtc(crtc));
1662
1663         /* FDI must be feeding us bits for PCH ports */
1664         assert_fdi_tx_enabled(dev_priv, pipe);
1665         assert_fdi_rx_enabled(dev_priv, pipe);
1666
1667         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669                 return;
1670         }
1671         reg = TRANSCONF(pipe);
1672         val = I915_READ(reg);
1673         pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675         if (HAS_PCH_IBX(dev_priv->dev)) {
1676                 /*
1677                  * make the BPC in transcoder be consistent with
1678                  * that in pipeconf reg.
1679                  */
1680                 val &= ~PIPE_BPC_MASK;
1681                 val |= pipeconf_val & PIPE_BPC_MASK;
1682         }
1683
1684         val &= ~TRANS_INTERLACE_MASK;
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686                 if (HAS_PCH_IBX(dev_priv->dev) &&
1687                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688                         val |= TRANS_LEGACY_INTERLACED_ILK;
1689                 else
1690                         val |= TRANS_INTERLACED;
1691         else
1692                 val |= TRANS_PROGRESSIVE;
1693
1694         I915_WRITE(reg, val | TRANS_ENABLE);
1695         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700                                      enum pipe pipe)
1701 {
1702         int reg;
1703         u32 val;
1704
1705         /* FDI relies on the transcoder */
1706         assert_fdi_tx_disabled(dev_priv, pipe);
1707         assert_fdi_rx_disabled(dev_priv, pipe);
1708
1709         /* Ports must be off as well */
1710         assert_pch_ports_disabled(dev_priv, pipe);
1711
1712         reg = TRANSCONF(pipe);
1713         val = I915_READ(reg);
1714         val &= ~TRANS_ENABLE;
1715         I915_WRITE(reg, val);
1716         /* wait for PCH transcoder off, transcoder state */
1717         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720
1721 /**
1722  * intel_enable_pipe - enable a pipe, asserting requirements
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe to enable
1725  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726  *
1727  * Enable @pipe, making sure that various hardware specific requirements
1728  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729  *
1730  * @pipe should be %PIPE_A or %PIPE_B.
1731  *
1732  * Will wait until the pipe is actually running (i.e. first vblank) before
1733  * returning.
1734  */
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736                               bool pch_port)
1737 {
1738         int reg;
1739         u32 val;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 assert_pll_enabled(dev_priv, pipe);
1748         else {
1749                 if (pch_port) {
1750                         /* if driving the PCH, we need FDI enabled */
1751                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753                 }
1754                 /* FIXME: assert CPU port conditions for SNB+ */
1755         }
1756
1757         reg = PIPECONF(pipe);
1758         val = I915_READ(reg);
1759         if (val & PIPECONF_ENABLE)
1760                 return;
1761
1762         I915_WRITE(reg, val | PIPECONF_ENABLE);
1763         intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765
1766 /**
1767  * intel_disable_pipe - disable a pipe, asserting requirements
1768  * @dev_priv: i915 private structure
1769  * @pipe: pipe to disable
1770  *
1771  * Disable @pipe, making sure that various hardware specific requirements
1772  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773  *
1774  * @pipe should be %PIPE_A or %PIPE_B.
1775  *
1776  * Will wait until the pipe has shut down before returning.
1777  */
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779                                enum pipe pipe)
1780 {
1781         int reg;
1782         u32 val;
1783
1784         /*
1785          * Make sure planes won't keep trying to pump pixels to us,
1786          * or we might hang the display.
1787          */
1788         assert_planes_disabled(dev_priv, pipe);
1789
1790         /* Don't disable pipe A or pipe A PLLs if needed */
1791         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792                 return;
1793
1794         reg = PIPECONF(pipe);
1795         val = I915_READ(reg);
1796         if ((val & PIPECONF_ENABLE) == 0)
1797                 return;
1798
1799         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802
1803 /*
1804  * Plane regs are double buffered, going from enabled->disabled needs a
1805  * trigger in order to latch.  The display address reg provides this.
1806  */
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808                                       enum plane plane)
1809 {
1810         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813
1814 /**
1815  * intel_enable_plane - enable a display plane on a given pipe
1816  * @dev_priv: i915 private structure
1817  * @plane: plane to enable
1818  * @pipe: pipe being fed
1819  *
1820  * Enable @plane on @pipe, making sure that @pipe is running first.
1821  */
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823                                enum plane plane, enum pipe pipe)
1824 {
1825         int reg;
1826         u32 val;
1827
1828         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829         assert_pipe_enabled(dev_priv, pipe);
1830
1831         reg = DSPCNTR(plane);
1832         val = I915_READ(reg);
1833         if (val & DISPLAY_PLANE_ENABLE)
1834                 return;
1835
1836         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837         intel_flush_display_plane(dev_priv, plane);
1838         intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840
1841 /**
1842  * intel_disable_plane - disable a display plane
1843  * @dev_priv: i915 private structure
1844  * @plane: plane to disable
1845  * @pipe: pipe consuming the data
1846  *
1847  * Disable @plane; should be an independent operation.
1848  */
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850                                 enum plane plane, enum pipe pipe)
1851 {
1852         int reg;
1853         u32 val;
1854
1855         reg = DSPCNTR(plane);
1856         val = I915_READ(reg);
1857         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858                 return;
1859
1860         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861         intel_flush_display_plane(dev_priv, plane);
1862         intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864
1865 int
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867                            struct drm_i915_gem_object *obj,
1868                            struct intel_ring_buffer *pipelined)
1869 {
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         u32 alignment;
1872         int ret;
1873
1874         switch (obj->tiling_mode) {
1875         case I915_TILING_NONE:
1876                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877                         alignment = 128 * 1024;
1878                 else if (INTEL_INFO(dev)->gen >= 4)
1879                         alignment = 4 * 1024;
1880                 else
1881                         alignment = 64 * 1024;
1882                 break;
1883         case I915_TILING_X:
1884                 /* pin() will align the object as required by fence */
1885                 alignment = 0;
1886                 break;
1887         case I915_TILING_Y:
1888                 /* FIXME: Is this true? */
1889                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890                 return -EINVAL;
1891         default:
1892                 BUG();
1893         }
1894
1895         dev_priv->mm.interruptible = false;
1896         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897         if (ret)
1898                 goto err_interruptible;
1899
1900         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901          * fence, whereas 965+ only requires a fence if using
1902          * framebuffer compression.  For simplicity, we always install
1903          * a fence as the cost is not that onerous.
1904          */
1905         ret = i915_gem_object_get_fence(obj);
1906         if (ret)
1907                 goto err_unpin;
1908
1909         i915_gem_object_pin_fence(obj);
1910
1911         dev_priv->mm.interruptible = true;
1912         return 0;
1913
1914 err_unpin:
1915         i915_gem_object_unpin(obj);
1916 err_interruptible:
1917         dev_priv->mm.interruptible = true;
1918         return ret;
1919 }
1920
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922 {
1923         i915_gem_object_unpin_fence(obj);
1924         i915_gem_object_unpin(obj);
1925 }
1926
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928  * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930                                                         unsigned int bpp,
1931                                                         unsigned int pitch)
1932 {
1933         int tile_rows, tiles;
1934
1935         tile_rows = *y / 8;
1936         *y %= 8;
1937         tiles = *x / (512/bpp);
1938         *x %= 512/bpp;
1939
1940         return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long linear_offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000
2001         if (INTEL_INFO(dev)->gen >= 4) {
2002                 intel_crtc->dspaddr_offset =
2003                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004                                                            fb->bits_per_pixel / 8,
2005                                                            fb->pitches[0]);
2006                 linear_offset -= intel_crtc->dspaddr_offset;
2007         } else {
2008                 intel_crtc->dspaddr_offset = linear_offset;
2009         }
2010
2011         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014         if (INTEL_INFO(dev)->gen >= 4) {
2015                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2017                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2019         } else
2020                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021         POSTING_READ(reg);
2022
2023         return 0;
2024 }
2025
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027                                  struct drm_framebuffer *fb, int x, int y)
2028 {
2029         struct drm_device *dev = crtc->dev;
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032         struct intel_framebuffer *intel_fb;
2033         struct drm_i915_gem_object *obj;
2034         int plane = intel_crtc->plane;
2035         unsigned long linear_offset;
2036         u32 dspcntr;
2037         u32 reg;
2038
2039         switch (plane) {
2040         case 0:
2041         case 1:
2042         case 2:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth != 16)
2062                         return -EINVAL;
2063
2064                 dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 if (fb->depth == 24)
2069                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070                 else if (fb->depth == 30)
2071                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072                 else
2073                         return -EINVAL;
2074                 break;
2075         default:
2076                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077                 return -EINVAL;
2078         }
2079
2080         if (obj->tiling_mode != I915_TILING_NONE)
2081                 dspcntr |= DISPPLANE_TILED;
2082         else
2083                 dspcntr &= ~DISPPLANE_TILED;
2084
2085         /* must disable */
2086         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088         I915_WRITE(reg, dspcntr);
2089
2090         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091         intel_crtc->dspaddr_offset =
2092                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093                                                    fb->bits_per_pixel / 8,
2094                                                    fb->pitches[0]);
2095         linear_offset -= intel_crtc->dspaddr_offset;
2096
2097         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100         I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2102         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103         I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         POSTING_READ(reg);
2105
2106         return 0;
2107 }
2108
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112                            int x, int y, enum mode_set_atomic state)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117         if (dev_priv->display.disable_fbc)
2118                 dev_priv->display.disable_fbc(dev);
2119         intel_increase_pllclock(crtc);
2120
2121         return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129         bool was_interruptible = dev_priv->mm.interruptible;
2130         int ret;
2131
2132         wait_event(dev_priv->pending_flip_queue,
2133                    atomic_read(&dev_priv->mm.wedged) ||
2134                    atomic_read(&obj->pending_flip) == 0);
2135
2136         /* Big Hammer, we also need to ensure that any pending
2137          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138          * current scanout is retired before unpinning the old
2139          * framebuffer.
2140          *
2141          * This should only fail upon a hung GPU, in which case we
2142          * can safely continue.
2143          */
2144         dev_priv->mm.interruptible = false;
2145         ret = i915_gem_object_finish_gpu(obj);
2146         dev_priv->mm.interruptible = was_interruptible;
2147
2148         return ret;
2149 }
2150
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153                     struct drm_framebuffer *fb)
2154 {
2155         struct drm_device *dev = crtc->dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct drm_i915_master_private *master_priv;
2158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159         struct drm_framebuffer *old_fb;
2160         int ret;
2161
2162         /* no fb bound */
2163         if (!fb) {
2164                 DRM_ERROR("No FB bound\n");
2165                 return 0;
2166         }
2167
2168         if(intel_crtc->plane > dev_priv->num_pipe) {
2169                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170                                 intel_crtc->plane,
2171                                 dev_priv->num_pipe);
2172                 return -EINVAL;
2173         }
2174
2175         mutex_lock(&dev->struct_mutex);
2176         ret = intel_pin_and_fence_fb_obj(dev,
2177                                          to_intel_framebuffer(fb)->obj,
2178                                          NULL);
2179         if (ret != 0) {
2180                 mutex_unlock(&dev->struct_mutex);
2181                 DRM_ERROR("pin & fence failed\n");
2182                 return ret;
2183         }
2184
2185         if (crtc->fb)
2186                 intel_finish_fb(crtc->fb);
2187
2188         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189         if (ret) {
2190                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191                 mutex_unlock(&dev->struct_mutex);
2192                 DRM_ERROR("failed to update base address\n");
2193                 return ret;
2194         }
2195
2196         old_fb = crtc->fb;
2197         crtc->fb = fb;
2198         crtc->x = x;
2199         crtc->y = y;
2200
2201         if (old_fb) {
2202                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204         }
2205
2206         intel_update_fbc(dev);
2207         mutex_unlock(&dev->struct_mutex);
2208
2209         if (!dev->primary->master)
2210                 return 0;
2211
2212         master_priv = dev->primary->master->driver_priv;
2213         if (!master_priv->sarea_priv)
2214                 return 0;
2215
2216         if (intel_crtc->pipe) {
2217                 master_priv->sarea_priv->pipeB_x = x;
2218                 master_priv->sarea_priv->pipeB_y = y;
2219         } else {
2220                 master_priv->sarea_priv->pipeA_x = x;
2221                 master_priv->sarea_priv->pipeA_y = y;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         u32 dpa_ctl;
2232
2233         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234         dpa_ctl = I915_READ(DP_A);
2235         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237         if (clock < 200000) {
2238                 u32 temp;
2239                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240                 /* workaround for 160Mhz:
2241                    1) program 0x4600c bits 15:0 = 0x8124
2242                    2) program 0x46010 bit 0 = 1
2243                    3) program 0x46034 bit 24 = 1
2244                    4) program 0x64000 bit 14 = 1
2245                    */
2246                 temp = I915_READ(0x4600c);
2247                 temp &= 0xffff0000;
2248                 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250                 temp = I915_READ(0x46010);
2251                 I915_WRITE(0x46010, temp | 1);
2252
2253                 temp = I915_READ(0x46034);
2254                 I915_WRITE(0x46034, temp | (1 << 24));
2255         } else {
2256                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257         }
2258         I915_WRITE(DP_A, dpa_ctl);
2259
2260         POSTING_READ(DP_A);
2261         udelay(500);
2262 }
2263
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269         int pipe = intel_crtc->pipe;
2270         u32 reg, temp;
2271
2272         /* enable normal train */
2273         reg = FDI_TX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         if (IS_IVYBRIDGE(dev)) {
2276                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278         } else {
2279                 temp &= ~FDI_LINK_TRAIN_NONE;
2280                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281         }
2282         I915_WRITE(reg, temp);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         if (HAS_PCH_CPT(dev)) {
2287                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289         } else {
2290                 temp &= ~FDI_LINK_TRAIN_NONE;
2291                 temp |= FDI_LINK_TRAIN_NONE;
2292         }
2293         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295         /* wait one idle pattern time */
2296         POSTING_READ(reg);
2297         udelay(1000);
2298
2299         /* IVB wants error correction enabled */
2300         if (IS_IVYBRIDGE(dev))
2301                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302                            FDI_FE_ERRC_ENABLE);
2303 }
2304
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310         flags |= FDI_PHASE_SYNC_OVR(pipe);
2311         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312         flags |= FDI_PHASE_SYNC_EN(pipe);
2313         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314         POSTING_READ(SOUTH_CHICKEN1);
2315 }
2316
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325         u32 reg, temp, tries;
2326
2327         /* FDI needs bits from pipe & plane first */
2328         assert_pipe_enabled(dev_priv, pipe);
2329         assert_plane_enabled(dev_priv, plane);
2330
2331         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332            for train result */
2333         reg = FDI_RX_IMR(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~FDI_RX_SYMBOL_LOCK;
2336         temp &= ~FDI_RX_BIT_LOCK;
2337         I915_WRITE(reg, temp);
2338         I915_READ(reg);
2339         udelay(150);
2340
2341         /* enable CPU FDI TX and PCH FDI RX */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~(7 << 19);
2345         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346         temp &= ~FDI_LINK_TRAIN_NONE;
2347         temp |= FDI_LINK_TRAIN_PATTERN_1;
2348         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         temp &= ~FDI_LINK_TRAIN_NONE;
2353         temp |= FDI_LINK_TRAIN_PATTERN_1;
2354         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356         POSTING_READ(reg);
2357         udelay(150);
2358
2359         /* Ironlake workaround, enable clock pointer after FDI enable*/
2360         if (HAS_PCH_IBX(dev)) {
2361                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                            FDI_RX_PHASE_SYNC_POINTER_EN);
2364         }
2365
2366         reg = FDI_RX_IIR(pipe);
2367         for (tries = 0; tries < 5; tries++) {
2368                 temp = I915_READ(reg);
2369                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371                 if ((temp & FDI_RX_BIT_LOCK)) {
2372                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2373                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374                         break;
2375                 }
2376         }
2377         if (tries == 5)
2378                 DRM_ERROR("FDI train 1 fail!\n");
2379
2380         /* Train 2 */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_LINK_TRAIN_NONE;
2384         temp |= FDI_LINK_TRAIN_PATTERN_2;
2385         I915_WRITE(reg, temp);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_2;
2391         I915_WRITE(reg, temp);
2392
2393         POSTING_READ(reg);
2394         udelay(150);
2395
2396         reg = FDI_RX_IIR(pipe);
2397         for (tries = 0; tries < 5; tries++) {
2398                 temp = I915_READ(reg);
2399                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401                 if (temp & FDI_RX_SYMBOL_LOCK) {
2402                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2404                         break;
2405                 }
2406         }
2407         if (tries == 5)
2408                 DRM_ERROR("FDI train 2 fail!\n");
2409
2410         DRM_DEBUG_KMS("FDI train done\n");
2411
2412 }
2413
2414 static const int snb_b_fdi_train_param[] = {
2415         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419 };
2420
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424         struct drm_device *dev = crtc->dev;
2425         struct drm_i915_private *dev_priv = dev->dev_private;
2426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427         int pipe = intel_crtc->pipe;
2428         u32 reg, temp, i, retry;
2429
2430         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431            for train result */
2432         reg = FDI_RX_IMR(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_RX_SYMBOL_LOCK;
2435         temp &= ~FDI_RX_BIT_LOCK;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         /* enable CPU FDI TX and PCH FDI RX */
2442         reg = FDI_TX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~(7 << 19);
2445         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446         temp &= ~FDI_LINK_TRAIN_NONE;
2447         temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449         /* SNB-B */
2450         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452
2453         reg = FDI_RX_CTL(pipe);
2454         temp = I915_READ(reg);
2455         if (HAS_PCH_CPT(dev)) {
2456                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458         } else {
2459                 temp &= ~FDI_LINK_TRAIN_NONE;
2460                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461         }
2462         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464         POSTING_READ(reg);
2465         udelay(150);
2466
2467         if (HAS_PCH_CPT(dev))
2468                 cpt_phase_pointer_enable(dev, pipe);
2469
2470         for (i = 0; i < 4; i++) {
2471                 reg = FDI_TX_CTL(pipe);
2472                 temp = I915_READ(reg);
2473                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474                 temp |= snb_b_fdi_train_param[i];
2475                 I915_WRITE(reg, temp);
2476
2477                 POSTING_READ(reg);
2478                 udelay(500);
2479
2480                 for (retry = 0; retry < 5; retry++) {
2481                         reg = FDI_RX_IIR(pipe);
2482                         temp = I915_READ(reg);
2483                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484                         if (temp & FDI_RX_BIT_LOCK) {
2485                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487                                 break;
2488                         }
2489                         udelay(50);
2490                 }
2491                 if (retry < 5)
2492                         break;
2493         }
2494         if (i == 4)
2495                 DRM_ERROR("FDI train 1 fail!\n");
2496
2497         /* Train 2 */
2498         reg = FDI_TX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_2;
2502         if (IS_GEN6(dev)) {
2503                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504                 /* SNB-B */
2505                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506         }
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         if (HAS_PCH_CPT(dev)) {
2512                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514         } else {
2515                 temp &= ~FDI_LINK_TRAIN_NONE;
2516                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517         }
2518         I915_WRITE(reg, temp);
2519
2520         POSTING_READ(reg);
2521         udelay(150);
2522
2523         for (i = 0; i < 4; i++) {
2524                 reg = FDI_TX_CTL(pipe);
2525                 temp = I915_READ(reg);
2526                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527                 temp |= snb_b_fdi_train_param[i];
2528                 I915_WRITE(reg, temp);
2529
2530                 POSTING_READ(reg);
2531                 udelay(500);
2532
2533                 for (retry = 0; retry < 5; retry++) {
2534                         reg = FDI_RX_IIR(pipe);
2535                         temp = I915_READ(reg);
2536                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537                         if (temp & FDI_RX_SYMBOL_LOCK) {
2538                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                                 break;
2541                         }
2542                         udelay(50);
2543                 }
2544                 if (retry < 5)
2545                         break;
2546         }
2547         if (i == 4)
2548                 DRM_ERROR("FDI train 2 fail!\n");
2549
2550         DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         struct drm_i915_private *dev_priv = dev->dev_private;
2558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559         int pipe = intel_crtc->pipe;
2560         u32 reg, temp, i;
2561
2562         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563            for train result */
2564         reg = FDI_RX_IMR(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~FDI_RX_SYMBOL_LOCK;
2567         temp &= ~FDI_RX_BIT_LOCK;
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         /* enable CPU FDI TX and PCH FDI RX */
2574         reg = FDI_TX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~(7 << 19);
2577         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         temp |= FDI_COMPOSITE_SYNC;
2583         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~FDI_LINK_TRAIN_AUTO;
2588         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         temp |= FDI_COMPOSITE_SYNC;
2591         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593         POSTING_READ(reg);
2594         udelay(150);
2595
2596         if (HAS_PCH_CPT(dev))
2597                 cpt_phase_pointer_enable(dev, pipe);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 reg = FDI_RX_IIR(pipe);
2610                 temp = I915_READ(reg);
2611                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613                 if (temp & FDI_RX_BIT_LOCK ||
2614                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2617                         break;
2618                 }
2619         }
2620         if (i == 4)
2621                 DRM_ERROR("FDI train 1 fail!\n");
2622
2623         /* Train 2 */
2624         reg = FDI_TX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630         I915_WRITE(reg, temp);
2631
2632         reg = FDI_RX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669         struct drm_device *dev = intel_crtc->base.dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         int pipe = intel_crtc->pipe;
2672         u32 reg, temp;
2673
2674         /* Write the TU size bits so error detection works */
2675         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677
2678         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679         reg = FDI_RX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~((0x7 << 19) | (0x7 << 16));
2682         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686         POSTING_READ(reg);
2687         udelay(200);
2688
2689         /* Switch from Rawclk to PCDclk */
2690         temp = I915_READ(reg);
2691         I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693         POSTING_READ(reg);
2694         udelay(200);
2695
2696         /* On Haswell, the PLL configuration for ports and pipes is handled
2697          * separately, as part of DDI setup */
2698         if (!IS_HASWELL(dev)) {
2699                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700                 reg = FDI_TX_CTL(pipe);
2701                 temp = I915_READ(reg);
2702                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704
2705                         POSTING_READ(reg);
2706                         udelay(100);
2707                 }
2708         }
2709 }
2710
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* Switch from PCDclk to Rawclk */
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723         /* Disable CPU FDI TX PLL */
2724         reg = FDI_TX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728         POSTING_READ(reg);
2729         udelay(100);
2730
2731         reg = FDI_RX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735         /* Wait for the clocks to turn off. */
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749         POSTING_READ(SOUTH_CHICKEN1);
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759         /* disable CPU FDI tx and PCH FDI rx */
2760         reg = FDI_TX_CTL(pipe);
2761         temp = I915_READ(reg);
2762         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763         POSTING_READ(reg);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(0x7 << 16);
2768         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(100);
2773
2774         /* Ironlake workaround, disable clock pointer after downing FDI */
2775         if (HAS_PCH_IBX(dev)) {
2776                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778                            I915_READ(FDI_RX_CHICKEN(pipe) &
2779                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780         } else if (HAS_PCH_CPT(dev)) {
2781                 cpt_phase_pointer_disable(dev, pipe);
2782         }
2783
2784         /* still set train pattern 1 */
2785         reg = FDI_TX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         temp &= ~FDI_LINK_TRAIN_NONE;
2788         temp |= FDI_LINK_TRAIN_PATTERN_1;
2789         I915_WRITE(reg, temp);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         if (HAS_PCH_CPT(dev)) {
2794                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796         } else {
2797                 temp &= ~FDI_LINK_TRAIN_NONE;
2798                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         }
2800         /* BPC in FDI rx is consistent with that in PIPECONF */
2801         temp &= ~(0x07 << 16);
2802         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803         I915_WRITE(reg, temp);
2804
2805         POSTING_READ(reg);
2806         udelay(100);
2807 }
2808
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812
2813         if (crtc->fb == NULL)
2814                 return;
2815
2816         mutex_lock(&dev->struct_mutex);
2817         intel_finish_fb(crtc->fb);
2818         mutex_unlock(&dev->struct_mutex);
2819 }
2820
2821 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822 {
2823         struct drm_device *dev = crtc->dev;
2824         struct intel_encoder *intel_encoder;
2825
2826         /*
2827          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828          * must be driven by its own crtc; no sharing is possible.
2829          */
2830         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2831
2832                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833                  * CPU handles all others */
2834                 if (IS_HASWELL(dev)) {
2835                         /* It is still unclear how this will work on PPT, so throw up a warning */
2836                         WARN_ON(!HAS_PCH_LPT(dev));
2837
2838                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2839                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840                                 return true;
2841                         } else {
2842                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2843                                               intel_encoder->type);
2844                                 return false;
2845                         }
2846                 }
2847
2848                 switch (intel_encoder->type) {
2849                 case INTEL_OUTPUT_EDP:
2850                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2851                                 return false;
2852                         continue;
2853                 }
2854         }
2855
2856         return true;
2857 }
2858
2859 /* Program iCLKIP clock to the desired frequency */
2860 static void lpt_program_iclkip(struct drm_crtc *crtc)
2861 {
2862         struct drm_device *dev = crtc->dev;
2863         struct drm_i915_private *dev_priv = dev->dev_private;
2864         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865         u32 temp;
2866
2867         /* It is necessary to ungate the pixclk gate prior to programming
2868          * the divisors, and gate it back when it is done.
2869          */
2870         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872         /* Disable SSCCTL */
2873         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875                                         SBI_SSCCTL_DISABLE);
2876
2877         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878         if (crtc->mode.clock == 20000) {
2879                 auxdiv = 1;
2880                 divsel = 0x41;
2881                 phaseinc = 0x20;
2882         } else {
2883                 /* The iCLK virtual clock root frequency is in MHz,
2884                  * but the crtc->mode.clock in in KHz. To get the divisors,
2885                  * it is necessary to divide one by another, so we
2886                  * convert the virtual clock precision to KHz here for higher
2887                  * precision.
2888                  */
2889                 u32 iclk_virtual_root_freq = 172800 * 1000;
2890                 u32 iclk_pi_range = 64;
2891                 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894                 msb_divisor_value = desired_divisor / iclk_pi_range;
2895                 pi_value = desired_divisor % iclk_pi_range;
2896
2897                 auxdiv = 0;
2898                 divsel = msb_divisor_value - 2;
2899                 phaseinc = pi_value;
2900         }
2901
2902         /* This should not happen with any sane values */
2903         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909                         crtc->mode.clock,
2910                         auxdiv,
2911                         divsel,
2912                         phasedir,
2913                         phaseinc);
2914
2915         /* Program SSCDIVINTPHASE6 */
2916         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924         intel_sbi_write(dev_priv,
2925                         SBI_SSCDIVINTPHASE6,
2926                         temp);
2927
2928         /* Program SSCAUXDIV */
2929         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932         intel_sbi_write(dev_priv,
2933                         SBI_SSCAUXDIV6,
2934                         temp);
2935
2936
2937         /* Enable modulator and associated divider */
2938         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939         temp &= ~SBI_SSCCTL_DISABLE;
2940         intel_sbi_write(dev_priv,
2941                         SBI_SSCCTL6,
2942                         temp);
2943
2944         /* Wait for initialization time */
2945         udelay(24);
2946
2947         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948 }
2949
2950 /*
2951  * Enable PCH resources required for PCH ports:
2952  *   - PCH PLLs
2953  *   - FDI training & RX/TX
2954  *   - update transcoder timings
2955  *   - DP transcoding bits
2956  *   - transcoder
2957  */
2958 static void ironlake_pch_enable(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp;
2965
2966         assert_transcoder_disabled(dev_priv, pipe);
2967
2968         /* For PCH output, training FDI link */
2969         dev_priv->display.fdi_link_train(crtc);
2970
2971         intel_enable_pch_pll(intel_crtc);
2972
2973         if (HAS_PCH_LPT(dev)) {
2974                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975                 lpt_program_iclkip(crtc);
2976         } else if (HAS_PCH_CPT(dev)) {
2977                 u32 sel;
2978
2979                 temp = I915_READ(PCH_DPLL_SEL);
2980                 switch (pipe) {
2981                 default:
2982                 case 0:
2983                         temp |= TRANSA_DPLL_ENABLE;
2984                         sel = TRANSA_DPLLB_SEL;
2985                         break;
2986                 case 1:
2987                         temp |= TRANSB_DPLL_ENABLE;
2988                         sel = TRANSB_DPLLB_SEL;
2989                         break;
2990                 case 2:
2991                         temp |= TRANSC_DPLL_ENABLE;
2992                         sel = TRANSC_DPLLB_SEL;
2993                         break;
2994                 }
2995                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996                         temp |= sel;
2997                 else
2998                         temp &= ~sel;
2999                 I915_WRITE(PCH_DPLL_SEL, temp);
3000         }
3001
3002         /* set transcoder timing, panel must allow it */
3003         assert_panel_unlocked(dev_priv, pipe);
3004         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3007
3008         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3011         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3012
3013         if (!IS_HASWELL(dev))
3014                 intel_fdi_normal_train(crtc);
3015
3016         /* For PCH DP, enable TRANS_DP_CTL */
3017         if (HAS_PCH_CPT(dev) &&
3018             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3020                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3021                 reg = TRANS_DP_CTL(pipe);
3022                 temp = I915_READ(reg);
3023                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3024                           TRANS_DP_SYNC_MASK |
3025                           TRANS_DP_BPC_MASK);
3026                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027                          TRANS_DP_ENH_FRAMING);
3028                 temp |= bpc << 9; /* same format but at 11:9 */
3029
3030                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3031                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3032                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3033                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3034
3035                 switch (intel_trans_dp_port_sel(crtc)) {
3036                 case PCH_DP_B:
3037                         temp |= TRANS_DP_PORT_SEL_B;
3038                         break;
3039                 case PCH_DP_C:
3040                         temp |= TRANS_DP_PORT_SEL_C;
3041                         break;
3042                 case PCH_DP_D:
3043                         temp |= TRANS_DP_PORT_SEL_D;
3044                         break;
3045                 default:
3046                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3047                         temp |= TRANS_DP_PORT_SEL_B;
3048                         break;
3049                 }
3050
3051                 I915_WRITE(reg, temp);
3052         }
3053
3054         intel_enable_transcoder(dev_priv, pipe);
3055 }
3056
3057 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058 {
3059         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061         if (pll == NULL)
3062                 return;
3063
3064         if (pll->refcount == 0) {
3065                 WARN(1, "bad PCH PLL refcount\n");
3066                 return;
3067         }
3068
3069         --pll->refcount;
3070         intel_crtc->pch_pll = NULL;
3071 }
3072
3073 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074 {
3075         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076         struct intel_pch_pll *pll;
3077         int i;
3078
3079         pll = intel_crtc->pch_pll;
3080         if (pll) {
3081                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082                               intel_crtc->base.base.id, pll->pll_reg);
3083                 goto prepare;
3084         }
3085
3086         if (HAS_PCH_IBX(dev_priv->dev)) {
3087                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088                 i = intel_crtc->pipe;
3089                 pll = &dev_priv->pch_plls[i];
3090
3091                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092                               intel_crtc->base.base.id, pll->pll_reg);
3093
3094                 goto found;
3095         }
3096
3097         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098                 pll = &dev_priv->pch_plls[i];
3099
3100                 /* Only want to check enabled timings first */
3101                 if (pll->refcount == 0)
3102                         continue;
3103
3104                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105                     fp == I915_READ(pll->fp0_reg)) {
3106                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107                                       intel_crtc->base.base.id,
3108                                       pll->pll_reg, pll->refcount, pll->active);
3109
3110                         goto found;
3111                 }
3112         }
3113
3114         /* Ok no matching timings, maybe there's a free one? */
3115         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116                 pll = &dev_priv->pch_plls[i];
3117                 if (pll->refcount == 0) {
3118                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119                                       intel_crtc->base.base.id, pll->pll_reg);
3120                         goto found;
3121                 }
3122         }
3123
3124         return NULL;
3125
3126 found:
3127         intel_crtc->pch_pll = pll;
3128         pll->refcount++;
3129         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130 prepare: /* separate function? */
3131         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3132
3133         /* Wait for the clocks to stabilize before rewriting the regs */
3134         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3135         POSTING_READ(pll->pll_reg);
3136         udelay(150);
3137
3138         I915_WRITE(pll->fp0_reg, fp);
3139         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3140         pll->on = false;
3141         return pll;
3142 }
3143
3144 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148         u32 temp;
3149
3150         temp = I915_READ(dslreg);
3151         udelay(500);
3152         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153                 /* Without this, mode sets may fail silently on FDI */
3154                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155                 udelay(250);
3156                 I915_WRITE(tc2reg, 0);
3157                 if (wait_for(I915_READ(dslreg) != temp, 5))
3158                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159         }
3160 }
3161
3162 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163 {
3164         struct drm_device *dev = crtc->dev;
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167         struct intel_encoder *encoder;
3168         int pipe = intel_crtc->pipe;
3169         int plane = intel_crtc->plane;
3170         u32 temp;
3171         bool is_pch_port;
3172
3173         WARN_ON(!crtc->enabled);
3174
3175         if (intel_crtc->active)
3176                 return;
3177
3178         intel_crtc->active = true;
3179         intel_update_watermarks(dev);
3180
3181         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182                 temp = I915_READ(PCH_LVDS);
3183                 if ((temp & LVDS_PORT_EN) == 0)
3184                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185         }
3186
3187         is_pch_port = intel_crtc_driving_pch(crtc);
3188
3189         if (is_pch_port) {
3190                 ironlake_fdi_pll_enable(intel_crtc);
3191         } else {
3192                 assert_fdi_tx_disabled(dev_priv, pipe);
3193                 assert_fdi_rx_disabled(dev_priv, pipe);
3194         }
3195
3196         for_each_encoder_on_crtc(dev, crtc, encoder)
3197                 if (encoder->pre_enable)
3198                         encoder->pre_enable(encoder);
3199
3200         /* Enable panel fitting for LVDS */
3201         if (dev_priv->pch_pf_size &&
3202             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3203                 /* Force use of hard-coded filter coefficients
3204                  * as some pre-programmed values are broken,
3205                  * e.g. x201.
3206                  */
3207                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3208                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3209                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3210         }
3211
3212         /*
3213          * On ILK+ LUT must be loaded before the pipe is running but with
3214          * clocks enabled
3215          */
3216         intel_crtc_load_lut(crtc);
3217
3218         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3219         intel_enable_plane(dev_priv, plane, pipe);
3220
3221         if (is_pch_port)
3222                 ironlake_pch_enable(crtc);
3223
3224         mutex_lock(&dev->struct_mutex);
3225         intel_update_fbc(dev);
3226         mutex_unlock(&dev->struct_mutex);
3227
3228         intel_crtc_update_cursor(crtc, true);
3229
3230         for_each_encoder_on_crtc(dev, crtc, encoder)
3231                 encoder->enable(encoder);
3232
3233         if (HAS_PCH_CPT(dev))
3234                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3235 }
3236
3237 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         struct intel_encoder *encoder;
3243         int pipe = intel_crtc->pipe;
3244         int plane = intel_crtc->plane;
3245         u32 reg, temp;
3246
3247
3248         if (!intel_crtc->active)
3249                 return;
3250
3251         for_each_encoder_on_crtc(dev, crtc, encoder)
3252                 encoder->disable(encoder);
3253
3254         intel_crtc_wait_for_pending_flips(crtc);
3255         drm_vblank_off(dev, pipe);
3256         intel_crtc_update_cursor(crtc, false);
3257
3258         intel_disable_plane(dev_priv, plane, pipe);
3259
3260         if (dev_priv->cfb_plane == plane)
3261                 intel_disable_fbc(dev);
3262
3263         intel_disable_pipe(dev_priv, pipe);
3264
3265         /* Disable PF */
3266         I915_WRITE(PF_CTL(pipe), 0);
3267         I915_WRITE(PF_WIN_SZ(pipe), 0);
3268
3269         for_each_encoder_on_crtc(dev, crtc, encoder)
3270                 if (encoder->post_disable)
3271                         encoder->post_disable(encoder);
3272
3273         ironlake_fdi_disable(crtc);
3274
3275         intel_disable_transcoder(dev_priv, pipe);
3276
3277         if (HAS_PCH_CPT(dev)) {
3278                 /* disable TRANS_DP_CTL */
3279                 reg = TRANS_DP_CTL(pipe);
3280                 temp = I915_READ(reg);
3281                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3282                 temp |= TRANS_DP_PORT_SEL_NONE;
3283                 I915_WRITE(reg, temp);
3284
3285                 /* disable DPLL_SEL */
3286                 temp = I915_READ(PCH_DPLL_SEL);
3287                 switch (pipe) {
3288                 case 0:
3289                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3290                         break;
3291                 case 1:
3292                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3293                         break;
3294                 case 2:
3295                         /* C shares PLL A or B */
3296                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3297                         break;
3298                 default:
3299                         BUG(); /* wtf */
3300                 }
3301                 I915_WRITE(PCH_DPLL_SEL, temp);
3302         }
3303
3304         /* disable PCH DPLL */
3305         intel_disable_pch_pll(intel_crtc);
3306
3307         ironlake_fdi_pll_disable(intel_crtc);
3308
3309         intel_crtc->active = false;
3310         intel_update_watermarks(dev);
3311
3312         mutex_lock(&dev->struct_mutex);
3313         intel_update_fbc(dev);
3314         mutex_unlock(&dev->struct_mutex);
3315 }
3316
3317 static void ironlake_crtc_off(struct drm_crtc *crtc)
3318 {
3319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3320         intel_put_pch_pll(intel_crtc);
3321 }
3322
3323 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3324 {
3325         if (!enable && intel_crtc->overlay) {
3326                 struct drm_device *dev = intel_crtc->base.dev;
3327                 struct drm_i915_private *dev_priv = dev->dev_private;
3328
3329                 mutex_lock(&dev->struct_mutex);
3330                 dev_priv->mm.interruptible = false;
3331                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3332                 dev_priv->mm.interruptible = true;
3333                 mutex_unlock(&dev->struct_mutex);
3334         }
3335
3336         /* Let userspace switch the overlay on again. In most cases userspace
3337          * has to recompute where to put it anyway.
3338          */
3339 }
3340
3341 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         struct intel_encoder *encoder;
3347         int pipe = intel_crtc->pipe;
3348         int plane = intel_crtc->plane;
3349
3350         WARN_ON(!crtc->enabled);
3351
3352         if (intel_crtc->active)
3353                 return;
3354
3355         intel_crtc->active = true;
3356         intel_update_watermarks(dev);
3357
3358         intel_enable_pll(dev_priv, pipe);
3359         intel_enable_pipe(dev_priv, pipe, false);
3360         intel_enable_plane(dev_priv, plane, pipe);
3361
3362         intel_crtc_load_lut(crtc);
3363         intel_update_fbc(dev);
3364
3365         /* Give the overlay scaler a chance to enable if it's on this pipe */
3366         intel_crtc_dpms_overlay(intel_crtc, true);
3367         intel_crtc_update_cursor(crtc, true);
3368
3369         for_each_encoder_on_crtc(dev, crtc, encoder)
3370                 encoder->enable(encoder);
3371 }
3372
3373 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3374 {
3375         struct drm_device *dev = crtc->dev;
3376         struct drm_i915_private *dev_priv = dev->dev_private;
3377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3378         struct intel_encoder *encoder;
3379         int pipe = intel_crtc->pipe;
3380         int plane = intel_crtc->plane;
3381
3382
3383         if (!intel_crtc->active)
3384                 return;
3385
3386         for_each_encoder_on_crtc(dev, crtc, encoder)
3387                 encoder->disable(encoder);
3388
3389         /* Give the overlay scaler a chance to disable if it's on this pipe */
3390         intel_crtc_wait_for_pending_flips(crtc);
3391         drm_vblank_off(dev, pipe);
3392         intel_crtc_dpms_overlay(intel_crtc, false);
3393         intel_crtc_update_cursor(crtc, false);
3394
3395         if (dev_priv->cfb_plane == plane)
3396                 intel_disable_fbc(dev);
3397
3398         intel_disable_plane(dev_priv, plane, pipe);
3399         intel_disable_pipe(dev_priv, pipe);
3400         intel_disable_pll(dev_priv, pipe);
3401
3402         intel_crtc->active = false;
3403         intel_update_fbc(dev);
3404         intel_update_watermarks(dev);
3405 }
3406
3407 static void i9xx_crtc_off(struct drm_crtc *crtc)
3408 {
3409 }
3410
3411 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3412                                     bool enabled)
3413 {
3414         struct drm_device *dev = crtc->dev;
3415         struct drm_i915_master_private *master_priv;
3416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3417         int pipe = intel_crtc->pipe;
3418
3419         if (!dev->primary->master)
3420                 return;
3421
3422         master_priv = dev->primary->master->driver_priv;
3423         if (!master_priv->sarea_priv)
3424                 return;
3425
3426         switch (pipe) {
3427         case 0:
3428                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3429                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3430                 break;
3431         case 1:
3432                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3433                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3434                 break;
3435         default:
3436                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3437                 break;
3438         }
3439 }
3440
3441 /**
3442  * Sets the power management mode of the pipe and plane.
3443  */
3444 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->dev;
3447         struct drm_i915_private *dev_priv = dev->dev_private;
3448         struct intel_encoder *intel_encoder;
3449         bool enable = false;
3450
3451         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3452                 enable |= intel_encoder->connectors_active;
3453
3454         if (enable)
3455                 dev_priv->display.crtc_enable(crtc);
3456         else
3457                 dev_priv->display.crtc_disable(crtc);
3458
3459         intel_crtc_update_sarea(crtc, enable);
3460 }
3461
3462 static void intel_crtc_noop(struct drm_crtc *crtc)
3463 {
3464 }
3465
3466 static void intel_crtc_disable(struct drm_crtc *crtc)
3467 {
3468         struct drm_device *dev = crtc->dev;
3469         struct drm_connector *connector;
3470         struct drm_i915_private *dev_priv = dev->dev_private;
3471
3472         /* crtc should still be enabled when we disable it. */
3473         WARN_ON(!crtc->enabled);
3474
3475         dev_priv->display.crtc_disable(crtc);
3476         intel_crtc_update_sarea(crtc, false);
3477         dev_priv->display.off(crtc);
3478
3479         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3480         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3481
3482         if (crtc->fb) {
3483                 mutex_lock(&dev->struct_mutex);
3484                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3485                 mutex_unlock(&dev->struct_mutex);
3486                 crtc->fb = NULL;
3487         }
3488
3489         /* Update computed state. */
3490         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3491                 if (!connector->encoder || !connector->encoder->crtc)
3492                         continue;
3493
3494                 if (connector->encoder->crtc != crtc)
3495                         continue;
3496
3497                 connector->dpms = DRM_MODE_DPMS_OFF;
3498                 to_intel_encoder(connector->encoder)->connectors_active = false;
3499         }
3500 }
3501
3502 void intel_modeset_disable(struct drm_device *dev)
3503 {
3504         struct drm_crtc *crtc;
3505
3506         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3507                 if (crtc->enabled)
3508                         intel_crtc_disable(crtc);
3509         }
3510 }
3511
3512 void intel_encoder_noop(struct drm_encoder *encoder)
3513 {
3514 }
3515
3516 void intel_encoder_destroy(struct drm_encoder *encoder)
3517 {
3518         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3519
3520         drm_encoder_cleanup(encoder);
3521         kfree(intel_encoder);
3522 }
3523
3524 /* Simple dpms helper for encodres with just one connector, no cloning and only
3525  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3526  * state of the entire output pipe. */
3527 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3528 {
3529         if (mode == DRM_MODE_DPMS_ON) {
3530                 encoder->connectors_active = true;
3531
3532                 intel_crtc_update_dpms(encoder->base.crtc);
3533         } else {
3534                 encoder->connectors_active = false;
3535
3536                 intel_crtc_update_dpms(encoder->base.crtc);
3537         }
3538 }
3539
3540 /* Cross check the actual hw state with our own modeset state tracking (and it's
3541  * internal consistency). */
3542 static void intel_connector_check_state(struct intel_connector *connector)
3543 {
3544         if (connector->get_hw_state(connector)) {
3545                 struct intel_encoder *encoder = connector->encoder;
3546                 struct drm_crtc *crtc;
3547                 bool encoder_enabled;
3548                 enum pipe pipe;
3549
3550                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3551                               connector->base.base.id,
3552                               drm_get_connector_name(&connector->base));
3553
3554                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3555                      "wrong connector dpms state\n");
3556                 WARN(connector->base.encoder != &encoder->base,
3557                      "active connector not linked to encoder\n");
3558                 WARN(!encoder->connectors_active,
3559                      "encoder->connectors_active not set\n");
3560
3561                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3562                 WARN(!encoder_enabled, "encoder not enabled\n");
3563                 if (WARN_ON(!encoder->base.crtc))
3564                         return;
3565
3566                 crtc = encoder->base.crtc;
3567
3568                 WARN(!crtc->enabled, "crtc not enabled\n");
3569                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3570                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3571                      "encoder active on the wrong pipe\n");
3572         }
3573 }
3574
3575 /* Even simpler default implementation, if there's really no special case to
3576  * consider. */
3577 void intel_connector_dpms(struct drm_connector *connector, int mode)
3578 {
3579         struct intel_encoder *encoder = intel_attached_encoder(connector);
3580
3581         /* All the simple cases only support two dpms states. */
3582         if (mode != DRM_MODE_DPMS_ON)
3583                 mode = DRM_MODE_DPMS_OFF;
3584
3585         if (mode == connector->dpms)
3586                 return;
3587
3588         connector->dpms = mode;
3589
3590         /* Only need to change hw state when actually enabled */
3591         if (encoder->base.crtc)
3592                 intel_encoder_dpms(encoder, mode);
3593         else
3594                 WARN_ON(encoder->connectors_active != false);
3595
3596         intel_modeset_check_state(connector->dev);
3597 }
3598
3599 /* Simple connector->get_hw_state implementation for encoders that support only
3600  * one connector and no cloning and hence the encoder state determines the state
3601  * of the connector. */
3602 bool intel_connector_get_hw_state(struct intel_connector *connector)
3603 {
3604         enum pipe pipe = 0;
3605         struct intel_encoder *encoder = connector->encoder;
3606
3607         return encoder->get_hw_state(encoder, &pipe);
3608 }
3609
3610 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3611                                   const struct drm_display_mode *mode,
3612                                   struct drm_display_mode *adjusted_mode)
3613 {
3614         struct drm_device *dev = crtc->dev;
3615
3616         if (HAS_PCH_SPLIT(dev)) {
3617                 /* FDI link clock is fixed at 2.7G */
3618                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3619                         return false;
3620         }
3621
3622         /* All interlaced capable intel hw wants timings in frames. Note though
3623          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3624          * timings, so we need to be careful not to clobber these.*/
3625         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3626                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3627
3628         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3629          * with a hsync front porch of 0.
3630          */
3631         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3632                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3633                 return false;
3634
3635         return true;
3636 }
3637
3638 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3639 {
3640         return 400000; /* FIXME */
3641 }
3642
3643 static int i945_get_display_clock_speed(struct drm_device *dev)
3644 {
3645         return 400000;
3646 }
3647
3648 static int i915_get_display_clock_speed(struct drm_device *dev)
3649 {
3650         return 333000;
3651 }
3652
3653 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3654 {
3655         return 200000;
3656 }
3657
3658 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3659 {
3660         u16 gcfgc = 0;
3661
3662         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3663
3664         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3665                 return 133000;
3666         else {
3667                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3668                 case GC_DISPLAY_CLOCK_333_MHZ:
3669                         return 333000;
3670                 default:
3671                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3672                         return 190000;
3673                 }
3674         }
3675 }
3676
3677 static int i865_get_display_clock_speed(struct drm_device *dev)
3678 {
3679         return 266000;
3680 }
3681
3682 static int i855_get_display_clock_speed(struct drm_device *dev)
3683 {
3684         u16 hpllcc = 0;
3685         /* Assume that the hardware is in the high speed state.  This
3686          * should be the default.
3687          */
3688         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3689         case GC_CLOCK_133_200:
3690         case GC_CLOCK_100_200:
3691                 return 200000;
3692         case GC_CLOCK_166_250:
3693                 return 250000;
3694         case GC_CLOCK_100_133:
3695                 return 133000;
3696         }
3697
3698         /* Shouldn't happen */
3699         return 0;
3700 }
3701
3702 static int i830_get_display_clock_speed(struct drm_device *dev)
3703 {
3704         return 133000;
3705 }
3706
3707 struct fdi_m_n {
3708         u32        tu;
3709         u32        gmch_m;
3710         u32        gmch_n;
3711         u32        link_m;
3712         u32        link_n;
3713 };
3714
3715 static void
3716 fdi_reduce_ratio(u32 *num, u32 *den)
3717 {
3718         while (*num > 0xffffff || *den > 0xffffff) {
3719                 *num >>= 1;
3720                 *den >>= 1;
3721         }
3722 }
3723
3724 static void
3725 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3726                      int link_clock, struct fdi_m_n *m_n)
3727 {
3728         m_n->tu = 64; /* default size */
3729
3730         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3731         m_n->gmch_m = bits_per_pixel * pixel_clock;
3732         m_n->gmch_n = link_clock * nlanes * 8;
3733         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3734
3735         m_n->link_m = pixel_clock;
3736         m_n->link_n = link_clock;
3737         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3738 }
3739
3740 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3741 {
3742         if (i915_panel_use_ssc >= 0)
3743                 return i915_panel_use_ssc != 0;
3744         return dev_priv->lvds_use_ssc
3745                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3746 }
3747
3748 /**
3749  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3750  * @crtc: CRTC structure
3751  * @mode: requested mode
3752  *
3753  * A pipe may be connected to one or more outputs.  Based on the depth of the
3754  * attached framebuffer, choose a good color depth to use on the pipe.
3755  *
3756  * If possible, match the pipe depth to the fb depth.  In some cases, this
3757  * isn't ideal, because the connected output supports a lesser or restricted
3758  * set of depths.  Resolve that here:
3759  *    LVDS typically supports only 6bpc, so clamp down in that case
3760  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3761  *    Displays may support a restricted set as well, check EDID and clamp as
3762  *      appropriate.
3763  *    DP may want to dither down to 6bpc to fit larger modes
3764  *
3765  * RETURNS:
3766  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3767  * true if they don't match).
3768  */
3769 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3770                                          struct drm_framebuffer *fb,
3771                                          unsigned int *pipe_bpp,
3772                                          struct drm_display_mode *mode)
3773 {
3774         struct drm_device *dev = crtc->dev;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         struct drm_connector *connector;
3777         struct intel_encoder *intel_encoder;
3778         unsigned int display_bpc = UINT_MAX, bpc;
3779
3780         /* Walk the encoders & connectors on this crtc, get min bpc */
3781         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3782
3783                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3784                         unsigned int lvds_bpc;
3785
3786                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3787                             LVDS_A3_POWER_UP)
3788                                 lvds_bpc = 8;
3789                         else
3790                                 lvds_bpc = 6;
3791
3792                         if (lvds_bpc < display_bpc) {
3793                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3794                                 display_bpc = lvds_bpc;
3795                         }
3796                         continue;
3797                 }
3798
3799                 /* Not one of the known troublemakers, check the EDID */
3800                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3801                                     head) {
3802                         if (connector->encoder != &intel_encoder->base)
3803                                 continue;
3804
3805                         /* Don't use an invalid EDID bpc value */
3806                         if (connector->display_info.bpc &&
3807                             connector->display_info.bpc < display_bpc) {
3808                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3809                                 display_bpc = connector->display_info.bpc;
3810                         }
3811                 }
3812
3813                 /*
3814                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3815                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3816                  */
3817                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3818                         if (display_bpc > 8 && display_bpc < 12) {
3819                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3820                                 display_bpc = 12;
3821                         } else {
3822                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3823                                 display_bpc = 8;
3824                         }
3825                 }
3826         }
3827
3828         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3829                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3830                 display_bpc = 6;
3831         }
3832
3833         /*
3834          * We could just drive the pipe at the highest bpc all the time and
3835          * enable dithering as needed, but that costs bandwidth.  So choose
3836          * the minimum value that expresses the full color range of the fb but
3837          * also stays within the max display bpc discovered above.
3838          */
3839
3840         switch (fb->depth) {
3841         case 8:
3842                 bpc = 8; /* since we go through a colormap */
3843                 break;
3844         case 15:
3845         case 16:
3846                 bpc = 6; /* min is 18bpp */
3847                 break;
3848         case 24:
3849                 bpc = 8;
3850                 break;
3851         case 30:
3852                 bpc = 10;
3853                 break;
3854         case 48:
3855                 bpc = 12;
3856                 break;
3857         default:
3858                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3859                 bpc = min((unsigned int)8, display_bpc);
3860                 break;
3861         }
3862
3863         display_bpc = min(display_bpc, bpc);
3864
3865         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3866                       bpc, display_bpc);
3867
3868         *pipe_bpp = display_bpc * 3;
3869
3870         return display_bpc != bpc;
3871 }
3872
3873 static int vlv_get_refclk(struct drm_crtc *crtc)
3874 {
3875         struct drm_device *dev = crtc->dev;
3876         struct drm_i915_private *dev_priv = dev->dev_private;
3877         int refclk = 27000; /* for DP & HDMI */
3878
3879         return 100000; /* only one validated so far */
3880
3881         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3882                 refclk = 96000;
3883         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3884                 if (intel_panel_use_ssc(dev_priv))
3885                         refclk = 100000;
3886                 else
3887                         refclk = 96000;
3888         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3889                 refclk = 100000;
3890         }
3891
3892         return refclk;
3893 }
3894
3895 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3896 {
3897         struct drm_device *dev = crtc->dev;
3898         struct drm_i915_private *dev_priv = dev->dev_private;
3899         int refclk;
3900
3901         if (IS_VALLEYVIEW(dev)) {
3902                 refclk = vlv_get_refclk(crtc);
3903         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3904             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3905                 refclk = dev_priv->lvds_ssc_freq * 1000;
3906                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3907                               refclk / 1000);
3908         } else if (!IS_GEN2(dev)) {
3909                 refclk = 96000;
3910         } else {
3911                 refclk = 48000;
3912         }
3913
3914         return refclk;
3915 }
3916
3917 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3918                                       intel_clock_t *clock)
3919 {
3920         /* SDVO TV has fixed PLL values depend on its clock range,
3921            this mirrors vbios setting. */
3922         if (adjusted_mode->clock >= 100000
3923             && adjusted_mode->clock < 140500) {
3924                 clock->p1 = 2;
3925                 clock->p2 = 10;
3926                 clock->n = 3;
3927                 clock->m1 = 16;
3928                 clock->m2 = 8;
3929         } else if (adjusted_mode->clock >= 140500
3930                    && adjusted_mode->clock <= 200000) {
3931                 clock->p1 = 1;
3932                 clock->p2 = 10;
3933                 clock->n = 6;
3934                 clock->m1 = 12;
3935                 clock->m2 = 8;
3936         }
3937 }
3938
3939 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3940                                      intel_clock_t *clock,
3941                                      intel_clock_t *reduced_clock)
3942 {
3943         struct drm_device *dev = crtc->dev;
3944         struct drm_i915_private *dev_priv = dev->dev_private;
3945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3946         int pipe = intel_crtc->pipe;
3947         u32 fp, fp2 = 0;
3948
3949         if (IS_PINEVIEW(dev)) {
3950                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3951                 if (reduced_clock)
3952                         fp2 = (1 << reduced_clock->n) << 16 |
3953                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3954         } else {
3955                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3956                 if (reduced_clock)
3957                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3958                                 reduced_clock->m2;
3959         }
3960
3961         I915_WRITE(FP0(pipe), fp);
3962
3963         intel_crtc->lowfreq_avail = false;
3964         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3965             reduced_clock && i915_powersave) {
3966                 I915_WRITE(FP1(pipe), fp2);
3967                 intel_crtc->lowfreq_avail = true;
3968         } else {
3969                 I915_WRITE(FP1(pipe), fp);
3970         }
3971 }
3972
3973 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3974                               struct drm_display_mode *adjusted_mode)
3975 {
3976         struct drm_device *dev = crtc->dev;
3977         struct drm_i915_private *dev_priv = dev->dev_private;
3978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979         int pipe = intel_crtc->pipe;
3980         u32 temp;
3981
3982         temp = I915_READ(LVDS);
3983         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3984         if (pipe == 1) {
3985                 temp |= LVDS_PIPEB_SELECT;
3986         } else {
3987                 temp &= ~LVDS_PIPEB_SELECT;
3988         }
3989         /* set the corresponsding LVDS_BORDER bit */
3990         temp |= dev_priv->lvds_border_bits;
3991         /* Set the B0-B3 data pairs corresponding to whether we're going to
3992          * set the DPLLs for dual-channel mode or not.
3993          */
3994         if (clock->p2 == 7)
3995                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3996         else
3997                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3998
3999         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4000          * appropriately here, but we need to look more thoroughly into how
4001          * panels behave in the two modes.
4002          */
4003         /* set the dithering flag on LVDS as needed */
4004         if (INTEL_INFO(dev)->gen >= 4) {
4005                 if (dev_priv->lvds_dither)
4006                         temp |= LVDS_ENABLE_DITHER;
4007                 else
4008                         temp &= ~LVDS_ENABLE_DITHER;
4009         }
4010         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4011         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4012                 temp |= LVDS_HSYNC_POLARITY;
4013         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4014                 temp |= LVDS_VSYNC_POLARITY;
4015         I915_WRITE(LVDS, temp);
4016 }
4017
4018 static void vlv_update_pll(struct drm_crtc *crtc,
4019                            struct drm_display_mode *mode,
4020                            struct drm_display_mode *adjusted_mode,
4021                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4022                            int num_connectors)
4023 {
4024         struct drm_device *dev = crtc->dev;
4025         struct drm_i915_private *dev_priv = dev->dev_private;
4026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4027         int pipe = intel_crtc->pipe;
4028         u32 dpll, mdiv, pdiv;
4029         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4030         bool is_sdvo;
4031         u32 temp;
4032
4033         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4034                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4035
4036         dpll = DPLL_VGA_MODE_DIS;
4037         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4038         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4039         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4040
4041         I915_WRITE(DPLL(pipe), dpll);
4042         POSTING_READ(DPLL(pipe));
4043
4044         bestn = clock->n;
4045         bestm1 = clock->m1;
4046         bestm2 = clock->m2;
4047         bestp1 = clock->p1;
4048         bestp2 = clock->p2;
4049
4050         /*
4051          * In Valleyview PLL and program lane counter registers are exposed
4052          * through DPIO interface
4053          */
4054         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4055         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4056         mdiv |= ((bestn << DPIO_N_SHIFT));
4057         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4058         mdiv |= (1 << DPIO_K_SHIFT);
4059         mdiv |= DPIO_ENABLE_CALIBRATION;
4060         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4061
4062         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4063
4064         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4065                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4066                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4067                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4068         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4069
4070         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4071
4072         dpll |= DPLL_VCO_ENABLE;
4073         I915_WRITE(DPLL(pipe), dpll);
4074         POSTING_READ(DPLL(pipe));
4075         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4076                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4077
4078         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4079
4080         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4081                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4082
4083         I915_WRITE(DPLL(pipe), dpll);
4084
4085         /* Wait for the clocks to stabilize. */
4086         POSTING_READ(DPLL(pipe));
4087         udelay(150);
4088
4089         temp = 0;
4090         if (is_sdvo) {
4091                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4092                 if (temp > 1)
4093                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4094                 else
4095                         temp = 0;
4096         }
4097         I915_WRITE(DPLL_MD(pipe), temp);
4098         POSTING_READ(DPLL_MD(pipe));
4099
4100         /* Now program lane control registers */
4101         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4102                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4103         {
4104                 temp = 0x1000C4;
4105                 if(pipe == 1)
4106                         temp |= (1 << 21);
4107                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4108         }
4109         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4110         {
4111                 temp = 0x1000C4;
4112                 if(pipe == 1)
4113                         temp |= (1 << 21);
4114                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4115         }
4116 }
4117
4118 static void i9xx_update_pll(struct drm_crtc *crtc,
4119                             struct drm_display_mode *mode,
4120                             struct drm_display_mode *adjusted_mode,
4121                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4122                             int num_connectors)
4123 {
4124         struct drm_device *dev = crtc->dev;
4125         struct drm_i915_private *dev_priv = dev->dev_private;
4126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127         int pipe = intel_crtc->pipe;
4128         u32 dpll;
4129         bool is_sdvo;
4130
4131         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4132
4133         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4134                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4135
4136         dpll = DPLL_VGA_MODE_DIS;
4137
4138         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4139                 dpll |= DPLLB_MODE_LVDS;
4140         else
4141                 dpll |= DPLLB_MODE_DAC_SERIAL;
4142         if (is_sdvo) {
4143                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4144                 if (pixel_multiplier > 1) {
4145                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4146                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4147                 }
4148                 dpll |= DPLL_DVO_HIGH_SPEED;
4149         }
4150         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4151                 dpll |= DPLL_DVO_HIGH_SPEED;
4152
4153         /* compute bitmask from p1 value */
4154         if (IS_PINEVIEW(dev))
4155                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4156         else {
4157                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4158                 if (IS_G4X(dev) && reduced_clock)
4159                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4160         }
4161         switch (clock->p2) {
4162         case 5:
4163                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4164                 break;
4165         case 7:
4166                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4167                 break;
4168         case 10:
4169                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4170                 break;
4171         case 14:
4172                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4173                 break;
4174         }
4175         if (INTEL_INFO(dev)->gen >= 4)
4176                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4177
4178         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4179                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4180         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4181                 /* XXX: just matching BIOS for now */
4182                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4183                 dpll |= 3;
4184         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4185                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4186                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4187         else
4188                 dpll |= PLL_REF_INPUT_DREFCLK;
4189
4190         dpll |= DPLL_VCO_ENABLE;
4191         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4192         POSTING_READ(DPLL(pipe));
4193         udelay(150);
4194
4195         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4196          * This is an exception to the general rule that mode_set doesn't turn
4197          * things on.
4198          */
4199         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4200                 intel_update_lvds(crtc, clock, adjusted_mode);
4201
4202         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4203                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4204
4205         I915_WRITE(DPLL(pipe), dpll);
4206
4207         /* Wait for the clocks to stabilize. */
4208         POSTING_READ(DPLL(pipe));
4209         udelay(150);
4210
4211         if (INTEL_INFO(dev)->gen >= 4) {
4212                 u32 temp = 0;
4213                 if (is_sdvo) {
4214                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4215                         if (temp > 1)
4216                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4217                         else
4218                                 temp = 0;
4219                 }
4220                 I915_WRITE(DPLL_MD(pipe), temp);
4221         } else {
4222                 /* The pixel multiplier can only be updated once the
4223                  * DPLL is enabled and the clocks are stable.
4224                  *
4225                  * So write it again.
4226                  */
4227                 I915_WRITE(DPLL(pipe), dpll);
4228         }
4229 }
4230
4231 static void i8xx_update_pll(struct drm_crtc *crtc,
4232                             struct drm_display_mode *adjusted_mode,
4233                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4234                             int num_connectors)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239         int pipe = intel_crtc->pipe;
4240         u32 dpll;
4241
4242         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4243
4244         dpll = DPLL_VGA_MODE_DIS;
4245
4246         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4247                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4248         } else {
4249                 if (clock->p1 == 2)
4250                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4251                 else
4252                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4253                 if (clock->p2 == 4)
4254                         dpll |= PLL_P2_DIVIDE_BY_4;
4255         }
4256
4257         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4258                 /* XXX: just matching BIOS for now */
4259                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4260                 dpll |= 3;
4261         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4262                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4263                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4264         else
4265                 dpll |= PLL_REF_INPUT_DREFCLK;
4266
4267         dpll |= DPLL_VCO_ENABLE;
4268         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4269         POSTING_READ(DPLL(pipe));
4270         udelay(150);
4271
4272         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4273          * This is an exception to the general rule that mode_set doesn't turn
4274          * things on.
4275          */
4276         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4277                 intel_update_lvds(crtc, clock, adjusted_mode);
4278
4279         I915_WRITE(DPLL(pipe), dpll);
4280
4281         /* Wait for the clocks to stabilize. */
4282         POSTING_READ(DPLL(pipe));
4283         udelay(150);
4284
4285         /* The pixel multiplier can only be updated once the
4286          * DPLL is enabled and the clocks are stable.
4287          *
4288          * So write it again.
4289          */
4290         I915_WRITE(DPLL(pipe), dpll);
4291 }
4292
4293 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4294                                    struct drm_display_mode *mode,
4295                                    struct drm_display_mode *adjusted_mode)
4296 {
4297         struct drm_device *dev = intel_crtc->base.dev;
4298         struct drm_i915_private *dev_priv = dev->dev_private;
4299         enum pipe pipe = intel_crtc->pipe;
4300         uint32_t vsyncshift;
4301
4302         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4303                 /* the chip adds 2 halflines automatically */
4304                 adjusted_mode->crtc_vtotal -= 1;
4305                 adjusted_mode->crtc_vblank_end -= 1;
4306                 vsyncshift = adjusted_mode->crtc_hsync_start
4307                              - adjusted_mode->crtc_htotal / 2;
4308         } else {
4309                 vsyncshift = 0;
4310         }
4311
4312         if (INTEL_INFO(dev)->gen > 3)
4313                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4314
4315         I915_WRITE(HTOTAL(pipe),
4316                    (adjusted_mode->crtc_hdisplay - 1) |
4317                    ((adjusted_mode->crtc_htotal - 1) << 16));
4318         I915_WRITE(HBLANK(pipe),
4319                    (adjusted_mode->crtc_hblank_start - 1) |
4320                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4321         I915_WRITE(HSYNC(pipe),
4322                    (adjusted_mode->crtc_hsync_start - 1) |
4323                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4324
4325         I915_WRITE(VTOTAL(pipe),
4326                    (adjusted_mode->crtc_vdisplay - 1) |
4327                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4328         I915_WRITE(VBLANK(pipe),
4329                    (adjusted_mode->crtc_vblank_start - 1) |
4330                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4331         I915_WRITE(VSYNC(pipe),
4332                    (adjusted_mode->crtc_vsync_start - 1) |
4333                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4334
4335         /* pipesrc controls the size that is scaled from, which should
4336          * always be the user's requested size.
4337          */
4338         I915_WRITE(PIPESRC(pipe),
4339                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4340 }
4341
4342 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4343                               struct drm_display_mode *mode,
4344                               struct drm_display_mode *adjusted_mode,
4345                               int x, int y,
4346                               struct drm_framebuffer *fb)
4347 {
4348         struct drm_device *dev = crtc->dev;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351         int pipe = intel_crtc->pipe;
4352         int plane = intel_crtc->plane;
4353         int refclk, num_connectors = 0;
4354         intel_clock_t clock, reduced_clock;
4355         u32 dspcntr, pipeconf;
4356         bool ok, has_reduced_clock = false, is_sdvo = false;
4357         bool is_lvds = false, is_tv = false, is_dp = false;
4358         struct intel_encoder *encoder;
4359         const intel_limit_t *limit;
4360         int ret;
4361
4362         for_each_encoder_on_crtc(dev, crtc, encoder) {
4363                 switch (encoder->type) {
4364                 case INTEL_OUTPUT_LVDS:
4365                         is_lvds = true;
4366                         break;
4367                 case INTEL_OUTPUT_SDVO:
4368                 case INTEL_OUTPUT_HDMI:
4369                         is_sdvo = true;
4370                         if (encoder->needs_tv_clock)
4371                                 is_tv = true;
4372                         break;
4373                 case INTEL_OUTPUT_TVOUT:
4374                         is_tv = true;
4375                         break;
4376                 case INTEL_OUTPUT_DISPLAYPORT:
4377                         is_dp = true;
4378                         break;
4379                 }
4380
4381                 num_connectors++;
4382         }
4383
4384         refclk = i9xx_get_refclk(crtc, num_connectors);
4385
4386         /*
4387          * Returns a set of divisors for the desired target clock with the given
4388          * refclk, or FALSE.  The returned values represent the clock equation:
4389          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4390          */
4391         limit = intel_limit(crtc, refclk);
4392         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4393                              &clock);
4394         if (!ok) {
4395                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4396                 return -EINVAL;
4397         }
4398
4399         /* Ensure that the cursor is valid for the new mode before changing... */
4400         intel_crtc_update_cursor(crtc, true);
4401
4402         if (is_lvds && dev_priv->lvds_downclock_avail) {
4403                 /*
4404                  * Ensure we match the reduced clock's P to the target clock.
4405                  * If the clocks don't match, we can't switch the display clock
4406                  * by using the FP0/FP1. In such case we will disable the LVDS
4407                  * downclock feature.
4408                 */
4409                 has_reduced_clock = limit->find_pll(limit, crtc,
4410                                                     dev_priv->lvds_downclock,
4411                                                     refclk,
4412                                                     &clock,
4413                                                     &reduced_clock);
4414         }
4415
4416         if (is_sdvo && is_tv)
4417                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4418
4419         if (IS_GEN2(dev))
4420                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4421                                 has_reduced_clock ? &reduced_clock : NULL,
4422                                 num_connectors);
4423         else if (IS_VALLEYVIEW(dev))
4424                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4425                                 has_reduced_clock ? &reduced_clock : NULL,
4426                                 num_connectors);
4427         else
4428                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4429                                 has_reduced_clock ? &reduced_clock : NULL,
4430                                 num_connectors);
4431
4432         /* setup pipeconf */
4433         pipeconf = I915_READ(PIPECONF(pipe));
4434
4435         /* Set up the display plane register */
4436         dspcntr = DISPPLANE_GAMMA_ENABLE;
4437
4438         if (pipe == 0)
4439                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4440         else
4441                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4442
4443         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4444                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4445                  * core speed.
4446                  *
4447                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4448                  * pipe == 0 check?
4449                  */
4450                 if (mode->clock >
4451                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4452                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4453                 else
4454                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4455         }
4456
4457         /* default to 8bpc */
4458         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4459         if (is_dp) {
4460                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4461                         pipeconf |= PIPECONF_BPP_6 |
4462                                     PIPECONF_DITHER_EN |
4463                                     PIPECONF_DITHER_TYPE_SP;
4464                 }
4465         }
4466
4467         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4468                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4469                         pipeconf |= PIPECONF_BPP_6 |
4470                                         PIPECONF_ENABLE |
4471                                         I965_PIPECONF_ACTIVE;
4472                 }
4473         }
4474
4475         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4476         drm_mode_debug_printmodeline(mode);
4477
4478         if (HAS_PIPE_CXSR(dev)) {
4479                 if (intel_crtc->lowfreq_avail) {
4480                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4481                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4482                 } else {
4483                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4484                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4485                 }
4486         }
4487
4488         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4489         if (!IS_GEN2(dev) &&
4490             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4491                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4492         else
4493                 pipeconf |= PIPECONF_PROGRESSIVE;
4494
4495         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4496
4497         /* pipesrc and dspsize control the size that is scaled from,
4498          * which should always be the user's requested size.
4499          */
4500         I915_WRITE(DSPSIZE(plane),
4501                    ((mode->vdisplay - 1) << 16) |
4502                    (mode->hdisplay - 1));
4503         I915_WRITE(DSPPOS(plane), 0);
4504
4505         I915_WRITE(PIPECONF(pipe), pipeconf);
4506         POSTING_READ(PIPECONF(pipe));
4507         intel_enable_pipe(dev_priv, pipe, false);
4508
4509         intel_wait_for_vblank(dev, pipe);
4510
4511         I915_WRITE(DSPCNTR(plane), dspcntr);
4512         POSTING_READ(DSPCNTR(plane));
4513
4514         ret = intel_pipe_set_base(crtc, x, y, fb);
4515
4516         intel_update_watermarks(dev);
4517
4518         return ret;
4519 }
4520
4521 /*
4522  * Initialize reference clocks when the driver loads
4523  */
4524 void ironlake_init_pch_refclk(struct drm_device *dev)
4525 {
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         struct drm_mode_config *mode_config = &dev->mode_config;
4528         struct intel_encoder *encoder;
4529         u32 temp;
4530         bool has_lvds = false;
4531         bool has_cpu_edp = false;
4532         bool has_pch_edp = false;
4533         bool has_panel = false;
4534         bool has_ck505 = false;
4535         bool can_ssc = false;
4536
4537         /* We need to take the global config into account */
4538         list_for_each_entry(encoder, &mode_config->encoder_list,
4539                             base.head) {
4540                 switch (encoder->type) {
4541                 case INTEL_OUTPUT_LVDS:
4542                         has_panel = true;
4543                         has_lvds = true;
4544                         break;
4545                 case INTEL_OUTPUT_EDP:
4546                         has_panel = true;
4547                         if (intel_encoder_is_pch_edp(&encoder->base))
4548                                 has_pch_edp = true;
4549                         else
4550                                 has_cpu_edp = true;
4551                         break;
4552                 }
4553         }
4554
4555         if (HAS_PCH_IBX(dev)) {
4556                 has_ck505 = dev_priv->display_clock_mode;
4557                 can_ssc = has_ck505;
4558         } else {
4559                 has_ck505 = false;
4560                 can_ssc = true;
4561         }
4562
4563         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4564                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4565                       has_ck505);
4566
4567         /* Ironlake: try to setup display ref clock before DPLL
4568          * enabling. This is only under driver's control after
4569          * PCH B stepping, previous chipset stepping should be
4570          * ignoring this setting.
4571          */
4572         temp = I915_READ(PCH_DREF_CONTROL);
4573         /* Always enable nonspread source */
4574         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4575
4576         if (has_ck505)
4577                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4578         else
4579                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4580
4581         if (has_panel) {
4582                 temp &= ~DREF_SSC_SOURCE_MASK;
4583                 temp |= DREF_SSC_SOURCE_ENABLE;
4584
4585                 /* SSC must be turned on before enabling the CPU output  */
4586                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4587                         DRM_DEBUG_KMS("Using SSC on panel\n");
4588                         temp |= DREF_SSC1_ENABLE;
4589                 } else
4590                         temp &= ~DREF_SSC1_ENABLE;
4591
4592                 /* Get SSC going before enabling the outputs */
4593                 I915_WRITE(PCH_DREF_CONTROL, temp);
4594                 POSTING_READ(PCH_DREF_CONTROL);
4595                 udelay(200);
4596
4597                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4598
4599                 /* Enable CPU source on CPU attached eDP */
4600                 if (has_cpu_edp) {
4601                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4602                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4603                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4604                         }
4605                         else
4606                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4607                 } else
4608                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4609
4610                 I915_WRITE(PCH_DREF_CONTROL, temp);
4611                 POSTING_READ(PCH_DREF_CONTROL);
4612                 udelay(200);
4613         } else {
4614                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4615
4616                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4617
4618                 /* Turn off CPU output */
4619                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4620
4621                 I915_WRITE(PCH_DREF_CONTROL, temp);
4622                 POSTING_READ(PCH_DREF_CONTROL);
4623                 udelay(200);
4624
4625                 /* Turn off the SSC source */
4626                 temp &= ~DREF_SSC_SOURCE_MASK;
4627                 temp |= DREF_SSC_SOURCE_DISABLE;
4628
4629                 /* Turn off SSC1 */
4630                 temp &= ~ DREF_SSC1_ENABLE;
4631
4632                 I915_WRITE(PCH_DREF_CONTROL, temp);
4633                 POSTING_READ(PCH_DREF_CONTROL);
4634                 udelay(200);
4635         }
4636 }
4637
4638 static int ironlake_get_refclk(struct drm_crtc *crtc)
4639 {
4640         struct drm_device *dev = crtc->dev;
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         struct intel_encoder *encoder;
4643         struct intel_encoder *edp_encoder = NULL;
4644         int num_connectors = 0;
4645         bool is_lvds = false;
4646
4647         for_each_encoder_on_crtc(dev, crtc, encoder) {
4648                 switch (encoder->type) {
4649                 case INTEL_OUTPUT_LVDS:
4650                         is_lvds = true;
4651                         break;
4652                 case INTEL_OUTPUT_EDP:
4653                         edp_encoder = encoder;
4654                         break;
4655                 }
4656                 num_connectors++;
4657         }
4658
4659         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4660                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4661                               dev_priv->lvds_ssc_freq);
4662                 return dev_priv->lvds_ssc_freq * 1000;
4663         }
4664
4665         return 120000;
4666 }
4667
4668 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4669                                   struct drm_display_mode *adjusted_mode,
4670                                   bool dither)
4671 {
4672         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4674         int pipe = intel_crtc->pipe;
4675         uint32_t val;
4676
4677         val = I915_READ(PIPECONF(pipe));
4678
4679         val &= ~PIPE_BPC_MASK;
4680         switch (intel_crtc->bpp) {
4681         case 18:
4682                 val |= PIPE_6BPC;
4683                 break;
4684         case 24:
4685                 val |= PIPE_8BPC;
4686                 break;
4687         case 30:
4688                 val |= PIPE_10BPC;
4689                 break;
4690         case 36:
4691                 val |= PIPE_12BPC;
4692                 break;
4693         default:
4694                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4695                 BUG();
4696         }
4697
4698         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4699         if (dither)
4700                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4701
4702         val &= ~PIPECONF_INTERLACE_MASK;
4703         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4704                 val |= PIPECONF_INTERLACED_ILK;
4705         else
4706                 val |= PIPECONF_PROGRESSIVE;
4707
4708         I915_WRITE(PIPECONF(pipe), val);
4709         POSTING_READ(PIPECONF(pipe));
4710 }
4711
4712 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4713                                     struct drm_display_mode *adjusted_mode,
4714                                     intel_clock_t *clock,
4715                                     bool *has_reduced_clock,
4716                                     intel_clock_t *reduced_clock)
4717 {
4718         struct drm_device *dev = crtc->dev;
4719         struct drm_i915_private *dev_priv = dev->dev_private;
4720         struct intel_encoder *intel_encoder;
4721         int refclk;
4722         const intel_limit_t *limit;
4723         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4724
4725         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4726                 switch (intel_encoder->type) {
4727                 case INTEL_OUTPUT_LVDS:
4728                         is_lvds = true;
4729                         break;
4730                 case INTEL_OUTPUT_SDVO:
4731                 case INTEL_OUTPUT_HDMI:
4732                         is_sdvo = true;
4733                         if (intel_encoder->needs_tv_clock)
4734                                 is_tv = true;
4735                         break;
4736                 case INTEL_OUTPUT_TVOUT:
4737                         is_tv = true;
4738                         break;
4739                 }
4740         }
4741
4742         refclk = ironlake_get_refclk(crtc);
4743
4744         /*
4745          * Returns a set of divisors for the desired target clock with the given
4746          * refclk, or FALSE.  The returned values represent the clock equation:
4747          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4748          */
4749         limit = intel_limit(crtc, refclk);
4750         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4751                               clock);
4752         if (!ret)
4753                 return false;
4754
4755         if (is_lvds && dev_priv->lvds_downclock_avail) {
4756                 /*
4757                  * Ensure we match the reduced clock's P to the target clock.
4758                  * If the clocks don't match, we can't switch the display clock
4759                  * by using the FP0/FP1. In such case we will disable the LVDS
4760                  * downclock feature.
4761                 */
4762                 *has_reduced_clock = limit->find_pll(limit, crtc,
4763                                                      dev_priv->lvds_downclock,
4764                                                      refclk,
4765                                                      clock,
4766                                                      reduced_clock);
4767         }
4768
4769         if (is_sdvo && is_tv)
4770                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4771
4772         return true;
4773 }
4774
4775 static void ironlake_set_m_n(struct drm_crtc *crtc,
4776                              struct drm_display_mode *mode,
4777                              struct drm_display_mode *adjusted_mode)
4778 {
4779         struct drm_device *dev = crtc->dev;
4780         struct drm_i915_private *dev_priv = dev->dev_private;
4781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782         enum pipe pipe = intel_crtc->pipe;
4783         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4784         struct fdi_m_n m_n = {0};
4785         int target_clock, pixel_multiplier, lane, link_bw;
4786         bool is_dp = false, is_cpu_edp = false;
4787
4788         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4789                 switch (intel_encoder->type) {
4790                 case INTEL_OUTPUT_DISPLAYPORT:
4791                         is_dp = true;
4792                         break;
4793                 case INTEL_OUTPUT_EDP:
4794                         is_dp = true;
4795                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4796                                 is_cpu_edp = true;
4797                         edp_encoder = intel_encoder;
4798                         break;
4799                 }
4800         }
4801
4802         /* FDI link */
4803         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4804         lane = 0;
4805         /* CPU eDP doesn't require FDI link, so just set DP M/N
4806            according to current link config */
4807         if (is_cpu_edp) {
4808                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4809         } else {
4810                 /* FDI is a binary signal running at ~2.7GHz, encoding
4811                  * each output octet as 10 bits. The actual frequency
4812                  * is stored as a divider into a 100MHz clock, and the
4813                  * mode pixel clock is stored in units of 1KHz.
4814                  * Hence the bw of each lane in terms of the mode signal
4815                  * is:
4816                  */
4817                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4818         }
4819
4820         /* [e]DP over FDI requires target mode clock instead of link clock. */
4821         if (edp_encoder)
4822                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4823         else if (is_dp)
4824                 target_clock = mode->clock;
4825         else
4826                 target_clock = adjusted_mode->clock;
4827
4828         if (!lane) {
4829                 /*
4830                  * Account for spread spectrum to avoid
4831                  * oversubscribing the link. Max center spread
4832                  * is 2.5%; use 5% for safety's sake.
4833                  */
4834                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4835                 lane = bps / (link_bw * 8) + 1;
4836         }
4837
4838         intel_crtc->fdi_lanes = lane;
4839
4840         if (pixel_multiplier > 1)
4841                 link_bw *= pixel_multiplier;
4842         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4843                              &m_n);
4844
4845         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4846         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4847         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4848         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4849 }
4850
4851 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4852                                       struct drm_display_mode *adjusted_mode,
4853                                       intel_clock_t *clock, u32 fp)
4854 {
4855         struct drm_crtc *crtc = &intel_crtc->base;
4856         struct drm_device *dev = crtc->dev;
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         struct intel_encoder *intel_encoder;
4859         uint32_t dpll;
4860         int factor, pixel_multiplier, num_connectors = 0;
4861         bool is_lvds = false, is_sdvo = false, is_tv = false;
4862         bool is_dp = false, is_cpu_edp = false;
4863
4864         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4865                 switch (intel_encoder->type) {
4866                 case INTEL_OUTPUT_LVDS:
4867                         is_lvds = true;
4868                         break;
4869                 case INTEL_OUTPUT_SDVO:
4870                 case INTEL_OUTPUT_HDMI:
4871                         is_sdvo = true;
4872                         if (intel_encoder->needs_tv_clock)
4873                                 is_tv = true;
4874                         break;
4875                 case INTEL_OUTPUT_TVOUT:
4876                         is_tv = true;
4877                         break;
4878                 case INTEL_OUTPUT_DISPLAYPORT:
4879                         is_dp = true;
4880                         break;
4881                 case INTEL_OUTPUT_EDP:
4882                         is_dp = true;
4883                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4884                                 is_cpu_edp = true;
4885                         break;
4886                 }
4887
4888                 num_connectors++;
4889         }
4890
4891         /* Enable autotuning of the PLL clock (if permissible) */
4892         factor = 21;
4893         if (is_lvds) {
4894                 if ((intel_panel_use_ssc(dev_priv) &&
4895                      dev_priv->lvds_ssc_freq == 100) ||
4896                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4897                         factor = 25;
4898         } else if (is_sdvo && is_tv)
4899                 factor = 20;
4900
4901         if (clock->m < factor * clock->n)
4902                 fp |= FP_CB_TUNE;
4903
4904         dpll = 0;
4905
4906         if (is_lvds)
4907                 dpll |= DPLLB_MODE_LVDS;
4908         else
4909                 dpll |= DPLLB_MODE_DAC_SERIAL;
4910         if (is_sdvo) {
4911                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4912                 if (pixel_multiplier > 1) {
4913                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4914                 }
4915                 dpll |= DPLL_DVO_HIGH_SPEED;
4916         }
4917         if (is_dp && !is_cpu_edp)
4918                 dpll |= DPLL_DVO_HIGH_SPEED;
4919
4920         /* compute bitmask from p1 value */
4921         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4922         /* also FPA1 */
4923         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4924
4925         switch (clock->p2) {
4926         case 5:
4927                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4928                 break;
4929         case 7:
4930                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4931                 break;
4932         case 10:
4933                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4934                 break;
4935         case 14:
4936                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4937                 break;
4938         }
4939
4940         if (is_sdvo && is_tv)
4941                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4942         else if (is_tv)
4943                 /* XXX: just matching BIOS for now */
4944                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4945                 dpll |= 3;
4946         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4947                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4948         else
4949                 dpll |= PLL_REF_INPUT_DREFCLK;
4950
4951         return dpll;
4952 }
4953
4954 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4955                                   struct drm_display_mode *mode,
4956                                   struct drm_display_mode *adjusted_mode,
4957                                   int x, int y,
4958                                   struct drm_framebuffer *fb)
4959 {
4960         struct drm_device *dev = crtc->dev;
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4963         int pipe = intel_crtc->pipe;
4964         int plane = intel_crtc->plane;
4965         int num_connectors = 0;
4966         intel_clock_t clock, reduced_clock;
4967         u32 dpll, fp = 0, fp2 = 0;
4968         bool ok, has_reduced_clock = false;
4969         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
4970         struct intel_encoder *encoder;
4971         u32 temp;
4972         int ret;
4973         bool dither;
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder) {
4976                 switch (encoder->type) {
4977                 case INTEL_OUTPUT_LVDS:
4978                         is_lvds = true;
4979                         break;
4980                 case INTEL_OUTPUT_DISPLAYPORT:
4981                         is_dp = true;
4982                         break;
4983                 case INTEL_OUTPUT_EDP:
4984                         is_dp = true;
4985                         if (!intel_encoder_is_pch_edp(&encoder->base))
4986                                 is_cpu_edp = true;
4987                         break;
4988                 }
4989
4990                 num_connectors++;
4991         }
4992
4993         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
4994                                      &has_reduced_clock, &reduced_clock);
4995         if (!ok) {
4996                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4997                 return -EINVAL;
4998         }
4999
5000         /* Ensure that the cursor is valid for the new mode before changing... */
5001         intel_crtc_update_cursor(crtc, true);
5002
5003         /* determine panel color depth */
5004         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5005         if (is_lvds && dev_priv->lvds_dither)
5006                 dither = true;
5007
5008         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5009         if (has_reduced_clock)
5010                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5011                         reduced_clock.m2;
5012
5013         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5014
5015         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5016         drm_mode_debug_printmodeline(mode);
5017
5018         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
5019          * pre-Haswell/LPT generation */
5020         if (HAS_PCH_LPT(dev)) {
5021                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
5022                                 pipe);
5023         } else if (!is_cpu_edp) {
5024                 struct intel_pch_pll *pll;
5025
5026                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5027                 if (pll == NULL) {
5028                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5029                                          pipe);
5030                         return -EINVAL;
5031                 }
5032         } else
5033                 intel_put_pch_pll(intel_crtc);
5034
5035         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5036          * This is an exception to the general rule that mode_set doesn't turn
5037          * things on.
5038          */
5039         if (is_lvds) {
5040                 temp = I915_READ(PCH_LVDS);
5041                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5042                 if (HAS_PCH_CPT(dev)) {
5043                         temp &= ~PORT_TRANS_SEL_MASK;
5044                         temp |= PORT_TRANS_SEL_CPT(pipe);
5045                 } else {
5046                         if (pipe == 1)
5047                                 temp |= LVDS_PIPEB_SELECT;
5048                         else
5049                                 temp &= ~LVDS_PIPEB_SELECT;
5050                 }
5051
5052                 /* set the corresponsding LVDS_BORDER bit */
5053                 temp |= dev_priv->lvds_border_bits;
5054                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5055                  * set the DPLLs for dual-channel mode or not.
5056                  */
5057                 if (clock.p2 == 7)
5058                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5059                 else
5060                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5061
5062                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5063                  * appropriately here, but we need to look more thoroughly into how
5064                  * panels behave in the two modes.
5065                  */
5066                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5067                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5068                         temp |= LVDS_HSYNC_POLARITY;
5069                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5070                         temp |= LVDS_VSYNC_POLARITY;
5071                 I915_WRITE(PCH_LVDS, temp);
5072         }
5073
5074         if (is_dp && !is_cpu_edp) {
5075                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5076         } else {
5077                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5078                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5079                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5080                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5081                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5082         }
5083
5084         if (intel_crtc->pch_pll) {
5085                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5086
5087                 /* Wait for the clocks to stabilize. */
5088                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5089                 udelay(150);
5090
5091                 /* The pixel multiplier can only be updated once the
5092                  * DPLL is enabled and the clocks are stable.
5093                  *
5094                  * So write it again.
5095                  */
5096                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5097         }
5098
5099         intel_crtc->lowfreq_avail = false;
5100         if (intel_crtc->pch_pll) {
5101                 if (is_lvds && has_reduced_clock && i915_powersave) {
5102                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5103                         intel_crtc->lowfreq_avail = true;
5104                 } else {
5105                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5106                 }
5107         }
5108
5109         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5110
5111         ironlake_set_m_n(crtc, mode, adjusted_mode);
5112
5113         if (is_cpu_edp)
5114                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5115
5116         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5117
5118         intel_wait_for_vblank(dev, pipe);
5119
5120         /* Set up the display plane register */
5121         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5122         POSTING_READ(DSPCNTR(plane));
5123
5124         ret = intel_pipe_set_base(crtc, x, y, fb);
5125
5126         intel_update_watermarks(dev);
5127
5128         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5129
5130         return ret;
5131 }
5132
5133 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5134                                struct drm_display_mode *mode,
5135                                struct drm_display_mode *adjusted_mode,
5136                                int x, int y,
5137                                struct drm_framebuffer *fb)
5138 {
5139         struct drm_device *dev = crtc->dev;
5140         struct drm_i915_private *dev_priv = dev->dev_private;
5141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5142         int pipe = intel_crtc->pipe;
5143         int ret;
5144
5145         drm_vblank_pre_modeset(dev, pipe);
5146
5147         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5148                                               x, y, fb);
5149         drm_vblank_post_modeset(dev, pipe);
5150
5151         return ret;
5152 }
5153
5154 static bool intel_eld_uptodate(struct drm_connector *connector,
5155                                int reg_eldv, uint32_t bits_eldv,
5156                                int reg_elda, uint32_t bits_elda,
5157                                int reg_edid)
5158 {
5159         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5160         uint8_t *eld = connector->eld;
5161         uint32_t i;
5162
5163         i = I915_READ(reg_eldv);
5164         i &= bits_eldv;
5165
5166         if (!eld[0])
5167                 return !i;
5168
5169         if (!i)
5170                 return false;
5171
5172         i = I915_READ(reg_elda);
5173         i &= ~bits_elda;
5174         I915_WRITE(reg_elda, i);
5175
5176         for (i = 0; i < eld[2]; i++)
5177                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5178                         return false;
5179
5180         return true;
5181 }
5182
5183 static void g4x_write_eld(struct drm_connector *connector,
5184                           struct drm_crtc *crtc)
5185 {
5186         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5187         uint8_t *eld = connector->eld;
5188         uint32_t eldv;
5189         uint32_t len;
5190         uint32_t i;
5191
5192         i = I915_READ(G4X_AUD_VID_DID);
5193
5194         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5195                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5196         else
5197                 eldv = G4X_ELDV_DEVCTG;
5198
5199         if (intel_eld_uptodate(connector,
5200                                G4X_AUD_CNTL_ST, eldv,
5201                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5202                                G4X_HDMIW_HDMIEDID))
5203                 return;
5204
5205         i = I915_READ(G4X_AUD_CNTL_ST);
5206         i &= ~(eldv | G4X_ELD_ADDR);
5207         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5208         I915_WRITE(G4X_AUD_CNTL_ST, i);
5209
5210         if (!eld[0])
5211                 return;
5212
5213         len = min_t(uint8_t, eld[2], len);
5214         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5215         for (i = 0; i < len; i++)
5216                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5217
5218         i = I915_READ(G4X_AUD_CNTL_ST);
5219         i |= eldv;
5220         I915_WRITE(G4X_AUD_CNTL_ST, i);
5221 }
5222
5223 static void haswell_write_eld(struct drm_connector *connector,
5224                                      struct drm_crtc *crtc)
5225 {
5226         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5227         uint8_t *eld = connector->eld;
5228         struct drm_device *dev = crtc->dev;
5229         uint32_t eldv;
5230         uint32_t i;
5231         int len;
5232         int pipe = to_intel_crtc(crtc)->pipe;
5233         int tmp;
5234
5235         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5236         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5237         int aud_config = HSW_AUD_CFG(pipe);
5238         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5239
5240
5241         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5242
5243         /* Audio output enable */
5244         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5245         tmp = I915_READ(aud_cntrl_st2);
5246         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5247         I915_WRITE(aud_cntrl_st2, tmp);
5248
5249         /* Wait for 1 vertical blank */
5250         intel_wait_for_vblank(dev, pipe);
5251
5252         /* Set ELD valid state */
5253         tmp = I915_READ(aud_cntrl_st2);
5254         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5255         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5256         I915_WRITE(aud_cntrl_st2, tmp);
5257         tmp = I915_READ(aud_cntrl_st2);
5258         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5259
5260         /* Enable HDMI mode */
5261         tmp = I915_READ(aud_config);
5262         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5263         /* clear N_programing_enable and N_value_index */
5264         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5265         I915_WRITE(aud_config, tmp);
5266
5267         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5268
5269         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5270
5271         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5272                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5273                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5274                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5275         } else
5276                 I915_WRITE(aud_config, 0);
5277
5278         if (intel_eld_uptodate(connector,
5279                                aud_cntrl_st2, eldv,
5280                                aud_cntl_st, IBX_ELD_ADDRESS,
5281                                hdmiw_hdmiedid))
5282                 return;
5283
5284         i = I915_READ(aud_cntrl_st2);
5285         i &= ~eldv;
5286         I915_WRITE(aud_cntrl_st2, i);
5287
5288         if (!eld[0])
5289                 return;
5290
5291         i = I915_READ(aud_cntl_st);
5292         i &= ~IBX_ELD_ADDRESS;
5293         I915_WRITE(aud_cntl_st, i);
5294         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5295         DRM_DEBUG_DRIVER("port num:%d\n", i);
5296
5297         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5298         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5299         for (i = 0; i < len; i++)
5300                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5301
5302         i = I915_READ(aud_cntrl_st2);
5303         i |= eldv;
5304         I915_WRITE(aud_cntrl_st2, i);
5305
5306 }
5307
5308 static void ironlake_write_eld(struct drm_connector *connector,
5309                                      struct drm_crtc *crtc)
5310 {
5311         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5312         uint8_t *eld = connector->eld;
5313         uint32_t eldv;
5314         uint32_t i;
5315         int len;
5316         int hdmiw_hdmiedid;
5317         int aud_config;
5318         int aud_cntl_st;
5319         int aud_cntrl_st2;
5320         int pipe = to_intel_crtc(crtc)->pipe;
5321
5322         if (HAS_PCH_IBX(connector->dev)) {
5323                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5324                 aud_config = IBX_AUD_CFG(pipe);
5325                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5326                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5327         } else {
5328                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5329                 aud_config = CPT_AUD_CFG(pipe);
5330                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5331                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5332         }
5333
5334         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5335
5336         i = I915_READ(aud_cntl_st);
5337         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5338         if (!i) {
5339                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5340                 /* operate blindly on all ports */
5341                 eldv = IBX_ELD_VALIDB;
5342                 eldv |= IBX_ELD_VALIDB << 4;
5343                 eldv |= IBX_ELD_VALIDB << 8;
5344         } else {
5345                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5346                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5347         }
5348
5349         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5350                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5351                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5352                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5353         } else
5354                 I915_WRITE(aud_config, 0);
5355
5356         if (intel_eld_uptodate(connector,
5357                                aud_cntrl_st2, eldv,
5358                                aud_cntl_st, IBX_ELD_ADDRESS,
5359                                hdmiw_hdmiedid))
5360                 return;
5361
5362         i = I915_READ(aud_cntrl_st2);
5363         i &= ~eldv;
5364         I915_WRITE(aud_cntrl_st2, i);
5365
5366         if (!eld[0])
5367                 return;
5368
5369         i = I915_READ(aud_cntl_st);
5370         i &= ~IBX_ELD_ADDRESS;
5371         I915_WRITE(aud_cntl_st, i);
5372
5373         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5374         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5375         for (i = 0; i < len; i++)
5376                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5377
5378         i = I915_READ(aud_cntrl_st2);
5379         i |= eldv;
5380         I915_WRITE(aud_cntrl_st2, i);
5381 }
5382
5383 void intel_write_eld(struct drm_encoder *encoder,
5384                      struct drm_display_mode *mode)
5385 {
5386         struct drm_crtc *crtc = encoder->crtc;
5387         struct drm_connector *connector;
5388         struct drm_device *dev = encoder->dev;
5389         struct drm_i915_private *dev_priv = dev->dev_private;
5390
5391         connector = drm_select_eld(encoder, mode);
5392         if (!connector)
5393                 return;
5394
5395         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5396                          connector->base.id,
5397                          drm_get_connector_name(connector),
5398                          connector->encoder->base.id,
5399                          drm_get_encoder_name(connector->encoder));
5400
5401         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5402
5403         if (dev_priv->display.write_eld)
5404                 dev_priv->display.write_eld(connector, crtc);
5405 }
5406
5407 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5408 void intel_crtc_load_lut(struct drm_crtc *crtc)
5409 {
5410         struct drm_device *dev = crtc->dev;
5411         struct drm_i915_private *dev_priv = dev->dev_private;
5412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413         int palreg = PALETTE(intel_crtc->pipe);
5414         int i;
5415
5416         /* The clocks have to be on to load the palette. */
5417         if (!crtc->enabled || !intel_crtc->active)
5418                 return;
5419
5420         /* use legacy palette for Ironlake */
5421         if (HAS_PCH_SPLIT(dev))
5422                 palreg = LGC_PALETTE(intel_crtc->pipe);
5423
5424         for (i = 0; i < 256; i++) {
5425                 I915_WRITE(palreg + 4 * i,
5426                            (intel_crtc->lut_r[i] << 16) |
5427                            (intel_crtc->lut_g[i] << 8) |
5428                            intel_crtc->lut_b[i]);
5429         }
5430 }
5431
5432 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5433 {
5434         struct drm_device *dev = crtc->dev;
5435         struct drm_i915_private *dev_priv = dev->dev_private;
5436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437         bool visible = base != 0;
5438         u32 cntl;
5439
5440         if (intel_crtc->cursor_visible == visible)
5441                 return;
5442
5443         cntl = I915_READ(_CURACNTR);
5444         if (visible) {
5445                 /* On these chipsets we can only modify the base whilst
5446                  * the cursor is disabled.
5447                  */
5448                 I915_WRITE(_CURABASE, base);
5449
5450                 cntl &= ~(CURSOR_FORMAT_MASK);
5451                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5452                 cntl |= CURSOR_ENABLE |
5453                         CURSOR_GAMMA_ENABLE |
5454                         CURSOR_FORMAT_ARGB;
5455         } else
5456                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5457         I915_WRITE(_CURACNTR, cntl);
5458
5459         intel_crtc->cursor_visible = visible;
5460 }
5461
5462 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5463 {
5464         struct drm_device *dev = crtc->dev;
5465         struct drm_i915_private *dev_priv = dev->dev_private;
5466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5467         int pipe = intel_crtc->pipe;
5468         bool visible = base != 0;
5469
5470         if (intel_crtc->cursor_visible != visible) {
5471                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5472                 if (base) {
5473                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5474                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5475                         cntl |= pipe << 28; /* Connect to correct pipe */
5476                 } else {
5477                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5478                         cntl |= CURSOR_MODE_DISABLE;
5479                 }
5480                 I915_WRITE(CURCNTR(pipe), cntl);
5481
5482                 intel_crtc->cursor_visible = visible;
5483         }
5484         /* and commit changes on next vblank */
5485         I915_WRITE(CURBASE(pipe), base);
5486 }
5487
5488 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5489 {
5490         struct drm_device *dev = crtc->dev;
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5493         int pipe = intel_crtc->pipe;
5494         bool visible = base != 0;
5495
5496         if (intel_crtc->cursor_visible != visible) {
5497                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5498                 if (base) {
5499                         cntl &= ~CURSOR_MODE;
5500                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5501                 } else {
5502                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5503                         cntl |= CURSOR_MODE_DISABLE;
5504                 }
5505                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5506
5507                 intel_crtc->cursor_visible = visible;
5508         }
5509         /* and commit changes on next vblank */
5510         I915_WRITE(CURBASE_IVB(pipe), base);
5511 }
5512
5513 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5514 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5515                                      bool on)
5516 {
5517         struct drm_device *dev = crtc->dev;
5518         struct drm_i915_private *dev_priv = dev->dev_private;
5519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5520         int pipe = intel_crtc->pipe;
5521         int x = intel_crtc->cursor_x;
5522         int y = intel_crtc->cursor_y;
5523         u32 base, pos;
5524         bool visible;
5525
5526         pos = 0;
5527
5528         if (on && crtc->enabled && crtc->fb) {
5529                 base = intel_crtc->cursor_addr;
5530                 if (x > (int) crtc->fb->width)
5531                         base = 0;
5532
5533                 if (y > (int) crtc->fb->height)
5534                         base = 0;
5535         } else
5536                 base = 0;
5537
5538         if (x < 0) {
5539                 if (x + intel_crtc->cursor_width < 0)
5540                         base = 0;
5541
5542                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5543                 x = -x;
5544         }
5545         pos |= x << CURSOR_X_SHIFT;
5546
5547         if (y < 0) {
5548                 if (y + intel_crtc->cursor_height < 0)
5549                         base = 0;
5550
5551                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5552                 y = -y;
5553         }
5554         pos |= y << CURSOR_Y_SHIFT;
5555
5556         visible = base != 0;
5557         if (!visible && !intel_crtc->cursor_visible)
5558                 return;
5559
5560         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5561                 I915_WRITE(CURPOS_IVB(pipe), pos);
5562                 ivb_update_cursor(crtc, base);
5563         } else {
5564                 I915_WRITE(CURPOS(pipe), pos);
5565                 if (IS_845G(dev) || IS_I865G(dev))
5566                         i845_update_cursor(crtc, base);
5567                 else
5568                         i9xx_update_cursor(crtc, base);
5569         }
5570 }
5571
5572 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5573                                  struct drm_file *file,
5574                                  uint32_t handle,
5575                                  uint32_t width, uint32_t height)
5576 {
5577         struct drm_device *dev = crtc->dev;
5578         struct drm_i915_private *dev_priv = dev->dev_private;
5579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5580         struct drm_i915_gem_object *obj;
5581         uint32_t addr;
5582         int ret;
5583
5584         /* if we want to turn off the cursor ignore width and height */
5585         if (!handle) {
5586                 DRM_DEBUG_KMS("cursor off\n");
5587                 addr = 0;
5588                 obj = NULL;
5589                 mutex_lock(&dev->struct_mutex);
5590                 goto finish;
5591         }
5592
5593         /* Currently we only support 64x64 cursors */
5594         if (width != 64 || height != 64) {
5595                 DRM_ERROR("we currently only support 64x64 cursors\n");
5596                 return -EINVAL;
5597         }
5598
5599         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5600         if (&obj->base == NULL)
5601                 return -ENOENT;
5602
5603         if (obj->base.size < width * height * 4) {
5604                 DRM_ERROR("buffer is to small\n");
5605                 ret = -ENOMEM;
5606                 goto fail;
5607         }
5608
5609         /* we only need to pin inside GTT if cursor is non-phy */
5610         mutex_lock(&dev->struct_mutex);
5611         if (!dev_priv->info->cursor_needs_physical) {
5612                 if (obj->tiling_mode) {
5613                         DRM_ERROR("cursor cannot be tiled\n");
5614                         ret = -EINVAL;
5615                         goto fail_locked;
5616                 }
5617
5618                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5619                 if (ret) {
5620                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5621                         goto fail_locked;
5622                 }
5623
5624                 ret = i915_gem_object_put_fence(obj);
5625                 if (ret) {
5626                         DRM_ERROR("failed to release fence for cursor");
5627                         goto fail_unpin;
5628                 }
5629
5630                 addr = obj->gtt_offset;
5631         } else {
5632                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5633                 ret = i915_gem_attach_phys_object(dev, obj,
5634                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5635                                                   align);
5636                 if (ret) {
5637                         DRM_ERROR("failed to attach phys object\n");
5638                         goto fail_locked;
5639                 }
5640                 addr = obj->phys_obj->handle->busaddr;
5641         }
5642
5643         if (IS_GEN2(dev))
5644                 I915_WRITE(CURSIZE, (height << 12) | width);
5645
5646  finish:
5647         if (intel_crtc->cursor_bo) {
5648                 if (dev_priv->info->cursor_needs_physical) {
5649                         if (intel_crtc->cursor_bo != obj)
5650                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5651                 } else
5652                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5653                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5654         }
5655
5656         mutex_unlock(&dev->struct_mutex);
5657
5658         intel_crtc->cursor_addr = addr;
5659         intel_crtc->cursor_bo = obj;
5660         intel_crtc->cursor_width = width;
5661         intel_crtc->cursor_height = height;
5662
5663         intel_crtc_update_cursor(crtc, true);
5664
5665         return 0;
5666 fail_unpin:
5667         i915_gem_object_unpin(obj);
5668 fail_locked:
5669         mutex_unlock(&dev->struct_mutex);
5670 fail:
5671         drm_gem_object_unreference_unlocked(&obj->base);
5672         return ret;
5673 }
5674
5675 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5676 {
5677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678
5679         intel_crtc->cursor_x = x;
5680         intel_crtc->cursor_y = y;
5681
5682         intel_crtc_update_cursor(crtc, true);
5683
5684         return 0;
5685 }
5686
5687 /** Sets the color ramps on behalf of RandR */
5688 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5689                                  u16 blue, int regno)
5690 {
5691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692
5693         intel_crtc->lut_r[regno] = red >> 8;
5694         intel_crtc->lut_g[regno] = green >> 8;
5695         intel_crtc->lut_b[regno] = blue >> 8;
5696 }
5697
5698 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5699                              u16 *blue, int regno)
5700 {
5701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702
5703         *red = intel_crtc->lut_r[regno] << 8;
5704         *green = intel_crtc->lut_g[regno] << 8;
5705         *blue = intel_crtc->lut_b[regno] << 8;
5706 }
5707
5708 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5709                                  u16 *blue, uint32_t start, uint32_t size)
5710 {
5711         int end = (start + size > 256) ? 256 : start + size, i;
5712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5713
5714         for (i = start; i < end; i++) {
5715                 intel_crtc->lut_r[i] = red[i] >> 8;
5716                 intel_crtc->lut_g[i] = green[i] >> 8;
5717                 intel_crtc->lut_b[i] = blue[i] >> 8;
5718         }
5719
5720         intel_crtc_load_lut(crtc);
5721 }
5722
5723 /**
5724  * Get a pipe with a simple mode set on it for doing load-based monitor
5725  * detection.
5726  *
5727  * It will be up to the load-detect code to adjust the pipe as appropriate for
5728  * its requirements.  The pipe will be connected to no other encoders.
5729  *
5730  * Currently this code will only succeed if there is a pipe with no encoders
5731  * configured for it.  In the future, it could choose to temporarily disable
5732  * some outputs to free up a pipe for its use.
5733  *
5734  * \return crtc, or NULL if no pipes are available.
5735  */
5736
5737 /* VESA 640x480x72Hz mode to set on the pipe */
5738 static struct drm_display_mode load_detect_mode = {
5739         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5740                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5741 };
5742
5743 static struct drm_framebuffer *
5744 intel_framebuffer_create(struct drm_device *dev,
5745                          struct drm_mode_fb_cmd2 *mode_cmd,
5746                          struct drm_i915_gem_object *obj)
5747 {
5748         struct intel_framebuffer *intel_fb;
5749         int ret;
5750
5751         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5752         if (!intel_fb) {
5753                 drm_gem_object_unreference_unlocked(&obj->base);
5754                 return ERR_PTR(-ENOMEM);
5755         }
5756
5757         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5758         if (ret) {
5759                 drm_gem_object_unreference_unlocked(&obj->base);
5760                 kfree(intel_fb);
5761                 return ERR_PTR(ret);
5762         }
5763
5764         return &intel_fb->base;
5765 }
5766
5767 static u32
5768 intel_framebuffer_pitch_for_width(int width, int bpp)
5769 {
5770         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5771         return ALIGN(pitch, 64);
5772 }
5773
5774 static u32
5775 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5776 {
5777         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5778         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5779 }
5780
5781 static struct drm_framebuffer *
5782 intel_framebuffer_create_for_mode(struct drm_device *dev,
5783                                   struct drm_display_mode *mode,
5784                                   int depth, int bpp)
5785 {
5786         struct drm_i915_gem_object *obj;
5787         struct drm_mode_fb_cmd2 mode_cmd;
5788
5789         obj = i915_gem_alloc_object(dev,
5790                                     intel_framebuffer_size_for_mode(mode, bpp));
5791         if (obj == NULL)
5792                 return ERR_PTR(-ENOMEM);
5793
5794         mode_cmd.width = mode->hdisplay;
5795         mode_cmd.height = mode->vdisplay;
5796         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5797                                                                 bpp);
5798         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5799
5800         return intel_framebuffer_create(dev, &mode_cmd, obj);
5801 }
5802
5803 static struct drm_framebuffer *
5804 mode_fits_in_fbdev(struct drm_device *dev,
5805                    struct drm_display_mode *mode)
5806 {
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         struct drm_i915_gem_object *obj;
5809         struct drm_framebuffer *fb;
5810
5811         if (dev_priv->fbdev == NULL)
5812                 return NULL;
5813
5814         obj = dev_priv->fbdev->ifb.obj;
5815         if (obj == NULL)
5816                 return NULL;
5817
5818         fb = &dev_priv->fbdev->ifb.base;
5819         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5820                                                                fb->bits_per_pixel))
5821                 return NULL;
5822
5823         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5824                 return NULL;
5825
5826         return fb;
5827 }
5828
5829 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5830                                 struct drm_display_mode *mode,
5831                                 struct intel_load_detect_pipe *old)
5832 {
5833         struct intel_crtc *intel_crtc;
5834         struct intel_encoder *intel_encoder =
5835                 intel_attached_encoder(connector);
5836         struct drm_crtc *possible_crtc;
5837         struct drm_encoder *encoder = &intel_encoder->base;
5838         struct drm_crtc *crtc = NULL;
5839         struct drm_device *dev = encoder->dev;
5840         struct drm_framebuffer *fb;
5841         int i = -1;
5842
5843         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5844                       connector->base.id, drm_get_connector_name(connector),
5845                       encoder->base.id, drm_get_encoder_name(encoder));
5846
5847         /*
5848          * Algorithm gets a little messy:
5849          *
5850          *   - if the connector already has an assigned crtc, use it (but make
5851          *     sure it's on first)
5852          *
5853          *   - try to find the first unused crtc that can drive this connector,
5854          *     and use that if we find one
5855          */
5856
5857         /* See if we already have a CRTC for this connector */
5858         if (encoder->crtc) {
5859                 crtc = encoder->crtc;
5860
5861                 old->dpms_mode = connector->dpms;
5862                 old->load_detect_temp = false;
5863
5864                 /* Make sure the crtc and connector are running */
5865                 if (connector->dpms != DRM_MODE_DPMS_ON)
5866                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5867
5868                 return true;
5869         }
5870
5871         /* Find an unused one (if possible) */
5872         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5873                 i++;
5874                 if (!(encoder->possible_crtcs & (1 << i)))
5875                         continue;
5876                 if (!possible_crtc->enabled) {
5877                         crtc = possible_crtc;
5878                         break;
5879                 }
5880         }
5881
5882         /*
5883          * If we didn't find an unused CRTC, don't use any.
5884          */
5885         if (!crtc) {
5886                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5887                 return false;
5888         }
5889
5890         intel_encoder->new_crtc = to_intel_crtc(crtc);
5891         to_intel_connector(connector)->new_encoder = intel_encoder;
5892
5893         intel_crtc = to_intel_crtc(crtc);
5894         old->dpms_mode = connector->dpms;
5895         old->load_detect_temp = true;
5896         old->release_fb = NULL;
5897
5898         if (!mode)
5899                 mode = &load_detect_mode;
5900
5901         /* We need a framebuffer large enough to accommodate all accesses
5902          * that the plane may generate whilst we perform load detection.
5903          * We can not rely on the fbcon either being present (we get called
5904          * during its initialisation to detect all boot displays, or it may
5905          * not even exist) or that it is large enough to satisfy the
5906          * requested mode.
5907          */
5908         fb = mode_fits_in_fbdev(dev, mode);
5909         if (fb == NULL) {
5910                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5911                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5912                 old->release_fb = fb;
5913         } else
5914                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5915         if (IS_ERR(fb)) {
5916                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5917                 goto fail;
5918         }
5919
5920         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5921                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5922                 if (old->release_fb)
5923                         old->release_fb->funcs->destroy(old->release_fb);
5924                 goto fail;
5925         }
5926
5927         /* let the connector get through one full cycle before testing */
5928         intel_wait_for_vblank(dev, intel_crtc->pipe);
5929
5930         return true;
5931 fail:
5932         connector->encoder = NULL;
5933         encoder->crtc = NULL;
5934         return false;
5935 }
5936
5937 void intel_release_load_detect_pipe(struct drm_connector *connector,
5938                                     struct intel_load_detect_pipe *old)
5939 {
5940         struct intel_encoder *intel_encoder =
5941                 intel_attached_encoder(connector);
5942         struct drm_encoder *encoder = &intel_encoder->base;
5943
5944         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5945                       connector->base.id, drm_get_connector_name(connector),
5946                       encoder->base.id, drm_get_encoder_name(encoder));
5947
5948         if (old->load_detect_temp) {
5949                 struct drm_crtc *crtc = encoder->crtc;
5950
5951                 to_intel_connector(connector)->new_encoder = NULL;
5952                 intel_encoder->new_crtc = NULL;
5953                 intel_set_mode(crtc, NULL, 0, 0, NULL);
5954
5955                 if (old->release_fb)
5956                         old->release_fb->funcs->destroy(old->release_fb);
5957
5958                 return;
5959         }
5960
5961         /* Switch crtc and encoder back off if necessary */
5962         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5963                 connector->funcs->dpms(connector, old->dpms_mode);
5964 }
5965
5966 /* Returns the clock of the currently programmed mode of the given pipe. */
5967 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5968 {
5969         struct drm_i915_private *dev_priv = dev->dev_private;
5970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5971         int pipe = intel_crtc->pipe;
5972         u32 dpll = I915_READ(DPLL(pipe));
5973         u32 fp;
5974         intel_clock_t clock;
5975
5976         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5977                 fp = I915_READ(FP0(pipe));
5978         else
5979                 fp = I915_READ(FP1(pipe));
5980
5981         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5982         if (IS_PINEVIEW(dev)) {
5983                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5984                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5985         } else {
5986                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5987                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5988         }
5989
5990         if (!IS_GEN2(dev)) {
5991                 if (IS_PINEVIEW(dev))
5992                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5993                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5994                 else
5995                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5996                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5997
5998                 switch (dpll & DPLL_MODE_MASK) {
5999                 case DPLLB_MODE_DAC_SERIAL:
6000                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6001                                 5 : 10;
6002                         break;
6003                 case DPLLB_MODE_LVDS:
6004                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6005                                 7 : 14;
6006                         break;
6007                 default:
6008                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6009                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6010                         return 0;
6011                 }
6012
6013                 /* XXX: Handle the 100Mhz refclk */
6014                 intel_clock(dev, 96000, &clock);
6015         } else {
6016                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6017
6018                 if (is_lvds) {
6019                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6020                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6021                         clock.p2 = 14;
6022
6023                         if ((dpll & PLL_REF_INPUT_MASK) ==
6024                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6025                                 /* XXX: might not be 66MHz */
6026                                 intel_clock(dev, 66000, &clock);
6027                         } else
6028                                 intel_clock(dev, 48000, &clock);
6029                 } else {
6030                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6031                                 clock.p1 = 2;
6032                         else {
6033                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6034                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6035                         }
6036                         if (dpll & PLL_P2_DIVIDE_BY_4)
6037                                 clock.p2 = 4;
6038                         else
6039                                 clock.p2 = 2;
6040
6041                         intel_clock(dev, 48000, &clock);
6042                 }
6043         }
6044
6045         /* XXX: It would be nice to validate the clocks, but we can't reuse
6046          * i830PllIsValid() because it relies on the xf86_config connector
6047          * configuration being accurate, which it isn't necessarily.
6048          */
6049
6050         return clock.dot;
6051 }
6052
6053 /** Returns the currently programmed mode of the given pipe. */
6054 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6055                                              struct drm_crtc *crtc)
6056 {
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059         int pipe = intel_crtc->pipe;
6060         struct drm_display_mode *mode;
6061         int htot = I915_READ(HTOTAL(pipe));
6062         int hsync = I915_READ(HSYNC(pipe));
6063         int vtot = I915_READ(VTOTAL(pipe));
6064         int vsync = I915_READ(VSYNC(pipe));
6065
6066         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6067         if (!mode)
6068                 return NULL;
6069
6070         mode->clock = intel_crtc_clock_get(dev, crtc);
6071         mode->hdisplay = (htot & 0xffff) + 1;
6072         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6073         mode->hsync_start = (hsync & 0xffff) + 1;
6074         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6075         mode->vdisplay = (vtot & 0xffff) + 1;
6076         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6077         mode->vsync_start = (vsync & 0xffff) + 1;
6078         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6079
6080         drm_mode_set_name(mode);
6081
6082         return mode;
6083 }
6084
6085 static void intel_increase_pllclock(struct drm_crtc *crtc)
6086 {
6087         struct drm_device *dev = crtc->dev;
6088         drm_i915_private_t *dev_priv = dev->dev_private;
6089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090         int pipe = intel_crtc->pipe;
6091         int dpll_reg = DPLL(pipe);
6092         int dpll;
6093
6094         if (HAS_PCH_SPLIT(dev))
6095                 return;
6096
6097         if (!dev_priv->lvds_downclock_avail)
6098                 return;
6099
6100         dpll = I915_READ(dpll_reg);
6101         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6102                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6103
6104                 assert_panel_unlocked(dev_priv, pipe);
6105
6106                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6107                 I915_WRITE(dpll_reg, dpll);
6108                 intel_wait_for_vblank(dev, pipe);
6109
6110                 dpll = I915_READ(dpll_reg);
6111                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6112                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6113         }
6114 }
6115
6116 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6117 {
6118         struct drm_device *dev = crtc->dev;
6119         drm_i915_private_t *dev_priv = dev->dev_private;
6120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6121
6122         if (HAS_PCH_SPLIT(dev))
6123                 return;
6124
6125         if (!dev_priv->lvds_downclock_avail)
6126                 return;
6127
6128         /*
6129          * Since this is called by a timer, we should never get here in
6130          * the manual case.
6131          */
6132         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6133                 int pipe = intel_crtc->pipe;
6134                 int dpll_reg = DPLL(pipe);
6135                 int dpll;
6136
6137                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6138
6139                 assert_panel_unlocked(dev_priv, pipe);
6140
6141                 dpll = I915_READ(dpll_reg);
6142                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6143                 I915_WRITE(dpll_reg, dpll);
6144                 intel_wait_for_vblank(dev, pipe);
6145                 dpll = I915_READ(dpll_reg);
6146                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6147                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6148         }
6149
6150 }
6151
6152 void intel_mark_busy(struct drm_device *dev)
6153 {
6154         i915_update_gfx_val(dev->dev_private);
6155 }
6156
6157 void intel_mark_idle(struct drm_device *dev)
6158 {
6159 }
6160
6161 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6162 {
6163         struct drm_device *dev = obj->base.dev;
6164         struct drm_crtc *crtc;
6165
6166         if (!i915_powersave)
6167                 return;
6168
6169         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6170                 if (!crtc->fb)
6171                         continue;
6172
6173                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6174                         intel_increase_pllclock(crtc);
6175         }
6176 }
6177
6178 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6179 {
6180         struct drm_device *dev = obj->base.dev;
6181         struct drm_crtc *crtc;
6182
6183         if (!i915_powersave)
6184                 return;
6185
6186         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6187                 if (!crtc->fb)
6188                         continue;
6189
6190                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6191                         intel_decrease_pllclock(crtc);
6192         }
6193 }
6194
6195 static void intel_crtc_destroy(struct drm_crtc *crtc)
6196 {
6197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198         struct drm_device *dev = crtc->dev;
6199         struct intel_unpin_work *work;
6200         unsigned long flags;
6201
6202         spin_lock_irqsave(&dev->event_lock, flags);
6203         work = intel_crtc->unpin_work;
6204         intel_crtc->unpin_work = NULL;
6205         spin_unlock_irqrestore(&dev->event_lock, flags);
6206
6207         if (work) {
6208                 cancel_work_sync(&work->work);
6209                 kfree(work);
6210         }
6211
6212         drm_crtc_cleanup(crtc);
6213
6214         kfree(intel_crtc);
6215 }
6216
6217 static void intel_unpin_work_fn(struct work_struct *__work)
6218 {
6219         struct intel_unpin_work *work =
6220                 container_of(__work, struct intel_unpin_work, work);
6221
6222         mutex_lock(&work->dev->struct_mutex);
6223         intel_unpin_fb_obj(work->old_fb_obj);
6224         drm_gem_object_unreference(&work->pending_flip_obj->base);
6225         drm_gem_object_unreference(&work->old_fb_obj->base);
6226
6227         intel_update_fbc(work->dev);
6228         mutex_unlock(&work->dev->struct_mutex);
6229         kfree(work);
6230 }
6231
6232 static void do_intel_finish_page_flip(struct drm_device *dev,
6233                                       struct drm_crtc *crtc)
6234 {
6235         drm_i915_private_t *dev_priv = dev->dev_private;
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         struct intel_unpin_work *work;
6238         struct drm_i915_gem_object *obj;
6239         struct drm_pending_vblank_event *e;
6240         struct timeval tnow, tvbl;
6241         unsigned long flags;
6242
6243         /* Ignore early vblank irqs */
6244         if (intel_crtc == NULL)
6245                 return;
6246
6247         do_gettimeofday(&tnow);
6248
6249         spin_lock_irqsave(&dev->event_lock, flags);
6250         work = intel_crtc->unpin_work;
6251         if (work == NULL || !work->pending) {
6252                 spin_unlock_irqrestore(&dev->event_lock, flags);
6253                 return;
6254         }
6255
6256         intel_crtc->unpin_work = NULL;
6257
6258         if (work->event) {
6259                 e = work->event;
6260                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6261
6262                 /* Called before vblank count and timestamps have
6263                  * been updated for the vblank interval of flip
6264                  * completion? Need to increment vblank count and
6265                  * add one videorefresh duration to returned timestamp
6266                  * to account for this. We assume this happened if we
6267                  * get called over 0.9 frame durations after the last
6268                  * timestamped vblank.
6269                  *
6270                  * This calculation can not be used with vrefresh rates
6271                  * below 5Hz (10Hz to be on the safe side) without
6272                  * promoting to 64 integers.
6273                  */
6274                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6275                     9 * crtc->framedur_ns) {
6276                         e->event.sequence++;
6277                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6278                                              crtc->framedur_ns);
6279                 }
6280
6281                 e->event.tv_sec = tvbl.tv_sec;
6282                 e->event.tv_usec = tvbl.tv_usec;
6283
6284                 list_add_tail(&e->base.link,
6285                               &e->base.file_priv->event_list);
6286                 wake_up_interruptible(&e->base.file_priv->event_wait);
6287         }
6288
6289         drm_vblank_put(dev, intel_crtc->pipe);
6290
6291         spin_unlock_irqrestore(&dev->event_lock, flags);
6292
6293         obj = work->old_fb_obj;
6294
6295         atomic_clear_mask(1 << intel_crtc->plane,
6296                           &obj->pending_flip.counter);
6297         if (atomic_read(&obj->pending_flip) == 0)
6298                 wake_up(&dev_priv->pending_flip_queue);
6299
6300         schedule_work(&work->work);
6301
6302         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6303 }
6304
6305 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6306 {
6307         drm_i915_private_t *dev_priv = dev->dev_private;
6308         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6309
6310         do_intel_finish_page_flip(dev, crtc);
6311 }
6312
6313 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6314 {
6315         drm_i915_private_t *dev_priv = dev->dev_private;
6316         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6317
6318         do_intel_finish_page_flip(dev, crtc);
6319 }
6320
6321 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6322 {
6323         drm_i915_private_t *dev_priv = dev->dev_private;
6324         struct intel_crtc *intel_crtc =
6325                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6326         unsigned long flags;
6327
6328         spin_lock_irqsave(&dev->event_lock, flags);
6329         if (intel_crtc->unpin_work) {
6330                 if ((++intel_crtc->unpin_work->pending) > 1)
6331                         DRM_ERROR("Prepared flip multiple times\n");
6332         } else {
6333                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6334         }
6335         spin_unlock_irqrestore(&dev->event_lock, flags);
6336 }
6337
6338 static int intel_gen2_queue_flip(struct drm_device *dev,
6339                                  struct drm_crtc *crtc,
6340                                  struct drm_framebuffer *fb,
6341                                  struct drm_i915_gem_object *obj)
6342 {
6343         struct drm_i915_private *dev_priv = dev->dev_private;
6344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345         u32 flip_mask;
6346         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6347         int ret;
6348
6349         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6350         if (ret)
6351                 goto err;
6352
6353         ret = intel_ring_begin(ring, 6);
6354         if (ret)
6355                 goto err_unpin;
6356
6357         /* Can't queue multiple flips, so wait for the previous
6358          * one to finish before executing the next.
6359          */
6360         if (intel_crtc->plane)
6361                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6362         else
6363                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6364         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6365         intel_ring_emit(ring, MI_NOOP);
6366         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6367                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6368         intel_ring_emit(ring, fb->pitches[0]);
6369         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6370         intel_ring_emit(ring, 0); /* aux display base address, unused */
6371         intel_ring_advance(ring);
6372         return 0;
6373
6374 err_unpin:
6375         intel_unpin_fb_obj(obj);
6376 err:
6377         return ret;
6378 }
6379
6380 static int intel_gen3_queue_flip(struct drm_device *dev,
6381                                  struct drm_crtc *crtc,
6382                                  struct drm_framebuffer *fb,
6383                                  struct drm_i915_gem_object *obj)
6384 {
6385         struct drm_i915_private *dev_priv = dev->dev_private;
6386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387         u32 flip_mask;
6388         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6389         int ret;
6390
6391         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6392         if (ret)
6393                 goto err;
6394
6395         ret = intel_ring_begin(ring, 6);
6396         if (ret)
6397                 goto err_unpin;
6398
6399         if (intel_crtc->plane)
6400                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6401         else
6402                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6403         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6404         intel_ring_emit(ring, MI_NOOP);
6405         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6406                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6407         intel_ring_emit(ring, fb->pitches[0]);
6408         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6409         intel_ring_emit(ring, MI_NOOP);
6410
6411         intel_ring_advance(ring);
6412         return 0;
6413
6414 err_unpin:
6415         intel_unpin_fb_obj(obj);
6416 err:
6417         return ret;
6418 }
6419
6420 static int intel_gen4_queue_flip(struct drm_device *dev,
6421                                  struct drm_crtc *crtc,
6422                                  struct drm_framebuffer *fb,
6423                                  struct drm_i915_gem_object *obj)
6424 {
6425         struct drm_i915_private *dev_priv = dev->dev_private;
6426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427         uint32_t pf, pipesrc;
6428         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6429         int ret;
6430
6431         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6432         if (ret)
6433                 goto err;
6434
6435         ret = intel_ring_begin(ring, 4);
6436         if (ret)
6437                 goto err_unpin;
6438
6439         /* i965+ uses the linear or tiled offsets from the
6440          * Display Registers (which do not change across a page-flip)
6441          * so we need only reprogram the base address.
6442          */
6443         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6444                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6445         intel_ring_emit(ring, fb->pitches[0]);
6446         intel_ring_emit(ring,
6447                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6448                         obj->tiling_mode);
6449
6450         /* XXX Enabling the panel-fitter across page-flip is so far
6451          * untested on non-native modes, so ignore it for now.
6452          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6453          */
6454         pf = 0;
6455         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6456         intel_ring_emit(ring, pf | pipesrc);
6457         intel_ring_advance(ring);
6458         return 0;
6459
6460 err_unpin:
6461         intel_unpin_fb_obj(obj);
6462 err:
6463         return ret;
6464 }
6465
6466 static int intel_gen6_queue_flip(struct drm_device *dev,
6467                                  struct drm_crtc *crtc,
6468                                  struct drm_framebuffer *fb,
6469                                  struct drm_i915_gem_object *obj)
6470 {
6471         struct drm_i915_private *dev_priv = dev->dev_private;
6472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6474         uint32_t pf, pipesrc;
6475         int ret;
6476
6477         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6478         if (ret)
6479                 goto err;
6480
6481         ret = intel_ring_begin(ring, 4);
6482         if (ret)
6483                 goto err_unpin;
6484
6485         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6486                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6487         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6488         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6489
6490         /* Contrary to the suggestions in the documentation,
6491          * "Enable Panel Fitter" does not seem to be required when page
6492          * flipping with a non-native mode, and worse causes a normal
6493          * modeset to fail.
6494          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6495          */
6496         pf = 0;
6497         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6498         intel_ring_emit(ring, pf | pipesrc);
6499         intel_ring_advance(ring);
6500         return 0;
6501
6502 err_unpin:
6503         intel_unpin_fb_obj(obj);
6504 err:
6505         return ret;
6506 }
6507
6508 /*
6509  * On gen7 we currently use the blit ring because (in early silicon at least)
6510  * the render ring doesn't give us interrpts for page flip completion, which
6511  * means clients will hang after the first flip is queued.  Fortunately the
6512  * blit ring generates interrupts properly, so use it instead.
6513  */
6514 static int intel_gen7_queue_flip(struct drm_device *dev,
6515                                  struct drm_crtc *crtc,
6516                                  struct drm_framebuffer *fb,
6517                                  struct drm_i915_gem_object *obj)
6518 {
6519         struct drm_i915_private *dev_priv = dev->dev_private;
6520         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6521         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6522         uint32_t plane_bit = 0;
6523         int ret;
6524
6525         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6526         if (ret)
6527                 goto err;
6528
6529         switch(intel_crtc->plane) {
6530         case PLANE_A:
6531                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6532                 break;
6533         case PLANE_B:
6534                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6535                 break;
6536         case PLANE_C:
6537                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6538                 break;
6539         default:
6540                 WARN_ONCE(1, "unknown plane in flip command\n");
6541                 ret = -ENODEV;
6542                 goto err_unpin;
6543         }
6544
6545         ret = intel_ring_begin(ring, 4);
6546         if (ret)
6547                 goto err_unpin;
6548
6549         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6550         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6551         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6552         intel_ring_emit(ring, (MI_NOOP));
6553         intel_ring_advance(ring);
6554         return 0;
6555
6556 err_unpin:
6557         intel_unpin_fb_obj(obj);
6558 err:
6559         return ret;
6560 }
6561
6562 static int intel_default_queue_flip(struct drm_device *dev,
6563                                     struct drm_crtc *crtc,
6564                                     struct drm_framebuffer *fb,
6565                                     struct drm_i915_gem_object *obj)
6566 {
6567         return -ENODEV;
6568 }
6569
6570 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6571                                 struct drm_framebuffer *fb,
6572                                 struct drm_pending_vblank_event *event)
6573 {
6574         struct drm_device *dev = crtc->dev;
6575         struct drm_i915_private *dev_priv = dev->dev_private;
6576         struct intel_framebuffer *intel_fb;
6577         struct drm_i915_gem_object *obj;
6578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6579         struct intel_unpin_work *work;
6580         unsigned long flags;
6581         int ret;
6582
6583         /* Can't change pixel format via MI display flips. */
6584         if (fb->pixel_format != crtc->fb->pixel_format)
6585                 return -EINVAL;
6586
6587         /*
6588          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6589          * Note that pitch changes could also affect these register.
6590          */
6591         if (INTEL_INFO(dev)->gen > 3 &&
6592             (fb->offsets[0] != crtc->fb->offsets[0] ||
6593              fb->pitches[0] != crtc->fb->pitches[0]))
6594                 return -EINVAL;
6595
6596         work = kzalloc(sizeof *work, GFP_KERNEL);
6597         if (work == NULL)
6598                 return -ENOMEM;
6599
6600         work->event = event;
6601         work->dev = crtc->dev;
6602         intel_fb = to_intel_framebuffer(crtc->fb);
6603         work->old_fb_obj = intel_fb->obj;
6604         INIT_WORK(&work->work, intel_unpin_work_fn);
6605
6606         ret = drm_vblank_get(dev, intel_crtc->pipe);
6607         if (ret)
6608                 goto free_work;
6609
6610         /* We borrow the event spin lock for protecting unpin_work */
6611         spin_lock_irqsave(&dev->event_lock, flags);
6612         if (intel_crtc->unpin_work) {
6613                 spin_unlock_irqrestore(&dev->event_lock, flags);
6614                 kfree(work);
6615                 drm_vblank_put(dev, intel_crtc->pipe);
6616
6617                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6618                 return -EBUSY;
6619         }
6620         intel_crtc->unpin_work = work;
6621         spin_unlock_irqrestore(&dev->event_lock, flags);
6622
6623         intel_fb = to_intel_framebuffer(fb);
6624         obj = intel_fb->obj;
6625
6626         ret = i915_mutex_lock_interruptible(dev);
6627         if (ret)
6628                 goto cleanup;
6629
6630         /* Reference the objects for the scheduled work. */
6631         drm_gem_object_reference(&work->old_fb_obj->base);
6632         drm_gem_object_reference(&obj->base);
6633
6634         crtc->fb = fb;
6635
6636         work->pending_flip_obj = obj;
6637
6638         work->enable_stall_check = true;
6639
6640         /* Block clients from rendering to the new back buffer until
6641          * the flip occurs and the object is no longer visible.
6642          */
6643         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6644
6645         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6646         if (ret)
6647                 goto cleanup_pending;
6648
6649         intel_disable_fbc(dev);
6650         intel_mark_fb_busy(obj);
6651         mutex_unlock(&dev->struct_mutex);
6652
6653         trace_i915_flip_request(intel_crtc->plane, obj);
6654
6655         return 0;
6656
6657 cleanup_pending:
6658         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6659         drm_gem_object_unreference(&work->old_fb_obj->base);
6660         drm_gem_object_unreference(&obj->base);
6661         mutex_unlock(&dev->struct_mutex);
6662
6663 cleanup:
6664         spin_lock_irqsave(&dev->event_lock, flags);
6665         intel_crtc->unpin_work = NULL;
6666         spin_unlock_irqrestore(&dev->event_lock, flags);
6667
6668         drm_vblank_put(dev, intel_crtc->pipe);
6669 free_work:
6670         kfree(work);
6671
6672         return ret;
6673 }
6674
6675 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6676         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6677         .load_lut = intel_crtc_load_lut,
6678         .disable = intel_crtc_noop,
6679 };
6680
6681 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6682 {
6683         struct intel_encoder *other_encoder;
6684         struct drm_crtc *crtc = &encoder->new_crtc->base;
6685
6686         if (WARN_ON(!crtc))
6687                 return false;
6688
6689         list_for_each_entry(other_encoder,
6690                             &crtc->dev->mode_config.encoder_list,
6691                             base.head) {
6692
6693                 if (&other_encoder->new_crtc->base != crtc ||
6694                     encoder == other_encoder)
6695                         continue;
6696                 else
6697                         return true;
6698         }
6699
6700         return false;
6701 }
6702
6703 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6704                                   struct drm_crtc *crtc)
6705 {
6706         struct drm_device *dev;
6707         struct drm_crtc *tmp;
6708         int crtc_mask = 1;
6709
6710         WARN(!crtc, "checking null crtc?\n");
6711
6712         dev = crtc->dev;
6713
6714         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6715                 if (tmp == crtc)
6716                         break;
6717                 crtc_mask <<= 1;
6718         }
6719
6720         if (encoder->possible_crtcs & crtc_mask)
6721                 return true;
6722         return false;
6723 }
6724
6725 /**
6726  * intel_modeset_update_staged_output_state
6727  *
6728  * Updates the staged output configuration state, e.g. after we've read out the
6729  * current hw state.
6730  */
6731 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6732 {
6733         struct intel_encoder *encoder;
6734         struct intel_connector *connector;
6735
6736         list_for_each_entry(connector, &dev->mode_config.connector_list,
6737                             base.head) {
6738                 connector->new_encoder =
6739                         to_intel_encoder(connector->base.encoder);
6740         }
6741
6742         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6743                             base.head) {
6744                 encoder->new_crtc =
6745                         to_intel_crtc(encoder->base.crtc);
6746         }
6747 }
6748
6749 /**
6750  * intel_modeset_commit_output_state
6751  *
6752  * This function copies the stage display pipe configuration to the real one.
6753  */
6754 static void intel_modeset_commit_output_state(struct drm_device *dev)
6755 {
6756         struct intel_encoder *encoder;
6757         struct intel_connector *connector;
6758
6759         list_for_each_entry(connector, &dev->mode_config.connector_list,
6760                             base.head) {
6761                 connector->base.encoder = &connector->new_encoder->base;
6762         }
6763
6764         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6765                             base.head) {
6766                 encoder->base.crtc = &encoder->new_crtc->base;
6767         }
6768 }
6769
6770 static struct drm_display_mode *
6771 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6772                             struct drm_display_mode *mode)
6773 {
6774         struct drm_device *dev = crtc->dev;
6775         struct drm_display_mode *adjusted_mode;
6776         struct drm_encoder_helper_funcs *encoder_funcs;
6777         struct intel_encoder *encoder;
6778
6779         adjusted_mode = drm_mode_duplicate(dev, mode);
6780         if (!adjusted_mode)
6781                 return ERR_PTR(-ENOMEM);
6782
6783         /* Pass our mode to the connectors and the CRTC to give them a chance to
6784          * adjust it according to limitations or connector properties, and also
6785          * a chance to reject the mode entirely.
6786          */
6787         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6788                             base.head) {
6789
6790                 if (&encoder->new_crtc->base != crtc)
6791                         continue;
6792                 encoder_funcs = encoder->base.helper_private;
6793                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6794                                                 adjusted_mode))) {
6795                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6796                         goto fail;
6797                 }
6798         }
6799
6800         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6801                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6802                 goto fail;
6803         }
6804         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6805
6806         return adjusted_mode;
6807 fail:
6808         drm_mode_destroy(dev, adjusted_mode);
6809         return ERR_PTR(-EINVAL);
6810 }
6811
6812 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6813  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6814 static void
6815 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6816                              unsigned *prepare_pipes, unsigned *disable_pipes)
6817 {
6818         struct intel_crtc *intel_crtc;
6819         struct drm_device *dev = crtc->dev;
6820         struct intel_encoder *encoder;
6821         struct intel_connector *connector;
6822         struct drm_crtc *tmp_crtc;
6823
6824         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6825
6826         /* Check which crtcs have changed outputs connected to them, these need
6827          * to be part of the prepare_pipes mask. We don't (yet) support global
6828          * modeset across multiple crtcs, so modeset_pipes will only have one
6829          * bit set at most. */
6830         list_for_each_entry(connector, &dev->mode_config.connector_list,
6831                             base.head) {
6832                 if (connector->base.encoder == &connector->new_encoder->base)
6833                         continue;
6834
6835                 if (connector->base.encoder) {
6836                         tmp_crtc = connector->base.encoder->crtc;
6837
6838                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6839                 }
6840
6841                 if (connector->new_encoder)
6842                         *prepare_pipes |=
6843                                 1 << connector->new_encoder->new_crtc->pipe;
6844         }
6845
6846         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6847                             base.head) {
6848                 if (encoder->base.crtc == &encoder->new_crtc->base)
6849                         continue;
6850
6851                 if (encoder->base.crtc) {
6852                         tmp_crtc = encoder->base.crtc;
6853
6854                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6855                 }
6856
6857                 if (encoder->new_crtc)
6858                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6859         }
6860
6861         /* Check for any pipes that will be fully disabled ... */
6862         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6863                             base.head) {
6864                 bool used = false;
6865
6866                 /* Don't try to disable disabled crtcs. */
6867                 if (!intel_crtc->base.enabled)
6868                         continue;
6869
6870                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6871                                     base.head) {
6872                         if (encoder->new_crtc == intel_crtc)
6873                                 used = true;
6874                 }
6875
6876                 if (!used)
6877                         *disable_pipes |= 1 << intel_crtc->pipe;
6878         }
6879
6880
6881         /* set_mode is also used to update properties on life display pipes. */
6882         intel_crtc = to_intel_crtc(crtc);
6883         if (crtc->enabled)
6884                 *prepare_pipes |= 1 << intel_crtc->pipe;
6885
6886         /* We only support modeset on one single crtc, hence we need to do that
6887          * only for the passed in crtc iff we change anything else than just
6888          * disable crtcs.
6889          *
6890          * This is actually not true, to be fully compatible with the old crtc
6891          * helper we automatically disable _any_ output (i.e. doesn't need to be
6892          * connected to the crtc we're modesetting on) if it's disconnected.
6893          * Which is a rather nutty api (since changed the output configuration
6894          * without userspace's explicit request can lead to confusion), but
6895          * alas. Hence we currently need to modeset on all pipes we prepare. */
6896         if (*prepare_pipes)
6897                 *modeset_pipes = *prepare_pipes;
6898
6899         /* ... and mask these out. */
6900         *modeset_pipes &= ~(*disable_pipes);
6901         *prepare_pipes &= ~(*disable_pipes);
6902 }
6903
6904 static bool intel_crtc_in_use(struct drm_crtc *crtc)
6905 {
6906         struct drm_encoder *encoder;
6907         struct drm_device *dev = crtc->dev;
6908
6909         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6910                 if (encoder->crtc == crtc)
6911                         return true;
6912
6913         return false;
6914 }
6915
6916 static void
6917 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6918 {
6919         struct intel_encoder *intel_encoder;
6920         struct intel_crtc *intel_crtc;
6921         struct drm_connector *connector;
6922
6923         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6924                             base.head) {
6925                 if (!intel_encoder->base.crtc)
6926                         continue;
6927
6928                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6929
6930                 if (prepare_pipes & (1 << intel_crtc->pipe))
6931                         intel_encoder->connectors_active = false;
6932         }
6933
6934         intel_modeset_commit_output_state(dev);
6935
6936         /* Update computed state. */
6937         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6938                             base.head) {
6939                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6940         }
6941
6942         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6943                 if (!connector->encoder || !connector->encoder->crtc)
6944                         continue;
6945
6946                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6947
6948                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6949                         struct drm_property *dpms_property =
6950                                 dev->mode_config.dpms_property;
6951
6952                         connector->dpms = DRM_MODE_DPMS_ON;
6953                         drm_connector_property_set_value(connector,
6954                                                          dpms_property,
6955                                                          DRM_MODE_DPMS_ON);
6956
6957                         intel_encoder = to_intel_encoder(connector->encoder);
6958                         intel_encoder->connectors_active = true;
6959                 }
6960         }
6961
6962 }
6963
6964 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6965         list_for_each_entry((intel_crtc), \
6966                             &(dev)->mode_config.crtc_list, \
6967                             base.head) \
6968                 if (mask & (1 <<(intel_crtc)->pipe)) \
6969
6970 void
6971 intel_modeset_check_state(struct drm_device *dev)
6972 {
6973         struct intel_crtc *crtc;
6974         struct intel_encoder *encoder;
6975         struct intel_connector *connector;
6976
6977         list_for_each_entry(connector, &dev->mode_config.connector_list,
6978                             base.head) {
6979                 /* This also checks the encoder/connector hw state with the
6980                  * ->get_hw_state callbacks. */
6981                 intel_connector_check_state(connector);
6982
6983                 WARN(&connector->new_encoder->base != connector->base.encoder,
6984                      "connector's staged encoder doesn't match current encoder\n");
6985         }
6986
6987         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6988                             base.head) {
6989                 bool enabled = false;
6990                 bool active = false;
6991                 enum pipe pipe, tracked_pipe;
6992
6993                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
6994                               encoder->base.base.id,
6995                               drm_get_encoder_name(&encoder->base));
6996
6997                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
6998                      "encoder's stage crtc doesn't match current crtc\n");
6999                 WARN(encoder->connectors_active && !encoder->base.crtc,
7000                      "encoder's active_connectors set, but no crtc\n");
7001
7002                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7003                                     base.head) {
7004                         if (connector->base.encoder != &encoder->base)
7005                                 continue;
7006                         enabled = true;
7007                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7008                                 active = true;
7009                 }
7010                 WARN(!!encoder->base.crtc != enabled,
7011                      "encoder's enabled state mismatch "
7012                      "(expected %i, found %i)\n",
7013                      !!encoder->base.crtc, enabled);
7014                 WARN(active && !encoder->base.crtc,
7015                      "active encoder with no crtc\n");
7016
7017                 WARN(encoder->connectors_active != active,
7018                      "encoder's computed active state doesn't match tracked active state "
7019                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7020
7021                 active = encoder->get_hw_state(encoder, &pipe);
7022                 WARN(active != encoder->connectors_active,
7023                      "encoder's hw state doesn't match sw tracking "
7024                      "(expected %i, found %i)\n",
7025                      encoder->connectors_active, active);
7026
7027                 if (!encoder->base.crtc)
7028                         continue;
7029
7030                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7031                 WARN(active && pipe != tracked_pipe,
7032                      "active encoder's pipe doesn't match"
7033                      "(expected %i, found %i)\n",
7034                      tracked_pipe, pipe);
7035
7036         }
7037
7038         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7039                             base.head) {
7040                 bool enabled = false;
7041                 bool active = false;
7042
7043                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7044                               crtc->base.base.id);
7045
7046                 WARN(crtc->active && !crtc->base.enabled,
7047                      "active crtc, but not enabled in sw tracking\n");
7048
7049                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7050                                     base.head) {
7051                         if (encoder->base.crtc != &crtc->base)
7052                                 continue;
7053                         enabled = true;
7054                         if (encoder->connectors_active)
7055                                 active = true;
7056                 }
7057                 WARN(active != crtc->active,
7058                      "crtc's computed active state doesn't match tracked active state "
7059                      "(expected %i, found %i)\n", active, crtc->active);
7060                 WARN(enabled != crtc->base.enabled,
7061                      "crtc's computed enabled state doesn't match tracked enabled state "
7062                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7063
7064                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7065         }
7066 }
7067
7068 bool intel_set_mode(struct drm_crtc *crtc,
7069                     struct drm_display_mode *mode,
7070                     int x, int y, struct drm_framebuffer *fb)
7071 {
7072         struct drm_device *dev = crtc->dev;
7073         drm_i915_private_t *dev_priv = dev->dev_private;
7074         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7075         struct drm_encoder_helper_funcs *encoder_funcs;
7076         struct drm_encoder *encoder;
7077         struct intel_crtc *intel_crtc;
7078         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7079         bool ret = true;
7080
7081         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7082                                      &prepare_pipes, &disable_pipes);
7083
7084         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7085                       modeset_pipes, prepare_pipes, disable_pipes);
7086
7087         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7088                 intel_crtc_disable(&intel_crtc->base);
7089
7090         saved_hwmode = crtc->hwmode;
7091         saved_mode = crtc->mode;
7092
7093         /* Hack: Because we don't (yet) support global modeset on multiple
7094          * crtcs, we don't keep track of the new mode for more than one crtc.
7095          * Hence simply check whether any bit is set in modeset_pipes in all the
7096          * pieces of code that are not yet converted to deal with mutliple crtcs
7097          * changing their mode at the same time. */
7098         adjusted_mode = NULL;
7099         if (modeset_pipes) {
7100                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7101                 if (IS_ERR(adjusted_mode)) {
7102                         return false;
7103                 }
7104         }
7105
7106         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7107                 if (intel_crtc->base.enabled)
7108                         dev_priv->display.crtc_disable(&intel_crtc->base);
7109         }
7110
7111         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7112          * to set it here already despite that we pass it down the callchain.
7113          */
7114         if (modeset_pipes)
7115                 crtc->mode = *mode;
7116
7117         /* Only after disabling all output pipelines that will be changed can we
7118          * update the the output configuration. */
7119         intel_modeset_update_state(dev, prepare_pipes);
7120
7121         /* Set up the DPLL and any encoders state that needs to adjust or depend
7122          * on the DPLL.
7123          */
7124         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7125                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7126                                            mode, adjusted_mode,
7127                                            x, y, fb);
7128                 if (!ret)
7129                     goto done;
7130
7131                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7132
7133                         if (encoder->crtc != &intel_crtc->base)
7134                                 continue;
7135
7136                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7137                                 encoder->base.id, drm_get_encoder_name(encoder),
7138                                 mode->base.id, mode->name);
7139                         encoder_funcs = encoder->helper_private;
7140                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7141                 }
7142         }
7143
7144         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7145         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7146                 dev_priv->display.crtc_enable(&intel_crtc->base);
7147
7148         if (modeset_pipes) {
7149                 /* Store real post-adjustment hardware mode. */
7150                 crtc->hwmode = *adjusted_mode;
7151
7152                 /* Calculate and store various constants which
7153                  * are later needed by vblank and swap-completion
7154                  * timestamping. They are derived from true hwmode.
7155                  */
7156                 drm_calc_timestamping_constants(crtc);
7157         }
7158
7159         /* FIXME: add subpixel order */
7160 done:
7161         drm_mode_destroy(dev, adjusted_mode);
7162         if (!ret && crtc->enabled) {
7163                 crtc->hwmode = saved_hwmode;
7164                 crtc->mode = saved_mode;
7165         } else {
7166                 intel_modeset_check_state(dev);
7167         }
7168
7169         return ret;
7170 }
7171
7172 #undef for_each_intel_crtc_masked
7173
7174 static void intel_set_config_free(struct intel_set_config *config)
7175 {
7176         if (!config)
7177                 return;
7178
7179         kfree(config->save_connector_encoders);
7180         kfree(config->save_encoder_crtcs);
7181         kfree(config);
7182 }
7183
7184 static int intel_set_config_save_state(struct drm_device *dev,
7185                                        struct intel_set_config *config)
7186 {
7187         struct drm_encoder *encoder;
7188         struct drm_connector *connector;
7189         int count;
7190
7191         config->save_encoder_crtcs =
7192                 kcalloc(dev->mode_config.num_encoder,
7193                         sizeof(struct drm_crtc *), GFP_KERNEL);
7194         if (!config->save_encoder_crtcs)
7195                 return -ENOMEM;
7196
7197         config->save_connector_encoders =
7198                 kcalloc(dev->mode_config.num_connector,
7199                         sizeof(struct drm_encoder *), GFP_KERNEL);
7200         if (!config->save_connector_encoders)
7201                 return -ENOMEM;
7202
7203         /* Copy data. Note that driver private data is not affected.
7204          * Should anything bad happen only the expected state is
7205          * restored, not the drivers personal bookkeeping.
7206          */
7207         count = 0;
7208         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7209                 config->save_encoder_crtcs[count++] = encoder->crtc;
7210         }
7211
7212         count = 0;
7213         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7214                 config->save_connector_encoders[count++] = connector->encoder;
7215         }
7216
7217         return 0;
7218 }
7219
7220 static void intel_set_config_restore_state(struct drm_device *dev,
7221                                            struct intel_set_config *config)
7222 {
7223         struct intel_encoder *encoder;
7224         struct intel_connector *connector;
7225         int count;
7226
7227         count = 0;
7228         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7229                 encoder->new_crtc =
7230                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7231         }
7232
7233         count = 0;
7234         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7235                 connector->new_encoder =
7236                         to_intel_encoder(config->save_connector_encoders[count++]);
7237         }
7238 }
7239
7240 static void
7241 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7242                                       struct intel_set_config *config)
7243 {
7244
7245         /* We should be able to check here if the fb has the same properties
7246          * and then just flip_or_move it */
7247         if (set->crtc->fb != set->fb) {
7248                 /* If we have no fb then treat it as a full mode set */
7249                 if (set->crtc->fb == NULL) {
7250                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7251                         config->mode_changed = true;
7252                 } else if (set->fb == NULL) {
7253                         config->mode_changed = true;
7254                 } else if (set->fb->depth != set->crtc->fb->depth) {
7255                         config->mode_changed = true;
7256                 } else if (set->fb->bits_per_pixel !=
7257                            set->crtc->fb->bits_per_pixel) {
7258                         config->mode_changed = true;
7259                 } else
7260                         config->fb_changed = true;
7261         }
7262
7263         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7264                 config->fb_changed = true;
7265
7266         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7267                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7268                 drm_mode_debug_printmodeline(&set->crtc->mode);
7269                 drm_mode_debug_printmodeline(set->mode);
7270                 config->mode_changed = true;
7271         }
7272 }
7273
7274 static int
7275 intel_modeset_stage_output_state(struct drm_device *dev,
7276                                  struct drm_mode_set *set,
7277                                  struct intel_set_config *config)
7278 {
7279         struct drm_crtc *new_crtc;
7280         struct intel_connector *connector;
7281         struct intel_encoder *encoder;
7282         int count, ro;
7283
7284         /* The upper layers ensure that we either disabl a crtc or have a list
7285          * of connectors. For paranoia, double-check this. */
7286         WARN_ON(!set->fb && (set->num_connectors != 0));
7287         WARN_ON(set->fb && (set->num_connectors == 0));
7288
7289         count = 0;
7290         list_for_each_entry(connector, &dev->mode_config.connector_list,
7291                             base.head) {
7292                 /* Otherwise traverse passed in connector list and get encoders
7293                  * for them. */
7294                 for (ro = 0; ro < set->num_connectors; ro++) {
7295                         if (set->connectors[ro] == &connector->base) {
7296                                 connector->new_encoder = connector->encoder;
7297                                 break;
7298                         }
7299                 }
7300
7301                 /* If we disable the crtc, disable all its connectors. Also, if
7302                  * the connector is on the changing crtc but not on the new
7303                  * connector list, disable it. */
7304                 if ((!set->fb || ro == set->num_connectors) &&
7305                     connector->base.encoder &&
7306                     connector->base.encoder->crtc == set->crtc) {
7307                         connector->new_encoder = NULL;
7308
7309                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7310                                 connector->base.base.id,
7311                                 drm_get_connector_name(&connector->base));
7312                 }
7313
7314
7315                 if (&connector->new_encoder->base != connector->base.encoder) {
7316                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7317                         config->mode_changed = true;
7318                 }
7319
7320                 /* Disable all disconnected encoders. */
7321                 if (connector->base.status == connector_status_disconnected)
7322                         connector->new_encoder = NULL;
7323         }
7324         /* connector->new_encoder is now updated for all connectors. */
7325
7326         /* Update crtc of enabled connectors. */
7327         count = 0;
7328         list_for_each_entry(connector, &dev->mode_config.connector_list,
7329                             base.head) {
7330                 if (!connector->new_encoder)
7331                         continue;
7332
7333                 new_crtc = connector->new_encoder->base.crtc;
7334
7335                 for (ro = 0; ro < set->num_connectors; ro++) {
7336                         if (set->connectors[ro] == &connector->base)
7337                                 new_crtc = set->crtc;
7338                 }
7339
7340                 /* Make sure the new CRTC will work with the encoder */
7341                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7342                                            new_crtc)) {
7343                         return -EINVAL;
7344                 }
7345                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7346
7347                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7348                         connector->base.base.id,
7349                         drm_get_connector_name(&connector->base),
7350                         new_crtc->base.id);
7351         }
7352
7353         /* Check for any encoders that needs to be disabled. */
7354         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7355                             base.head) {
7356                 list_for_each_entry(connector,
7357                                     &dev->mode_config.connector_list,
7358                                     base.head) {
7359                         if (connector->new_encoder == encoder) {
7360                                 WARN_ON(!connector->new_encoder->new_crtc);
7361
7362                                 goto next_encoder;
7363                         }
7364                 }
7365                 encoder->new_crtc = NULL;
7366 next_encoder:
7367                 /* Only now check for crtc changes so we don't miss encoders
7368                  * that will be disabled. */
7369                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7370                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7371                         config->mode_changed = true;
7372                 }
7373         }
7374         /* Now we've also updated encoder->new_crtc for all encoders. */
7375
7376         return 0;
7377 }
7378
7379 static int intel_crtc_set_config(struct drm_mode_set *set)
7380 {
7381         struct drm_device *dev;
7382         struct drm_mode_set save_set;
7383         struct intel_set_config *config;
7384         int ret;
7385
7386         BUG_ON(!set);
7387         BUG_ON(!set->crtc);
7388         BUG_ON(!set->crtc->helper_private);
7389
7390         if (!set->mode)
7391                 set->fb = NULL;
7392
7393         /* The fb helper likes to play gross jokes with ->mode_set_config.
7394          * Unfortunately the crtc helper doesn't do much at all for this case,
7395          * so we have to cope with this madness until the fb helper is fixed up. */
7396         if (set->fb && set->num_connectors == 0)
7397                 return 0;
7398
7399         if (set->fb) {
7400                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7401                                 set->crtc->base.id, set->fb->base.id,
7402                                 (int)set->num_connectors, set->x, set->y);
7403         } else {
7404                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7405         }
7406
7407         dev = set->crtc->dev;
7408
7409         ret = -ENOMEM;
7410         config = kzalloc(sizeof(*config), GFP_KERNEL);
7411         if (!config)
7412                 goto out_config;
7413
7414         ret = intel_set_config_save_state(dev, config);
7415         if (ret)
7416                 goto out_config;
7417
7418         save_set.crtc = set->crtc;
7419         save_set.mode = &set->crtc->mode;
7420         save_set.x = set->crtc->x;
7421         save_set.y = set->crtc->y;
7422         save_set.fb = set->crtc->fb;
7423
7424         /* Compute whether we need a full modeset, only an fb base update or no
7425          * change at all. In the future we might also check whether only the
7426          * mode changed, e.g. for LVDS where we only change the panel fitter in
7427          * such cases. */
7428         intel_set_config_compute_mode_changes(set, config);
7429
7430         ret = intel_modeset_stage_output_state(dev, set, config);
7431         if (ret)
7432                 goto fail;
7433
7434         if (config->mode_changed) {
7435                 if (set->mode) {
7436                         DRM_DEBUG_KMS("attempting to set mode from"
7437                                         " userspace\n");
7438                         drm_mode_debug_printmodeline(set->mode);
7439                 }
7440
7441                 if (!intel_set_mode(set->crtc, set->mode,
7442                                     set->x, set->y, set->fb)) {
7443                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7444                                   set->crtc->base.id);
7445                         ret = -EINVAL;
7446                         goto fail;
7447                 }
7448         } else if (config->fb_changed) {
7449                 ret = intel_pipe_set_base(set->crtc,
7450                                           set->x, set->y, set->fb);
7451         }
7452
7453         intel_set_config_free(config);
7454
7455         return 0;
7456
7457 fail:
7458         intel_set_config_restore_state(dev, config);
7459
7460         /* Try to restore the config */
7461         if (config->mode_changed &&
7462             !intel_set_mode(save_set.crtc, save_set.mode,
7463                             save_set.x, save_set.y, save_set.fb))
7464                 DRM_ERROR("failed to restore config after modeset failure\n");
7465
7466 out_config:
7467         intel_set_config_free(config);
7468         return ret;
7469 }
7470
7471 static const struct drm_crtc_funcs intel_crtc_funcs = {
7472         .cursor_set = intel_crtc_cursor_set,
7473         .cursor_move = intel_crtc_cursor_move,
7474         .gamma_set = intel_crtc_gamma_set,
7475         .set_config = intel_crtc_set_config,
7476         .destroy = intel_crtc_destroy,
7477         .page_flip = intel_crtc_page_flip,
7478 };
7479
7480 static void intel_pch_pll_init(struct drm_device *dev)
7481 {
7482         drm_i915_private_t *dev_priv = dev->dev_private;
7483         int i;
7484
7485         if (dev_priv->num_pch_pll == 0) {
7486                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7487                 return;
7488         }
7489
7490         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7491                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7492                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7493                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7494         }
7495 }
7496
7497 static void intel_crtc_init(struct drm_device *dev, int pipe)
7498 {
7499         drm_i915_private_t *dev_priv = dev->dev_private;
7500         struct intel_crtc *intel_crtc;
7501         int i;
7502
7503         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7504         if (intel_crtc == NULL)
7505                 return;
7506
7507         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7508
7509         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7510         for (i = 0; i < 256; i++) {
7511                 intel_crtc->lut_r[i] = i;
7512                 intel_crtc->lut_g[i] = i;
7513                 intel_crtc->lut_b[i] = i;
7514         }
7515
7516         /* Swap pipes & planes for FBC on pre-965 */
7517         intel_crtc->pipe = pipe;
7518         intel_crtc->plane = pipe;
7519         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7520                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7521                 intel_crtc->plane = !pipe;
7522         }
7523
7524         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7525                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7526         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7527         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7528
7529         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7530
7531         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7532 }
7533
7534 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7535                                 struct drm_file *file)
7536 {
7537         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7538         struct drm_mode_object *drmmode_obj;
7539         struct intel_crtc *crtc;
7540
7541         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7542                 return -ENODEV;
7543
7544         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7545                         DRM_MODE_OBJECT_CRTC);
7546
7547         if (!drmmode_obj) {
7548                 DRM_ERROR("no such CRTC id\n");
7549                 return -EINVAL;
7550         }
7551
7552         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7553         pipe_from_crtc_id->pipe = crtc->pipe;
7554
7555         return 0;
7556 }
7557
7558 static int intel_encoder_clones(struct intel_encoder *encoder)
7559 {
7560         struct drm_device *dev = encoder->base.dev;
7561         struct intel_encoder *source_encoder;
7562         int index_mask = 0;
7563         int entry = 0;
7564
7565         list_for_each_entry(source_encoder,
7566                             &dev->mode_config.encoder_list, base.head) {
7567
7568                 if (encoder == source_encoder)
7569                         index_mask |= (1 << entry);
7570
7571                 /* Intel hw has only one MUX where enocoders could be cloned. */
7572                 if (encoder->cloneable && source_encoder->cloneable)
7573                         index_mask |= (1 << entry);
7574
7575                 entry++;
7576         }
7577
7578         return index_mask;
7579 }
7580
7581 static bool has_edp_a(struct drm_device *dev)
7582 {
7583         struct drm_i915_private *dev_priv = dev->dev_private;
7584
7585         if (!IS_MOBILE(dev))
7586                 return false;
7587
7588         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7589                 return false;
7590
7591         if (IS_GEN5(dev) &&
7592             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7593                 return false;
7594
7595         return true;
7596 }
7597
7598 static void intel_setup_outputs(struct drm_device *dev)
7599 {
7600         struct drm_i915_private *dev_priv = dev->dev_private;
7601         struct intel_encoder *encoder;
7602         bool dpd_is_edp = false;
7603         bool has_lvds;
7604
7605         has_lvds = intel_lvds_init(dev);
7606         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7607                 /* disable the panel fitter on everything but LVDS */
7608                 I915_WRITE(PFIT_CONTROL, 0);
7609         }
7610
7611         if (HAS_PCH_SPLIT(dev)) {
7612                 dpd_is_edp = intel_dpd_is_edp(dev);
7613
7614                 if (has_edp_a(dev))
7615                         intel_dp_init(dev, DP_A, PORT_A);
7616
7617                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7618                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7619         }
7620
7621         intel_crt_init(dev);
7622
7623         if (IS_HASWELL(dev)) {
7624                 int found;
7625
7626                 /* Haswell uses DDI functions to detect digital outputs */
7627                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7628                 /* DDI A only supports eDP */
7629                 if (found)
7630                         intel_ddi_init(dev, PORT_A);
7631
7632                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7633                  * register */
7634                 found = I915_READ(SFUSE_STRAP);
7635
7636                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7637                         intel_ddi_init(dev, PORT_B);
7638                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7639                         intel_ddi_init(dev, PORT_C);
7640                 if (found & SFUSE_STRAP_DDID_DETECTED)
7641                         intel_ddi_init(dev, PORT_D);
7642         } else if (HAS_PCH_SPLIT(dev)) {
7643                 int found;
7644
7645                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7646                         /* PCH SDVOB multiplex with HDMIB */
7647                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7648                         if (!found)
7649                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7650                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7651                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7652                 }
7653
7654                 if (I915_READ(HDMIC) & PORT_DETECTED)
7655                         intel_hdmi_init(dev, HDMIC, PORT_C);
7656
7657                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7658                         intel_hdmi_init(dev, HDMID, PORT_D);
7659
7660                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7661                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7662
7663                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7664                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7665         } else if (IS_VALLEYVIEW(dev)) {
7666                 int found;
7667
7668                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7669                 if (I915_READ(DP_C) & DP_DETECTED)
7670                         intel_dp_init(dev, DP_C, PORT_C);
7671
7672                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7673                         /* SDVOB multiplex with HDMIB */
7674                         found = intel_sdvo_init(dev, SDVOB, true);
7675                         if (!found)
7676                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7677                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7678                                 intel_dp_init(dev, DP_B, PORT_B);
7679                 }
7680
7681                 if (I915_READ(SDVOC) & PORT_DETECTED)
7682                         intel_hdmi_init(dev, SDVOC, PORT_C);
7683
7684         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7685                 bool found = false;
7686
7687                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7688                         DRM_DEBUG_KMS("probing SDVOB\n");
7689                         found = intel_sdvo_init(dev, SDVOB, true);
7690                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7691                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7692                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7693                         }
7694
7695                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7696                                 DRM_DEBUG_KMS("probing DP_B\n");
7697                                 intel_dp_init(dev, DP_B, PORT_B);
7698                         }
7699                 }
7700
7701                 /* Before G4X SDVOC doesn't have its own detect register */
7702
7703                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7704                         DRM_DEBUG_KMS("probing SDVOC\n");
7705                         found = intel_sdvo_init(dev, SDVOC, false);
7706                 }
7707
7708                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7709
7710                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7711                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7712                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7713                         }
7714                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7715                                 DRM_DEBUG_KMS("probing DP_C\n");
7716                                 intel_dp_init(dev, DP_C, PORT_C);
7717                         }
7718                 }
7719
7720                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7721                     (I915_READ(DP_D) & DP_DETECTED)) {
7722                         DRM_DEBUG_KMS("probing DP_D\n");
7723                         intel_dp_init(dev, DP_D, PORT_D);
7724                 }
7725         } else if (IS_GEN2(dev))
7726                 intel_dvo_init(dev);
7727
7728         if (SUPPORTS_TV(dev))
7729                 intel_tv_init(dev);
7730
7731         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7732                 encoder->base.possible_crtcs = encoder->crtc_mask;
7733                 encoder->base.possible_clones =
7734                         intel_encoder_clones(encoder);
7735         }
7736
7737         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7738                 ironlake_init_pch_refclk(dev);
7739 }
7740
7741 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7742 {
7743         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7744
7745         drm_framebuffer_cleanup(fb);
7746         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7747
7748         kfree(intel_fb);
7749 }
7750
7751 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7752                                                 struct drm_file *file,
7753                                                 unsigned int *handle)
7754 {
7755         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7756         struct drm_i915_gem_object *obj = intel_fb->obj;
7757
7758         return drm_gem_handle_create(file, &obj->base, handle);
7759 }
7760
7761 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7762         .destroy = intel_user_framebuffer_destroy,
7763         .create_handle = intel_user_framebuffer_create_handle,
7764 };
7765
7766 int intel_framebuffer_init(struct drm_device *dev,
7767                            struct intel_framebuffer *intel_fb,
7768                            struct drm_mode_fb_cmd2 *mode_cmd,
7769                            struct drm_i915_gem_object *obj)
7770 {
7771         int ret;
7772
7773         if (obj->tiling_mode == I915_TILING_Y)
7774                 return -EINVAL;
7775
7776         if (mode_cmd->pitches[0] & 63)
7777                 return -EINVAL;
7778
7779         switch (mode_cmd->pixel_format) {
7780         case DRM_FORMAT_RGB332:
7781         case DRM_FORMAT_RGB565:
7782         case DRM_FORMAT_XRGB8888:
7783         case DRM_FORMAT_XBGR8888:
7784         case DRM_FORMAT_ARGB8888:
7785         case DRM_FORMAT_XRGB2101010:
7786         case DRM_FORMAT_ARGB2101010:
7787                 /* RGB formats are common across chipsets */
7788                 break;
7789         case DRM_FORMAT_YUYV:
7790         case DRM_FORMAT_UYVY:
7791         case DRM_FORMAT_YVYU:
7792         case DRM_FORMAT_VYUY:
7793                 break;
7794         default:
7795                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7796                                 mode_cmd->pixel_format);
7797                 return -EINVAL;
7798         }
7799
7800         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7801         if (ret) {
7802                 DRM_ERROR("framebuffer init failed %d\n", ret);
7803                 return ret;
7804         }
7805
7806         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7807         intel_fb->obj = obj;
7808         return 0;
7809 }
7810
7811 static struct drm_framebuffer *
7812 intel_user_framebuffer_create(struct drm_device *dev,
7813                               struct drm_file *filp,
7814                               struct drm_mode_fb_cmd2 *mode_cmd)
7815 {
7816         struct drm_i915_gem_object *obj;
7817
7818         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7819                                                 mode_cmd->handles[0]));
7820         if (&obj->base == NULL)
7821                 return ERR_PTR(-ENOENT);
7822
7823         return intel_framebuffer_create(dev, mode_cmd, obj);
7824 }
7825
7826 static const struct drm_mode_config_funcs intel_mode_funcs = {
7827         .fb_create = intel_user_framebuffer_create,
7828         .output_poll_changed = intel_fb_output_poll_changed,
7829 };
7830
7831 /* Set up chip specific display functions */
7832 static void intel_init_display(struct drm_device *dev)
7833 {
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835
7836         /* We always want a DPMS function */
7837         if (HAS_PCH_SPLIT(dev)) {
7838                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7839                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7840                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7841                 dev_priv->display.off = ironlake_crtc_off;
7842                 dev_priv->display.update_plane = ironlake_update_plane;
7843         } else {
7844                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7845                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7846                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7847                 dev_priv->display.off = i9xx_crtc_off;
7848                 dev_priv->display.update_plane = i9xx_update_plane;
7849         }
7850
7851         /* Returns the core display clock speed */
7852         if (IS_VALLEYVIEW(dev))
7853                 dev_priv->display.get_display_clock_speed =
7854                         valleyview_get_display_clock_speed;
7855         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7856                 dev_priv->display.get_display_clock_speed =
7857                         i945_get_display_clock_speed;
7858         else if (IS_I915G(dev))
7859                 dev_priv->display.get_display_clock_speed =
7860                         i915_get_display_clock_speed;
7861         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7862                 dev_priv->display.get_display_clock_speed =
7863                         i9xx_misc_get_display_clock_speed;
7864         else if (IS_I915GM(dev))
7865                 dev_priv->display.get_display_clock_speed =
7866                         i915gm_get_display_clock_speed;
7867         else if (IS_I865G(dev))
7868                 dev_priv->display.get_display_clock_speed =
7869                         i865_get_display_clock_speed;
7870         else if (IS_I85X(dev))
7871                 dev_priv->display.get_display_clock_speed =
7872                         i855_get_display_clock_speed;
7873         else /* 852, 830 */
7874                 dev_priv->display.get_display_clock_speed =
7875                         i830_get_display_clock_speed;
7876
7877         if (HAS_PCH_SPLIT(dev)) {
7878                 if (IS_GEN5(dev)) {
7879                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7880                         dev_priv->display.write_eld = ironlake_write_eld;
7881                 } else if (IS_GEN6(dev)) {
7882                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7883                         dev_priv->display.write_eld = ironlake_write_eld;
7884                 } else if (IS_IVYBRIDGE(dev)) {
7885                         /* FIXME: detect B0+ stepping and use auto training */
7886                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7887                         dev_priv->display.write_eld = ironlake_write_eld;
7888                 } else if (IS_HASWELL(dev)) {
7889                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7890                         dev_priv->display.write_eld = haswell_write_eld;
7891                 } else
7892                         dev_priv->display.update_wm = NULL;
7893         } else if (IS_G4X(dev)) {
7894                 dev_priv->display.write_eld = g4x_write_eld;
7895         }
7896
7897         /* Default just returns -ENODEV to indicate unsupported */
7898         dev_priv->display.queue_flip = intel_default_queue_flip;
7899
7900         switch (INTEL_INFO(dev)->gen) {
7901         case 2:
7902                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7903                 break;
7904
7905         case 3:
7906                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7907                 break;
7908
7909         case 4:
7910         case 5:
7911                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7912                 break;
7913
7914         case 6:
7915                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7916                 break;
7917         case 7:
7918                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7919                 break;
7920         }
7921 }
7922
7923 /*
7924  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7925  * resume, or other times.  This quirk makes sure that's the case for
7926  * affected systems.
7927  */
7928 static void quirk_pipea_force(struct drm_device *dev)
7929 {
7930         struct drm_i915_private *dev_priv = dev->dev_private;
7931
7932         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7933         DRM_INFO("applying pipe a force quirk\n");
7934 }
7935
7936 /*
7937  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7938  */
7939 static void quirk_ssc_force_disable(struct drm_device *dev)
7940 {
7941         struct drm_i915_private *dev_priv = dev->dev_private;
7942         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7943         DRM_INFO("applying lvds SSC disable quirk\n");
7944 }
7945
7946 /*
7947  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7948  * brightness value
7949  */
7950 static void quirk_invert_brightness(struct drm_device *dev)
7951 {
7952         struct drm_i915_private *dev_priv = dev->dev_private;
7953         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7954         DRM_INFO("applying inverted panel brightness quirk\n");
7955 }
7956
7957 struct intel_quirk {
7958         int device;
7959         int subsystem_vendor;
7960         int subsystem_device;
7961         void (*hook)(struct drm_device *dev);
7962 };
7963
7964 static struct intel_quirk intel_quirks[] = {
7965         /* HP Mini needs pipe A force quirk (LP: #322104) */
7966         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7967
7968         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7969         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7970
7971         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7972         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7973
7974         /* 855 & before need to leave pipe A & dpll A up */
7975         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7976         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7977         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7978
7979         /* Lenovo U160 cannot use SSC on LVDS */
7980         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7981
7982         /* Sony Vaio Y cannot use SSC on LVDS */
7983         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7984
7985         /* Acer Aspire 5734Z must invert backlight brightness */
7986         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7987 };
7988
7989 static void intel_init_quirks(struct drm_device *dev)
7990 {
7991         struct pci_dev *d = dev->pdev;
7992         int i;
7993
7994         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7995                 struct intel_quirk *q = &intel_quirks[i];
7996
7997                 if (d->device == q->device &&
7998                     (d->subsystem_vendor == q->subsystem_vendor ||
7999                      q->subsystem_vendor == PCI_ANY_ID) &&
8000                     (d->subsystem_device == q->subsystem_device ||
8001                      q->subsystem_device == PCI_ANY_ID))
8002                         q->hook(dev);
8003         }
8004 }
8005
8006 /* Disable the VGA plane that we never use */
8007 static void i915_disable_vga(struct drm_device *dev)
8008 {
8009         struct drm_i915_private *dev_priv = dev->dev_private;
8010         u8 sr1;
8011         u32 vga_reg;
8012
8013         if (HAS_PCH_SPLIT(dev))
8014                 vga_reg = CPU_VGACNTRL;
8015         else
8016                 vga_reg = VGACNTRL;
8017
8018         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8019         outb(SR01, VGA_SR_INDEX);
8020         sr1 = inb(VGA_SR_DATA);
8021         outb(sr1 | 1<<5, VGA_SR_DATA);
8022         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8023         udelay(300);
8024
8025         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8026         POSTING_READ(vga_reg);
8027 }
8028
8029 void intel_modeset_init_hw(struct drm_device *dev)
8030 {
8031         /* We attempt to init the necessary power wells early in the initialization
8032          * time, so the subsystems that expect power to be enabled can work.
8033          */
8034         intel_init_power_wells(dev);
8035
8036         intel_prepare_ddi(dev);
8037
8038         intel_init_clock_gating(dev);
8039
8040         mutex_lock(&dev->struct_mutex);
8041         intel_enable_gt_powersave(dev);
8042         mutex_unlock(&dev->struct_mutex);
8043 }
8044
8045 void intel_modeset_init(struct drm_device *dev)
8046 {
8047         struct drm_i915_private *dev_priv = dev->dev_private;
8048         int i, ret;
8049
8050         drm_mode_config_init(dev);
8051
8052         dev->mode_config.min_width = 0;
8053         dev->mode_config.min_height = 0;
8054
8055         dev->mode_config.preferred_depth = 24;
8056         dev->mode_config.prefer_shadow = 1;
8057
8058         dev->mode_config.funcs = &intel_mode_funcs;
8059
8060         intel_init_quirks(dev);
8061
8062         intel_init_pm(dev);
8063
8064         intel_init_display(dev);
8065
8066         if (IS_GEN2(dev)) {
8067                 dev->mode_config.max_width = 2048;
8068                 dev->mode_config.max_height = 2048;
8069         } else if (IS_GEN3(dev)) {
8070                 dev->mode_config.max_width = 4096;
8071                 dev->mode_config.max_height = 4096;
8072         } else {
8073                 dev->mode_config.max_width = 8192;
8074                 dev->mode_config.max_height = 8192;
8075         }
8076         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8077
8078         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8079                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8080
8081         for (i = 0; i < dev_priv->num_pipe; i++) {
8082                 intel_crtc_init(dev, i);
8083                 ret = intel_plane_init(dev, i);
8084                 if (ret)
8085                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8086         }
8087
8088         intel_pch_pll_init(dev);
8089
8090         /* Just disable it once at startup */
8091         i915_disable_vga(dev);
8092         intel_setup_outputs(dev);
8093 }
8094
8095 static void
8096 intel_connector_break_all_links(struct intel_connector *connector)
8097 {
8098         connector->base.dpms = DRM_MODE_DPMS_OFF;
8099         connector->base.encoder = NULL;
8100         connector->encoder->connectors_active = false;
8101         connector->encoder->base.crtc = NULL;
8102 }
8103
8104 static void intel_enable_pipe_a(struct drm_device *dev)
8105 {
8106         struct intel_connector *connector;
8107         struct drm_connector *crt = NULL;
8108         struct intel_load_detect_pipe load_detect_temp;
8109
8110         /* We can't just switch on the pipe A, we need to set things up with a
8111          * proper mode and output configuration. As a gross hack, enable pipe A
8112          * by enabling the load detect pipe once. */
8113         list_for_each_entry(connector,
8114                             &dev->mode_config.connector_list,
8115                             base.head) {
8116                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8117                         crt = &connector->base;
8118                         break;
8119                 }
8120         }
8121
8122         if (!crt)
8123                 return;
8124
8125         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8126                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8127
8128
8129 }
8130
8131 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8132 {
8133         struct drm_device *dev = crtc->base.dev;
8134         struct drm_i915_private *dev_priv = dev->dev_private;
8135         u32 reg, val;
8136
8137         /* Clear any frame start delays used for debugging left by the BIOS */
8138         reg = PIPECONF(crtc->pipe);
8139         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8140
8141         /* We need to sanitize the plane -> pipe mapping first because this will
8142          * disable the crtc (and hence change the state) if it is wrong. */
8143         if (!HAS_PCH_SPLIT(dev)) {
8144                 struct intel_connector *connector;
8145                 bool plane;
8146
8147                 reg = DSPCNTR(crtc->plane);
8148                 val = I915_READ(reg);
8149
8150                 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8151                     (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8152                         goto ok;
8153
8154                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8155                               crtc->base.base.id);
8156
8157                 /* Pipe has the wrong plane attached and the plane is active.
8158                  * Temporarily change the plane mapping and disable everything
8159                  * ...  */
8160                 plane = crtc->plane;
8161                 crtc->plane = !plane;
8162                 dev_priv->display.crtc_disable(&crtc->base);
8163                 crtc->plane = plane;
8164
8165                 /* ... and break all links. */
8166                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8167                                     base.head) {
8168                         if (connector->encoder->base.crtc != &crtc->base)
8169                                 continue;
8170
8171                         intel_connector_break_all_links(connector);
8172                 }
8173
8174                 WARN_ON(crtc->active);
8175                 crtc->base.enabled = false;
8176         }
8177 ok:
8178
8179         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8180             crtc->pipe == PIPE_A && !crtc->active) {
8181                 /* BIOS forgot to enable pipe A, this mostly happens after
8182                  * resume. Force-enable the pipe to fix this, the update_dpms
8183                  * call below we restore the pipe to the right state, but leave
8184                  * the required bits on. */
8185                 intel_enable_pipe_a(dev);
8186         }
8187
8188         /* Adjust the state of the output pipe according to whether we
8189          * have active connectors/encoders. */
8190         intel_crtc_update_dpms(&crtc->base);
8191
8192         if (crtc->active != crtc->base.enabled) {
8193                 struct intel_encoder *encoder;
8194
8195                 /* This can happen either due to bugs in the get_hw_state
8196                  * functions or because the pipe is force-enabled due to the
8197                  * pipe A quirk. */
8198                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8199                               crtc->base.base.id,
8200                               crtc->base.enabled ? "enabled" : "disabled",
8201                               crtc->active ? "enabled" : "disabled");
8202
8203                 crtc->base.enabled = crtc->active;
8204
8205                 /* Because we only establish the connector -> encoder ->
8206                  * crtc links if something is active, this means the
8207                  * crtc is now deactivated. Break the links. connector
8208                  * -> encoder links are only establish when things are
8209                  *  actually up, hence no need to break them. */
8210                 WARN_ON(crtc->active);
8211
8212                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8213                         WARN_ON(encoder->connectors_active);
8214                         encoder->base.crtc = NULL;
8215                 }
8216         }
8217 }
8218
8219 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8220 {
8221         struct intel_connector *connector;
8222         struct drm_device *dev = encoder->base.dev;
8223
8224         /* We need to check both for a crtc link (meaning that the
8225          * encoder is active and trying to read from a pipe) and the
8226          * pipe itself being active. */
8227         bool has_active_crtc = encoder->base.crtc &&
8228                 to_intel_crtc(encoder->base.crtc)->active;
8229
8230         if (encoder->connectors_active && !has_active_crtc) {
8231                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8232                               encoder->base.base.id,
8233                               drm_get_encoder_name(&encoder->base));
8234
8235                 /* Connector is active, but has no active pipe. This is
8236                  * fallout from our resume register restoring. Disable
8237                  * the encoder manually again. */
8238                 if (encoder->base.crtc) {
8239                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8240                                       encoder->base.base.id,
8241                                       drm_get_encoder_name(&encoder->base));
8242                         encoder->disable(encoder);
8243                 }
8244
8245                 /* Inconsistent output/port/pipe state happens presumably due to
8246                  * a bug in one of the get_hw_state functions. Or someplace else
8247                  * in our code, like the register restore mess on resume. Clamp
8248                  * things to off as a safer default. */
8249                 list_for_each_entry(connector,
8250                                     &dev->mode_config.connector_list,
8251                                     base.head) {
8252                         if (connector->encoder != encoder)
8253                                 continue;
8254
8255                         intel_connector_break_all_links(connector);
8256                 }
8257         }
8258         /* Enabled encoders without active connectors will be fixed in
8259          * the crtc fixup. */
8260 }
8261
8262 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8263  * and i915 state tracking structures. */
8264 void intel_modeset_setup_hw_state(struct drm_device *dev)
8265 {
8266         struct drm_i915_private *dev_priv = dev->dev_private;
8267         enum pipe pipe;
8268         u32 tmp;
8269         struct intel_crtc *crtc;
8270         struct intel_encoder *encoder;
8271         struct intel_connector *connector;
8272
8273         for_each_pipe(pipe) {
8274                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8275
8276                 tmp = I915_READ(PIPECONF(pipe));
8277                 if (tmp & PIPECONF_ENABLE)
8278                         crtc->active = true;
8279                 else
8280                         crtc->active = false;
8281
8282                 crtc->base.enabled = crtc->active;
8283
8284                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8285                               crtc->base.base.id,
8286                               crtc->active ? "enabled" : "disabled");
8287         }
8288
8289         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8290                             base.head) {
8291                 pipe = 0;
8292
8293                 if (encoder->get_hw_state(encoder, &pipe)) {
8294                         encoder->base.crtc =
8295                                 dev_priv->pipe_to_crtc_mapping[pipe];
8296                 } else {
8297                         encoder->base.crtc = NULL;
8298                 }
8299
8300                 encoder->connectors_active = false;
8301                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8302                               encoder->base.base.id,
8303                               drm_get_encoder_name(&encoder->base),
8304                               encoder->base.crtc ? "enabled" : "disabled",
8305                               pipe);
8306         }
8307
8308         list_for_each_entry(connector, &dev->mode_config.connector_list,
8309                             base.head) {
8310                 if (connector->get_hw_state(connector)) {
8311                         connector->base.dpms = DRM_MODE_DPMS_ON;
8312                         connector->encoder->connectors_active = true;
8313                         connector->base.encoder = &connector->encoder->base;
8314                 } else {
8315                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8316                         connector->base.encoder = NULL;
8317                 }
8318                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8319                               connector->base.base.id,
8320                               drm_get_connector_name(&connector->base),
8321                               connector->base.encoder ? "enabled" : "disabled");
8322         }
8323
8324         /* HW state is read out, now we need to sanitize this mess. */
8325         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8326                             base.head) {
8327                 intel_sanitize_encoder(encoder);
8328         }
8329
8330         for_each_pipe(pipe) {
8331                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8332                 intel_sanitize_crtc(crtc);
8333         }
8334
8335         intel_modeset_update_staged_output_state(dev);
8336
8337         intel_modeset_check_state(dev);
8338 }
8339
8340 void intel_modeset_gem_init(struct drm_device *dev)
8341 {
8342         intel_modeset_init_hw(dev);
8343
8344         intel_setup_overlay(dev);
8345
8346         intel_modeset_setup_hw_state(dev);
8347 }
8348
8349 void intel_modeset_cleanup(struct drm_device *dev)
8350 {
8351         struct drm_i915_private *dev_priv = dev->dev_private;
8352         struct drm_crtc *crtc;
8353         struct intel_crtc *intel_crtc;
8354
8355         drm_kms_helper_poll_fini(dev);
8356         mutex_lock(&dev->struct_mutex);
8357
8358         intel_unregister_dsm_handler();
8359
8360
8361         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8362                 /* Skip inactive CRTCs */
8363                 if (!crtc->fb)
8364                         continue;
8365
8366                 intel_crtc = to_intel_crtc(crtc);
8367                 intel_increase_pllclock(crtc);
8368         }
8369
8370         intel_disable_fbc(dev);
8371
8372         intel_disable_gt_powersave(dev);
8373
8374         ironlake_teardown_rc6(dev);
8375
8376         if (IS_VALLEYVIEW(dev))
8377                 vlv_init_dpio(dev);
8378
8379         mutex_unlock(&dev->struct_mutex);
8380
8381         /* Disable the irq before mode object teardown, for the irq might
8382          * enqueue unpin/hotplug work. */
8383         drm_irq_uninstall(dev);
8384         cancel_work_sync(&dev_priv->hotplug_work);
8385         cancel_work_sync(&dev_priv->rps.work);
8386
8387         /* flush any delayed tasks or pending work */
8388         flush_scheduled_work();
8389
8390         drm_mode_config_cleanup(dev);
8391 }
8392
8393 /*
8394  * Return which encoder is currently attached for connector.
8395  */
8396 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8397 {
8398         return &intel_attached_encoder(connector)->base;
8399 }
8400
8401 void intel_connector_attach_encoder(struct intel_connector *connector,
8402                                     struct intel_encoder *encoder)
8403 {
8404         connector->encoder = encoder;
8405         drm_mode_connector_attach_encoder(&connector->base,
8406                                           &encoder->base);
8407 }
8408
8409 /*
8410  * set vga decode state - true == enable VGA decode
8411  */
8412 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8413 {
8414         struct drm_i915_private *dev_priv = dev->dev_private;
8415         u16 gmch_ctrl;
8416
8417         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8418         if (state)
8419                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8420         else
8421                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8422         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8423         return 0;
8424 }
8425
8426 #ifdef CONFIG_DEBUG_FS
8427 #include <linux/seq_file.h>
8428
8429 struct intel_display_error_state {
8430         struct intel_cursor_error_state {
8431                 u32 control;
8432                 u32 position;
8433                 u32 base;
8434                 u32 size;
8435         } cursor[I915_MAX_PIPES];
8436
8437         struct intel_pipe_error_state {
8438                 u32 conf;
8439                 u32 source;
8440
8441                 u32 htotal;
8442                 u32 hblank;
8443                 u32 hsync;
8444                 u32 vtotal;
8445                 u32 vblank;
8446                 u32 vsync;
8447         } pipe[I915_MAX_PIPES];
8448
8449         struct intel_plane_error_state {
8450                 u32 control;
8451                 u32 stride;
8452                 u32 size;
8453                 u32 pos;
8454                 u32 addr;
8455                 u32 surface;
8456                 u32 tile_offset;
8457         } plane[I915_MAX_PIPES];
8458 };
8459
8460 struct intel_display_error_state *
8461 intel_display_capture_error_state(struct drm_device *dev)
8462 {
8463         drm_i915_private_t *dev_priv = dev->dev_private;
8464         struct intel_display_error_state *error;
8465         int i;
8466
8467         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8468         if (error == NULL)
8469                 return NULL;
8470
8471         for_each_pipe(i) {
8472                 error->cursor[i].control = I915_READ(CURCNTR(i));
8473                 error->cursor[i].position = I915_READ(CURPOS(i));
8474                 error->cursor[i].base = I915_READ(CURBASE(i));
8475
8476                 error->plane[i].control = I915_READ(DSPCNTR(i));
8477                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8478                 error->plane[i].size = I915_READ(DSPSIZE(i));
8479                 error->plane[i].pos = I915_READ(DSPPOS(i));
8480                 error->plane[i].addr = I915_READ(DSPADDR(i));
8481                 if (INTEL_INFO(dev)->gen >= 4) {
8482                         error->plane[i].surface = I915_READ(DSPSURF(i));
8483                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8484                 }
8485
8486                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8487                 error->pipe[i].source = I915_READ(PIPESRC(i));
8488                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8489                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8490                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8491                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8492                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8493                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8494         }
8495
8496         return error;
8497 }
8498
8499 void
8500 intel_display_print_error_state(struct seq_file *m,
8501                                 struct drm_device *dev,
8502                                 struct intel_display_error_state *error)
8503 {
8504         drm_i915_private_t *dev_priv = dev->dev_private;
8505         int i;
8506
8507         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8508         for_each_pipe(i) {
8509                 seq_printf(m, "Pipe [%d]:\n", i);
8510                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8511                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8512                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8513                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8514                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8515                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8516                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8517                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8518
8519                 seq_printf(m, "Plane [%d]:\n", i);
8520                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8521                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8522                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8523                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8524                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8525                 if (INTEL_INFO(dev)->gen >= 4) {
8526                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8527                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8528                 }
8529
8530                 seq_printf(m, "Cursor [%d]:\n", i);
8531                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8532                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8533                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8534         }
8535 }
8536 #endif