drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47 #include <linux/reservation.h>
  48 #include <linux/dma-buf.h>
  49
  50 /* Primary plane formats for gen <= 3 */
  51 static const uint32_t i8xx_primary_formats[] = {
  52         DRM_FORMAT_C8,
  53         DRM_FORMAT_RGB565,
  54         DRM_FORMAT_XRGB1555,
  55         DRM_FORMAT_XRGB8888,
  56 };
  57
  58 /* Primary plane formats for gen >= 4 */
  59 static const uint32_t i965_primary_formats[] = {
  60         DRM_FORMAT_C8,
  61         DRM_FORMAT_RGB565,
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_XRGB2101010,
  65         DRM_FORMAT_XBGR2101010,
  66 };
  67
  68 static const uint32_t skl_primary_formats[] = {
  69         DRM_FORMAT_C8,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_XBGR8888,
  73         DRM_FORMAT_ARGB8888,
  74         DRM_FORMAT_ABGR8888,
  75         DRM_FORMAT_XRGB2101010,
  76         DRM_FORMAT_XBGR2101010,
  77         DRM_FORMAT_YUYV,
  78         DRM_FORMAT_YVYU,
  79         DRM_FORMAT_UYVY,
  80         DRM_FORMAT_VYUY,
  81 };
  82
  83 /* Cursor formats */
  84 static const uint32_t intel_cursor_formats[] = {
  85         DRM_FORMAT_ARGB8888,
  86 };
  87
  88 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  89
  90 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  91                                 struct intel_crtc_state *pipe_config);
  92 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  93                                    struct intel_crtc_state *pipe_config);
  94
  95 static int intel_framebuffer_init(struct drm_device *dev,
  96                                   struct intel_framebuffer *ifb,
  97                                   struct drm_mode_fb_cmd2 *mode_cmd,
  98                                   struct drm_i915_gem_object *obj);
  99 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 114         struct intel_crtc_state *crtc_state);
 115 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 116                            int num_connectors);
 117 static void skylake_pfit_enable(struct intel_crtc *crtc);
 118 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 119 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 120 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 121
 122 typedef struct {
 123         int     min, max;
 124 } intel_range_t;
 125
 126 typedef struct {
 127         int     dot_limit;
 128         int     p2_slow, p2_fast;
 129 } intel_p2_t;
 130
 131 typedef struct intel_limit intel_limit_t;
 132 struct intel_limit {
 133         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 134         intel_p2_t          p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 152                                   const char *name, u32 reg)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         if (dev_priv->hpll_freq == 0)
 158                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 159
 160         mutex_lock(&dev_priv->sb_lock);
 161         val = vlv_cck_read(dev_priv, reg);
 162         mutex_unlock(&dev_priv->sb_lock);
 163
 164         divider = val & CCK_FREQUENCY_VALUES;
 165
 166         WARN((val & CCK_FREQUENCY_STATUS) !=
 167              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 168              "%s change in progress\n", name);
 169
 170         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 171 }
 172
 173 int
 174 intel_pch_rawclk(struct drm_device *dev)
 175 {
 176         struct drm_i915_private *dev_priv = dev->dev_private;
 177
 178         WARN_ON(!HAS_PCH_SPLIT(dev));
 179
 180         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 181 }
 182
 183 /* hrawclock is 1/4 the FSB frequency */
 184 int intel_hrawclk(struct drm_device *dev)
 185 {
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         uint32_t clkcfg;
 188
 189         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 190         if (IS_VALLEYVIEW(dev))
 191                 return 200;
 192
 193         clkcfg = I915_READ(CLKCFG);
 194         switch (clkcfg & CLKCFG_FSB_MASK) {
 195         case CLKCFG_FSB_400:
 196                 return 100;
 197         case CLKCFG_FSB_533:
 198                 return 133;
 199         case CLKCFG_FSB_667:
 200                 return 166;
 201         case CLKCFG_FSB_800:
 202                 return 200;
 203         case CLKCFG_FSB_1067:
 204                 return 266;
 205         case CLKCFG_FSB_1333:
 206                 return 333;
 207         /* these two are just a guess; one of them might be right */
 208         case CLKCFG_FSB_1600:
 209         case CLKCFG_FSB_1600_ALT:
 210                 return 400;
 211         default:
 212                 return 133;
 213         }
 214 }
 215
 216 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 217 {
 218         if (!IS_VALLEYVIEW(dev_priv))
 219                 return;
 220
 221         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 222                                                       CCK_CZ_CLOCK_CONTROL);
 223
 224         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 225 }
 226
 227 static inline u32 /* units of 100MHz */
 228 intel_fdi_link_freq(struct drm_device *dev)
 229 {
 230         if (IS_GEN5(dev)) {
 231                 struct drm_i915_private *dev_priv = dev->dev_private;
 232                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 233         } else
 234                 return 27;
 235 }
 236
 237 static const intel_limit_t intel_limits_i8xx_dac = {
 238         .dot = { .min = 25000, .max = 350000 },
 239         .vco = { .min = 908000, .max = 1512000 },
 240         .n = { .min = 2, .max = 16 },
 241         .m = { .min = 96, .max = 140 },
 242         .m1 = { .min = 18, .max = 26 },
 243         .m2 = { .min = 6, .max = 16 },
 244         .p = { .min = 4, .max = 128 },
 245         .p1 = { .min = 2, .max = 33 },
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 4, .p2_fast = 2 },
 248 };
 249
 250 static const intel_limit_t intel_limits_i8xx_dvo = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 908000, .max = 1512000 },
 253         .n = { .min = 2, .max = 16 },
 254         .m = { .min = 96, .max = 140 },
 255         .m1 = { .min = 18, .max = 26 },
 256         .m2 = { .min = 6, .max = 16 },
 257         .p = { .min = 4, .max = 128 },
 258         .p1 = { .min = 2, .max = 33 },
 259         .p2 = { .dot_limit = 165000,
 260                 .p2_slow = 4, .p2_fast = 4 },
 261 };
 262
 263 static const intel_limit_t intel_limits_i8xx_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 908000, .max = 1512000 },
 266         .n = { .min = 2, .max = 16 },
 267         .m = { .min = 96, .max = 140 },
 268         .m1 = { .min = 18, .max = 26 },
 269         .m2 = { .min = 6, .max = 16 },
 270         .p = { .min = 4, .max = 128 },
 271         .p1 = { .min = 1, .max = 6 },
 272         .p2 = { .dot_limit = 165000,
 273                 .p2_slow = 14, .p2_fast = 7 },
 274 };
 275
 276 static const intel_limit_t intel_limits_i9xx_sdvo = {
 277         .dot = { .min = 20000, .max = 400000 },
 278         .vco = { .min = 1400000, .max = 2800000 },
 279         .n = { .min = 1, .max = 6 },
 280         .m = { .min = 70, .max = 120 },
 281         .m1 = { .min = 8, .max = 18 },
 282         .m2 = { .min = 3, .max = 7 },
 283         .p = { .min = 5, .max = 80 },
 284         .p1 = { .min = 1, .max = 8 },
 285         .p2 = { .dot_limit = 200000,
 286                 .p2_slow = 10, .p2_fast = 5 },
 287 };
 288
 289 static const intel_limit_t intel_limits_i9xx_lvds = {
 290         .dot = { .min = 20000, .max = 400000 },
 291         .vco = { .min = 1400000, .max = 2800000 },
 292         .n = { .min = 1, .max = 6 },
 293         .m = { .min = 70, .max = 120 },
 294         .m1 = { .min = 8, .max = 18 },
 295         .m2 = { .min = 3, .max = 7 },
 296         .p = { .min = 7, .max = 98 },
 297         .p1 = { .min = 1, .max = 8 },
 298         .p2 = { .dot_limit = 112000,
 299                 .p2_slow = 14, .p2_fast = 7 },
 300 };
 301
 302
 303 static const intel_limit_t intel_limits_g4x_sdvo = {
 304         .dot = { .min = 25000, .max = 270000 },
 305         .vco = { .min = 1750000, .max = 3500000},
 306         .n = { .min = 1, .max = 4 },
 307         .m = { .min = 104, .max = 138 },
 308         .m1 = { .min = 17, .max = 23 },
 309         .m2 = { .min = 5, .max = 11 },
 310         .p = { .min = 10, .max = 30 },
 311         .p1 = { .min = 1, .max = 3},
 312         .p2 = { .dot_limit = 270000,
 313                 .p2_slow = 10,
 314                 .p2_fast = 10
 315         },
 316 };
 317
 318 static const intel_limit_t intel_limits_g4x_hdmi = {
 319         .dot = { .min = 22000, .max = 400000 },
 320         .vco = { .min = 1750000, .max = 3500000},
 321         .n = { .min = 1, .max = 4 },
 322         .m = { .min = 104, .max = 138 },
 323         .m1 = { .min = 16, .max = 23 },
 324         .m2 = { .min = 5, .max = 11 },
 325         .p = { .min = 5, .max = 80 },
 326         .p1 = { .min = 1, .max = 8},
 327         .p2 = { .dot_limit = 165000,
 328                 .p2_slow = 10, .p2_fast = 5 },
 329 };
 330
 331 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 332         .dot = { .min = 20000, .max = 115000 },
 333         .vco = { .min = 1750000, .max = 3500000 },
 334         .n = { .min = 1, .max = 3 },
 335         .m = { .min = 104, .max = 138 },
 336         .m1 = { .min = 17, .max = 23 },
 337         .m2 = { .min = 5, .max = 11 },
 338         .p = { .min = 28, .max = 112 },
 339         .p1 = { .min = 2, .max = 8 },
 340         .p2 = { .dot_limit = 0,
 341                 .p2_slow = 14, .p2_fast = 14
 342         },
 343 };
 344
 345 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 346         .dot = { .min = 80000, .max = 224000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 14, .max = 42 },
 353         .p1 = { .min = 2, .max = 6 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 7, .p2_fast = 7
 356         },
 357 };
 358
 359 static const intel_limit_t intel_limits_pineview_sdvo = {
 360         .dot = { .min = 20000, .max = 400000},
 361         .vco = { .min = 1700000, .max = 3500000 },
 362         /* Pineview's Ncounter is a ring counter */
 363         .n = { .min = 3, .max = 6 },
 364         .m = { .min = 2, .max = 256 },
 365         /* Pineview only has one combined m divider, which we treat as m2. */
 366         .m1 = { .min = 0, .max = 0 },
 367         .m2 = { .min = 0, .max = 254 },
 368         .p = { .min = 5, .max = 80 },
 369         .p1 = { .min = 1, .max = 8 },
 370         .p2 = { .dot_limit = 200000,
 371                 .p2_slow = 10, .p2_fast = 5 },
 372 };
 373
 374 static const intel_limit_t intel_limits_pineview_lvds = {
 375         .dot = { .min = 20000, .max = 400000 },
 376         .vco = { .min = 1700000, .max = 3500000 },
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         .m1 = { .min = 0, .max = 0 },
 380         .m2 = { .min = 0, .max = 254 },
 381         .p = { .min = 7, .max = 112 },
 382         .p1 = { .min = 1, .max = 8 },
 383         .p2 = { .dot_limit = 112000,
 384                 .p2_slow = 14, .p2_fast = 14 },
 385 };
 386
 387 /* Ironlake / Sandybridge
 388  *
 389  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 390  * the range value for them is (actual_value - 2).
 391  */
 392 static const intel_limit_t intel_limits_ironlake_dac = {
 393         .dot = { .min = 25000, .max = 350000 },
 394         .vco = { .min = 1760000, .max = 3510000 },
 395         .n = { .min = 1, .max = 5 },
 396         .m = { .min = 79, .max = 127 },
 397         .m1 = { .min = 12, .max = 22 },
 398         .m2 = { .min = 5, .max = 9 },
 399         .p = { .min = 5, .max = 80 },
 400         .p1 = { .min = 1, .max = 8 },
 401         .p2 = { .dot_limit = 225000,
 402                 .p2_slow = 10, .p2_fast = 5 },
 403 };
 404
 405 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 406         .dot = { .min = 25000, .max = 350000 },
 407         .vco = { .min = 1760000, .max = 3510000 },
 408         .n = { .min = 1, .max = 3 },
 409         .m = { .min = 79, .max = 118 },
 410         .m1 = { .min = 12, .max = 22 },
 411         .m2 = { .min = 5, .max = 9 },
 412         .p = { .min = 28, .max = 112 },
 413         .p1 = { .min = 2, .max = 8 },
 414         .p2 = { .dot_limit = 225000,
 415                 .p2_slow = 14, .p2_fast = 14 },
 416 };
 417
 418 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 419         .dot = { .min = 25000, .max = 350000 },
 420         .vco = { .min = 1760000, .max = 3510000 },
 421         .n = { .min = 1, .max = 3 },
 422         .m = { .min = 79, .max = 127 },
 423         .m1 = { .min = 12, .max = 22 },
 424         .m2 = { .min = 5, .max = 9 },
 425         .p = { .min = 14, .max = 56 },
 426         .p1 = { .min = 2, .max = 8 },
 427         .p2 = { .dot_limit = 225000,
 428                 .p2_slow = 7, .p2_fast = 7 },
 429 };
 430
 431 /* LVDS 100mhz refclk limits. */
 432 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 2 },
 436         .m = { .min = 79, .max = 126 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 28, .max = 112 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 14, .p2_fast = 14 },
 443 };
 444
 445 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 446         .dot = { .min = 25000, .max = 350000 },
 447         .vco = { .min = 1760000, .max = 3510000 },
 448         .n = { .min = 1, .max = 3 },
 449         .m = { .min = 79, .max = 126 },
 450         .m1 = { .min = 12, .max = 22 },
 451         .m2 = { .min = 5, .max = 9 },
 452         .p = { .min = 14, .max = 42 },
 453         .p1 = { .min = 2, .max = 6 },
 454         .p2 = { .dot_limit = 225000,
 455                 .p2_slow = 7, .p2_fast = 7 },
 456 };
 457
 458 static const intel_limit_t intel_limits_vlv = {
 459          /*
 460           * These are the data rate limits (measured in fast clocks)
 461           * since those are the strictest limits we have. The fast
 462           * clock and actual rate limits are more relaxed, so checking
 463           * them would make no difference.
 464           */
 465         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 466         .vco = { .min = 4000000, .max = 6000000 },
 467         .n = { .min = 1, .max = 7 },
 468         .m1 = { .min = 2, .max = 3 },
 469         .m2 = { .min = 11, .max = 156 },
 470         .p1 = { .min = 2, .max = 3 },
 471         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 472 };
 473
 474 static const intel_limit_t intel_limits_chv = {
 475         /*
 476          * These are the data rate limits (measured in fast clocks)
 477          * since those are the strictest limits we have.  The fast
 478          * clock and actual rate limits are more relaxed, so checking
 479          * them would make no difference.
 480          */
 481         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 482         .vco = { .min = 4800000, .max = 6480000 },
 483         .n = { .min = 1, .max = 1 },
 484         .m1 = { .min = 2, .max = 2 },
 485         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 486         .p1 = { .min = 2, .max = 4 },
 487         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 488 };
 489
 490 static const intel_limit_t intel_limits_bxt = {
 491         /* FIXME: find real dot limits */
 492         .dot = { .min = 0, .max = INT_MAX },
 493         .vco = { .min = 4800000, .max = 6700000 },
 494         .n = { .min = 1, .max = 1 },
 495         .m1 = { .min = 2, .max = 2 },
 496         /* FIXME: find real m2 limits */
 497         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 498         .p1 = { .min = 2, .max = 4 },
 499         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 500 };
 501
 502 static bool
 503 needs_modeset(struct drm_crtc_state *state)
 504 {
 505         return drm_atomic_crtc_needs_modeset(state);
 506 }
 507
 508 /**
 509  * Returns whether any output on the specified pipe is of the specified type
 510  */
 511 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 512 {
 513         struct drm_device *dev = crtc->base.dev;
 514         struct intel_encoder *encoder;
 515
 516         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 517                 if (encoder->type == type)
 518                         return true;
 519
 520         return false;
 521 }
 522
 523 /**
 524  * Returns whether any output on the specified pipe will have the specified
 525  * type after a staged modeset is complete, i.e., the same as
 526  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 527  * encoder->crtc.
 528  */
 529 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 530                                       int type)
 531 {
 532         struct drm_atomic_state *state = crtc_state->base.state;
 533         struct drm_connector *connector;
 534         struct drm_connector_state *connector_state;
 535         struct intel_encoder *encoder;
 536         int i, num_connectors = 0;
 537
 538         for_each_connector_in_state(state, connector, connector_state, i) {
 539                 if (connector_state->crtc != crtc_state->base.crtc)
 540                         continue;
 541
 542                 num_connectors++;
 543
 544                 encoder = to_intel_encoder(connector_state->best_encoder);
 545                 if (encoder->type == type)
 546                         return true;
 547         }
 548
 549         WARN_ON(num_connectors == 0);
 550
 551         return false;
 552 }
 553
 554 static const intel_limit_t *
 555 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 556 {
 557         struct drm_device *dev = crtc_state->base.crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 561                 if (intel_is_dual_link_lvds(dev)) {
 562                         if (refclk == 100000)
 563                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 564                         else
 565                                 limit = &intel_limits_ironlake_dual_lvds;
 566                 } else {
 567                         if (refclk == 100000)
 568                                 limit = &intel_limits_ironlake_single_lvds_100m;
 569                         else
 570                                 limit = &intel_limits_ironlake_single_lvds;
 571                 }
 572         } else
 573                 limit = &intel_limits_ironlake_dac;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *
 579 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 580 {
 581         struct drm_device *dev = crtc_state->base.crtc->dev;
 582         const intel_limit_t *limit;
 583
 584         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 585                 if (intel_is_dual_link_lvds(dev))
 586                         limit = &intel_limits_g4x_dual_channel_lvds;
 587                 else
 588                         limit = &intel_limits_g4x_single_channel_lvds;
 589         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 590                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 591                 limit = &intel_limits_g4x_hdmi;
 592         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 593                 limit = &intel_limits_g4x_sdvo;
 594         } else /* The option is for other outputs */
 595                 limit = &intel_limits_i9xx_sdvo;
 596
 597         return limit;
 598 }
 599
 600 static const intel_limit_t *
 601 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 602 {
 603         struct drm_device *dev = crtc_state->base.crtc->dev;
 604         const intel_limit_t *limit;
 605
 606         if (IS_BROXTON(dev))
 607                 limit = &intel_limits_bxt;
 608         else if (HAS_PCH_SPLIT(dev))
 609                 limit = intel_ironlake_limit(crtc_state, refclk);
 610         else if (IS_G4X(dev)) {
 611                 limit = intel_g4x_limit(crtc_state);
 612         } else if (IS_PINEVIEW(dev)) {
 613                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 614                         limit = &intel_limits_pineview_lvds;
 615                 else
 616                         limit = &intel_limits_pineview_sdvo;
 617         } else if (IS_CHERRYVIEW(dev)) {
 618                 limit = &intel_limits_chv;
 619         } else if (IS_VALLEYVIEW(dev)) {
 620                 limit = &intel_limits_vlv;
 621         } else if (!IS_GEN2(dev)) {
 622                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 623                         limit = &intel_limits_i9xx_lvds;
 624                 else
 625                         limit = &intel_limits_i9xx_sdvo;
 626         } else {
 627                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 628                         limit = &intel_limits_i8xx_lvds;
 629                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 630                         limit = &intel_limits_i8xx_dvo;
 631                 else
 632                         limit = &intel_limits_i8xx_dac;
 633         }
 634         return limit;
 635 }
 636
 637 /*
 638  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 639  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 640  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 641  * The helpers' return value is the rate of the clock that is fed to the
 642  * display engine's pipe which can be the above fast dot clock rate or a
 643  * divided-down version of it.
 644  */
 645 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 646 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 647 {
 648         clock->m = clock->m2 + 2;
 649         clock->p = clock->p1 * clock->p2;
 650         if (WARN_ON(clock->n == 0 || clock->p == 0))
 651                 return 0;
 652         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 653         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 654
 655         return clock->dot;
 656 }
 657
 658 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 659 {
 660         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 661 }
 662
 663 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 664 {
 665         clock->m = i9xx_dpll_compute_m(clock);
 666         clock->p = clock->p1 * clock->p2;
 667         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 668                 return 0;
 669         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 670         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 671
 672         return clock->dot;
 673 }
 674
 675 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 676 {
 677         clock->m = clock->m1 * clock->m2;
 678         clock->p = clock->p1 * clock->p2;
 679         if (WARN_ON(clock->n == 0 || clock->p == 0))
 680                 return 0;
 681         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 682         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 683
 684         return clock->dot / 5;
 685 }
 686
 687 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 688 {
 689         clock->m = clock->m1 * clock->m2;
 690         clock->p = clock->p1 * clock->p2;
 691         if (WARN_ON(clock->n == 0 || clock->p == 0))
 692                 return 0;
 693         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 694                         clock->n << 22);
 695         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 696
 697         return clock->dot / 5;
 698 }
 699
 700 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 701 /**
 702  * Returns whether the given set of divisors are valid for a given refclk with
 703  * the given connectors.
 704  */
 705
 706 static bool intel_PLL_is_valid(struct drm_device *dev,
 707                                const intel_limit_t *limit,
 708                                const intel_clock_t *clock)
 709 {
 710         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 711                 INTELPllInvalid("n out of range\n");
 712         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 713                 INTELPllInvalid("p1 out of range\n");
 714         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 715                 INTELPllInvalid("m2 out of range\n");
 716         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 717                 INTELPllInvalid("m1 out of range\n");
 718
 719         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 720                 if (clock->m1 <= clock->m2)
 721                         INTELPllInvalid("m1 <= m2\n");
 722
 723         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 724                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 725                         INTELPllInvalid("p out of range\n");
 726                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 727                         INTELPllInvalid("m out of range\n");
 728         }
 729
 730         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 731                 INTELPllInvalid("vco out of range\n");
 732         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 733          * connector, etc., rather than just a single range.
 734          */
 735         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 736                 INTELPllInvalid("dot out of range\n");
 737
 738         return true;
 739 }
 740
 741 static int
 742 i9xx_select_p2_div(const intel_limit_t *limit,
 743                    const struct intel_crtc_state *crtc_state,
 744                    int target)
 745 {
 746         struct drm_device *dev = crtc_state->base.crtc->dev;
 747
 748         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 749                 /*
 750                  * For LVDS just rely on its current settings for dual-channel.
 751                  * We haven't figured out how to reliably set up different
 752                  * single/dual channel state, if we even can.
 753                  */
 754                 if (intel_is_dual_link_lvds(dev))
 755                         return limit->p2.p2_fast;
 756                 else
 757                         return limit->p2.p2_slow;
 758         } else {
 759                 if (target < limit->p2.dot_limit)
 760                         return limit->p2.p2_slow;
 761                 else
 762                         return limit->p2.p2_fast;
 763         }
 764 }
 765
 766 static bool
 767 i9xx_find_best_dpll(const intel_limit_t *limit,
 768                     struct intel_crtc_state *crtc_state,
 769                     int target, int refclk, intel_clock_t *match_clock,
 770                     intel_clock_t *best_clock)
 771 {
 772         struct drm_device *dev = crtc_state->base.crtc->dev;
 773         intel_clock_t clock;
 774         int err = target;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 779
 780         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 781              clock.m1++) {
 782                 for (clock.m2 = limit->m2.min;
 783                      clock.m2 <= limit->m2.max; clock.m2++) {
 784                         if (clock.m2 >= clock.m1)
 785                                 break;
 786                         for (clock.n = limit->n.min;
 787                              clock.n <= limit->n.max; clock.n++) {
 788                                 for (clock.p1 = limit->p1.min;
 789                                         clock.p1 <= limit->p1.max; clock.p1++) {
 790                                         int this_err;
 791
 792                                         i9xx_calc_dpll_params(refclk, &clock);
 793                                         if (!intel_PLL_is_valid(dev, limit,
 794                                                                 &clock))
 795                                                 continue;
 796                                         if (match_clock &&
 797                                             clock.p != match_clock->p)
 798                                                 continue;
 799
 800                                         this_err = abs(clock.dot - target);
 801                                         if (this_err < err) {
 802                                                 *best_clock = clock;
 803                                                 err = this_err;
 804                                         }
 805                                 }
 806                         }
 807                 }
 808         }
 809
 810         return (err != target);
 811 }
 812
 813 static bool
 814 pnv_find_best_dpll(const intel_limit_t *limit,
 815                    struct intel_crtc_state *crtc_state,
 816                    int target, int refclk, intel_clock_t *match_clock,
 817                    intel_clock_t *best_clock)
 818 {
 819         struct drm_device *dev = crtc_state->base.crtc->dev;
 820         intel_clock_t clock;
 821         int err = target;
 822
 823         memset(best_clock, 0, sizeof(*best_clock));
 824
 825         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 826
 827         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 828              clock.m1++) {
 829                 for (clock.m2 = limit->m2.min;
 830                      clock.m2 <= limit->m2.max; clock.m2++) {
 831                         for (clock.n = limit->n.min;
 832                              clock.n <= limit->n.max; clock.n++) {
 833                                 for (clock.p1 = limit->p1.min;
 834                                         clock.p1 <= limit->p1.max; clock.p1++) {
 835                                         int this_err;
 836
 837                                         pnv_calc_dpll_params(refclk, &clock);
 838                                         if (!intel_PLL_is_valid(dev, limit,
 839                                                                 &clock))
 840                                                 continue;
 841                                         if (match_clock &&
 842                                             clock.p != match_clock->p)
 843                                                 continue;
 844
 845                                         this_err = abs(clock.dot - target);
 846                                         if (this_err < err) {
 847                                                 *best_clock = clock;
 848                                                 err = this_err;
 849                                         }
 850                                 }
 851                         }
 852                 }
 853         }
 854
 855         return (err != target);
 856 }
 857
 858 static bool
 859 g4x_find_best_dpll(const intel_limit_t *limit,
 860                    struct intel_crtc_state *crtc_state,
 861                    int target, int refclk, intel_clock_t *match_clock,
 862                    intel_clock_t *best_clock)
 863 {
 864         struct drm_device *dev = crtc_state->base.crtc->dev;
 865         intel_clock_t clock;
 866         int max_n;
 867         bool found = false;
 868         /* approximately equals target * 0.00585 */
 869         int err_most = (target >> 8) + (target >> 9);
 870
 871         memset(best_clock, 0, sizeof(*best_clock));
 872
 873         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 874
 875         max_n = limit->n.max;
 876         /* based on hardware requirement, prefer smaller n to precision */
 877         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 878                 /* based on hardware requirement, prefere larger m1,m2 */
 879                 for (clock.m1 = limit->m1.max;
 880                      clock.m1 >= limit->m1.min; clock.m1--) {
 881                         for (clock.m2 = limit->m2.max;
 882                              clock.m2 >= limit->m2.min; clock.m2--) {
 883                                 for (clock.p1 = limit->p1.max;
 884                                      clock.p1 >= limit->p1.min; clock.p1--) {
 885                                         int this_err;
 886
 887                                         i9xx_calc_dpll_params(refclk, &clock);
 888                                         if (!intel_PLL_is_valid(dev, limit,
 889                                                                 &clock))
 890                                                 continue;
 891
 892                                         this_err = abs(clock.dot - target);
 893                                         if (this_err < err_most) {
 894                                                 *best_clock = clock;
 895                                                 err_most = this_err;
 896                                                 max_n = clock.n;
 897                                                 found = true;
 898                                         }
 899                                 }
 900                         }
 901                 }
 902         }
 903         return found;
 904 }
 905
 906 /*
 907  * Check if the calculated PLL configuration is more optimal compared to the
 908  * best configuration and error found so far. Return the calculated error.
 909  */
 910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 911                                const intel_clock_t *calculated_clock,
 912                                const intel_clock_t *best_clock,
 913                                unsigned int best_error_ppm,
 914                                unsigned int *error_ppm)
 915 {
 916         /*
 917          * For CHV ignore the error and consider only the P value.
 918          * Prefer a bigger P value based on HW requirements.
 919          */
 920         if (IS_CHERRYVIEW(dev)) {
 921                 *error_ppm = 0;
 922
 923                 return calculated_clock->p > best_clock->p;
 924         }
 925
 926         if (WARN_ON_ONCE(!target_freq))
 927                 return false;
 928
 929         *error_ppm = div_u64(1000000ULL *
 930                                 abs(target_freq - calculated_clock->dot),
 931                              target_freq);
 932         /*
 933          * Prefer a better P value over a better (smaller) error if the error
 934          * is small. Ensure this preference for future configurations too by
 935          * setting the error to 0.
 936          */
 937         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 938                 *error_ppm = 0;
 939
 940                 return true;
 941         }
 942
 943         return *error_ppm + 10 < best_error_ppm;
 944 }
 945
 946 static bool
 947 vlv_find_best_dpll(const intel_limit_t *limit,
 948                    struct intel_crtc_state *crtc_state,
 949                    int target, int refclk, intel_clock_t *match_clock,
 950                    intel_clock_t *best_clock)
 951 {
 952         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 953         struct drm_device *dev = crtc->base.dev;
 954         intel_clock_t clock;
 955         unsigned int bestppm = 1000000;
 956         /* min update 19.2 MHz */
 957         int max_n = min(limit->n.max, refclk / 19200);
 958         bool found = false;
 959
 960         target *= 5; /* fast clock */
 961
 962         memset(best_clock, 0, sizeof(*best_clock));
 963
 964         /* based on hardware requirement, prefer smaller n to precision */
 965         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 966                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 967                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 968                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 969                                 clock.p = clock.p1 * clock.p2;
 970                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 971                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 972                                         unsigned int ppm;
 973
 974                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 975                                                                      refclk * clock.m1);
 976
 977                                         vlv_calc_dpll_params(refclk, &clock);
 978
 979                                         if (!intel_PLL_is_valid(dev, limit,
 980                                                                 &clock))
 981                                                 continue;
 982
 983                                         if (!vlv_PLL_is_optimal(dev, target,
 984                                                                 &clock,
 985                                                                 best_clock,
 986                                                                 bestppm, &ppm))
 987                                                 continue;
 988
 989                                         *best_clock = clock;
 990                                         bestppm = ppm;
 991                                         found = true;
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return found;
 998 }
 999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002                    struct intel_crtc_state *crtc_state,
1003                    int target, int refclk, intel_clock_t *match_clock,
1004                    intel_clock_t *best_clock)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007         struct drm_device *dev = crtc->base.dev;
1008         unsigned int best_error_ppm;
1009         intel_clock_t clock;
1010         uint64_t m2;
1011         int found = false;
1012
1013         memset(best_clock, 0, sizeof(*best_clock));
1014         best_error_ppm = 1000000;
1015
1016         /*
1017          * Based on hardware doc, the n always set to 1, and m1 always
1018          * set to 2.  If requires to support 200Mhz refclk, we need to
1019          * revisit this because n may not 1 anymore.
1020          */
1021         clock.n = 1, clock.m1 = 2;
1022         target *= 5;    /* fast clock */
1023
1024         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025                 for (clock.p2 = limit->p2.p2_fast;
1026                                 clock.p2 >= limit->p2.p2_slow;
1027                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028                         unsigned int error_ppm;
1029
1030                         clock.p = clock.p1 * clock.p2;
1031
1032                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033                                         clock.n) << 22, refclk * clock.m1);
1034
1035                         if (m2 > INT_MAX/clock.m1)
1036                                 continue;
1037
1038                         clock.m2 = m2;
1039
1040                         chv_calc_dpll_params(refclk, &clock);
1041
1042                         if (!intel_PLL_is_valid(dev, limit, &clock))
1043                                 continue;
1044
1045                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046                                                 best_error_ppm, &error_ppm))
1047                                 continue;
1048
1049                         *best_clock = clock;
1050                         best_error_ppm = error_ppm;
1051                         found = true;
1052                 }
1053         }
1054
1055         return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059                         intel_clock_t *best_clock)
1060 {
1061         int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064                                   target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071         /* Be paranoid as we can arrive here with only partial
1072          * state retrieved from the hardware during setup.
1073          *
1074          * We can ditch the adjusted_mode.crtc_clock check as soon
1075          * as Haswell has gained clock readout/fastboot support.
1076          *
1077          * We can ditch the crtc->primary->fb check as soon as we can
1078          * properly reconstruct framebuffers.
1079          *
1080          * FIXME: The intel_crtc->active here should be switched to
1081          * crtc->state->active once we have proper CRTC states wired up
1082          * for atomic.
1083          */
1084         return intel_crtc->active && crtc->primary->state->fb &&
1085                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089                                              enum pipe pipe)
1090 {
1091         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094         return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         i915_reg_t reg = PIPEDSL(pipe);
1101         u32 line1, line2;
1102         u32 line_mask;
1103
1104         if (IS_GEN2(dev))
1105                 line_mask = DSL_LINEMASK_GEN2;
1106         else
1107                 line_mask = DSL_LINEMASK_GEN3;
1108
1109         line1 = I915_READ(reg) & line_mask;
1110         msleep(5);
1111         line2 = I915_READ(reg) & line_mask;
1112
1113         return line1 == line2;
1114 }
1115
1116 /*
1117  * intel_wait_for_pipe_off - wait for pipe to turn off
1118  * @crtc: crtc whose pipe to wait for
1119  *
1120  * After disabling a pipe, we can't wait for vblank in the usual way,
1121  * spinning on the vblank interrupt status bit, since we won't actually
1122  * see an interrupt when the pipe is disabled.
1123  *
1124  * On Gen4 and above:
1125  *   wait for the pipe register state bit to turn off
1126  *
1127  * Otherwise:
1128  *   wait for the display line value to settle (it usually
1129  *   ends up stopping at the start of the next frame).
1130  *
1131  */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134         struct drm_device *dev = crtc->base.dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137         enum pipe pipe = crtc->pipe;
1138
1139         if (INTEL_INFO(dev)->gen >= 4) {
1140                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142                 /* Wait for the Pipe State to go off */
1143                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144                              100))
1145                         WARN(1, "pipe_off wait timed out\n");
1146         } else {
1147                 /* Wait for the display line to settle */
1148                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149                         WARN(1, "pipe_off wait timed out\n");
1150         }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155         return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160                 enum pipe pipe, bool state)
1161 {
1162         u32 val;
1163         bool cur_state;
1164
1165         val = I915_READ(DPLL(pipe));
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         bool cur_state;
1223         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224                                                                       pipe);
1225
1226         if (HAS_DDI(dev_priv->dev)) {
1227                 /* DDI does not have a specific FDI_TX register */
1228                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230         } else {
1231                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232                 cur_state = !!(val & FDI_TX_ENABLE);
1233         }
1234         I915_STATE_WARN(cur_state != state,
1235              "FDI TX state assertion failure (expected %s, current %s)\n",
1236              state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242                           enum pipe pipe, bool state)
1243 {
1244         u32 val;
1245         bool cur_state;
1246
1247         val = I915_READ(FDI_RX_CTL(pipe));
1248         cur_state = !!(val & FDI_RX_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX state assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257                                       enum pipe pipe)
1258 {
1259         u32 val;
1260
1261         /* ILK FDI PLL is always enabled */
1262         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263                 return;
1264
1265         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266         if (HAS_DDI(dev_priv->dev))
1267                 return;
1268
1269         val = I915_READ(FDI_TX_CTL(pipe));
1270         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274                        enum pipe pipe, bool state)
1275 {
1276         u32 val;
1277         bool cur_state;
1278
1279         val = I915_READ(FDI_RX_CTL(pipe));
1280         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281         I915_STATE_WARN(cur_state != state,
1282              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283              state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287                            enum pipe pipe)
1288 {
1289         struct drm_device *dev = dev_priv->dev;
1290         i915_reg_t pp_reg;
1291         u32 val;
1292         enum pipe panel_pipe = PIPE_A;
1293         bool locked = true;
1294
1295         if (WARN_ON(HAS_DDI(dev)))
1296                 return;
1297
1298         if (HAS_PCH_SPLIT(dev)) {
1299                 u32 port_sel;
1300
1301                 pp_reg = PCH_PP_CONTROL;
1302                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306                         panel_pipe = PIPE_B;
1307                 /* XXX: else fix for eDP */
1308         } else if (IS_VALLEYVIEW(dev)) {
1309                 /* presumably write lock depends on pipe, not port select */
1310                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311                 panel_pipe = pipe;
1312         } else {
1313                 pp_reg = PP_CONTROL;
1314                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315                         panel_pipe = PIPE_B;
1316         }
1317
1318         val = I915_READ(pp_reg);
1319         if (!(val & PANEL_POWER_ON) ||
1320             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321                 locked = false;
1322
1323         I915_STATE_WARN(panel_pipe == pipe && locked,
1324              "panel assertion failure, pipe %c regs locked\n",
1325              pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329                           enum pipe pipe, bool state)
1330 {
1331         struct drm_device *dev = dev_priv->dev;
1332         bool cur_state;
1333
1334         if (IS_845G(dev) || IS_I865G(dev))
1335                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336         else
1337                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339         I915_STATE_WARN(cur_state != state,
1340              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341              pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347                  enum pipe pipe, bool state)
1348 {
1349         bool cur_state;
1350         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351                                                                       pipe);
1352
1353         /* if we need the pipe quirk it must be always on */
1354         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356                 state = true;
1357
1358         if (!intel_display_power_is_enabled(dev_priv,
1359                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360                 cur_state = false;
1361         } else {
1362                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363                 cur_state = !!(val & PIPECONF_ENABLE);
1364         }
1365
1366         I915_STATE_WARN(cur_state != state,
1367              "pipe %c assertion failure (expected %s, current %s)\n",
1368              pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372                          enum plane plane, bool state)
1373 {
1374         u32 val;
1375         bool cur_state;
1376
1377         val = I915_READ(DSPCNTR(plane));
1378         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379         I915_STATE_WARN(cur_state != state,
1380              "plane %c assertion failure (expected %s, current %s)\n",
1381              plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388                                    enum pipe pipe)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391         int i;
1392
1393         /* Primary planes are fixed to pipes on gen4+ */
1394         if (INTEL_INFO(dev)->gen >= 4) {
1395                 u32 val = I915_READ(DSPCNTR(pipe));
1396                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397                      "plane %c assertion failure, should be disabled but not\n",
1398                      plane_name(pipe));
1399                 return;
1400         }
1401
1402         /* Need to check both planes against the pipe */
1403         for_each_pipe(dev_priv, i) {
1404                 u32 val = I915_READ(DSPCNTR(i));
1405                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406                         DISPPLANE_SEL_PIPE_SHIFT;
1407                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(i), pipe_name(pipe));
1410         }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414                                     enum pipe pipe)
1415 {
1416         struct drm_device *dev = dev_priv->dev;
1417         int sprite;
1418
1419         if (INTEL_INFO(dev)->gen >= 9) {
1420                 for_each_sprite(dev_priv, pipe, sprite) {
1421                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424                              sprite, pipe_name(pipe));
1425                 }
1426         } else if (IS_VALLEYVIEW(dev)) {
1427                 for_each_sprite(dev_priv, pipe, sprite) {
1428                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1429                         I915_STATE_WARN(val & SP_ENABLE,
1430                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431                              sprite_name(pipe, sprite), pipe_name(pipe));
1432                 }
1433         } else if (INTEL_INFO(dev)->gen >= 7) {
1434                 u32 val = I915_READ(SPRCTL(pipe));
1435                 I915_STATE_WARN(val & SPRITE_ENABLE,
1436                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437                      plane_name(pipe), pipe_name(pipe));
1438         } else if (INTEL_INFO(dev)->gen >= 5) {
1439                 u32 val = I915_READ(DVSCNTR(pipe));
1440                 I915_STATE_WARN(val & DVS_ENABLE,
1441                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442                      plane_name(pipe), pipe_name(pipe));
1443         }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449                 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454         u32 val;
1455         bool enabled;
1456
1457         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459         val = I915_READ(PCH_DREF_CONTROL);
1460         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461                             DREF_SUPERSPREAD_SOURCE_MASK));
1462         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466                                            enum pipe pipe)
1467 {
1468         u32 val;
1469         bool enabled;
1470
1471         val = I915_READ(PCH_TRANSCONF(pipe));
1472         enabled = !!(val & TRANS_ENABLE);
1473         I915_STATE_WARN(enabled,
1474              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475              pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479                             enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481         if ((val & DP_PORT_EN) == 0)
1482                 return false;
1483
1484         if (HAS_PCH_CPT(dev_priv->dev)) {
1485                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487                         return false;
1488         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490                         return false;
1491         } else {
1492                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493                         return false;
1494         }
1495         return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499                               enum pipe pipe, u32 val)
1500 {
1501         if ((val & SDVO_ENABLE) == 0)
1502                 return false;
1503
1504         if (HAS_PCH_CPT(dev_priv->dev)) {
1505                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506                         return false;
1507         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & LVDS_PORT_EN) == 0)
1521                 return false;
1522
1523         if (HAS_PCH_CPT(dev_priv->dev)) {
1524                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525                         return false;
1526         } else {
1527                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528                         return false;
1529         }
1530         return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534                               enum pipe pipe, u32 val)
1535 {
1536         if ((val & ADPA_DAC_ENABLE) == 0)
1537                 return false;
1538         if (HAS_PCH_CPT(dev_priv->dev)) {
1539                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540                         return false;
1541         } else {
1542                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543                         return false;
1544         }
1545         return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549                                    enum pipe pipe, i915_reg_t reg,
1550                                    u32 port_sel)
1551 {
1552         u32 val = I915_READ(reg);
1553         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555              i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558              && (val & DP_PIPEB_SELECT),
1559              "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563                                      enum pipe pipe, i915_reg_t reg)
1564 {
1565         u32 val = I915_READ(reg);
1566         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568              i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571              && (val & SDVO_PIPE_B_SELECT),
1572              "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576                                       enum pipe pipe)
1577 {
1578         u32 val;
1579
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584         val = I915_READ(PCH_ADPA);
1585         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586              "PCH VGA enabled on transcoder %c, should be disabled\n",
1587              pipe_name(pipe));
1588
1589         val = I915_READ(PCH_LVDS);
1590         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592              pipe_name(pipe));
1593
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600                            const struct intel_crtc_state *pipe_config)
1601 {
1602         struct drm_device *dev = crtc->base.dev;
1603         struct drm_i915_private *dev_priv = dev->dev_private;
1604         i915_reg_t reg = DPLL(crtc->pipe);
1605         u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607         assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609         /* No really, not for ILK+ */
1610         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1611
1612         /* PLL is protected by panel, make sure we can write it */
1613         if (IS_MOBILE(dev_priv->dev))
1614                 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616         I915_WRITE(reg, dpll);
1617         POSTING_READ(reg);
1618         udelay(150);
1619
1620         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1621                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1622
1623         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1624         POSTING_READ(DPLL_MD(crtc->pipe));
1625
1626         /* We do this three times for luck */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630         I915_WRITE(reg, dpll);
1631         POSTING_READ(reg);
1632         udelay(150); /* wait for warmup */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636 }
1637
1638 static void chv_enable_pll(struct intel_crtc *crtc,
1639                            const struct intel_crtc_state *pipe_config)
1640 {
1641         struct drm_device *dev = crtc->base.dev;
1642         struct drm_i915_private *dev_priv = dev->dev_private;
1643         int pipe = crtc->pipe;
1644         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1645         u32 tmp;
1646
1647         assert_pipe_disabled(dev_priv, crtc->pipe);
1648
1649         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1650
1651         mutex_lock(&dev_priv->sb_lock);
1652
1653         /* Enable back the 10bit clock to display controller */
1654         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1655         tmp |= DPIO_DCLKP_EN;
1656         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1657
1658         mutex_unlock(&dev_priv->sb_lock);
1659
1660         /*
1661          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1662          */
1663         udelay(1);
1664
1665         /* Enable PLL */
1666         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1667
1668         /* Check PLL is locked */
1669         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1670                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1671
1672         /* not sure when this should be written */
1673         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1674         POSTING_READ(DPLL_MD(pipe));
1675 }
1676
1677 static int intel_num_dvo_pipes(struct drm_device *dev)
1678 {
1679         struct intel_crtc *crtc;
1680         int count = 0;
1681
1682         for_each_intel_crtc(dev, crtc)
1683                 count += crtc->base.state->active &&
1684                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1685
1686         return count;
1687 }
1688
1689 static void i9xx_enable_pll(struct intel_crtc *crtc)
1690 {
1691         struct drm_device *dev = crtc->base.dev;
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         i915_reg_t reg = DPLL(crtc->pipe);
1694         u32 dpll = crtc->config->dpll_hw_state.dpll;
1695
1696         assert_pipe_disabled(dev_priv, crtc->pipe);
1697
1698         /* No really, not for ILK+ */
1699         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1700
1701         /* PLL is protected by panel, make sure we can write it */
1702         if (IS_MOBILE(dev) && !IS_I830(dev))
1703                 assert_panel_unlocked(dev_priv, crtc->pipe);
1704
1705         /* Enable DVO 2x clock on both PLLs if necessary */
1706         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1707                 /*
1708                  * It appears to be important that we don't enable this
1709                  * for the current pipe before otherwise configuring the
1710                  * PLL. No idea how this should be handled if multiple
1711                  * DVO outputs are enabled simultaneosly.
1712                  */
1713                 dpll |= DPLL_DVO_2X_MODE;
1714                 I915_WRITE(DPLL(!crtc->pipe),
1715                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1716         }
1717
1718         /*
1719          * Apparently we need to have VGA mode enabled prior to changing
1720          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1721          * dividers, even though the register value does change.
1722          */
1723         I915_WRITE(reg, 0);
1724
1725         I915_WRITE(reg, dpll);
1726
1727         /* Wait for the clocks to stabilize. */
1728         POSTING_READ(reg);
1729         udelay(150);
1730
1731         if (INTEL_INFO(dev)->gen >= 4) {
1732                 I915_WRITE(DPLL_MD(crtc->pipe),
1733                            crtc->config->dpll_hw_state.dpll_md);
1734         } else {
1735                 /* The pixel multiplier can only be updated once the
1736                  * DPLL is enabled and the clocks are stable.
1737                  *
1738                  * So write it again.
1739                  */
1740                 I915_WRITE(reg, dpll);
1741         }
1742
1743         /* We do this three times for luck */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750         I915_WRITE(reg, dpll);
1751         POSTING_READ(reg);
1752         udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756  * i9xx_disable_pll - disable a PLL
1757  * @dev_priv: i915 private structure
1758  * @pipe: pipe PLL to disable
1759  *
1760  * Disable the PLL for @pipe, making sure the pipe is off first.
1761  *
1762  * Note!  This is for pre-ILK only.
1763  */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766         struct drm_device *dev = crtc->base.dev;
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         enum pipe pipe = crtc->pipe;
1769
1770         /* Disable DVO 2x clock on both PLLs if necessary */
1771         if (IS_I830(dev) &&
1772             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773             !intel_num_dvo_pipes(dev)) {
1774                 I915_WRITE(DPLL(PIPE_B),
1775                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776                 I915_WRITE(DPLL(PIPE_A),
1777                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778         }
1779
1780         /* Don't disable pipe or pipe PLLs if needed */
1781         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783                 return;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1789         POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794         u32 val;
1795
1796         /* Make sure the pipe isn't still relying on us */
1797         assert_pipe_disabled(dev_priv, pipe);
1798
1799         /*
1800          * Leave integrated clock source and reference clock enabled for pipe B.
1801          * The latter is needed for VGA hotplug / manual detection.
1802          */
1803         val = DPLL_VGA_MODE_DIS;
1804         if (pipe == PIPE_B)
1805                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1806         I915_WRITE(DPLL(pipe), val);
1807         POSTING_READ(DPLL(pipe));
1808
1809 }
1810
1811 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1814         u32 val;
1815
1816         /* Make sure the pipe isn't still relying on us */
1817         assert_pipe_disabled(dev_priv, pipe);
1818
1819         /* Set PLL en = 0 */
1820         val = DPLL_SSC_REF_CLK_CHV |
1821                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1822         if (pipe != PIPE_A)
1823                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824         I915_WRITE(DPLL(pipe), val);
1825         POSTING_READ(DPLL(pipe));
1826
1827         mutex_lock(&dev_priv->sb_lock);
1828
1829         /* Disable 10bit clock to display controller */
1830         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831         val &= ~DPIO_DCLKP_EN;
1832         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
1834         mutex_unlock(&dev_priv->sb_lock);
1835 }
1836
1837 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1838                          struct intel_digital_port *dport,
1839                          unsigned int expected_mask)
1840 {
1841         u32 port_mask;
1842         i915_reg_t dpll_reg;
1843
1844         switch (dport->port) {
1845         case PORT_B:
1846                 port_mask = DPLL_PORTB_READY_MASK;
1847                 dpll_reg = DPLL(0);
1848                 break;
1849         case PORT_C:
1850                 port_mask = DPLL_PORTC_READY_MASK;
1851                 dpll_reg = DPLL(0);
1852                 expected_mask <<= 4;
1853                 break;
1854         case PORT_D:
1855                 port_mask = DPLL_PORTD_READY_MASK;
1856                 dpll_reg = DPIO_PHY_STATUS;
1857                 break;
1858         default:
1859                 BUG();
1860         }
1861
1862         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1863                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1864                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1865 }
1866
1867 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1868 {
1869         struct drm_device *dev = crtc->base.dev;
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1872
1873         if (WARN_ON(pll == NULL))
1874                 return;
1875
1876         WARN_ON(!pll->config.crtc_mask);
1877         if (pll->active == 0) {
1878                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1879                 WARN_ON(pll->on);
1880                 assert_shared_dpll_disabled(dev_priv, pll);
1881
1882                 pll->mode_set(dev_priv, pll);
1883         }
1884 }
1885
1886 /**
1887  * intel_enable_shared_dpll - enable PCH PLL
1888  * @dev_priv: i915 private structure
1889  * @pipe: pipe PLL to enable
1890  *
1891  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1892  * drives the transcoder clock.
1893  */
1894 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1895 {
1896         struct drm_device *dev = crtc->base.dev;
1897         struct drm_i915_private *dev_priv = dev->dev_private;
1898         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1899
1900         if (WARN_ON(pll == NULL))
1901                 return;
1902
1903         if (WARN_ON(pll->config.crtc_mask == 0))
1904                 return;
1905
1906         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1907                       pll->name, pll->active, pll->on,
1908                       crtc->base.base.id);
1909
1910         if (pll->active++) {
1911                 WARN_ON(!pll->on);
1912                 assert_shared_dpll_enabled(dev_priv, pll);
1913                 return;
1914         }
1915         WARN_ON(pll->on);
1916
1917         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1918
1919         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1920         pll->enable(dev_priv, pll);
1921         pll->on = true;
1922 }
1923
1924 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1925 {
1926         struct drm_device *dev = crtc->base.dev;
1927         struct drm_i915_private *dev_priv = dev->dev_private;
1928         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1929
1930         /* PCH only available on ILK+ */
1931         if (INTEL_INFO(dev)->gen < 5)
1932                 return;
1933
1934         if (pll == NULL)
1935                 return;
1936
1937         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1938                 return;
1939
1940         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1941                       pll->name, pll->active, pll->on,
1942                       crtc->base.base.id);
1943
1944         if (WARN_ON(pll->active == 0)) {
1945                 assert_shared_dpll_disabled(dev_priv, pll);
1946                 return;
1947         }
1948
1949         assert_shared_dpll_enabled(dev_priv, pll);
1950         WARN_ON(!pll->on);
1951         if (--pll->active)
1952                 return;
1953
1954         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1955         pll->disable(dev_priv, pll);
1956         pll->on = false;
1957
1958         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1959 }
1960
1961 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1962                                            enum pipe pipe)
1963 {
1964         struct drm_device *dev = dev_priv->dev;
1965         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1967         i915_reg_t reg;
1968         uint32_t val, pipeconf_val;
1969
1970         /* PCH only available on ILK+ */
1971         BUG_ON(!HAS_PCH_SPLIT(dev));
1972
1973         /* Make sure PCH DPLL is enabled */
1974         assert_shared_dpll_enabled(dev_priv,
1975                                    intel_crtc_to_shared_dpll(intel_crtc));
1976
1977         /* FDI must be feeding us bits for PCH ports */
1978         assert_fdi_tx_enabled(dev_priv, pipe);
1979         assert_fdi_rx_enabled(dev_priv, pipe);
1980
1981         if (HAS_PCH_CPT(dev)) {
1982                 /* Workaround: Set the timing override bit before enabling the
1983                  * pch transcoder. */
1984                 reg = TRANS_CHICKEN2(pipe);
1985                 val = I915_READ(reg);
1986                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1987                 I915_WRITE(reg, val);
1988         }
1989
1990         reg = PCH_TRANSCONF(pipe);
1991         val = I915_READ(reg);
1992         pipeconf_val = I915_READ(PIPECONF(pipe));
1993
1994         if (HAS_PCH_IBX(dev_priv->dev)) {
1995                 /*
1996                  * Make the BPC in transcoder be consistent with
1997                  * that in pipeconf reg. For HDMI we must use 8bpc
1998                  * here for both 8bpc and 12bpc.
1999                  */
2000                 val &= ~PIPECONF_BPC_MASK;
2001                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2002                         val |= PIPECONF_8BPC;
2003                 else
2004                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2005         }
2006
2007         val &= ~TRANS_INTERLACE_MASK;
2008         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2009                 if (HAS_PCH_IBX(dev_priv->dev) &&
2010                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2011                         val |= TRANS_LEGACY_INTERLACED_ILK;
2012                 else
2013                         val |= TRANS_INTERLACED;
2014         else
2015                 val |= TRANS_PROGRESSIVE;
2016
2017         I915_WRITE(reg, val | TRANS_ENABLE);
2018         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2019                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2020 }
2021
2022 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2023                                       enum transcoder cpu_transcoder)
2024 {
2025         u32 val, pipeconf_val;
2026
2027         /* PCH only available on ILK+ */
2028         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2029
2030         /* FDI must be feeding us bits for PCH ports */
2031         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2032         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2033
2034         /* Workaround: set timing override bit. */
2035         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2036         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2037         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2038
2039         val = TRANS_ENABLE;
2040         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2041
2042         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2043             PIPECONF_INTERLACED_ILK)
2044                 val |= TRANS_INTERLACED;
2045         else
2046                 val |= TRANS_PROGRESSIVE;
2047
2048         I915_WRITE(LPT_TRANSCONF, val);
2049         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2050                 DRM_ERROR("Failed to enable PCH transcoder\n");
2051 }
2052
2053 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2054                                             enum pipe pipe)
2055 {
2056         struct drm_device *dev = dev_priv->dev;
2057         i915_reg_t reg;
2058         uint32_t val;
2059
2060         /* FDI relies on the transcoder */
2061         assert_fdi_tx_disabled(dev_priv, pipe);
2062         assert_fdi_rx_disabled(dev_priv, pipe);
2063
2064         /* Ports must be off as well */
2065         assert_pch_ports_disabled(dev_priv, pipe);
2066
2067         reg = PCH_TRANSCONF(pipe);
2068         val = I915_READ(reg);
2069         val &= ~TRANS_ENABLE;
2070         I915_WRITE(reg, val);
2071         /* wait for PCH transcoder off, transcoder state */
2072         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2073                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2074
2075         if (HAS_PCH_CPT(dev)) {
2076                 /* Workaround: Clear the timing override chicken bit again. */
2077                 reg = TRANS_CHICKEN2(pipe);
2078                 val = I915_READ(reg);
2079                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080                 I915_WRITE(reg, val);
2081         }
2082 }
2083
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2085 {
2086         u32 val;
2087
2088         val = I915_READ(LPT_TRANSCONF);
2089         val &= ~TRANS_ENABLE;
2090         I915_WRITE(LPT_TRANSCONF, val);
2091         /* wait for PCH transcoder off, transcoder state */
2092         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2093                 DRM_ERROR("Failed to disable PCH transcoder\n");
2094
2095         /* Workaround: clear timing override bit. */
2096         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2097         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2098         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2099 }
2100
2101 /**
2102  * intel_enable_pipe - enable a pipe, asserting requirements
2103  * @crtc: crtc responsible for the pipe
2104  *
2105  * Enable @crtc's pipe, making sure that various hardware specific requirements
2106  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2107  */
2108 static void intel_enable_pipe(struct intel_crtc *crtc)
2109 {
2110         struct drm_device *dev = crtc->base.dev;
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112         enum pipe pipe = crtc->pipe;
2113         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2114         enum pipe pch_transcoder;
2115         i915_reg_t reg;
2116         u32 val;
2117
2118         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2119
2120         assert_planes_disabled(dev_priv, pipe);
2121         assert_cursor_disabled(dev_priv, pipe);
2122         assert_sprites_disabled(dev_priv, pipe);
2123
2124         if (HAS_PCH_LPT(dev_priv->dev))
2125                 pch_transcoder = TRANSCODER_A;
2126         else
2127                 pch_transcoder = pipe;
2128
2129         /*
2130          * A pipe without a PLL won't actually be able to drive bits from
2131          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2132          * need the check.
2133          */
2134         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135                 if (crtc->config->has_dsi_encoder)
2136                         assert_dsi_pll_enabled(dev_priv);
2137                 else
2138                         assert_pll_enabled(dev_priv, pipe);
2139         else {
2140                 if (crtc->config->has_pch_encoder) {
2141                         /* if driving the PCH, we need FDI enabled */
2142                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143                         assert_fdi_tx_pll_enabled(dev_priv,
2144                                                   (enum pipe) cpu_transcoder);
2145                 }
2146                 /* FIXME: assert CPU port conditions for SNB+ */
2147         }
2148
2149         reg = PIPECONF(cpu_transcoder);
2150         val = I915_READ(reg);
2151         if (val & PIPECONF_ENABLE) {
2152                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154                 return;
2155         }
2156
2157         I915_WRITE(reg, val | PIPECONF_ENABLE);
2158         POSTING_READ(reg);
2159 }
2160
2161 /**
2162  * intel_disable_pipe - disable a pipe, asserting requirements
2163  * @crtc: crtc whose pipes is to be disabled
2164  *
2165  * Disable the pipe of @crtc, making sure that various hardware
2166  * specific requirements are met, if applicable, e.g. plane
2167  * disabled, panel fitter off, etc.
2168  *
2169  * Will wait until the pipe has shut down before returning.
2170  */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175         enum pipe pipe = crtc->pipe;
2176         i915_reg_t reg;
2177         u32 val;
2178
2179         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181         /*
2182          * Make sure planes won't keep trying to pump pixels to us,
2183          * or we might hang the display.
2184          */
2185         assert_planes_disabled(dev_priv, pipe);
2186         assert_cursor_disabled(dev_priv, pipe);
2187         assert_sprites_disabled(dev_priv, pipe);
2188
2189         reg = PIPECONF(cpu_transcoder);
2190         val = I915_READ(reg);
2191         if ((val & PIPECONF_ENABLE) == 0)
2192                 return;
2193
2194         /*
2195          * Double wide has implications for planes
2196          * so best keep it disabled when not needed.
2197          */
2198         if (crtc->config->double_wide)
2199                 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201         /* Don't disable pipe or pipe PLLs if needed */
2202         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204                 val &= ~PIPECONF_ENABLE;
2205
2206         I915_WRITE(reg, val);
2207         if ((val & PIPECONF_ENABLE) == 0)
2208                 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215                 return true;
2216 #endif
2217         return false;
2218 }
2219
2220 unsigned int
2221 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2222                   uint64_t fb_format_modifier, unsigned int plane)
2223 {
2224         unsigned int tile_height;
2225         uint32_t pixel_bytes;
2226
2227         switch (fb_format_modifier) {
2228         case DRM_FORMAT_MOD_NONE:
2229                 tile_height = 1;
2230                 break;
2231         case I915_FORMAT_MOD_X_TILED:
2232                 tile_height = IS_GEN2(dev) ? 16 : 8;
2233                 break;
2234         case I915_FORMAT_MOD_Y_TILED:
2235                 tile_height = 32;
2236                 break;
2237         case I915_FORMAT_MOD_Yf_TILED:
2238                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2239                 switch (pixel_bytes) {
2240                 default:
2241                 case 1:
2242                         tile_height = 64;
2243                         break;
2244                 case 2:
2245                 case 4:
2246                         tile_height = 32;
2247                         break;
2248                 case 8:
2249                         tile_height = 16;
2250                         break;
2251                 case 16:
2252                         WARN_ONCE(1,
2253                                   "128-bit pixels are not supported for display!");
2254                         tile_height = 16;
2255                         break;
2256                 }
2257                 break;
2258         default:
2259                 MISSING_CASE(fb_format_modifier);
2260                 tile_height = 1;
2261                 break;
2262         }
2263
2264         return tile_height;
2265 }
2266
2267 unsigned int
2268 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2269                       uint32_t pixel_format, uint64_t fb_format_modifier)
2270 {
2271         return ALIGN(height, intel_tile_height(dev, pixel_format,
2272                                                fb_format_modifier, 0));
2273 }
2274
2275 static void
2276 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2277                         const struct drm_plane_state *plane_state)
2278 {
2279         struct intel_rotation_info *info = &view->params.rotation_info;
2280         unsigned int tile_height, tile_pitch;
2281
2282         *view = i915_ggtt_view_normal;
2283
2284         if (!plane_state)
2285                 return;
2286
2287         if (!intel_rotation_90_or_270(plane_state->rotation))
2288                 return;
2289
2290         *view = i915_ggtt_view_rotated;
2291
2292         info->height = fb->height;
2293         info->pixel_format = fb->pixel_format;
2294         info->pitch = fb->pitches[0];
2295         info->uv_offset = fb->offsets[1];
2296         info->fb_modifier = fb->modifier[0];
2297
2298         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2299                                         fb->modifier[0], 0);
2300         tile_pitch = PAGE_SIZE / tile_height;
2301         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2302         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2303         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2304
2305         if (info->pixel_format == DRM_FORMAT_NV12) {
2306                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2307                                                 fb->modifier[0], 1);
2308                 tile_pitch = PAGE_SIZE / tile_height;
2309                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2310                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2311                                                      tile_height);
2312                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2313                                 PAGE_SIZE;
2314         }
2315 }
2316
2317 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318 {
2319         if (INTEL_INFO(dev_priv)->gen >= 9)
2320                 return 256 * 1024;
2321         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322                  IS_VALLEYVIEW(dev_priv))
2323                 return 128 * 1024;
2324         else if (INTEL_INFO(dev_priv)->gen >= 4)
2325                 return 4 * 1024;
2326         else
2327                 return 0;
2328 }
2329
2330 int
2331 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332                            struct drm_framebuffer *fb,
2333                            const struct drm_plane_state *plane_state)
2334 {
2335         struct drm_device *dev = fb->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2338         struct i915_ggtt_view view;
2339         u32 alignment;
2340         int ret;
2341
2342         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2343
2344         switch (fb->modifier[0]) {
2345         case DRM_FORMAT_MOD_NONE:
2346                 alignment = intel_linear_alignment(dev_priv);
2347                 break;
2348         case I915_FORMAT_MOD_X_TILED:
2349                 if (INTEL_INFO(dev)->gen >= 9)
2350                         alignment = 256 * 1024;
2351                 else {
2352                         /* pin() will align the object as required by fence */
2353                         alignment = 0;
2354                 }
2355                 break;
2356         case I915_FORMAT_MOD_Y_TILED:
2357         case I915_FORMAT_MOD_Yf_TILED:
2358                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2359                           "Y tiling bo slipped through, driver bug!\n"))
2360                         return -EINVAL;
2361                 alignment = 1 * 1024 * 1024;
2362                 break;
2363         default:
2364                 MISSING_CASE(fb->modifier[0]);
2365                 return -EINVAL;
2366         }
2367
2368         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369
2370         /* Note that the w/a also requires 64 PTE of padding following the
2371          * bo. We currently fill all unused PTE with the shadow page and so
2372          * we should always have valid PTE following the scanout preventing
2373          * the VT-d warning.
2374          */
2375         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2376                 alignment = 256 * 1024;
2377
2378         /*
2379          * Global gtt pte registers are special registers which actually forward
2380          * writes to a chunk of system memory. Which means that there is no risk
2381          * that the register values disappear as soon as we call
2382          * intel_runtime_pm_put(), so it is correct to wrap only the
2383          * pin/unpin/fence and not more.
2384          */
2385         intel_runtime_pm_get(dev_priv);
2386
2387         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2388                                                    &view);
2389         if (ret)
2390                 goto err_pm;
2391
2392         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393          * fence, whereas 965+ only requires a fence if using
2394          * framebuffer compression.  For simplicity, we always install
2395          * a fence as the cost is not that onerous.
2396          */
2397         if (view.type == I915_GGTT_VIEW_NORMAL) {
2398                 ret = i915_gem_object_get_fence(obj);
2399                 if (ret == -EDEADLK) {
2400                         /*
2401                          * -EDEADLK means there are no free fences
2402                          * no pending flips.
2403                          *
2404                          * This is propagated to atomic, but it uses
2405                          * -EDEADLK to force a locking recovery, so
2406                          * change the returned error to -EBUSY.
2407                          */
2408                         ret = -EBUSY;
2409                         goto err_unpin;
2410                 } else if (ret)
2411                         goto err_unpin;
2412
2413                 i915_gem_object_pin_fence(obj);
2414         }
2415
2416         intel_runtime_pm_put(dev_priv);
2417         return 0;
2418
2419 err_unpin:
2420         i915_gem_object_unpin_from_display_plane(obj, &view);
2421 err_pm:
2422         intel_runtime_pm_put(dev_priv);
2423         return ret;
2424 }
2425
2426 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2427                                const struct drm_plane_state *plane_state)
2428 {
2429         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2430         struct i915_ggtt_view view;
2431
2432         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2433
2434         intel_fill_fb_ggtt_view(&view, fb, plane_state);
2435
2436         if (view.type == I915_GGTT_VIEW_NORMAL)
2437                 i915_gem_object_unpin_fence(obj);
2438
2439         i915_gem_object_unpin_from_display_plane(obj, &view);
2440 }
2441
2442 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2443  * is assumed to be a power-of-two. */
2444 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2445                                              int *x, int *y,
2446                                              unsigned int tiling_mode,
2447                                              unsigned int cpp,
2448                                              unsigned int pitch)
2449 {
2450         if (tiling_mode != I915_TILING_NONE) {
2451                 unsigned int tile_rows, tiles;
2452
2453                 tile_rows = *y / 8;
2454                 *y %= 8;
2455
2456                 tiles = *x / (512/cpp);
2457                 *x %= 512/cpp;
2458
2459                 return tile_rows * pitch * 8 + tiles * 4096;
2460         } else {
2461                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2462                 unsigned int offset;
2463
2464                 offset = *y * pitch + *x * cpp;
2465                 *y = (offset & alignment) / pitch;
2466                 *x = ((offset & alignment) - *y * pitch) / cpp;
2467                 return offset & ~alignment;
2468         }
2469 }
2470
2471 static int i9xx_format_to_fourcc(int format)
2472 {
2473         switch (format) {
2474         case DISPPLANE_8BPP:
2475                 return DRM_FORMAT_C8;
2476         case DISPPLANE_BGRX555:
2477                 return DRM_FORMAT_XRGB1555;
2478         case DISPPLANE_BGRX565:
2479                 return DRM_FORMAT_RGB565;
2480         default:
2481         case DISPPLANE_BGRX888:
2482                 return DRM_FORMAT_XRGB8888;
2483         case DISPPLANE_RGBX888:
2484                 return DRM_FORMAT_XBGR8888;
2485         case DISPPLANE_BGRX101010:
2486                 return DRM_FORMAT_XRGB2101010;
2487         case DISPPLANE_RGBX101010:
2488                 return DRM_FORMAT_XBGR2101010;
2489         }
2490 }
2491
2492 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493 {
2494         switch (format) {
2495         case PLANE_CTL_FORMAT_RGB_565:
2496                 return DRM_FORMAT_RGB565;
2497         default:
2498         case PLANE_CTL_FORMAT_XRGB_8888:
2499                 if (rgb_order) {
2500                         if (alpha)
2501                                 return DRM_FORMAT_ABGR8888;
2502                         else
2503                                 return DRM_FORMAT_XBGR8888;
2504                 } else {
2505                         if (alpha)
2506                                 return DRM_FORMAT_ARGB8888;
2507                         else
2508                                 return DRM_FORMAT_XRGB8888;
2509                 }
2510         case PLANE_CTL_FORMAT_XRGB_2101010:
2511                 if (rgb_order)
2512                         return DRM_FORMAT_XBGR2101010;
2513                 else
2514                         return DRM_FORMAT_XRGB2101010;
2515         }
2516 }
2517
2518 static bool
2519 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520                               struct intel_initial_plane_config *plane_config)
2521 {
2522         struct drm_device *dev = crtc->base.dev;
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         struct drm_i915_gem_object *obj = NULL;
2525         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526         struct drm_framebuffer *fb = &plane_config->fb->base;
2527         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529                                     PAGE_SIZE);
2530
2531         size_aligned -= base_aligned;
2532
2533         if (plane_config->size == 0)
2534                 return false;
2535
2536         /* If the FB is too big, just don't use it since fbdev is not very
2537          * important and we should probably use that space with FBC or other
2538          * features. */
2539         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2540                 return false;
2541
2542         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2543                                                              base_aligned,
2544                                                              base_aligned,
2545                                                              size_aligned);
2546         if (!obj)
2547                 return false;
2548
2549         obj->tiling_mode = plane_config->tiling;
2550         if (obj->tiling_mode == I915_TILING_X)
2551                 obj->stride = fb->pitches[0];
2552
2553         mode_cmd.pixel_format = fb->pixel_format;
2554         mode_cmd.width = fb->width;
2555         mode_cmd.height = fb->height;
2556         mode_cmd.pitches[0] = fb->pitches[0];
2557         mode_cmd.modifier[0] = fb->modifier[0];
2558         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2559
2560         mutex_lock(&dev->struct_mutex);
2561         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2562                                    &mode_cmd, obj)) {
2563                 DRM_DEBUG_KMS("intel fb init failed\n");
2564                 goto out_unref_obj;
2565         }
2566         mutex_unlock(&dev->struct_mutex);
2567
2568         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2569         return true;
2570
2571 out_unref_obj:
2572         drm_gem_object_unreference(&obj->base);
2573         mutex_unlock(&dev->struct_mutex);
2574         return false;
2575 }
2576
2577 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2578 static void
2579 update_state_fb(struct drm_plane *plane)
2580 {
2581         if (plane->fb == plane->state->fb)
2582                 return;
2583
2584         if (plane->state->fb)
2585                 drm_framebuffer_unreference(plane->state->fb);
2586         plane->state->fb = plane->fb;
2587         if (plane->state->fb)
2588                 drm_framebuffer_reference(plane->state->fb);
2589 }
2590
2591 static void
2592 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2593                              struct intel_initial_plane_config *plane_config)
2594 {
2595         struct drm_device *dev = intel_crtc->base.dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct drm_crtc *c;
2598         struct intel_crtc *i;
2599         struct drm_i915_gem_object *obj;
2600         struct drm_plane *primary = intel_crtc->base.primary;
2601         struct drm_plane_state *plane_state = primary->state;
2602         struct drm_framebuffer *fb;
2603
2604         if (!plane_config->fb)
2605                 return;
2606
2607         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2608                 fb = &plane_config->fb->base;
2609                 goto valid_fb;
2610         }
2611
2612         kfree(plane_config->fb);
2613
2614         /*
2615          * Failed to alloc the obj, check to see if we should share
2616          * an fb with another CRTC instead
2617          */
2618         for_each_crtc(dev, c) {
2619                 i = to_intel_crtc(c);
2620
2621                 if (c == &intel_crtc->base)
2622                         continue;
2623
2624                 if (!i->active)
2625                         continue;
2626
2627                 fb = c->primary->fb;
2628                 if (!fb)
2629                         continue;
2630
2631                 obj = intel_fb_obj(fb);
2632                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2633                         drm_framebuffer_reference(fb);
2634                         goto valid_fb;
2635                 }
2636         }
2637
2638         return;
2639
2640 valid_fb:
2641         plane_state->src_x = 0;
2642         plane_state->src_y = 0;
2643         plane_state->src_w = fb->width << 16;
2644         plane_state->src_h = fb->height << 16;
2645
2646         plane_state->crtc_x = 0;
2647         plane_state->crtc_y = 0;
2648         plane_state->crtc_w = fb->width;
2649         plane_state->crtc_h = fb->height;
2650
2651         obj = intel_fb_obj(fb);
2652         if (obj->tiling_mode != I915_TILING_NONE)
2653                 dev_priv->preserve_bios_swizzle = true;
2654
2655         drm_framebuffer_reference(fb);
2656         primary->fb = primary->state->fb = fb;
2657         primary->crtc = primary->state->crtc = &intel_crtc->base;
2658         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2659         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2660 }
2661
2662 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2663                                       struct drm_framebuffer *fb,
2664                                       int x, int y)
2665 {
2666         struct drm_device *dev = crtc->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2669         struct drm_plane *primary = crtc->primary;
2670         bool visible = to_intel_plane_state(primary->state)->visible;
2671         struct drm_i915_gem_object *obj;
2672         int plane = intel_crtc->plane;
2673         unsigned long linear_offset;
2674         u32 dspcntr;
2675         i915_reg_t reg = DSPCNTR(plane);
2676         int pixel_size;
2677
2678         if (!visible || !fb) {
2679                 I915_WRITE(reg, 0);
2680                 if (INTEL_INFO(dev)->gen >= 4)
2681                         I915_WRITE(DSPSURF(plane), 0);
2682                 else
2683                         I915_WRITE(DSPADDR(plane), 0);
2684                 POSTING_READ(reg);
2685                 return;
2686         }
2687
2688         obj = intel_fb_obj(fb);
2689         if (WARN_ON(obj == NULL))
2690                 return;
2691
2692         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2693
2694         dspcntr = DISPPLANE_GAMMA_ENABLE;
2695
2696         dspcntr |= DISPLAY_PLANE_ENABLE;
2697
2698         if (INTEL_INFO(dev)->gen < 4) {
2699                 if (intel_crtc->pipe == PIPE_B)
2700                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2701
2702                 /* pipesrc and dspsize control the size that is scaled from,
2703                  * which should always be the user's requested size.
2704                  */
2705                 I915_WRITE(DSPSIZE(plane),
2706                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2707                            (intel_crtc->config->pipe_src_w - 1));
2708                 I915_WRITE(DSPPOS(plane), 0);
2709         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2710                 I915_WRITE(PRIMSIZE(plane),
2711                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2712                            (intel_crtc->config->pipe_src_w - 1));
2713                 I915_WRITE(PRIMPOS(plane), 0);
2714                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2715         }
2716
2717         switch (fb->pixel_format) {
2718         case DRM_FORMAT_C8:
2719                 dspcntr |= DISPPLANE_8BPP;
2720                 break;
2721         case DRM_FORMAT_XRGB1555:
2722                 dspcntr |= DISPPLANE_BGRX555;
2723                 break;
2724         case DRM_FORMAT_RGB565:
2725                 dspcntr |= DISPPLANE_BGRX565;
2726                 break;
2727         case DRM_FORMAT_XRGB8888:
2728                 dspcntr |= DISPPLANE_BGRX888;
2729                 break;
2730         case DRM_FORMAT_XBGR8888:
2731                 dspcntr |= DISPPLANE_RGBX888;
2732                 break;
2733         case DRM_FORMAT_XRGB2101010:
2734                 dspcntr |= DISPPLANE_BGRX101010;
2735                 break;
2736         case DRM_FORMAT_XBGR2101010:
2737                 dspcntr |= DISPPLANE_RGBX101010;
2738                 break;
2739         default:
2740                 BUG();
2741         }
2742
2743         if (INTEL_INFO(dev)->gen >= 4 &&
2744             obj->tiling_mode != I915_TILING_NONE)
2745                 dspcntr |= DISPPLANE_TILED;
2746
2747         if (IS_G4X(dev))
2748                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2749
2750         linear_offset = y * fb->pitches[0] + x * pixel_size;
2751
2752         if (INTEL_INFO(dev)->gen >= 4) {
2753                 intel_crtc->dspaddr_offset =
2754                         intel_gen4_compute_page_offset(dev_priv,
2755                                                        &x, &y, obj->tiling_mode,
2756                                                        pixel_size,
2757                                                        fb->pitches[0]);
2758                 linear_offset -= intel_crtc->dspaddr_offset;
2759         } else {
2760                 intel_crtc->dspaddr_offset = linear_offset;
2761         }
2762
2763         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2764                 dspcntr |= DISPPLANE_ROTATE_180;
2765
2766                 x += (intel_crtc->config->pipe_src_w - 1);
2767                 y += (intel_crtc->config->pipe_src_h - 1);
2768
2769                 /* Finding the last pixel of the last line of the display
2770                 data and adding to linear_offset*/
2771                 linear_offset +=
2772                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2773                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2774         }
2775
2776         intel_crtc->adjusted_x = x;
2777         intel_crtc->adjusted_y = y;
2778
2779         I915_WRITE(reg, dspcntr);
2780
2781         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782         if (INTEL_INFO(dev)->gen >= 4) {
2783                 I915_WRITE(DSPSURF(plane),
2784                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787         } else
2788                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789         POSTING_READ(reg);
2790 }
2791
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793                                           struct drm_framebuffer *fb,
2794                                           int x, int y)
2795 {
2796         struct drm_device *dev = crtc->dev;
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         struct drm_plane *primary = crtc->primary;
2800         bool visible = to_intel_plane_state(primary->state)->visible;
2801         struct drm_i915_gem_object *obj;
2802         int plane = intel_crtc->plane;
2803         unsigned long linear_offset;
2804         u32 dspcntr;
2805         i915_reg_t reg = DSPCNTR(plane);
2806         int pixel_size;
2807
2808         if (!visible || !fb) {
2809                 I915_WRITE(reg, 0);
2810                 I915_WRITE(DSPSURF(plane), 0);
2811                 POSTING_READ(reg);
2812                 return;
2813         }
2814
2815         obj = intel_fb_obj(fb);
2816         if (WARN_ON(obj == NULL))
2817                 return;
2818
2819         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2820
2821         dspcntr = DISPPLANE_GAMMA_ENABLE;
2822
2823         dspcntr |= DISPLAY_PLANE_ENABLE;
2824
2825         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2826                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2827
2828         switch (fb->pixel_format) {
2829         case DRM_FORMAT_C8:
2830                 dspcntr |= DISPPLANE_8BPP;
2831                 break;
2832         case DRM_FORMAT_RGB565:
2833                 dspcntr |= DISPPLANE_BGRX565;
2834                 break;
2835         case DRM_FORMAT_XRGB8888:
2836                 dspcntr |= DISPPLANE_BGRX888;
2837                 break;
2838         case DRM_FORMAT_XBGR8888:
2839                 dspcntr |= DISPPLANE_RGBX888;
2840                 break;
2841         case DRM_FORMAT_XRGB2101010:
2842                 dspcntr |= DISPPLANE_BGRX101010;
2843                 break;
2844         case DRM_FORMAT_XBGR2101010:
2845                 dspcntr |= DISPPLANE_RGBX101010;
2846                 break;
2847         default:
2848                 BUG();
2849         }
2850
2851         if (obj->tiling_mode != I915_TILING_NONE)
2852                 dspcntr |= DISPPLANE_TILED;
2853
2854         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2855                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2856
2857         linear_offset = y * fb->pitches[0] + x * pixel_size;
2858         intel_crtc->dspaddr_offset =
2859                 intel_gen4_compute_page_offset(dev_priv,
2860                                                &x, &y, obj->tiling_mode,
2861                                                pixel_size,
2862                                                fb->pitches[0]);
2863         linear_offset -= intel_crtc->dspaddr_offset;
2864         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2865                 dspcntr |= DISPPLANE_ROTATE_180;
2866
2867                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2868                         x += (intel_crtc->config->pipe_src_w - 1);
2869                         y += (intel_crtc->config->pipe_src_h - 1);
2870
2871                         /* Finding the last pixel of the last line of the display
2872                         data and adding to linear_offset*/
2873                         linear_offset +=
2874                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2875                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2876                 }
2877         }
2878
2879         intel_crtc->adjusted_x = x;
2880         intel_crtc->adjusted_y = y;
2881
2882         I915_WRITE(reg, dspcntr);
2883
2884         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2885         I915_WRITE(DSPSURF(plane),
2886                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2887         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2888                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2889         } else {
2890                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2891                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2892         }
2893         POSTING_READ(reg);
2894 }
2895
2896 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2897                               uint32_t pixel_format)
2898 {
2899         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2900
2901         /*
2902          * The stride is either expressed as a multiple of 64 bytes
2903          * chunks for linear buffers or in number of tiles for tiled
2904          * buffers.
2905          */
2906         switch (fb_modifier) {
2907         case DRM_FORMAT_MOD_NONE:
2908                 return 64;
2909         case I915_FORMAT_MOD_X_TILED:
2910                 if (INTEL_INFO(dev)->gen == 2)
2911                         return 128;
2912                 return 512;
2913         case I915_FORMAT_MOD_Y_TILED:
2914                 /* No need to check for old gens and Y tiling since this is
2915                  * about the display engine and those will be blocked before
2916                  * we get here.
2917                  */
2918                 return 128;
2919         case I915_FORMAT_MOD_Yf_TILED:
2920                 if (bits_per_pixel == 8)
2921                         return 64;
2922                 else
2923                         return 128;
2924         default:
2925                 MISSING_CASE(fb_modifier);
2926                 return 64;
2927         }
2928 }
2929
2930 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2931                            struct drm_i915_gem_object *obj,
2932                            unsigned int plane)
2933 {
2934         struct i915_ggtt_view view;
2935         struct i915_vma *vma;
2936         u64 offset;
2937
2938         intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2939                                 intel_plane->base.state);
2940
2941         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2942         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2943                 view.type))
2944                 return -1;
2945
2946         offset = vma->node.start;
2947
2948         if (plane == 1) {
2949                 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2950                           PAGE_SIZE;
2951         }
2952
2953         WARN_ON(upper_32_bits(offset));
2954
2955         return lower_32_bits(offset);
2956 }
2957
2958 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962
2963         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2964         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2965         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2966 }
2967
2968 /*
2969  * This function detaches (aka. unbinds) unused scalers in hardware
2970  */
2971 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2972 {
2973         struct intel_crtc_scaler_state *scaler_state;
2974         int i;
2975
2976         scaler_state = &intel_crtc->config->scaler_state;
2977
2978         /* loop through and disable scalers that aren't in use */
2979         for (i = 0; i < intel_crtc->num_scalers; i++) {
2980                 if (!scaler_state->scalers[i].in_use)
2981                         skl_detach_scaler(intel_crtc, i);
2982         }
2983 }
2984
2985 u32 skl_plane_ctl_format(uint32_t pixel_format)
2986 {
2987         switch (pixel_format) {
2988         case DRM_FORMAT_C8:
2989                 return PLANE_CTL_FORMAT_INDEXED;
2990         case DRM_FORMAT_RGB565:
2991                 return PLANE_CTL_FORMAT_RGB_565;
2992         case DRM_FORMAT_XBGR8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2994         case DRM_FORMAT_XRGB8888:
2995                 return PLANE_CTL_FORMAT_XRGB_8888;
2996         /*
2997          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2998          * to be already pre-multiplied. We need to add a knob (or a different
2999          * DRM_FORMAT) for user-space to configure that.
3000          */
3001         case DRM_FORMAT_ABGR8888:
3002                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3003                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3004         case DRM_FORMAT_ARGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888 |
3006                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3007         case DRM_FORMAT_XRGB2101010:
3008                 return PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_XBGR2101010:
3010                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3011         case DRM_FORMAT_YUYV:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3013         case DRM_FORMAT_YVYU:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3015         case DRM_FORMAT_UYVY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3017         case DRM_FORMAT_VYUY:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3019         default:
3020                 MISSING_CASE(pixel_format);
3021         }
3022
3023         return 0;
3024 }
3025
3026 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3027 {
3028         switch (fb_modifier) {
3029         case DRM_FORMAT_MOD_NONE:
3030                 break;
3031         case I915_FORMAT_MOD_X_TILED:
3032                 return PLANE_CTL_TILED_X;
3033         case I915_FORMAT_MOD_Y_TILED:
3034                 return PLANE_CTL_TILED_Y;
3035         case I915_FORMAT_MOD_Yf_TILED:
3036                 return PLANE_CTL_TILED_YF;
3037         default:
3038                 MISSING_CASE(fb_modifier);
3039         }
3040
3041         return 0;
3042 }
3043
3044 u32 skl_plane_ctl_rotation(unsigned int rotation)
3045 {
3046         switch (rotation) {
3047         case BIT(DRM_ROTATE_0):
3048                 break;
3049         /*
3050          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3051          * while i915 HW rotation is clockwise, thats why this swapping.
3052          */
3053         case BIT(DRM_ROTATE_90):
3054                 return PLANE_CTL_ROTATE_270;
3055         case BIT(DRM_ROTATE_180):
3056                 return PLANE_CTL_ROTATE_180;
3057         case BIT(DRM_ROTATE_270):
3058                 return PLANE_CTL_ROTATE_90;
3059         default:
3060                 MISSING_CASE(rotation);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3067                                          struct drm_framebuffer *fb,
3068                                          int x, int y)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073         struct drm_plane *plane = crtc->primary;
3074         bool visible = to_intel_plane_state(plane->state)->visible;
3075         struct drm_i915_gem_object *obj;
3076         int pipe = intel_crtc->pipe;
3077         u32 plane_ctl, stride_div, stride;
3078         u32 tile_height, plane_offset, plane_size;
3079         unsigned int rotation;
3080         int x_offset, y_offset;
3081         u32 surf_addr;
3082         struct intel_crtc_state *crtc_state = intel_crtc->config;
3083         struct intel_plane_state *plane_state;
3084         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3085         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3086         int scaler_id = -1;
3087
3088         plane_state = to_intel_plane_state(plane->state);
3089
3090         if (!visible || !fb) {
3091                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3092                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3093                 POSTING_READ(PLANE_CTL(pipe, 0));
3094                 return;
3095         }
3096
3097         plane_ctl = PLANE_CTL_ENABLE |
3098                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3099                     PLANE_CTL_PIPE_CSC_ENABLE;
3100
3101         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3102         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3103         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3104
3105         rotation = plane->state->rotation;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         obj = intel_fb_obj(fb);
3109         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3110                                                fb->pixel_format);
3111         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3112
3113         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3114
3115         scaler_id = plane_state->scaler_id;
3116         src_x = plane_state->src.x1 >> 16;
3117         src_y = plane_state->src.y1 >> 16;
3118         src_w = drm_rect_width(&plane_state->src) >> 16;
3119         src_h = drm_rect_height(&plane_state->src) >> 16;
3120         dst_x = plane_state->dst.x1;
3121         dst_y = plane_state->dst.y1;
3122         dst_w = drm_rect_width(&plane_state->dst);
3123         dst_h = drm_rect_height(&plane_state->dst);
3124
3125         WARN_ON(x != src_x || y != src_y);
3126
3127         if (intel_rotation_90_or_270(rotation)) {
3128                 /* stride = Surface height in tiles */
3129                 tile_height = intel_tile_height(dev, fb->pixel_format,
3130                                                 fb->modifier[0], 0);
3131                 stride = DIV_ROUND_UP(fb->height, tile_height);
3132                 x_offset = stride * tile_height - y - src_h;
3133                 y_offset = x;
3134                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3135         } else {
3136                 stride = fb->pitches[0] / stride_div;
3137                 x_offset = x;
3138                 y_offset = y;
3139                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3140         }
3141         plane_offset = y_offset << 16 | x_offset;
3142
3143         intel_crtc->adjusted_x = x_offset;
3144         intel_crtc->adjusted_y = y_offset;
3145
3146         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3147         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3148         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3149         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3150
3151         if (scaler_id >= 0) {
3152                 uint32_t ps_ctrl = 0;
3153
3154                 WARN_ON(!dst_w || !dst_h);
3155                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3156                         crtc_state->scaler_state.scalers[scaler_id].mode;
3157                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3158                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3159                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3160                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3161                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3162         } else {
3163                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3164         }
3165
3166         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3167
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178
3179         if (dev_priv->fbc.deactivate)
3180                 dev_priv->fbc.deactivate(dev_priv);
3181
3182         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3183
3184         return 0;
3185 }
3186
3187 static void intel_complete_page_flips(struct drm_device *dev)
3188 {
3189         struct drm_crtc *crtc;
3190
3191         for_each_crtc(dev, crtc) {
3192                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193                 enum plane plane = intel_crtc->plane;
3194
3195                 intel_prepare_page_flip(dev, plane);
3196                 intel_finish_page_flip_plane(dev, plane);
3197         }
3198 }
3199
3200 static void intel_update_primary_planes(struct drm_device *dev)
3201 {
3202         struct drm_crtc *crtc;
3203
3204         for_each_crtc(dev, crtc) {
3205                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3206                 struct intel_plane_state *plane_state;
3207
3208                 drm_modeset_lock_crtc(crtc, &plane->base);
3209                 plane_state = to_intel_plane_state(plane->base.state);
3210
3211                 if (crtc->state->active && plane_state->base.fb)
3212                         plane->commit_plane(&plane->base, plane_state);
3213
3214                 drm_modeset_unlock_crtc(crtc);
3215         }
3216 }
3217
3218 void intel_prepare_reset(struct drm_device *dev)
3219 {
3220         /* no reset support for gen2 */
3221         if (IS_GEN2(dev))
3222                 return;
3223
3224         /* reset doesn't touch the display */
3225         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3226                 return;
3227
3228         drm_modeset_lock_all(dev);
3229         /*
3230          * Disabling the crtcs gracefully seems nicer. Also the
3231          * g33 docs say we should at least disable all the planes.
3232          */
3233         intel_display_suspend(dev);
3234 }
3235
3236 void intel_finish_reset(struct drm_device *dev)
3237 {
3238         struct drm_i915_private *dev_priv = to_i915(dev);
3239
3240         /*
3241          * Flips in the rings will be nuked by the reset,
3242          * so complete all pending flips so that user space
3243          * will get its events and not get stuck.
3244          */
3245         intel_complete_page_flips(dev);
3246
3247         /* no reset support for gen2 */
3248         if (IS_GEN2(dev))
3249                 return;
3250
3251         /* reset doesn't touch the display */
3252         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3253                 /*
3254                  * Flips in the rings have been nuked by the reset,
3255                  * so update the base address of all primary
3256                  * planes to the the last fb to make sure we're
3257                  * showing the correct fb after a reset.
3258                  *
3259                  * FIXME: Atomic will make this obsolete since we won't schedule
3260                  * CS-based flips (which might get lost in gpu resets) any more.
3261                  */
3262                 intel_update_primary_planes(dev);
3263                 return;
3264         }
3265
3266         /*
3267          * The display has been reset as well,
3268          * so need a full re-initialization.
3269          */
3270         intel_runtime_pm_disable_interrupts(dev_priv);
3271         intel_runtime_pm_enable_interrupts(dev_priv);
3272
3273         intel_modeset_init_hw(dev);
3274
3275         spin_lock_irq(&dev_priv->irq_lock);
3276         if (dev_priv->display.hpd_irq_setup)
3277                 dev_priv->display.hpd_irq_setup(dev);
3278         spin_unlock_irq(&dev_priv->irq_lock);
3279
3280         intel_display_resume(dev);
3281
3282         intel_hpd_init(dev_priv);
3283
3284         drm_modeset_unlock_all(dev);
3285 }
3286
3287 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3288 {
3289         struct drm_device *dev = crtc->dev;
3290         struct drm_i915_private *dev_priv = dev->dev_private;
3291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292         bool pending;
3293
3294         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3295             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3296                 return false;
3297
3298         spin_lock_irq(&dev->event_lock);
3299         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3300         spin_unlock_irq(&dev->event_lock);
3301
3302         return pending;
3303 }
3304
3305 static void intel_update_pipe_config(struct intel_crtc *crtc,
3306                                      struct intel_crtc_state *old_crtc_state)
3307 {
3308         struct drm_device *dev = crtc->base.dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         struct intel_crtc_state *pipe_config =
3311                 to_intel_crtc_state(crtc->base.state);
3312
3313         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3314         crtc->base.mode = crtc->base.state->mode;
3315
3316         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3317                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3318                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3319
3320         if (HAS_DDI(dev))
3321                 intel_set_pipe_csc(&crtc->base);
3322
3323         /*
3324          * Update pipe size and adjust fitter if needed: the reason for this is
3325          * that in compute_mode_changes we check the native mode (not the pfit
3326          * mode) to see if we can flip rather than do a full mode set. In the
3327          * fastboot case, we'll flip, but if we don't update the pipesrc and
3328          * pfit state, we'll end up with a big fb scanned out into the wrong
3329          * sized surface.
3330          */
3331
3332         I915_WRITE(PIPESRC(crtc->pipe),
3333                    ((pipe_config->pipe_src_w - 1) << 16) |
3334                    (pipe_config->pipe_src_h - 1));
3335
3336         /* on skylake this is done by detaching scalers */
3337         if (INTEL_INFO(dev)->gen >= 9) {
3338                 skl_detach_scalers(crtc);
3339
3340                 if (pipe_config->pch_pfit.enabled)
3341                         skylake_pfit_enable(crtc);
3342         } else if (HAS_PCH_SPLIT(dev)) {
3343                 if (pipe_config->pch_pfit.enabled)
3344                         ironlake_pfit_enable(crtc);
3345                 else if (old_crtc_state->pch_pfit.enabled)
3346                         ironlake_pfit_disable(crtc, true);
3347         }
3348 }
3349
3350 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         int pipe = intel_crtc->pipe;
3356         i915_reg_t reg;
3357         u32 temp;
3358
3359         /* enable normal train */
3360         reg = FDI_TX_CTL(pipe);
3361         temp = I915_READ(reg);
3362         if (IS_IVYBRIDGE(dev)) {
3363                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3364                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3365         } else {
3366                 temp &= ~FDI_LINK_TRAIN_NONE;
3367                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3368         }
3369         I915_WRITE(reg, temp);
3370
3371         reg = FDI_RX_CTL(pipe);
3372         temp = I915_READ(reg);
3373         if (HAS_PCH_CPT(dev)) {
3374                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3376         } else {
3377                 temp &= ~FDI_LINK_TRAIN_NONE;
3378                 temp |= FDI_LINK_TRAIN_NONE;
3379         }
3380         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3381
3382         /* wait one idle pattern time */
3383         POSTING_READ(reg);
3384         udelay(1000);
3385
3386         /* IVB wants error correction enabled */
3387         if (IS_IVYBRIDGE(dev))
3388                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3389                            FDI_FE_ERRC_ENABLE);
3390 }
3391
3392 /* The FDI link training functions for ILK/Ibexpeak. */
3393 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3394 {
3395         struct drm_device *dev = crtc->dev;
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398         int pipe = intel_crtc->pipe;
3399         i915_reg_t reg;
3400         u32 temp, tries;
3401
3402         /* FDI needs bits from pipe first */
3403         assert_pipe_enabled(dev_priv, pipe);
3404
3405         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406            for train result */
3407         reg = FDI_RX_IMR(pipe);
3408         temp = I915_READ(reg);
3409         temp &= ~FDI_RX_SYMBOL_LOCK;
3410         temp &= ~FDI_RX_BIT_LOCK;
3411         I915_WRITE(reg, temp);
3412         I915_READ(reg);
3413         udelay(150);
3414
3415         /* enable CPU FDI TX and PCH FDI RX */
3416         reg = FDI_TX_CTL(pipe);
3417         temp = I915_READ(reg);
3418         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420         temp &= ~FDI_LINK_TRAIN_NONE;
3421         temp |= FDI_LINK_TRAIN_PATTERN_1;
3422         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3423
3424         reg = FDI_RX_CTL(pipe);
3425         temp = I915_READ(reg);
3426         temp &= ~FDI_LINK_TRAIN_NONE;
3427         temp |= FDI_LINK_TRAIN_PATTERN_1;
3428         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430         POSTING_READ(reg);
3431         udelay(150);
3432
3433         /* Ironlake workaround, enable clock pointer after FDI enable*/
3434         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436                    FDI_RX_PHASE_SYNC_POINTER_EN);
3437
3438         reg = FDI_RX_IIR(pipe);
3439         for (tries = 0; tries < 5; tries++) {
3440                 temp = I915_READ(reg);
3441                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443                 if ((temp & FDI_RX_BIT_LOCK)) {
3444                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3445                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446                         break;
3447                 }
3448         }
3449         if (tries == 5)
3450                 DRM_ERROR("FDI train 1 fail!\n");
3451
3452         /* Train 2 */
3453         reg = FDI_TX_CTL(pipe);
3454         temp = I915_READ(reg);
3455         temp &= ~FDI_LINK_TRAIN_NONE;
3456         temp |= FDI_LINK_TRAIN_PATTERN_2;
3457         I915_WRITE(reg, temp);
3458
3459         reg = FDI_RX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         temp &= ~FDI_LINK_TRAIN_NONE;
3462         temp |= FDI_LINK_TRAIN_PATTERN_2;
3463         I915_WRITE(reg, temp);
3464
3465         POSTING_READ(reg);
3466         udelay(150);
3467
3468         reg = FDI_RX_IIR(pipe);
3469         for (tries = 0; tries < 5; tries++) {
3470                 temp = I915_READ(reg);
3471                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473                 if (temp & FDI_RX_SYMBOL_LOCK) {
3474                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3476                         break;
3477                 }
3478         }
3479         if (tries == 5)
3480                 DRM_ERROR("FDI train 2 fail!\n");
3481
3482         DRM_DEBUG_KMS("FDI train done\n");
3483
3484 }
3485
3486 static const int snb_b_fdi_train_param[] = {
3487         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491 };
3492
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499         int pipe = intel_crtc->pipe;
3500         i915_reg_t reg;
3501         u32 temp, i, retry;
3502
3503         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504            for train result */
3505         reg = FDI_RX_IMR(pipe);
3506         temp = I915_READ(reg);
3507         temp &= ~FDI_RX_SYMBOL_LOCK;
3508         temp &= ~FDI_RX_BIT_LOCK;
3509         I915_WRITE(reg, temp);
3510
3511         POSTING_READ(reg);
3512         udelay(150);
3513
3514         /* enable CPU FDI TX and PCH FDI RX */
3515         reg = FDI_TX_CTL(pipe);
3516         temp = I915_READ(reg);
3517         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3518         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3519         temp &= ~FDI_LINK_TRAIN_NONE;
3520         temp |= FDI_LINK_TRAIN_PATTERN_1;
3521         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522         /* SNB-B */
3523         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3524         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3525
3526         I915_WRITE(FDI_RX_MISC(pipe),
3527                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3528
3529         reg = FDI_RX_CTL(pipe);
3530         temp = I915_READ(reg);
3531         if (HAS_PCH_CPT(dev)) {
3532                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3533                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534         } else {
3535                 temp &= ~FDI_LINK_TRAIN_NONE;
3536                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537         }
3538         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3539
3540         POSTING_READ(reg);
3541         udelay(150);
3542
3543         for (i = 0; i < 4; i++) {
3544                 reg = FDI_TX_CTL(pipe);
3545                 temp = I915_READ(reg);
3546                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3547                 temp |= snb_b_fdi_train_param[i];
3548                 I915_WRITE(reg, temp);
3549
3550                 POSTING_READ(reg);
3551                 udelay(500);
3552
3553                 for (retry = 0; retry < 5; retry++) {
3554                         reg = FDI_RX_IIR(pipe);
3555                         temp = I915_READ(reg);
3556                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3557                         if (temp & FDI_RX_BIT_LOCK) {
3558                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3559                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3560                                 break;
3561                         }
3562                         udelay(50);
3563                 }
3564                 if (retry < 5)
3565                         break;
3566         }
3567         if (i == 4)
3568                 DRM_ERROR("FDI train 1 fail!\n");
3569
3570         /* Train 2 */
3571         reg = FDI_TX_CTL(pipe);
3572         temp = I915_READ(reg);
3573         temp &= ~FDI_LINK_TRAIN_NONE;
3574         temp |= FDI_LINK_TRAIN_PATTERN_2;
3575         if (IS_GEN6(dev)) {
3576                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577                 /* SNB-B */
3578                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3579         }
3580         I915_WRITE(reg, temp);
3581
3582         reg = FDI_RX_CTL(pipe);
3583         temp = I915_READ(reg);
3584         if (HAS_PCH_CPT(dev)) {
3585                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3586                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3587         } else {
3588                 temp &= ~FDI_LINK_TRAIN_NONE;
3589                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590         }
3591         I915_WRITE(reg, temp);
3592
3593         POSTING_READ(reg);
3594         udelay(150);
3595
3596         for (i = 0; i < 4; i++) {
3597                 reg = FDI_TX_CTL(pipe);
3598                 temp = I915_READ(reg);
3599                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3600                 temp |= snb_b_fdi_train_param[i];
3601                 I915_WRITE(reg, temp);
3602
3603                 POSTING_READ(reg);
3604                 udelay(500);
3605
3606                 for (retry = 0; retry < 5; retry++) {
3607                         reg = FDI_RX_IIR(pipe);
3608                         temp = I915_READ(reg);
3609                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3610                         if (temp & FDI_RX_SYMBOL_LOCK) {
3611                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3612                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3613                                 break;
3614                         }
3615                         udelay(50);
3616                 }
3617                 if (retry < 5)
3618                         break;
3619         }
3620         if (i == 4)
3621                 DRM_ERROR("FDI train 2 fail!\n");
3622
3623         DRM_DEBUG_KMS("FDI train done.\n");
3624 }
3625
3626 /* Manual link training for Ivy Bridge A0 parts */
3627 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3628 {
3629         struct drm_device *dev = crtc->dev;
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632         int pipe = intel_crtc->pipe;
3633         i915_reg_t reg;
3634         u32 temp, i, j;
3635
3636         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3637            for train result */
3638         reg = FDI_RX_IMR(pipe);
3639         temp = I915_READ(reg);
3640         temp &= ~FDI_RX_SYMBOL_LOCK;
3641         temp &= ~FDI_RX_BIT_LOCK;
3642         I915_WRITE(reg, temp);
3643
3644         POSTING_READ(reg);
3645         udelay(150);
3646
3647         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3648                       I915_READ(FDI_RX_IIR(pipe)));
3649
3650         /* Try each vswing and preemphasis setting twice before moving on */
3651         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3652                 /* disable first in case we need to retry */
3653                 reg = FDI_TX_CTL(pipe);
3654                 temp = I915_READ(reg);
3655                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3656                 temp &= ~FDI_TX_ENABLE;
3657                 I915_WRITE(reg, temp);
3658
3659                 reg = FDI_RX_CTL(pipe);
3660                 temp = I915_READ(reg);
3661                 temp &= ~FDI_LINK_TRAIN_AUTO;
3662                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3663                 temp &= ~FDI_RX_ENABLE;
3664                 I915_WRITE(reg, temp);
3665
3666                 /* enable CPU FDI TX and PCH FDI RX */
3667                 reg = FDI_TX_CTL(pipe);
3668                 temp = I915_READ(reg);
3669                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3670                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3671                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3672                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3673                 temp |= snb_b_fdi_train_param[j/2];
3674                 temp |= FDI_COMPOSITE_SYNC;
3675                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3676
3677                 I915_WRITE(FDI_RX_MISC(pipe),
3678                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3679
3680                 reg = FDI_RX_CTL(pipe);
3681                 temp = I915_READ(reg);
3682                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3683                 temp |= FDI_COMPOSITE_SYNC;
3684                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685
3686                 POSTING_READ(reg);
3687                 udelay(1); /* should be 0.5us */
3688
3689                 for (i = 0; i < 4; i++) {
3690                         reg = FDI_RX_IIR(pipe);
3691                         temp = I915_READ(reg);
3692                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3693
3694                         if (temp & FDI_RX_BIT_LOCK ||
3695                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3696                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3697                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3698                                               i);
3699                                 break;
3700                         }
3701                         udelay(1); /* should be 0.5us */
3702                 }
3703                 if (i == 4) {
3704                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3705                         continue;
3706                 }
3707
3708                 /* Train 2 */
3709                 reg = FDI_TX_CTL(pipe);
3710                 temp = I915_READ(reg);
3711                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3712                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3713                 I915_WRITE(reg, temp);
3714
3715                 reg = FDI_RX_CTL(pipe);
3716                 temp = I915_READ(reg);
3717                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3718                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3719                 I915_WRITE(reg, temp);
3720
3721                 POSTING_READ(reg);
3722                 udelay(2); /* should be 1.5us */
3723
3724                 for (i = 0; i < 4; i++) {
3725                         reg = FDI_RX_IIR(pipe);
3726                         temp = I915_READ(reg);
3727                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3728
3729                         if (temp & FDI_RX_SYMBOL_LOCK ||
3730                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3731                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3732                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3733                                               i);
3734                                 goto train_done;
3735                         }
3736                         udelay(2); /* should be 1.5us */
3737                 }
3738                 if (i == 4)
3739                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3740         }
3741
3742 train_done:
3743         DRM_DEBUG_KMS("FDI train done.\n");
3744 }
3745
3746 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3747 {
3748         struct drm_device *dev = intel_crtc->base.dev;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         int pipe = intel_crtc->pipe;
3751         i915_reg_t reg;
3752         u32 temp;
3753
3754         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3755         reg = FDI_RX_CTL(pipe);
3756         temp = I915_READ(reg);
3757         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3758         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3759         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3760         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3761
3762         POSTING_READ(reg);
3763         udelay(200);
3764
3765         /* Switch from Rawclk to PCDclk */
3766         temp = I915_READ(reg);
3767         I915_WRITE(reg, temp | FDI_PCDCLK);
3768
3769         POSTING_READ(reg);
3770         udelay(200);
3771
3772         /* Enable CPU FDI TX PLL, always on for Ironlake */
3773         reg = FDI_TX_CTL(pipe);
3774         temp = I915_READ(reg);
3775         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3776                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3777
3778                 POSTING_READ(reg);
3779                 udelay(100);
3780         }
3781 }
3782
3783 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3784 {
3785         struct drm_device *dev = intel_crtc->base.dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         int pipe = intel_crtc->pipe;
3788         i915_reg_t reg;
3789         u32 temp;
3790
3791         /* Switch from PCDclk to Rawclk */
3792         reg = FDI_RX_CTL(pipe);
3793         temp = I915_READ(reg);
3794         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3795
3796         /* Disable CPU FDI TX PLL */
3797         reg = FDI_TX_CTL(pipe);
3798         temp = I915_READ(reg);
3799         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3800
3801         POSTING_READ(reg);
3802         udelay(100);
3803
3804         reg = FDI_RX_CTL(pipe);
3805         temp = I915_READ(reg);
3806         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3807
3808         /* Wait for the clocks to turn off. */
3809         POSTING_READ(reg);
3810         udelay(100);
3811 }
3812
3813 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_i915_private *dev_priv = dev->dev_private;
3817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818         int pipe = intel_crtc->pipe;
3819         i915_reg_t reg;
3820         u32 temp;
3821
3822         /* disable CPU FDI tx and PCH FDI rx */
3823         reg = FDI_TX_CTL(pipe);
3824         temp = I915_READ(reg);
3825         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3826         POSTING_READ(reg);
3827
3828         reg = FDI_RX_CTL(pipe);
3829         temp = I915_READ(reg);
3830         temp &= ~(0x7 << 16);
3831         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3832         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833
3834         POSTING_READ(reg);
3835         udelay(100);
3836
3837         /* Ironlake workaround, disable clock pointer after downing FDI */
3838         if (HAS_PCH_IBX(dev))
3839                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3840
3841         /* still set train pattern 1 */
3842         reg = FDI_TX_CTL(pipe);
3843         temp = I915_READ(reg);
3844         temp &= ~FDI_LINK_TRAIN_NONE;
3845         temp |= FDI_LINK_TRAIN_PATTERN_1;
3846         I915_WRITE(reg, temp);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         if (HAS_PCH_CPT(dev)) {
3851                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3852                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3853         } else {
3854                 temp &= ~FDI_LINK_TRAIN_NONE;
3855                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3856         }
3857         /* BPC in FDI rx is consistent with that in PIPECONF */
3858         temp &= ~(0x07 << 16);
3859         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3860         I915_WRITE(reg, temp);
3861
3862         POSTING_READ(reg);
3863         udelay(100);
3864 }
3865
3866 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3867 {
3868         struct intel_crtc *crtc;
3869
3870         /* Note that we don't need to be called with mode_config.lock here
3871          * as our list of CRTC objects is static for the lifetime of the
3872          * device and so cannot disappear as we iterate. Similarly, we can
3873          * happily treat the predicates as racy, atomic checks as userspace
3874          * cannot claim and pin a new fb without at least acquring the
3875          * struct_mutex and so serialising with us.
3876          */
3877         for_each_intel_crtc(dev, crtc) {
3878                 if (atomic_read(&crtc->unpin_work_count) == 0)
3879                         continue;
3880
3881                 if (crtc->unpin_work)
3882                         intel_wait_for_vblank(dev, crtc->pipe);
3883
3884                 return true;
3885         }
3886
3887         return false;
3888 }
3889
3890 static void page_flip_completed(struct intel_crtc *intel_crtc)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3893         struct intel_unpin_work *work = intel_crtc->unpin_work;
3894
3895         /* ensure that the unpin work is consistent wrt ->pending. */
3896         smp_rmb();
3897         intel_crtc->unpin_work = NULL;
3898
3899         if (work->event)
3900                 drm_send_vblank_event(intel_crtc->base.dev,
3901                                       intel_crtc->pipe,
3902                                       work->event);
3903
3904         drm_crtc_vblank_put(&intel_crtc->base);
3905
3906         wake_up_all(&dev_priv->pending_flip_queue);
3907         queue_work(dev_priv->wq, &work->work);
3908
3909         trace_i915_flip_complete(intel_crtc->plane,
3910                                  work->pending_flip_obj);
3911 }
3912
3913 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3914 {
3915         struct drm_device *dev = crtc->dev;
3916         struct drm_i915_private *dev_priv = dev->dev_private;
3917         long ret;
3918
3919         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3920
3921         ret = wait_event_interruptible_timeout(
3922                                         dev_priv->pending_flip_queue,
3923                                         !intel_crtc_has_pending_flip(crtc),
3924                                         60*HZ);
3925
3926         if (ret < 0)
3927                 return ret;
3928
3929         if (ret == 0) {
3930                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932                 spin_lock_irq(&dev->event_lock);
3933                 if (intel_crtc->unpin_work) {
3934                         WARN_ONCE(1, "Removing stuck page flip\n");
3935                         page_flip_completed(intel_crtc);
3936                 }
3937                 spin_unlock_irq(&dev->event_lock);
3938         }
3939
3940         return 0;
3941 }
3942
3943 /* Program iCLKIP clock to the desired frequency */
3944 static void lpt_program_iclkip(struct drm_crtc *crtc)
3945 {
3946         struct drm_device *dev = crtc->dev;
3947         struct drm_i915_private *dev_priv = dev->dev_private;
3948         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3949         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3950         u32 temp;
3951
3952         mutex_lock(&dev_priv->sb_lock);
3953
3954         /* It is necessary to ungate the pixclk gate prior to programming
3955          * the divisors, and gate it back when it is done.
3956          */
3957         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3958
3959         /* Disable SSCCTL */
3960         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3961                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3962                                 SBI_SSCCTL_DISABLE,
3963                         SBI_ICLK);
3964
3965         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3966         if (clock == 20000) {
3967                 auxdiv = 1;
3968                 divsel = 0x41;
3969                 phaseinc = 0x20;
3970         } else {
3971                 /* The iCLK virtual clock root frequency is in MHz,
3972                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3973                  * divisors, it is necessary to divide one by another, so we
3974                  * convert the virtual clock precision to KHz here for higher
3975                  * precision.
3976                  */
3977                 u32 iclk_virtual_root_freq = 172800 * 1000;
3978                 u32 iclk_pi_range = 64;
3979                 u32 desired_divisor, msb_divisor_value, pi_value;
3980
3981                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3982                 msb_divisor_value = desired_divisor / iclk_pi_range;
3983                 pi_value = desired_divisor % iclk_pi_range;
3984
3985                 auxdiv = 0;
3986                 divsel = msb_divisor_value - 2;
3987                 phaseinc = pi_value;
3988         }
3989
3990         /* This should not happen with any sane values */
3991         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3992                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3993         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3994                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3995
3996         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3997                         clock,
3998                         auxdiv,
3999                         divsel,
4000                         phasedir,
4001                         phaseinc);
4002
4003         /* Program SSCDIVINTPHASE6 */
4004         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4005         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4006         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4007         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4008         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4009         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4010         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4011         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4012
4013         /* Program SSCAUXDIV */
4014         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4015         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4016         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4017         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4018
4019         /* Enable modulator and associated divider */
4020         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4021         temp &= ~SBI_SSCCTL_DISABLE;
4022         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4023
4024         /* Wait for initialization time */
4025         udelay(24);
4026
4027         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4028
4029         mutex_unlock(&dev_priv->sb_lock);
4030 }
4031
4032 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4033                                                 enum pipe pch_transcoder)
4034 {
4035         struct drm_device *dev = crtc->base.dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4038
4039         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4040                    I915_READ(HTOTAL(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4042                    I915_READ(HBLANK(cpu_transcoder)));
4043         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4044                    I915_READ(HSYNC(cpu_transcoder)));
4045
4046         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4047                    I915_READ(VTOTAL(cpu_transcoder)));
4048         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4049                    I915_READ(VBLANK(cpu_transcoder)));
4050         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4051                    I915_READ(VSYNC(cpu_transcoder)));
4052         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4053                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4054 }
4055
4056 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4057 {
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059         uint32_t temp;
4060
4061         temp = I915_READ(SOUTH_CHICKEN1);
4062         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4063                 return;
4064
4065         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4066         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4067
4068         temp &= ~FDI_BC_BIFURCATION_SELECT;
4069         if (enable)
4070                 temp |= FDI_BC_BIFURCATION_SELECT;
4071
4072         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4073         I915_WRITE(SOUTH_CHICKEN1, temp);
4074         POSTING_READ(SOUTH_CHICKEN1);
4075 }
4076
4077 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4078 {
4079         struct drm_device *dev = intel_crtc->base.dev;
4080
4081         switch (intel_crtc->pipe) {
4082         case PIPE_A:
4083                 break;
4084         case PIPE_B:
4085                 if (intel_crtc->config->fdi_lanes > 2)
4086                         cpt_set_fdi_bc_bifurcation(dev, false);
4087                 else
4088                         cpt_set_fdi_bc_bifurcation(dev, true);
4089
4090                 break;
4091         case PIPE_C:
4092                 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094                 break;
4095         default:
4096                 BUG();
4097         }
4098 }
4099
4100 /* Return which DP Port should be selected for Transcoder DP control */
4101 static enum port
4102 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct intel_encoder *encoder;
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder) {
4108                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4109                     encoder->type == INTEL_OUTPUT_EDP)
4110                         return enc_to_dig_port(&encoder->base)->port;
4111         }
4112
4113         return -1;
4114 }
4115
4116 /*
4117  * Enable PCH resources required for PCH ports:
4118  *   - PCH PLLs
4119  *   - FDI training & RX/TX
4120  *   - update transcoder timings
4121  *   - DP transcoding bits
4122  *   - transcoder
4123  */
4124 static void ironlake_pch_enable(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         int pipe = intel_crtc->pipe;
4130         u32 temp;
4131
4132         assert_pch_transcoder_disabled(dev_priv, pipe);
4133
4134         if (IS_IVYBRIDGE(dev))
4135                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4136
4137         /* Write the TU size bits before fdi link training, so that error
4138          * detection works. */
4139         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4140                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4141
4142         /*
4143          * Sometimes spurious CPU pipe underruns happen during FDI
4144          * training, at least with VGA+HDMI cloning. Suppress them.
4145          */
4146         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4147
4148         /* For PCH output, training FDI link */
4149         dev_priv->display.fdi_link_train(crtc);
4150
4151         /* We need to program the right clock selection before writing the pixel
4152          * mutliplier into the DPLL. */
4153         if (HAS_PCH_CPT(dev)) {
4154                 u32 sel;
4155
4156                 temp = I915_READ(PCH_DPLL_SEL);
4157                 temp |= TRANS_DPLL_ENABLE(pipe);
4158                 sel = TRANS_DPLLB_SEL(pipe);
4159                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4160                         temp |= sel;
4161                 else
4162                         temp &= ~sel;
4163                 I915_WRITE(PCH_DPLL_SEL, temp);
4164         }
4165
4166         /* XXX: pch pll's can be enabled any time before we enable the PCH
4167          * transcoder, and we actually should do this to not upset any PCH
4168          * transcoder that already use the clock when we share it.
4169          *
4170          * Note that enable_shared_dpll tries to do the right thing, but
4171          * get_shared_dpll unconditionally resets the pll - we need that to have
4172          * the right LVDS enable sequence. */
4173         intel_enable_shared_dpll(intel_crtc);
4174
4175         /* set transcoder timing, panel must allow it */
4176         assert_panel_unlocked(dev_priv, pipe);
4177         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4178
4179         intel_fdi_normal_train(crtc);
4180
4181         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4182
4183         /* For PCH DP, enable TRANS_DP_CTL */
4184         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4185                 const struct drm_display_mode *adjusted_mode =
4186                         &intel_crtc->config->base.adjusted_mode;
4187                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4188                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4189                 temp = I915_READ(reg);
4190                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4191                           TRANS_DP_SYNC_MASK |
4192                           TRANS_DP_BPC_MASK);
4193                 temp |= TRANS_DP_OUTPUT_ENABLE;
4194                 temp |= bpc << 9; /* same format but at 11:9 */
4195
4196                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4197                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4198                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4199                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4200
4201                 switch (intel_trans_dp_port_sel(crtc)) {
4202                 case PORT_B:
4203                         temp |= TRANS_DP_PORT_SEL_B;
4204                         break;
4205                 case PORT_C:
4206                         temp |= TRANS_DP_PORT_SEL_C;
4207                         break;
4208                 case PORT_D:
4209                         temp |= TRANS_DP_PORT_SEL_D;
4210                         break;
4211                 default:
4212                         BUG();
4213                 }
4214
4215                 I915_WRITE(reg, temp);
4216         }
4217
4218         ironlake_enable_pch_transcoder(dev_priv, pipe);
4219 }
4220
4221 static void lpt_pch_enable(struct drm_crtc *crtc)
4222 {
4223         struct drm_device *dev = crtc->dev;
4224         struct drm_i915_private *dev_priv = dev->dev_private;
4225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4227
4228         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4229
4230         lpt_program_iclkip(crtc);
4231
4232         /* Set transcoder timing. */
4233         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4234
4235         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4236 }
4237
4238 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239                                                 struct intel_crtc_state *crtc_state)
4240 {
4241         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4242         struct intel_shared_dpll *pll;
4243         struct intel_shared_dpll_config *shared_dpll;
4244         enum intel_dpll_id i;
4245         int max = dev_priv->num_shared_dpll;
4246
4247         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4248
4249         if (HAS_PCH_IBX(dev_priv->dev)) {
4250                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4251                 i = (enum intel_dpll_id) crtc->pipe;
4252                 pll = &dev_priv->shared_dplls[i];
4253
4254                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4255                               crtc->base.base.id, pll->name);
4256
4257                 WARN_ON(shared_dpll[i].crtc_mask);
4258
4259                 goto found;
4260         }
4261
4262         if (IS_BROXTON(dev_priv->dev)) {
4263                 /* PLL is attached to port in bxt */
4264                 struct intel_encoder *encoder;
4265                 struct intel_digital_port *intel_dig_port;
4266
4267                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4268                 if (WARN_ON(!encoder))
4269                         return NULL;
4270
4271                 intel_dig_port = enc_to_dig_port(&encoder->base);
4272                 /* 1:1 mapping between ports and PLLs */
4273                 i = (enum intel_dpll_id)intel_dig_port->port;
4274                 pll = &dev_priv->shared_dplls[i];
4275                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4276                         crtc->base.base.id, pll->name);
4277                 WARN_ON(shared_dpll[i].crtc_mask);
4278
4279                 goto found;
4280         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4281                 /* Do not consider SPLL */
4282                 max = 2;
4283
4284         for (i = 0; i < max; i++) {
4285                 pll = &dev_priv->shared_dplls[i];
4286
4287                 /* Only want to check enabled timings first */
4288                 if (shared_dpll[i].crtc_mask == 0)
4289                         continue;
4290
4291                 if (memcmp(&crtc_state->dpll_hw_state,
4292                            &shared_dpll[i].hw_state,
4293                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4294                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4295                                       crtc->base.base.id, pll->name,
4296                                       shared_dpll[i].crtc_mask,
4297                                       pll->active);
4298                         goto found;
4299                 }
4300         }
4301
4302         /* Ok no matching timings, maybe there's a free one? */
4303         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4304                 pll = &dev_priv->shared_dplls[i];
4305                 if (shared_dpll[i].crtc_mask == 0) {
4306                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4307                                       crtc->base.base.id, pll->name);
4308                         goto found;
4309                 }
4310         }
4311
4312         return NULL;
4313
4314 found:
4315         if (shared_dpll[i].crtc_mask == 0)
4316                 shared_dpll[i].hw_state =
4317                         crtc_state->dpll_hw_state;
4318
4319         crtc_state->shared_dpll = i;
4320         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4321                          pipe_name(crtc->pipe));
4322
4323         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4324
4325         return pll;
4326 }
4327
4328 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4329 {
4330         struct drm_i915_private *dev_priv = to_i915(state->dev);
4331         struct intel_shared_dpll_config *shared_dpll;
4332         struct intel_shared_dpll *pll;
4333         enum intel_dpll_id i;
4334
4335         if (!to_intel_atomic_state(state)->dpll_set)
4336                 return;
4337
4338         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4339         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4340                 pll = &dev_priv->shared_dplls[i];
4341                 pll->config = shared_dpll[i];
4342         }
4343 }
4344
4345 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4346 {
4347         struct drm_i915_private *dev_priv = dev->dev_private;
4348         i915_reg_t dslreg = PIPEDSL(pipe);
4349         u32 temp;
4350
4351         temp = I915_READ(dslreg);
4352         udelay(500);
4353         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4354                 if (wait_for(I915_READ(dslreg) != temp, 5))
4355                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4356         }
4357 }
4358
4359 static int
4360 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4361                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4362                   int src_w, int src_h, int dst_w, int dst_h)
4363 {
4364         struct intel_crtc_scaler_state *scaler_state =
4365                 &crtc_state->scaler_state;
4366         struct intel_crtc *intel_crtc =
4367                 to_intel_crtc(crtc_state->base.crtc);
4368         int need_scaling;
4369
4370         need_scaling = intel_rotation_90_or_270(rotation) ?
4371                 (src_h != dst_w || src_w != dst_h):
4372                 (src_w != dst_w || src_h != dst_h);
4373
4374         /*
4375          * if plane is being disabled or scaler is no more required or force detach
4376          *  - free scaler binded to this plane/crtc
4377          *  - in order to do this, update crtc->scaler_usage
4378          *
4379          * Here scaler state in crtc_state is set free so that
4380          * scaler can be assigned to other user. Actual register
4381          * update to free the scaler is done in plane/panel-fit programming.
4382          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4383          */
4384         if (force_detach || !need_scaling) {
4385                 if (*scaler_id >= 0) {
4386                         scaler_state->scaler_users &= ~(1 << scaler_user);
4387                         scaler_state->scalers[*scaler_id].in_use = 0;
4388
4389                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4390                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4391                                 intel_crtc->pipe, scaler_user, *scaler_id,
4392                                 scaler_state->scaler_users);
4393                         *scaler_id = -1;
4394                 }
4395                 return 0;
4396         }
4397
4398         /* range checks */
4399         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4400                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4401
4402                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4403                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4404                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4405                         "size is out of scaler range\n",
4406                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4407                 return -EINVAL;
4408         }
4409
4410         /* mark this plane as a scaler user in crtc_state */
4411         scaler_state->scaler_users |= (1 << scaler_user);
4412         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4413                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4414                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4415                 scaler_state->scaler_users);
4416
4417         return 0;
4418 }
4419
4420 /**
4421  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4422  *
4423  * @state: crtc's scaler state
4424  *
4425  * Return
4426  *     0 - scaler_usage updated successfully
4427  *    error - requested scaling cannot be supported or other error condition
4428  */
4429 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4430 {
4431         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4432         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4433
4434         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4435                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4436
4437         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4438                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4439                 state->pipe_src_w, state->pipe_src_h,
4440                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4441 }
4442
4443 /**
4444  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4445  *
4446  * @state: crtc's scaler state
4447  * @plane_state: atomic plane state to update
4448  *
4449  * Return
4450  *     0 - scaler_usage updated successfully
4451  *    error - requested scaling cannot be supported or other error condition
4452  */
4453 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4454                                    struct intel_plane_state *plane_state)
4455 {
4456
4457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4458         struct intel_plane *intel_plane =
4459                 to_intel_plane(plane_state->base.plane);
4460         struct drm_framebuffer *fb = plane_state->base.fb;
4461         int ret;
4462
4463         bool force_detach = !fb || !plane_state->visible;
4464
4465         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4466                       intel_plane->base.base.id, intel_crtc->pipe,
4467                       drm_plane_index(&intel_plane->base));
4468
4469         ret = skl_update_scaler(crtc_state, force_detach,
4470                                 drm_plane_index(&intel_plane->base),
4471                                 &plane_state->scaler_id,
4472                                 plane_state->base.rotation,
4473                                 drm_rect_width(&plane_state->src) >> 16,
4474                                 drm_rect_height(&plane_state->src) >> 16,
4475                                 drm_rect_width(&plane_state->dst),
4476                                 drm_rect_height(&plane_state->dst));
4477
4478         if (ret || plane_state->scaler_id < 0)
4479                 return ret;
4480
4481         /* check colorkey */
4482         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4483                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4484                               intel_plane->base.base.id);
4485                 return -EINVAL;
4486         }
4487
4488         /* Check src format */
4489         switch (fb->pixel_format) {
4490         case DRM_FORMAT_RGB565:
4491         case DRM_FORMAT_XBGR8888:
4492         case DRM_FORMAT_XRGB8888:
4493         case DRM_FORMAT_ABGR8888:
4494         case DRM_FORMAT_ARGB8888:
4495         case DRM_FORMAT_XRGB2101010:
4496         case DRM_FORMAT_XBGR2101010:
4497         case DRM_FORMAT_YUYV:
4498         case DRM_FORMAT_YVYU:
4499         case DRM_FORMAT_UYVY:
4500         case DRM_FORMAT_VYUY:
4501                 break;
4502         default:
4503                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4504                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4505                 return -EINVAL;
4506         }
4507
4508         return 0;
4509 }
4510
4511 static void skylake_scaler_disable(struct intel_crtc *crtc)
4512 {
4513         int i;
4514
4515         for (i = 0; i < crtc->num_scalers; i++)
4516                 skl_detach_scaler(crtc, i);
4517 }
4518
4519 static void skylake_pfit_enable(struct intel_crtc *crtc)
4520 {
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         int pipe = crtc->pipe;
4524         struct intel_crtc_scaler_state *scaler_state =
4525                 &crtc->config->scaler_state;
4526
4527         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4528
4529         if (crtc->config->pch_pfit.enabled) {
4530                 int id;
4531
4532                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4533                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4534                         return;
4535                 }
4536
4537                 id = scaler_state->scaler_id;
4538                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4539                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4540                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4541                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4542
4543                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4544         }
4545 }
4546
4547 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4548 {
4549         struct drm_device *dev = crtc->base.dev;
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         int pipe = crtc->pipe;
4552
4553         if (crtc->config->pch_pfit.enabled) {
4554                 /* Force use of hard-coded filter coefficients
4555                  * as some pre-programmed values are broken,
4556                  * e.g. x201.
4557                  */
4558                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4559                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4560                                                  PF_PIPE_SEL_IVB(pipe));
4561                 else
4562                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4563                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4564                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4565         }
4566 }
4567
4568 void hsw_enable_ips(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572
4573         if (!crtc->config->ips_enabled)
4574                 return;
4575
4576         /* We can only enable IPS after we enable a plane and wait for a vblank */
4577         intel_wait_for_vblank(dev, crtc->pipe);
4578
4579         assert_plane_enabled(dev_priv, crtc->plane);
4580         if (IS_BROADWELL(dev)) {
4581                 mutex_lock(&dev_priv->rps.hw_lock);
4582                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4583                 mutex_unlock(&dev_priv->rps.hw_lock);
4584                 /* Quoting Art Runyan: "its not safe to expect any particular
4585                  * value in IPS_CTL bit 31 after enabling IPS through the
4586                  * mailbox." Moreover, the mailbox may return a bogus state,
4587                  * so we need to just enable it and continue on.
4588                  */
4589         } else {
4590                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4591                 /* The bit only becomes 1 in the next vblank, so this wait here
4592                  * is essentially intel_wait_for_vblank. If we don't have this
4593                  * and don't wait for vblanks until the end of crtc_enable, then
4594                  * the HW state readout code will complain that the expected
4595                  * IPS_CTL value is not the one we read. */
4596                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4597                         DRM_ERROR("Timed out waiting for IPS enable\n");
4598         }
4599 }
4600
4601 void hsw_disable_ips(struct intel_crtc *crtc)
4602 {
4603         struct drm_device *dev = crtc->base.dev;
4604         struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606         if (!crtc->config->ips_enabled)
4607                 return;
4608
4609         assert_plane_enabled(dev_priv, crtc->plane);
4610         if (IS_BROADWELL(dev)) {
4611                 mutex_lock(&dev_priv->rps.hw_lock);
4612                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4613                 mutex_unlock(&dev_priv->rps.hw_lock);
4614                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4615                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4616                         DRM_ERROR("Timed out waiting for IPS disable\n");
4617         } else {
4618                 I915_WRITE(IPS_CTL, 0);
4619                 POSTING_READ(IPS_CTL);
4620         }
4621
4622         /* We need to wait for a vblank before we can disable the plane. */
4623         intel_wait_for_vblank(dev, crtc->pipe);
4624 }
4625
4626 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4627 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4628 {
4629         struct drm_device *dev = crtc->dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632         enum pipe pipe = intel_crtc->pipe;
4633         int i;
4634         bool reenable_ips = false;
4635
4636         /* The clocks have to be on to load the palette. */
4637         if (!crtc->state->active)
4638                 return;
4639
4640         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4641                 if (intel_crtc->config->has_dsi_encoder)
4642                         assert_dsi_pll_enabled(dev_priv);
4643                 else
4644                         assert_pll_enabled(dev_priv, pipe);
4645         }
4646
4647         /* Workaround : Do not read or write the pipe palette/gamma data while
4648          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4649          */
4650         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4651             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4652              GAMMA_MODE_MODE_SPLIT)) {
4653                 hsw_disable_ips(intel_crtc);
4654                 reenable_ips = true;
4655         }
4656
4657         for (i = 0; i < 256; i++) {
4658                 i915_reg_t palreg;
4659
4660                 if (HAS_GMCH_DISPLAY(dev))
4661                         palreg = PALETTE(pipe, i);
4662                 else
4663                         palreg = LGC_PALETTE(pipe, i);
4664
4665                 I915_WRITE(palreg,
4666                            (intel_crtc->lut_r[i] << 16) |
4667                            (intel_crtc->lut_g[i] << 8) |
4668                            intel_crtc->lut_b[i]);
4669         }
4670
4671         if (reenable_ips)
4672                 hsw_enable_ips(intel_crtc);
4673 }
4674
4675 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4676 {
4677         if (intel_crtc->overlay) {
4678                 struct drm_device *dev = intel_crtc->base.dev;
4679                 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681                 mutex_lock(&dev->struct_mutex);
4682                 dev_priv->mm.interruptible = false;
4683                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4684                 dev_priv->mm.interruptible = true;
4685                 mutex_unlock(&dev->struct_mutex);
4686         }
4687
4688         /* Let userspace switch the overlay on again. In most cases userspace
4689          * has to recompute where to put it anyway.
4690          */
4691 }
4692
4693 /**
4694  * intel_post_enable_primary - Perform operations after enabling primary plane
4695  * @crtc: the CRTC whose primary plane was just enabled
4696  *
4697  * Performs potentially sleeping operations that must be done after the primary
4698  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4699  * called due to an explicit primary plane update, or due to an implicit
4700  * re-enable that is caused when a sprite plane is updated to no longer
4701  * completely hide the primary plane.
4702  */
4703 static void
4704 intel_post_enable_primary(struct drm_crtc *crtc)
4705 {
4706         struct drm_device *dev = crtc->dev;
4707         struct drm_i915_private *dev_priv = dev->dev_private;
4708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709         int pipe = intel_crtc->pipe;
4710
4711         /*
4712          * FIXME IPS should be fine as long as one plane is
4713          * enabled, but in practice it seems to have problems
4714          * when going from primary only to sprite only and vice
4715          * versa.
4716          */
4717         hsw_enable_ips(intel_crtc);
4718
4719         /*
4720          * Gen2 reports pipe underruns whenever all planes are disabled.
4721          * So don't enable underrun reporting before at least some planes
4722          * are enabled.
4723          * FIXME: Need to fix the logic to work when we turn off all planes
4724          * but leave the pipe running.
4725          */
4726         if (IS_GEN2(dev))
4727                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4728
4729         /* Underruns don't always raise interrupts, so check manually. */
4730         intel_check_cpu_fifo_underruns(dev_priv);
4731         intel_check_pch_fifo_underruns(dev_priv);
4732 }
4733
4734 /**
4735  * intel_pre_disable_primary - Perform operations before disabling primary plane
4736  * @crtc: the CRTC whose primary plane is to be disabled
4737  *
4738  * Performs potentially sleeping operations that must be done before the
4739  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4740  * be called due to an explicit primary plane update, or due to an implicit
4741  * disable that is caused when a sprite plane completely hides the primary
4742  * plane.
4743  */
4744 static void
4745 intel_pre_disable_primary(struct drm_crtc *crtc)
4746 {
4747         struct drm_device *dev = crtc->dev;
4748         struct drm_i915_private *dev_priv = dev->dev_private;
4749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750         int pipe = intel_crtc->pipe;
4751
4752         /*
4753          * Gen2 reports pipe underruns whenever all planes are disabled.
4754          * So diasble underrun reporting before all the planes get disabled.
4755          * FIXME: Need to fix the logic to work when we turn off all planes
4756          * but leave the pipe running.
4757          */
4758         if (IS_GEN2(dev))
4759                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4760
4761         /*
4762          * Vblank time updates from the shadow to live plane control register
4763          * are blocked if the memory self-refresh mode is active at that
4764          * moment. So to make sure the plane gets truly disabled, disable
4765          * first the self-refresh mode. The self-refresh enable bit in turn
4766          * will be checked/applied by the HW only at the next frame start
4767          * event which is after the vblank start event, so we need to have a
4768          * wait-for-vblank between disabling the plane and the pipe.
4769          */
4770         if (HAS_GMCH_DISPLAY(dev)) {
4771                 intel_set_memory_cxsr(dev_priv, false);
4772                 dev_priv->wm.vlv.cxsr = false;
4773                 intel_wait_for_vblank(dev, pipe);
4774         }
4775
4776         /*
4777          * FIXME IPS should be fine as long as one plane is
4778          * enabled, but in practice it seems to have problems
4779          * when going from primary only to sprite only and vice
4780          * versa.
4781          */
4782         hsw_disable_ips(intel_crtc);
4783 }
4784
4785 static void intel_post_plane_update(struct intel_crtc *crtc)
4786 {
4787         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4788         struct intel_crtc_state *pipe_config =
4789                 to_intel_crtc_state(crtc->base.state);
4790         struct drm_device *dev = crtc->base.dev;
4791
4792         if (atomic->wait_vblank)
4793                 intel_wait_for_vblank(dev, crtc->pipe);
4794
4795         intel_frontbuffer_flip(dev, atomic->fb_bits);
4796
4797         crtc->wm.cxsr_allowed = true;
4798
4799         if (pipe_config->wm_changed && pipe_config->base.active)
4800                 intel_update_watermarks(&crtc->base);
4801
4802         if (atomic->update_fbc)
4803                 intel_fbc_update(crtc);
4804
4805         if (atomic->post_enable_primary)
4806                 intel_post_enable_primary(&crtc->base);
4807
4808         memset(atomic, 0, sizeof(*atomic));
4809 }
4810
4811 static void intel_pre_plane_update(struct intel_crtc *crtc)
4812 {
4813         struct drm_device *dev = crtc->base.dev;
4814         struct drm_i915_private *dev_priv = dev->dev_private;
4815         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4816         struct intel_crtc_state *pipe_config =
4817                 to_intel_crtc_state(crtc->base.state);
4818
4819         if (atomic->disable_fbc)
4820                 intel_fbc_deactivate(crtc);
4821
4822         if (crtc->atomic.disable_ips)
4823                 hsw_disable_ips(crtc);
4824
4825         if (atomic->pre_disable_primary)
4826                 intel_pre_disable_primary(&crtc->base);
4827
4828         if (pipe_config->disable_cxsr) {
4829                 crtc->wm.cxsr_allowed = false;
4830                 intel_set_memory_cxsr(dev_priv, false);
4831         }
4832
4833         if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4834                 intel_update_watermarks(&crtc->base);
4835 }
4836
4837 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4838 {
4839         struct drm_device *dev = crtc->dev;
4840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4841         struct drm_plane *p;
4842         int pipe = intel_crtc->pipe;
4843
4844         intel_crtc_dpms_overlay_disable(intel_crtc);
4845
4846         drm_for_each_plane_mask(p, dev, plane_mask)
4847                 to_intel_plane(p)->disable_plane(p, crtc);
4848
4849         /*
4850          * FIXME: Once we grow proper nuclear flip support out of this we need
4851          * to compute the mask of flip planes precisely. For the time being
4852          * consider this a flip to a NULL plane.
4853          */
4854         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4855 }
4856
4857 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4858 {
4859         struct drm_device *dev = crtc->dev;
4860         struct drm_i915_private *dev_priv = dev->dev_private;
4861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862         struct intel_encoder *encoder;
4863         int pipe = intel_crtc->pipe;
4864
4865         if (WARN_ON(intel_crtc->active))
4866                 return;
4867
4868         if (intel_crtc->config->has_pch_encoder)
4869                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4870
4871         if (intel_crtc->config->has_pch_encoder)
4872                 intel_prepare_shared_dpll(intel_crtc);
4873
4874         if (intel_crtc->config->has_dp_encoder)
4875                 intel_dp_set_m_n(intel_crtc, M1_N1);
4876
4877         intel_set_pipe_timings(intel_crtc);
4878
4879         if (intel_crtc->config->has_pch_encoder) {
4880                 intel_cpu_transcoder_set_m_n(intel_crtc,
4881                                      &intel_crtc->config->fdi_m_n, NULL);
4882         }
4883
4884         ironlake_set_pipeconf(crtc);
4885
4886         intel_crtc->active = true;
4887
4888         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4889
4890         for_each_encoder_on_crtc(dev, crtc, encoder)
4891                 if (encoder->pre_enable)
4892                         encoder->pre_enable(encoder);
4893
4894         if (intel_crtc->config->has_pch_encoder) {
4895                 /* Note: FDI PLL enabling _must_ be done before we enable the
4896                  * cpu pipes, hence this is separate from all the other fdi/pch
4897                  * enabling. */
4898                 ironlake_fdi_pll_enable(intel_crtc);
4899         } else {
4900                 assert_fdi_tx_disabled(dev_priv, pipe);
4901                 assert_fdi_rx_disabled(dev_priv, pipe);
4902         }
4903
4904         ironlake_pfit_enable(intel_crtc);
4905
4906         /*
4907          * On ILK+ LUT must be loaded before the pipe is running but with
4908          * clocks enabled
4909          */
4910         intel_crtc_load_lut(crtc);
4911
4912         intel_update_watermarks(crtc);
4913         intel_enable_pipe(intel_crtc);
4914
4915         if (intel_crtc->config->has_pch_encoder)
4916                 ironlake_pch_enable(crtc);
4917
4918         assert_vblank_disabled(crtc);
4919         drm_crtc_vblank_on(crtc);
4920
4921         for_each_encoder_on_crtc(dev, crtc, encoder)
4922                 encoder->enable(encoder);
4923
4924         if (HAS_PCH_CPT(dev))
4925                 cpt_verify_modeset(dev, intel_crtc->pipe);
4926
4927         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4928         if (intel_crtc->config->has_pch_encoder)
4929                 intel_wait_for_vblank(dev, pipe);
4930         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4931
4932         intel_fbc_enable(intel_crtc);
4933 }
4934
4935 /* IPS only exists on ULT machines and is tied to pipe A. */
4936 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4937 {
4938         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4939 }
4940
4941 static void haswell_crtc_enable(struct drm_crtc *crtc)
4942 {
4943         struct drm_device *dev = crtc->dev;
4944         struct drm_i915_private *dev_priv = dev->dev_private;
4945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4946         struct intel_encoder *encoder;
4947         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4948         struct intel_crtc_state *pipe_config =
4949                 to_intel_crtc_state(crtc->state);
4950
4951         if (WARN_ON(intel_crtc->active))
4952                 return;
4953
4954         if (intel_crtc->config->has_pch_encoder)
4955                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4956                                                       false);
4957
4958         if (intel_crtc_to_shared_dpll(intel_crtc))
4959                 intel_enable_shared_dpll(intel_crtc);
4960
4961         if (intel_crtc->config->has_dp_encoder)
4962                 intel_dp_set_m_n(intel_crtc, M1_N1);
4963
4964         intel_set_pipe_timings(intel_crtc);
4965
4966         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4967                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4968                            intel_crtc->config->pixel_multiplier - 1);
4969         }
4970
4971         if (intel_crtc->config->has_pch_encoder) {
4972                 intel_cpu_transcoder_set_m_n(intel_crtc,
4973                                      &intel_crtc->config->fdi_m_n, NULL);
4974         }
4975
4976         haswell_set_pipeconf(crtc);
4977
4978         intel_set_pipe_csc(crtc);
4979
4980         intel_crtc->active = true;
4981
4982         if (intel_crtc->config->has_pch_encoder)
4983                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4984         else
4985                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4986
4987         for_each_encoder_on_crtc(dev, crtc, encoder) {
4988                 if (encoder->pre_enable)
4989                         encoder->pre_enable(encoder);
4990         }
4991
4992         if (intel_crtc->config->has_pch_encoder)
4993                 dev_priv->display.fdi_link_train(crtc);
4994
4995         if (!intel_crtc->config->has_dsi_encoder)
4996                 intel_ddi_enable_pipe_clock(intel_crtc);
4997
4998         if (INTEL_INFO(dev)->gen >= 9)
4999                 skylake_pfit_enable(intel_crtc);
5000         else
5001                 ironlake_pfit_enable(intel_crtc);
5002
5003         /*
5004          * On ILK+ LUT must be loaded before the pipe is running but with
5005          * clocks enabled
5006          */
5007         intel_crtc_load_lut(crtc);
5008
5009         intel_ddi_set_pipe_settings(crtc);
5010         if (!intel_crtc->config->has_dsi_encoder)
5011                 intel_ddi_enable_transcoder_func(crtc);
5012
5013         intel_update_watermarks(crtc);
5014         intel_enable_pipe(intel_crtc);
5015
5016         if (intel_crtc->config->has_pch_encoder)
5017                 lpt_pch_enable(crtc);
5018
5019         if (intel_crtc->config->dp_encoder_is_mst)
5020                 intel_ddi_set_vc_payload_alloc(crtc, true);
5021
5022         assert_vblank_disabled(crtc);
5023         drm_crtc_vblank_on(crtc);
5024
5025         for_each_encoder_on_crtc(dev, crtc, encoder) {
5026                 encoder->enable(encoder);
5027                 intel_opregion_notify_encoder(encoder, true);
5028         }
5029
5030         if (intel_crtc->config->has_pch_encoder) {
5031                 intel_wait_for_vblank(dev, pipe);
5032                 intel_wait_for_vblank(dev, pipe);
5033                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5034                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5035                                                       true);
5036         }
5037
5038         /* If we change the relative order between pipe/planes enabling, we need
5039          * to change the workaround. */
5040         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5041         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5042                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5043                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5044         }
5045
5046         intel_fbc_enable(intel_crtc);
5047 }
5048
5049 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5050 {
5051         struct drm_device *dev = crtc->base.dev;
5052         struct drm_i915_private *dev_priv = dev->dev_private;
5053         int pipe = crtc->pipe;
5054
5055         /* To avoid upsetting the power well on haswell only disable the pfit if
5056          * it's in use. The hw state code will make sure we get this right. */
5057         if (force || crtc->config->pch_pfit.enabled) {
5058                 I915_WRITE(PF_CTL(pipe), 0);
5059                 I915_WRITE(PF_WIN_POS(pipe), 0);
5060                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5061         }
5062 }
5063
5064 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5065 {
5066         struct drm_device *dev = crtc->dev;
5067         struct drm_i915_private *dev_priv = dev->dev_private;
5068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069         struct intel_encoder *encoder;
5070         int pipe = intel_crtc->pipe;
5071
5072         if (intel_crtc->config->has_pch_encoder)
5073                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5074
5075         for_each_encoder_on_crtc(dev, crtc, encoder)
5076                 encoder->disable(encoder);
5077
5078         drm_crtc_vblank_off(crtc);
5079         assert_vblank_disabled(crtc);
5080
5081         /*
5082          * Sometimes spurious CPU pipe underruns happen when the
5083          * pipe is already disabled, but FDI RX/TX is still enabled.
5084          * Happens at least with VGA+HDMI cloning. Suppress them.
5085          */
5086         if (intel_crtc->config->has_pch_encoder)
5087                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5088
5089         intel_disable_pipe(intel_crtc);
5090
5091         ironlake_pfit_disable(intel_crtc, false);
5092
5093         if (intel_crtc->config->has_pch_encoder) {
5094                 ironlake_fdi_disable(crtc);
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5096         }
5097
5098         for_each_encoder_on_crtc(dev, crtc, encoder)
5099                 if (encoder->post_disable)
5100                         encoder->post_disable(encoder);
5101
5102         if (intel_crtc->config->has_pch_encoder) {
5103                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5104
5105                 if (HAS_PCH_CPT(dev)) {
5106                         i915_reg_t reg;
5107                         u32 temp;
5108
5109                         /* disable TRANS_DP_CTL */
5110                         reg = TRANS_DP_CTL(pipe);
5111                         temp = I915_READ(reg);
5112                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5113                                   TRANS_DP_PORT_SEL_MASK);
5114                         temp |= TRANS_DP_PORT_SEL_NONE;
5115                         I915_WRITE(reg, temp);
5116
5117                         /* disable DPLL_SEL */
5118                         temp = I915_READ(PCH_DPLL_SEL);
5119                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5120                         I915_WRITE(PCH_DPLL_SEL, temp);
5121                 }
5122
5123                 ironlake_fdi_pll_disable(intel_crtc);
5124         }
5125
5126         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5127
5128         intel_fbc_disable_crtc(intel_crtc);
5129 }
5130
5131 static void haswell_crtc_disable(struct drm_crtc *crtc)
5132 {
5133         struct drm_device *dev = crtc->dev;
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136         struct intel_encoder *encoder;
5137         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5138
5139         if (intel_crtc->config->has_pch_encoder)
5140                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5141                                                       false);
5142
5143         for_each_encoder_on_crtc(dev, crtc, encoder) {
5144                 intel_opregion_notify_encoder(encoder, false);
5145                 encoder->disable(encoder);
5146         }
5147
5148         drm_crtc_vblank_off(crtc);
5149         assert_vblank_disabled(crtc);
5150
5151         intel_disable_pipe(intel_crtc);
5152
5153         if (intel_crtc->config->dp_encoder_is_mst)
5154                 intel_ddi_set_vc_payload_alloc(crtc, false);
5155
5156         if (!intel_crtc->config->has_dsi_encoder)
5157                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5158
5159         if (INTEL_INFO(dev)->gen >= 9)
5160                 skylake_scaler_disable(intel_crtc);
5161         else
5162                 ironlake_pfit_disable(intel_crtc, false);
5163
5164         if (!intel_crtc->config->has_dsi_encoder)
5165                 intel_ddi_disable_pipe_clock(intel_crtc);
5166
5167         for_each_encoder_on_crtc(dev, crtc, encoder)
5168                 if (encoder->post_disable)
5169                         encoder->post_disable(encoder);
5170
5171         if (intel_crtc->config->has_pch_encoder) {
5172                 lpt_disable_pch_transcoder(dev_priv);
5173                 intel_ddi_fdi_disable(crtc);
5174
5175                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5176                                                       true);
5177         }
5178
5179         intel_fbc_disable_crtc(intel_crtc);
5180 }
5181
5182 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5183 {
5184         struct drm_device *dev = crtc->base.dev;
5185         struct drm_i915_private *dev_priv = dev->dev_private;
5186         struct intel_crtc_state *pipe_config = crtc->config;
5187
5188         if (!pipe_config->gmch_pfit.control)
5189                 return;
5190
5191         /*
5192          * The panel fitter should only be adjusted whilst the pipe is disabled,
5193          * according to register description and PRM.
5194          */
5195         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5196         assert_pipe_disabled(dev_priv, crtc->pipe);
5197
5198         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5199         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5200
5201         /* Border color in case we don't scale up to the full screen. Black by
5202          * default, change to something else for debugging. */
5203         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5204 }
5205
5206 static enum intel_display_power_domain port_to_power_domain(enum port port)
5207 {
5208         switch (port) {
5209         case PORT_A:
5210                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5211         case PORT_B:
5212                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5213         case PORT_C:
5214                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5215         case PORT_D:
5216                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5217         case PORT_E:
5218                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5219         default:
5220                 MISSING_CASE(port);
5221                 return POWER_DOMAIN_PORT_OTHER;
5222         }
5223 }
5224
5225 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5226 {
5227         switch (port) {
5228         case PORT_A:
5229                 return POWER_DOMAIN_AUX_A;
5230         case PORT_B:
5231                 return POWER_DOMAIN_AUX_B;
5232         case PORT_C:
5233                 return POWER_DOMAIN_AUX_C;
5234         case PORT_D:
5235                 return POWER_DOMAIN_AUX_D;
5236         case PORT_E:
5237                 /* FIXME: Check VBT for actual wiring of PORT E */
5238                 return POWER_DOMAIN_AUX_D;
5239         default:
5240                 MISSING_CASE(port);
5241                 return POWER_DOMAIN_AUX_A;
5242         }
5243 }
5244
5245 enum intel_display_power_domain
5246 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5247 {
5248         struct drm_device *dev = intel_encoder->base.dev;
5249         struct intel_digital_port *intel_dig_port;
5250
5251         switch (intel_encoder->type) {
5252         case INTEL_OUTPUT_UNKNOWN:
5253                 /* Only DDI platforms should ever use this output type */
5254                 WARN_ON_ONCE(!HAS_DDI(dev));
5255         case INTEL_OUTPUT_DISPLAYPORT:
5256         case INTEL_OUTPUT_HDMI:
5257         case INTEL_OUTPUT_EDP:
5258                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5259                 return port_to_power_domain(intel_dig_port->port);
5260         case INTEL_OUTPUT_DP_MST:
5261                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5262                 return port_to_power_domain(intel_dig_port->port);
5263         case INTEL_OUTPUT_ANALOG:
5264                 return POWER_DOMAIN_PORT_CRT;
5265         case INTEL_OUTPUT_DSI:
5266                 return POWER_DOMAIN_PORT_DSI;
5267         default:
5268                 return POWER_DOMAIN_PORT_OTHER;
5269         }
5270 }
5271
5272 enum intel_display_power_domain
5273 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5274 {
5275         struct drm_device *dev = intel_encoder->base.dev;
5276         struct intel_digital_port *intel_dig_port;
5277
5278         switch (intel_encoder->type) {
5279         case INTEL_OUTPUT_UNKNOWN:
5280         case INTEL_OUTPUT_HDMI:
5281                 /*
5282                  * Only DDI platforms should ever use these output types.
5283                  * We can get here after the HDMI detect code has already set
5284                  * the type of the shared encoder. Since we can't be sure
5285                  * what's the status of the given connectors, play safe and
5286                  * run the DP detection too.
5287                  */
5288                 WARN_ON_ONCE(!HAS_DDI(dev));
5289         case INTEL_OUTPUT_DISPLAYPORT:
5290         case INTEL_OUTPUT_EDP:
5291                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5292                 return port_to_aux_power_domain(intel_dig_port->port);
5293         case INTEL_OUTPUT_DP_MST:
5294                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5295                 return port_to_aux_power_domain(intel_dig_port->port);
5296         default:
5297                 MISSING_CASE(intel_encoder->type);
5298                 return POWER_DOMAIN_AUX_A;
5299         }
5300 }
5301
5302 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5303 {
5304         struct drm_device *dev = crtc->dev;
5305         struct intel_encoder *intel_encoder;
5306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5307         enum pipe pipe = intel_crtc->pipe;
5308         unsigned long mask;
5309         enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5310
5311         if (!crtc->state->active)
5312                 return 0;
5313
5314         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5315         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5316         if (intel_crtc->config->pch_pfit.enabled ||
5317             intel_crtc->config->pch_pfit.force_thru)
5318                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5319
5320         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5321                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5322
5323         return mask;
5324 }
5325
5326 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5327 {
5328         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330         enum intel_display_power_domain domain;
5331         unsigned long domains, new_domains, old_domains;
5332
5333         old_domains = intel_crtc->enabled_power_domains;
5334         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5335
5336         domains = new_domains & ~old_domains;
5337
5338         for_each_power_domain(domain, domains)
5339                 intel_display_power_get(dev_priv, domain);
5340
5341         return old_domains & ~new_domains;
5342 }
5343
5344 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5345                                       unsigned long domains)
5346 {
5347         enum intel_display_power_domain domain;
5348
5349         for_each_power_domain(domain, domains)
5350                 intel_display_power_put(dev_priv, domain);
5351 }
5352
5353 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5354 {
5355         struct drm_device *dev = state->dev;
5356         struct drm_i915_private *dev_priv = dev->dev_private;
5357         unsigned long put_domains[I915_MAX_PIPES] = {};
5358         struct drm_crtc_state *crtc_state;
5359         struct drm_crtc *crtc;
5360         int i;
5361
5362         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5363                 if (needs_modeset(crtc->state))
5364                         put_domains[to_intel_crtc(crtc)->pipe] =
5365                                 modeset_get_crtc_power_domains(crtc);
5366         }
5367
5368         if (dev_priv->display.modeset_commit_cdclk) {
5369                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5370
5371                 if (cdclk != dev_priv->cdclk_freq &&
5372                     !WARN_ON(!state->allow_modeset))
5373                         dev_priv->display.modeset_commit_cdclk(state);
5374         }
5375
5376         for (i = 0; i < I915_MAX_PIPES; i++)
5377                 if (put_domains[i])
5378                         modeset_put_power_domains(dev_priv, put_domains[i]);
5379 }
5380
5381 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5382 {
5383         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5384
5385         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5386             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5387                 return max_cdclk_freq;
5388         else if (IS_CHERRYVIEW(dev_priv))
5389                 return max_cdclk_freq*95/100;
5390         else if (INTEL_INFO(dev_priv)->gen < 4)
5391                 return 2*max_cdclk_freq*90/100;
5392         else
5393                 return max_cdclk_freq*90/100;
5394 }
5395
5396 static void intel_update_max_cdclk(struct drm_device *dev)
5397 {
5398         struct drm_i915_private *dev_priv = dev->dev_private;
5399
5400         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5401                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5402
5403                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5404                         dev_priv->max_cdclk_freq = 675000;
5405                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5406                         dev_priv->max_cdclk_freq = 540000;
5407                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5408                         dev_priv->max_cdclk_freq = 450000;
5409                 else
5410                         dev_priv->max_cdclk_freq = 337500;
5411         } else if (IS_BROADWELL(dev))  {
5412                 /*
5413                  * FIXME with extra cooling we can allow
5414                  * 540 MHz for ULX and 675 Mhz for ULT.
5415                  * How can we know if extra cooling is
5416                  * available? PCI ID, VTB, something else?
5417                  */
5418                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5419                         dev_priv->max_cdclk_freq = 450000;
5420                 else if (IS_BDW_ULX(dev))
5421                         dev_priv->max_cdclk_freq = 450000;
5422                 else if (IS_BDW_ULT(dev))
5423                         dev_priv->max_cdclk_freq = 540000;
5424                 else
5425                         dev_priv->max_cdclk_freq = 675000;
5426         } else if (IS_CHERRYVIEW(dev)) {
5427                 dev_priv->max_cdclk_freq = 320000;
5428         } else if (IS_VALLEYVIEW(dev)) {
5429                 dev_priv->max_cdclk_freq = 400000;
5430         } else {
5431                 /* otherwise assume cdclk is fixed */
5432                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5433         }
5434
5435         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5436
5437         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5438                          dev_priv->max_cdclk_freq);
5439
5440         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5441                          dev_priv->max_dotclk_freq);
5442 }
5443
5444 static void intel_update_cdclk(struct drm_device *dev)
5445 {
5446         struct drm_i915_private *dev_priv = dev->dev_private;
5447
5448         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5449         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5450                          dev_priv->cdclk_freq);
5451
5452         /*
5453          * Program the gmbus_freq based on the cdclk frequency.
5454          * BSpec erroneously claims we should aim for 4MHz, but
5455          * in fact 1MHz is the correct frequency.
5456          */
5457         if (IS_VALLEYVIEW(dev)) {
5458                 /*
5459                  * Program the gmbus_freq based on the cdclk frequency.
5460                  * BSpec erroneously claims we should aim for 4MHz, but
5461                  * in fact 1MHz is the correct frequency.
5462                  */
5463                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5464         }
5465
5466         if (dev_priv->max_cdclk_freq == 0)
5467                 intel_update_max_cdclk(dev);
5468 }
5469
5470 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5471 {
5472         struct drm_i915_private *dev_priv = dev->dev_private;
5473         uint32_t divider;
5474         uint32_t ratio;
5475         uint32_t current_freq;
5476         int ret;
5477
5478         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5479         switch (frequency) {
5480         case 144000:
5481                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5482                 ratio = BXT_DE_PLL_RATIO(60);
5483                 break;
5484         case 288000:
5485                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5486                 ratio = BXT_DE_PLL_RATIO(60);
5487                 break;
5488         case 384000:
5489                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5490                 ratio = BXT_DE_PLL_RATIO(60);
5491                 break;
5492         case 576000:
5493                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5494                 ratio = BXT_DE_PLL_RATIO(60);
5495                 break;
5496         case 624000:
5497                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5498                 ratio = BXT_DE_PLL_RATIO(65);
5499                 break;
5500         case 19200:
5501                 /*
5502                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5503                  * to suppress GCC warning.
5504                  */
5505                 ratio = 0;
5506                 divider = 0;
5507                 break;
5508         default:
5509                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5510
5511                 return;
5512         }
5513
5514         mutex_lock(&dev_priv->rps.hw_lock);
5515         /* Inform power controller of upcoming frequency change */
5516         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5517                                       0x80000000);
5518         mutex_unlock(&dev_priv->rps.hw_lock);
5519
5520         if (ret) {
5521                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5522                           ret, frequency);
5523                 return;
5524         }
5525
5526         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5527         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5528         current_freq = current_freq * 500 + 1000;
5529
5530         /*
5531          * DE PLL has to be disabled when
5532          * - setting to 19.2MHz (bypass, PLL isn't used)
5533          * - before setting to 624MHz (PLL needs toggling)
5534          * - before setting to any frequency from 624MHz (PLL needs toggling)
5535          */
5536         if (frequency == 19200 || frequency == 624000 ||
5537             current_freq == 624000) {
5538                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5539                 /* Timeout 200us */
5540                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5541                              1))
5542                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5543         }
5544
5545         if (frequency != 19200) {
5546                 uint32_t val;
5547
5548                 val = I915_READ(BXT_DE_PLL_CTL);
5549                 val &= ~BXT_DE_PLL_RATIO_MASK;
5550                 val |= ratio;
5551                 I915_WRITE(BXT_DE_PLL_CTL, val);
5552
5553                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5554                 /* Timeout 200us */
5555                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5556                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5557
5558                 val = I915_READ(CDCLK_CTL);
5559                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5560                 val |= divider;
5561                 /*
5562                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5563                  * enable otherwise.
5564                  */
5565                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5566                 if (frequency >= 500000)
5567                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5568
5569                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5570                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5571                 val |= (frequency - 1000) / 500;
5572                 I915_WRITE(CDCLK_CTL, val);
5573         }
5574
5575         mutex_lock(&dev_priv->rps.hw_lock);
5576         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5577                                       DIV_ROUND_UP(frequency, 25000));
5578         mutex_unlock(&dev_priv->rps.hw_lock);
5579
5580         if (ret) {
5581                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5582                           ret, frequency);
5583                 return;
5584         }
5585
5586         intel_update_cdclk(dev);
5587 }
5588
5589 void broxton_init_cdclk(struct drm_device *dev)
5590 {
5591         struct drm_i915_private *dev_priv = dev->dev_private;
5592         uint32_t val;
5593
5594         /*
5595          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5596          * or else the reset will hang because there is no PCH to respond.
5597          * Move the handshake programming to initialization sequence.
5598          * Previously was left up to BIOS.
5599          */
5600         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5601         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5602         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5603
5604         /* Enable PG1 for cdclk */
5605         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5606
5607         /* check if cd clock is enabled */
5608         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5609                 DRM_DEBUG_KMS("Display already initialized\n");
5610                 return;
5611         }
5612
5613         /*
5614          * FIXME:
5615          * - The initial CDCLK needs to be read from VBT.
5616          *   Need to make this change after VBT has changes for BXT.
5617          * - check if setting the max (or any) cdclk freq is really necessary
5618          *   here, it belongs to modeset time
5619          */
5620         broxton_set_cdclk(dev, 624000);
5621
5622         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5623         POSTING_READ(DBUF_CTL);
5624
5625         udelay(10);
5626
5627         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5628                 DRM_ERROR("DBuf power enable timeout!\n");
5629 }
5630
5631 void broxton_uninit_cdclk(struct drm_device *dev)
5632 {
5633         struct drm_i915_private *dev_priv = dev->dev_private;
5634
5635         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5636         POSTING_READ(DBUF_CTL);
5637
5638         udelay(10);
5639
5640         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5641                 DRM_ERROR("DBuf power disable timeout!\n");
5642
5643         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5644         broxton_set_cdclk(dev, 19200);
5645
5646         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5647 }
5648
5649 static const struct skl_cdclk_entry {
5650         unsigned int freq;
5651         unsigned int vco;
5652 } skl_cdclk_frequencies[] = {
5653         { .freq = 308570, .vco = 8640 },
5654         { .freq = 337500, .vco = 8100 },
5655         { .freq = 432000, .vco = 8640 },
5656         { .freq = 450000, .vco = 8100 },
5657         { .freq = 540000, .vco = 8100 },
5658         { .freq = 617140, .vco = 8640 },
5659         { .freq = 675000, .vco = 8100 },
5660 };
5661
5662 static unsigned int skl_cdclk_decimal(unsigned int freq)
5663 {
5664         return (freq - 1000) / 500;
5665 }
5666
5667 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5668 {
5669         unsigned int i;
5670
5671         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5672                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5673
5674                 if (e->freq == freq)
5675                         return e->vco;
5676         }
5677
5678         return 8100;
5679 }
5680
5681 static void
5682 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5683 {
5684         unsigned int min_freq;
5685         u32 val;
5686
5687         /* select the minimum CDCLK before enabling DPLL 0 */
5688         val = I915_READ(CDCLK_CTL);
5689         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5690         val |= CDCLK_FREQ_337_308;
5691
5692         if (required_vco == 8640)
5693                 min_freq = 308570;
5694         else
5695                 min_freq = 337500;
5696
5697         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5698
5699         I915_WRITE(CDCLK_CTL, val);
5700         POSTING_READ(CDCLK_CTL);
5701
5702         /*
5703          * We always enable DPLL0 with the lowest link rate possible, but still
5704          * taking into account the VCO required to operate the eDP panel at the
5705          * desired frequency. The usual DP link rates operate with a VCO of
5706          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5707          * The modeset code is responsible for the selection of the exact link
5708          * rate later on, with the constraint of choosing a frequency that
5709          * works with required_vco.
5710          */
5711         val = I915_READ(DPLL_CTRL1);
5712
5713         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5714                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5715         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5716         if (required_vco == 8640)
5717                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5718                                             SKL_DPLL0);
5719         else
5720                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5721                                             SKL_DPLL0);
5722
5723         I915_WRITE(DPLL_CTRL1, val);
5724         POSTING_READ(DPLL_CTRL1);
5725
5726         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5727
5728         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5729                 DRM_ERROR("DPLL0 not locked\n");
5730 }
5731
5732 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5733 {
5734         int ret;
5735         u32 val;
5736
5737         /* inform PCU we want to change CDCLK */
5738         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5739         mutex_lock(&dev_priv->rps.hw_lock);
5740         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5741         mutex_unlock(&dev_priv->rps.hw_lock);
5742
5743         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5744 }
5745
5746 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5747 {
5748         unsigned int i;
5749
5750         for (i = 0; i < 15; i++) {
5751                 if (skl_cdclk_pcu_ready(dev_priv))
5752                         return true;
5753                 udelay(10);
5754         }
5755
5756         return false;
5757 }
5758
5759 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5760 {
5761         struct drm_device *dev = dev_priv->dev;
5762         u32 freq_select, pcu_ack;
5763
5764         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5765
5766         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5767                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5768                 return;
5769         }
5770
5771         /* set CDCLK_CTL */
5772         switch(freq) {
5773         case 450000:
5774         case 432000:
5775                 freq_select = CDCLK_FREQ_450_432;
5776                 pcu_ack = 1;
5777                 break;
5778         case 540000:
5779                 freq_select = CDCLK_FREQ_540;
5780                 pcu_ack = 2;
5781                 break;
5782         case 308570:
5783         case 337500:
5784         default:
5785                 freq_select = CDCLK_FREQ_337_308;
5786                 pcu_ack = 0;
5787                 break;
5788         case 617140:
5789         case 675000:
5790                 freq_select = CDCLK_FREQ_675_617;
5791                 pcu_ack = 3;
5792                 break;
5793         }
5794
5795         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5796         POSTING_READ(CDCLK_CTL);
5797
5798         /* inform PCU of the change */
5799         mutex_lock(&dev_priv->rps.hw_lock);
5800         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5801         mutex_unlock(&dev_priv->rps.hw_lock);
5802
5803         intel_update_cdclk(dev);
5804 }
5805
5806 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5807 {
5808         /* disable DBUF power */
5809         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5810         POSTING_READ(DBUF_CTL);
5811
5812         udelay(10);
5813
5814         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5815                 DRM_ERROR("DBuf power disable timeout\n");
5816
5817         /* disable DPLL0 */
5818         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5819         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5820                 DRM_ERROR("Couldn't disable DPLL0\n");
5821 }
5822
5823 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5824 {
5825         unsigned int required_vco;
5826
5827         /* DPLL0 not enabled (happens on early BIOS versions) */
5828         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5829                 /* enable DPLL0 */
5830                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5831                 skl_dpll0_enable(dev_priv, required_vco);
5832         }
5833
5834         /* set CDCLK to the frequency the BIOS chose */
5835         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5836
5837         /* enable DBUF power */
5838         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5839         POSTING_READ(DBUF_CTL);
5840
5841         udelay(10);
5842
5843         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5844                 DRM_ERROR("DBuf power enable timeout\n");
5845 }
5846
5847 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5848 {
5849         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5850         uint32_t cdctl = I915_READ(CDCLK_CTL);
5851         int freq = dev_priv->skl_boot_cdclk;
5852
5853         /*
5854          * check if the pre-os intialized the display
5855          * There is SWF18 scratchpad register defined which is set by the
5856          * pre-os which can be used by the OS drivers to check the status
5857          */
5858         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5859                 goto sanitize;
5860
5861         /* Is PLL enabled and locked ? */
5862         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5863                 goto sanitize;
5864
5865         /* DPLL okay; verify the cdclock
5866          *
5867          * Noticed in some instances that the freq selection is correct but
5868          * decimal part is programmed wrong from BIOS where pre-os does not
5869          * enable display. Verify the same as well.
5870          */
5871         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5872                 /* All well; nothing to sanitize */
5873                 return false;
5874 sanitize:
5875         /*
5876          * As of now initialize with max cdclk till
5877          * we get dynamic cdclk support
5878          * */
5879         dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5880         skl_init_cdclk(dev_priv);
5881
5882         /* we did have to sanitize */
5883         return true;
5884 }
5885
5886 /* Adjust CDclk dividers to allow high res or save power if possible */
5887 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5888 {
5889         struct drm_i915_private *dev_priv = dev->dev_private;
5890         u32 val, cmd;
5891
5892         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5893                                         != dev_priv->cdclk_freq);
5894
5895         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5896                 cmd = 2;
5897         else if (cdclk == 266667)
5898                 cmd = 1;
5899         else
5900                 cmd = 0;
5901
5902         mutex_lock(&dev_priv->rps.hw_lock);
5903         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5904         val &= ~DSPFREQGUAR_MASK;
5905         val |= (cmd << DSPFREQGUAR_SHIFT);
5906         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5907         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5908                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5909                      50)) {
5910                 DRM_ERROR("timed out waiting for CDclk change\n");
5911         }
5912         mutex_unlock(&dev_priv->rps.hw_lock);
5913
5914         mutex_lock(&dev_priv->sb_lock);
5915
5916         if (cdclk == 400000) {
5917                 u32 divider;
5918
5919                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5920
5921                 /* adjust cdclk divider */
5922                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5923                 val &= ~CCK_FREQUENCY_VALUES;
5924                 val |= divider;
5925                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5926
5927                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5928                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5929                              50))
5930                         DRM_ERROR("timed out waiting for CDclk change\n");
5931         }
5932
5933         /* adjust self-refresh exit latency value */
5934         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5935         val &= ~0x7f;
5936
5937         /*
5938          * For high bandwidth configs, we set a higher latency in the bunit
5939          * so that the core display fetch happens in time to avoid underruns.
5940          */
5941         if (cdclk == 400000)
5942                 val |= 4500 / 250; /* 4.5 usec */
5943         else
5944                 val |= 3000 / 250; /* 3.0 usec */
5945         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5946
5947         mutex_unlock(&dev_priv->sb_lock);
5948
5949         intel_update_cdclk(dev);
5950 }
5951
5952 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5953 {
5954         struct drm_i915_private *dev_priv = dev->dev_private;
5955         u32 val, cmd;
5956
5957         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5958                                                 != dev_priv->cdclk_freq);
5959
5960         switch (cdclk) {
5961         case 333333:
5962         case 320000:
5963         case 266667:
5964         case 200000:
5965                 break;
5966         default:
5967                 MISSING_CASE(cdclk);
5968                 return;
5969         }
5970
5971         /*
5972          * Specs are full of misinformation, but testing on actual
5973          * hardware has shown that we just need to write the desired
5974          * CCK divider into the Punit register.
5975          */
5976         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5977
5978         mutex_lock(&dev_priv->rps.hw_lock);
5979         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5980         val &= ~DSPFREQGUAR_MASK_CHV;
5981         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5982         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5983         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5984                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5985                      50)) {
5986                 DRM_ERROR("timed out waiting for CDclk change\n");
5987         }
5988         mutex_unlock(&dev_priv->rps.hw_lock);
5989
5990         intel_update_cdclk(dev);
5991 }
5992
5993 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5994                                  int max_pixclk)
5995 {
5996         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5997         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5998
5999         /*
6000          * Really only a few cases to deal with, as only 4 CDclks are supported:
6001          *   200MHz
6002          *   267MHz
6003          *   320/333MHz (depends on HPLL freq)
6004          *   400MHz (VLV only)
6005          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6006          * of the lower bin and adjust if needed.
6007          *
6008          * We seem to get an unstable or solid color picture at 200MHz.
6009          * Not sure what's wrong. For now use 200MHz only when all pipes
6010          * are off.
6011          */
6012         if (!IS_CHERRYVIEW(dev_priv) &&
6013             max_pixclk > freq_320*limit/100)
6014                 return 400000;
6015         else if (max_pixclk > 266667*limit/100)
6016                 return freq_320;
6017         else if (max_pixclk > 0)
6018                 return 266667;
6019         else
6020                 return 200000;
6021 }
6022
6023 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6024                               int max_pixclk)
6025 {
6026         /*
6027          * FIXME:
6028          * - remove the guardband, it's not needed on BXT
6029          * - set 19.2MHz bypass frequency if there are no active pipes
6030          */
6031         if (max_pixclk > 576000*9/10)
6032                 return 624000;
6033         else if (max_pixclk > 384000*9/10)
6034                 return 576000;
6035         else if (max_pixclk > 288000*9/10)
6036                 return 384000;
6037         else if (max_pixclk > 144000*9/10)
6038                 return 288000;
6039         else
6040                 return 144000;
6041 }
6042
6043 /* Compute the max pixel clock for new configuration. Uses atomic state if
6044  * that's non-NULL, look at current state otherwise. */
6045 static int intel_mode_max_pixclk(struct drm_device *dev,
6046                                  struct drm_atomic_state *state)
6047 {
6048         struct intel_crtc *intel_crtc;
6049         struct intel_crtc_state *crtc_state;
6050         int max_pixclk = 0;
6051
6052         for_each_intel_crtc(dev, intel_crtc) {
6053                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6054                 if (IS_ERR(crtc_state))
6055                         return PTR_ERR(crtc_state);
6056
6057                 if (!crtc_state->base.enable)
6058                         continue;
6059
6060                 max_pixclk = max(max_pixclk,
6061                                  crtc_state->base.adjusted_mode.crtc_clock);
6062         }
6063
6064         return max_pixclk;
6065 }
6066
6067 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6068 {
6069         struct drm_device *dev = state->dev;
6070         struct drm_i915_private *dev_priv = dev->dev_private;
6071         int max_pixclk = intel_mode_max_pixclk(dev, state);
6072
6073         if (max_pixclk < 0)
6074                 return max_pixclk;
6075
6076         to_intel_atomic_state(state)->cdclk =
6077                 valleyview_calc_cdclk(dev_priv, max_pixclk);
6078
6079         return 0;
6080 }
6081
6082 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6083 {
6084         struct drm_device *dev = state->dev;
6085         struct drm_i915_private *dev_priv = dev->dev_private;
6086         int max_pixclk = intel_mode_max_pixclk(dev, state);
6087
6088         if (max_pixclk < 0)
6089                 return max_pixclk;
6090
6091         to_intel_atomic_state(state)->cdclk =
6092                 broxton_calc_cdclk(dev_priv, max_pixclk);
6093
6094         return 0;
6095 }
6096
6097 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6098 {
6099         unsigned int credits, default_credits;
6100
6101         if (IS_CHERRYVIEW(dev_priv))
6102                 default_credits = PFI_CREDIT(12);
6103         else
6104                 default_credits = PFI_CREDIT(8);
6105
6106         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6107                 /* CHV suggested value is 31 or 63 */
6108                 if (IS_CHERRYVIEW(dev_priv))
6109                         credits = PFI_CREDIT_63;
6110                 else
6111                         credits = PFI_CREDIT(15);
6112         } else {
6113                 credits = default_credits;
6114         }
6115
6116         /*
6117          * WA - write default credits before re-programming
6118          * FIXME: should we also set the resend bit here?
6119          */
6120         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6121                    default_credits);
6122
6123         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6124                    credits | PFI_CREDIT_RESEND);
6125
6126         /*
6127          * FIXME is this guaranteed to clear
6128          * immediately or should we poll for it?
6129          */
6130         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6131 }
6132
6133 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6134 {
6135         struct drm_device *dev = old_state->dev;
6136         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138
6139         /*
6140          * FIXME: We can end up here with all power domains off, yet
6141          * with a CDCLK frequency other than the minimum. To account
6142          * for this take the PIPE-A power domain, which covers the HW
6143          * blocks needed for the following programming. This can be
6144          * removed once it's guaranteed that we get here either with
6145          * the minimum CDCLK set, or the required power domains
6146          * enabled.
6147          */
6148         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6149
6150         if (IS_CHERRYVIEW(dev))
6151                 cherryview_set_cdclk(dev, req_cdclk);
6152         else
6153                 valleyview_set_cdclk(dev, req_cdclk);
6154
6155         vlv_program_pfi_credits(dev_priv);
6156
6157         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6158 }
6159
6160 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6161 {
6162         struct drm_device *dev = crtc->dev;
6163         struct drm_i915_private *dev_priv = to_i915(dev);
6164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165         struct intel_encoder *encoder;
6166         int pipe = intel_crtc->pipe;
6167
6168         if (WARN_ON(intel_crtc->active))
6169                 return;
6170
6171         if (intel_crtc->config->has_dp_encoder)
6172                 intel_dp_set_m_n(intel_crtc, M1_N1);
6173
6174         intel_set_pipe_timings(intel_crtc);
6175
6176         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6177                 struct drm_i915_private *dev_priv = dev->dev_private;
6178
6179                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6180                 I915_WRITE(CHV_CANVAS(pipe), 0);
6181         }
6182
6183         i9xx_set_pipeconf(intel_crtc);
6184
6185         intel_crtc->active = true;
6186
6187         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6188
6189         for_each_encoder_on_crtc(dev, crtc, encoder)
6190                 if (encoder->pre_pll_enable)
6191                         encoder->pre_pll_enable(encoder);
6192
6193         if (!intel_crtc->config->has_dsi_encoder) {
6194                 if (IS_CHERRYVIEW(dev)) {
6195                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6196                         chv_enable_pll(intel_crtc, intel_crtc->config);
6197                 } else {
6198                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6199                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6200                 }
6201         }
6202
6203         for_each_encoder_on_crtc(dev, crtc, encoder)
6204                 if (encoder->pre_enable)
6205                         encoder->pre_enable(encoder);
6206
6207         i9xx_pfit_enable(intel_crtc);
6208
6209         intel_crtc_load_lut(crtc);
6210
6211         intel_enable_pipe(intel_crtc);
6212
6213         assert_vblank_disabled(crtc);
6214         drm_crtc_vblank_on(crtc);
6215
6216         for_each_encoder_on_crtc(dev, crtc, encoder)
6217                 encoder->enable(encoder);
6218 }
6219
6220 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6221 {
6222         struct drm_device *dev = crtc->base.dev;
6223         struct drm_i915_private *dev_priv = dev->dev_private;
6224
6225         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6226         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6227 }
6228
6229 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6230 {
6231         struct drm_device *dev = crtc->dev;
6232         struct drm_i915_private *dev_priv = to_i915(dev);
6233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234         struct intel_encoder *encoder;
6235         int pipe = intel_crtc->pipe;
6236
6237         if (WARN_ON(intel_crtc->active))
6238                 return;
6239
6240         i9xx_set_pll_dividers(intel_crtc);
6241
6242         if (intel_crtc->config->has_dp_encoder)
6243                 intel_dp_set_m_n(intel_crtc, M1_N1);
6244
6245         intel_set_pipe_timings(intel_crtc);
6246
6247         i9xx_set_pipeconf(intel_crtc);
6248
6249         intel_crtc->active = true;
6250
6251         if (!IS_GEN2(dev))
6252                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6253
6254         for_each_encoder_on_crtc(dev, crtc, encoder)
6255                 if (encoder->pre_enable)
6256                         encoder->pre_enable(encoder);
6257
6258         i9xx_enable_pll(intel_crtc);
6259
6260         i9xx_pfit_enable(intel_crtc);
6261
6262         intel_crtc_load_lut(crtc);
6263
6264         intel_update_watermarks(crtc);
6265         intel_enable_pipe(intel_crtc);
6266
6267         assert_vblank_disabled(crtc);
6268         drm_crtc_vblank_on(crtc);
6269
6270         for_each_encoder_on_crtc(dev, crtc, encoder)
6271                 encoder->enable(encoder);
6272
6273         intel_fbc_enable(intel_crtc);
6274 }
6275
6276 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6277 {
6278         struct drm_device *dev = crtc->base.dev;
6279         struct drm_i915_private *dev_priv = dev->dev_private;
6280
6281         if (!crtc->config->gmch_pfit.control)
6282                 return;
6283
6284         assert_pipe_disabled(dev_priv, crtc->pipe);
6285
6286         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6287                          I915_READ(PFIT_CONTROL));
6288         I915_WRITE(PFIT_CONTROL, 0);
6289 }
6290
6291 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6292 {
6293         struct drm_device *dev = crtc->dev;
6294         struct drm_i915_private *dev_priv = dev->dev_private;
6295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6296         struct intel_encoder *encoder;
6297         int pipe = intel_crtc->pipe;
6298
6299         /*
6300          * On gen2 planes are double buffered but the pipe isn't, so we must
6301          * wait for planes to fully turn off before disabling the pipe.
6302          * We also need to wait on all gmch platforms because of the
6303          * self-refresh mode constraint explained above.
6304          */
6305         intel_wait_for_vblank(dev, pipe);
6306
6307         for_each_encoder_on_crtc(dev, crtc, encoder)
6308                 encoder->disable(encoder);
6309
6310         drm_crtc_vblank_off(crtc);
6311         assert_vblank_disabled(crtc);
6312
6313         intel_disable_pipe(intel_crtc);
6314
6315         i9xx_pfit_disable(intel_crtc);
6316
6317         for_each_encoder_on_crtc(dev, crtc, encoder)
6318                 if (encoder->post_disable)
6319                         encoder->post_disable(encoder);
6320
6321         if (!intel_crtc->config->has_dsi_encoder) {
6322                 if (IS_CHERRYVIEW(dev))
6323                         chv_disable_pll(dev_priv, pipe);
6324                 else if (IS_VALLEYVIEW(dev))
6325                         vlv_disable_pll(dev_priv, pipe);
6326                 else
6327                         i9xx_disable_pll(intel_crtc);
6328         }
6329
6330         for_each_encoder_on_crtc(dev, crtc, encoder)
6331                 if (encoder->post_pll_disable)
6332                         encoder->post_pll_disable(encoder);
6333
6334         if (!IS_GEN2(dev))
6335                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6336
6337         intel_fbc_disable_crtc(intel_crtc);
6338 }
6339
6340 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6341 {
6342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6343         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6344         enum intel_display_power_domain domain;
6345         unsigned long domains;
6346
6347         if (!intel_crtc->active)
6348                 return;
6349
6350         if (to_intel_plane_state(crtc->primary->state)->visible) {
6351                 WARN_ON(intel_crtc->unpin_work);
6352
6353                 intel_pre_disable_primary(crtc);
6354         }
6355
6356         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6357         dev_priv->display.crtc_disable(crtc);
6358         intel_crtc->active = false;
6359         intel_update_watermarks(crtc);
6360         intel_disable_shared_dpll(intel_crtc);
6361
6362         domains = intel_crtc->enabled_power_domains;
6363         for_each_power_domain(domain, domains)
6364                 intel_display_power_put(dev_priv, domain);
6365         intel_crtc->enabled_power_domains = 0;
6366 }
6367
6368 /*
6369  * turn all crtc's off, but do not adjust state
6370  * This has to be paired with a call to intel_modeset_setup_hw_state.
6371  */
6372 int intel_display_suspend(struct drm_device *dev)
6373 {
6374         struct drm_mode_config *config = &dev->mode_config;
6375         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6376         struct drm_atomic_state *state;
6377         struct drm_crtc *crtc;
6378         unsigned crtc_mask = 0;
6379         int ret = 0;
6380
6381         if (WARN_ON(!ctx))
6382                 return 0;
6383
6384         lockdep_assert_held(&ctx->ww_ctx);
6385         state = drm_atomic_state_alloc(dev);
6386         if (WARN_ON(!state))
6387                 return -ENOMEM;
6388
6389         state->acquire_ctx = ctx;
6390         state->allow_modeset = true;
6391
6392         for_each_crtc(dev, crtc) {
6393                 struct drm_crtc_state *crtc_state =
6394                         drm_atomic_get_crtc_state(state, crtc);
6395
6396                 ret = PTR_ERR_OR_ZERO(crtc_state);
6397                 if (ret)
6398                         goto free;
6399
6400                 if (!crtc_state->active)
6401                         continue;
6402
6403                 crtc_state->active = false;
6404                 crtc_mask |= 1 << drm_crtc_index(crtc);
6405         }
6406
6407         if (crtc_mask) {
6408                 ret = drm_atomic_commit(state);
6409
6410                 if (!ret) {
6411                         for_each_crtc(dev, crtc)
6412                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6413                                         crtc->state->active = true;
6414
6415                         return ret;
6416                 }
6417         }
6418
6419 free:
6420         if (ret)
6421                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6422         drm_atomic_state_free(state);
6423         return ret;
6424 }
6425
6426 void intel_encoder_destroy(struct drm_encoder *encoder)
6427 {
6428         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6429
6430         drm_encoder_cleanup(encoder);
6431         kfree(intel_encoder);
6432 }
6433
6434 /* Cross check the actual hw state with our own modeset state tracking (and it's
6435  * internal consistency). */
6436 static void intel_connector_check_state(struct intel_connector *connector)
6437 {
6438         struct drm_crtc *crtc = connector->base.state->crtc;
6439
6440         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6441                       connector->base.base.id,
6442                       connector->base.name);
6443
6444         if (connector->get_hw_state(connector)) {
6445                 struct intel_encoder *encoder = connector->encoder;
6446                 struct drm_connector_state *conn_state = connector->base.state;
6447
6448                 I915_STATE_WARN(!crtc,
6449                          "connector enabled without attached crtc\n");
6450
6451                 if (!crtc)
6452                         return;
6453
6454                 I915_STATE_WARN(!crtc->state->active,
6455                       "connector is active, but attached crtc isn't\n");
6456
6457                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6458                         return;
6459
6460                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6461                         "atomic encoder doesn't match attached encoder\n");
6462
6463                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6464                         "attached encoder crtc differs from connector crtc\n");
6465         } else {
6466                 I915_STATE_WARN(crtc && crtc->state->active,
6467                         "attached crtc is active, but connector isn't\n");
6468                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6469                         "best encoder set without crtc!\n");
6470         }
6471 }
6472
6473 int intel_connector_init(struct intel_connector *connector)
6474 {
6475         struct drm_connector_state *connector_state;
6476
6477         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6478         if (!connector_state)
6479                 return -ENOMEM;
6480
6481         connector->base.state = connector_state;
6482         return 0;
6483 }
6484
6485 struct intel_connector *intel_connector_alloc(void)
6486 {
6487         struct intel_connector *connector;
6488
6489         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6490         if (!connector)
6491                 return NULL;
6492
6493         if (intel_connector_init(connector) < 0) {
6494                 kfree(connector);
6495                 return NULL;
6496         }
6497
6498         return connector;
6499 }
6500
6501 /* Simple connector->get_hw_state implementation for encoders that support only
6502  * one connector and no cloning and hence the encoder state determines the state
6503  * of the connector. */
6504 bool intel_connector_get_hw_state(struct intel_connector *connector)
6505 {
6506         enum pipe pipe = 0;
6507         struct intel_encoder *encoder = connector->encoder;
6508
6509         return encoder->get_hw_state(encoder, &pipe);
6510 }
6511
6512 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6513 {
6514         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6515                 return crtc_state->fdi_lanes;
6516
6517         return 0;
6518 }
6519
6520 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6521                                      struct intel_crtc_state *pipe_config)
6522 {
6523         struct drm_atomic_state *state = pipe_config->base.state;
6524         struct intel_crtc *other_crtc;
6525         struct intel_crtc_state *other_crtc_state;
6526
6527         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6528                       pipe_name(pipe), pipe_config->fdi_lanes);
6529         if (pipe_config->fdi_lanes > 4) {
6530                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6531                               pipe_name(pipe), pipe_config->fdi_lanes);
6532                 return -EINVAL;
6533         }
6534
6535         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6536                 if (pipe_config->fdi_lanes > 2) {
6537                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6538                                       pipe_config->fdi_lanes);
6539                         return -EINVAL;
6540                 } else {
6541                         return 0;
6542                 }
6543         }
6544
6545         if (INTEL_INFO(dev)->num_pipes == 2)
6546                 return 0;
6547
6548         /* Ivybridge 3 pipe is really complicated */
6549         switch (pipe) {
6550         case PIPE_A:
6551                 return 0;
6552         case PIPE_B:
6553                 if (pipe_config->fdi_lanes <= 2)
6554                         return 0;
6555
6556                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6557                 other_crtc_state =
6558                         intel_atomic_get_crtc_state(state, other_crtc);
6559                 if (IS_ERR(other_crtc_state))
6560                         return PTR_ERR(other_crtc_state);
6561
6562                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6563                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6564                                       pipe_name(pipe), pipe_config->fdi_lanes);
6565                         return -EINVAL;
6566                 }
6567                 return 0;
6568         case PIPE_C:
6569                 if (pipe_config->fdi_lanes > 2) {
6570                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6571                                       pipe_name(pipe), pipe_config->fdi_lanes);
6572                         return -EINVAL;
6573                 }
6574
6575                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6576                 other_crtc_state =
6577                         intel_atomic_get_crtc_state(state, other_crtc);
6578                 if (IS_ERR(other_crtc_state))
6579                         return PTR_ERR(other_crtc_state);
6580
6581                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6582                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6583                         return -EINVAL;
6584                 }
6585                 return 0;
6586         default:
6587                 BUG();
6588         }
6589 }
6590
6591 #define RETRY 1
6592 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6593                                        struct intel_crtc_state *pipe_config)
6594 {
6595         struct drm_device *dev = intel_crtc->base.dev;
6596         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6597         int lane, link_bw, fdi_dotclock, ret;
6598         bool needs_recompute = false;
6599
6600 retry:
6601         /* FDI is a binary signal running at ~2.7GHz, encoding
6602          * each output octet as 10 bits. The actual frequency
6603          * is stored as a divider into a 100MHz clock, and the
6604          * mode pixel clock is stored in units of 1KHz.
6605          * Hence the bw of each lane in terms of the mode signal
6606          * is:
6607          */
6608         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6609
6610         fdi_dotclock = adjusted_mode->crtc_clock;
6611
6612         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6613                                            pipe_config->pipe_bpp);
6614
6615         pipe_config->fdi_lanes = lane;
6616
6617         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6618                                link_bw, &pipe_config->fdi_m_n);
6619
6620         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6621                                        intel_crtc->pipe, pipe_config);
6622         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6623                 pipe_config->pipe_bpp -= 2*3;
6624                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6625                               pipe_config->pipe_bpp);
6626                 needs_recompute = true;
6627                 pipe_config->bw_constrained = true;
6628
6629                 goto retry;
6630         }
6631
6632         if (needs_recompute)
6633                 return RETRY;
6634
6635         return ret;
6636 }
6637
6638 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6639                                      struct intel_crtc_state *pipe_config)
6640 {
6641         if (pipe_config->pipe_bpp > 24)
6642                 return false;
6643
6644         /* HSW can handle pixel rate up to cdclk? */
6645         if (IS_HASWELL(dev_priv->dev))
6646                 return true;
6647
6648         /*
6649          * We compare against max which means we must take
6650          * the increased cdclk requirement into account when
6651          * calculating the new cdclk.
6652          *
6653          * Should measure whether using a lower cdclk w/o IPS
6654          */
6655         return ilk_pipe_pixel_rate(pipe_config) <=
6656                 dev_priv->max_cdclk_freq * 95 / 100;
6657 }
6658
6659 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6660                                    struct intel_crtc_state *pipe_config)
6661 {
6662         struct drm_device *dev = crtc->base.dev;
6663         struct drm_i915_private *dev_priv = dev->dev_private;
6664
6665         pipe_config->ips_enabled = i915.enable_ips &&
6666                 hsw_crtc_supports_ips(crtc) &&
6667                 pipe_config_supports_ips(dev_priv, pipe_config);
6668 }
6669
6670 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6671 {
6672         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6673
6674         /* GDG double wide on either pipe, otherwise pipe A only */
6675         return INTEL_INFO(dev_priv)->gen < 4 &&
6676                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6677 }
6678
6679 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6680                                      struct intel_crtc_state *pipe_config)
6681 {
6682         struct drm_device *dev = crtc->base.dev;
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6685
6686         /* FIXME should check pixel clock limits on all platforms */
6687         if (INTEL_INFO(dev)->gen < 4) {
6688                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6689
6690                 /*
6691                  * Enable double wide mode when the dot clock
6692                  * is > 90% of the (display) core speed.
6693                  */
6694                 if (intel_crtc_supports_double_wide(crtc) &&
6695                     adjusted_mode->crtc_clock > clock_limit) {
6696                         clock_limit *= 2;
6697                         pipe_config->double_wide = true;
6698                 }
6699
6700                 if (adjusted_mode->crtc_clock > clock_limit) {
6701                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6702                                       adjusted_mode->crtc_clock, clock_limit,
6703                                       yesno(pipe_config->double_wide));
6704                         return -EINVAL;
6705                 }
6706         }
6707
6708         /*
6709          * Pipe horizontal size must be even in:
6710          * - DVO ganged mode
6711          * - LVDS dual channel mode
6712          * - Double wide pipe
6713          */
6714         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6715              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6716                 pipe_config->pipe_src_w &= ~1;
6717
6718         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6719          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6720          */
6721         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6722                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6723                 return -EINVAL;
6724
6725         if (HAS_IPS(dev))
6726                 hsw_compute_ips_config(crtc, pipe_config);
6727
6728         if (pipe_config->has_pch_encoder)
6729                 return ironlake_fdi_compute_config(crtc, pipe_config);
6730
6731         return 0;
6732 }
6733
6734 static int skylake_get_display_clock_speed(struct drm_device *dev)
6735 {
6736         struct drm_i915_private *dev_priv = to_i915(dev);
6737         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6738         uint32_t cdctl = I915_READ(CDCLK_CTL);
6739         uint32_t linkrate;
6740
6741         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6742                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6743
6744         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6745                 return 540000;
6746
6747         linkrate = (I915_READ(DPLL_CTRL1) &
6748                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6749
6750         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6751             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6752                 /* vco 8640 */
6753                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6754                 case CDCLK_FREQ_450_432:
6755                         return 432000;
6756                 case CDCLK_FREQ_337_308:
6757                         return 308570;
6758                 case CDCLK_FREQ_675_617:
6759                         return 617140;
6760                 default:
6761                         WARN(1, "Unknown cd freq selection\n");
6762                 }
6763         } else {
6764                 /* vco 8100 */
6765                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6766                 case CDCLK_FREQ_450_432:
6767                         return 450000;
6768                 case CDCLK_FREQ_337_308:
6769                         return 337500;
6770                 case CDCLK_FREQ_675_617:
6771                         return 675000;
6772                 default:
6773                         WARN(1, "Unknown cd freq selection\n");
6774                 }
6775         }
6776
6777         /* error case, do as if DPLL0 isn't enabled */
6778         return 24000;
6779 }
6780
6781 static int broxton_get_display_clock_speed(struct drm_device *dev)
6782 {
6783         struct drm_i915_private *dev_priv = to_i915(dev);
6784         uint32_t cdctl = I915_READ(CDCLK_CTL);
6785         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6786         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6787         int cdclk;
6788
6789         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6790                 return 19200;
6791
6792         cdclk = 19200 * pll_ratio / 2;
6793
6794         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6795         case BXT_CDCLK_CD2X_DIV_SEL_1:
6796                 return cdclk;  /* 576MHz or 624MHz */
6797         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6798                 return cdclk * 2 / 3; /* 384MHz */
6799         case BXT_CDCLK_CD2X_DIV_SEL_2:
6800                 return cdclk / 2; /* 288MHz */
6801         case BXT_CDCLK_CD2X_DIV_SEL_4:
6802                 return cdclk / 4; /* 144MHz */
6803         }
6804
6805         /* error case, do as if DE PLL isn't enabled */
6806         return 19200;
6807 }
6808
6809 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6810 {
6811         struct drm_i915_private *dev_priv = dev->dev_private;
6812         uint32_t lcpll = I915_READ(LCPLL_CTL);
6813         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6814
6815         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6816                 return 800000;
6817         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6818                 return 450000;
6819         else if (freq == LCPLL_CLK_FREQ_450)
6820                 return 450000;
6821         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6822                 return 540000;
6823         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6824                 return 337500;
6825         else
6826                 return 675000;
6827 }
6828
6829 static int haswell_get_display_clock_speed(struct drm_device *dev)
6830 {
6831         struct drm_i915_private *dev_priv = dev->dev_private;
6832         uint32_t lcpll = I915_READ(LCPLL_CTL);
6833         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6834
6835         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6836                 return 800000;
6837         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6838                 return 450000;
6839         else if (freq == LCPLL_CLK_FREQ_450)
6840                 return 450000;
6841         else if (IS_HSW_ULT(dev))
6842                 return 337500;
6843         else
6844                 return 540000;
6845 }
6846
6847 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6850                                       CCK_DISPLAY_CLOCK_CONTROL);
6851 }
6852
6853 static int ilk_get_display_clock_speed(struct drm_device *dev)
6854 {
6855         return 450000;
6856 }
6857
6858 static int i945_get_display_clock_speed(struct drm_device *dev)
6859 {
6860         return 400000;
6861 }
6862
6863 static int i915_get_display_clock_speed(struct drm_device *dev)
6864 {
6865         return 333333;
6866 }
6867
6868 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6869 {
6870         return 200000;
6871 }
6872
6873 static int pnv_get_display_clock_speed(struct drm_device *dev)
6874 {
6875         u16 gcfgc = 0;
6876
6877         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6878
6879         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6880         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6881                 return 266667;
6882         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6883                 return 333333;
6884         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6885                 return 444444;
6886         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6887                 return 200000;
6888         default:
6889                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6890         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6891                 return 133333;
6892         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6893                 return 166667;
6894         }
6895 }
6896
6897 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6898 {
6899         u16 gcfgc = 0;
6900
6901         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6902
6903         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6904                 return 133333;
6905         else {
6906                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6907                 case GC_DISPLAY_CLOCK_333_MHZ:
6908                         return 333333;
6909                 default:
6910                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6911                         return 190000;
6912                 }
6913         }
6914 }
6915
6916 static int i865_get_display_clock_speed(struct drm_device *dev)
6917 {
6918         return 266667;
6919 }
6920
6921 static int i85x_get_display_clock_speed(struct drm_device *dev)
6922 {
6923         u16 hpllcc = 0;
6924
6925         /*
6926          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6927          * encoding is different :(
6928          * FIXME is this the right way to detect 852GM/852GMV?
6929          */
6930         if (dev->pdev->revision == 0x1)
6931                 return 133333;
6932
6933         pci_bus_read_config_word(dev->pdev->bus,
6934                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6935
6936         /* Assume that the hardware is in the high speed state.  This
6937          * should be the default.
6938          */
6939         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6940         case GC_CLOCK_133_200:
6941         case GC_CLOCK_133_200_2:
6942         case GC_CLOCK_100_200:
6943                 return 200000;
6944         case GC_CLOCK_166_250:
6945                 return 250000;
6946         case GC_CLOCK_100_133:
6947                 return 133333;
6948         case GC_CLOCK_133_266:
6949         case GC_CLOCK_133_266_2:
6950         case GC_CLOCK_166_266:
6951                 return 266667;
6952         }
6953
6954         /* Shouldn't happen */
6955         return 0;
6956 }
6957
6958 static int i830_get_display_clock_speed(struct drm_device *dev)
6959 {
6960         return 133333;
6961 }
6962
6963 static unsigned int intel_hpll_vco(struct drm_device *dev)
6964 {
6965         struct drm_i915_private *dev_priv = dev->dev_private;
6966         static const unsigned int blb_vco[8] = {
6967                 [0] = 3200000,
6968                 [1] = 4000000,
6969                 [2] = 5333333,
6970                 [3] = 4800000,
6971                 [4] = 6400000,
6972         };
6973         static const unsigned int pnv_vco[8] = {
6974                 [0] = 3200000,
6975                 [1] = 4000000,
6976                 [2] = 5333333,
6977                 [3] = 4800000,
6978                 [4] = 2666667,
6979         };
6980         static const unsigned int cl_vco[8] = {
6981                 [0] = 3200000,
6982                 [1] = 4000000,
6983                 [2] = 5333333,
6984                 [3] = 6400000,
6985                 [4] = 3333333,
6986                 [5] = 3566667,
6987                 [6] = 4266667,
6988         };
6989         static const unsigned int elk_vco[8] = {
6990                 [0] = 3200000,
6991                 [1] = 4000000,
6992                 [2] = 5333333,
6993                 [3] = 4800000,
6994         };
6995         static const unsigned int ctg_vco[8] = {
6996                 [0] = 3200000,
6997                 [1] = 4000000,
6998                 [2] = 5333333,
6999                 [3] = 6400000,
7000                 [4] = 2666667,
7001                 [5] = 4266667,
7002         };
7003         const unsigned int *vco_table;
7004         unsigned int vco;
7005         uint8_t tmp = 0;
7006
7007         /* FIXME other chipsets? */
7008         if (IS_GM45(dev))
7009                 vco_table = ctg_vco;
7010         else if (IS_G4X(dev))
7011                 vco_table = elk_vco;
7012         else if (IS_CRESTLINE(dev))
7013                 vco_table = cl_vco;
7014         else if (IS_PINEVIEW(dev))
7015                 vco_table = pnv_vco;
7016         else if (IS_G33(dev))
7017                 vco_table = blb_vco;
7018         else
7019                 return 0;
7020
7021         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7022
7023         vco = vco_table[tmp & 0x7];
7024         if (vco == 0)
7025                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7026         else
7027                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7028
7029         return vco;
7030 }
7031
7032 static int gm45_get_display_clock_speed(struct drm_device *dev)
7033 {
7034         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7035         uint16_t tmp = 0;
7036
7037         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7038
7039         cdclk_sel = (tmp >> 12) & 0x1;
7040
7041         switch (vco) {
7042         case 2666667:
7043         case 4000000:
7044         case 5333333:
7045                 return cdclk_sel ? 333333 : 222222;
7046         case 3200000:
7047                 return cdclk_sel ? 320000 : 228571;
7048         default:
7049                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7050                 return 222222;
7051         }
7052 }
7053
7054 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7055 {
7056         static const uint8_t div_3200[] = { 16, 10,  8 };
7057         static const uint8_t div_4000[] = { 20, 12, 10 };
7058         static const uint8_t div_5333[] = { 24, 16, 14 };
7059         const uint8_t *div_table;
7060         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7061         uint16_t tmp = 0;
7062
7063         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7064
7065         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7066
7067         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7068                 goto fail;
7069
7070         switch (vco) {
7071         case 3200000:
7072                 div_table = div_3200;
7073                 break;
7074         case 4000000:
7075                 div_table = div_4000;
7076                 break;
7077         case 5333333:
7078                 div_table = div_5333;
7079                 break;
7080         default:
7081                 goto fail;
7082         }
7083
7084         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7085
7086 fail:
7087         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7088         return 200000;
7089 }
7090
7091 static int g33_get_display_clock_speed(struct drm_device *dev)
7092 {
7093         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
7094         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
7095         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7096         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7097         const uint8_t *div_table;
7098         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7099         uint16_t tmp = 0;
7100
7101         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7102
7103         cdclk_sel = (tmp >> 4) & 0x7;
7104
7105         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7106                 goto fail;
7107
7108         switch (vco) {
7109         case 3200000:
7110                 div_table = div_3200;
7111                 break;
7112         case 4000000:
7113                 div_table = div_4000;
7114                 break;
7115         case 4800000:
7116                 div_table = div_4800;
7117                 break;
7118         case 5333333:
7119                 div_table = div_5333;
7120                 break;
7121         default:
7122                 goto fail;
7123         }
7124
7125         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7126
7127 fail:
7128         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7129         return 190476;
7130 }
7131
7132 static void
7133 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7134 {
7135         while (*num > DATA_LINK_M_N_MASK ||
7136                *den > DATA_LINK_M_N_MASK) {
7137                 *num >>= 1;
7138                 *den >>= 1;
7139         }
7140 }
7141
7142 static void compute_m_n(unsigned int m, unsigned int n,
7143                         uint32_t *ret_m, uint32_t *ret_n)
7144 {
7145         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7146         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7147         intel_reduce_m_n_ratio(ret_m, ret_n);
7148 }
7149
7150 void
7151 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7152                        int pixel_clock, int link_clock,
7153                        struct intel_link_m_n *m_n)
7154 {
7155         m_n->tu = 64;
7156
7157         compute_m_n(bits_per_pixel * pixel_clock,
7158                     link_clock * nlanes * 8,
7159                     &m_n->gmch_m, &m_n->gmch_n);
7160
7161         compute_m_n(pixel_clock, link_clock,
7162                     &m_n->link_m, &m_n->link_n);
7163 }
7164
7165 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7166 {
7167         if (i915.panel_use_ssc >= 0)
7168                 return i915.panel_use_ssc != 0;
7169         return dev_priv->vbt.lvds_use_ssc
7170                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7171 }
7172
7173 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7174                            int num_connectors)
7175 {
7176         struct drm_device *dev = crtc_state->base.crtc->dev;
7177         struct drm_i915_private *dev_priv = dev->dev_private;
7178         int refclk;
7179
7180         WARN_ON(!crtc_state->base.state);
7181
7182         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7183                 refclk = 100000;
7184         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7185             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7186                 refclk = dev_priv->vbt.lvds_ssc_freq;
7187                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7188         } else if (!IS_GEN2(dev)) {
7189                 refclk = 96000;
7190         } else {
7191                 refclk = 48000;
7192         }
7193
7194         return refclk;
7195 }
7196
7197 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7198 {
7199         return (1 << dpll->n) << 16 | dpll->m2;
7200 }
7201
7202 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7203 {
7204         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7205 }
7206
7207 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7208                                      struct intel_crtc_state *crtc_state,
7209                                      intel_clock_t *reduced_clock)
7210 {
7211         struct drm_device *dev = crtc->base.dev;
7212         u32 fp, fp2 = 0;
7213
7214         if (IS_PINEVIEW(dev)) {
7215                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7216                 if (reduced_clock)
7217                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7218         } else {
7219                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7220                 if (reduced_clock)
7221                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7222         }
7223
7224         crtc_state->dpll_hw_state.fp0 = fp;
7225
7226         crtc->lowfreq_avail = false;
7227         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7228             reduced_clock) {
7229                 crtc_state->dpll_hw_state.fp1 = fp2;
7230                 crtc->lowfreq_avail = true;
7231         } else {
7232                 crtc_state->dpll_hw_state.fp1 = fp;
7233         }
7234 }
7235
7236 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7237                 pipe)
7238 {
7239         u32 reg_val;
7240
7241         /*
7242          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7243          * and set it to a reasonable value instead.
7244          */
7245         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7246         reg_val &= 0xffffff00;
7247         reg_val |= 0x00000030;
7248         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7249
7250         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7251         reg_val &= 0x8cffffff;
7252         reg_val = 0x8c000000;
7253         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7254
7255         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7256         reg_val &= 0xffffff00;
7257         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7258
7259         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7260         reg_val &= 0x00ffffff;
7261         reg_val |= 0xb0000000;
7262         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7263 }
7264
7265 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7266                                          struct intel_link_m_n *m_n)
7267 {
7268         struct drm_device *dev = crtc->base.dev;
7269         struct drm_i915_private *dev_priv = dev->dev_private;
7270         int pipe = crtc->pipe;
7271
7272         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7273         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7274         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7275         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7276 }
7277
7278 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7279                                          struct intel_link_m_n *m_n,
7280                                          struct intel_link_m_n *m2_n2)
7281 {
7282         struct drm_device *dev = crtc->base.dev;
7283         struct drm_i915_private *dev_priv = dev->dev_private;
7284         int pipe = crtc->pipe;
7285         enum transcoder transcoder = crtc->config->cpu_transcoder;
7286
7287         if (INTEL_INFO(dev)->gen >= 5) {
7288                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7289                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7290                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7291                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7292                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7293                  * for gen < 8) and if DRRS is supported (to make sure the
7294                  * registers are not unnecessarily accessed).
7295                  */
7296                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7297                         crtc->config->has_drrs) {
7298                         I915_WRITE(PIPE_DATA_M2(transcoder),
7299                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7300                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7301                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7302                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7303                 }
7304         } else {
7305                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7306                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7307                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7308                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7309         }
7310 }
7311
7312 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7313 {
7314         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7315
7316         if (m_n == M1_N1) {
7317                 dp_m_n = &crtc->config->dp_m_n;
7318                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7319         } else if (m_n == M2_N2) {
7320
7321                 /*
7322                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7323                  * needs to be programmed into M1_N1.
7324                  */
7325                 dp_m_n = &crtc->config->dp_m2_n2;
7326         } else {
7327                 DRM_ERROR("Unsupported divider value\n");
7328                 return;
7329         }
7330
7331         if (crtc->config->has_pch_encoder)
7332                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7333         else
7334                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7335 }
7336
7337 static void vlv_compute_dpll(struct intel_crtc *crtc,
7338                              struct intel_crtc_state *pipe_config)
7339 {
7340         u32 dpll, dpll_md;
7341
7342         /*
7343          * Enable DPIO clock input. We should never disable the reference
7344          * clock for pipe B, since VGA hotplug / manual detection depends
7345          * on it.
7346          */
7347         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7348                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7349         /* We should never disable this, set it here for state tracking */
7350         if (crtc->pipe == PIPE_B)
7351                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7352         dpll |= DPLL_VCO_ENABLE;
7353         pipe_config->dpll_hw_state.dpll = dpll;
7354
7355         dpll_md = (pipe_config->pixel_multiplier - 1)
7356                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7357         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7358 }
7359
7360 static void vlv_prepare_pll(struct intel_crtc *crtc,
7361                             const struct intel_crtc_state *pipe_config)
7362 {
7363         struct drm_device *dev = crtc->base.dev;
7364         struct drm_i915_private *dev_priv = dev->dev_private;
7365         int pipe = crtc->pipe;
7366         u32 mdiv;
7367         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7368         u32 coreclk, reg_val;
7369
7370         mutex_lock(&dev_priv->sb_lock);
7371
7372         bestn = pipe_config->dpll.n;
7373         bestm1 = pipe_config->dpll.m1;
7374         bestm2 = pipe_config->dpll.m2;
7375         bestp1 = pipe_config->dpll.p1;
7376         bestp2 = pipe_config->dpll.p2;
7377
7378         /* See eDP HDMI DPIO driver vbios notes doc */
7379
7380         /* PLL B needs special handling */
7381         if (pipe == PIPE_B)
7382                 vlv_pllb_recal_opamp(dev_priv, pipe);
7383
7384         /* Set up Tx target for periodic Rcomp update */
7385         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7386
7387         /* Disable target IRef on PLL */
7388         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7389         reg_val &= 0x00ffffff;
7390         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7391
7392         /* Disable fast lock */
7393         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7394
7395         /* Set idtafcrecal before PLL is enabled */
7396         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7397         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7398         mdiv |= ((bestn << DPIO_N_SHIFT));
7399         mdiv |= (1 << DPIO_K_SHIFT);
7400
7401         /*
7402          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7403          * but we don't support that).
7404          * Note: don't use the DAC post divider as it seems unstable.
7405          */
7406         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7407         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7408
7409         mdiv |= DPIO_ENABLE_CALIBRATION;
7410         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7411
7412         /* Set HBR and RBR LPF coefficients */
7413         if (pipe_config->port_clock == 162000 ||
7414             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7415             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7416                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7417                                  0x009f0003);
7418         else
7419                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7420                                  0x00d0000f);
7421
7422         if (pipe_config->has_dp_encoder) {
7423                 /* Use SSC source */
7424                 if (pipe == PIPE_A)
7425                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7426                                          0x0df40000);
7427                 else
7428                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7429                                          0x0df70000);
7430         } else { /* HDMI or VGA */
7431                 /* Use bend source */
7432                 if (pipe == PIPE_A)
7433                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7434                                          0x0df70000);
7435                 else
7436                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7437                                          0x0df40000);
7438         }
7439
7440         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7441         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7442         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7443             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7444                 coreclk |= 0x01000000;
7445         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7446
7447         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7448         mutex_unlock(&dev_priv->sb_lock);
7449 }
7450
7451 static void chv_compute_dpll(struct intel_crtc *crtc,
7452                              struct intel_crtc_state *pipe_config)
7453 {
7454         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7455                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7456                 DPLL_VCO_ENABLE;
7457         if (crtc->pipe != PIPE_A)
7458                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7459
7460         pipe_config->dpll_hw_state.dpll_md =
7461                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7462 }
7463
7464 static void chv_prepare_pll(struct intel_crtc *crtc,
7465                             const struct intel_crtc_state *pipe_config)
7466 {
7467         struct drm_device *dev = crtc->base.dev;
7468         struct drm_i915_private *dev_priv = dev->dev_private;
7469         int pipe = crtc->pipe;
7470         i915_reg_t dpll_reg = DPLL(crtc->pipe);
7471         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7472         u32 loopfilter, tribuf_calcntr;
7473         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7474         u32 dpio_val;
7475         int vco;
7476
7477         bestn = pipe_config->dpll.n;
7478         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7479         bestm1 = pipe_config->dpll.m1;
7480         bestm2 = pipe_config->dpll.m2 >> 22;
7481         bestp1 = pipe_config->dpll.p1;
7482         bestp2 = pipe_config->dpll.p2;
7483         vco = pipe_config->dpll.vco;
7484         dpio_val = 0;
7485         loopfilter = 0;
7486
7487         /*
7488          * Enable Refclk and SSC
7489          */
7490         I915_WRITE(dpll_reg,
7491                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7492
7493         mutex_lock(&dev_priv->sb_lock);
7494
7495         /* p1 and p2 divider */
7496         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7497                         5 << DPIO_CHV_S1_DIV_SHIFT |
7498                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7499                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7500                         1 << DPIO_CHV_K_DIV_SHIFT);
7501
7502         /* Feedback post-divider - m2 */
7503         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7504
7505         /* Feedback refclk divider - n and m1 */
7506         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7507                         DPIO_CHV_M1_DIV_BY_2 |
7508                         1 << DPIO_CHV_N_DIV_SHIFT);
7509
7510         /* M2 fraction division */
7511         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7512
7513         /* M2 fraction division enable */
7514         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7515         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7516         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7517         if (bestm2_frac)
7518                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7519         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7520
7521         /* Program digital lock detect threshold */
7522         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7523         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7524                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7525         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7526         if (!bestm2_frac)
7527                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7528         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7529
7530         /* Loop filter */
7531         if (vco == 5400000) {
7532                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7533                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7534                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7535                 tribuf_calcntr = 0x9;
7536         } else if (vco <= 6200000) {
7537                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7538                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7539                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7540                 tribuf_calcntr = 0x9;
7541         } else if (vco <= 6480000) {
7542                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7543                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7544                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7545                 tribuf_calcntr = 0x8;
7546         } else {
7547                 /* Not supported. Apply the same limits as in the max case */
7548                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7549                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7550                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7551                 tribuf_calcntr = 0;
7552         }
7553         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7554
7555         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7556         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7557         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7558         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7559
7560         /* AFC Recal */
7561         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7562                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7563                         DPIO_AFC_RECAL);
7564
7565         mutex_unlock(&dev_priv->sb_lock);
7566 }
7567
7568 /**
7569  * vlv_force_pll_on - forcibly enable just the PLL
7570  * @dev_priv: i915 private structure
7571  * @pipe: pipe PLL to enable
7572  * @dpll: PLL configuration
7573  *
7574  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7575  * in cases where we need the PLL enabled even when @pipe is not going to
7576  * be enabled.
7577  */
7578 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7579                       const struct dpll *dpll)
7580 {
7581         struct intel_crtc *crtc =
7582                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7583         struct intel_crtc_state pipe_config = {
7584                 .base.crtc = &crtc->base,
7585                 .pixel_multiplier = 1,
7586                 .dpll = *dpll,
7587         };
7588
7589         if (IS_CHERRYVIEW(dev)) {
7590                 chv_compute_dpll(crtc, &pipe_config);
7591                 chv_prepare_pll(crtc, &pipe_config);
7592                 chv_enable_pll(crtc, &pipe_config);
7593         } else {
7594                 vlv_compute_dpll(crtc, &pipe_config);
7595                 vlv_prepare_pll(crtc, &pipe_config);
7596                 vlv_enable_pll(crtc, &pipe_config);
7597         }
7598 }
7599
7600 /**
7601  * vlv_force_pll_off - forcibly disable just the PLL
7602  * @dev_priv: i915 private structure
7603  * @pipe: pipe PLL to disable
7604  *
7605  * Disable the PLL for @pipe. To be used in cases where we need
7606  * the PLL enabled even when @pipe is not going to be enabled.
7607  */
7608 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7609 {
7610         if (IS_CHERRYVIEW(dev))
7611                 chv_disable_pll(to_i915(dev), pipe);
7612         else
7613                 vlv_disable_pll(to_i915(dev), pipe);
7614 }
7615
7616 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7617                               struct intel_crtc_state *crtc_state,
7618                               intel_clock_t *reduced_clock,
7619                               int num_connectors)
7620 {
7621         struct drm_device *dev = crtc->base.dev;
7622         struct drm_i915_private *dev_priv = dev->dev_private;
7623         u32 dpll;
7624         bool is_sdvo;
7625         struct dpll *clock = &crtc_state->dpll;
7626
7627         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7628
7629         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7630                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7631
7632         dpll = DPLL_VGA_MODE_DIS;
7633
7634         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7635                 dpll |= DPLLB_MODE_LVDS;
7636         else
7637                 dpll |= DPLLB_MODE_DAC_SERIAL;
7638
7639         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7640                 dpll |= (crtc_state->pixel_multiplier - 1)
7641                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7642         }
7643
7644         if (is_sdvo)
7645                 dpll |= DPLL_SDVO_HIGH_SPEED;
7646
7647         if (crtc_state->has_dp_encoder)
7648                 dpll |= DPLL_SDVO_HIGH_SPEED;
7649
7650         /* compute bitmask from p1 value */
7651         if (IS_PINEVIEW(dev))
7652                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7653         else {
7654                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7655                 if (IS_G4X(dev) && reduced_clock)
7656                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7657         }
7658         switch (clock->p2) {
7659         case 5:
7660                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7661                 break;
7662         case 7:
7663                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7664                 break;
7665         case 10:
7666                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7667                 break;
7668         case 14:
7669                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7670                 break;
7671         }
7672         if (INTEL_INFO(dev)->gen >= 4)
7673                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7674
7675         if (crtc_state->sdvo_tv_clock)
7676                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7677         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7678                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7679                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7680         else
7681                 dpll |= PLL_REF_INPUT_DREFCLK;
7682
7683         dpll |= DPLL_VCO_ENABLE;
7684         crtc_state->dpll_hw_state.dpll = dpll;
7685
7686         if (INTEL_INFO(dev)->gen >= 4) {
7687                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7688                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7689                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7690         }
7691 }
7692
7693 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7694                               struct intel_crtc_state *crtc_state,
7695                               intel_clock_t *reduced_clock,
7696                               int num_connectors)
7697 {
7698         struct drm_device *dev = crtc->base.dev;
7699         struct drm_i915_private *dev_priv = dev->dev_private;
7700         u32 dpll;
7701         struct dpll *clock = &crtc_state->dpll;
7702
7703         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7704
7705         dpll = DPLL_VGA_MODE_DIS;
7706
7707         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7708                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7709         } else {
7710                 if (clock->p1 == 2)
7711                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7712                 else
7713                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7714                 if (clock->p2 == 4)
7715                         dpll |= PLL_P2_DIVIDE_BY_4;
7716         }
7717
7718         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7719                 dpll |= DPLL_DVO_2X_MODE;
7720
7721         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7722                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7723                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7724         else
7725                 dpll |= PLL_REF_INPUT_DREFCLK;
7726
7727         dpll |= DPLL_VCO_ENABLE;
7728         crtc_state->dpll_hw_state.dpll = dpll;
7729 }
7730
7731 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7732 {
7733         struct drm_device *dev = intel_crtc->base.dev;
7734         struct drm_i915_private *dev_priv = dev->dev_private;
7735         enum pipe pipe = intel_crtc->pipe;
7736         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7737         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7738         uint32_t crtc_vtotal, crtc_vblank_end;
7739         int vsyncshift = 0;
7740
7741         /* We need to be careful not to changed the adjusted mode, for otherwise
7742          * the hw state checker will get angry at the mismatch. */
7743         crtc_vtotal = adjusted_mode->crtc_vtotal;
7744         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7745
7746         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7747                 /* the chip adds 2 halflines automatically */
7748                 crtc_vtotal -= 1;
7749                 crtc_vblank_end -= 1;
7750
7751                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7752                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7753                 else
7754                         vsyncshift = adjusted_mode->crtc_hsync_start -
7755                                 adjusted_mode->crtc_htotal / 2;
7756                 if (vsyncshift < 0)
7757                         vsyncshift += adjusted_mode->crtc_htotal;
7758         }
7759
7760         if (INTEL_INFO(dev)->gen > 3)
7761                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7762
7763         I915_WRITE(HTOTAL(cpu_transcoder),
7764                    (adjusted_mode->crtc_hdisplay - 1) |
7765                    ((adjusted_mode->crtc_htotal - 1) << 16));
7766         I915_WRITE(HBLANK(cpu_transcoder),
7767                    (adjusted_mode->crtc_hblank_start - 1) |
7768                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7769         I915_WRITE(HSYNC(cpu_transcoder),
7770                    (adjusted_mode->crtc_hsync_start - 1) |
7771                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7772
7773         I915_WRITE(VTOTAL(cpu_transcoder),
7774                    (adjusted_mode->crtc_vdisplay - 1) |
7775                    ((crtc_vtotal - 1) << 16));
7776         I915_WRITE(VBLANK(cpu_transcoder),
7777                    (adjusted_mode->crtc_vblank_start - 1) |
7778                    ((crtc_vblank_end - 1) << 16));
7779         I915_WRITE(VSYNC(cpu_transcoder),
7780                    (adjusted_mode->crtc_vsync_start - 1) |
7781                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7782
7783         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7784          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7785          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7786          * bits. */
7787         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7788             (pipe == PIPE_B || pipe == PIPE_C))
7789                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7790
7791         /* pipesrc controls the size that is scaled from, which should
7792          * always be the user's requested size.
7793          */
7794         I915_WRITE(PIPESRC(pipe),
7795                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7796                    (intel_crtc->config->pipe_src_h - 1));
7797 }
7798
7799 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7800                                    struct intel_crtc_state *pipe_config)
7801 {
7802         struct drm_device *dev = crtc->base.dev;
7803         struct drm_i915_private *dev_priv = dev->dev_private;
7804         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7805         uint32_t tmp;
7806
7807         tmp = I915_READ(HTOTAL(cpu_transcoder));
7808         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7809         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7810         tmp = I915_READ(HBLANK(cpu_transcoder));
7811         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7812         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7813         tmp = I915_READ(HSYNC(cpu_transcoder));
7814         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7815         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7816
7817         tmp = I915_READ(VTOTAL(cpu_transcoder));
7818         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7819         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7820         tmp = I915_READ(VBLANK(cpu_transcoder));
7821         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7822         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7823         tmp = I915_READ(VSYNC(cpu_transcoder));
7824         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7825         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7826
7827         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7828                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7829                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7830                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7831         }
7832
7833         tmp = I915_READ(PIPESRC(crtc->pipe));
7834         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7835         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7836
7837         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7838         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7839 }
7840
7841 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7842                                  struct intel_crtc_state *pipe_config)
7843 {
7844         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7845         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7846         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7847         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7848
7849         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7850         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7851         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7852         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7853
7854         mode->flags = pipe_config->base.adjusted_mode.flags;
7855         mode->type = DRM_MODE_TYPE_DRIVER;
7856
7857         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7858         mode->flags |= pipe_config->base.adjusted_mode.flags;
7859
7860         mode->hsync = drm_mode_hsync(mode);
7861         mode->vrefresh = drm_mode_vrefresh(mode);
7862         drm_mode_set_name(mode);
7863 }
7864
7865 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7866 {
7867         struct drm_device *dev = intel_crtc->base.dev;
7868         struct drm_i915_private *dev_priv = dev->dev_private;
7869         uint32_t pipeconf;
7870
7871         pipeconf = 0;
7872
7873         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7874             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7875                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7876
7877         if (intel_crtc->config->double_wide)
7878                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7879
7880         /* only g4x and later have fancy bpc/dither controls */
7881         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7882                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7883                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7884                         pipeconf |= PIPECONF_DITHER_EN |
7885                                     PIPECONF_DITHER_TYPE_SP;
7886
7887                 switch (intel_crtc->config->pipe_bpp) {
7888                 case 18:
7889                         pipeconf |= PIPECONF_6BPC;
7890                         break;
7891                 case 24:
7892                         pipeconf |= PIPECONF_8BPC;
7893                         break;
7894                 case 30:
7895                         pipeconf |= PIPECONF_10BPC;
7896                         break;
7897                 default:
7898                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7899                         BUG();
7900                 }
7901         }
7902
7903         if (HAS_PIPE_CXSR(dev)) {
7904                 if (intel_crtc->lowfreq_avail) {
7905                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7906                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7907                 } else {
7908                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7909                 }
7910         }
7911
7912         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7913                 if (INTEL_INFO(dev)->gen < 4 ||
7914                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7915                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7916                 else
7917                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7918         } else
7919                 pipeconf |= PIPECONF_PROGRESSIVE;
7920
7921         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7922                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7923
7924         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7925         POSTING_READ(PIPECONF(intel_crtc->pipe));
7926 }
7927
7928 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7929                                    struct intel_crtc_state *crtc_state)
7930 {
7931         struct drm_device *dev = crtc->base.dev;
7932         struct drm_i915_private *dev_priv = dev->dev_private;
7933         int refclk, num_connectors = 0;
7934         intel_clock_t clock;
7935         bool ok;
7936         const intel_limit_t *limit;
7937         struct drm_atomic_state *state = crtc_state->base.state;
7938         struct drm_connector *connector;
7939         struct drm_connector_state *connector_state;
7940         int i;
7941
7942         memset(&crtc_state->dpll_hw_state, 0,
7943                sizeof(crtc_state->dpll_hw_state));
7944
7945         if (crtc_state->has_dsi_encoder)
7946                 return 0;
7947
7948         for_each_connector_in_state(state, connector, connector_state, i) {
7949                 if (connector_state->crtc == &crtc->base)
7950                         num_connectors++;
7951         }
7952
7953         if (!crtc_state->clock_set) {
7954                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7955
7956                 /*
7957                  * Returns a set of divisors for the desired target clock with
7958                  * the given refclk, or FALSE.  The returned values represent
7959                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7960                  * 2) / p1 / p2.
7961                  */
7962                 limit = intel_limit(crtc_state, refclk);
7963                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7964                                                  crtc_state->port_clock,
7965                                                  refclk, NULL, &clock);
7966                 if (!ok) {
7967                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7968                         return -EINVAL;
7969                 }
7970
7971                 /* Compat-code for transition, will disappear. */
7972                 crtc_state->dpll.n = clock.n;
7973                 crtc_state->dpll.m1 = clock.m1;
7974                 crtc_state->dpll.m2 = clock.m2;
7975                 crtc_state->dpll.p1 = clock.p1;
7976                 crtc_state->dpll.p2 = clock.p2;
7977         }
7978
7979         if (IS_GEN2(dev)) {
7980                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7981                                   num_connectors);
7982         } else if (IS_CHERRYVIEW(dev)) {
7983                 chv_compute_dpll(crtc, crtc_state);
7984         } else if (IS_VALLEYVIEW(dev)) {
7985                 vlv_compute_dpll(crtc, crtc_state);
7986         } else {
7987                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7988                                   num_connectors);
7989         }
7990
7991         return 0;
7992 }
7993
7994 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7995                                  struct intel_crtc_state *pipe_config)
7996 {
7997         struct drm_device *dev = crtc->base.dev;
7998         struct drm_i915_private *dev_priv = dev->dev_private;
7999         uint32_t tmp;
8000
8001         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8002                 return;
8003
8004         tmp = I915_READ(PFIT_CONTROL);
8005         if (!(tmp & PFIT_ENABLE))
8006                 return;
8007
8008         /* Check whether the pfit is attached to our pipe. */
8009         if (INTEL_INFO(dev)->gen < 4) {
8010                 if (crtc->pipe != PIPE_B)
8011                         return;
8012         } else {
8013                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8014                         return;
8015         }
8016
8017         pipe_config->gmch_pfit.control = tmp;
8018         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8019         if (INTEL_INFO(dev)->gen < 5)
8020                 pipe_config->gmch_pfit.lvds_border_bits =
8021                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8022 }
8023
8024 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8025                                struct intel_crtc_state *pipe_config)
8026 {
8027         struct drm_device *dev = crtc->base.dev;
8028         struct drm_i915_private *dev_priv = dev->dev_private;
8029         int pipe = pipe_config->cpu_transcoder;
8030         intel_clock_t clock;
8031         u32 mdiv;
8032         int refclk = 100000;
8033
8034         /* In case of MIPI DPLL will not even be used */
8035         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8036                 return;
8037
8038         mutex_lock(&dev_priv->sb_lock);
8039         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8040         mutex_unlock(&dev_priv->sb_lock);
8041
8042         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8043         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8044         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8045         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8046         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8047
8048         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8049 }
8050
8051 static void
8052 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8053                               struct intel_initial_plane_config *plane_config)
8054 {
8055         struct drm_device *dev = crtc->base.dev;
8056         struct drm_i915_private *dev_priv = dev->dev_private;
8057         u32 val, base, offset;
8058         int pipe = crtc->pipe, plane = crtc->plane;
8059         int fourcc, pixel_format;
8060         unsigned int aligned_height;
8061         struct drm_framebuffer *fb;
8062         struct intel_framebuffer *intel_fb;
8063
8064         val = I915_READ(DSPCNTR(plane));
8065         if (!(val & DISPLAY_PLANE_ENABLE))
8066                 return;
8067
8068         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8069         if (!intel_fb) {
8070                 DRM_DEBUG_KMS("failed to alloc fb\n");
8071                 return;
8072         }
8073
8074         fb = &intel_fb->base;
8075
8076         if (INTEL_INFO(dev)->gen >= 4) {
8077                 if (val & DISPPLANE_TILED) {
8078                         plane_config->tiling = I915_TILING_X;
8079                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8080                 }
8081         }
8082
8083         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8084         fourcc = i9xx_format_to_fourcc(pixel_format);
8085         fb->pixel_format = fourcc;
8086         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8087
8088         if (INTEL_INFO(dev)->gen >= 4) {
8089                 if (plane_config->tiling)
8090                         offset = I915_READ(DSPTILEOFF(plane));
8091                 else
8092                         offset = I915_READ(DSPLINOFF(plane));
8093                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8094         } else {
8095                 base = I915_READ(DSPADDR(plane));
8096         }
8097         plane_config->base = base;
8098
8099         val = I915_READ(PIPESRC(pipe));
8100         fb->width = ((val >> 16) & 0xfff) + 1;
8101         fb->height = ((val >> 0) & 0xfff) + 1;
8102
8103         val = I915_READ(DSPSTRIDE(pipe));
8104         fb->pitches[0] = val & 0xffffffc0;
8105
8106         aligned_height = intel_fb_align_height(dev, fb->height,
8107                                                fb->pixel_format,
8108                                                fb->modifier[0]);
8109
8110         plane_config->size = fb->pitches[0] * aligned_height;
8111
8112         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8113                       pipe_name(pipe), plane, fb->width, fb->height,
8114                       fb->bits_per_pixel, base, fb->pitches[0],
8115                       plane_config->size);
8116
8117         plane_config->fb = intel_fb;
8118 }
8119
8120 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8121                                struct intel_crtc_state *pipe_config)
8122 {
8123         struct drm_device *dev = crtc->base.dev;
8124         struct drm_i915_private *dev_priv = dev->dev_private;
8125         int pipe = pipe_config->cpu_transcoder;
8126         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8127         intel_clock_t clock;
8128         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8129         int refclk = 100000;
8130
8131         mutex_lock(&dev_priv->sb_lock);
8132         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8133         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8134         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8135         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8136         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8137         mutex_unlock(&dev_priv->sb_lock);
8138
8139         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8140         clock.m2 = (pll_dw0 & 0xff) << 22;
8141         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8142                 clock.m2 |= pll_dw2 & 0x3fffff;
8143         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8144         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8145         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8146
8147         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8148 }
8149
8150 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8151                                  struct intel_crtc_state *pipe_config)
8152 {
8153         struct drm_device *dev = crtc->base.dev;
8154         struct drm_i915_private *dev_priv = dev->dev_private;
8155         uint32_t tmp;
8156
8157         if (!intel_display_power_is_enabled(dev_priv,
8158                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8159                 return false;
8160
8161         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8162         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8163
8164         tmp = I915_READ(PIPECONF(crtc->pipe));
8165         if (!(tmp & PIPECONF_ENABLE))
8166                 return false;
8167
8168         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8169                 switch (tmp & PIPECONF_BPC_MASK) {
8170                 case PIPECONF_6BPC:
8171                         pipe_config->pipe_bpp = 18;
8172                         break;
8173                 case PIPECONF_8BPC:
8174                         pipe_config->pipe_bpp = 24;
8175                         break;
8176                 case PIPECONF_10BPC:
8177                         pipe_config->pipe_bpp = 30;
8178                         break;
8179                 default:
8180                         break;
8181                 }
8182         }
8183
8184         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8185                 pipe_config->limited_color_range = true;
8186
8187         if (INTEL_INFO(dev)->gen < 4)
8188                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8189
8190         intel_get_pipe_timings(crtc, pipe_config);
8191
8192         i9xx_get_pfit_config(crtc, pipe_config);
8193
8194         if (INTEL_INFO(dev)->gen >= 4) {
8195                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8196                 pipe_config->pixel_multiplier =
8197                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8198                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8199                 pipe_config->dpll_hw_state.dpll_md = tmp;
8200         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8201                 tmp = I915_READ(DPLL(crtc->pipe));
8202                 pipe_config->pixel_multiplier =
8203                         ((tmp & SDVO_MULTIPLIER_MASK)
8204                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8205         } else {
8206                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8207                  * port and will be fixed up in the encoder->get_config
8208                  * function. */
8209                 pipe_config->pixel_multiplier = 1;
8210         }
8211         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8212         if (!IS_VALLEYVIEW(dev)) {
8213                 /*
8214                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8215                  * on 830. Filter it out here so that we don't
8216                  * report errors due to that.
8217                  */
8218                 if (IS_I830(dev))
8219                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8220
8221                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8222                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8223         } else {
8224                 /* Mask out read-only status bits. */
8225                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8226                                                      DPLL_PORTC_READY_MASK |
8227                                                      DPLL_PORTB_READY_MASK);
8228         }
8229
8230         if (IS_CHERRYVIEW(dev))
8231                 chv_crtc_clock_get(crtc, pipe_config);
8232         else if (IS_VALLEYVIEW(dev))
8233                 vlv_crtc_clock_get(crtc, pipe_config);
8234         else
8235                 i9xx_crtc_clock_get(crtc, pipe_config);
8236
8237         /*
8238          * Normally the dotclock is filled in by the encoder .get_config()
8239          * but in case the pipe is enabled w/o any ports we need a sane
8240          * default.
8241          */
8242         pipe_config->base.adjusted_mode.crtc_clock =
8243                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8244
8245         return true;
8246 }
8247
8248 static void ironlake_init_pch_refclk(struct drm_device *dev)
8249 {
8250         struct drm_i915_private *dev_priv = dev->dev_private;
8251         struct intel_encoder *encoder;
8252         u32 val, final;
8253         bool has_lvds = false;
8254         bool has_cpu_edp = false;
8255         bool has_panel = false;
8256         bool has_ck505 = false;
8257         bool can_ssc = false;
8258
8259         /* We need to take the global config into account */
8260         for_each_intel_encoder(dev, encoder) {
8261                 switch (encoder->type) {
8262                 case INTEL_OUTPUT_LVDS:
8263                         has_panel = true;
8264                         has_lvds = true;
8265                         break;
8266                 case INTEL_OUTPUT_EDP:
8267                         has_panel = true;
8268                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8269                                 has_cpu_edp = true;
8270                         break;
8271                 default:
8272                         break;
8273                 }
8274         }
8275
8276         if (HAS_PCH_IBX(dev)) {
8277                 has_ck505 = dev_priv->vbt.display_clock_mode;
8278                 can_ssc = has_ck505;
8279         } else {
8280                 has_ck505 = false;
8281                 can_ssc = true;
8282         }
8283
8284         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8285                       has_panel, has_lvds, has_ck505);
8286
8287         /* Ironlake: try to setup display ref clock before DPLL
8288          * enabling. This is only under driver's control after
8289          * PCH B stepping, previous chipset stepping should be
8290          * ignoring this setting.
8291          */
8292         val = I915_READ(PCH_DREF_CONTROL);
8293
8294         /* As we must carefully and slowly disable/enable each source in turn,
8295          * compute the final state we want first and check if we need to
8296          * make any changes at all.
8297          */
8298         final = val;
8299         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8300         if (has_ck505)
8301                 final |= DREF_NONSPREAD_CK505_ENABLE;
8302         else
8303                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8304
8305         final &= ~DREF_SSC_SOURCE_MASK;
8306         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8307         final &= ~DREF_SSC1_ENABLE;
8308
8309         if (has_panel) {
8310                 final |= DREF_SSC_SOURCE_ENABLE;
8311
8312                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8313                         final |= DREF_SSC1_ENABLE;
8314
8315                 if (has_cpu_edp) {
8316                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8317                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8318                         else
8319                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8320                 } else
8321                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8322         } else {
8323                 final |= DREF_SSC_SOURCE_DISABLE;
8324                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8325         }
8326
8327         if (final == val)
8328                 return;
8329
8330         /* Always enable nonspread source */
8331         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8332
8333         if (has_ck505)
8334                 val |= DREF_NONSPREAD_CK505_ENABLE;
8335         else
8336                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8337
8338         if (has_panel) {
8339                 val &= ~DREF_SSC_SOURCE_MASK;
8340                 val |= DREF_SSC_SOURCE_ENABLE;
8341
8342                 /* SSC must be turned on before enabling the CPU output  */
8343                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8344                         DRM_DEBUG_KMS("Using SSC on panel\n");
8345                         val |= DREF_SSC1_ENABLE;
8346                 } else
8347                         val &= ~DREF_SSC1_ENABLE;
8348
8349                 /* Get SSC going before enabling the outputs */
8350                 I915_WRITE(PCH_DREF_CONTROL, val);
8351                 POSTING_READ(PCH_DREF_CONTROL);
8352                 udelay(200);
8353
8354                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8355
8356                 /* Enable CPU source on CPU attached eDP */
8357                 if (has_cpu_edp) {
8358                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8359                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8360                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8361                         } else
8362                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8363                 } else
8364                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8365
8366                 I915_WRITE(PCH_DREF_CONTROL, val);
8367                 POSTING_READ(PCH_DREF_CONTROL);
8368                 udelay(200);
8369         } else {
8370                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8371
8372                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8373
8374                 /* Turn off CPU output */
8375                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8376
8377                 I915_WRITE(PCH_DREF_CONTROL, val);
8378                 POSTING_READ(PCH_DREF_CONTROL);
8379                 udelay(200);
8380
8381                 /* Turn off the SSC source */
8382                 val &= ~DREF_SSC_SOURCE_MASK;
8383                 val |= DREF_SSC_SOURCE_DISABLE;
8384
8385                 /* Turn off SSC1 */
8386                 val &= ~DREF_SSC1_ENABLE;
8387
8388                 I915_WRITE(PCH_DREF_CONTROL, val);
8389                 POSTING_READ(PCH_DREF_CONTROL);
8390                 udelay(200);
8391         }
8392
8393         BUG_ON(val != final);
8394 }
8395
8396 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8397 {
8398         uint32_t tmp;
8399
8400         tmp = I915_READ(SOUTH_CHICKEN2);
8401         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8402         I915_WRITE(SOUTH_CHICKEN2, tmp);
8403
8404         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8405                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8406                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8407
8408         tmp = I915_READ(SOUTH_CHICKEN2);
8409         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8410         I915_WRITE(SOUTH_CHICKEN2, tmp);
8411
8412         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8413                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8414                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8415 }
8416
8417 /* WaMPhyProgramming:hsw */
8418 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8419 {
8420         uint32_t tmp;
8421
8422         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8423         tmp &= ~(0xFF << 24);
8424         tmp |= (0x12 << 24);
8425         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8426
8427         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8428         tmp |= (1 << 11);
8429         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8430
8431         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8432         tmp |= (1 << 11);
8433         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8434
8435         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8436         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8437         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8438
8439         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8440         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8441         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8442
8443         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8444         tmp &= ~(7 << 13);
8445         tmp |= (5 << 13);
8446         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8449         tmp &= ~(7 << 13);
8450         tmp |= (5 << 13);
8451         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8452
8453         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8454         tmp &= ~0xFF;
8455         tmp |= 0x1C;
8456         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8457
8458         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8459         tmp &= ~0xFF;
8460         tmp |= 0x1C;
8461         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8462
8463         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8464         tmp &= ~(0xFF << 16);
8465         tmp |= (0x1C << 16);
8466         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8467
8468         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8469         tmp &= ~(0xFF << 16);
8470         tmp |= (0x1C << 16);
8471         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8472
8473         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8474         tmp |= (1 << 27);
8475         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8476
8477         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8478         tmp |= (1 << 27);
8479         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8480
8481         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8482         tmp &= ~(0xF << 28);
8483         tmp |= (4 << 28);
8484         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8485
8486         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8487         tmp &= ~(0xF << 28);
8488         tmp |= (4 << 28);
8489         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8490 }
8491
8492 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8493  * Programming" based on the parameters passed:
8494  * - Sequence to enable CLKOUT_DP
8495  * - Sequence to enable CLKOUT_DP without spread
8496  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8497  */
8498 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8499                                  bool with_fdi)
8500 {
8501         struct drm_i915_private *dev_priv = dev->dev_private;
8502         uint32_t reg, tmp;
8503
8504         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8505                 with_spread = true;
8506         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8507                 with_fdi = false;
8508
8509         mutex_lock(&dev_priv->sb_lock);
8510
8511         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8512         tmp &= ~SBI_SSCCTL_DISABLE;
8513         tmp |= SBI_SSCCTL_PATHALT;
8514         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8515
8516         udelay(24);
8517
8518         if (with_spread) {
8519                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8520                 tmp &= ~SBI_SSCCTL_PATHALT;
8521                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8522
8523                 if (with_fdi) {
8524                         lpt_reset_fdi_mphy(dev_priv);
8525                         lpt_program_fdi_mphy(dev_priv);
8526                 }
8527         }
8528
8529         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8530         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8531         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8532         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8533
8534         mutex_unlock(&dev_priv->sb_lock);
8535 }
8536
8537 /* Sequence to disable CLKOUT_DP */
8538 static void lpt_disable_clkout_dp(struct drm_device *dev)
8539 {
8540         struct drm_i915_private *dev_priv = dev->dev_private;
8541         uint32_t reg, tmp;
8542
8543         mutex_lock(&dev_priv->sb_lock);
8544
8545         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8546         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8547         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8548         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8549
8550         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8551         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8552                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8553                         tmp |= SBI_SSCCTL_PATHALT;
8554                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8555                         udelay(32);
8556                 }
8557                 tmp |= SBI_SSCCTL_DISABLE;
8558                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8559         }
8560
8561         mutex_unlock(&dev_priv->sb_lock);
8562 }
8563
8564 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8565
8566 static const uint16_t sscdivintphase[] = {
8567         [BEND_IDX( 50)] = 0x3B23,
8568         [BEND_IDX( 45)] = 0x3B23,
8569         [BEND_IDX( 40)] = 0x3C23,
8570         [BEND_IDX( 35)] = 0x3C23,
8571         [BEND_IDX( 30)] = 0x3D23,
8572         [BEND_IDX( 25)] = 0x3D23,
8573         [BEND_IDX( 20)] = 0x3E23,
8574         [BEND_IDX( 15)] = 0x3E23,
8575         [BEND_IDX( 10)] = 0x3F23,
8576         [BEND_IDX(  5)] = 0x3F23,
8577         [BEND_IDX(  0)] = 0x0025,
8578         [BEND_IDX( -5)] = 0x0025,
8579         [BEND_IDX(-10)] = 0x0125,
8580         [BEND_IDX(-15)] = 0x0125,
8581         [BEND_IDX(-20)] = 0x0225,
8582         [BEND_IDX(-25)] = 0x0225,
8583         [BEND_IDX(-30)] = 0x0325,
8584         [BEND_IDX(-35)] = 0x0325,
8585         [BEND_IDX(-40)] = 0x0425,
8586         [BEND_IDX(-45)] = 0x0425,
8587         [BEND_IDX(-50)] = 0x0525,
8588 };
8589
8590 /*
8591  * Bend CLKOUT_DP
8592  * steps -50 to 50 inclusive, in steps of 5
8593  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8594  * change in clock period = -(steps / 10) * 5.787 ps
8595  */
8596 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8597 {
8598         uint32_t tmp;
8599         int idx = BEND_IDX(steps);
8600
8601         if (WARN_ON(steps % 5 != 0))
8602                 return;
8603
8604         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8605                 return;
8606
8607         mutex_lock(&dev_priv->sb_lock);
8608
8609         if (steps % 10 != 0)
8610                 tmp = 0xAAAAAAAB;
8611         else
8612                 tmp = 0x00000000;
8613         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8614
8615         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8616         tmp &= 0xffff0000;
8617         tmp |= sscdivintphase[idx];
8618         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8619
8620         mutex_unlock(&dev_priv->sb_lock);
8621 }
8622
8623 #undef BEND_IDX
8624
8625 static void lpt_init_pch_refclk(struct drm_device *dev)
8626 {
8627         struct intel_encoder *encoder;
8628         bool has_vga = false;
8629
8630         for_each_intel_encoder(dev, encoder) {
8631                 switch (encoder->type) {
8632                 case INTEL_OUTPUT_ANALOG:
8633                         has_vga = true;
8634                         break;
8635                 default:
8636                         break;
8637                 }
8638         }
8639
8640         if (has_vga) {
8641                 lpt_bend_clkout_dp(to_i915(dev), 0);
8642                 lpt_enable_clkout_dp(dev, true, true);
8643         } else {
8644                 lpt_disable_clkout_dp(dev);
8645         }
8646 }
8647
8648 /*
8649  * Initialize reference clocks when the driver loads
8650  */
8651 void intel_init_pch_refclk(struct drm_device *dev)
8652 {
8653         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8654                 ironlake_init_pch_refclk(dev);
8655         else if (HAS_PCH_LPT(dev))
8656                 lpt_init_pch_refclk(dev);
8657 }
8658
8659 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8660 {
8661         struct drm_device *dev = crtc_state->base.crtc->dev;
8662         struct drm_i915_private *dev_priv = dev->dev_private;
8663         struct drm_atomic_state *state = crtc_state->base.state;
8664         struct drm_connector *connector;
8665         struct drm_connector_state *connector_state;
8666         struct intel_encoder *encoder;
8667         int num_connectors = 0, i;
8668         bool is_lvds = false;
8669
8670         for_each_connector_in_state(state, connector, connector_state, i) {
8671                 if (connector_state->crtc != crtc_state->base.crtc)
8672                         continue;
8673
8674                 encoder = to_intel_encoder(connector_state->best_encoder);
8675
8676                 switch (encoder->type) {
8677                 case INTEL_OUTPUT_LVDS:
8678                         is_lvds = true;
8679                         break;
8680                 default:
8681                         break;
8682                 }
8683                 num_connectors++;
8684         }
8685
8686         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8687                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8688                               dev_priv->vbt.lvds_ssc_freq);
8689                 return dev_priv->vbt.lvds_ssc_freq;
8690         }
8691
8692         return 120000;
8693 }
8694
8695 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8696 {
8697         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8699         int pipe = intel_crtc->pipe;
8700         uint32_t val;
8701
8702         val = 0;
8703
8704         switch (intel_crtc->config->pipe_bpp) {
8705         case 18:
8706                 val |= PIPECONF_6BPC;
8707                 break;
8708         case 24:
8709                 val |= PIPECONF_8BPC;
8710                 break;
8711         case 30:
8712                 val |= PIPECONF_10BPC;
8713                 break;
8714         case 36:
8715                 val |= PIPECONF_12BPC;
8716                 break;
8717         default:
8718                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8719                 BUG();
8720         }
8721
8722         if (intel_crtc->config->dither)
8723                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8724
8725         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8726                 val |= PIPECONF_INTERLACED_ILK;
8727         else
8728                 val |= PIPECONF_PROGRESSIVE;
8729
8730         if (intel_crtc->config->limited_color_range)
8731                 val |= PIPECONF_COLOR_RANGE_SELECT;
8732
8733         I915_WRITE(PIPECONF(pipe), val);
8734         POSTING_READ(PIPECONF(pipe));
8735 }
8736
8737 /*
8738  * Set up the pipe CSC unit.
8739  *
8740  * Currently only full range RGB to limited range RGB conversion
8741  * is supported, but eventually this should handle various
8742  * RGB<->YCbCr scenarios as well.
8743  */
8744 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8745 {
8746         struct drm_device *dev = crtc->dev;
8747         struct drm_i915_private *dev_priv = dev->dev_private;
8748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8749         int pipe = intel_crtc->pipe;
8750         uint16_t coeff = 0x7800; /* 1.0 */
8751
8752         /*
8753          * TODO: Check what kind of values actually come out of the pipe
8754          * with these coeff/postoff values and adjust to get the best
8755          * accuracy. Perhaps we even need to take the bpc value into
8756          * consideration.
8757          */
8758
8759         if (intel_crtc->config->limited_color_range)
8760                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8761
8762         /*
8763          * GY/GU and RY/RU should be the other way around according
8764          * to BSpec, but reality doesn't agree. Just set them up in
8765          * a way that results in the correct picture.
8766          */
8767         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8768         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8769
8770         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8771         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8772
8773         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8774         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8775
8776         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8777         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8778         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8779
8780         if (INTEL_INFO(dev)->gen > 6) {
8781                 uint16_t postoff = 0;
8782
8783                 if (intel_crtc->config->limited_color_range)
8784                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8785
8786                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8787                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8788                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8789
8790                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8791         } else {
8792                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8793
8794                 if (intel_crtc->config->limited_color_range)
8795                         mode |= CSC_BLACK_SCREEN_OFFSET;
8796
8797                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8798         }
8799 }
8800
8801 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8802 {
8803         struct drm_device *dev = crtc->dev;
8804         struct drm_i915_private *dev_priv = dev->dev_private;
8805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8806         enum pipe pipe = intel_crtc->pipe;
8807         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8808         uint32_t val;
8809
8810         val = 0;
8811
8812         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8813                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8814
8815         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8816                 val |= PIPECONF_INTERLACED_ILK;
8817         else
8818                 val |= PIPECONF_PROGRESSIVE;
8819
8820         I915_WRITE(PIPECONF(cpu_transcoder), val);
8821         POSTING_READ(PIPECONF(cpu_transcoder));
8822
8823         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8824         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8825
8826         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8827                 val = 0;
8828
8829                 switch (intel_crtc->config->pipe_bpp) {
8830                 case 18:
8831                         val |= PIPEMISC_DITHER_6_BPC;
8832                         break;
8833                 case 24:
8834                         val |= PIPEMISC_DITHER_8_BPC;
8835                         break;
8836                 case 30:
8837                         val |= PIPEMISC_DITHER_10_BPC;
8838                         break;
8839                 case 36:
8840                         val |= PIPEMISC_DITHER_12_BPC;
8841                         break;
8842                 default:
8843                         /* Case prevented by pipe_config_set_bpp. */
8844                         BUG();
8845                 }
8846
8847                 if (intel_crtc->config->dither)
8848                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8849
8850                 I915_WRITE(PIPEMISC(pipe), val);
8851         }
8852 }
8853
8854 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8855                                     struct intel_crtc_state *crtc_state,
8856                                     intel_clock_t *clock,
8857                                     bool *has_reduced_clock,
8858                                     intel_clock_t *reduced_clock)
8859 {
8860         struct drm_device *dev = crtc->dev;
8861         struct drm_i915_private *dev_priv = dev->dev_private;
8862         int refclk;
8863         const intel_limit_t *limit;
8864         bool ret;
8865
8866         refclk = ironlake_get_refclk(crtc_state);
8867
8868         /*
8869          * Returns a set of divisors for the desired target clock with the given
8870          * refclk, or FALSE.  The returned values represent the clock equation:
8871          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8872          */
8873         limit = intel_limit(crtc_state, refclk);
8874         ret = dev_priv->display.find_dpll(limit, crtc_state,
8875                                           crtc_state->port_clock,
8876                                           refclk, NULL, clock);
8877         if (!ret)
8878                 return false;
8879
8880         return true;
8881 }
8882
8883 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8884 {
8885         /*
8886          * Account for spread spectrum to avoid
8887          * oversubscribing the link. Max center spread
8888          * is 2.5%; use 5% for safety's sake.
8889          */
8890         u32 bps = target_clock * bpp * 21 / 20;
8891         return DIV_ROUND_UP(bps, link_bw * 8);
8892 }
8893
8894 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8895 {
8896         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8897 }
8898
8899 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8900                                       struct intel_crtc_state *crtc_state,
8901                                       u32 *fp,
8902                                       intel_clock_t *reduced_clock, u32 *fp2)
8903 {
8904         struct drm_crtc *crtc = &intel_crtc->base;
8905         struct drm_device *dev = crtc->dev;
8906         struct drm_i915_private *dev_priv = dev->dev_private;
8907         struct drm_atomic_state *state = crtc_state->base.state;
8908         struct drm_connector *connector;
8909         struct drm_connector_state *connector_state;
8910         struct intel_encoder *encoder;
8911         uint32_t dpll;
8912         int factor, num_connectors = 0, i;
8913         bool is_lvds = false, is_sdvo = false;
8914
8915         for_each_connector_in_state(state, connector, connector_state, i) {
8916                 if (connector_state->crtc != crtc_state->base.crtc)
8917                         continue;
8918
8919                 encoder = to_intel_encoder(connector_state->best_encoder);
8920
8921                 switch (encoder->type) {
8922                 case INTEL_OUTPUT_LVDS:
8923                         is_lvds = true;
8924                         break;
8925                 case INTEL_OUTPUT_SDVO:
8926                 case INTEL_OUTPUT_HDMI:
8927                         is_sdvo = true;
8928                         break;
8929                 default:
8930                         break;
8931                 }
8932
8933                 num_connectors++;
8934         }
8935
8936         /* Enable autotuning of the PLL clock (if permissible) */
8937         factor = 21;
8938         if (is_lvds) {
8939                 if ((intel_panel_use_ssc(dev_priv) &&
8940                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8941                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8942                         factor = 25;
8943         } else if (crtc_state->sdvo_tv_clock)
8944                 factor = 20;
8945
8946         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8947                 *fp |= FP_CB_TUNE;
8948
8949         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8950                 *fp2 |= FP_CB_TUNE;
8951
8952         dpll = 0;
8953
8954         if (is_lvds)
8955                 dpll |= DPLLB_MODE_LVDS;
8956         else
8957                 dpll |= DPLLB_MODE_DAC_SERIAL;
8958
8959         dpll |= (crtc_state->pixel_multiplier - 1)
8960                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8961
8962         if (is_sdvo)
8963                 dpll |= DPLL_SDVO_HIGH_SPEED;
8964         if (crtc_state->has_dp_encoder)
8965                 dpll |= DPLL_SDVO_HIGH_SPEED;
8966
8967         /* compute bitmask from p1 value */
8968         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8969         /* also FPA1 */
8970         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8971
8972         switch (crtc_state->dpll.p2) {
8973         case 5:
8974                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8975                 break;
8976         case 7:
8977                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8978                 break;
8979         case 10:
8980                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8981                 break;
8982         case 14:
8983                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8984                 break;
8985         }
8986
8987         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8988                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8989         else
8990                 dpll |= PLL_REF_INPUT_DREFCLK;
8991
8992         return dpll | DPLL_VCO_ENABLE;
8993 }
8994
8995 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8996                                        struct intel_crtc_state *crtc_state)
8997 {
8998         struct drm_device *dev = crtc->base.dev;
8999         intel_clock_t clock, reduced_clock;
9000         u32 dpll = 0, fp = 0, fp2 = 0;
9001         bool ok, has_reduced_clock = false;
9002         bool is_lvds = false;
9003         struct intel_shared_dpll *pll;
9004
9005         memset(&crtc_state->dpll_hw_state, 0,
9006                sizeof(crtc_state->dpll_hw_state));
9007
9008         is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9009
9010         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9011              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9012
9013         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9014                                      &has_reduced_clock, &reduced_clock);
9015         if (!ok && !crtc_state->clock_set) {
9016                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9017                 return -EINVAL;
9018         }
9019         /* Compat-code for transition, will disappear. */
9020         if (!crtc_state->clock_set) {
9021                 crtc_state->dpll.n = clock.n;
9022                 crtc_state->dpll.m1 = clock.m1;
9023                 crtc_state->dpll.m2 = clock.m2;
9024                 crtc_state->dpll.p1 = clock.p1;
9025                 crtc_state->dpll.p2 = clock.p2;
9026         }
9027
9028         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9029         if (crtc_state->has_pch_encoder) {
9030                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9031                 if (has_reduced_clock)
9032                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9033
9034                 dpll = ironlake_compute_dpll(crtc, crtc_state,
9035                                              &fp, &reduced_clock,
9036                                              has_reduced_clock ? &fp2 : NULL);
9037
9038                 crtc_state->dpll_hw_state.dpll = dpll;
9039                 crtc_state->dpll_hw_state.fp0 = fp;
9040                 if (has_reduced_clock)
9041                         crtc_state->dpll_hw_state.fp1 = fp2;
9042                 else
9043                         crtc_state->dpll_hw_state.fp1 = fp;
9044
9045                 pll = intel_get_shared_dpll(crtc, crtc_state);
9046                 if (pll == NULL) {
9047                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9048                                          pipe_name(crtc->pipe));
9049                         return -EINVAL;
9050                 }
9051         }
9052
9053         if (is_lvds && has_reduced_clock)
9054                 crtc->lowfreq_avail = true;
9055         else
9056                 crtc->lowfreq_avail = false;
9057
9058         return 0;
9059 }
9060
9061 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9062                                          struct intel_link_m_n *m_n)
9063 {
9064         struct drm_device *dev = crtc->base.dev;
9065         struct drm_i915_private *dev_priv = dev->dev_private;
9066         enum pipe pipe = crtc->pipe;
9067
9068         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9069         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9070         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9071                 & ~TU_SIZE_MASK;
9072         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9073         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9074                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9075 }
9076
9077 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9078                                          enum transcoder transcoder,
9079                                          struct intel_link_m_n *m_n,
9080                                          struct intel_link_m_n *m2_n2)
9081 {
9082         struct drm_device *dev = crtc->base.dev;
9083         struct drm_i915_private *dev_priv = dev->dev_private;
9084         enum pipe pipe = crtc->pipe;
9085
9086         if (INTEL_INFO(dev)->gen >= 5) {
9087                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9088                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9089                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9090                         & ~TU_SIZE_MASK;
9091                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9092                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9093                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9094                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9095                  * gen < 8) and if DRRS is supported (to make sure the
9096                  * registers are not unnecessarily read).
9097                  */
9098                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9099                         crtc->config->has_drrs) {
9100                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9101                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9102                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9103                                         & ~TU_SIZE_MASK;
9104                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9105                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9106                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9107                 }
9108         } else {
9109                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9110                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9111                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9112                         & ~TU_SIZE_MASK;
9113                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9114                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9115                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9116         }
9117 }
9118
9119 void intel_dp_get_m_n(struct intel_crtc *crtc,
9120                       struct intel_crtc_state *pipe_config)
9121 {
9122         if (pipe_config->has_pch_encoder)
9123                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9124         else
9125                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9126                                              &pipe_config->dp_m_n,
9127                                              &pipe_config->dp_m2_n2);
9128 }
9129
9130 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9131                                         struct intel_crtc_state *pipe_config)
9132 {
9133         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9134                                      &pipe_config->fdi_m_n, NULL);
9135 }
9136
9137 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9138                                     struct intel_crtc_state *pipe_config)
9139 {
9140         struct drm_device *dev = crtc->base.dev;
9141         struct drm_i915_private *dev_priv = dev->dev_private;
9142         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9143         uint32_t ps_ctrl = 0;
9144         int id = -1;
9145         int i;
9146
9147         /* find scaler attached to this pipe */
9148         for (i = 0; i < crtc->num_scalers; i++) {
9149                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9150                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9151                         id = i;
9152                         pipe_config->pch_pfit.enabled = true;
9153                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9154                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9155                         break;
9156                 }
9157         }
9158
9159         scaler_state->scaler_id = id;
9160         if (id >= 0) {
9161                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9162         } else {
9163                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9164         }
9165 }
9166
9167 static void
9168 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9169                                  struct intel_initial_plane_config *plane_config)
9170 {
9171         struct drm_device *dev = crtc->base.dev;
9172         struct drm_i915_private *dev_priv = dev->dev_private;
9173         u32 val, base, offset, stride_mult, tiling;
9174         int pipe = crtc->pipe;
9175         int fourcc, pixel_format;
9176         unsigned int aligned_height;
9177         struct drm_framebuffer *fb;
9178         struct intel_framebuffer *intel_fb;
9179
9180         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9181         if (!intel_fb) {
9182                 DRM_DEBUG_KMS("failed to alloc fb\n");
9183                 return;
9184         }
9185
9186         fb = &intel_fb->base;
9187
9188         val = I915_READ(PLANE_CTL(pipe, 0));
9189         if (!(val & PLANE_CTL_ENABLE))
9190                 goto error;
9191
9192         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9193         fourcc = skl_format_to_fourcc(pixel_format,
9194                                       val & PLANE_CTL_ORDER_RGBX,
9195                                       val & PLANE_CTL_ALPHA_MASK);
9196         fb->pixel_format = fourcc;
9197         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9198
9199         tiling = val & PLANE_CTL_TILED_MASK;
9200         switch (tiling) {
9201         case PLANE_CTL_TILED_LINEAR:
9202                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9203                 break;
9204         case PLANE_CTL_TILED_X:
9205                 plane_config->tiling = I915_TILING_X;
9206                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9207                 break;
9208         case PLANE_CTL_TILED_Y:
9209                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9210                 break;
9211         case PLANE_CTL_TILED_YF:
9212                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9213                 break;
9214         default:
9215                 MISSING_CASE(tiling);
9216                 goto error;
9217         }
9218
9219         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9220         plane_config->base = base;
9221
9222         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9223
9224         val = I915_READ(PLANE_SIZE(pipe, 0));
9225         fb->height = ((val >> 16) & 0xfff) + 1;
9226         fb->width = ((val >> 0) & 0x1fff) + 1;
9227
9228         val = I915_READ(PLANE_STRIDE(pipe, 0));
9229         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9230                                                 fb->pixel_format);
9231         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9232
9233         aligned_height = intel_fb_align_height(dev, fb->height,
9234                                                fb->pixel_format,
9235                                                fb->modifier[0]);
9236
9237         plane_config->size = fb->pitches[0] * aligned_height;
9238
9239         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9240                       pipe_name(pipe), fb->width, fb->height,
9241                       fb->bits_per_pixel, base, fb->pitches[0],
9242                       plane_config->size);
9243
9244         plane_config->fb = intel_fb;
9245         return;
9246
9247 error:
9248         kfree(fb);
9249 }
9250
9251 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9252                                      struct intel_crtc_state *pipe_config)
9253 {
9254         struct drm_device *dev = crtc->base.dev;
9255         struct drm_i915_private *dev_priv = dev->dev_private;
9256         uint32_t tmp;
9257
9258         tmp = I915_READ(PF_CTL(crtc->pipe));
9259
9260         if (tmp & PF_ENABLE) {
9261                 pipe_config->pch_pfit.enabled = true;
9262                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9263                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9264
9265                 /* We currently do not free assignements of panel fitters on
9266                  * ivb/hsw (since we don't use the higher upscaling modes which
9267                  * differentiates them) so just WARN about this case for now. */
9268                 if (IS_GEN7(dev)) {
9269                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9270                                 PF_PIPE_SEL_IVB(crtc->pipe));
9271                 }
9272         }
9273 }
9274
9275 static void
9276 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9277                                   struct intel_initial_plane_config *plane_config)
9278 {
9279         struct drm_device *dev = crtc->base.dev;
9280         struct drm_i915_private *dev_priv = dev->dev_private;
9281         u32 val, base, offset;
9282         int pipe = crtc->pipe;
9283         int fourcc, pixel_format;
9284         unsigned int aligned_height;
9285         struct drm_framebuffer *fb;
9286         struct intel_framebuffer *intel_fb;
9287
9288         val = I915_READ(DSPCNTR(pipe));
9289         if (!(val & DISPLAY_PLANE_ENABLE))
9290                 return;
9291
9292         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9293         if (!intel_fb) {
9294                 DRM_DEBUG_KMS("failed to alloc fb\n");
9295                 return;
9296         }
9297
9298         fb = &intel_fb->base;
9299
9300         if (INTEL_INFO(dev)->gen >= 4) {
9301                 if (val & DISPPLANE_TILED) {
9302                         plane_config->tiling = I915_TILING_X;
9303                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9304                 }
9305         }
9306
9307         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9308         fourcc = i9xx_format_to_fourcc(pixel_format);
9309         fb->pixel_format = fourcc;
9310         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9311
9312         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9313         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9314                 offset = I915_READ(DSPOFFSET(pipe));
9315         } else {
9316                 if (plane_config->tiling)
9317                         offset = I915_READ(DSPTILEOFF(pipe));
9318                 else
9319                         offset = I915_READ(DSPLINOFF(pipe));
9320         }
9321         plane_config->base = base;
9322
9323         val = I915_READ(PIPESRC(pipe));
9324         fb->width = ((val >> 16) & 0xfff) + 1;
9325         fb->height = ((val >> 0) & 0xfff) + 1;
9326
9327         val = I915_READ(DSPSTRIDE(pipe));
9328         fb->pitches[0] = val & 0xffffffc0;
9329
9330         aligned_height = intel_fb_align_height(dev, fb->height,
9331                                                fb->pixel_format,
9332                                                fb->modifier[0]);
9333
9334         plane_config->size = fb->pitches[0] * aligned_height;
9335
9336         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9337                       pipe_name(pipe), fb->width, fb->height,
9338                       fb->bits_per_pixel, base, fb->pitches[0],
9339                       plane_config->size);
9340
9341         plane_config->fb = intel_fb;
9342 }
9343
9344 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9345                                      struct intel_crtc_state *pipe_config)
9346 {
9347         struct drm_device *dev = crtc->base.dev;
9348         struct drm_i915_private *dev_priv = dev->dev_private;
9349         uint32_t tmp;
9350
9351         if (!intel_display_power_is_enabled(dev_priv,
9352                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9353                 return false;
9354
9355         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9356         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9357
9358         tmp = I915_READ(PIPECONF(crtc->pipe));
9359         if (!(tmp & PIPECONF_ENABLE))
9360                 return false;
9361
9362         switch (tmp & PIPECONF_BPC_MASK) {
9363         case PIPECONF_6BPC:
9364                 pipe_config->pipe_bpp = 18;
9365                 break;
9366         case PIPECONF_8BPC:
9367                 pipe_config->pipe_bpp = 24;
9368                 break;
9369         case PIPECONF_10BPC:
9370                 pipe_config->pipe_bpp = 30;
9371                 break;
9372         case PIPECONF_12BPC:
9373                 pipe_config->pipe_bpp = 36;
9374                 break;
9375         default:
9376                 break;
9377         }
9378
9379         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9380                 pipe_config->limited_color_range = true;
9381
9382         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9383                 struct intel_shared_dpll *pll;
9384
9385                 pipe_config->has_pch_encoder = true;
9386
9387                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9388                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9389                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9390
9391                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9392
9393                 if (HAS_PCH_IBX(dev_priv->dev)) {
9394                         pipe_config->shared_dpll =
9395                                 (enum intel_dpll_id) crtc->pipe;
9396                 } else {
9397                         tmp = I915_READ(PCH_DPLL_SEL);
9398                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9399                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9400                         else
9401                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9402                 }
9403
9404                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9405
9406                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9407                                            &pipe_config->dpll_hw_state));
9408
9409                 tmp = pipe_config->dpll_hw_state.dpll;
9410                 pipe_config->pixel_multiplier =
9411                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9412                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9413
9414                 ironlake_pch_clock_get(crtc, pipe_config);
9415         } else {
9416                 pipe_config->pixel_multiplier = 1;
9417         }
9418
9419         intel_get_pipe_timings(crtc, pipe_config);
9420
9421         ironlake_get_pfit_config(crtc, pipe_config);
9422
9423         return true;
9424 }
9425
9426 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9427 {
9428         struct drm_device *dev = dev_priv->dev;
9429         struct intel_crtc *crtc;
9430
9431         for_each_intel_crtc(dev, crtc)
9432                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9433                      pipe_name(crtc->pipe));
9434
9435         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9436         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9437         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9438         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9439         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9440         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9441              "CPU PWM1 enabled\n");
9442         if (IS_HASWELL(dev))
9443                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9444                      "CPU PWM2 enabled\n");
9445         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9446              "PCH PWM1 enabled\n");
9447         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9448              "Utility pin enabled\n");
9449         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9450
9451         /*
9452          * In theory we can still leave IRQs enabled, as long as only the HPD
9453          * interrupts remain enabled. We used to check for that, but since it's
9454          * gen-specific and since we only disable LCPLL after we fully disable
9455          * the interrupts, the check below should be enough.
9456          */
9457         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9458 }
9459
9460 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9461 {
9462         struct drm_device *dev = dev_priv->dev;
9463
9464         if (IS_HASWELL(dev))
9465                 return I915_READ(D_COMP_HSW);
9466         else
9467                 return I915_READ(D_COMP_BDW);
9468 }
9469
9470 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9471 {
9472         struct drm_device *dev = dev_priv->dev;
9473
9474         if (IS_HASWELL(dev)) {
9475                 mutex_lock(&dev_priv->rps.hw_lock);
9476                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9477                                             val))
9478                         DRM_ERROR("Failed to write to D_COMP\n");
9479                 mutex_unlock(&dev_priv->rps.hw_lock);
9480         } else {
9481                 I915_WRITE(D_COMP_BDW, val);
9482                 POSTING_READ(D_COMP_BDW);
9483         }
9484 }
9485
9486 /*
9487  * This function implements pieces of two sequences from BSpec:
9488  * - Sequence for display software to disable LCPLL
9489  * - Sequence for display software to allow package C8+
9490  * The steps implemented here are just the steps that actually touch the LCPLL
9491  * register. Callers should take care of disabling all the display engine
9492  * functions, doing the mode unset, fixing interrupts, etc.
9493  */
9494 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9495                               bool switch_to_fclk, bool allow_power_down)
9496 {
9497         uint32_t val;
9498
9499         assert_can_disable_lcpll(dev_priv);
9500
9501         val = I915_READ(LCPLL_CTL);
9502
9503         if (switch_to_fclk) {
9504                 val |= LCPLL_CD_SOURCE_FCLK;
9505                 I915_WRITE(LCPLL_CTL, val);
9506
9507                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9508                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9509                         DRM_ERROR("Switching to FCLK failed\n");
9510
9511                 val = I915_READ(LCPLL_CTL);
9512         }
9513
9514         val |= LCPLL_PLL_DISABLE;
9515         I915_WRITE(LCPLL_CTL, val);
9516         POSTING_READ(LCPLL_CTL);
9517
9518         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9519                 DRM_ERROR("LCPLL still locked\n");
9520
9521         val = hsw_read_dcomp(dev_priv);
9522         val |= D_COMP_COMP_DISABLE;
9523         hsw_write_dcomp(dev_priv, val);
9524         ndelay(100);
9525
9526         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9527                      1))
9528                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9529
9530         if (allow_power_down) {
9531                 val = I915_READ(LCPLL_CTL);
9532                 val |= LCPLL_POWER_DOWN_ALLOW;
9533                 I915_WRITE(LCPLL_CTL, val);
9534                 POSTING_READ(LCPLL_CTL);
9535         }
9536 }
9537
9538 /*
9539  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9540  * source.
9541  */
9542 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9543 {
9544         uint32_t val;
9545
9546         val = I915_READ(LCPLL_CTL);
9547
9548         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9549                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9550                 return;
9551
9552         /*
9553          * Make sure we're not on PC8 state before disabling PC8, otherwise
9554          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9555          */
9556         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9557
9558         if (val & LCPLL_POWER_DOWN_ALLOW) {
9559                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9560                 I915_WRITE(LCPLL_CTL, val);
9561                 POSTING_READ(LCPLL_CTL);
9562         }
9563
9564         val = hsw_read_dcomp(dev_priv);
9565         val |= D_COMP_COMP_FORCE;
9566         val &= ~D_COMP_COMP_DISABLE;
9567         hsw_write_dcomp(dev_priv, val);
9568
9569         val = I915_READ(LCPLL_CTL);
9570         val &= ~LCPLL_PLL_DISABLE;
9571         I915_WRITE(LCPLL_CTL, val);
9572
9573         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9574                 DRM_ERROR("LCPLL not locked yet\n");
9575
9576         if (val & LCPLL_CD_SOURCE_FCLK) {
9577                 val = I915_READ(LCPLL_CTL);
9578                 val &= ~LCPLL_CD_SOURCE_FCLK;
9579                 I915_WRITE(LCPLL_CTL, val);
9580
9581                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9582                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9583                         DRM_ERROR("Switching back to LCPLL failed\n");
9584         }
9585
9586         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9587         intel_update_cdclk(dev_priv->dev);
9588 }
9589
9590 /*
9591  * Package states C8 and deeper are really deep PC states that can only be
9592  * reached when all the devices on the system allow it, so even if the graphics
9593  * device allows PC8+, it doesn't mean the system will actually get to these
9594  * states. Our driver only allows PC8+ when going into runtime PM.
9595  *
9596  * The requirements for PC8+ are that all the outputs are disabled, the power
9597  * well is disabled and most interrupts are disabled, and these are also
9598  * requirements for runtime PM. When these conditions are met, we manually do
9599  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9600  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9601  * hang the machine.
9602  *
9603  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9604  * the state of some registers, so when we come back from PC8+ we need to
9605  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9606  * need to take care of the registers kept by RC6. Notice that this happens even
9607  * if we don't put the device in PCI D3 state (which is what currently happens
9608  * because of the runtime PM support).
9609  *
9610  * For more, read "Display Sequences for Package C8" on the hardware
9611  * documentation.
9612  */
9613 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9614 {
9615         struct drm_device *dev = dev_priv->dev;
9616         uint32_t val;
9617
9618         DRM_DEBUG_KMS("Enabling package C8+\n");
9619
9620         if (HAS_PCH_LPT_LP(dev)) {
9621                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9622                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9623                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9624         }
9625
9626         lpt_disable_clkout_dp(dev);
9627         hsw_disable_lcpll(dev_priv, true, true);
9628 }
9629
9630 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9631 {
9632         struct drm_device *dev = dev_priv->dev;
9633         uint32_t val;
9634
9635         DRM_DEBUG_KMS("Disabling package C8+\n");
9636
9637         hsw_restore_lcpll(dev_priv);
9638         lpt_init_pch_refclk(dev);
9639
9640         if (HAS_PCH_LPT_LP(dev)) {
9641                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9642                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9643                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9644         }
9645
9646         intel_prepare_ddi(dev);
9647 }
9648
9649 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9650 {
9651         struct drm_device *dev = old_state->dev;
9652         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9653
9654         broxton_set_cdclk(dev, req_cdclk);
9655 }
9656
9657 /* compute the max rate for new configuration */
9658 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9659 {
9660         struct intel_crtc *intel_crtc;
9661         struct intel_crtc_state *crtc_state;
9662         int max_pixel_rate = 0;
9663
9664         for_each_intel_crtc(state->dev, intel_crtc) {
9665                 int pixel_rate;
9666
9667                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9668                 if (IS_ERR(crtc_state))
9669                         return PTR_ERR(crtc_state);
9670
9671                 if (!crtc_state->base.enable)
9672                         continue;
9673
9674                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9675
9676                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9677                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9678                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9679
9680                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9681         }
9682
9683         return max_pixel_rate;
9684 }
9685
9686 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9687 {
9688         struct drm_i915_private *dev_priv = dev->dev_private;
9689         uint32_t val, data;
9690         int ret;
9691
9692         if (WARN((I915_READ(LCPLL_CTL) &
9693                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9694                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9695                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9696                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9697                  "trying to change cdclk frequency with cdclk not enabled\n"))
9698                 return;
9699
9700         mutex_lock(&dev_priv->rps.hw_lock);
9701         ret = sandybridge_pcode_write(dev_priv,
9702                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9703         mutex_unlock(&dev_priv->rps.hw_lock);
9704         if (ret) {
9705                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9706                 return;
9707         }
9708
9709         val = I915_READ(LCPLL_CTL);
9710         val |= LCPLL_CD_SOURCE_FCLK;
9711         I915_WRITE(LCPLL_CTL, val);
9712
9713         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9714                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9715                 DRM_ERROR("Switching to FCLK failed\n");
9716
9717         val = I915_READ(LCPLL_CTL);
9718         val &= ~LCPLL_CLK_FREQ_MASK;
9719
9720         switch (cdclk) {
9721         case 450000:
9722                 val |= LCPLL_CLK_FREQ_450;
9723                 data = 0;
9724                 break;
9725         case 540000:
9726                 val |= LCPLL_CLK_FREQ_54O_BDW;
9727                 data = 1;
9728                 break;
9729         case 337500:
9730                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9731                 data = 2;
9732                 break;
9733         case 675000:
9734                 val |= LCPLL_CLK_FREQ_675_BDW;
9735                 data = 3;
9736                 break;
9737         default:
9738                 WARN(1, "invalid cdclk frequency\n");
9739                 return;
9740         }
9741
9742         I915_WRITE(LCPLL_CTL, val);
9743
9744         val = I915_READ(LCPLL_CTL);
9745         val &= ~LCPLL_CD_SOURCE_FCLK;
9746         I915_WRITE(LCPLL_CTL, val);
9747
9748         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9749                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9750                 DRM_ERROR("Switching back to LCPLL failed\n");
9751
9752         mutex_lock(&dev_priv->rps.hw_lock);
9753         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9754         mutex_unlock(&dev_priv->rps.hw_lock);
9755
9756         intel_update_cdclk(dev);
9757
9758         WARN(cdclk != dev_priv->cdclk_freq,
9759              "cdclk requested %d kHz but got %d kHz\n",
9760              cdclk, dev_priv->cdclk_freq);
9761 }
9762
9763 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9764 {
9765         struct drm_i915_private *dev_priv = to_i915(state->dev);
9766         int max_pixclk = ilk_max_pixel_rate(state);
9767         int cdclk;
9768
9769         /*
9770          * FIXME should also account for plane ratio
9771          * once 64bpp pixel formats are supported.
9772          */
9773         if (max_pixclk > 540000)
9774                 cdclk = 675000;
9775         else if (max_pixclk > 450000)
9776                 cdclk = 540000;
9777         else if (max_pixclk > 337500)
9778                 cdclk = 450000;
9779         else
9780                 cdclk = 337500;
9781
9782         if (cdclk > dev_priv->max_cdclk_freq) {
9783                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9784                               cdclk, dev_priv->max_cdclk_freq);
9785                 return -EINVAL;
9786         }
9787
9788         to_intel_atomic_state(state)->cdclk = cdclk;
9789
9790         return 0;
9791 }
9792
9793 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9794 {
9795         struct drm_device *dev = old_state->dev;
9796         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9797
9798         broadwell_set_cdclk(dev, req_cdclk);
9799 }
9800
9801 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9802                                       struct intel_crtc_state *crtc_state)
9803 {
9804         if (!intel_ddi_pll_select(crtc, crtc_state))
9805                 return -EINVAL;
9806
9807         crtc->lowfreq_avail = false;
9808
9809         return 0;
9810 }
9811
9812 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9813                                 enum port port,
9814                                 struct intel_crtc_state *pipe_config)
9815 {
9816         switch (port) {
9817         case PORT_A:
9818                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9819                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9820                 break;
9821         case PORT_B:
9822                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9823                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9824                 break;
9825         case PORT_C:
9826                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9827                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9828                 break;
9829         default:
9830                 DRM_ERROR("Incorrect port type\n");
9831         }
9832 }
9833
9834 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9835                                 enum port port,
9836                                 struct intel_crtc_state *pipe_config)
9837 {
9838         u32 temp, dpll_ctl1;
9839
9840         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9841         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9842
9843         switch (pipe_config->ddi_pll_sel) {
9844         case SKL_DPLL0:
9845                 /*
9846                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9847                  * of the shared DPLL framework and thus needs to be read out
9848                  * separately
9849                  */
9850                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9851                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9852                 break;
9853         case SKL_DPLL1:
9854                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9855                 break;
9856         case SKL_DPLL2:
9857                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9858                 break;
9859         case SKL_DPLL3:
9860                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9861                 break;
9862         }
9863 }
9864
9865 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9866                                 enum port port,
9867                                 struct intel_crtc_state *pipe_config)
9868 {
9869         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9870
9871         switch (pipe_config->ddi_pll_sel) {
9872         case PORT_CLK_SEL_WRPLL1:
9873                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9874                 break;
9875         case PORT_CLK_SEL_WRPLL2:
9876                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9877                 break;
9878         case PORT_CLK_SEL_SPLL:
9879                 pipe_config->shared_dpll = DPLL_ID_SPLL;
9880                 break;
9881         }
9882 }
9883
9884 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9885                                        struct intel_crtc_state *pipe_config)
9886 {
9887         struct drm_device *dev = crtc->base.dev;
9888         struct drm_i915_private *dev_priv = dev->dev_private;
9889         struct intel_shared_dpll *pll;
9890         enum port port;
9891         uint32_t tmp;
9892
9893         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9894
9895         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9896
9897         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9898                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9899         else if (IS_BROXTON(dev))
9900                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9901         else
9902                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9903
9904         if (pipe_config->shared_dpll >= 0) {
9905                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9906
9907                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9908                                            &pipe_config->dpll_hw_state));
9909         }
9910
9911         /*
9912          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9913          * DDI E. So just check whether this pipe is wired to DDI E and whether
9914          * the PCH transcoder is on.
9915          */
9916         if (INTEL_INFO(dev)->gen < 9 &&
9917             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9918                 pipe_config->has_pch_encoder = true;
9919
9920                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9921                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9922                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9923
9924                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9925         }
9926 }
9927
9928 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9929                                     struct intel_crtc_state *pipe_config)
9930 {
9931         struct drm_device *dev = crtc->base.dev;
9932         struct drm_i915_private *dev_priv = dev->dev_private;
9933         enum intel_display_power_domain pfit_domain;
9934         uint32_t tmp;
9935
9936         if (!intel_display_power_is_enabled(dev_priv,
9937                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9938                 return false;
9939
9940         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9941         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9942
9943         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9944         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9945                 enum pipe trans_edp_pipe;
9946                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9947                 default:
9948                         WARN(1, "unknown pipe linked to edp transcoder\n");
9949                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9950                 case TRANS_DDI_EDP_INPUT_A_ON:
9951                         trans_edp_pipe = PIPE_A;
9952                         break;
9953                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9954                         trans_edp_pipe = PIPE_B;
9955                         break;
9956                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9957                         trans_edp_pipe = PIPE_C;
9958                         break;
9959                 }
9960
9961                 if (trans_edp_pipe == crtc->pipe)
9962                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9963         }
9964
9965         if (!intel_display_power_is_enabled(dev_priv,
9966                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9967                 return false;
9968
9969         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9970         if (!(tmp & PIPECONF_ENABLE))
9971                 return false;
9972
9973         haswell_get_ddi_port_state(crtc, pipe_config);
9974
9975         intel_get_pipe_timings(crtc, pipe_config);
9976
9977         if (INTEL_INFO(dev)->gen >= 9) {
9978                 skl_init_scalers(dev, crtc, pipe_config);
9979         }
9980
9981         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9982
9983         if (INTEL_INFO(dev)->gen >= 9) {
9984                 pipe_config->scaler_state.scaler_id = -1;
9985                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9986         }
9987
9988         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9989                 if (INTEL_INFO(dev)->gen >= 9)
9990                         skylake_get_pfit_config(crtc, pipe_config);
9991                 else
9992                         ironlake_get_pfit_config(crtc, pipe_config);
9993         }
9994
9995         if (IS_HASWELL(dev))
9996                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9997                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9998
9999         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10000                 pipe_config->pixel_multiplier =
10001                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10002         } else {
10003                 pipe_config->pixel_multiplier = 1;
10004         }
10005
10006         return true;
10007 }
10008
10009 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
10010 {
10011         struct drm_device *dev = crtc->dev;
10012         struct drm_i915_private *dev_priv = dev->dev_private;
10013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10014         uint32_t cntl = 0, size = 0;
10015
10016         if (base) {
10017                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10018                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
10019                 unsigned int stride = roundup_pow_of_two(width) * 4;
10020
10021                 switch (stride) {
10022                 default:
10023                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10024                                   width, stride);
10025                         stride = 256;
10026                         /* fallthrough */
10027                 case 256:
10028                 case 512:
10029                 case 1024:
10030                 case 2048:
10031                         break;
10032                 }
10033
10034                 cntl |= CURSOR_ENABLE |
10035                         CURSOR_GAMMA_ENABLE |
10036                         CURSOR_FORMAT_ARGB |
10037                         CURSOR_STRIDE(stride);
10038
10039                 size = (height << 12) | width;
10040         }
10041
10042         if (intel_crtc->cursor_cntl != 0 &&
10043             (intel_crtc->cursor_base != base ||
10044              intel_crtc->cursor_size != size ||
10045              intel_crtc->cursor_cntl != cntl)) {
10046                 /* On these chipsets we can only modify the base/size/stride
10047                  * whilst the cursor is disabled.
10048                  */
10049                 I915_WRITE(CURCNTR(PIPE_A), 0);
10050                 POSTING_READ(CURCNTR(PIPE_A));
10051                 intel_crtc->cursor_cntl = 0;
10052         }
10053
10054         if (intel_crtc->cursor_base != base) {
10055                 I915_WRITE(CURBASE(PIPE_A), base);
10056                 intel_crtc->cursor_base = base;
10057         }
10058
10059         if (intel_crtc->cursor_size != size) {
10060                 I915_WRITE(CURSIZE, size);
10061                 intel_crtc->cursor_size = size;
10062         }
10063
10064         if (intel_crtc->cursor_cntl != cntl) {
10065                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10066                 POSTING_READ(CURCNTR(PIPE_A));
10067                 intel_crtc->cursor_cntl = cntl;
10068         }
10069 }
10070
10071 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10072 {
10073         struct drm_device *dev = crtc->dev;
10074         struct drm_i915_private *dev_priv = dev->dev_private;
10075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10076         int pipe = intel_crtc->pipe;
10077         uint32_t cntl;
10078
10079         cntl = 0;
10080         if (base) {
10081                 cntl = MCURSOR_GAMMA_ENABLE;
10082                 switch (intel_crtc->base.cursor->state->crtc_w) {
10083                         case 64:
10084                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10085                                 break;
10086                         case 128:
10087                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10088                                 break;
10089                         case 256:
10090                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10091                                 break;
10092                         default:
10093                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10094                                 return;
10095                 }
10096                 cntl |= pipe << 28; /* Connect to correct pipe */
10097
10098                 if (HAS_DDI(dev))
10099                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10100         }
10101
10102         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10103                 cntl |= CURSOR_ROTATE_180;
10104
10105         if (intel_crtc->cursor_cntl != cntl) {
10106                 I915_WRITE(CURCNTR(pipe), cntl);
10107                 POSTING_READ(CURCNTR(pipe));
10108                 intel_crtc->cursor_cntl = cntl;
10109         }
10110
10111         /* and commit changes on next vblank */
10112         I915_WRITE(CURBASE(pipe), base);
10113         POSTING_READ(CURBASE(pipe));
10114
10115         intel_crtc->cursor_base = base;
10116 }
10117
10118 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10119 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10120                                      bool on)
10121 {
10122         struct drm_device *dev = crtc->dev;
10123         struct drm_i915_private *dev_priv = dev->dev_private;
10124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10125         int pipe = intel_crtc->pipe;
10126         struct drm_plane_state *cursor_state = crtc->cursor->state;
10127         int x = cursor_state->crtc_x;
10128         int y = cursor_state->crtc_y;
10129         u32 base = 0, pos = 0;
10130
10131         if (on)
10132                 base = intel_crtc->cursor_addr;
10133
10134         if (x >= intel_crtc->config->pipe_src_w)
10135                 base = 0;
10136
10137         if (y >= intel_crtc->config->pipe_src_h)
10138                 base = 0;
10139
10140         if (x < 0) {
10141                 if (x + cursor_state->crtc_w <= 0)
10142                         base = 0;
10143
10144                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10145                 x = -x;
10146         }
10147         pos |= x << CURSOR_X_SHIFT;
10148
10149         if (y < 0) {
10150                 if (y + cursor_state->crtc_h <= 0)
10151                         base = 0;
10152
10153                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10154                 y = -y;
10155         }
10156         pos |= y << CURSOR_Y_SHIFT;
10157
10158         if (base == 0 && intel_crtc->cursor_base == 0)
10159                 return;
10160
10161         I915_WRITE(CURPOS(pipe), pos);
10162
10163         /* ILK+ do this automagically */
10164         if (HAS_GMCH_DISPLAY(dev) &&
10165             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10166                 base += (cursor_state->crtc_h *
10167                          cursor_state->crtc_w - 1) * 4;
10168         }
10169
10170         if (IS_845G(dev) || IS_I865G(dev))
10171                 i845_update_cursor(crtc, base);
10172         else
10173                 i9xx_update_cursor(crtc, base);
10174 }
10175
10176 static bool cursor_size_ok(struct drm_device *dev,
10177                            uint32_t width, uint32_t height)
10178 {
10179         if (width == 0 || height == 0)
10180                 return false;
10181
10182         /*
10183          * 845g/865g are special in that they are only limited by
10184          * the width of their cursors, the height is arbitrary up to
10185          * the precision of the register. Everything else requires
10186          * square cursors, limited to a few power-of-two sizes.
10187          */
10188         if (IS_845G(dev) || IS_I865G(dev)) {
10189                 if ((width & 63) != 0)
10190                         return false;
10191
10192                 if (width > (IS_845G(dev) ? 64 : 512))
10193                         return false;
10194
10195                 if (height > 1023)
10196                         return false;
10197         } else {
10198                 switch (width | height) {
10199                 case 256:
10200                 case 128:
10201                         if (IS_GEN2(dev))
10202                                 return false;
10203                 case 64:
10204                         break;
10205                 default:
10206                         return false;
10207                 }
10208         }
10209
10210         return true;
10211 }
10212
10213 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10214                                  u16 *blue, uint32_t start, uint32_t size)
10215 {
10216         int end = (start + size > 256) ? 256 : start + size, i;
10217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10218
10219         for (i = start; i < end; i++) {
10220                 intel_crtc->lut_r[i] = red[i] >> 8;
10221                 intel_crtc->lut_g[i] = green[i] >> 8;
10222                 intel_crtc->lut_b[i] = blue[i] >> 8;
10223         }
10224
10225         intel_crtc_load_lut(crtc);
10226 }
10227
10228 /* VESA 640x480x72Hz mode to set on the pipe */
10229 static struct drm_display_mode load_detect_mode = {
10230         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10231                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10232 };
10233
10234 struct drm_framebuffer *
10235 __intel_framebuffer_create(struct drm_device *dev,
10236                            struct drm_mode_fb_cmd2 *mode_cmd,
10237                            struct drm_i915_gem_object *obj)
10238 {
10239         struct intel_framebuffer *intel_fb;
10240         int ret;
10241
10242         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10243         if (!intel_fb)
10244                 return ERR_PTR(-ENOMEM);
10245
10246         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10247         if (ret)
10248                 goto err;
10249
10250         return &intel_fb->base;
10251
10252 err:
10253         kfree(intel_fb);
10254         return ERR_PTR(ret);
10255 }
10256
10257 static struct drm_framebuffer *
10258 intel_framebuffer_create(struct drm_device *dev,
10259                          struct drm_mode_fb_cmd2 *mode_cmd,
10260                          struct drm_i915_gem_object *obj)
10261 {
10262         struct drm_framebuffer *fb;
10263         int ret;
10264
10265         ret = i915_mutex_lock_interruptible(dev);
10266         if (ret)
10267                 return ERR_PTR(ret);
10268         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10269         mutex_unlock(&dev->struct_mutex);
10270
10271         return fb;
10272 }
10273
10274 static u32
10275 intel_framebuffer_pitch_for_width(int width, int bpp)
10276 {
10277         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10278         return ALIGN(pitch, 64);
10279 }
10280
10281 static u32
10282 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10283 {
10284         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10285         return PAGE_ALIGN(pitch * mode->vdisplay);
10286 }
10287
10288 static struct drm_framebuffer *
10289 intel_framebuffer_create_for_mode(struct drm_device *dev,
10290                                   struct drm_display_mode *mode,
10291                                   int depth, int bpp)
10292 {
10293         struct drm_framebuffer *fb;
10294         struct drm_i915_gem_object *obj;
10295         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10296
10297         obj = i915_gem_alloc_object(dev,
10298                                     intel_framebuffer_size_for_mode(mode, bpp));
10299         if (obj == NULL)
10300                 return ERR_PTR(-ENOMEM);
10301
10302         mode_cmd.width = mode->hdisplay;
10303         mode_cmd.height = mode->vdisplay;
10304         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10305                                                                 bpp);
10306         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10307
10308         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10309         if (IS_ERR(fb))
10310                 drm_gem_object_unreference_unlocked(&obj->base);
10311
10312         return fb;
10313 }
10314
10315 static struct drm_framebuffer *
10316 mode_fits_in_fbdev(struct drm_device *dev,
10317                    struct drm_display_mode *mode)
10318 {
10319 #ifdef CONFIG_DRM_FBDEV_EMULATION
10320         struct drm_i915_private *dev_priv = dev->dev_private;
10321         struct drm_i915_gem_object *obj;
10322         struct drm_framebuffer *fb;
10323
10324         if (!dev_priv->fbdev)
10325                 return NULL;
10326
10327         if (!dev_priv->fbdev->fb)
10328                 return NULL;
10329
10330         obj = dev_priv->fbdev->fb->obj;
10331         BUG_ON(!obj);
10332
10333         fb = &dev_priv->fbdev->fb->base;
10334         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10335                                                                fb->bits_per_pixel))
10336                 return NULL;
10337
10338         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10339                 return NULL;
10340
10341         return fb;
10342 #else
10343         return NULL;
10344 #endif
10345 }
10346
10347 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10348                                            struct drm_crtc *crtc,
10349                                            struct drm_display_mode *mode,
10350                                            struct drm_framebuffer *fb,
10351                                            int x, int y)
10352 {
10353         struct drm_plane_state *plane_state;
10354         int hdisplay, vdisplay;
10355         int ret;
10356
10357         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10358         if (IS_ERR(plane_state))
10359                 return PTR_ERR(plane_state);
10360
10361         if (mode)
10362                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10363         else
10364                 hdisplay = vdisplay = 0;
10365
10366         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10367         if (ret)
10368                 return ret;
10369         drm_atomic_set_fb_for_plane(plane_state, fb);
10370         plane_state->crtc_x = 0;
10371         plane_state->crtc_y = 0;
10372         plane_state->crtc_w = hdisplay;
10373         plane_state->crtc_h = vdisplay;
10374         plane_state->src_x = x << 16;
10375         plane_state->src_y = y << 16;
10376         plane_state->src_w = hdisplay << 16;
10377         plane_state->src_h = vdisplay << 16;
10378
10379         return 0;
10380 }
10381
10382 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10383                                 struct drm_display_mode *mode,
10384                                 struct intel_load_detect_pipe *old,
10385                                 struct drm_modeset_acquire_ctx *ctx)
10386 {
10387         struct intel_crtc *intel_crtc;
10388         struct intel_encoder *intel_encoder =
10389                 intel_attached_encoder(connector);
10390         struct drm_crtc *possible_crtc;
10391         struct drm_encoder *encoder = &intel_encoder->base;
10392         struct drm_crtc *crtc = NULL;
10393         struct drm_device *dev = encoder->dev;
10394         struct drm_framebuffer *fb;
10395         struct drm_mode_config *config = &dev->mode_config;
10396         struct drm_atomic_state *state = NULL;
10397         struct drm_connector_state *connector_state;
10398         struct intel_crtc_state *crtc_state;
10399         int ret, i = -1;
10400
10401         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10402                       connector->base.id, connector->name,
10403                       encoder->base.id, encoder->name);
10404
10405 retry:
10406         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10407         if (ret)
10408                 goto fail;
10409
10410         /*
10411          * Algorithm gets a little messy:
10412          *
10413          *   - if the connector already has an assigned crtc, use it (but make
10414          *     sure it's on first)
10415          *
10416          *   - try to find the first unused crtc that can drive this connector,
10417          *     and use that if we find one
10418          */
10419
10420         /* See if we already have a CRTC for this connector */
10421         if (encoder->crtc) {
10422                 crtc = encoder->crtc;
10423
10424                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10425                 if (ret)
10426                         goto fail;
10427                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10428                 if (ret)
10429                         goto fail;
10430
10431                 old->dpms_mode = connector->dpms;
10432                 old->load_detect_temp = false;
10433
10434                 /* Make sure the crtc and connector are running */
10435                 if (connector->dpms != DRM_MODE_DPMS_ON)
10436                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10437
10438                 return true;
10439         }
10440
10441         /* Find an unused one (if possible) */
10442         for_each_crtc(dev, possible_crtc) {
10443                 i++;
10444                 if (!(encoder->possible_crtcs & (1 << i)))
10445                         continue;
10446                 if (possible_crtc->state->enable)
10447                         continue;
10448
10449                 crtc = possible_crtc;
10450                 break;
10451         }
10452
10453         /*
10454          * If we didn't find an unused CRTC, don't use any.
10455          */
10456         if (!crtc) {
10457                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10458                 goto fail;
10459         }
10460
10461         ret = drm_modeset_lock(&crtc->mutex, ctx);
10462         if (ret)
10463                 goto fail;
10464         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10465         if (ret)
10466                 goto fail;
10467
10468         intel_crtc = to_intel_crtc(crtc);
10469         old->dpms_mode = connector->dpms;
10470         old->load_detect_temp = true;
10471         old->release_fb = NULL;
10472
10473         state = drm_atomic_state_alloc(dev);
10474         if (!state)
10475                 return false;
10476
10477         state->acquire_ctx = ctx;
10478
10479         connector_state = drm_atomic_get_connector_state(state, connector);
10480         if (IS_ERR(connector_state)) {
10481                 ret = PTR_ERR(connector_state);
10482                 goto fail;
10483         }
10484
10485         connector_state->crtc = crtc;
10486         connector_state->best_encoder = &intel_encoder->base;
10487
10488         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10489         if (IS_ERR(crtc_state)) {
10490                 ret = PTR_ERR(crtc_state);
10491                 goto fail;
10492         }
10493
10494         crtc_state->base.active = crtc_state->base.enable = true;
10495
10496         if (!mode)
10497                 mode = &load_detect_mode;
10498
10499         /* We need a framebuffer large enough to accommodate all accesses
10500          * that the plane may generate whilst we perform load detection.
10501          * We can not rely on the fbcon either being present (we get called
10502          * during its initialisation to detect all boot displays, or it may
10503          * not even exist) or that it is large enough to satisfy the
10504          * requested mode.
10505          */
10506         fb = mode_fits_in_fbdev(dev, mode);
10507         if (fb == NULL) {
10508                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10509                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10510                 old->release_fb = fb;
10511         } else
10512                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10513         if (IS_ERR(fb)) {
10514                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10515                 goto fail;
10516         }
10517
10518         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10519         if (ret)
10520                 goto fail;
10521
10522         drm_mode_copy(&crtc_state->base.mode, mode);
10523
10524         if (drm_atomic_commit(state)) {
10525                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10526                 if (old->release_fb)
10527                         old->release_fb->funcs->destroy(old->release_fb);
10528                 goto fail;
10529         }
10530         crtc->primary->crtc = crtc;
10531
10532         /* let the connector get through one full cycle before testing */
10533         intel_wait_for_vblank(dev, intel_crtc->pipe);
10534         return true;
10535
10536 fail:
10537         drm_atomic_state_free(state);
10538         state = NULL;
10539
10540         if (ret == -EDEADLK) {
10541                 drm_modeset_backoff(ctx);
10542                 goto retry;
10543         }
10544
10545         return false;
10546 }
10547
10548 void intel_release_load_detect_pipe(struct drm_connector *connector,
10549                                     struct intel_load_detect_pipe *old,
10550                                     struct drm_modeset_acquire_ctx *ctx)
10551 {
10552         struct drm_device *dev = connector->dev;
10553         struct intel_encoder *intel_encoder =
10554                 intel_attached_encoder(connector);
10555         struct drm_encoder *encoder = &intel_encoder->base;
10556         struct drm_crtc *crtc = encoder->crtc;
10557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10558         struct drm_atomic_state *state;
10559         struct drm_connector_state *connector_state;
10560         struct intel_crtc_state *crtc_state;
10561         int ret;
10562
10563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10564                       connector->base.id, connector->name,
10565                       encoder->base.id, encoder->name);
10566
10567         if (old->load_detect_temp) {
10568                 state = drm_atomic_state_alloc(dev);
10569                 if (!state)
10570                         goto fail;
10571
10572                 state->acquire_ctx = ctx;
10573
10574                 connector_state = drm_atomic_get_connector_state(state, connector);
10575                 if (IS_ERR(connector_state))
10576                         goto fail;
10577
10578                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10579                 if (IS_ERR(crtc_state))
10580                         goto fail;
10581
10582                 connector_state->best_encoder = NULL;
10583                 connector_state->crtc = NULL;
10584
10585                 crtc_state->base.enable = crtc_state->base.active = false;
10586
10587                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10588                                                       0, 0);
10589                 if (ret)
10590                         goto fail;
10591
10592                 ret = drm_atomic_commit(state);
10593                 if (ret)
10594                         goto fail;
10595
10596                 if (old->release_fb) {
10597                         drm_framebuffer_unregister_private(old->release_fb);
10598                         drm_framebuffer_unreference(old->release_fb);
10599                 }
10600
10601                 return;
10602         }
10603
10604         /* Switch crtc and encoder back off if necessary */
10605         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10606                 connector->funcs->dpms(connector, old->dpms_mode);
10607
10608         return;
10609 fail:
10610         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10611         drm_atomic_state_free(state);
10612 }
10613
10614 static int i9xx_pll_refclk(struct drm_device *dev,
10615                            const struct intel_crtc_state *pipe_config)
10616 {
10617         struct drm_i915_private *dev_priv = dev->dev_private;
10618         u32 dpll = pipe_config->dpll_hw_state.dpll;
10619
10620         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10621                 return dev_priv->vbt.lvds_ssc_freq;
10622         else if (HAS_PCH_SPLIT(dev))
10623                 return 120000;
10624         else if (!IS_GEN2(dev))
10625                 return 96000;
10626         else
10627                 return 48000;
10628 }
10629
10630 /* Returns the clock of the currently programmed mode of the given pipe. */
10631 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10632                                 struct intel_crtc_state *pipe_config)
10633 {
10634         struct drm_device *dev = crtc->base.dev;
10635         struct drm_i915_private *dev_priv = dev->dev_private;
10636         int pipe = pipe_config->cpu_transcoder;
10637         u32 dpll = pipe_config->dpll_hw_state.dpll;
10638         u32 fp;
10639         intel_clock_t clock;
10640         int port_clock;
10641         int refclk = i9xx_pll_refclk(dev, pipe_config);
10642
10643         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10644                 fp = pipe_config->dpll_hw_state.fp0;
10645         else
10646                 fp = pipe_config->dpll_hw_state.fp1;
10647
10648         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10649         if (IS_PINEVIEW(dev)) {
10650                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10651                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10652         } else {
10653                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10654                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10655         }
10656
10657         if (!IS_GEN2(dev)) {
10658                 if (IS_PINEVIEW(dev))
10659                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10660                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10661                 else
10662                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10663                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10664
10665                 switch (dpll & DPLL_MODE_MASK) {
10666                 case DPLLB_MODE_DAC_SERIAL:
10667                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10668                                 5 : 10;
10669                         break;
10670                 case DPLLB_MODE_LVDS:
10671                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10672                                 7 : 14;
10673                         break;
10674                 default:
10675                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10676                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10677                         return;
10678                 }
10679
10680                 if (IS_PINEVIEW(dev))
10681                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10682                 else
10683                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10684         } else {
10685                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10686                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10687
10688                 if (is_lvds) {
10689                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10690                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10691
10692                         if (lvds & LVDS_CLKB_POWER_UP)
10693                                 clock.p2 = 7;
10694                         else
10695                                 clock.p2 = 14;
10696                 } else {
10697                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10698                                 clock.p1 = 2;
10699                         else {
10700                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10701                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10702                         }
10703                         if (dpll & PLL_P2_DIVIDE_BY_4)
10704                                 clock.p2 = 4;
10705                         else
10706                                 clock.p2 = 2;
10707                 }
10708
10709                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10710         }
10711
10712         /*
10713          * This value includes pixel_multiplier. We will use
10714          * port_clock to compute adjusted_mode.crtc_clock in the
10715          * encoder's get_config() function.
10716          */
10717         pipe_config->port_clock = port_clock;
10718 }
10719
10720 int intel_dotclock_calculate(int link_freq,
10721                              const struct intel_link_m_n *m_n)
10722 {
10723         /*
10724          * The calculation for the data clock is:
10725          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10726          * But we want to avoid losing precison if possible, so:
10727          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10728          *
10729          * and the link clock is simpler:
10730          * link_clock = (m * link_clock) / n
10731          */
10732
10733         if (!m_n->link_n)
10734                 return 0;
10735
10736         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10737 }
10738
10739 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10740                                    struct intel_crtc_state *pipe_config)
10741 {
10742         struct drm_device *dev = crtc->base.dev;
10743
10744         /* read out port_clock from the DPLL */
10745         i9xx_crtc_clock_get(crtc, pipe_config);
10746
10747         /*
10748          * This value does not include pixel_multiplier.
10749          * We will check that port_clock and adjusted_mode.crtc_clock
10750          * agree once we know their relationship in the encoder's
10751          * get_config() function.
10752          */
10753         pipe_config->base.adjusted_mode.crtc_clock =
10754                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10755                                          &pipe_config->fdi_m_n);
10756 }
10757
10758 /** Returns the currently programmed mode of the given pipe. */
10759 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10760                                              struct drm_crtc *crtc)
10761 {
10762         struct drm_i915_private *dev_priv = dev->dev_private;
10763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10764         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10765         struct drm_display_mode *mode;
10766         struct intel_crtc_state pipe_config;
10767         int htot = I915_READ(HTOTAL(cpu_transcoder));
10768         int hsync = I915_READ(HSYNC(cpu_transcoder));
10769         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10770         int vsync = I915_READ(VSYNC(cpu_transcoder));
10771         enum pipe pipe = intel_crtc->pipe;
10772
10773         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10774         if (!mode)
10775                 return NULL;
10776
10777         /*
10778          * Construct a pipe_config sufficient for getting the clock info
10779          * back out of crtc_clock_get.
10780          *
10781          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10782          * to use a real value here instead.
10783          */
10784         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10785         pipe_config.pixel_multiplier = 1;
10786         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10787         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10788         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10789         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10790
10791         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10792         mode->hdisplay = (htot & 0xffff) + 1;
10793         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10794         mode->hsync_start = (hsync & 0xffff) + 1;
10795         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10796         mode->vdisplay = (vtot & 0xffff) + 1;
10797         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10798         mode->vsync_start = (vsync & 0xffff) + 1;
10799         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10800
10801         drm_mode_set_name(mode);
10802
10803         return mode;
10804 }
10805
10806 void intel_mark_busy(struct drm_device *dev)
10807 {
10808         struct drm_i915_private *dev_priv = dev->dev_private;
10809
10810         if (dev_priv->mm.busy)
10811                 return;
10812
10813         intel_runtime_pm_get(dev_priv);
10814         i915_update_gfx_val(dev_priv);
10815         if (INTEL_INFO(dev)->gen >= 6)
10816                 gen6_rps_busy(dev_priv);
10817         dev_priv->mm.busy = true;
10818 }
10819
10820 void intel_mark_idle(struct drm_device *dev)
10821 {
10822         struct drm_i915_private *dev_priv = dev->dev_private;
10823
10824         if (!dev_priv->mm.busy)
10825                 return;
10826
10827         dev_priv->mm.busy = false;
10828
10829         if (INTEL_INFO(dev)->gen >= 6)
10830                 gen6_rps_idle(dev->dev_private);
10831
10832         intel_runtime_pm_put(dev_priv);
10833 }
10834
10835 static void intel_crtc_destroy(struct drm_crtc *crtc)
10836 {
10837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10838         struct drm_device *dev = crtc->dev;
10839         struct intel_unpin_work *work;
10840
10841         spin_lock_irq(&dev->event_lock);
10842         work = intel_crtc->unpin_work;
10843         intel_crtc->unpin_work = NULL;
10844         spin_unlock_irq(&dev->event_lock);
10845
10846         if (work) {
10847                 cancel_work_sync(&work->work);
10848                 kfree(work);
10849         }
10850
10851         drm_crtc_cleanup(crtc);
10852
10853         kfree(intel_crtc);
10854 }
10855
10856 static void intel_unpin_work_fn(struct work_struct *__work)
10857 {
10858         struct intel_unpin_work *work =
10859                 container_of(__work, struct intel_unpin_work, work);
10860         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10861         struct drm_device *dev = crtc->base.dev;
10862         struct drm_plane *primary = crtc->base.primary;
10863
10864         mutex_lock(&dev->struct_mutex);
10865         intel_unpin_fb_obj(work->old_fb, primary->state);
10866         drm_gem_object_unreference(&work->pending_flip_obj->base);
10867
10868         if (work->flip_queued_req)
10869                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10870         mutex_unlock(&dev->struct_mutex);
10871
10872         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10873         drm_framebuffer_unreference(work->old_fb);
10874
10875         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10876         atomic_dec(&crtc->unpin_work_count);
10877
10878         kfree(work);
10879 }
10880
10881 static void do_intel_finish_page_flip(struct drm_device *dev,
10882                                       struct drm_crtc *crtc)
10883 {
10884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10885         struct intel_unpin_work *work;
10886         unsigned long flags;
10887
10888         /* Ignore early vblank irqs */
10889         if (intel_crtc == NULL)
10890                 return;
10891
10892         /*
10893          * This is called both by irq handlers and the reset code (to complete
10894          * lost pageflips) so needs the full irqsave spinlocks.
10895          */
10896         spin_lock_irqsave(&dev->event_lock, flags);
10897         work = intel_crtc->unpin_work;
10898
10899         /* Ensure we don't miss a work->pending update ... */
10900         smp_rmb();
10901
10902         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10903                 spin_unlock_irqrestore(&dev->event_lock, flags);
10904                 return;
10905         }
10906
10907         page_flip_completed(intel_crtc);
10908
10909         spin_unlock_irqrestore(&dev->event_lock, flags);
10910 }
10911
10912 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10913 {
10914         struct drm_i915_private *dev_priv = dev->dev_private;
10915         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10916
10917         do_intel_finish_page_flip(dev, crtc);
10918 }
10919
10920 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10921 {
10922         struct drm_i915_private *dev_priv = dev->dev_private;
10923         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10924
10925         do_intel_finish_page_flip(dev, crtc);
10926 }
10927
10928 /* Is 'a' after or equal to 'b'? */
10929 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10930 {
10931         return !((a - b) & 0x80000000);
10932 }
10933
10934 static bool page_flip_finished(struct intel_crtc *crtc)
10935 {
10936         struct drm_device *dev = crtc->base.dev;
10937         struct drm_i915_private *dev_priv = dev->dev_private;
10938
10939         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10940             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10941                 return true;
10942
10943         /*
10944          * The relevant registers doen't exist on pre-ctg.
10945          * As the flip done interrupt doesn't trigger for mmio
10946          * flips on gmch platforms, a flip count check isn't
10947          * really needed there. But since ctg has the registers,
10948          * include it in the check anyway.
10949          */
10950         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10951                 return true;
10952
10953         /*
10954          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10955          * used the same base address. In that case the mmio flip might
10956          * have completed, but the CS hasn't even executed the flip yet.
10957          *
10958          * A flip count check isn't enough as the CS might have updated
10959          * the base address just after start of vblank, but before we
10960          * managed to process the interrupt. This means we'd complete the
10961          * CS flip too soon.
10962          *
10963          * Combining both checks should get us a good enough result. It may
10964          * still happen that the CS flip has been executed, but has not
10965          * yet actually completed. But in case the base address is the same
10966          * anyway, we don't really care.
10967          */
10968         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10969                 crtc->unpin_work->gtt_offset &&
10970                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10971                                     crtc->unpin_work->flip_count);
10972 }
10973
10974 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10975 {
10976         struct drm_i915_private *dev_priv = dev->dev_private;
10977         struct intel_crtc *intel_crtc =
10978                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10979         unsigned long flags;
10980
10981
10982         /*
10983          * This is called both by irq handlers and the reset code (to complete
10984          * lost pageflips) so needs the full irqsave spinlocks.
10985          *
10986          * NB: An MMIO update of the plane base pointer will also
10987          * generate a page-flip completion irq, i.e. every modeset
10988          * is also accompanied by a spurious intel_prepare_page_flip().
10989          */
10990         spin_lock_irqsave(&dev->event_lock, flags);
10991         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10992                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10993         spin_unlock_irqrestore(&dev->event_lock, flags);
10994 }
10995
10996 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10997 {
10998         /* Ensure that the work item is consistent when activating it ... */
10999         smp_wmb();
11000         atomic_set(&work->pending, INTEL_FLIP_PENDING);
11001         /* and that it is marked active as soon as the irq could fire. */
11002         smp_wmb();
11003 }
11004
11005 static int intel_gen2_queue_flip(struct drm_device *dev,
11006                                  struct drm_crtc *crtc,
11007                                  struct drm_framebuffer *fb,
11008                                  struct drm_i915_gem_object *obj,
11009                                  struct drm_i915_gem_request *req,
11010                                  uint32_t flags)
11011 {
11012         struct intel_engine_cs *ring = req->ring;
11013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11014         u32 flip_mask;
11015         int ret;
11016
11017         ret = intel_ring_begin(req, 6);
11018         if (ret)
11019                 return ret;
11020
11021         /* Can't queue multiple flips, so wait for the previous
11022          * one to finish before executing the next.
11023          */
11024         if (intel_crtc->plane)
11025                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11026         else
11027                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11028         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11029         intel_ring_emit(ring, MI_NOOP);
11030         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11031                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11032         intel_ring_emit(ring, fb->pitches[0]);
11033         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11034         intel_ring_emit(ring, 0); /* aux display base address, unused */
11035
11036         intel_mark_page_flip_active(intel_crtc->unpin_work);
11037         return 0;
11038 }
11039
11040 static int intel_gen3_queue_flip(struct drm_device *dev,
11041                                  struct drm_crtc *crtc,
11042                                  struct drm_framebuffer *fb,
11043                                  struct drm_i915_gem_object *obj,
11044                                  struct drm_i915_gem_request *req,
11045                                  uint32_t flags)
11046 {
11047         struct intel_engine_cs *ring = req->ring;
11048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11049         u32 flip_mask;
11050         int ret;
11051
11052         ret = intel_ring_begin(req, 6);
11053         if (ret)
11054                 return ret;
11055
11056         if (intel_crtc->plane)
11057                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11058         else
11059                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11060         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11061         intel_ring_emit(ring, MI_NOOP);
11062         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11063                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11064         intel_ring_emit(ring, fb->pitches[0]);
11065         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11066         intel_ring_emit(ring, MI_NOOP);
11067
11068         intel_mark_page_flip_active(intel_crtc->unpin_work);
11069         return 0;
11070 }
11071
11072 static int intel_gen4_queue_flip(struct drm_device *dev,
11073                                  struct drm_crtc *crtc,
11074                                  struct drm_framebuffer *fb,
11075                                  struct drm_i915_gem_object *obj,
11076                                  struct drm_i915_gem_request *req,
11077                                  uint32_t flags)
11078 {
11079         struct intel_engine_cs *ring = req->ring;
11080         struct drm_i915_private *dev_priv = dev->dev_private;
11081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11082         uint32_t pf, pipesrc;
11083         int ret;
11084
11085         ret = intel_ring_begin(req, 4);
11086         if (ret)
11087                 return ret;
11088
11089         /* i965+ uses the linear or tiled offsets from the
11090          * Display Registers (which do not change across a page-flip)
11091          * so we need only reprogram the base address.
11092          */
11093         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11094                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11095         intel_ring_emit(ring, fb->pitches[0]);
11096         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11097                         obj->tiling_mode);
11098
11099         /* XXX Enabling the panel-fitter across page-flip is so far
11100          * untested on non-native modes, so ignore it for now.
11101          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11102          */
11103         pf = 0;
11104         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11105         intel_ring_emit(ring, pf | pipesrc);
11106
11107         intel_mark_page_flip_active(intel_crtc->unpin_work);
11108         return 0;
11109 }
11110
11111 static int intel_gen6_queue_flip(struct drm_device *dev,
11112                                  struct drm_crtc *crtc,
11113                                  struct drm_framebuffer *fb,
11114                                  struct drm_i915_gem_object *obj,
11115                                  struct drm_i915_gem_request *req,
11116                                  uint32_t flags)
11117 {
11118         struct intel_engine_cs *ring = req->ring;
11119         struct drm_i915_private *dev_priv = dev->dev_private;
11120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11121         uint32_t pf, pipesrc;
11122         int ret;
11123
11124         ret = intel_ring_begin(req, 4);
11125         if (ret)
11126                 return ret;
11127
11128         intel_ring_emit(ring, MI_DISPLAY_FLIP |
11129                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11130         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11131         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11132
11133         /* Contrary to the suggestions in the documentation,
11134          * "Enable Panel Fitter" does not seem to be required when page
11135          * flipping with a non-native mode, and worse causes a normal
11136          * modeset to fail.
11137          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11138          */
11139         pf = 0;
11140         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11141         intel_ring_emit(ring, pf | pipesrc);
11142
11143         intel_mark_page_flip_active(intel_crtc->unpin_work);
11144         return 0;
11145 }
11146
11147 static int intel_gen7_queue_flip(struct drm_device *dev,
11148                                  struct drm_crtc *crtc,
11149                                  struct drm_framebuffer *fb,
11150                                  struct drm_i915_gem_object *obj,
11151                                  struct drm_i915_gem_request *req,
11152                                  uint32_t flags)
11153 {
11154         struct intel_engine_cs *ring = req->ring;
11155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11156         uint32_t plane_bit = 0;
11157         int len, ret;
11158
11159         switch (intel_crtc->plane) {
11160         case PLANE_A:
11161                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11162                 break;
11163         case PLANE_B:
11164                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11165                 break;
11166         case PLANE_C:
11167                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11168                 break;
11169         default:
11170                 WARN_ONCE(1, "unknown plane in flip command\n");
11171                 return -ENODEV;
11172         }
11173
11174         len = 4;
11175         if (ring->id == RCS) {
11176                 len += 6;
11177                 /*
11178                  * On Gen 8, SRM is now taking an extra dword to accommodate
11179                  * 48bits addresses, and we need a NOOP for the batch size to
11180                  * stay even.
11181                  */
11182                 if (IS_GEN8(dev))
11183                         len += 2;
11184         }
11185
11186         /*
11187          * BSpec MI_DISPLAY_FLIP for IVB:
11188          * "The full packet must be contained within the same cache line."
11189          *
11190          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11191          * cacheline, if we ever start emitting more commands before
11192          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11193          * then do the cacheline alignment, and finally emit the
11194          * MI_DISPLAY_FLIP.
11195          */
11196         ret = intel_ring_cacheline_align(req);
11197         if (ret)
11198                 return ret;
11199
11200         ret = intel_ring_begin(req, len);
11201         if (ret)
11202                 return ret;
11203
11204         /* Unmask the flip-done completion message. Note that the bspec says that
11205          * we should do this for both the BCS and RCS, and that we must not unmask
11206          * more than one flip event at any time (or ensure that one flip message
11207          * can be sent by waiting for flip-done prior to queueing new flips).
11208          * Experimentation says that BCS works despite DERRMR masking all
11209          * flip-done completion events and that unmasking all planes at once
11210          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11211          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11212          */
11213         if (ring->id == RCS) {
11214                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11215                 intel_ring_emit_reg(ring, DERRMR);
11216                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11217                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11218                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11219                 if (IS_GEN8(dev))
11220                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11221                                               MI_SRM_LRM_GLOBAL_GTT);
11222                 else
11223                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11224                                               MI_SRM_LRM_GLOBAL_GTT);
11225                 intel_ring_emit_reg(ring, DERRMR);
11226                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11227                 if (IS_GEN8(dev)) {
11228                         intel_ring_emit(ring, 0);
11229                         intel_ring_emit(ring, MI_NOOP);
11230                 }
11231         }
11232
11233         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11234         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11235         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11236         intel_ring_emit(ring, (MI_NOOP));
11237
11238         intel_mark_page_flip_active(intel_crtc->unpin_work);
11239         return 0;
11240 }
11241
11242 static bool use_mmio_flip(struct intel_engine_cs *ring,
11243                           struct drm_i915_gem_object *obj)
11244 {
11245         /*
11246          * This is not being used for older platforms, because
11247          * non-availability of flip done interrupt forces us to use
11248          * CS flips. Older platforms derive flip done using some clever
11249          * tricks involving the flip_pending status bits and vblank irqs.
11250          * So using MMIO flips there would disrupt this mechanism.
11251          */
11252
11253         if (ring == NULL)
11254                 return true;
11255
11256         if (INTEL_INFO(ring->dev)->gen < 5)
11257                 return false;
11258
11259         if (i915.use_mmio_flip < 0)
11260                 return false;
11261         else if (i915.use_mmio_flip > 0)
11262                 return true;
11263         else if (i915.enable_execlists)
11264                 return true;
11265         else if (obj->base.dma_buf &&
11266                  !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11267                                                        false))
11268                 return true;
11269         else
11270                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11271 }
11272
11273 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11274                              unsigned int rotation,
11275                              struct intel_unpin_work *work)
11276 {
11277         struct drm_device *dev = intel_crtc->base.dev;
11278         struct drm_i915_private *dev_priv = dev->dev_private;
11279         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11280         const enum pipe pipe = intel_crtc->pipe;
11281         u32 ctl, stride, tile_height;
11282
11283         ctl = I915_READ(PLANE_CTL(pipe, 0));
11284         ctl &= ~PLANE_CTL_TILED_MASK;
11285         switch (fb->modifier[0]) {
11286         case DRM_FORMAT_MOD_NONE:
11287                 break;
11288         case I915_FORMAT_MOD_X_TILED:
11289                 ctl |= PLANE_CTL_TILED_X;
11290                 break;
11291         case I915_FORMAT_MOD_Y_TILED:
11292                 ctl |= PLANE_CTL_TILED_Y;
11293                 break;
11294         case I915_FORMAT_MOD_Yf_TILED:
11295                 ctl |= PLANE_CTL_TILED_YF;
11296                 break;
11297         default:
11298                 MISSING_CASE(fb->modifier[0]);
11299         }
11300
11301         /*
11302          * The stride is either expressed as a multiple of 64 bytes chunks for
11303          * linear buffers or in number of tiles for tiled buffers.
11304          */
11305         if (intel_rotation_90_or_270(rotation)) {
11306                 /* stride = Surface height in tiles */
11307                 tile_height = intel_tile_height(dev, fb->pixel_format,
11308                                                 fb->modifier[0], 0);
11309                 stride = DIV_ROUND_UP(fb->height, tile_height);
11310         } else {
11311                 stride = fb->pitches[0] /
11312                                 intel_fb_stride_alignment(dev, fb->modifier[0],
11313                                                           fb->pixel_format);
11314         }
11315
11316         /*
11317          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11318          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11319          */
11320         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11321         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11322
11323         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11324         POSTING_READ(PLANE_SURF(pipe, 0));
11325 }
11326
11327 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11328                              struct intel_unpin_work *work)
11329 {
11330         struct drm_device *dev = intel_crtc->base.dev;
11331         struct drm_i915_private *dev_priv = dev->dev_private;
11332         struct intel_framebuffer *intel_fb =
11333                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11334         struct drm_i915_gem_object *obj = intel_fb->obj;
11335         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11336         u32 dspcntr;
11337
11338         dspcntr = I915_READ(reg);
11339
11340         if (obj->tiling_mode != I915_TILING_NONE)
11341                 dspcntr |= DISPPLANE_TILED;
11342         else
11343                 dspcntr &= ~DISPPLANE_TILED;
11344
11345         I915_WRITE(reg, dspcntr);
11346
11347         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11348         POSTING_READ(DSPSURF(intel_crtc->plane));
11349 }
11350
11351 /*
11352  * XXX: This is the temporary way to update the plane registers until we get
11353  * around to using the usual plane update functions for MMIO flips
11354  */
11355 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11356 {
11357         struct intel_crtc *crtc = mmio_flip->crtc;
11358         struct intel_unpin_work *work;
11359
11360         spin_lock_irq(&crtc->base.dev->event_lock);
11361         work = crtc->unpin_work;
11362         spin_unlock_irq(&crtc->base.dev->event_lock);
11363         if (work == NULL)
11364                 return;
11365
11366         intel_mark_page_flip_active(work);
11367
11368         intel_pipe_update_start(crtc);
11369
11370         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11371                 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11372         else
11373                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11374                 ilk_do_mmio_flip(crtc, work);
11375
11376         intel_pipe_update_end(crtc);
11377 }
11378
11379 static void intel_mmio_flip_work_func(struct work_struct *work)
11380 {
11381         struct intel_mmio_flip *mmio_flip =
11382                 container_of(work, struct intel_mmio_flip, work);
11383         struct intel_framebuffer *intel_fb =
11384                 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11385         struct drm_i915_gem_object *obj = intel_fb->obj;
11386
11387         if (mmio_flip->req) {
11388                 WARN_ON(__i915_wait_request(mmio_flip->req,
11389                                             mmio_flip->crtc->reset_counter,
11390                                             false, NULL,
11391                                             &mmio_flip->i915->rps.mmioflips));
11392                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11393         }
11394
11395         /* For framebuffer backed by dmabuf, wait for fence */
11396         if (obj->base.dma_buf)
11397                 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11398                                                             false, false,
11399                                                             MAX_SCHEDULE_TIMEOUT) < 0);
11400
11401         intel_do_mmio_flip(mmio_flip);
11402         kfree(mmio_flip);
11403 }
11404
11405 static int intel_queue_mmio_flip(struct drm_device *dev,
11406                                  struct drm_crtc *crtc,
11407                                  struct drm_i915_gem_object *obj)
11408 {
11409         struct intel_mmio_flip *mmio_flip;
11410
11411         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11412         if (mmio_flip == NULL)
11413                 return -ENOMEM;
11414
11415         mmio_flip->i915 = to_i915(dev);
11416         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11417         mmio_flip->crtc = to_intel_crtc(crtc);
11418         mmio_flip->rotation = crtc->primary->state->rotation;
11419
11420         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11421         schedule_work(&mmio_flip->work);
11422
11423         return 0;
11424 }
11425
11426 static int intel_default_queue_flip(struct drm_device *dev,
11427                                     struct drm_crtc *crtc,
11428                                     struct drm_framebuffer *fb,
11429                                     struct drm_i915_gem_object *obj,
11430                                     struct drm_i915_gem_request *req,
11431                                     uint32_t flags)
11432 {
11433         return -ENODEV;
11434 }
11435
11436 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11437                                          struct drm_crtc *crtc)
11438 {
11439         struct drm_i915_private *dev_priv = dev->dev_private;
11440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11441         struct intel_unpin_work *work = intel_crtc->unpin_work;
11442         u32 addr;
11443
11444         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11445                 return true;
11446
11447         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11448                 return false;
11449
11450         if (!work->enable_stall_check)
11451                 return false;
11452
11453         if (work->flip_ready_vblank == 0) {
11454                 if (work->flip_queued_req &&
11455                     !i915_gem_request_completed(work->flip_queued_req, true))
11456                         return false;
11457
11458                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11459         }
11460
11461         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11462                 return false;
11463
11464         /* Potential stall - if we see that the flip has happened,
11465          * assume a missed interrupt. */
11466         if (INTEL_INFO(dev)->gen >= 4)
11467                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11468         else
11469                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11470
11471         /* There is a potential issue here with a false positive after a flip
11472          * to the same address. We could address this by checking for a
11473          * non-incrementing frame counter.
11474          */
11475         return addr == work->gtt_offset;
11476 }
11477
11478 void intel_check_page_flip(struct drm_device *dev, int pipe)
11479 {
11480         struct drm_i915_private *dev_priv = dev->dev_private;
11481         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11483         struct intel_unpin_work *work;
11484
11485         WARN_ON(!in_interrupt());
11486
11487         if (crtc == NULL)
11488                 return;
11489
11490         spin_lock(&dev->event_lock);
11491         work = intel_crtc->unpin_work;
11492         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11493                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11494                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11495                 page_flip_completed(intel_crtc);
11496                 work = NULL;
11497         }
11498         if (work != NULL &&
11499             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11500                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11501         spin_unlock(&dev->event_lock);
11502 }
11503
11504 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11505                                 struct drm_framebuffer *fb,
11506                                 struct drm_pending_vblank_event *event,
11507                                 uint32_t page_flip_flags)
11508 {
11509         struct drm_device *dev = crtc->dev;
11510         struct drm_i915_private *dev_priv = dev->dev_private;
11511         struct drm_framebuffer *old_fb = crtc->primary->fb;
11512         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11514         struct drm_plane *primary = crtc->primary;
11515         enum pipe pipe = intel_crtc->pipe;
11516         struct intel_unpin_work *work;
11517         struct intel_engine_cs *ring;
11518         bool mmio_flip;
11519         struct drm_i915_gem_request *request = NULL;
11520         int ret;
11521
11522         /*
11523          * drm_mode_page_flip_ioctl() should already catch this, but double
11524          * check to be safe.  In the future we may enable pageflipping from
11525          * a disabled primary plane.
11526          */
11527         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11528                 return -EBUSY;
11529
11530         /* Can't change pixel format via MI display flips. */
11531         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11532                 return -EINVAL;
11533
11534         /*
11535          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11536          * Note that pitch changes could also affect these register.
11537          */
11538         if (INTEL_INFO(dev)->gen > 3 &&
11539             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11540              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11541                 return -EINVAL;
11542
11543         if (i915_terminally_wedged(&dev_priv->gpu_error))
11544                 goto out_hang;
11545
11546         work = kzalloc(sizeof(*work), GFP_KERNEL);
11547         if (work == NULL)
11548                 return -ENOMEM;
11549
11550         work->event = event;
11551         work->crtc = crtc;
11552         work->old_fb = old_fb;
11553         INIT_WORK(&work->work, intel_unpin_work_fn);
11554
11555         ret = drm_crtc_vblank_get(crtc);
11556         if (ret)
11557                 goto free_work;
11558
11559         /* We borrow the event spin lock for protecting unpin_work */
11560         spin_lock_irq(&dev->event_lock);
11561         if (intel_crtc->unpin_work) {
11562                 /* Before declaring the flip queue wedged, check if
11563                  * the hardware completed the operation behind our backs.
11564                  */
11565                 if (__intel_pageflip_stall_check(dev, crtc)) {
11566                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11567                         page_flip_completed(intel_crtc);
11568                 } else {
11569                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11570                         spin_unlock_irq(&dev->event_lock);
11571
11572                         drm_crtc_vblank_put(crtc);
11573                         kfree(work);
11574                         return -EBUSY;
11575                 }
11576         }
11577         intel_crtc->unpin_work = work;
11578         spin_unlock_irq(&dev->event_lock);
11579
11580         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11581                 flush_workqueue(dev_priv->wq);
11582
11583         /* Reference the objects for the scheduled work. */
11584         drm_framebuffer_reference(work->old_fb);
11585         drm_gem_object_reference(&obj->base);
11586
11587         crtc->primary->fb = fb;
11588         update_state_fb(crtc->primary);
11589
11590         work->pending_flip_obj = obj;
11591
11592         ret = i915_mutex_lock_interruptible(dev);
11593         if (ret)
11594                 goto cleanup;
11595
11596         atomic_inc(&intel_crtc->unpin_work_count);
11597         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11598
11599         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11600                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11601
11602         if (IS_VALLEYVIEW(dev)) {
11603                 ring = &dev_priv->ring[BCS];
11604                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11605                         /* vlv: DISPLAY_FLIP fails to change tiling */
11606                         ring = NULL;
11607         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11608                 ring = &dev_priv->ring[BCS];
11609         } else if (INTEL_INFO(dev)->gen >= 7) {
11610                 ring = i915_gem_request_get_ring(obj->last_write_req);
11611                 if (ring == NULL || ring->id != RCS)
11612                         ring = &dev_priv->ring[BCS];
11613         } else {
11614                 ring = &dev_priv->ring[RCS];
11615         }
11616
11617         mmio_flip = use_mmio_flip(ring, obj);
11618
11619         /* When using CS flips, we want to emit semaphores between rings.
11620          * However, when using mmio flips we will create a task to do the
11621          * synchronisation, so all we want here is to pin the framebuffer
11622          * into the display plane and skip any waits.
11623          */
11624         if (!mmio_flip) {
11625                 ret = i915_gem_object_sync(obj, ring, &request);
11626                 if (ret)
11627                         goto cleanup_pending;
11628         }
11629
11630         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11631                                          crtc->primary->state);
11632         if (ret)
11633                 goto cleanup_pending;
11634
11635         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11636                                                   obj, 0);
11637         work->gtt_offset += intel_crtc->dspaddr_offset;
11638
11639         if (mmio_flip) {
11640                 ret = intel_queue_mmio_flip(dev, crtc, obj);
11641                 if (ret)
11642                         goto cleanup_unpin;
11643
11644                 i915_gem_request_assign(&work->flip_queued_req,
11645                                         obj->last_write_req);
11646         } else {
11647                 if (!request) {
11648                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11649                         if (ret)
11650                                 goto cleanup_unpin;
11651                 }
11652
11653                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11654                                                    page_flip_flags);
11655                 if (ret)
11656                         goto cleanup_unpin;
11657
11658                 i915_gem_request_assign(&work->flip_queued_req, request);
11659         }
11660
11661         if (request)
11662                 i915_add_request_no_flush(request);
11663
11664         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11665         work->enable_stall_check = true;
11666
11667         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11668                           to_intel_plane(primary)->frontbuffer_bit);
11669         mutex_unlock(&dev->struct_mutex);
11670
11671         intel_fbc_deactivate(intel_crtc);
11672         intel_frontbuffer_flip_prepare(dev,
11673                                        to_intel_plane(primary)->frontbuffer_bit);
11674
11675         trace_i915_flip_request(intel_crtc->plane, obj);
11676
11677         return 0;
11678
11679 cleanup_unpin:
11680         intel_unpin_fb_obj(fb, crtc->primary->state);
11681 cleanup_pending:
11682         if (request)
11683                 i915_gem_request_cancel(request);
11684         atomic_dec(&intel_crtc->unpin_work_count);
11685         mutex_unlock(&dev->struct_mutex);
11686 cleanup:
11687         crtc->primary->fb = old_fb;
11688         update_state_fb(crtc->primary);
11689
11690         drm_gem_object_unreference_unlocked(&obj->base);
11691         drm_framebuffer_unreference(work->old_fb);
11692
11693         spin_lock_irq(&dev->event_lock);
11694         intel_crtc->unpin_work = NULL;
11695         spin_unlock_irq(&dev->event_lock);
11696
11697         drm_crtc_vblank_put(crtc);
11698 free_work:
11699         kfree(work);
11700
11701         if (ret == -EIO) {
11702                 struct drm_atomic_state *state;
11703                 struct drm_plane_state *plane_state;
11704
11705 out_hang:
11706                 state = drm_atomic_state_alloc(dev);
11707                 if (!state)
11708                         return -ENOMEM;
11709                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11710
11711 retry:
11712                 plane_state = drm_atomic_get_plane_state(state, primary);
11713                 ret = PTR_ERR_OR_ZERO(plane_state);
11714                 if (!ret) {
11715                         drm_atomic_set_fb_for_plane(plane_state, fb);
11716
11717                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11718                         if (!ret)
11719                                 ret = drm_atomic_commit(state);
11720                 }
11721
11722                 if (ret == -EDEADLK) {
11723                         drm_modeset_backoff(state->acquire_ctx);
11724                         drm_atomic_state_clear(state);
11725                         goto retry;
11726                 }
11727
11728                 if (ret)
11729                         drm_atomic_state_free(state);
11730
11731                 if (ret == 0 && event) {
11732                         spin_lock_irq(&dev->event_lock);
11733                         drm_send_vblank_event(dev, pipe, event);
11734                         spin_unlock_irq(&dev->event_lock);
11735                 }
11736         }
11737         return ret;
11738 }
11739
11740
11741 /**
11742  * intel_wm_need_update - Check whether watermarks need updating
11743  * @plane: drm plane
11744  * @state: new plane state
11745  *
11746  * Check current plane state versus the new one to determine whether
11747  * watermarks need to be recalculated.
11748  *
11749  * Returns true or false.
11750  */
11751 static bool intel_wm_need_update(struct drm_plane *plane,
11752                                  struct drm_plane_state *state)
11753 {
11754         struct intel_plane_state *new = to_intel_plane_state(state);
11755         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11756
11757         /* Update watermarks on tiling or size changes. */
11758         if (new->visible != cur->visible)
11759                 return true;
11760
11761         if (!cur->base.fb || !new->base.fb)
11762                 return false;
11763
11764         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11765             cur->base.rotation != new->base.rotation ||
11766             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11767             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11768             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11769             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11770                 return true;
11771
11772         return false;
11773 }
11774
11775 static bool needs_scaling(struct intel_plane_state *state)
11776 {
11777         int src_w = drm_rect_width(&state->src) >> 16;
11778         int src_h = drm_rect_height(&state->src) >> 16;
11779         int dst_w = drm_rect_width(&state->dst);
11780         int dst_h = drm_rect_height(&state->dst);
11781
11782         return (src_w != dst_w || src_h != dst_h);
11783 }
11784
11785 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11786                                     struct drm_plane_state *plane_state)
11787 {
11788         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11789         struct drm_crtc *crtc = crtc_state->crtc;
11790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11791         struct drm_plane *plane = plane_state->plane;
11792         struct drm_device *dev = crtc->dev;
11793         struct drm_i915_private *dev_priv = dev->dev_private;
11794         struct intel_plane_state *old_plane_state =
11795                 to_intel_plane_state(plane->state);
11796         int idx = intel_crtc->base.base.id, ret;
11797         int i = drm_plane_index(plane);
11798         bool mode_changed = needs_modeset(crtc_state);
11799         bool was_crtc_enabled = crtc->state->active;
11800         bool is_crtc_enabled = crtc_state->active;
11801         bool turn_off, turn_on, visible, was_visible;
11802         struct drm_framebuffer *fb = plane_state->fb;
11803
11804         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11805             plane->type != DRM_PLANE_TYPE_CURSOR) {
11806                 ret = skl_update_scaler_plane(
11807                         to_intel_crtc_state(crtc_state),
11808                         to_intel_plane_state(plane_state));
11809                 if (ret)
11810                         return ret;
11811         }
11812
11813         was_visible = old_plane_state->visible;
11814         visible = to_intel_plane_state(plane_state)->visible;
11815
11816         if (!was_crtc_enabled && WARN_ON(was_visible))
11817                 was_visible = false;
11818
11819         if (!is_crtc_enabled && WARN_ON(visible))
11820                 visible = false;
11821
11822         if (!was_visible && !visible)
11823                 return 0;
11824
11825         turn_off = was_visible && (!visible || mode_changed);
11826         turn_on = visible && (!was_visible || mode_changed);
11827
11828         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11829                          plane->base.id, fb ? fb->base.id : -1);
11830
11831         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11832                          plane->base.id, was_visible, visible,
11833                          turn_off, turn_on, mode_changed);
11834
11835         if (turn_on || turn_off) {
11836                 pipe_config->wm_changed = true;
11837
11838                 /* must disable cxsr around plane enable/disable */
11839                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11840                         if (is_crtc_enabled)
11841                                 intel_crtc->atomic.wait_vblank = true;
11842                         pipe_config->disable_cxsr = true;
11843                 }
11844         } else if (intel_wm_need_update(plane, plane_state)) {
11845                 pipe_config->wm_changed = true;
11846         }
11847
11848         if (visible || was_visible)
11849                 intel_crtc->atomic.fb_bits |=
11850                         to_intel_plane(plane)->frontbuffer_bit;
11851
11852         switch (plane->type) {
11853         case DRM_PLANE_TYPE_PRIMARY:
11854                 intel_crtc->atomic.pre_disable_primary = turn_off;
11855                 intel_crtc->atomic.post_enable_primary = turn_on;
11856
11857                 if (turn_off) {
11858                         /*
11859                          * FIXME: Actually if we will still have any other
11860                          * plane enabled on the pipe we could let IPS enabled
11861                          * still, but for now lets consider that when we make
11862                          * primary invisible by setting DSPCNTR to 0 on
11863                          * update_primary_plane function IPS needs to be
11864                          * disable.
11865                          */
11866                         intel_crtc->atomic.disable_ips = true;
11867
11868                         intel_crtc->atomic.disable_fbc = true;
11869                 }
11870
11871                 /*
11872                  * FBC does not work on some platforms for rotated
11873                  * planes, so disable it when rotation is not 0 and
11874                  * update it when rotation is set back to 0.
11875                  *
11876                  * FIXME: This is redundant with the fbc update done in
11877                  * the primary plane enable function except that that
11878                  * one is done too late. We eventually need to unify
11879                  * this.
11880                  */
11881
11882                 if (visible &&
11883                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11884                     dev_priv->fbc.crtc == intel_crtc &&
11885                     plane_state->rotation != BIT(DRM_ROTATE_0))
11886                         intel_crtc->atomic.disable_fbc = true;
11887
11888                 /*
11889                  * BDW signals flip done immediately if the plane
11890                  * is disabled, even if the plane enable is already
11891                  * armed to occur at the next vblank :(
11892                  */
11893                 if (turn_on && IS_BROADWELL(dev))
11894                         intel_crtc->atomic.wait_vblank = true;
11895
11896                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11897                 break;
11898         case DRM_PLANE_TYPE_CURSOR:
11899                 break;
11900         case DRM_PLANE_TYPE_OVERLAY:
11901                 /*
11902                  * WaCxSRDisabledForSpriteScaling:ivb
11903                  *
11904                  * cstate->update_wm was already set above, so this flag will
11905                  * take effect when we commit and program watermarks.
11906                  */
11907                 if (IS_IVYBRIDGE(dev) &&
11908                     needs_scaling(to_intel_plane_state(plane_state)) &&
11909                     !needs_scaling(old_plane_state)) {
11910                         to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11911                 } else if (turn_off && !mode_changed) {
11912                         intel_crtc->atomic.wait_vblank = true;
11913                         intel_crtc->atomic.update_sprite_watermarks |=
11914                                 1 << i;
11915                 }
11916
11917                 break;
11918         }
11919         return 0;
11920 }
11921
11922 static bool encoders_cloneable(const struct intel_encoder *a,
11923                                const struct intel_encoder *b)
11924 {
11925         /* masks could be asymmetric, so check both ways */
11926         return a == b || (a->cloneable & (1 << b->type) &&
11927                           b->cloneable & (1 << a->type));
11928 }
11929
11930 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11931                                          struct intel_crtc *crtc,
11932                                          struct intel_encoder *encoder)
11933 {
11934         struct intel_encoder *source_encoder;
11935         struct drm_connector *connector;
11936         struct drm_connector_state *connector_state;
11937         int i;
11938
11939         for_each_connector_in_state(state, connector, connector_state, i) {
11940                 if (connector_state->crtc != &crtc->base)
11941                         continue;
11942
11943                 source_encoder =
11944                         to_intel_encoder(connector_state->best_encoder);
11945                 if (!encoders_cloneable(encoder, source_encoder))
11946                         return false;
11947         }
11948
11949         return true;
11950 }
11951
11952 static bool check_encoder_cloning(struct drm_atomic_state *state,
11953                                   struct intel_crtc *crtc)
11954 {
11955         struct intel_encoder *encoder;
11956         struct drm_connector *connector;
11957         struct drm_connector_state *connector_state;
11958         int i;
11959
11960         for_each_connector_in_state(state, connector, connector_state, i) {
11961                 if (connector_state->crtc != &crtc->base)
11962                         continue;
11963
11964                 encoder = to_intel_encoder(connector_state->best_encoder);
11965                 if (!check_single_encoder_cloning(state, crtc, encoder))
11966                         return false;
11967         }
11968
11969         return true;
11970 }
11971
11972 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11973                                    struct drm_crtc_state *crtc_state)
11974 {
11975         struct drm_device *dev = crtc->dev;
11976         struct drm_i915_private *dev_priv = dev->dev_private;
11977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11978         struct intel_crtc_state *pipe_config =
11979                 to_intel_crtc_state(crtc_state);
11980         struct drm_atomic_state *state = crtc_state->state;
11981         int ret;
11982         bool mode_changed = needs_modeset(crtc_state);
11983
11984         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11985                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11986                 return -EINVAL;
11987         }
11988
11989         if (mode_changed && !crtc_state->active)
11990                 pipe_config->wm_changed = true;
11991
11992         if (mode_changed && crtc_state->enable &&
11993             dev_priv->display.crtc_compute_clock &&
11994             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11995                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11996                                                            pipe_config);
11997                 if (ret)
11998                         return ret;
11999         }
12000
12001         ret = 0;
12002         if (dev_priv->display.compute_pipe_wm) {
12003                 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12004                 if (ret)
12005                         return ret;
12006         }
12007
12008         if (INTEL_INFO(dev)->gen >= 9) {
12009                 if (mode_changed)
12010                         ret = skl_update_scaler_crtc(pipe_config);
12011
12012                 if (!ret)
12013                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
12014                                                          pipe_config);
12015         }
12016
12017         return ret;
12018 }
12019
12020 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12021         .mode_set_base_atomic = intel_pipe_set_base_atomic,
12022         .load_lut = intel_crtc_load_lut,
12023         .atomic_begin = intel_begin_crtc_commit,
12024         .atomic_flush = intel_finish_crtc_commit,
12025         .atomic_check = intel_crtc_atomic_check,
12026 };
12027
12028 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12029 {
12030         struct intel_connector *connector;
12031
12032         for_each_intel_connector(dev, connector) {
12033                 if (connector->base.encoder) {
12034                         connector->base.state->best_encoder =
12035                                 connector->base.encoder;
12036                         connector->base.state->crtc =
12037                                 connector->base.encoder->crtc;
12038                 } else {
12039                         connector->base.state->best_encoder = NULL;
12040                         connector->base.state->crtc = NULL;
12041                 }
12042         }
12043 }
12044
12045 static void
12046 connected_sink_compute_bpp(struct intel_connector *connector,
12047                            struct intel_crtc_state *pipe_config)
12048 {
12049         int bpp = pipe_config->pipe_bpp;
12050
12051         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12052                 connector->base.base.id,
12053                 connector->base.name);
12054
12055         /* Don't use an invalid EDID bpc value */
12056         if (connector->base.display_info.bpc &&
12057             connector->base.display_info.bpc * 3 < bpp) {
12058                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12059                               bpp, connector->base.display_info.bpc*3);
12060                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12061         }
12062
12063         /* Clamp bpp to 8 on screens without EDID 1.4 */
12064         if (connector->base.display_info.bpc == 0 && bpp > 24) {
12065                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12066                               bpp);
12067                 pipe_config->pipe_bpp = 24;
12068         }
12069 }
12070
12071 static int
12072 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12073                           struct intel_crtc_state *pipe_config)
12074 {
12075         struct drm_device *dev = crtc->base.dev;
12076         struct drm_atomic_state *state;
12077         struct drm_connector *connector;
12078         struct drm_connector_state *connector_state;
12079         int bpp, i;
12080
12081         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12082                 bpp = 10*3;
12083         else if (INTEL_INFO(dev)->gen >= 5)
12084                 bpp = 12*3;
12085         else
12086                 bpp = 8*3;
12087
12088
12089         pipe_config->pipe_bpp = bpp;
12090
12091         state = pipe_config->base.state;
12092
12093         /* Clamp display bpp to EDID value */
12094         for_each_connector_in_state(state, connector, connector_state, i) {
12095                 if (connector_state->crtc != &crtc->base)
12096                         continue;
12097
12098                 connected_sink_compute_bpp(to_intel_connector(connector),
12099                                            pipe_config);
12100         }
12101
12102         return bpp;
12103 }
12104
12105 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12106 {
12107         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12108                         "type: 0x%x flags: 0x%x\n",
12109                 mode->crtc_clock,
12110                 mode->crtc_hdisplay, mode->crtc_hsync_start,
12111                 mode->crtc_hsync_end, mode->crtc_htotal,
12112                 mode->crtc_vdisplay, mode->crtc_vsync_start,
12113                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12114 }
12115
12116 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12117                                    struct intel_crtc_state *pipe_config,
12118                                    const char *context)
12119 {
12120         struct drm_device *dev = crtc->base.dev;
12121         struct drm_plane *plane;
12122         struct intel_plane *intel_plane;
12123         struct intel_plane_state *state;
12124         struct drm_framebuffer *fb;
12125
12126         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12127                       context, pipe_config, pipe_name(crtc->pipe));
12128
12129         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12130         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12131                       pipe_config->pipe_bpp, pipe_config->dither);
12132         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12133                       pipe_config->has_pch_encoder,
12134                       pipe_config->fdi_lanes,
12135                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12136                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12137                       pipe_config->fdi_m_n.tu);
12138         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12139                       pipe_config->has_dp_encoder,
12140                       pipe_config->lane_count,
12141                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12142                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12143                       pipe_config->dp_m_n.tu);
12144
12145         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12146                       pipe_config->has_dp_encoder,
12147                       pipe_config->lane_count,
12148                       pipe_config->dp_m2_n2.gmch_m,
12149                       pipe_config->dp_m2_n2.gmch_n,
12150                       pipe_config->dp_m2_n2.link_m,
12151                       pipe_config->dp_m2_n2.link_n,
12152                       pipe_config->dp_m2_n2.tu);
12153
12154         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12155                       pipe_config->has_audio,
12156                       pipe_config->has_infoframe);
12157
12158         DRM_DEBUG_KMS("requested mode:\n");
12159         drm_mode_debug_printmodeline(&pipe_config->base.mode);
12160         DRM_DEBUG_KMS("adjusted mode:\n");
12161         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12162         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12163         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12164         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12165                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12166         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12167                       crtc->num_scalers,
12168                       pipe_config->scaler_state.scaler_users,
12169                       pipe_config->scaler_state.scaler_id);
12170         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12171                       pipe_config->gmch_pfit.control,
12172                       pipe_config->gmch_pfit.pgm_ratios,
12173                       pipe_config->gmch_pfit.lvds_border_bits);
12174         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12175                       pipe_config->pch_pfit.pos,
12176                       pipe_config->pch_pfit.size,
12177                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12178         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12179         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12180
12181         if (IS_BROXTON(dev)) {
12182                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12183                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12184                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12185                               pipe_config->ddi_pll_sel,
12186                               pipe_config->dpll_hw_state.ebb0,
12187                               pipe_config->dpll_hw_state.ebb4,
12188                               pipe_config->dpll_hw_state.pll0,
12189                               pipe_config->dpll_hw_state.pll1,
12190                               pipe_config->dpll_hw_state.pll2,
12191                               pipe_config->dpll_hw_state.pll3,
12192                               pipe_config->dpll_hw_state.pll6,
12193                               pipe_config->dpll_hw_state.pll8,
12194                               pipe_config->dpll_hw_state.pll9,
12195                               pipe_config->dpll_hw_state.pll10,
12196                               pipe_config->dpll_hw_state.pcsdw12);
12197         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12198                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12199                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12200                               pipe_config->ddi_pll_sel,
12201                               pipe_config->dpll_hw_state.ctrl1,
12202                               pipe_config->dpll_hw_state.cfgcr1,
12203                               pipe_config->dpll_hw_state.cfgcr2);
12204         } else if (HAS_DDI(dev)) {
12205                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12206                               pipe_config->ddi_pll_sel,
12207                               pipe_config->dpll_hw_state.wrpll,
12208                               pipe_config->dpll_hw_state.spll);
12209         } else {
12210                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12211                               "fp0: 0x%x, fp1: 0x%x\n",
12212                               pipe_config->dpll_hw_state.dpll,
12213                               pipe_config->dpll_hw_state.dpll_md,
12214                               pipe_config->dpll_hw_state.fp0,
12215                               pipe_config->dpll_hw_state.fp1);
12216         }
12217
12218         DRM_DEBUG_KMS("planes on this crtc\n");
12219         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12220                 intel_plane = to_intel_plane(plane);
12221                 if (intel_plane->pipe != crtc->pipe)
12222                         continue;
12223
12224                 state = to_intel_plane_state(plane->state);
12225                 fb = state->base.fb;
12226                 if (!fb) {
12227                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12228                                 "disabled, scaler_id = %d\n",
12229                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12230                                 plane->base.id, intel_plane->pipe,
12231                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12232                                 drm_plane_index(plane), state->scaler_id);
12233                         continue;
12234                 }
12235
12236                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12237                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12238                         plane->base.id, intel_plane->pipe,
12239                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12240                         drm_plane_index(plane));
12241                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12242                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12243                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12244                         state->scaler_id,
12245                         state->src.x1 >> 16, state->src.y1 >> 16,
12246                         drm_rect_width(&state->src) >> 16,
12247                         drm_rect_height(&state->src) >> 16,
12248                         state->dst.x1, state->dst.y1,
12249                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12250         }
12251 }
12252
12253 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12254 {
12255         struct drm_device *dev = state->dev;
12256         struct intel_encoder *encoder;
12257         struct drm_connector *connector;
12258         struct drm_connector_state *connector_state;
12259         unsigned int used_ports = 0;
12260         int i;
12261
12262         /*
12263          * Walk the connector list instead of the encoder
12264          * list to detect the problem on ddi platforms
12265          * where there's just one encoder per digital port.
12266          */
12267         for_each_connector_in_state(state, connector, connector_state, i) {
12268                 if (!connector_state->best_encoder)
12269                         continue;
12270
12271                 encoder = to_intel_encoder(connector_state->best_encoder);
12272
12273                 WARN_ON(!connector_state->crtc);
12274
12275                 switch (encoder->type) {
12276                         unsigned int port_mask;
12277                 case INTEL_OUTPUT_UNKNOWN:
12278                         if (WARN_ON(!HAS_DDI(dev)))
12279                                 break;
12280                 case INTEL_OUTPUT_DISPLAYPORT:
12281                 case INTEL_OUTPUT_HDMI:
12282                 case INTEL_OUTPUT_EDP:
12283                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12284
12285                         /* the same port mustn't appear more than once */
12286                         if (used_ports & port_mask)
12287                                 return false;
12288
12289                         used_ports |= port_mask;
12290                 default:
12291                         break;
12292                 }
12293         }
12294
12295         return true;
12296 }
12297
12298 static void
12299 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12300 {
12301         struct drm_crtc_state tmp_state;
12302         struct intel_crtc_scaler_state scaler_state;
12303         struct intel_dpll_hw_state dpll_hw_state;
12304         enum intel_dpll_id shared_dpll;
12305         uint32_t ddi_pll_sel;
12306         bool force_thru;
12307
12308         /* FIXME: before the switch to atomic started, a new pipe_config was
12309          * kzalloc'd. Code that depends on any field being zero should be
12310          * fixed, so that the crtc_state can be safely duplicated. For now,
12311          * only fields that are know to not cause problems are preserved. */
12312
12313         tmp_state = crtc_state->base;
12314         scaler_state = crtc_state->scaler_state;
12315         shared_dpll = crtc_state->shared_dpll;
12316         dpll_hw_state = crtc_state->dpll_hw_state;
12317         ddi_pll_sel = crtc_state->ddi_pll_sel;
12318         force_thru = crtc_state->pch_pfit.force_thru;
12319
12320         memset(crtc_state, 0, sizeof *crtc_state);
12321
12322         crtc_state->base = tmp_state;
12323         crtc_state->scaler_state = scaler_state;
12324         crtc_state->shared_dpll = shared_dpll;
12325         crtc_state->dpll_hw_state = dpll_hw_state;
12326         crtc_state->ddi_pll_sel = ddi_pll_sel;
12327         crtc_state->pch_pfit.force_thru = force_thru;
12328 }
12329
12330 static int
12331 intel_modeset_pipe_config(struct drm_crtc *crtc,
12332                           struct intel_crtc_state *pipe_config)
12333 {
12334         struct drm_atomic_state *state = pipe_config->base.state;
12335         struct intel_encoder *encoder;
12336         struct drm_connector *connector;
12337         struct drm_connector_state *connector_state;
12338         int base_bpp, ret = -EINVAL;
12339         int i;
12340         bool retry = true;
12341
12342         clear_intel_crtc_state(pipe_config);
12343
12344         pipe_config->cpu_transcoder =
12345                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12346
12347         /*
12348          * Sanitize sync polarity flags based on requested ones. If neither
12349          * positive or negative polarity is requested, treat this as meaning
12350          * negative polarity.
12351          */
12352         if (!(pipe_config->base.adjusted_mode.flags &
12353               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12354                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12355
12356         if (!(pipe_config->base.adjusted_mode.flags &
12357               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12358                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12359
12360         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12361                                              pipe_config);
12362         if (base_bpp < 0)
12363                 goto fail;
12364
12365         /*
12366          * Determine the real pipe dimensions. Note that stereo modes can
12367          * increase the actual pipe size due to the frame doubling and
12368          * insertion of additional space for blanks between the frame. This
12369          * is stored in the crtc timings. We use the requested mode to do this
12370          * computation to clearly distinguish it from the adjusted mode, which
12371          * can be changed by the connectors in the below retry loop.
12372          */
12373         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12374                                &pipe_config->pipe_src_w,
12375                                &pipe_config->pipe_src_h);
12376
12377 encoder_retry:
12378         /* Ensure the port clock defaults are reset when retrying. */
12379         pipe_config->port_clock = 0;
12380         pipe_config->pixel_multiplier = 1;
12381
12382         /* Fill in default crtc timings, allow encoders to overwrite them. */
12383         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12384                               CRTC_STEREO_DOUBLE);
12385
12386         /* Pass our mode to the connectors and the CRTC to give them a chance to
12387          * adjust it according to limitations or connector properties, and also
12388          * a chance to reject the mode entirely.
12389          */
12390         for_each_connector_in_state(state, connector, connector_state, i) {
12391                 if (connector_state->crtc != crtc)
12392                         continue;
12393
12394                 encoder = to_intel_encoder(connector_state->best_encoder);
12395
12396                 if (!(encoder->compute_config(encoder, pipe_config))) {
12397                         DRM_DEBUG_KMS("Encoder config failure\n");
12398                         goto fail;
12399                 }
12400         }
12401
12402         /* Set default port clock if not overwritten by the encoder. Needs to be
12403          * done afterwards in case the encoder adjusts the mode. */
12404         if (!pipe_config->port_clock)
12405                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12406                         * pipe_config->pixel_multiplier;
12407
12408         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12409         if (ret < 0) {
12410                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12411                 goto fail;
12412         }
12413
12414         if (ret == RETRY) {
12415                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12416                         ret = -EINVAL;
12417                         goto fail;
12418                 }
12419
12420                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12421                 retry = false;
12422                 goto encoder_retry;
12423         }
12424
12425         /* Dithering seems to not pass-through bits correctly when it should, so
12426          * only enable it on 6bpc panels. */
12427         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12428         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12429                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12430
12431 fail:
12432         return ret;
12433 }
12434
12435 static void
12436 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12437 {
12438         struct drm_crtc *crtc;
12439         struct drm_crtc_state *crtc_state;
12440         int i;
12441
12442         /* Double check state. */
12443         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12444                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12445
12446                 /* Update hwmode for vblank functions */
12447                 if (crtc->state->active)
12448                         crtc->hwmode = crtc->state->adjusted_mode;
12449                 else
12450                         crtc->hwmode.crtc_clock = 0;
12451
12452                 /*
12453                  * Update legacy state to satisfy fbc code. This can
12454                  * be removed when fbc uses the atomic state.
12455                  */
12456                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12457                         struct drm_plane_state *plane_state = crtc->primary->state;
12458
12459                         crtc->primary->fb = plane_state->fb;
12460                         crtc->x = plane_state->src_x >> 16;
12461                         crtc->y = plane_state->src_y >> 16;
12462                 }
12463         }
12464 }
12465
12466 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12467 {
12468         int diff;
12469
12470         if (clock1 == clock2)
12471                 return true;
12472
12473         if (!clock1 || !clock2)
12474                 return false;
12475
12476         diff = abs(clock1 - clock2);
12477
12478         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12479                 return true;
12480
12481         return false;
12482 }
12483
12484 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12485         list_for_each_entry((intel_crtc), \
12486                             &(dev)->mode_config.crtc_list, \
12487                             base.head) \
12488                 if (mask & (1 <<(intel_crtc)->pipe))
12489
12490 static bool
12491 intel_compare_m_n(unsigned int m, unsigned int n,
12492                   unsigned int m2, unsigned int n2,
12493                   bool exact)
12494 {
12495         if (m == m2 && n == n2)
12496                 return true;
12497
12498         if (exact || !m || !n || !m2 || !n2)
12499                 return false;
12500
12501         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12502
12503         if (m > m2) {
12504                 while (m > m2) {
12505                         m2 <<= 1;
12506                         n2 <<= 1;
12507                 }
12508         } else if (m < m2) {
12509                 while (m < m2) {
12510                         m <<= 1;
12511                         n <<= 1;
12512                 }
12513         }
12514
12515         return m == m2 && n == n2;
12516 }
12517
12518 static bool
12519 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12520                        struct intel_link_m_n *m2_n2,
12521                        bool adjust)
12522 {
12523         if (m_n->tu == m2_n2->tu &&
12524             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12525                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12526             intel_compare_m_n(m_n->link_m, m_n->link_n,
12527                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12528                 if (adjust)
12529                         *m2_n2 = *m_n;
12530
12531                 return true;
12532         }
12533
12534         return false;
12535 }
12536
12537 static bool
12538 intel_pipe_config_compare(struct drm_device *dev,
12539                           struct intel_crtc_state *current_config,
12540                           struct intel_crtc_state *pipe_config,
12541                           bool adjust)
12542 {
12543         bool ret = true;
12544
12545 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12546         do { \
12547                 if (!adjust) \
12548                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12549                 else \
12550                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12551         } while (0)
12552
12553 #define PIPE_CONF_CHECK_X(name) \
12554         if (current_config->name != pipe_config->name) { \
12555                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12556                           "(expected 0x%08x, found 0x%08x)\n", \
12557                           current_config->name, \
12558                           pipe_config->name); \
12559                 ret = false; \
12560         }
12561
12562 #define PIPE_CONF_CHECK_I(name) \
12563         if (current_config->name != pipe_config->name) { \
12564                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12565                           "(expected %i, found %i)\n", \
12566                           current_config->name, \
12567                           pipe_config->name); \
12568                 ret = false; \
12569         }
12570
12571 #define PIPE_CONF_CHECK_M_N(name) \
12572         if (!intel_compare_link_m_n(&current_config->name, \
12573                                     &pipe_config->name,\
12574                                     adjust)) { \
12575                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12576                           "(expected tu %i gmch %i/%i link %i/%i, " \
12577                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12578                           current_config->name.tu, \
12579                           current_config->name.gmch_m, \
12580                           current_config->name.gmch_n, \
12581                           current_config->name.link_m, \
12582                           current_config->name.link_n, \
12583                           pipe_config->name.tu, \
12584                           pipe_config->name.gmch_m, \
12585                           pipe_config->name.gmch_n, \
12586                           pipe_config->name.link_m, \
12587                           pipe_config->name.link_n); \
12588                 ret = false; \
12589         }
12590
12591 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12592         if (!intel_compare_link_m_n(&current_config->name, \
12593                                     &pipe_config->name, adjust) && \
12594             !intel_compare_link_m_n(&current_config->alt_name, \
12595                                     &pipe_config->name, adjust)) { \
12596                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12597                           "(expected tu %i gmch %i/%i link %i/%i, " \
12598                           "or tu %i gmch %i/%i link %i/%i, " \
12599                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12600                           current_config->name.tu, \
12601                           current_config->name.gmch_m, \
12602                           current_config->name.gmch_n, \
12603                           current_config->name.link_m, \
12604                           current_config->name.link_n, \
12605                           current_config->alt_name.tu, \
12606                           current_config->alt_name.gmch_m, \
12607                           current_config->alt_name.gmch_n, \
12608                           current_config->alt_name.link_m, \
12609                           current_config->alt_name.link_n, \
12610                           pipe_config->name.tu, \
12611                           pipe_config->name.gmch_m, \
12612                           pipe_config->name.gmch_n, \
12613                           pipe_config->name.link_m, \
12614                           pipe_config->name.link_n); \
12615                 ret = false; \
12616         }
12617
12618 /* This is required for BDW+ where there is only one set of registers for
12619  * switching between high and low RR.
12620  * This macro can be used whenever a comparison has to be made between one
12621  * hw state and multiple sw state variables.
12622  */
12623 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12624         if ((current_config->name != pipe_config->name) && \
12625                 (current_config->alt_name != pipe_config->name)) { \
12626                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12627                                   "(expected %i or %i, found %i)\n", \
12628                                   current_config->name, \
12629                                   current_config->alt_name, \
12630                                   pipe_config->name); \
12631                         ret = false; \
12632         }
12633
12634 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12635         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12636                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12637                           "(expected %i, found %i)\n", \
12638                           current_config->name & (mask), \
12639                           pipe_config->name & (mask)); \
12640                 ret = false; \
12641         }
12642
12643 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12644         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12645                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12646                           "(expected %i, found %i)\n", \
12647                           current_config->name, \
12648                           pipe_config->name); \
12649                 ret = false; \
12650         }
12651
12652 #define PIPE_CONF_QUIRK(quirk)  \
12653         ((current_config->quirks | pipe_config->quirks) & (quirk))
12654
12655         PIPE_CONF_CHECK_I(cpu_transcoder);
12656
12657         PIPE_CONF_CHECK_I(has_pch_encoder);
12658         PIPE_CONF_CHECK_I(fdi_lanes);
12659         PIPE_CONF_CHECK_M_N(fdi_m_n);
12660
12661         PIPE_CONF_CHECK_I(has_dp_encoder);
12662         PIPE_CONF_CHECK_I(lane_count);
12663
12664         if (INTEL_INFO(dev)->gen < 8) {
12665                 PIPE_CONF_CHECK_M_N(dp_m_n);
12666
12667                 PIPE_CONF_CHECK_I(has_drrs);
12668                 if (current_config->has_drrs)
12669                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12670         } else
12671                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12672
12673         PIPE_CONF_CHECK_I(has_dsi_encoder);
12674
12675         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12676         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12677         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12678         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12679         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12680         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12681
12682         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12683         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12684         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12685         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12686         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12687         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12688
12689         PIPE_CONF_CHECK_I(pixel_multiplier);
12690         PIPE_CONF_CHECK_I(has_hdmi_sink);
12691         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12692             IS_VALLEYVIEW(dev))
12693                 PIPE_CONF_CHECK_I(limited_color_range);
12694         PIPE_CONF_CHECK_I(has_infoframe);
12695
12696         PIPE_CONF_CHECK_I(has_audio);
12697
12698         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12699                               DRM_MODE_FLAG_INTERLACE);
12700
12701         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12702                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12703                                       DRM_MODE_FLAG_PHSYNC);
12704                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12705                                       DRM_MODE_FLAG_NHSYNC);
12706                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12707                                       DRM_MODE_FLAG_PVSYNC);
12708                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12709                                       DRM_MODE_FLAG_NVSYNC);
12710         }
12711
12712         PIPE_CONF_CHECK_X(gmch_pfit.control);
12713         /* pfit ratios are autocomputed by the hw on gen4+ */
12714         if (INTEL_INFO(dev)->gen < 4)
12715                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12716         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12717
12718         if (!adjust) {
12719                 PIPE_CONF_CHECK_I(pipe_src_w);
12720                 PIPE_CONF_CHECK_I(pipe_src_h);
12721
12722                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12723                 if (current_config->pch_pfit.enabled) {
12724                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12725                         PIPE_CONF_CHECK_X(pch_pfit.size);
12726                 }
12727
12728                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12729         }
12730
12731         /* BDW+ don't expose a synchronous way to read the state */
12732         if (IS_HASWELL(dev))
12733                 PIPE_CONF_CHECK_I(ips_enabled);
12734
12735         PIPE_CONF_CHECK_I(double_wide);
12736
12737         PIPE_CONF_CHECK_X(ddi_pll_sel);
12738
12739         PIPE_CONF_CHECK_I(shared_dpll);
12740         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12741         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12742         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12743         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12744         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12745         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12746         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12747         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12748         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12749
12750         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12751                 PIPE_CONF_CHECK_I(pipe_bpp);
12752
12753         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12754         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12755
12756 #undef PIPE_CONF_CHECK_X
12757 #undef PIPE_CONF_CHECK_I
12758 #undef PIPE_CONF_CHECK_I_ALT
12759 #undef PIPE_CONF_CHECK_FLAGS
12760 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12761 #undef PIPE_CONF_QUIRK
12762 #undef INTEL_ERR_OR_DBG_KMS
12763
12764         return ret;
12765 }
12766
12767 static void check_wm_state(struct drm_device *dev)
12768 {
12769         struct drm_i915_private *dev_priv = dev->dev_private;
12770         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12771         struct intel_crtc *intel_crtc;
12772         int plane;
12773
12774         if (INTEL_INFO(dev)->gen < 9)
12775                 return;
12776
12777         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12778         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12779
12780         for_each_intel_crtc(dev, intel_crtc) {
12781                 struct skl_ddb_entry *hw_entry, *sw_entry;
12782                 const enum pipe pipe = intel_crtc->pipe;
12783
12784                 if (!intel_crtc->active)
12785                         continue;
12786
12787                 /* planes */
12788                 for_each_plane(dev_priv, pipe, plane) {
12789                         hw_entry = &hw_ddb.plane[pipe][plane];
12790                         sw_entry = &sw_ddb->plane[pipe][plane];
12791
12792                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12793                                 continue;
12794
12795                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12796                                   "(expected (%u,%u), found (%u,%u))\n",
12797                                   pipe_name(pipe), plane + 1,
12798                                   sw_entry->start, sw_entry->end,
12799                                   hw_entry->start, hw_entry->end);
12800                 }
12801
12802                 /* cursor */
12803                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12804                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12805
12806                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12807                         continue;
12808
12809                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12810                           "(expected (%u,%u), found (%u,%u))\n",
12811                           pipe_name(pipe),
12812                           sw_entry->start, sw_entry->end,
12813                           hw_entry->start, hw_entry->end);
12814         }
12815 }
12816
12817 static void
12818 check_connector_state(struct drm_device *dev,
12819                       struct drm_atomic_state *old_state)
12820 {
12821         struct drm_connector_state *old_conn_state;
12822         struct drm_connector *connector;
12823         int i;
12824
12825         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12826                 struct drm_encoder *encoder = connector->encoder;
12827                 struct drm_connector_state *state = connector->state;
12828
12829                 /* This also checks the encoder/connector hw state with the
12830                  * ->get_hw_state callbacks. */
12831                 intel_connector_check_state(to_intel_connector(connector));
12832
12833                 I915_STATE_WARN(state->best_encoder != encoder,
12834                      "connector's atomic encoder doesn't match legacy encoder\n");
12835         }
12836 }
12837
12838 static void
12839 check_encoder_state(struct drm_device *dev)
12840 {
12841         struct intel_encoder *encoder;
12842         struct intel_connector *connector;
12843
12844         for_each_intel_encoder(dev, encoder) {
12845                 bool enabled = false;
12846                 enum pipe pipe;
12847
12848                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12849                               encoder->base.base.id,
12850                               encoder->base.name);
12851
12852                 for_each_intel_connector(dev, connector) {
12853                         if (connector->base.state->best_encoder != &encoder->base)
12854                                 continue;
12855                         enabled = true;
12856
12857                         I915_STATE_WARN(connector->base.state->crtc !=
12858                                         encoder->base.crtc,
12859                              "connector's crtc doesn't match encoder crtc\n");
12860                 }
12861
12862                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12863                      "encoder's enabled state mismatch "
12864                      "(expected %i, found %i)\n",
12865                      !!encoder->base.crtc, enabled);
12866
12867                 if (!encoder->base.crtc) {
12868                         bool active;
12869
12870                         active = encoder->get_hw_state(encoder, &pipe);
12871                         I915_STATE_WARN(active,
12872                              "encoder detached but still enabled on pipe %c.\n",
12873                              pipe_name(pipe));
12874                 }
12875         }
12876 }
12877
12878 static void
12879 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12880 {
12881         struct drm_i915_private *dev_priv = dev->dev_private;
12882         struct intel_encoder *encoder;
12883         struct drm_crtc_state *old_crtc_state;
12884         struct drm_crtc *crtc;
12885         int i;
12886
12887         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12888                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12889                 struct intel_crtc_state *pipe_config, *sw_config;
12890                 bool active;
12891
12892                 if (!needs_modeset(crtc->state) &&
12893                     !to_intel_crtc_state(crtc->state)->update_pipe)
12894                         continue;
12895
12896                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12897                 pipe_config = to_intel_crtc_state(old_crtc_state);
12898                 memset(pipe_config, 0, sizeof(*pipe_config));
12899                 pipe_config->base.crtc = crtc;
12900                 pipe_config->base.state = old_state;
12901
12902                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12903                               crtc->base.id);
12904
12905                 active = dev_priv->display.get_pipe_config(intel_crtc,
12906                                                            pipe_config);
12907
12908                 /* hw state is inconsistent with the pipe quirk */
12909                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12910                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12911                         active = crtc->state->active;
12912
12913                 I915_STATE_WARN(crtc->state->active != active,
12914                      "crtc active state doesn't match with hw state "
12915                      "(expected %i, found %i)\n", crtc->state->active, active);
12916
12917                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12918                      "transitional active state does not match atomic hw state "
12919                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12920
12921                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12922                         enum pipe pipe;
12923
12924                         active = encoder->get_hw_state(encoder, &pipe);
12925                         I915_STATE_WARN(active != crtc->state->active,
12926                                 "[ENCODER:%i] active %i with crtc active %i\n",
12927                                 encoder->base.base.id, active, crtc->state->active);
12928
12929                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12930                                         "Encoder connected to wrong pipe %c\n",
12931                                         pipe_name(pipe));
12932
12933                         if (active)
12934                                 encoder->get_config(encoder, pipe_config);
12935                 }
12936
12937                 if (!crtc->state->active)
12938                         continue;
12939
12940                 sw_config = to_intel_crtc_state(crtc->state);
12941                 if (!intel_pipe_config_compare(dev, sw_config,
12942                                                pipe_config, false)) {
12943                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12944                         intel_dump_pipe_config(intel_crtc, pipe_config,
12945                                                "[hw state]");
12946                         intel_dump_pipe_config(intel_crtc, sw_config,
12947                                                "[sw state]");
12948                 }
12949         }
12950 }
12951
12952 static void
12953 check_shared_dpll_state(struct drm_device *dev)
12954 {
12955         struct drm_i915_private *dev_priv = dev->dev_private;
12956         struct intel_crtc *crtc;
12957         struct intel_dpll_hw_state dpll_hw_state;
12958         int i;
12959
12960         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12961                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12962                 int enabled_crtcs = 0, active_crtcs = 0;
12963                 bool active;
12964
12965                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12966
12967                 DRM_DEBUG_KMS("%s\n", pll->name);
12968
12969                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12970
12971                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12972                      "more active pll users than references: %i vs %i\n",
12973                      pll->active, hweight32(pll->config.crtc_mask));
12974                 I915_STATE_WARN(pll->active && !pll->on,
12975                      "pll in active use but not on in sw tracking\n");
12976                 I915_STATE_WARN(pll->on && !pll->active,
12977                      "pll in on but not on in use in sw tracking\n");
12978                 I915_STATE_WARN(pll->on != active,
12979                      "pll on state mismatch (expected %i, found %i)\n",
12980                      pll->on, active);
12981
12982                 for_each_intel_crtc(dev, crtc) {
12983                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12984                                 enabled_crtcs++;
12985                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12986                                 active_crtcs++;
12987                 }
12988                 I915_STATE_WARN(pll->active != active_crtcs,
12989                      "pll active crtcs mismatch (expected %i, found %i)\n",
12990                      pll->active, active_crtcs);
12991                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12992                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12993                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12994
12995                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12996                                        sizeof(dpll_hw_state)),
12997                      "pll hw state mismatch\n");
12998         }
12999 }
13000
13001 static void
13002 intel_modeset_check_state(struct drm_device *dev,
13003                           struct drm_atomic_state *old_state)
13004 {
13005         check_wm_state(dev);
13006         check_connector_state(dev, old_state);
13007         check_encoder_state(dev);
13008         check_crtc_state(dev, old_state);
13009         check_shared_dpll_state(dev);
13010 }
13011
13012 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13013                                      int dotclock)
13014 {
13015         /*
13016          * FDI already provided one idea for the dotclock.
13017          * Yell if the encoder disagrees.
13018          */
13019         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13020              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13021              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13022 }
13023
13024 static void update_scanline_offset(struct intel_crtc *crtc)
13025 {
13026         struct drm_device *dev = crtc->base.dev;
13027
13028         /*
13029          * The scanline counter increments at the leading edge of hsync.
13030          *
13031          * On most platforms it starts counting from vtotal-1 on the
13032          * first active line. That means the scanline counter value is
13033          * always one less than what we would expect. Ie. just after
13034          * start of vblank, which also occurs at start of hsync (on the
13035          * last active line), the scanline counter will read vblank_start-1.
13036          *
13037          * On gen2 the scanline counter starts counting from 1 instead
13038          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13039          * to keep the value positive), instead of adding one.
13040          *
13041          * On HSW+ the behaviour of the scanline counter depends on the output
13042          * type. For DP ports it behaves like most other platforms, but on HDMI
13043          * there's an extra 1 line difference. So we need to add two instead of
13044          * one to the value.
13045          */
13046         if (IS_GEN2(dev)) {
13047                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13048                 int vtotal;
13049
13050                 vtotal = adjusted_mode->crtc_vtotal;
13051                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13052                         vtotal /= 2;
13053
13054                 crtc->scanline_offset = vtotal - 1;
13055         } else if (HAS_DDI(dev) &&
13056                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13057                 crtc->scanline_offset = 2;
13058         } else
13059                 crtc->scanline_offset = 1;
13060 }
13061
13062 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13063 {
13064         struct drm_device *dev = state->dev;
13065         struct drm_i915_private *dev_priv = to_i915(dev);
13066         struct intel_shared_dpll_config *shared_dpll = NULL;
13067         struct intel_crtc *intel_crtc;
13068         struct intel_crtc_state *intel_crtc_state;
13069         struct drm_crtc *crtc;
13070         struct drm_crtc_state *crtc_state;
13071         int i;
13072
13073         if (!dev_priv->display.crtc_compute_clock)
13074                 return;
13075
13076         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13077                 int dpll;
13078
13079                 intel_crtc = to_intel_crtc(crtc);
13080                 intel_crtc_state = to_intel_crtc_state(crtc_state);
13081                 dpll = intel_crtc_state->shared_dpll;
13082
13083                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13084                         continue;
13085
13086                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13087
13088                 if (!shared_dpll)
13089                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
13090
13091                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13092         }
13093 }
13094
13095 /*
13096  * This implements the workaround described in the "notes" section of the mode
13097  * set sequence documentation. When going from no pipes or single pipe to
13098  * multiple pipes, and planes are enabled after the pipe, we need to wait at
13099  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13100  */
13101 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13102 {
13103         struct drm_crtc_state *crtc_state;
13104         struct intel_crtc *intel_crtc;
13105         struct drm_crtc *crtc;
13106         struct intel_crtc_state *first_crtc_state = NULL;
13107         struct intel_crtc_state *other_crtc_state = NULL;
13108         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13109         int i;
13110
13111         /* look at all crtc's that are going to be enabled in during modeset */
13112         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13113                 intel_crtc = to_intel_crtc(crtc);
13114
13115                 if (!crtc_state->active || !needs_modeset(crtc_state))
13116                         continue;
13117
13118                 if (first_crtc_state) {
13119                         other_crtc_state = to_intel_crtc_state(crtc_state);
13120                         break;
13121                 } else {
13122                         first_crtc_state = to_intel_crtc_state(crtc_state);
13123                         first_pipe = intel_crtc->pipe;
13124                 }
13125         }
13126
13127         /* No workaround needed? */
13128         if (!first_crtc_state)
13129                 return 0;
13130
13131         /* w/a possibly needed, check how many crtc's are already enabled. */
13132         for_each_intel_crtc(state->dev, intel_crtc) {
13133                 struct intel_crtc_state *pipe_config;
13134
13135                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13136                 if (IS_ERR(pipe_config))
13137                         return PTR_ERR(pipe_config);
13138
13139                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13140
13141                 if (!pipe_config->base.active ||
13142                     needs_modeset(&pipe_config->base))
13143                         continue;
13144
13145                 /* 2 or more enabled crtcs means no need for w/a */
13146                 if (enabled_pipe != INVALID_PIPE)
13147                         return 0;
13148
13149                 enabled_pipe = intel_crtc->pipe;
13150         }
13151
13152         if (enabled_pipe != INVALID_PIPE)
13153                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13154         else if (other_crtc_state)
13155                 other_crtc_state->hsw_workaround_pipe = first_pipe;
13156
13157         return 0;
13158 }
13159
13160 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13161 {
13162         struct drm_crtc *crtc;
13163         struct drm_crtc_state *crtc_state;
13164         int ret = 0;
13165
13166         /* add all active pipes to the state */
13167         for_each_crtc(state->dev, crtc) {
13168                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13169                 if (IS_ERR(crtc_state))
13170                         return PTR_ERR(crtc_state);
13171
13172                 if (!crtc_state->active || needs_modeset(crtc_state))
13173                         continue;
13174
13175                 crtc_state->mode_changed = true;
13176
13177                 ret = drm_atomic_add_affected_connectors(state, crtc);
13178                 if (ret)
13179                         break;
13180
13181                 ret = drm_atomic_add_affected_planes(state, crtc);
13182                 if (ret)
13183                         break;
13184         }
13185
13186         return ret;
13187 }
13188
13189 static int intel_modeset_checks(struct drm_atomic_state *state)
13190 {
13191         struct drm_device *dev = state->dev;
13192         struct drm_i915_private *dev_priv = dev->dev_private;
13193         int ret;
13194
13195         if (!check_digital_port_conflicts(state)) {
13196                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13197                 return -EINVAL;
13198         }
13199
13200         /*
13201          * See if the config requires any additional preparation, e.g.
13202          * to adjust global state with pipes off.  We need to do this
13203          * here so we can get the modeset_pipe updated config for the new
13204          * mode set on this crtc.  For other crtcs we need to use the
13205          * adjusted_mode bits in the crtc directly.
13206          */
13207         if (dev_priv->display.modeset_calc_cdclk) {
13208                 unsigned int cdclk;
13209
13210                 ret = dev_priv->display.modeset_calc_cdclk(state);
13211
13212                 cdclk = to_intel_atomic_state(state)->cdclk;
13213                 if (!ret && cdclk != dev_priv->cdclk_freq)
13214                         ret = intel_modeset_all_pipes(state);
13215
13216                 if (ret < 0)
13217                         return ret;
13218         } else
13219                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13220
13221         intel_modeset_clear_plls(state);
13222
13223         if (IS_HASWELL(dev))
13224                 return haswell_mode_set_planes_workaround(state);
13225
13226         return 0;
13227 }
13228
13229 /*
13230  * Handle calculation of various watermark data at the end of the atomic check
13231  * phase.  The code here should be run after the per-crtc and per-plane 'check'
13232  * handlers to ensure that all derived state has been updated.
13233  */
13234 static void calc_watermark_data(struct drm_atomic_state *state)
13235 {
13236         struct drm_device *dev = state->dev;
13237         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13238         struct drm_crtc *crtc;
13239         struct drm_crtc_state *cstate;
13240         struct drm_plane *plane;
13241         struct drm_plane_state *pstate;
13242
13243         /*
13244          * Calculate watermark configuration details now that derived
13245          * plane/crtc state is all properly updated.
13246          */
13247         drm_for_each_crtc(crtc, dev) {
13248                 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13249                         crtc->state;
13250
13251                 if (cstate->active)
13252                         intel_state->wm_config.num_pipes_active++;
13253         }
13254         drm_for_each_legacy_plane(plane, dev) {
13255                 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13256                         plane->state;
13257
13258                 if (!to_intel_plane_state(pstate)->visible)
13259                         continue;
13260
13261                 intel_state->wm_config.sprites_enabled = true;
13262                 if (pstate->crtc_w != pstate->src_w >> 16 ||
13263                     pstate->crtc_h != pstate->src_h >> 16)
13264                         intel_state->wm_config.sprites_scaled = true;
13265         }
13266 }
13267
13268 /**
13269  * intel_atomic_check - validate state object
13270  * @dev: drm device
13271  * @state: state to validate
13272  */
13273 static int intel_atomic_check(struct drm_device *dev,
13274                               struct drm_atomic_state *state)
13275 {
13276         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13277         struct drm_crtc *crtc;
13278         struct drm_crtc_state *crtc_state;
13279         int ret, i;
13280         bool any_ms = false;
13281
13282         ret = drm_atomic_helper_check_modeset(dev, state);
13283         if (ret)
13284                 return ret;
13285
13286         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13287                 struct intel_crtc_state *pipe_config =
13288                         to_intel_crtc_state(crtc_state);
13289
13290                 memset(&to_intel_crtc(crtc)->atomic, 0,
13291                        sizeof(struct intel_crtc_atomic_commit));
13292
13293                 /* Catch I915_MODE_FLAG_INHERITED */
13294                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13295                         crtc_state->mode_changed = true;
13296
13297                 if (!crtc_state->enable) {
13298                         if (needs_modeset(crtc_state))
13299                                 any_ms = true;
13300                         continue;
13301                 }
13302
13303                 if (!needs_modeset(crtc_state))
13304                         continue;
13305
13306                 /* FIXME: For only active_changed we shouldn't need to do any
13307                  * state recomputation at all. */
13308
13309                 ret = drm_atomic_add_affected_connectors(state, crtc);
13310                 if (ret)
13311                         return ret;
13312
13313                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13314                 if (ret)
13315                         return ret;
13316
13317                 if (i915.fastboot &&
13318                     intel_pipe_config_compare(state->dev,
13319                                         to_intel_crtc_state(crtc->state),
13320                                         pipe_config, true)) {
13321                         crtc_state->mode_changed = false;
13322                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13323                 }
13324
13325                 if (needs_modeset(crtc_state)) {
13326                         any_ms = true;
13327
13328                         ret = drm_atomic_add_affected_planes(state, crtc);
13329                         if (ret)
13330                                 return ret;
13331                 }
13332
13333                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13334                                        needs_modeset(crtc_state) ?
13335                                        "[modeset]" : "[fastset]");
13336         }
13337
13338         if (any_ms) {
13339                 ret = intel_modeset_checks(state);
13340
13341                 if (ret)
13342                         return ret;
13343         } else
13344                 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13345
13346         ret = drm_atomic_helper_check_planes(state->dev, state);
13347         if (ret)
13348                 return ret;
13349
13350         calc_watermark_data(state);
13351
13352         return 0;
13353 }
13354
13355 static int intel_atomic_prepare_commit(struct drm_device *dev,
13356                                        struct drm_atomic_state *state,
13357                                        bool async)
13358 {
13359         struct drm_i915_private *dev_priv = dev->dev_private;
13360         struct drm_plane_state *plane_state;
13361         struct drm_crtc_state *crtc_state;
13362         struct drm_plane *plane;
13363         struct drm_crtc *crtc;
13364         int i, ret;
13365
13366         if (async) {
13367                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13368                 return -EINVAL;
13369         }
13370
13371         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13372                 ret = intel_crtc_wait_for_pending_flips(crtc);
13373                 if (ret)
13374                         return ret;
13375
13376                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13377                         flush_workqueue(dev_priv->wq);
13378         }
13379
13380         ret = mutex_lock_interruptible(&dev->struct_mutex);
13381         if (ret)
13382                 return ret;
13383
13384         ret = drm_atomic_helper_prepare_planes(dev, state);
13385         if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13386                 u32 reset_counter;
13387
13388                 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13389                 mutex_unlock(&dev->struct_mutex);
13390
13391                 for_each_plane_in_state(state, plane, plane_state, i) {
13392                         struct intel_plane_state *intel_plane_state =
13393                                 to_intel_plane_state(plane_state);
13394
13395                         if (!intel_plane_state->wait_req)
13396                                 continue;
13397
13398                         ret = __i915_wait_request(intel_plane_state->wait_req,
13399                                                   reset_counter, true,
13400                                                   NULL, NULL);
13401
13402                         /* Swallow -EIO errors to allow updates during hw lockup. */
13403                         if (ret == -EIO)
13404                                 ret = 0;
13405
13406                         if (ret)
13407                                 break;
13408                 }
13409
13410                 if (!ret)
13411                         return 0;
13412
13413                 mutex_lock(&dev->struct_mutex);
13414                 drm_atomic_helper_cleanup_planes(dev, state);
13415         }
13416
13417         mutex_unlock(&dev->struct_mutex);
13418         return ret;
13419 }
13420
13421 /**
13422  * intel_atomic_commit - commit validated state object
13423  * @dev: DRM device
13424  * @state: the top-level driver state object
13425  * @async: asynchronous commit
13426  *
13427  * This function commits a top-level state object that has been validated
13428  * with drm_atomic_helper_check().
13429  *
13430  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13431  * we can only handle plane-related operations and do not yet support
13432  * asynchronous commit.
13433  *
13434  * RETURNS
13435  * Zero for success or -errno.
13436  */
13437 static int intel_atomic_commit(struct drm_device *dev,
13438                                struct drm_atomic_state *state,
13439                                bool async)
13440 {
13441         struct drm_i915_private *dev_priv = dev->dev_private;
13442         struct drm_crtc_state *crtc_state;
13443         struct drm_crtc *crtc;
13444         int ret = 0;
13445         int i;
13446         bool any_ms = false;
13447
13448         ret = intel_atomic_prepare_commit(dev, state, async);
13449         if (ret) {
13450                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13451                 return ret;
13452         }
13453
13454         drm_atomic_helper_swap_state(dev, state);
13455         dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13456
13457         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13458                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13459
13460                 if (!needs_modeset(crtc->state))
13461                         continue;
13462
13463                 any_ms = true;
13464                 intel_pre_plane_update(intel_crtc);
13465
13466                 if (crtc_state->active) {
13467                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13468                         dev_priv->display.crtc_disable(crtc);
13469                         intel_crtc->active = false;
13470                         intel_disable_shared_dpll(intel_crtc);
13471
13472                         /*
13473                          * Underruns don't always raise
13474                          * interrupts, so check manually.
13475                          */
13476                         intel_check_cpu_fifo_underruns(dev_priv);
13477                         intel_check_pch_fifo_underruns(dev_priv);
13478
13479                         if (!crtc->state->active)
13480                                 intel_update_watermarks(crtc);
13481                 }
13482         }
13483
13484         /* Only after disabling all output pipelines that will be changed can we
13485          * update the the output configuration. */
13486         intel_modeset_update_crtc_state(state);
13487
13488         if (any_ms) {
13489                 intel_shared_dpll_commit(state);
13490
13491                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13492                 modeset_update_crtc_power_domains(state);
13493         }
13494
13495         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13496         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13497                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13498                 bool modeset = needs_modeset(crtc->state);
13499                 bool update_pipe = !modeset &&
13500                         to_intel_crtc_state(crtc->state)->update_pipe;
13501                 unsigned long put_domains = 0;
13502
13503                 if (modeset)
13504                         intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13505
13506                 if (modeset && crtc->state->active) {
13507                         update_scanline_offset(to_intel_crtc(crtc));
13508                         dev_priv->display.crtc_enable(crtc);
13509                 }
13510
13511                 if (update_pipe) {
13512                         put_domains = modeset_get_crtc_power_domains(crtc);
13513
13514                         /* make sure intel_modeset_check_state runs */
13515                         any_ms = true;
13516                 }
13517
13518                 if (!modeset)
13519                         intel_pre_plane_update(intel_crtc);
13520
13521                 if (crtc->state->active &&
13522                     (crtc->state->planes_changed || update_pipe))
13523                         drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13524
13525                 if (put_domains)
13526                         modeset_put_power_domains(dev_priv, put_domains);
13527
13528                 intel_post_plane_update(intel_crtc);
13529
13530                 if (modeset)
13531                         intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13532         }
13533
13534         /* FIXME: add subpixel order */
13535
13536         drm_atomic_helper_wait_for_vblanks(dev, state);
13537
13538         mutex_lock(&dev->struct_mutex);
13539         drm_atomic_helper_cleanup_planes(dev, state);
13540         mutex_unlock(&dev->struct_mutex);
13541
13542         if (any_ms)
13543                 intel_modeset_check_state(dev, state);
13544
13545         drm_atomic_state_free(state);
13546
13547         return 0;
13548 }
13549
13550 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13551 {
13552         struct drm_device *dev = crtc->dev;
13553         struct drm_atomic_state *state;
13554         struct drm_crtc_state *crtc_state;
13555         int ret;
13556
13557         state = drm_atomic_state_alloc(dev);
13558         if (!state) {
13559                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13560                               crtc->base.id);
13561                 return;
13562         }
13563
13564         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13565
13566 retry:
13567         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13568         ret = PTR_ERR_OR_ZERO(crtc_state);
13569         if (!ret) {
13570                 if (!crtc_state->active)
13571                         goto out;
13572
13573                 crtc_state->mode_changed = true;
13574                 ret = drm_atomic_commit(state);
13575         }
13576
13577         if (ret == -EDEADLK) {
13578                 drm_atomic_state_clear(state);
13579                 drm_modeset_backoff(state->acquire_ctx);
13580                 goto retry;
13581         }
13582
13583         if (ret)
13584 out:
13585                 drm_atomic_state_free(state);
13586 }
13587
13588 #undef for_each_intel_crtc_masked
13589
13590 static const struct drm_crtc_funcs intel_crtc_funcs = {
13591         .gamma_set = intel_crtc_gamma_set,
13592         .set_config = drm_atomic_helper_set_config,
13593         .destroy = intel_crtc_destroy,
13594         .page_flip = intel_crtc_page_flip,
13595         .atomic_duplicate_state = intel_crtc_duplicate_state,
13596         .atomic_destroy_state = intel_crtc_destroy_state,
13597 };
13598
13599 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13600                                       struct intel_shared_dpll *pll,
13601                                       struct intel_dpll_hw_state *hw_state)
13602 {
13603         uint32_t val;
13604
13605         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13606                 return false;
13607
13608         val = I915_READ(PCH_DPLL(pll->id));
13609         hw_state->dpll = val;
13610         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13611         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13612
13613         return val & DPLL_VCO_ENABLE;
13614 }
13615
13616 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13617                                   struct intel_shared_dpll *pll)
13618 {
13619         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13620         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13621 }
13622
13623 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13624                                 struct intel_shared_dpll *pll)
13625 {
13626         /* PCH refclock must be enabled first */
13627         ibx_assert_pch_refclk_enabled(dev_priv);
13628
13629         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13630
13631         /* Wait for the clocks to stabilize. */
13632         POSTING_READ(PCH_DPLL(pll->id));
13633         udelay(150);
13634
13635         /* The pixel multiplier can only be updated once the
13636          * DPLL is enabled and the clocks are stable.
13637          *
13638          * So write it again.
13639          */
13640         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13641         POSTING_READ(PCH_DPLL(pll->id));
13642         udelay(200);
13643 }
13644
13645 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13646                                  struct intel_shared_dpll *pll)
13647 {
13648         struct drm_device *dev = dev_priv->dev;
13649         struct intel_crtc *crtc;
13650
13651         /* Make sure no transcoder isn't still depending on us. */
13652         for_each_intel_crtc(dev, crtc) {
13653                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13654                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13655         }
13656
13657         I915_WRITE(PCH_DPLL(pll->id), 0);
13658         POSTING_READ(PCH_DPLL(pll->id));
13659         udelay(200);
13660 }
13661
13662 static char *ibx_pch_dpll_names[] = {
13663         "PCH DPLL A",
13664         "PCH DPLL B",
13665 };
13666
13667 static void ibx_pch_dpll_init(struct drm_device *dev)
13668 {
13669         struct drm_i915_private *dev_priv = dev->dev_private;
13670         int i;
13671
13672         dev_priv->num_shared_dpll = 2;
13673
13674         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13675                 dev_priv->shared_dplls[i].id = i;
13676                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13677                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13678                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13679                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13680                 dev_priv->shared_dplls[i].get_hw_state =
13681                         ibx_pch_dpll_get_hw_state;
13682         }
13683 }
13684
13685 static void intel_shared_dpll_init(struct drm_device *dev)
13686 {
13687         struct drm_i915_private *dev_priv = dev->dev_private;
13688
13689         if (HAS_DDI(dev))
13690                 intel_ddi_pll_init(dev);
13691         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13692                 ibx_pch_dpll_init(dev);
13693         else
13694                 dev_priv->num_shared_dpll = 0;
13695
13696         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13697 }
13698
13699 /**
13700  * intel_prepare_plane_fb - Prepare fb for usage on plane
13701  * @plane: drm plane to prepare for
13702  * @fb: framebuffer to prepare for presentation
13703  *
13704  * Prepares a framebuffer for usage on a display plane.  Generally this
13705  * involves pinning the underlying object and updating the frontbuffer tracking
13706  * bits.  Some older platforms need special physical address handling for
13707  * cursor planes.
13708  *
13709  * Must be called with struct_mutex held.
13710  *
13711  * Returns 0 on success, negative error code on failure.
13712  */
13713 int
13714 intel_prepare_plane_fb(struct drm_plane *plane,
13715                        const struct drm_plane_state *new_state)
13716 {
13717         struct drm_device *dev = plane->dev;
13718         struct drm_framebuffer *fb = new_state->fb;
13719         struct intel_plane *intel_plane = to_intel_plane(plane);
13720         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13721         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13722         int ret = 0;
13723
13724         if (!obj && !old_obj)
13725                 return 0;
13726
13727         if (old_obj) {
13728                 struct drm_crtc_state *crtc_state =
13729                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13730
13731                 /* Big Hammer, we also need to ensure that any pending
13732                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13733                  * current scanout is retired before unpinning the old
13734                  * framebuffer. Note that we rely on userspace rendering
13735                  * into the buffer attached to the pipe they are waiting
13736                  * on. If not, userspace generates a GPU hang with IPEHR
13737                  * point to the MI_WAIT_FOR_EVENT.
13738                  *
13739                  * This should only fail upon a hung GPU, in which case we
13740                  * can safely continue.
13741                  */
13742                 if (needs_modeset(crtc_state))
13743                         ret = i915_gem_object_wait_rendering(old_obj, true);
13744
13745                 /* Swallow -EIO errors to allow updates during hw lockup. */
13746                 if (ret && ret != -EIO)
13747                         return ret;
13748         }
13749
13750         /* For framebuffer backed by dmabuf, wait for fence */
13751         if (obj && obj->base.dma_buf) {
13752                 ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13753                                                           false, true,
13754                                                           MAX_SCHEDULE_TIMEOUT);
13755                 if (ret == -ERESTARTSYS)
13756                         return ret;
13757
13758                 WARN_ON(ret < 0);
13759         }
13760
13761         if (!obj) {
13762                 ret = 0;
13763         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13764             INTEL_INFO(dev)->cursor_needs_physical) {
13765                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13766                 ret = i915_gem_object_attach_phys(obj, align);
13767                 if (ret)
13768                         DRM_DEBUG_KMS("failed to attach phys object\n");
13769         } else {
13770                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13771         }
13772
13773         if (ret == 0) {
13774                 if (obj) {
13775                         struct intel_plane_state *plane_state =
13776                                 to_intel_plane_state(new_state);
13777
13778                         i915_gem_request_assign(&plane_state->wait_req,
13779                                                 obj->last_write_req);
13780                 }
13781
13782                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13783         }
13784
13785         return ret;
13786 }
13787
13788 /**
13789  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13790  * @plane: drm plane to clean up for
13791  * @fb: old framebuffer that was on plane
13792  *
13793  * Cleans up a framebuffer that has just been removed from a plane.
13794  *
13795  * Must be called with struct_mutex held.
13796  */
13797 void
13798 intel_cleanup_plane_fb(struct drm_plane *plane,
13799                        const struct drm_plane_state *old_state)
13800 {
13801         struct drm_device *dev = plane->dev;
13802         struct intel_plane *intel_plane = to_intel_plane(plane);
13803         struct intel_plane_state *old_intel_state;
13804         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13805         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13806
13807         old_intel_state = to_intel_plane_state(old_state);
13808
13809         if (!obj && !old_obj)
13810                 return;
13811
13812         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13813             !INTEL_INFO(dev)->cursor_needs_physical))
13814                 intel_unpin_fb_obj(old_state->fb, old_state);
13815
13816         /* prepare_fb aborted? */
13817         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13818             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13819                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13820
13821         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13822
13823 }
13824
13825 int
13826 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13827 {
13828         int max_scale;
13829         struct drm_device *dev;
13830         struct drm_i915_private *dev_priv;
13831         int crtc_clock, cdclk;
13832
13833         if (!intel_crtc || !crtc_state)
13834                 return DRM_PLANE_HELPER_NO_SCALING;
13835
13836         dev = intel_crtc->base.dev;
13837         dev_priv = dev->dev_private;
13838         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13839         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13840
13841         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13842                 return DRM_PLANE_HELPER_NO_SCALING;
13843
13844         /*
13845          * skl max scale is lower of:
13846          *    close to 3 but not 3, -1 is for that purpose
13847          *            or
13848          *    cdclk/crtc_clock
13849          */
13850         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13851
13852         return max_scale;
13853 }
13854
13855 static int
13856 intel_check_primary_plane(struct drm_plane *plane,
13857                           struct intel_crtc_state *crtc_state,
13858                           struct intel_plane_state *state)
13859 {
13860         struct drm_crtc *crtc = state->base.crtc;
13861         struct drm_framebuffer *fb = state->base.fb;
13862         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13863         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13864         bool can_position = false;
13865
13866         /* use scaler when colorkey is not required */
13867         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13868             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13869                 min_scale = 1;
13870                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13871                 can_position = true;
13872         }
13873
13874         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13875                                              &state->dst, &state->clip,
13876                                              min_scale, max_scale,
13877                                              can_position, true,
13878                                              &state->visible);
13879 }
13880
13881 static void
13882 intel_commit_primary_plane(struct drm_plane *plane,
13883                            struct intel_plane_state *state)
13884 {
13885         struct drm_crtc *crtc = state->base.crtc;
13886         struct drm_framebuffer *fb = state->base.fb;
13887         struct drm_device *dev = plane->dev;
13888         struct drm_i915_private *dev_priv = dev->dev_private;
13889
13890         crtc = crtc ? crtc : plane->crtc;
13891
13892         dev_priv->display.update_primary_plane(crtc, fb,
13893                                                state->src.x1 >> 16,
13894                                                state->src.y1 >> 16);
13895 }
13896
13897 static void
13898 intel_disable_primary_plane(struct drm_plane *plane,
13899                             struct drm_crtc *crtc)
13900 {
13901         struct drm_device *dev = plane->dev;
13902         struct drm_i915_private *dev_priv = dev->dev_private;
13903
13904         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13905 }
13906
13907 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13908                                     struct drm_crtc_state *old_crtc_state)
13909 {
13910         struct drm_device *dev = crtc->dev;
13911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13912         struct intel_crtc_state *old_intel_state =
13913                 to_intel_crtc_state(old_crtc_state);
13914         bool modeset = needs_modeset(crtc->state);
13915
13916         /* Perform vblank evasion around commit operation */
13917         intel_pipe_update_start(intel_crtc);
13918
13919         if (modeset)
13920                 return;
13921
13922         if (to_intel_crtc_state(crtc->state)->update_pipe)
13923                 intel_update_pipe_config(intel_crtc, old_intel_state);
13924         else if (INTEL_INFO(dev)->gen >= 9)
13925                 skl_detach_scalers(intel_crtc);
13926 }
13927
13928 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13929                                      struct drm_crtc_state *old_crtc_state)
13930 {
13931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13932
13933         intel_pipe_update_end(intel_crtc);
13934 }
13935
13936 /**
13937  * intel_plane_destroy - destroy a plane
13938  * @plane: plane to destroy
13939  *
13940  * Common destruction function for all types of planes (primary, cursor,
13941  * sprite).
13942  */
13943 void intel_plane_destroy(struct drm_plane *plane)
13944 {
13945         struct intel_plane *intel_plane = to_intel_plane(plane);
13946         drm_plane_cleanup(plane);
13947         kfree(intel_plane);
13948 }
13949
13950 const struct drm_plane_funcs intel_plane_funcs = {
13951         .update_plane = drm_atomic_helper_update_plane,
13952         .disable_plane = drm_atomic_helper_disable_plane,
13953         .destroy = intel_plane_destroy,
13954         .set_property = drm_atomic_helper_plane_set_property,
13955         .atomic_get_property = intel_plane_atomic_get_property,
13956         .atomic_set_property = intel_plane_atomic_set_property,
13957         .atomic_duplicate_state = intel_plane_duplicate_state,
13958         .atomic_destroy_state = intel_plane_destroy_state,
13959
13960 };
13961
13962 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13963                                                     int pipe)
13964 {
13965         struct intel_plane *primary;
13966         struct intel_plane_state *state;
13967         const uint32_t *intel_primary_formats;
13968         unsigned int num_formats;
13969
13970         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13971         if (primary == NULL)
13972                 return NULL;
13973
13974         state = intel_create_plane_state(&primary->base);
13975         if (!state) {
13976                 kfree(primary);
13977                 return NULL;
13978         }
13979         primary->base.state = &state->base;
13980
13981         primary->can_scale = false;
13982         primary->max_downscale = 1;
13983         if (INTEL_INFO(dev)->gen >= 9) {
13984                 primary->can_scale = true;
13985                 state->scaler_id = -1;
13986         }
13987         primary->pipe = pipe;
13988         primary->plane = pipe;
13989         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13990         primary->check_plane = intel_check_primary_plane;
13991         primary->commit_plane = intel_commit_primary_plane;
13992         primary->disable_plane = intel_disable_primary_plane;
13993         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13994                 primary->plane = !pipe;
13995
13996         if (INTEL_INFO(dev)->gen >= 9) {
13997                 intel_primary_formats = skl_primary_formats;
13998                 num_formats = ARRAY_SIZE(skl_primary_formats);
13999         } else if (INTEL_INFO(dev)->gen >= 4) {
14000                 intel_primary_formats = i965_primary_formats;
14001                 num_formats = ARRAY_SIZE(i965_primary_formats);
14002         } else {
14003                 intel_primary_formats = i8xx_primary_formats;
14004                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14005         }
14006
14007         drm_universal_plane_init(dev, &primary->base, 0,
14008                                  &intel_plane_funcs,
14009                                  intel_primary_formats, num_formats,
14010                                  DRM_PLANE_TYPE_PRIMARY);
14011
14012         if (INTEL_INFO(dev)->gen >= 4)
14013                 intel_create_rotation_property(dev, primary);
14014
14015         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14016
14017         return &primary->base;
14018 }
14019
14020 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14021 {
14022         if (!dev->mode_config.rotation_property) {
14023                 unsigned long flags = BIT(DRM_ROTATE_0) |
14024                         BIT(DRM_ROTATE_180);
14025
14026                 if (INTEL_INFO(dev)->gen >= 9)
14027                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14028
14029                 dev->mode_config.rotation_property =
14030                         drm_mode_create_rotation_property(dev, flags);
14031         }
14032         if (dev->mode_config.rotation_property)
14033                 drm_object_attach_property(&plane->base.base,
14034                                 dev->mode_config.rotation_property,
14035                                 plane->base.state->rotation);
14036 }
14037
14038 static int
14039 intel_check_cursor_plane(struct drm_plane *plane,
14040                          struct intel_crtc_state *crtc_state,
14041                          struct intel_plane_state *state)
14042 {
14043         struct drm_crtc *crtc = crtc_state->base.crtc;
14044         struct drm_framebuffer *fb = state->base.fb;
14045         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14046         unsigned stride;
14047         int ret;
14048
14049         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14050                                             &state->dst, &state->clip,
14051                                             DRM_PLANE_HELPER_NO_SCALING,
14052                                             DRM_PLANE_HELPER_NO_SCALING,
14053                                             true, true, &state->visible);
14054         if (ret)
14055                 return ret;
14056
14057         /* if we want to turn off the cursor ignore width and height */
14058         if (!obj)
14059                 return 0;
14060
14061         /* Check for which cursor types we support */
14062         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14063                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14064                           state->base.crtc_w, state->base.crtc_h);
14065                 return -EINVAL;
14066         }
14067
14068         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14069         if (obj->base.size < stride * state->base.crtc_h) {
14070                 DRM_DEBUG_KMS("buffer is too small\n");
14071                 return -ENOMEM;
14072         }
14073
14074         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14075                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14076                 return -EINVAL;
14077         }
14078
14079         return 0;
14080 }
14081
14082 static void
14083 intel_disable_cursor_plane(struct drm_plane *plane,
14084                            struct drm_crtc *crtc)
14085 {
14086         intel_crtc_update_cursor(crtc, false);
14087 }
14088
14089 static void
14090 intel_commit_cursor_plane(struct drm_plane *plane,
14091                           struct intel_plane_state *state)
14092 {
14093         struct drm_crtc *crtc = state->base.crtc;
14094         struct drm_device *dev = plane->dev;
14095         struct intel_crtc *intel_crtc;
14096         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14097         uint32_t addr;
14098
14099         crtc = crtc ? crtc : plane->crtc;
14100         intel_crtc = to_intel_crtc(crtc);
14101
14102         if (intel_crtc->cursor_bo == obj)
14103                 goto update;
14104
14105         if (!obj)
14106                 addr = 0;
14107         else if (!INTEL_INFO(dev)->cursor_needs_physical)
14108                 addr = i915_gem_obj_ggtt_offset(obj);
14109         else
14110                 addr = obj->phys_handle->busaddr;
14111
14112         intel_crtc->cursor_addr = addr;
14113         intel_crtc->cursor_bo = obj;
14114
14115 update:
14116         intel_crtc_update_cursor(crtc, state->visible);
14117 }
14118
14119 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14120                                                    int pipe)
14121 {
14122         struct intel_plane *cursor;
14123         struct intel_plane_state *state;
14124
14125         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14126         if (cursor == NULL)
14127                 return NULL;
14128
14129         state = intel_create_plane_state(&cursor->base);
14130         if (!state) {
14131                 kfree(cursor);
14132                 return NULL;
14133         }
14134         cursor->base.state = &state->base;
14135
14136         cursor->can_scale = false;
14137         cursor->max_downscale = 1;
14138         cursor->pipe = pipe;
14139         cursor->plane = pipe;
14140         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14141         cursor->check_plane = intel_check_cursor_plane;
14142         cursor->commit_plane = intel_commit_cursor_plane;
14143         cursor->disable_plane = intel_disable_cursor_plane;
14144
14145         drm_universal_plane_init(dev, &cursor->base, 0,
14146                                  &intel_plane_funcs,
14147                                  intel_cursor_formats,
14148                                  ARRAY_SIZE(intel_cursor_formats),
14149                                  DRM_PLANE_TYPE_CURSOR);
14150
14151         if (INTEL_INFO(dev)->gen >= 4) {
14152                 if (!dev->mode_config.rotation_property)
14153                         dev->mode_config.rotation_property =
14154                                 drm_mode_create_rotation_property(dev,
14155                                                         BIT(DRM_ROTATE_0) |
14156                                                         BIT(DRM_ROTATE_180));
14157                 if (dev->mode_config.rotation_property)
14158                         drm_object_attach_property(&cursor->base.base,
14159                                 dev->mode_config.rotation_property,
14160                                 state->base.rotation);
14161         }
14162
14163         if (INTEL_INFO(dev)->gen >=9)
14164                 state->scaler_id = -1;
14165
14166         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14167
14168         return &cursor->base;
14169 }
14170
14171 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14172         struct intel_crtc_state *crtc_state)
14173 {
14174         int i;
14175         struct intel_scaler *intel_scaler;
14176         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14177
14178         for (i = 0; i < intel_crtc->num_scalers; i++) {
14179                 intel_scaler = &scaler_state->scalers[i];
14180                 intel_scaler->in_use = 0;
14181                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14182         }
14183
14184         scaler_state->scaler_id = -1;
14185 }
14186
14187 static void intel_crtc_init(struct drm_device *dev, int pipe)
14188 {
14189         struct drm_i915_private *dev_priv = dev->dev_private;
14190         struct intel_crtc *intel_crtc;
14191         struct intel_crtc_state *crtc_state = NULL;
14192         struct drm_plane *primary = NULL;
14193         struct drm_plane *cursor = NULL;
14194         int i, ret;
14195
14196         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14197         if (intel_crtc == NULL)
14198                 return;
14199
14200         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14201         if (!crtc_state)
14202                 goto fail;
14203         intel_crtc->config = crtc_state;
14204         intel_crtc->base.state = &crtc_state->base;
14205         crtc_state->base.crtc = &intel_crtc->base;
14206
14207         /* initialize shared scalers */
14208         if (INTEL_INFO(dev)->gen >= 9) {
14209                 if (pipe == PIPE_C)
14210                         intel_crtc->num_scalers = 1;
14211                 else
14212                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14213
14214                 skl_init_scalers(dev, intel_crtc, crtc_state);
14215         }
14216
14217         primary = intel_primary_plane_create(dev, pipe);
14218         if (!primary)
14219                 goto fail;
14220
14221         cursor = intel_cursor_plane_create(dev, pipe);
14222         if (!cursor)
14223                 goto fail;
14224
14225         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14226                                         cursor, &intel_crtc_funcs);
14227         if (ret)
14228                 goto fail;
14229
14230         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14231         for (i = 0; i < 256; i++) {
14232                 intel_crtc->lut_r[i] = i;
14233                 intel_crtc->lut_g[i] = i;
14234                 intel_crtc->lut_b[i] = i;
14235         }
14236
14237         /*
14238          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14239          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14240          */
14241         intel_crtc->pipe = pipe;
14242         intel_crtc->plane = pipe;
14243         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14244                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14245                 intel_crtc->plane = !pipe;
14246         }
14247
14248         intel_crtc->cursor_base = ~0;
14249         intel_crtc->cursor_cntl = ~0;
14250         intel_crtc->cursor_size = ~0;
14251
14252         intel_crtc->wm.cxsr_allowed = true;
14253
14254         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14255                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14256         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14257         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14258
14259         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14260
14261         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14262         return;
14263
14264 fail:
14265         if (primary)
14266                 drm_plane_cleanup(primary);
14267         if (cursor)
14268                 drm_plane_cleanup(cursor);
14269         kfree(crtc_state);
14270         kfree(intel_crtc);
14271 }
14272
14273 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14274 {
14275         struct drm_encoder *encoder = connector->base.encoder;
14276         struct drm_device *dev = connector->base.dev;
14277
14278         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14279
14280         if (!encoder || WARN_ON(!encoder->crtc))
14281                 return INVALID_PIPE;
14282
14283         return to_intel_crtc(encoder->crtc)->pipe;
14284 }
14285
14286 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14287                                 struct drm_file *file)
14288 {
14289         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14290         struct drm_crtc *drmmode_crtc;
14291         struct intel_crtc *crtc;
14292
14293         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14294
14295         if (!drmmode_crtc) {
14296                 DRM_ERROR("no such CRTC id\n");
14297                 return -ENOENT;
14298         }
14299
14300         crtc = to_intel_crtc(drmmode_crtc);
14301         pipe_from_crtc_id->pipe = crtc->pipe;
14302
14303         return 0;
14304 }
14305
14306 static int intel_encoder_clones(struct intel_encoder *encoder)
14307 {
14308         struct drm_device *dev = encoder->base.dev;
14309         struct intel_encoder *source_encoder;
14310         int index_mask = 0;
14311         int entry = 0;
14312
14313         for_each_intel_encoder(dev, source_encoder) {
14314                 if (encoders_cloneable(encoder, source_encoder))
14315                         index_mask |= (1 << entry);
14316
14317                 entry++;
14318         }
14319
14320         return index_mask;
14321 }
14322
14323 static bool has_edp_a(struct drm_device *dev)
14324 {
14325         struct drm_i915_private *dev_priv = dev->dev_private;
14326
14327         if (!IS_MOBILE(dev))
14328                 return false;
14329
14330         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14331                 return false;
14332
14333         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14334                 return false;
14335
14336         return true;
14337 }
14338
14339 static bool intel_crt_present(struct drm_device *dev)
14340 {
14341         struct drm_i915_private *dev_priv = dev->dev_private;
14342
14343         if (INTEL_INFO(dev)->gen >= 9)
14344                 return false;
14345
14346         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14347                 return false;
14348
14349         if (IS_CHERRYVIEW(dev))
14350                 return false;
14351
14352         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14353                 return false;
14354
14355         /* DDI E can't be used if DDI A requires 4 lanes */
14356         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14357                 return false;
14358
14359         if (!dev_priv->vbt.int_crt_support)
14360                 return false;
14361
14362         return true;
14363 }
14364
14365 static void intel_setup_outputs(struct drm_device *dev)
14366 {
14367         struct drm_i915_private *dev_priv = dev->dev_private;
14368         struct intel_encoder *encoder;
14369         bool dpd_is_edp = false;
14370
14371         intel_lvds_init(dev);
14372
14373         if (intel_crt_present(dev))
14374                 intel_crt_init(dev);
14375
14376         if (IS_BROXTON(dev)) {
14377                 /*
14378                  * FIXME: Broxton doesn't support port detection via the
14379                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14380                  * detect the ports.
14381                  */
14382                 intel_ddi_init(dev, PORT_A);
14383                 intel_ddi_init(dev, PORT_B);
14384                 intel_ddi_init(dev, PORT_C);
14385         } else if (HAS_DDI(dev)) {
14386                 int found;
14387
14388                 /*
14389                  * Haswell uses DDI functions to detect digital outputs.
14390                  * On SKL pre-D0 the strap isn't connected, so we assume
14391                  * it's there.
14392                  */
14393                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14394                 /* WaIgnoreDDIAStrap: skl */
14395                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14396                         intel_ddi_init(dev, PORT_A);
14397
14398                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14399                  * register */
14400                 found = I915_READ(SFUSE_STRAP);
14401
14402                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14403                         intel_ddi_init(dev, PORT_B);
14404                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14405                         intel_ddi_init(dev, PORT_C);
14406                 if (found & SFUSE_STRAP_DDID_DETECTED)
14407                         intel_ddi_init(dev, PORT_D);
14408                 /*
14409                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14410                  */
14411                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14412                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14413                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14414                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14415                         intel_ddi_init(dev, PORT_E);
14416
14417         } else if (HAS_PCH_SPLIT(dev)) {
14418                 int found;
14419                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14420
14421                 if (has_edp_a(dev))
14422                         intel_dp_init(dev, DP_A, PORT_A);
14423
14424                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14425                         /* PCH SDVOB multiplex with HDMIB */
14426                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14427                         if (!found)
14428                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14429                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14430                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14431                 }
14432
14433                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14434                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14435
14436                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14437                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14438
14439                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14440                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14441
14442                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14443                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14444         } else if (IS_VALLEYVIEW(dev)) {
14445                 /*
14446                  * The DP_DETECTED bit is the latched state of the DDC
14447                  * SDA pin at boot. However since eDP doesn't require DDC
14448                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14449                  * eDP ports may have been muxed to an alternate function.
14450                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14451                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14452                  * detect eDP ports.
14453                  */
14454                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14455                     !intel_dp_is_edp(dev, PORT_B))
14456                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14457                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14458                     intel_dp_is_edp(dev, PORT_B))
14459                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14460
14461                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14462                     !intel_dp_is_edp(dev, PORT_C))
14463                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14464                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14465                     intel_dp_is_edp(dev, PORT_C))
14466                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14467
14468                 if (IS_CHERRYVIEW(dev)) {
14469                         /* eDP not supported on port D, so don't check VBT */
14470                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14471                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14472                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14473                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14474                 }
14475
14476                 intel_dsi_init(dev);
14477         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14478                 bool found = false;
14479
14480                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14481                         DRM_DEBUG_KMS("probing SDVOB\n");
14482                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14483                         if (!found && IS_G4X(dev)) {
14484                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14485                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14486                         }
14487
14488                         if (!found && IS_G4X(dev))
14489                                 intel_dp_init(dev, DP_B, PORT_B);
14490                 }
14491
14492                 /* Before G4X SDVOC doesn't have its own detect register */
14493
14494                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14495                         DRM_DEBUG_KMS("probing SDVOC\n");
14496                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14497                 }
14498
14499                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14500
14501                         if (IS_G4X(dev)) {
14502                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14503                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14504                         }
14505                         if (IS_G4X(dev))
14506                                 intel_dp_init(dev, DP_C, PORT_C);
14507                 }
14508
14509                 if (IS_G4X(dev) &&
14510                     (I915_READ(DP_D) & DP_DETECTED))
14511                         intel_dp_init(dev, DP_D, PORT_D);
14512         } else if (IS_GEN2(dev))
14513                 intel_dvo_init(dev);
14514
14515         if (SUPPORTS_TV(dev))
14516                 intel_tv_init(dev);
14517
14518         intel_psr_init(dev);
14519
14520         for_each_intel_encoder(dev, encoder) {
14521                 encoder->base.possible_crtcs = encoder->crtc_mask;
14522                 encoder->base.possible_clones =
14523                         intel_encoder_clones(encoder);
14524         }
14525
14526         intel_init_pch_refclk(dev);
14527
14528         drm_helper_move_panel_connectors_to_head(dev);
14529 }
14530
14531 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14532 {
14533         struct drm_device *dev = fb->dev;
14534         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14535
14536         drm_framebuffer_cleanup(fb);
14537         mutex_lock(&dev->struct_mutex);
14538         WARN_ON(!intel_fb->obj->framebuffer_references--);
14539         drm_gem_object_unreference(&intel_fb->obj->base);
14540         mutex_unlock(&dev->struct_mutex);
14541         kfree(intel_fb);
14542 }
14543
14544 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14545                                                 struct drm_file *file,
14546                                                 unsigned int *handle)
14547 {
14548         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14549         struct drm_i915_gem_object *obj = intel_fb->obj;
14550
14551         if (obj->userptr.mm) {
14552                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14553                 return -EINVAL;
14554         }
14555
14556         return drm_gem_handle_create(file, &obj->base, handle);
14557 }
14558
14559 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14560                                         struct drm_file *file,
14561                                         unsigned flags, unsigned color,
14562                                         struct drm_clip_rect *clips,
14563                                         unsigned num_clips)
14564 {
14565         struct drm_device *dev = fb->dev;
14566         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14567         struct drm_i915_gem_object *obj = intel_fb->obj;
14568
14569         mutex_lock(&dev->struct_mutex);
14570         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14571         mutex_unlock(&dev->struct_mutex);
14572
14573         return 0;
14574 }
14575
14576 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14577         .destroy = intel_user_framebuffer_destroy,
14578         .create_handle = intel_user_framebuffer_create_handle,
14579         .dirty = intel_user_framebuffer_dirty,
14580 };
14581
14582 static
14583 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14584                          uint32_t pixel_format)
14585 {
14586         u32 gen = INTEL_INFO(dev)->gen;
14587
14588         if (gen >= 9) {
14589                 /* "The stride in bytes must not exceed the of the size of 8K
14590                  *  pixels and 32K bytes."
14591                  */
14592                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14593         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14594                 return 32*1024;
14595         } else if (gen >= 4) {
14596                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14597                         return 16*1024;
14598                 else
14599                         return 32*1024;
14600         } else if (gen >= 3) {
14601                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14602                         return 8*1024;
14603                 else
14604                         return 16*1024;
14605         } else {
14606                 /* XXX DSPC is limited to 4k tiled */
14607                 return 8*1024;
14608         }
14609 }
14610
14611 static int intel_framebuffer_init(struct drm_device *dev,
14612                                   struct intel_framebuffer *intel_fb,
14613                                   struct drm_mode_fb_cmd2 *mode_cmd,
14614                                   struct drm_i915_gem_object *obj)
14615 {
14616         unsigned int aligned_height;
14617         int ret;
14618         u32 pitch_limit, stride_alignment;
14619
14620         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14621
14622         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14623                 /* Enforce that fb modifier and tiling mode match, but only for
14624                  * X-tiled. This is needed for FBC. */
14625                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14626                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14627                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14628                         return -EINVAL;
14629                 }
14630         } else {
14631                 if (obj->tiling_mode == I915_TILING_X)
14632                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14633                 else if (obj->tiling_mode == I915_TILING_Y) {
14634                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14635                         return -EINVAL;
14636                 }
14637         }
14638
14639         /* Passed in modifier sanity checking. */
14640         switch (mode_cmd->modifier[0]) {
14641         case I915_FORMAT_MOD_Y_TILED:
14642         case I915_FORMAT_MOD_Yf_TILED:
14643                 if (INTEL_INFO(dev)->gen < 9) {
14644                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14645                                   mode_cmd->modifier[0]);
14646                         return -EINVAL;
14647                 }
14648         case DRM_FORMAT_MOD_NONE:
14649         case I915_FORMAT_MOD_X_TILED:
14650                 break;
14651         default:
14652                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14653                           mode_cmd->modifier[0]);
14654                 return -EINVAL;
14655         }
14656
14657         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14658                                                      mode_cmd->pixel_format);
14659         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14660                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14661                           mode_cmd->pitches[0], stride_alignment);
14662                 return -EINVAL;
14663         }
14664
14665         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14666                                            mode_cmd->pixel_format);
14667         if (mode_cmd->pitches[0] > pitch_limit) {
14668                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14669                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14670                           "tiled" : "linear",
14671                           mode_cmd->pitches[0], pitch_limit);
14672                 return -EINVAL;
14673         }
14674
14675         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14676             mode_cmd->pitches[0] != obj->stride) {
14677                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14678                           mode_cmd->pitches[0], obj->stride);
14679                 return -EINVAL;
14680         }
14681
14682         /* Reject formats not supported by any plane early. */
14683         switch (mode_cmd->pixel_format) {
14684         case DRM_FORMAT_C8:
14685         case DRM_FORMAT_RGB565:
14686         case DRM_FORMAT_XRGB8888:
14687         case DRM_FORMAT_ARGB8888:
14688                 break;
14689         case DRM_FORMAT_XRGB1555:
14690                 if (INTEL_INFO(dev)->gen > 3) {
14691                         DRM_DEBUG("unsupported pixel format: %s\n",
14692                                   drm_get_format_name(mode_cmd->pixel_format));
14693                         return -EINVAL;
14694                 }
14695                 break;
14696         case DRM_FORMAT_ABGR8888:
14697                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14698                         DRM_DEBUG("unsupported pixel format: %s\n",
14699                                   drm_get_format_name(mode_cmd->pixel_format));
14700                         return -EINVAL;
14701                 }
14702                 break;
14703         case DRM_FORMAT_XBGR8888:
14704         case DRM_FORMAT_XRGB2101010:
14705         case DRM_FORMAT_XBGR2101010:
14706                 if (INTEL_INFO(dev)->gen < 4) {
14707                         DRM_DEBUG("unsupported pixel format: %s\n",
14708                                   drm_get_format_name(mode_cmd->pixel_format));
14709                         return -EINVAL;
14710                 }
14711                 break;
14712         case DRM_FORMAT_ABGR2101010:
14713                 if (!IS_VALLEYVIEW(dev)) {
14714                         DRM_DEBUG("unsupported pixel format: %s\n",
14715                                   drm_get_format_name(mode_cmd->pixel_format));
14716                         return -EINVAL;
14717                 }
14718                 break;
14719         case DRM_FORMAT_YUYV:
14720         case DRM_FORMAT_UYVY:
14721         case DRM_FORMAT_YVYU:
14722         case DRM_FORMAT_VYUY:
14723                 if (INTEL_INFO(dev)->gen < 5) {
14724                         DRM_DEBUG("unsupported pixel format: %s\n",
14725                                   drm_get_format_name(mode_cmd->pixel_format));
14726                         return -EINVAL;
14727                 }
14728                 break;
14729         default:
14730                 DRM_DEBUG("unsupported pixel format: %s\n",
14731                           drm_get_format_name(mode_cmd->pixel_format));
14732                 return -EINVAL;
14733         }
14734
14735         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14736         if (mode_cmd->offsets[0] != 0)
14737                 return -EINVAL;
14738
14739         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14740                                                mode_cmd->pixel_format,
14741                                                mode_cmd->modifier[0]);
14742         /* FIXME drm helper for size checks (especially planar formats)? */
14743         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14744                 return -EINVAL;
14745
14746         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14747         intel_fb->obj = obj;
14748         intel_fb->obj->framebuffer_references++;
14749
14750         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14751         if (ret) {
14752                 DRM_ERROR("framebuffer init failed %d\n", ret);
14753                 return ret;
14754         }
14755
14756         return 0;
14757 }
14758
14759 static struct drm_framebuffer *
14760 intel_user_framebuffer_create(struct drm_device *dev,
14761                               struct drm_file *filp,
14762                               struct drm_mode_fb_cmd2 *user_mode_cmd)
14763 {
14764         struct drm_framebuffer *fb;
14765         struct drm_i915_gem_object *obj;
14766         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14767
14768         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14769                                                 mode_cmd.handles[0]));
14770         if (&obj->base == NULL)
14771                 return ERR_PTR(-ENOENT);
14772
14773         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14774         if (IS_ERR(fb))
14775                 drm_gem_object_unreference_unlocked(&obj->base);
14776
14777         return fb;
14778 }
14779
14780 #ifndef CONFIG_DRM_FBDEV_EMULATION
14781 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14782 {
14783 }
14784 #endif
14785
14786 static const struct drm_mode_config_funcs intel_mode_funcs = {
14787         .fb_create = intel_user_framebuffer_create,
14788         .output_poll_changed = intel_fbdev_output_poll_changed,
14789         .atomic_check = intel_atomic_check,
14790         .atomic_commit = intel_atomic_commit,
14791         .atomic_state_alloc = intel_atomic_state_alloc,
14792         .atomic_state_clear = intel_atomic_state_clear,
14793 };
14794
14795 /* Set up chip specific display functions */
14796 static void intel_init_display(struct drm_device *dev)
14797 {
14798         struct drm_i915_private *dev_priv = dev->dev_private;
14799
14800         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14801                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14802         else if (IS_CHERRYVIEW(dev))
14803                 dev_priv->display.find_dpll = chv_find_best_dpll;
14804         else if (IS_VALLEYVIEW(dev))
14805                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14806         else if (IS_PINEVIEW(dev))
14807                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14808         else
14809                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14810
14811         if (INTEL_INFO(dev)->gen >= 9) {
14812                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14813                 dev_priv->display.get_initial_plane_config =
14814                         skylake_get_initial_plane_config;
14815                 dev_priv->display.crtc_compute_clock =
14816                         haswell_crtc_compute_clock;
14817                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14818                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14819                 dev_priv->display.update_primary_plane =
14820                         skylake_update_primary_plane;
14821         } else if (HAS_DDI(dev)) {
14822                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14823                 dev_priv->display.get_initial_plane_config =
14824                         ironlake_get_initial_plane_config;
14825                 dev_priv->display.crtc_compute_clock =
14826                         haswell_crtc_compute_clock;
14827                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14828                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14829                 dev_priv->display.update_primary_plane =
14830                         ironlake_update_primary_plane;
14831         } else if (HAS_PCH_SPLIT(dev)) {
14832                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14833                 dev_priv->display.get_initial_plane_config =
14834                         ironlake_get_initial_plane_config;
14835                 dev_priv->display.crtc_compute_clock =
14836                         ironlake_crtc_compute_clock;
14837                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14838                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14839                 dev_priv->display.update_primary_plane =
14840                         ironlake_update_primary_plane;
14841         } else if (IS_VALLEYVIEW(dev)) {
14842                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14843                 dev_priv->display.get_initial_plane_config =
14844                         i9xx_get_initial_plane_config;
14845                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14846                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14847                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14848                 dev_priv->display.update_primary_plane =
14849                         i9xx_update_primary_plane;
14850         } else {
14851                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14852                 dev_priv->display.get_initial_plane_config =
14853                         i9xx_get_initial_plane_config;
14854                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14855                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14856                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14857                 dev_priv->display.update_primary_plane =
14858                         i9xx_update_primary_plane;
14859         }
14860
14861         /* Returns the core display clock speed */
14862         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14863                 dev_priv->display.get_display_clock_speed =
14864                         skylake_get_display_clock_speed;
14865         else if (IS_BROXTON(dev))
14866                 dev_priv->display.get_display_clock_speed =
14867                         broxton_get_display_clock_speed;
14868         else if (IS_BROADWELL(dev))
14869                 dev_priv->display.get_display_clock_speed =
14870                         broadwell_get_display_clock_speed;
14871         else if (IS_HASWELL(dev))
14872                 dev_priv->display.get_display_clock_speed =
14873                         haswell_get_display_clock_speed;
14874         else if (IS_VALLEYVIEW(dev))
14875                 dev_priv->display.get_display_clock_speed =
14876                         valleyview_get_display_clock_speed;
14877         else if (IS_GEN5(dev))
14878                 dev_priv->display.get_display_clock_speed =
14879                         ilk_get_display_clock_speed;
14880         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14881                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14882                 dev_priv->display.get_display_clock_speed =
14883                         i945_get_display_clock_speed;
14884         else if (IS_GM45(dev))
14885                 dev_priv->display.get_display_clock_speed =
14886                         gm45_get_display_clock_speed;
14887         else if (IS_CRESTLINE(dev))
14888                 dev_priv->display.get_display_clock_speed =
14889                         i965gm_get_display_clock_speed;
14890         else if (IS_PINEVIEW(dev))
14891                 dev_priv->display.get_display_clock_speed =
14892                         pnv_get_display_clock_speed;
14893         else if (IS_G33(dev) || IS_G4X(dev))
14894                 dev_priv->display.get_display_clock_speed =
14895                         g33_get_display_clock_speed;
14896         else if (IS_I915G(dev))
14897                 dev_priv->display.get_display_clock_speed =
14898                         i915_get_display_clock_speed;
14899         else if (IS_I945GM(dev) || IS_845G(dev))
14900                 dev_priv->display.get_display_clock_speed =
14901                         i9xx_misc_get_display_clock_speed;
14902         else if (IS_I915GM(dev))
14903                 dev_priv->display.get_display_clock_speed =
14904                         i915gm_get_display_clock_speed;
14905         else if (IS_I865G(dev))
14906                 dev_priv->display.get_display_clock_speed =
14907                         i865_get_display_clock_speed;
14908         else if (IS_I85X(dev))
14909                 dev_priv->display.get_display_clock_speed =
14910                         i85x_get_display_clock_speed;
14911         else { /* 830 */
14912                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14913                 dev_priv->display.get_display_clock_speed =
14914                         i830_get_display_clock_speed;
14915         }
14916
14917         if (IS_GEN5(dev)) {
14918                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14919         } else if (IS_GEN6(dev)) {
14920                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14921         } else if (IS_IVYBRIDGE(dev)) {
14922                 /* FIXME: detect B0+ stepping and use auto training */
14923                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14924         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14925                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14926                 if (IS_BROADWELL(dev)) {
14927                         dev_priv->display.modeset_commit_cdclk =
14928                                 broadwell_modeset_commit_cdclk;
14929                         dev_priv->display.modeset_calc_cdclk =
14930                                 broadwell_modeset_calc_cdclk;
14931                 }
14932         } else if (IS_VALLEYVIEW(dev)) {
14933                 dev_priv->display.modeset_commit_cdclk =
14934                         valleyview_modeset_commit_cdclk;
14935                 dev_priv->display.modeset_calc_cdclk =
14936                         valleyview_modeset_calc_cdclk;
14937         } else if (IS_BROXTON(dev)) {
14938                 dev_priv->display.modeset_commit_cdclk =
14939                         broxton_modeset_commit_cdclk;
14940                 dev_priv->display.modeset_calc_cdclk =
14941                         broxton_modeset_calc_cdclk;
14942         }
14943
14944         switch (INTEL_INFO(dev)->gen) {
14945         case 2:
14946                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14947                 break;
14948
14949         case 3:
14950                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14951                 break;
14952
14953         case 4:
14954         case 5:
14955                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14956                 break;
14957
14958         case 6:
14959                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14960                 break;
14961         case 7:
14962         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14963                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14964                 break;
14965         case 9:
14966                 /* Drop through - unsupported since execlist only. */
14967         default:
14968                 /* Default just returns -ENODEV to indicate unsupported */
14969                 dev_priv->display.queue_flip = intel_default_queue_flip;
14970         }
14971
14972         mutex_init(&dev_priv->pps_mutex);
14973 }
14974
14975 /*
14976  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14977  * resume, or other times.  This quirk makes sure that's the case for
14978  * affected systems.
14979  */
14980 static void quirk_pipea_force(struct drm_device *dev)
14981 {
14982         struct drm_i915_private *dev_priv = dev->dev_private;
14983
14984         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14985         DRM_INFO("applying pipe a force quirk\n");
14986 }
14987
14988 static void quirk_pipeb_force(struct drm_device *dev)
14989 {
14990         struct drm_i915_private *dev_priv = dev->dev_private;
14991
14992         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14993         DRM_INFO("applying pipe b force quirk\n");
14994 }
14995
14996 /*
14997  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14998  */
14999 static void quirk_ssc_force_disable(struct drm_device *dev)
15000 {
15001         struct drm_i915_private *dev_priv = dev->dev_private;
15002         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15003         DRM_INFO("applying lvds SSC disable quirk\n");
15004 }
15005
15006 /*
15007  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15008  * brightness value
15009  */
15010 static void quirk_invert_brightness(struct drm_device *dev)
15011 {
15012         struct drm_i915_private *dev_priv = dev->dev_private;
15013         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15014         DRM_INFO("applying inverted panel brightness quirk\n");
15015 }
15016
15017 /* Some VBT's incorrectly indicate no backlight is present */
15018 static void quirk_backlight_present(struct drm_device *dev)
15019 {
15020         struct drm_i915_private *dev_priv = dev->dev_private;
15021         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15022         DRM_INFO("applying backlight present quirk\n");
15023 }
15024
15025 struct intel_quirk {
15026         int device;
15027         int subsystem_vendor;
15028         int subsystem_device;
15029         void (*hook)(struct drm_device *dev);
15030 };
15031
15032 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15033 struct intel_dmi_quirk {
15034         void (*hook)(struct drm_device *dev);
15035         const struct dmi_system_id (*dmi_id_list)[];
15036 };
15037
15038 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15039 {
15040         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15041         return 1;
15042 }
15043
15044 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15045         {
15046                 .dmi_id_list = &(const struct dmi_system_id[]) {
15047                         {
15048                                 .callback = intel_dmi_reverse_brightness,
15049                                 .ident = "NCR Corporation",
15050                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15051                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
15052                                 },
15053                         },
15054                         { }  /* terminating entry */
15055                 },
15056                 .hook = quirk_invert_brightness,
15057         },
15058 };
15059
15060 static struct intel_quirk intel_quirks[] = {
15061         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15062         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15063
15064         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15065         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15066
15067         /* 830 needs to leave pipe A & dpll A up */
15068         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15069
15070         /* 830 needs to leave pipe B & dpll B up */
15071         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15072
15073         /* Lenovo U160 cannot use SSC on LVDS */
15074         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15075
15076         /* Sony Vaio Y cannot use SSC on LVDS */
15077         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15078
15079         /* Acer Aspire 5734Z must invert backlight brightness */
15080         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15081
15082         /* Acer/eMachines G725 */
15083         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15084
15085         /* Acer/eMachines e725 */
15086         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15087
15088         /* Acer/Packard Bell NCL20 */
15089         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15090
15091         /* Acer Aspire 4736Z */
15092         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15093
15094         /* Acer Aspire 5336 */
15095         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15096
15097         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15098         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15099
15100         /* Acer C720 Chromebook (Core i3 4005U) */
15101         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15102
15103         /* Apple Macbook 2,1 (Core 2 T7400) */
15104         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15105
15106         /* Apple Macbook 4,1 */
15107         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15108
15109         /* Toshiba CB35 Chromebook (Celeron 2955U) */
15110         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15111
15112         /* HP Chromebook 14 (Celeron 2955U) */
15113         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15114
15115         /* Dell Chromebook 11 */
15116         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15117
15118         /* Dell Chromebook 11 (2015 version) */
15119         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15120 };
15121
15122 static void intel_init_quirks(struct drm_device *dev)
15123 {
15124         struct pci_dev *d = dev->pdev;
15125         int i;
15126
15127         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15128                 struct intel_quirk *q = &intel_quirks[i];
15129
15130                 if (d->device == q->device &&
15131                     (d->subsystem_vendor == q->subsystem_vendor ||
15132                      q->subsystem_vendor == PCI_ANY_ID) &&
15133                     (d->subsystem_device == q->subsystem_device ||
15134                      q->subsystem_device == PCI_ANY_ID))
15135                         q->hook(dev);
15136         }
15137         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15138                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15139                         intel_dmi_quirks[i].hook(dev);
15140         }
15141 }
15142
15143 /* Disable the VGA plane that we never use */
15144 static void i915_disable_vga(struct drm_device *dev)
15145 {
15146         struct drm_i915_private *dev_priv = dev->dev_private;
15147         u8 sr1;
15148         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15149
15150         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15151         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15152         outb(SR01, VGA_SR_INDEX);
15153         sr1 = inb(VGA_SR_DATA);
15154         outb(sr1 | 1<<5, VGA_SR_DATA);
15155         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15156         udelay(300);
15157
15158         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15159         POSTING_READ(vga_reg);
15160 }
15161
15162 void intel_modeset_init_hw(struct drm_device *dev)
15163 {
15164         intel_update_cdclk(dev);
15165         intel_prepare_ddi(dev);
15166         intel_init_clock_gating(dev);
15167         intel_enable_gt_powersave(dev);
15168 }
15169
15170 void intel_modeset_init(struct drm_device *dev)
15171 {
15172         struct drm_i915_private *dev_priv = dev->dev_private;
15173         int sprite, ret;
15174         enum pipe pipe;
15175         struct intel_crtc *crtc;
15176
15177         drm_mode_config_init(dev);
15178
15179         dev->mode_config.min_width = 0;
15180         dev->mode_config.min_height = 0;
15181
15182         dev->mode_config.preferred_depth = 24;
15183         dev->mode_config.prefer_shadow = 1;
15184
15185         dev->mode_config.allow_fb_modifiers = true;
15186
15187         dev->mode_config.funcs = &intel_mode_funcs;
15188
15189         intel_init_quirks(dev);
15190
15191         intel_init_pm(dev);
15192
15193         if (INTEL_INFO(dev)->num_pipes == 0)
15194                 return;
15195
15196         /*
15197          * There may be no VBT; and if the BIOS enabled SSC we can
15198          * just keep using it to avoid unnecessary flicker.  Whereas if the
15199          * BIOS isn't using it, don't assume it will work even if the VBT
15200          * indicates as much.
15201          */
15202         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15203                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15204                                             DREF_SSC1_ENABLE);
15205
15206                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15207                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15208                                      bios_lvds_use_ssc ? "en" : "dis",
15209                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15210                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15211                 }
15212         }
15213
15214         intel_init_display(dev);
15215         intel_init_audio(dev);
15216
15217         if (IS_GEN2(dev)) {
15218                 dev->mode_config.max_width = 2048;
15219                 dev->mode_config.max_height = 2048;
15220         } else if (IS_GEN3(dev)) {
15221                 dev->mode_config.max_width = 4096;
15222                 dev->mode_config.max_height = 4096;
15223         } else {
15224                 dev->mode_config.max_width = 8192;
15225                 dev->mode_config.max_height = 8192;
15226         }
15227
15228         if (IS_845G(dev) || IS_I865G(dev)) {
15229                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15230                 dev->mode_config.cursor_height = 1023;
15231         } else if (IS_GEN2(dev)) {
15232                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15233                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15234         } else {
15235                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15236                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15237         }
15238
15239         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15240
15241         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15242                       INTEL_INFO(dev)->num_pipes,
15243                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15244
15245         for_each_pipe(dev_priv, pipe) {
15246                 intel_crtc_init(dev, pipe);
15247                 for_each_sprite(dev_priv, pipe, sprite) {
15248                         ret = intel_plane_init(dev, pipe, sprite);
15249                         if (ret)
15250                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15251                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15252                 }
15253         }
15254
15255         intel_update_czclk(dev_priv);
15256         intel_update_cdclk(dev);
15257
15258         intel_shared_dpll_init(dev);
15259
15260         /* Just disable it once at startup */
15261         i915_disable_vga(dev);
15262         intel_setup_outputs(dev);
15263
15264         drm_modeset_lock_all(dev);
15265         intel_modeset_setup_hw_state(dev);
15266         drm_modeset_unlock_all(dev);
15267
15268         for_each_intel_crtc(dev, crtc) {
15269                 struct intel_initial_plane_config plane_config = {};
15270
15271                 if (!crtc->active)
15272                         continue;
15273
15274                 /*
15275                  * Note that reserving the BIOS fb up front prevents us
15276                  * from stuffing other stolen allocations like the ring
15277                  * on top.  This prevents some ugliness at boot time, and
15278                  * can even allow for smooth boot transitions if the BIOS
15279                  * fb is large enough for the active pipe configuration.
15280                  */
15281                 dev_priv->display.get_initial_plane_config(crtc,
15282                                                            &plane_config);
15283
15284                 /*
15285                  * If the fb is shared between multiple heads, we'll
15286                  * just get the first one.
15287                  */
15288                 intel_find_initial_plane_obj(crtc, &plane_config);
15289         }
15290 }
15291
15292 static void intel_enable_pipe_a(struct drm_device *dev)
15293 {
15294         struct intel_connector *connector;
15295         struct drm_connector *crt = NULL;
15296         struct intel_load_detect_pipe load_detect_temp;
15297         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15298
15299         /* We can't just switch on the pipe A, we need to set things up with a
15300          * proper mode and output configuration. As a gross hack, enable pipe A
15301          * by enabling the load detect pipe once. */
15302         for_each_intel_connector(dev, connector) {
15303                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15304                         crt = &connector->base;
15305                         break;
15306                 }
15307         }
15308
15309         if (!crt)
15310                 return;
15311
15312         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15313                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15314 }
15315
15316 static bool
15317 intel_check_plane_mapping(struct intel_crtc *crtc)
15318 {
15319         struct drm_device *dev = crtc->base.dev;
15320         struct drm_i915_private *dev_priv = dev->dev_private;
15321         u32 val;
15322
15323         if (INTEL_INFO(dev)->num_pipes == 1)
15324                 return true;
15325
15326         val = I915_READ(DSPCNTR(!crtc->plane));
15327
15328         if ((val & DISPLAY_PLANE_ENABLE) &&
15329             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15330                 return false;
15331
15332         return true;
15333 }
15334
15335 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15336 {
15337         struct drm_device *dev = crtc->base.dev;
15338         struct intel_encoder *encoder;
15339
15340         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15341                 return true;
15342
15343         return false;
15344 }
15345
15346 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15347 {
15348         struct drm_device *dev = crtc->base.dev;
15349         struct drm_i915_private *dev_priv = dev->dev_private;
15350         i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15351
15352         /* Clear any frame start delays used for debugging left by the BIOS */
15353         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15354
15355         /* restore vblank interrupts to correct state */
15356         drm_crtc_vblank_reset(&crtc->base);
15357         if (crtc->active) {
15358                 struct intel_plane *plane;
15359
15360                 drm_crtc_vblank_on(&crtc->base);
15361
15362                 /* Disable everything but the primary plane */
15363                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15364                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15365                                 continue;
15366
15367                         plane->disable_plane(&plane->base, &crtc->base);
15368                 }
15369         }
15370
15371         /* We need to sanitize the plane -> pipe mapping first because this will
15372          * disable the crtc (and hence change the state) if it is wrong. Note
15373          * that gen4+ has a fixed plane -> pipe mapping.  */
15374         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15375                 bool plane;
15376
15377                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15378                               crtc->base.base.id);
15379
15380                 /* Pipe has the wrong plane attached and the plane is active.
15381                  * Temporarily change the plane mapping and disable everything
15382                  * ...  */
15383                 plane = crtc->plane;
15384                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15385                 crtc->plane = !plane;
15386                 intel_crtc_disable_noatomic(&crtc->base);
15387                 crtc->plane = plane;
15388         }
15389
15390         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15391             crtc->pipe == PIPE_A && !crtc->active) {
15392                 /* BIOS forgot to enable pipe A, this mostly happens after
15393                  * resume. Force-enable the pipe to fix this, the update_dpms
15394                  * call below we restore the pipe to the right state, but leave
15395                  * the required bits on. */
15396                 intel_enable_pipe_a(dev);
15397         }
15398
15399         /* Adjust the state of the output pipe according to whether we
15400          * have active connectors/encoders. */
15401         if (!intel_crtc_has_encoders(crtc))
15402                 intel_crtc_disable_noatomic(&crtc->base);
15403
15404         if (crtc->active != crtc->base.state->active) {
15405                 struct intel_encoder *encoder;
15406
15407                 /* This can happen either due to bugs in the get_hw_state
15408                  * functions or because of calls to intel_crtc_disable_noatomic,
15409                  * or because the pipe is force-enabled due to the
15410                  * pipe A quirk. */
15411                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15412                               crtc->base.base.id,
15413                               crtc->base.state->enable ? "enabled" : "disabled",
15414                               crtc->active ? "enabled" : "disabled");
15415
15416                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15417                 crtc->base.state->active = crtc->active;
15418                 crtc->base.enabled = crtc->active;
15419
15420                 /* Because we only establish the connector -> encoder ->
15421                  * crtc links if something is active, this means the
15422                  * crtc is now deactivated. Break the links. connector
15423                  * -> encoder links are only establish when things are
15424                  *  actually up, hence no need to break them. */
15425                 WARN_ON(crtc->active);
15426
15427                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15428                         encoder->base.crtc = NULL;
15429         }
15430
15431         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15432                 /*
15433                  * We start out with underrun reporting disabled to avoid races.
15434                  * For correct bookkeeping mark this on active crtcs.
15435                  *
15436                  * Also on gmch platforms we dont have any hardware bits to
15437                  * disable the underrun reporting. Which means we need to start
15438                  * out with underrun reporting disabled also on inactive pipes,
15439                  * since otherwise we'll complain about the garbage we read when
15440                  * e.g. coming up after runtime pm.
15441                  *
15442                  * No protection against concurrent access is required - at
15443                  * worst a fifo underrun happens which also sets this to false.
15444                  */
15445                 crtc->cpu_fifo_underrun_disabled = true;
15446                 crtc->pch_fifo_underrun_disabled = true;
15447         }
15448 }
15449
15450 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15451 {
15452         struct intel_connector *connector;
15453         struct drm_device *dev = encoder->base.dev;
15454         bool active = false;
15455
15456         /* We need to check both for a crtc link (meaning that the
15457          * encoder is active and trying to read from a pipe) and the
15458          * pipe itself being active. */
15459         bool has_active_crtc = encoder->base.crtc &&
15460                 to_intel_crtc(encoder->base.crtc)->active;
15461
15462         for_each_intel_connector(dev, connector) {
15463                 if (connector->base.encoder != &encoder->base)
15464                         continue;
15465
15466                 active = true;
15467                 break;
15468         }
15469
15470         if (active && !has_active_crtc) {
15471                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15472                               encoder->base.base.id,
15473                               encoder->base.name);
15474
15475                 /* Connector is active, but has no active pipe. This is
15476                  * fallout from our resume register restoring. Disable
15477                  * the encoder manually again. */
15478                 if (encoder->base.crtc) {
15479                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15480                                       encoder->base.base.id,
15481                                       encoder->base.name);
15482                         encoder->disable(encoder);
15483                         if (encoder->post_disable)
15484                                 encoder->post_disable(encoder);
15485                 }
15486                 encoder->base.crtc = NULL;
15487
15488                 /* Inconsistent output/port/pipe state happens presumably due to
15489                  * a bug in one of the get_hw_state functions. Or someplace else
15490                  * in our code, like the register restore mess on resume. Clamp
15491                  * things to off as a safer default. */
15492                 for_each_intel_connector(dev, connector) {
15493                         if (connector->encoder != encoder)
15494                                 continue;
15495                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15496                         connector->base.encoder = NULL;
15497                 }
15498         }
15499         /* Enabled encoders without active connectors will be fixed in
15500          * the crtc fixup. */
15501 }
15502
15503 void i915_redisable_vga_power_on(struct drm_device *dev)
15504 {
15505         struct drm_i915_private *dev_priv = dev->dev_private;
15506         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15507
15508         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15509                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15510                 i915_disable_vga(dev);
15511         }
15512 }
15513
15514 void i915_redisable_vga(struct drm_device *dev)
15515 {
15516         struct drm_i915_private *dev_priv = dev->dev_private;
15517
15518         /* This function can be called both from intel_modeset_setup_hw_state or
15519          * at a very early point in our resume sequence, where the power well
15520          * structures are not yet restored. Since this function is at a very
15521          * paranoid "someone might have enabled VGA while we were not looking"
15522          * level, just check if the power well is enabled instead of trying to
15523          * follow the "don't touch the power well if we don't need it" policy
15524          * the rest of the driver uses. */
15525         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15526                 return;
15527
15528         i915_redisable_vga_power_on(dev);
15529 }
15530
15531 static bool primary_get_hw_state(struct intel_plane *plane)
15532 {
15533         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15534
15535         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15536 }
15537
15538 /* FIXME read out full plane state for all planes */
15539 static void readout_plane_state(struct intel_crtc *crtc)
15540 {
15541         struct drm_plane *primary = crtc->base.primary;
15542         struct intel_plane_state *plane_state =
15543                 to_intel_plane_state(primary->state);
15544
15545         plane_state->visible = crtc->active &&
15546                 primary_get_hw_state(to_intel_plane(primary));
15547
15548         if (plane_state->visible)
15549                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15550 }
15551
15552 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15553 {
15554         struct drm_i915_private *dev_priv = dev->dev_private;
15555         enum pipe pipe;
15556         struct intel_crtc *crtc;
15557         struct intel_encoder *encoder;
15558         struct intel_connector *connector;
15559         int i;
15560
15561         for_each_intel_crtc(dev, crtc) {
15562                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15563                 memset(crtc->config, 0, sizeof(*crtc->config));
15564                 crtc->config->base.crtc = &crtc->base;
15565
15566                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15567                                                                  crtc->config);
15568
15569                 crtc->base.state->active = crtc->active;
15570                 crtc->base.enabled = crtc->active;
15571
15572                 readout_plane_state(crtc);
15573
15574                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15575                               crtc->base.base.id,
15576                               crtc->active ? "enabled" : "disabled");
15577         }
15578
15579         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15580                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15581
15582                 pll->on = pll->get_hw_state(dev_priv, pll,
15583                                             &pll->config.hw_state);
15584                 pll->active = 0;
15585                 pll->config.crtc_mask = 0;
15586                 for_each_intel_crtc(dev, crtc) {
15587                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15588                                 pll->active++;
15589                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15590                         }
15591                 }
15592
15593                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15594                               pll->name, pll->config.crtc_mask, pll->on);
15595
15596                 if (pll->config.crtc_mask)
15597                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15598         }
15599
15600         for_each_intel_encoder(dev, encoder) {
15601                 pipe = 0;
15602
15603                 if (encoder->get_hw_state(encoder, &pipe)) {
15604                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15605                         encoder->base.crtc = &crtc->base;
15606                         encoder->get_config(encoder, crtc->config);
15607                 } else {
15608                         encoder->base.crtc = NULL;
15609                 }
15610
15611                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15612                               encoder->base.base.id,
15613                               encoder->base.name,
15614                               encoder->base.crtc ? "enabled" : "disabled",
15615                               pipe_name(pipe));
15616         }
15617
15618         for_each_intel_connector(dev, connector) {
15619                 if (connector->get_hw_state(connector)) {
15620                         connector->base.dpms = DRM_MODE_DPMS_ON;
15621                         connector->base.encoder = &connector->encoder->base;
15622                 } else {
15623                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15624                         connector->base.encoder = NULL;
15625                 }
15626                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15627                               connector->base.base.id,
15628                               connector->base.name,
15629                               connector->base.encoder ? "enabled" : "disabled");
15630         }
15631
15632         for_each_intel_crtc(dev, crtc) {
15633                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15634
15635                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15636                 if (crtc->base.state->active) {
15637                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15638                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15639                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15640
15641                         /*
15642                          * The initial mode needs to be set in order to keep
15643                          * the atomic core happy. It wants a valid mode if the
15644                          * crtc's enabled, so we do the above call.
15645                          *
15646                          * At this point some state updated by the connectors
15647                          * in their ->detect() callback has not run yet, so
15648                          * no recalculation can be done yet.
15649                          *
15650                          * Even if we could do a recalculation and modeset
15651                          * right now it would cause a double modeset if
15652                          * fbdev or userspace chooses a different initial mode.
15653                          *
15654                          * If that happens, someone indicated they wanted a
15655                          * mode change, which means it's safe to do a full
15656                          * recalculation.
15657                          */
15658                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15659
15660                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15661                         update_scanline_offset(crtc);
15662                 }
15663         }
15664 }
15665
15666 /* Scan out the current hw modeset state,
15667  * and sanitizes it to the current state
15668  */
15669 static void
15670 intel_modeset_setup_hw_state(struct drm_device *dev)
15671 {
15672         struct drm_i915_private *dev_priv = dev->dev_private;
15673         enum pipe pipe;
15674         struct intel_crtc *crtc;
15675         struct intel_encoder *encoder;
15676         int i;
15677
15678         intel_modeset_readout_hw_state(dev);
15679
15680         /* HW state is read out, now we need to sanitize this mess. */
15681         for_each_intel_encoder(dev, encoder) {
15682                 intel_sanitize_encoder(encoder);
15683         }
15684
15685         for_each_pipe(dev_priv, pipe) {
15686                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15687                 intel_sanitize_crtc(crtc);
15688                 intel_dump_pipe_config(crtc, crtc->config,
15689                                        "[setup_hw_state]");
15690         }
15691
15692         intel_modeset_update_connector_atomic_state(dev);
15693
15694         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15695                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15696
15697                 if (!pll->on || pll->active)
15698                         continue;
15699
15700                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15701
15702                 pll->disable(dev_priv, pll);
15703                 pll->on = false;
15704         }
15705
15706         if (IS_VALLEYVIEW(dev))
15707                 vlv_wm_get_hw_state(dev);
15708         else if (IS_GEN9(dev))
15709                 skl_wm_get_hw_state(dev);
15710         else if (HAS_PCH_SPLIT(dev))
15711                 ilk_wm_get_hw_state(dev);
15712
15713         for_each_intel_crtc(dev, crtc) {
15714                 unsigned long put_domains;
15715
15716                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15717                 if (WARN_ON(put_domains))
15718                         modeset_put_power_domains(dev_priv, put_domains);
15719         }
15720         intel_display_set_init_power(dev_priv, false);
15721 }
15722
15723 void intel_display_resume(struct drm_device *dev)
15724 {
15725         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15726         struct intel_connector *conn;
15727         struct intel_plane *plane;
15728         struct drm_crtc *crtc;
15729         int ret;
15730
15731         if (!state)
15732                 return;
15733
15734         state->acquire_ctx = dev->mode_config.acquire_ctx;
15735
15736         /* preserve complete old state, including dpll */
15737         intel_atomic_get_shared_dpll_state(state);
15738
15739         for_each_crtc(dev, crtc) {
15740                 struct drm_crtc_state *crtc_state =
15741                         drm_atomic_get_crtc_state(state, crtc);
15742
15743                 ret = PTR_ERR_OR_ZERO(crtc_state);
15744                 if (ret)
15745                         goto err;
15746
15747                 /* force a restore */
15748                 crtc_state->mode_changed = true;
15749         }
15750
15751         for_each_intel_plane(dev, plane) {
15752                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15753                 if (ret)
15754                         goto err;
15755         }
15756
15757         for_each_intel_connector(dev, conn) {
15758                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15759                 if (ret)
15760                         goto err;
15761         }
15762
15763         intel_modeset_setup_hw_state(dev);
15764
15765         i915_redisable_vga(dev);
15766         ret = drm_atomic_commit(state);
15767         if (!ret)
15768                 return;
15769
15770 err:
15771         DRM_ERROR("Restoring old state failed with %i\n", ret);
15772         drm_atomic_state_free(state);
15773 }
15774
15775 void intel_modeset_gem_init(struct drm_device *dev)
15776 {
15777         struct drm_crtc *c;
15778         struct drm_i915_gem_object *obj;
15779         int ret;
15780
15781         mutex_lock(&dev->struct_mutex);
15782         intel_init_gt_powersave(dev);
15783         mutex_unlock(&dev->struct_mutex);
15784
15785         intel_modeset_init_hw(dev);
15786
15787         intel_setup_overlay(dev);
15788
15789         /*
15790          * Make sure any fbs we allocated at startup are properly
15791          * pinned & fenced.  When we do the allocation it's too early
15792          * for this.
15793          */
15794         for_each_crtc(dev, c) {
15795                 obj = intel_fb_obj(c->primary->fb);
15796                 if (obj == NULL)
15797                         continue;
15798
15799                 mutex_lock(&dev->struct_mutex);
15800                 ret = intel_pin_and_fence_fb_obj(c->primary,
15801                                                  c->primary->fb,
15802                                                  c->primary->state);
15803                 mutex_unlock(&dev->struct_mutex);
15804                 if (ret) {
15805                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15806                                   to_intel_crtc(c)->pipe);
15807                         drm_framebuffer_unreference(c->primary->fb);
15808                         c->primary->fb = NULL;
15809                         c->primary->crtc = c->primary->state->crtc = NULL;
15810                         update_state_fb(c->primary);
15811                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15812                 }
15813         }
15814
15815         intel_backlight_register(dev);
15816 }
15817
15818 void intel_connector_unregister(struct intel_connector *intel_connector)
15819 {
15820         struct drm_connector *connector = &intel_connector->base;
15821
15822         intel_panel_destroy_backlight(connector);
15823         drm_connector_unregister(connector);
15824 }
15825
15826 void intel_modeset_cleanup(struct drm_device *dev)
15827 {
15828         struct drm_i915_private *dev_priv = dev->dev_private;
15829         struct drm_connector *connector;
15830
15831         intel_disable_gt_powersave(dev);
15832
15833         intel_backlight_unregister(dev);
15834
15835         /*
15836          * Interrupts and polling as the first thing to avoid creating havoc.
15837          * Too much stuff here (turning of connectors, ...) would
15838          * experience fancy races otherwise.
15839          */
15840         intel_irq_uninstall(dev_priv);
15841
15842         /*
15843          * Due to the hpd irq storm handling the hotplug work can re-arm the
15844          * poll handlers. Hence disable polling after hpd handling is shut down.
15845          */
15846         drm_kms_helper_poll_fini(dev);
15847
15848         intel_unregister_dsm_handler();
15849
15850         intel_fbc_disable(dev_priv);
15851
15852         /* flush any delayed tasks or pending work */
15853         flush_scheduled_work();
15854
15855         /* destroy the backlight and sysfs files before encoders/connectors */
15856         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15857                 struct intel_connector *intel_connector;
15858
15859                 intel_connector = to_intel_connector(connector);
15860                 intel_connector->unregister(intel_connector);
15861         }
15862
15863         drm_mode_config_cleanup(dev);
15864
15865         intel_cleanup_overlay(dev);
15866
15867         mutex_lock(&dev->struct_mutex);
15868         intel_cleanup_gt_powersave(dev);
15869         mutex_unlock(&dev->struct_mutex);
15870 }
15871
15872 /*
15873  * Return which encoder is currently attached for connector.
15874  */
15875 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15876 {
15877         return &intel_attached_encoder(connector)->base;
15878 }
15879
15880 void intel_connector_attach_encoder(struct intel_connector *connector,
15881                                     struct intel_encoder *encoder)
15882 {
15883         connector->encoder = encoder;
15884         drm_mode_connector_attach_encoder(&connector->base,
15885                                           &encoder->base);
15886 }
15887
15888 /*
15889  * set vga decode state - true == enable VGA decode
15890  */
15891 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15892 {
15893         struct drm_i915_private *dev_priv = dev->dev_private;
15894         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15895         u16 gmch_ctrl;
15896
15897         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15898                 DRM_ERROR("failed to read control word\n");
15899                 return -EIO;
15900         }
15901
15902         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15903                 return 0;
15904
15905         if (state)
15906                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15907         else
15908                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15909
15910         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15911                 DRM_ERROR("failed to write control word\n");
15912                 return -EIO;
15913         }
15914
15915         return 0;
15916 }
15917
15918 struct intel_display_error_state {
15919
15920         u32 power_well_driver;
15921
15922         int num_transcoders;
15923
15924         struct intel_cursor_error_state {
15925                 u32 control;
15926                 u32 position;
15927                 u32 base;
15928                 u32 size;
15929         } cursor[I915_MAX_PIPES];
15930
15931         struct intel_pipe_error_state {
15932                 bool power_domain_on;
15933                 u32 source;
15934                 u32 stat;
15935         } pipe[I915_MAX_PIPES];
15936
15937         struct intel_plane_error_state {
15938                 u32 control;
15939                 u32 stride;
15940                 u32 size;
15941                 u32 pos;
15942                 u32 addr;
15943                 u32 surface;
15944                 u32 tile_offset;
15945         } plane[I915_MAX_PIPES];
15946
15947         struct intel_transcoder_error_state {
15948                 bool power_domain_on;
15949                 enum transcoder cpu_transcoder;
15950
15951                 u32 conf;
15952
15953                 u32 htotal;
15954                 u32 hblank;
15955                 u32 hsync;
15956                 u32 vtotal;
15957                 u32 vblank;
15958                 u32 vsync;
15959         } transcoder[4];
15960 };
15961
15962 struct intel_display_error_state *
15963 intel_display_capture_error_state(struct drm_device *dev)
15964 {
15965         struct drm_i915_private *dev_priv = dev->dev_private;
15966         struct intel_display_error_state *error;
15967         int transcoders[] = {
15968                 TRANSCODER_A,
15969                 TRANSCODER_B,
15970                 TRANSCODER_C,
15971                 TRANSCODER_EDP,
15972         };
15973         int i;
15974
15975         if (INTEL_INFO(dev)->num_pipes == 0)
15976                 return NULL;
15977
15978         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15979         if (error == NULL)
15980                 return NULL;
15981
15982         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15983                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15984
15985         for_each_pipe(dev_priv, i) {
15986                 error->pipe[i].power_domain_on =
15987                         __intel_display_power_is_enabled(dev_priv,
15988                                                          POWER_DOMAIN_PIPE(i));
15989                 if (!error->pipe[i].power_domain_on)
15990                         continue;
15991
15992                 error->cursor[i].control = I915_READ(CURCNTR(i));
15993                 error->cursor[i].position = I915_READ(CURPOS(i));
15994                 error->cursor[i].base = I915_READ(CURBASE(i));
15995
15996                 error->plane[i].control = I915_READ(DSPCNTR(i));
15997                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15998                 if (INTEL_INFO(dev)->gen <= 3) {
15999                         error->plane[i].size = I915_READ(DSPSIZE(i));
16000                         error->plane[i].pos = I915_READ(DSPPOS(i));
16001                 }
16002                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16003                         error->plane[i].addr = I915_READ(DSPADDR(i));
16004                 if (INTEL_INFO(dev)->gen >= 4) {
16005                         error->plane[i].surface = I915_READ(DSPSURF(i));
16006                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16007                 }
16008
16009                 error->pipe[i].source = I915_READ(PIPESRC(i));
16010
16011                 if (HAS_GMCH_DISPLAY(dev))
16012                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
16013         }
16014
16015         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16016         if (HAS_DDI(dev_priv->dev))
16017                 error->num_transcoders++; /* Account for eDP. */
16018
16019         for (i = 0; i < error->num_transcoders; i++) {
16020                 enum transcoder cpu_transcoder = transcoders[i];
16021
16022                 error->transcoder[i].power_domain_on =
16023                         __intel_display_power_is_enabled(dev_priv,
16024                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16025                 if (!error->transcoder[i].power_domain_on)
16026                         continue;
16027
16028                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16029
16030                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16031                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16032                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16033                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16034                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16035                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16036                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16037         }
16038
16039         return error;
16040 }
16041
16042 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16043
16044 void
16045 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16046                                 struct drm_device *dev,
16047                                 struct intel_display_error_state *error)
16048 {
16049         struct drm_i915_private *dev_priv = dev->dev_private;
16050         int i;
16051
16052         if (!error)
16053                 return;
16054
16055         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16056         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16057                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16058                            error->power_well_driver);
16059         for_each_pipe(dev_priv, i) {
16060                 err_printf(m, "Pipe [%d]:\n", i);
16061                 err_printf(m, "  Power: %s\n",
16062                            error->pipe[i].power_domain_on ? "on" : "off");
16063                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
16064                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
16065
16066                 err_printf(m, "Plane [%d]:\n", i);
16067                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
16068                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
16069                 if (INTEL_INFO(dev)->gen <= 3) {
16070                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
16071                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
16072                 }
16073                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16074                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
16075                 if (INTEL_INFO(dev)->gen >= 4) {
16076                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
16077                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
16078                 }
16079
16080                 err_printf(m, "Cursor [%d]:\n", i);
16081                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
16082                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
16083                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
16084         }
16085
16086         for (i = 0; i < error->num_transcoders; i++) {
16087                 err_printf(m, "CPU transcoder: %c\n",
16088                            transcoder_name(error->transcoder[i].cpu_transcoder));
16089                 err_printf(m, "  Power: %s\n",
16090                            error->transcoder[i].power_domain_on ? "on" : "off");
16091                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
16092                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
16093                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
16094                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
16095                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
16096                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
16097                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
16098         }
16099 }
16100
16101 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16102 {
16103         struct intel_crtc *crtc;
16104
16105         for_each_intel_crtc(dev, crtc) {
16106                 struct intel_unpin_work *work;
16107
16108                 spin_lock_irq(&dev->event_lock);
16109
16110                 work = crtc->unpin_work;
16111
16112                 if (work && work->event &&
16113                     work->event->base.file_priv == file) {
16114                         kfree(work->event);
16115                         work->event = NULL;
16116                 }
16117
16118                 spin_unlock_irq(&dev->event_lock);
16119         }
16120 }