drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_set_mode(struct drm_atomic_state *state);
  90 static int intel_framebuffer_init(struct drm_device *dev,
  91                                   struct intel_framebuffer *ifb,
  92                                   struct drm_mode_fb_cmd2 *mode_cmd,
  93                                   struct drm_i915_gem_object *obj);
  94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  97                                          struct intel_link_m_n *m_n,
  98                                          struct intel_link_m_n *m2_n2);
  99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 102 static void vlv_prepare_pll(struct intel_crtc *crtc,
 103                             const struct intel_crtc_state *pipe_config);
 104 static void chv_prepare_pll(struct intel_crtc *crtc,
 105                             const struct intel_crtc_state *pipe_config);
 106 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
 107 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
 108 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 109         struct intel_crtc_state *crtc_state);
 110 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 111                            int num_connectors);
 112
 113 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 114 {
 115         if (!connector->mst_port)
 116                 return connector->encoder;
 117         else
 118                 return &connector->mst_port->mst_encoders[pipe]->base;
 119 }
 120
 121 typedef struct {
 122         int     min, max;
 123 } intel_range_t;
 124
 125 typedef struct {
 126         int     dot_limit;
 127         int     p2_slow, p2_fast;
 128 } intel_p2_t;
 129
 130 typedef struct intel_limit intel_limit_t;
 131 struct intel_limit {
 132         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 133         intel_p2_t          p2;
 134 };
 135
 136 int
 137 intel_pch_rawclk(struct drm_device *dev)
 138 {
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140
 141         WARN_ON(!HAS_PCH_SPLIT(dev));
 142
 143         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 144 }
 145
 146 static inline u32 /* units of 100MHz */
 147 intel_fdi_link_freq(struct drm_device *dev)
 148 {
 149         if (IS_GEN5(dev)) {
 150                 struct drm_i915_private *dev_priv = dev->dev_private;
 151                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 152         } else
 153                 return 27;
 154 }
 155
 156 static const intel_limit_t intel_limits_i8xx_dac = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 2 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_dvo = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 2, .max = 33 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 4, .p2_fast = 4 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i8xx_lvds = {
 183         .dot = { .min = 25000, .max = 350000 },
 184         .vco = { .min = 908000, .max = 1512000 },
 185         .n = { .min = 2, .max = 16 },
 186         .m = { .min = 96, .max = 140 },
 187         .m1 = { .min = 18, .max = 26 },
 188         .m2 = { .min = 6, .max = 16 },
 189         .p = { .min = 4, .max = 128 },
 190         .p1 = { .min = 1, .max = 6 },
 191         .p2 = { .dot_limit = 165000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_sdvo = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 5, .max = 80 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 200000,
 205                 .p2_slow = 10, .p2_fast = 5 },
 206 };
 207
 208 static const intel_limit_t intel_limits_i9xx_lvds = {
 209         .dot = { .min = 20000, .max = 400000 },
 210         .vco = { .min = 1400000, .max = 2800000 },
 211         .n = { .min = 1, .max = 6 },
 212         .m = { .min = 70, .max = 120 },
 213         .m1 = { .min = 8, .max = 18 },
 214         .m2 = { .min = 3, .max = 7 },
 215         .p = { .min = 7, .max = 98 },
 216         .p1 = { .min = 1, .max = 8 },
 217         .p2 = { .dot_limit = 112000,
 218                 .p2_slow = 14, .p2_fast = 7 },
 219 };
 220
 221
 222 static const intel_limit_t intel_limits_g4x_sdvo = {
 223         .dot = { .min = 25000, .max = 270000 },
 224         .vco = { .min = 1750000, .max = 3500000},
 225         .n = { .min = 1, .max = 4 },
 226         .m = { .min = 104, .max = 138 },
 227         .m1 = { .min = 17, .max = 23 },
 228         .m2 = { .min = 5, .max = 11 },
 229         .p = { .min = 10, .max = 30 },
 230         .p1 = { .min = 1, .max = 3},
 231         .p2 = { .dot_limit = 270000,
 232                 .p2_slow = 10,
 233                 .p2_fast = 10
 234         },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_hdmi = {
 238         .dot = { .min = 22000, .max = 400000 },
 239         .vco = { .min = 1750000, .max = 3500000},
 240         .n = { .min = 1, .max = 4 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 16, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 5, .max = 80 },
 245         .p1 = { .min = 1, .max = 8},
 246         .p2 = { .dot_limit = 165000,
 247                 .p2_slow = 10, .p2_fast = 5 },
 248 };
 249
 250 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 251         .dot = { .min = 20000, .max = 115000 },
 252         .vco = { .min = 1750000, .max = 3500000 },
 253         .n = { .min = 1, .max = 3 },
 254         .m = { .min = 104, .max = 138 },
 255         .m1 = { .min = 17, .max = 23 },
 256         .m2 = { .min = 5, .max = 11 },
 257         .p = { .min = 28, .max = 112 },
 258         .p1 = { .min = 2, .max = 8 },
 259         .p2 = { .dot_limit = 0,
 260                 .p2_slow = 14, .p2_fast = 14
 261         },
 262 };
 263
 264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 265         .dot = { .min = 80000, .max = 224000 },
 266         .vco = { .min = 1750000, .max = 3500000 },
 267         .n = { .min = 1, .max = 3 },
 268         .m = { .min = 104, .max = 138 },
 269         .m1 = { .min = 17, .max = 23 },
 270         .m2 = { .min = 5, .max = 11 },
 271         .p = { .min = 14, .max = 42 },
 272         .p1 = { .min = 2, .max = 6 },
 273         .p2 = { .dot_limit = 0,
 274                 .p2_slow = 7, .p2_fast = 7
 275         },
 276 };
 277
 278 static const intel_limit_t intel_limits_pineview_sdvo = {
 279         .dot = { .min = 20000, .max = 400000},
 280         .vco = { .min = 1700000, .max = 3500000 },
 281         /* Pineview's Ncounter is a ring counter */
 282         .n = { .min = 3, .max = 6 },
 283         .m = { .min = 2, .max = 256 },
 284         /* Pineview only has one combined m divider, which we treat as m2. */
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 5, .max = 80 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 200000,
 290                 .p2_slow = 10, .p2_fast = 5 },
 291 };
 292
 293 static const intel_limit_t intel_limits_pineview_lvds = {
 294         .dot = { .min = 20000, .max = 400000 },
 295         .vco = { .min = 1700000, .max = 3500000 },
 296         .n = { .min = 3, .max = 6 },
 297         .m = { .min = 2, .max = 256 },
 298         .m1 = { .min = 0, .max = 0 },
 299         .m2 = { .min = 0, .max = 254 },
 300         .p = { .min = 7, .max = 112 },
 301         .p1 = { .min = 1, .max = 8 },
 302         .p2 = { .dot_limit = 112000,
 303                 .p2_slow = 14, .p2_fast = 14 },
 304 };
 305
 306 /* Ironlake / Sandybridge
 307  *
 308  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 309  * the range value for them is (actual_value - 2).
 310  */
 311 static const intel_limit_t intel_limits_ironlake_dac = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 5 },
 315         .m = { .min = 79, .max = 127 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 5, .max = 80 },
 319         .p1 = { .min = 1, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 10, .p2_fast = 5 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 118 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 28, .max = 112 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 14, .p2_fast = 14 },
 335 };
 336
 337 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 338         .dot = { .min = 25000, .max = 350000 },
 339         .vco = { .min = 1760000, .max = 3510000 },
 340         .n = { .min = 1, .max = 3 },
 341         .m = { .min = 79, .max = 127 },
 342         .m1 = { .min = 12, .max = 22 },
 343         .m2 = { .min = 5, .max = 9 },
 344         .p = { .min = 14, .max = 56 },
 345         .p1 = { .min = 2, .max = 8 },
 346         .p2 = { .dot_limit = 225000,
 347                 .p2_slow = 7, .p2_fast = 7 },
 348 };
 349
 350 /* LVDS 100mhz refclk limits. */
 351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 2 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 14, .p2_fast = 14 },
 362 };
 363
 364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 365         .dot = { .min = 25000, .max = 350000 },
 366         .vco = { .min = 1760000, .max = 3510000 },
 367         .n = { .min = 1, .max = 3 },
 368         .m = { .min = 79, .max = 126 },
 369         .m1 = { .min = 12, .max = 22 },
 370         .m2 = { .min = 5, .max = 9 },
 371         .p = { .min = 14, .max = 42 },
 372         .p1 = { .min = 2, .max = 6 },
 373         .p2 = { .dot_limit = 225000,
 374                 .p2_slow = 7, .p2_fast = 7 },
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv = {
 378          /*
 379           * These are the data rate limits (measured in fast clocks)
 380           * since those are the strictest limits we have. The fast
 381           * clock and actual rate limits are more relaxed, so checking
 382           * them would make no difference.
 383           */
 384         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 385         .vco = { .min = 4000000, .max = 6000000 },
 386         .n = { .min = 1, .max = 7 },
 387         .m1 = { .min = 2, .max = 3 },
 388         .m2 = { .min = 11, .max = 156 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 391 };
 392
 393 static const intel_limit_t intel_limits_chv = {
 394         /*
 395          * These are the data rate limits (measured in fast clocks)
 396          * since those are the strictest limits we have.  The fast
 397          * clock and actual rate limits are more relaxed, so checking
 398          * them would make no difference.
 399          */
 400         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 401         .vco = { .min = 4800000, .max = 6480000 },
 402         .n = { .min = 1, .max = 1 },
 403         .m1 = { .min = 2, .max = 2 },
 404         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 405         .p1 = { .min = 2, .max = 4 },
 406         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 407 };
 408
 409 static const intel_limit_t intel_limits_bxt = {
 410         /* FIXME: find real dot limits */
 411         .dot = { .min = 0, .max = INT_MAX },
 412         .vco = { .min = 4800000, .max = 6480000 },
 413         .n = { .min = 1, .max = 1 },
 414         .m1 = { .min = 2, .max = 2 },
 415         /* FIXME: find real m2 limits */
 416         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 417         .p1 = { .min = 2, .max = 4 },
 418         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 419 };
 420
 421 static void vlv_clock(int refclk, intel_clock_t *clock)
 422 {
 423         clock->m = clock->m1 * clock->m2;
 424         clock->p = clock->p1 * clock->p2;
 425         if (WARN_ON(clock->n == 0 || clock->p == 0))
 426                 return;
 427         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 428         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 429 }
 430
 431 static bool
 432 needs_modeset(struct drm_crtc_state *state)
 433 {
 434         return state->mode_changed || state->active_changed;
 435 }
 436
 437 /**
 438  * Returns whether any output on the specified pipe is of the specified type
 439  */
 440 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 441 {
 442         struct drm_device *dev = crtc->base.dev;
 443         struct intel_encoder *encoder;
 444
 445         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 446                 if (encoder->type == type)
 447                         return true;
 448
 449         return false;
 450 }
 451
 452 /**
 453  * Returns whether any output on the specified pipe will have the specified
 454  * type after a staged modeset is complete, i.e., the same as
 455  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 456  * encoder->crtc.
 457  */
 458 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 459                                       int type)
 460 {
 461         struct drm_atomic_state *state = crtc_state->base.state;
 462         struct drm_connector *connector;
 463         struct drm_connector_state *connector_state;
 464         struct intel_encoder *encoder;
 465         int i, num_connectors = 0;
 466
 467         for_each_connector_in_state(state, connector, connector_state, i) {
 468                 if (connector_state->crtc != crtc_state->base.crtc)
 469                         continue;
 470
 471                 num_connectors++;
 472
 473                 encoder = to_intel_encoder(connector_state->best_encoder);
 474                 if (encoder->type == type)
 475                         return true;
 476         }
 477
 478         WARN_ON(num_connectors == 0);
 479
 480         return false;
 481 }
 482
 483 static const intel_limit_t *
 484 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 485 {
 486         struct drm_device *dev = crtc_state->base.crtc->dev;
 487         const intel_limit_t *limit;
 488
 489         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 490                 if (intel_is_dual_link_lvds(dev)) {
 491                         if (refclk == 100000)
 492                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 493                         else
 494                                 limit = &intel_limits_ironlake_dual_lvds;
 495                 } else {
 496                         if (refclk == 100000)
 497                                 limit = &intel_limits_ironlake_single_lvds_100m;
 498                         else
 499                                 limit = &intel_limits_ironlake_single_lvds;
 500                 }
 501         } else
 502                 limit = &intel_limits_ironlake_dac;
 503
 504         return limit;
 505 }
 506
 507 static const intel_limit_t *
 508 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 509 {
 510         struct drm_device *dev = crtc_state->base.crtc->dev;
 511         const intel_limit_t *limit;
 512
 513         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 514                 if (intel_is_dual_link_lvds(dev))
 515                         limit = &intel_limits_g4x_dual_channel_lvds;
 516                 else
 517                         limit = &intel_limits_g4x_single_channel_lvds;
 518         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 519                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 520                 limit = &intel_limits_g4x_hdmi;
 521         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 522                 limit = &intel_limits_g4x_sdvo;
 523         } else /* The option is for other outputs */
 524                 limit = &intel_limits_i9xx_sdvo;
 525
 526         return limit;
 527 }
 528
 529 static const intel_limit_t *
 530 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 531 {
 532         struct drm_device *dev = crtc_state->base.crtc->dev;
 533         const intel_limit_t *limit;
 534
 535         if (IS_BROXTON(dev))
 536                 limit = &intel_limits_bxt;
 537         else if (HAS_PCH_SPLIT(dev))
 538                 limit = intel_ironlake_limit(crtc_state, refclk);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc_state);
 541         } else if (IS_PINEVIEW(dev)) {
 542                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_pineview_lvds;
 544                 else
 545                         limit = &intel_limits_pineview_sdvo;
 546         } else if (IS_CHERRYVIEW(dev)) {
 547                 limit = &intel_limits_chv;
 548         } else if (IS_VALLEYVIEW(dev)) {
 549                 limit = &intel_limits_vlv;
 550         } else if (!IS_GEN2(dev)) {
 551                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 552                         limit = &intel_limits_i9xx_lvds;
 553                 else
 554                         limit = &intel_limits_i9xx_sdvo;
 555         } else {
 556                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 557                         limit = &intel_limits_i8xx_lvds;
 558                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 559                         limit = &intel_limits_i8xx_dvo;
 560                 else
 561                         limit = &intel_limits_i8xx_dac;
 562         }
 563         return limit;
 564 }
 565
 566 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 567 static void pineview_clock(int refclk, intel_clock_t *clock)
 568 {
 569         clock->m = clock->m2 + 2;
 570         clock->p = clock->p1 * clock->p2;
 571         if (WARN_ON(clock->n == 0 || clock->p == 0))
 572                 return;
 573         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 574         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 575 }
 576
 577 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 578 {
 579         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 580 }
 581
 582 static void i9xx_clock(int refclk, intel_clock_t *clock)
 583 {
 584         clock->m = i9xx_dpll_compute_m(clock);
 585         clock->p = clock->p1 * clock->p2;
 586         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 587                 return;
 588         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 589         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 590 }
 591
 592 static void chv_clock(int refclk, intel_clock_t *clock)
 593 {
 594         clock->m = clock->m1 * clock->m2;
 595         clock->p = clock->p1 * clock->p2;
 596         if (WARN_ON(clock->n == 0 || clock->p == 0))
 597                 return;
 598         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 599                         clock->n << 22);
 600         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 601 }
 602
 603 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 604 /**
 605  * Returns whether the given set of divisors are valid for a given refclk with
 606  * the given connectors.
 607  */
 608
 609 static bool intel_PLL_is_valid(struct drm_device *dev,
 610                                const intel_limit_t *limit,
 611                                const intel_clock_t *clock)
 612 {
 613         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 614                 INTELPllInvalid("n out of range\n");
 615         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 616                 INTELPllInvalid("p1 out of range\n");
 617         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 618                 INTELPllInvalid("m2 out of range\n");
 619         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 620                 INTELPllInvalid("m1 out of range\n");
 621
 622         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 623                 if (clock->m1 <= clock->m2)
 624                         INTELPllInvalid("m1 <= m2\n");
 625
 626         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 627                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 628                         INTELPllInvalid("p out of range\n");
 629                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 630                         INTELPllInvalid("m out of range\n");
 631         }
 632
 633         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 634                 INTELPllInvalid("vco out of range\n");
 635         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 636          * connector, etc., rather than just a single range.
 637          */
 638         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 639                 INTELPllInvalid("dot out of range\n");
 640
 641         return true;
 642 }
 643
 644 static int
 645 i9xx_select_p2_div(const intel_limit_t *limit,
 646                    const struct intel_crtc_state *crtc_state,
 647                    int target)
 648 {
 649         struct drm_device *dev = crtc_state->base.crtc->dev;
 650
 651         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 652                 /*
 653                  * For LVDS just rely on its current settings for dual-channel.
 654                  * We haven't figured out how to reliably set up different
 655                  * single/dual channel state, if we even can.
 656                  */
 657                 if (intel_is_dual_link_lvds(dev))
 658                         return limit->p2.p2_fast;
 659                 else
 660                         return limit->p2.p2_slow;
 661         } else {
 662                 if (target < limit->p2.dot_limit)
 663                         return limit->p2.p2_slow;
 664                 else
 665                         return limit->p2.p2_fast;
 666         }
 667 }
 668
 669 static bool
 670 i9xx_find_best_dpll(const intel_limit_t *limit,
 671                     struct intel_crtc_state *crtc_state,
 672                     int target, int refclk, intel_clock_t *match_clock,
 673                     intel_clock_t *best_clock)
 674 {
 675         struct drm_device *dev = crtc_state->base.crtc->dev;
 676         intel_clock_t clock;
 677         int err = target;
 678
 679         memset(best_clock, 0, sizeof(*best_clock));
 680
 681         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 682
 683         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 684              clock.m1++) {
 685                 for (clock.m2 = limit->m2.min;
 686                      clock.m2 <= limit->m2.max; clock.m2++) {
 687                         if (clock.m2 >= clock.m1)
 688                                 break;
 689                         for (clock.n = limit->n.min;
 690                              clock.n <= limit->n.max; clock.n++) {
 691                                 for (clock.p1 = limit->p1.min;
 692                                         clock.p1 <= limit->p1.max; clock.p1++) {
 693                                         int this_err;
 694
 695                                         i9xx_clock(refclk, &clock);
 696                                         if (!intel_PLL_is_valid(dev, limit,
 697                                                                 &clock))
 698                                                 continue;
 699                                         if (match_clock &&
 700                                             clock.p != match_clock->p)
 701                                                 continue;
 702
 703                                         this_err = abs(clock.dot - target);
 704                                         if (this_err < err) {
 705                                                 *best_clock = clock;
 706                                                 err = this_err;
 707                                         }
 708                                 }
 709                         }
 710                 }
 711         }
 712
 713         return (err != target);
 714 }
 715
 716 static bool
 717 pnv_find_best_dpll(const intel_limit_t *limit,
 718                    struct intel_crtc_state *crtc_state,
 719                    int target, int refclk, intel_clock_t *match_clock,
 720                    intel_clock_t *best_clock)
 721 {
 722         struct drm_device *dev = crtc_state->base.crtc->dev;
 723         intel_clock_t clock;
 724         int err = target;
 725
 726         memset(best_clock, 0, sizeof(*best_clock));
 727
 728         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 729
 730         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 731              clock.m1++) {
 732                 for (clock.m2 = limit->m2.min;
 733                      clock.m2 <= limit->m2.max; clock.m2++) {
 734                         for (clock.n = limit->n.min;
 735                              clock.n <= limit->n.max; clock.n++) {
 736                                 for (clock.p1 = limit->p1.min;
 737                                         clock.p1 <= limit->p1.max; clock.p1++) {
 738                                         int this_err;
 739
 740                                         pineview_clock(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744                                         if (match_clock &&
 745                                             clock.p != match_clock->p)
 746                                                 continue;
 747
 748                                         this_err = abs(clock.dot - target);
 749                                         if (this_err < err) {
 750                                                 *best_clock = clock;
 751                                                 err = this_err;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         return (err != target);
 759 }
 760
 761 static bool
 762 g4x_find_best_dpll(const intel_limit_t *limit,
 763                    struct intel_crtc_state *crtc_state,
 764                    int target, int refclk, intel_clock_t *match_clock,
 765                    intel_clock_t *best_clock)
 766 {
 767         struct drm_device *dev = crtc_state->base.crtc->dev;
 768         intel_clock_t clock;
 769         int max_n;
 770         bool found = false;
 771         /* approximately equals target * 0.00585 */
 772         int err_most = (target >> 8) + (target >> 9);
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         max_n = limit->n.max;
 779         /* based on hardware requirement, prefer smaller n to precision */
 780         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 781                 /* based on hardware requirement, prefere larger m1,m2 */
 782                 for (clock.m1 = limit->m1.max;
 783                      clock.m1 >= limit->m1.min; clock.m1--) {
 784                         for (clock.m2 = limit->m2.max;
 785                              clock.m2 >= limit->m2.min; clock.m2--) {
 786                                 for (clock.p1 = limit->p1.max;
 787                                      clock.p1 >= limit->p1.min; clock.p1--) {
 788                                         int this_err;
 789
 790                                         i9xx_clock(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794
 795                                         this_err = abs(clock.dot - target);
 796                                         if (this_err < err_most) {
 797                                                 *best_clock = clock;
 798                                                 err_most = this_err;
 799                                                 max_n = clock.n;
 800                                                 found = true;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806         return found;
 807 }
 808
 809 /*
 810  * Check if the calculated PLL configuration is more optimal compared to the
 811  * best configuration and error found so far. Return the calculated error.
 812  */
 813 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 814                                const intel_clock_t *calculated_clock,
 815                                const intel_clock_t *best_clock,
 816                                unsigned int best_error_ppm,
 817                                unsigned int *error_ppm)
 818 {
 819         /*
 820          * For CHV ignore the error and consider only the P value.
 821          * Prefer a bigger P value based on HW requirements.
 822          */
 823         if (IS_CHERRYVIEW(dev)) {
 824                 *error_ppm = 0;
 825
 826                 return calculated_clock->p > best_clock->p;
 827         }
 828
 829         if (WARN_ON_ONCE(!target_freq))
 830                 return false;
 831
 832         *error_ppm = div_u64(1000000ULL *
 833                                 abs(target_freq - calculated_clock->dot),
 834                              target_freq);
 835         /*
 836          * Prefer a better P value over a better (smaller) error if the error
 837          * is small. Ensure this preference for future configurations too by
 838          * setting the error to 0.
 839          */
 840         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 841                 *error_ppm = 0;
 842
 843                 return true;
 844         }
 845
 846         return *error_ppm + 10 < best_error_ppm;
 847 }
 848
 849 static bool
 850 vlv_find_best_dpll(const intel_limit_t *limit,
 851                    struct intel_crtc_state *crtc_state,
 852                    int target, int refclk, intel_clock_t *match_clock,
 853                    intel_clock_t *best_clock)
 854 {
 855         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 856         struct drm_device *dev = crtc->base.dev;
 857         intel_clock_t clock;
 858         unsigned int bestppm = 1000000;
 859         /* min update 19.2 MHz */
 860         int max_n = min(limit->n.max, refclk / 19200);
 861         bool found = false;
 862
 863         target *= 5; /* fast clock */
 864
 865         memset(best_clock, 0, sizeof(*best_clock));
 866
 867         /* based on hardware requirement, prefer smaller n to precision */
 868         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 869                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 870                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 871                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 872                                 clock.p = clock.p1 * clock.p2;
 873                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 874                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 875                                         unsigned int ppm;
 876
 877                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 878                                                                      refclk * clock.m1);
 879
 880                                         vlv_clock(refclk, &clock);
 881
 882                                         if (!intel_PLL_is_valid(dev, limit,
 883                                                                 &clock))
 884                                                 continue;
 885
 886                                         if (!vlv_PLL_is_optimal(dev, target,
 887                                                                 &clock,
 888                                                                 best_clock,
 889                                                                 bestppm, &ppm))
 890                                                 continue;
 891
 892                                         *best_clock = clock;
 893                                         bestppm = ppm;
 894                                         found = true;
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         return found;
 901 }
 902
 903 static bool
 904 chv_find_best_dpll(const intel_limit_t *limit,
 905                    struct intel_crtc_state *crtc_state,
 906                    int target, int refclk, intel_clock_t *match_clock,
 907                    intel_clock_t *best_clock)
 908 {
 909         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 910         struct drm_device *dev = crtc->base.dev;
 911         unsigned int best_error_ppm;
 912         intel_clock_t clock;
 913         uint64_t m2;
 914         int found = false;
 915
 916         memset(best_clock, 0, sizeof(*best_clock));
 917         best_error_ppm = 1000000;
 918
 919         /*
 920          * Based on hardware doc, the n always set to 1, and m1 always
 921          * set to 2.  If requires to support 200Mhz refclk, we need to
 922          * revisit this because n may not 1 anymore.
 923          */
 924         clock.n = 1, clock.m1 = 2;
 925         target *= 5;    /* fast clock */
 926
 927         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 928                 for (clock.p2 = limit->p2.p2_fast;
 929                                 clock.p2 >= limit->p2.p2_slow;
 930                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 931                         unsigned int error_ppm;
 932
 933                         clock.p = clock.p1 * clock.p2;
 934
 935                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 936                                         clock.n) << 22, refclk * clock.m1);
 937
 938                         if (m2 > INT_MAX/clock.m1)
 939                                 continue;
 940
 941                         clock.m2 = m2;
 942
 943                         chv_clock(refclk, &clock);
 944
 945                         if (!intel_PLL_is_valid(dev, limit, &clock))
 946                                 continue;
 947
 948                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 949                                                 best_error_ppm, &error_ppm))
 950                                 continue;
 951
 952                         *best_clock = clock;
 953                         best_error_ppm = error_ppm;
 954                         found = true;
 955                 }
 956         }
 957
 958         return found;
 959 }
 960
 961 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 962                         intel_clock_t *best_clock)
 963 {
 964         int refclk = i9xx_get_refclk(crtc_state, 0);
 965
 966         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 967                                   target_clock, refclk, NULL, best_clock);
 968 }
 969
 970 bool intel_crtc_active(struct drm_crtc *crtc)
 971 {
 972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 973
 974         /* Be paranoid as we can arrive here with only partial
 975          * state retrieved from the hardware during setup.
 976          *
 977          * We can ditch the adjusted_mode.crtc_clock check as soon
 978          * as Haswell has gained clock readout/fastboot support.
 979          *
 980          * We can ditch the crtc->primary->fb check as soon as we can
 981          * properly reconstruct framebuffers.
 982          *
 983          * FIXME: The intel_crtc->active here should be switched to
 984          * crtc->state->active once we have proper CRTC states wired up
 985          * for atomic.
 986          */
 987         return intel_crtc->active && crtc->primary->state->fb &&
 988                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 989 }
 990
 991 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 992                                              enum pipe pipe)
 993 {
 994         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 996
 997         return intel_crtc->config->cpu_transcoder;
 998 }
 999
1000 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001 {
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         u32 reg = PIPEDSL(pipe);
1004         u32 line1, line2;
1005         u32 line_mask;
1006
1007         if (IS_GEN2(dev))
1008                 line_mask = DSL_LINEMASK_GEN2;
1009         else
1010                 line_mask = DSL_LINEMASK_GEN3;
1011
1012         line1 = I915_READ(reg) & line_mask;
1013         mdelay(5);
1014         line2 = I915_READ(reg) & line_mask;
1015
1016         return line1 == line2;
1017 }
1018
1019 /*
1020  * intel_wait_for_pipe_off - wait for pipe to turn off
1021  * @crtc: crtc whose pipe to wait for
1022  *
1023  * After disabling a pipe, we can't wait for vblank in the usual way,
1024  * spinning on the vblank interrupt status bit, since we won't actually
1025  * see an interrupt when the pipe is disabled.
1026  *
1027  * On Gen4 and above:
1028  *   wait for the pipe register state bit to turn off
1029  *
1030  * Otherwise:
1031  *   wait for the display line value to settle (it usually
1032  *   ends up stopping at the start of the next frame).
1033  *
1034  */
1035 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1036 {
1037         struct drm_device *dev = crtc->base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1040         enum pipe pipe = crtc->pipe;
1041
1042         if (INTEL_INFO(dev)->gen >= 4) {
1043                 int reg = PIPECONF(cpu_transcoder);
1044
1045                 /* Wait for the Pipe State to go off */
1046                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047                              100))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         } else {
1050                 /* Wait for the display line to settle */
1051                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1052                         WARN(1, "pipe_off wait timed out\n");
1053         }
1054 }
1055
1056 /*
1057  * ibx_digital_port_connected - is the specified port connected?
1058  * @dev_priv: i915 private structure
1059  * @port: the port to test
1060  *
1061  * Returns true if @port is connected, false otherwise.
1062  */
1063 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064                                 struct intel_digital_port *port)
1065 {
1066         u32 bit;
1067
1068         if (HAS_PCH_IBX(dev_priv->dev)) {
1069                 switch (port->port) {
1070                 case PORT_B:
1071                         bit = SDE_PORTB_HOTPLUG;
1072                         break;
1073                 case PORT_C:
1074                         bit = SDE_PORTC_HOTPLUG;
1075                         break;
1076                 case PORT_D:
1077                         bit = SDE_PORTD_HOTPLUG;
1078                         break;
1079                 default:
1080                         return true;
1081                 }
1082         } else {
1083                 switch (port->port) {
1084                 case PORT_B:
1085                         bit = SDE_PORTB_HOTPLUG_CPT;
1086                         break;
1087                 case PORT_C:
1088                         bit = SDE_PORTC_HOTPLUG_CPT;
1089                         break;
1090                 case PORT_D:
1091                         bit = SDE_PORTD_HOTPLUG_CPT;
1092                         break;
1093                 default:
1094                         return true;
1095                 }
1096         }
1097
1098         return I915_READ(SDEISR) & bit;
1099 }
1100
1101 static const char *state_string(bool enabled)
1102 {
1103         return enabled ? "on" : "off";
1104 }
1105
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108                 enum pipe pipe, bool state)
1109 {
1110         int reg;
1111         u32 val;
1112         bool cur_state;
1113
1114         reg = DPLL(pipe);
1115         val = I915_READ(reg);
1116         cur_state = !!(val & DPLL_VCO_ENABLE);
1117         I915_STATE_WARN(cur_state != state,
1118              "PLL state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121
1122 /* XXX: the dsi pll is shared between MIPI DSI ports */
1123 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124 {
1125         u32 val;
1126         bool cur_state;
1127
1128         mutex_lock(&dev_priv->sb_lock);
1129         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1130         mutex_unlock(&dev_priv->sb_lock);
1131
1132         cur_state = val & DSI_PLL_VCO_EN;
1133         I915_STATE_WARN(cur_state != state,
1134              "DSI PLL state assertion failure (expected %s, current %s)\n",
1135              state_string(state), state_string(cur_state));
1136 }
1137 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
1140 struct intel_shared_dpll *
1141 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142 {
1143         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
1145         if (crtc->config->shared_dpll < 0)
1146                 return NULL;
1147
1148         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1149 }
1150
1151 /* For ILK+ */
1152 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153                         struct intel_shared_dpll *pll,
1154                         bool state)
1155 {
1156         bool cur_state;
1157         struct intel_dpll_hw_state hw_state;
1158
1159         if (WARN (!pll,
1160                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1161                 return;
1162
1163         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1164         I915_STATE_WARN(cur_state != state,
1165              "%s assertion failure (expected %s, current %s)\n",
1166              pll->name, state_string(state), state_string(cur_state));
1167 }
1168
1169 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170                           enum pipe pipe, bool state)
1171 {
1172         int reg;
1173         u32 val;
1174         bool cur_state;
1175         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176                                                                       pipe);
1177
1178         if (HAS_DDI(dev_priv->dev)) {
1179                 /* DDI does not have a specific FDI_TX register */
1180                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1181                 val = I915_READ(reg);
1182                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1183         } else {
1184                 reg = FDI_TX_CTL(pipe);
1185                 val = I915_READ(reg);
1186                 cur_state = !!(val & FDI_TX_ENABLE);
1187         }
1188         I915_STATE_WARN(cur_state != state,
1189              "FDI TX state assertion failure (expected %s, current %s)\n",
1190              state_string(state), state_string(cur_state));
1191 }
1192 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196                           enum pipe pipe, bool state)
1197 {
1198         int reg;
1199         u32 val;
1200         bool cur_state;
1201
1202         reg = FDI_RX_CTL(pipe);
1203         val = I915_READ(reg);
1204         cur_state = !!(val & FDI_RX_ENABLE);
1205         I915_STATE_WARN(cur_state != state,
1206              "FDI RX state assertion failure (expected %s, current %s)\n",
1207              state_string(state), state_string(cur_state));
1208 }
1209 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213                                       enum pipe pipe)
1214 {
1215         int reg;
1216         u32 val;
1217
1218         /* ILK FDI PLL is always enabled */
1219         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1220                 return;
1221
1222         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1223         if (HAS_DDI(dev_priv->dev))
1224                 return;
1225
1226         reg = FDI_TX_CTL(pipe);
1227         val = I915_READ(reg);
1228         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1229 }
1230
1231 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232                        enum pipe pipe, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = FDI_RX_CTL(pipe);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1241         I915_STATE_WARN(cur_state != state,
1242              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243              state_string(state), state_string(cur_state));
1244 }
1245
1246 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247                            enum pipe pipe)
1248 {
1249         struct drm_device *dev = dev_priv->dev;
1250         int pp_reg;
1251         u32 val;
1252         enum pipe panel_pipe = PIPE_A;
1253         bool locked = true;
1254
1255         if (WARN_ON(HAS_DDI(dev)))
1256                 return;
1257
1258         if (HAS_PCH_SPLIT(dev)) {
1259                 u32 port_sel;
1260
1261                 pp_reg = PCH_PP_CONTROL;
1262                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266                         panel_pipe = PIPE_B;
1267                 /* XXX: else fix for eDP */
1268         } else if (IS_VALLEYVIEW(dev)) {
1269                 /* presumably write lock depends on pipe, not port select */
1270                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271                 panel_pipe = pipe;
1272         } else {
1273                 pp_reg = PP_CONTROL;
1274                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275                         panel_pipe = PIPE_B;
1276         }
1277
1278         val = I915_READ(pp_reg);
1279         if (!(val & PANEL_POWER_ON) ||
1280             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1281                 locked = false;
1282
1283         I915_STATE_WARN(panel_pipe == pipe && locked,
1284              "panel assertion failure, pipe %c regs locked\n",
1285              pipe_name(pipe));
1286 }
1287
1288 static void assert_cursor(struct drm_i915_private *dev_priv,
1289                           enum pipe pipe, bool state)
1290 {
1291         struct drm_device *dev = dev_priv->dev;
1292         bool cur_state;
1293
1294         if (IS_845G(dev) || IS_I865G(dev))
1295                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1296         else
1297                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1298
1299         I915_STATE_WARN(cur_state != state,
1300              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301              pipe_name(pipe), state_string(state), state_string(cur_state));
1302 }
1303 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
1306 void assert_pipe(struct drm_i915_private *dev_priv,
1307                  enum pipe pipe, bool state)
1308 {
1309         int reg;
1310         u32 val;
1311         bool cur_state;
1312         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313                                                                       pipe);
1314
1315         /* if we need the pipe quirk it must be always on */
1316         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1318                 state = true;
1319
1320         if (!intel_display_power_is_enabled(dev_priv,
1321                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1322                 cur_state = false;
1323         } else {
1324                 reg = PIPECONF(cpu_transcoder);
1325                 val = I915_READ(reg);
1326                 cur_state = !!(val & PIPECONF_ENABLE);
1327         }
1328
1329         I915_STATE_WARN(cur_state != state,
1330              "pipe %c assertion failure (expected %s, current %s)\n",
1331              pipe_name(pipe), state_string(state), state_string(cur_state));
1332 }
1333
1334 static void assert_plane(struct drm_i915_private *dev_priv,
1335                          enum plane plane, bool state)
1336 {
1337         int reg;
1338         u32 val;
1339         bool cur_state;
1340
1341         reg = DSPCNTR(plane);
1342         val = I915_READ(reg);
1343         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1344         I915_STATE_WARN(cur_state != state,
1345              "plane %c assertion failure (expected %s, current %s)\n",
1346              plane_name(plane), state_string(state), state_string(cur_state));
1347 }
1348
1349 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
1352 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353                                    enum pipe pipe)
1354 {
1355         struct drm_device *dev = dev_priv->dev;
1356         int reg, i;
1357         u32 val;
1358         int cur_pipe;
1359
1360         /* Primary planes are fixed to pipes on gen4+ */
1361         if (INTEL_INFO(dev)->gen >= 4) {
1362                 reg = DSPCNTR(pipe);
1363                 val = I915_READ(reg);
1364                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1365                      "plane %c assertion failure, should be disabled but not\n",
1366                      plane_name(pipe));
1367                 return;
1368         }
1369
1370         /* Need to check both planes against the pipe */
1371         for_each_pipe(dev_priv, i) {
1372                 reg = DSPCNTR(i);
1373                 val = I915_READ(reg);
1374                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375                         DISPPLANE_SEL_PIPE_SHIFT;
1376                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1377                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378                      plane_name(i), pipe_name(pipe));
1379         }
1380 }
1381
1382 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383                                     enum pipe pipe)
1384 {
1385         struct drm_device *dev = dev_priv->dev;
1386         int reg, sprite;
1387         u32 val;
1388
1389         if (INTEL_INFO(dev)->gen >= 9) {
1390                 for_each_sprite(dev_priv, pipe, sprite) {
1391                         val = I915_READ(PLANE_CTL(pipe, sprite));
1392                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1393                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394                              sprite, pipe_name(pipe));
1395                 }
1396         } else if (IS_VALLEYVIEW(dev)) {
1397                 for_each_sprite(dev_priv, pipe, sprite) {
1398                         reg = SPCNTR(pipe, sprite);
1399                         val = I915_READ(reg);
1400                         I915_STATE_WARN(val & SP_ENABLE,
1401                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite_name(pipe, sprite), pipe_name(pipe));
1403                 }
1404         } else if (INTEL_INFO(dev)->gen >= 7) {
1405                 reg = SPRCTL(pipe);
1406                 val = I915_READ(reg);
1407                 I915_STATE_WARN(val & SPRITE_ENABLE,
1408                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1409                      plane_name(pipe), pipe_name(pipe));
1410         } else if (INTEL_INFO(dev)->gen >= 5) {
1411                 reg = DVSCNTR(pipe);
1412                 val = I915_READ(reg);
1413                 I915_STATE_WARN(val & DVS_ENABLE,
1414                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1415                      plane_name(pipe), pipe_name(pipe));
1416         }
1417 }
1418
1419 static void assert_vblank_disabled(struct drm_crtc *crtc)
1420 {
1421         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1422                 drm_crtc_vblank_put(crtc);
1423 }
1424
1425 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1426 {
1427         u32 val;
1428         bool enabled;
1429
1430         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1431
1432         val = I915_READ(PCH_DREF_CONTROL);
1433         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434                             DREF_SUPERSPREAD_SOURCE_MASK));
1435         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1436 }
1437
1438 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439                                            enum pipe pipe)
1440 {
1441         int reg;
1442         u32 val;
1443         bool enabled;
1444
1445         reg = PCH_TRANSCONF(pipe);
1446         val = I915_READ(reg);
1447         enabled = !!(val & TRANS_ENABLE);
1448         I915_STATE_WARN(enabled,
1449              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450              pipe_name(pipe));
1451 }
1452
1453 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454                             enum pipe pipe, u32 port_sel, u32 val)
1455 {
1456         if ((val & DP_PORT_EN) == 0)
1457                 return false;
1458
1459         if (HAS_PCH_CPT(dev_priv->dev)) {
1460                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463                         return false;
1464         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466                         return false;
1467         } else {
1468                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469                         return false;
1470         }
1471         return true;
1472 }
1473
1474 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475                               enum pipe pipe, u32 val)
1476 {
1477         if ((val & SDVO_ENABLE) == 0)
1478                 return false;
1479
1480         if (HAS_PCH_CPT(dev_priv->dev)) {
1481                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1482                         return false;
1483         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485                         return false;
1486         } else {
1487                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1488                         return false;
1489         }
1490         return true;
1491 }
1492
1493 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494                               enum pipe pipe, u32 val)
1495 {
1496         if ((val & LVDS_PORT_EN) == 0)
1497                 return false;
1498
1499         if (HAS_PCH_CPT(dev_priv->dev)) {
1500                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501                         return false;
1502         } else {
1503                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504                         return false;
1505         }
1506         return true;
1507 }
1508
1509 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510                               enum pipe pipe, u32 val)
1511 {
1512         if ((val & ADPA_DAC_ENABLE) == 0)
1513                 return false;
1514         if (HAS_PCH_CPT(dev_priv->dev)) {
1515                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516                         return false;
1517         } else {
1518                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519                         return false;
1520         }
1521         return true;
1522 }
1523
1524 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1525                                    enum pipe pipe, int reg, u32 port_sel)
1526 {
1527         u32 val = I915_READ(reg);
1528         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1529              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1530              reg, pipe_name(pipe));
1531
1532         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1533              && (val & DP_PIPEB_SELECT),
1534              "IBX PCH dp port still using transcoder B\n");
1535 }
1536
1537 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538                                      enum pipe pipe, int reg)
1539 {
1540         u32 val = I915_READ(reg);
1541         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1542              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1543              reg, pipe_name(pipe));
1544
1545         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1546              && (val & SDVO_PIPE_B_SELECT),
1547              "IBX PCH hdmi port still using transcoder B\n");
1548 }
1549
1550 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551                                       enum pipe pipe)
1552 {
1553         int reg;
1554         u32 val;
1555
1556         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1559
1560         reg = PCH_ADPA;
1561         val = I915_READ(reg);
1562         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1563              "PCH VGA enabled on transcoder %c, should be disabled\n",
1564              pipe_name(pipe));
1565
1566         reg = PCH_LVDS;
1567         val = I915_READ(reg);
1568         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1569              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1570              pipe_name(pipe));
1571
1572         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1575 }
1576
1577 static void intel_init_dpio(struct drm_device *dev)
1578 {
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581         if (!IS_VALLEYVIEW(dev))
1582                 return;
1583
1584         /*
1585          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586          * CHV x1 PHY (DP/HDMI D)
1587          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588          */
1589         if (IS_CHERRYVIEW(dev)) {
1590                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592         } else {
1593                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594         }
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /* Wait for the clocks to stabilize. */
1717         POSTING_READ(reg);
1718         udelay(150);
1719
1720         if (INTEL_INFO(dev)->gen >= 4) {
1721                 I915_WRITE(DPLL_MD(crtc->pipe),
1722                            crtc->config->dpll_hw_state.dpll_md);
1723         } else {
1724                 /* The pixel multiplier can only be updated once the
1725                  * DPLL is enabled and the clocks are stable.
1726                  *
1727                  * So write it again.
1728                  */
1729                 I915_WRITE(reg, dpll);
1730         }
1731
1732         /* We do this three times for luck */
1733         I915_WRITE(reg, dpll);
1734         POSTING_READ(reg);
1735         udelay(150); /* wait for warmup */
1736         I915_WRITE(reg, dpll);
1737         POSTING_READ(reg);
1738         udelay(150); /* wait for warmup */
1739         I915_WRITE(reg, dpll);
1740         POSTING_READ(reg);
1741         udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745  * i9xx_disable_pll - disable a PLL
1746  * @dev_priv: i915 private structure
1747  * @pipe: pipe PLL to disable
1748  *
1749  * Disable the PLL for @pipe, making sure the pipe is off first.
1750  *
1751  * Note!  This is for pre-ILK only.
1752  */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755         struct drm_device *dev = crtc->base.dev;
1756         struct drm_i915_private *dev_priv = dev->dev_private;
1757         enum pipe pipe = crtc->pipe;
1758
1759         /* Disable DVO 2x clock on both PLLs if necessary */
1760         if (IS_I830(dev) &&
1761             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762             !intel_num_dvo_pipes(dev)) {
1763                 I915_WRITE(DPLL(PIPE_B),
1764                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765                 I915_WRITE(DPLL(PIPE_A),
1766                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767         }
1768
1769         /* Don't disable pipe or pipe PLLs if needed */
1770         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772                 return;
1773
1774         /* Make sure the pipe isn't still relying on us */
1775         assert_pipe_disabled(dev_priv, pipe);
1776
1777         I915_WRITE(DPLL(pipe), 0);
1778         POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783         u32 val = 0;
1784
1785         /* Make sure the pipe isn't still relying on us */
1786         assert_pipe_disabled(dev_priv, pipe);
1787
1788         /*
1789          * Leave integrated clock source and reference clock enabled for pipe B.
1790          * The latter is needed for VGA hotplug / manual detection.
1791          */
1792         if (pipe == PIPE_B)
1793                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1794         I915_WRITE(DPLL(pipe), val);
1795         POSTING_READ(DPLL(pipe));
1796
1797 }
1798
1799 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800 {
1801         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1802         u32 val;
1803
1804         /* Make sure the pipe isn't still relying on us */
1805         assert_pipe_disabled(dev_priv, pipe);
1806
1807         /* Set PLL en = 0 */
1808         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1809         if (pipe != PIPE_A)
1810                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811         I915_WRITE(DPLL(pipe), val);
1812         POSTING_READ(DPLL(pipe));
1813
1814         mutex_lock(&dev_priv->sb_lock);
1815
1816         /* Disable 10bit clock to display controller */
1817         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818         val &= ~DPIO_DCLKP_EN;
1819         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
1821         /* disable left/right clock distribution */
1822         if (pipe != PIPE_B) {
1823                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826         } else {
1827                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830         }
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         BUG_ON(INTEL_INFO(dev)->gen < 5);
1930         if (pll == NULL)
1931                 return;
1932
1933         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1934                 return;
1935
1936         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937                       pll->name, pll->active, pll->on,
1938                       crtc->base.base.id);
1939
1940         if (WARN_ON(pll->active == 0)) {
1941                 assert_shared_dpll_disabled(dev_priv, pll);
1942                 return;
1943         }
1944
1945         assert_shared_dpll_enabled(dev_priv, pll);
1946         WARN_ON(!pll->on);
1947         if (--pll->active)
1948                 return;
1949
1950         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1951         pll->disable(dev_priv, pll);
1952         pll->on = false;
1953
1954         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1955 }
1956
1957 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958                                            enum pipe pipe)
1959 {
1960         struct drm_device *dev = dev_priv->dev;
1961         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1963         uint32_t reg, val, pipeconf_val;
1964
1965         /* PCH only available on ILK+ */
1966         BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968         /* Make sure PCH DPLL is enabled */
1969         assert_shared_dpll_enabled(dev_priv,
1970                                    intel_crtc_to_shared_dpll(intel_crtc));
1971
1972         /* FDI must be feeding us bits for PCH ports */
1973         assert_fdi_tx_enabled(dev_priv, pipe);
1974         assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976         if (HAS_PCH_CPT(dev)) {
1977                 /* Workaround: Set the timing override bit before enabling the
1978                  * pch transcoder. */
1979                 reg = TRANS_CHICKEN2(pipe);
1980                 val = I915_READ(reg);
1981                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982                 I915_WRITE(reg, val);
1983         }
1984
1985         reg = PCH_TRANSCONF(pipe);
1986         val = I915_READ(reg);
1987         pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989         if (HAS_PCH_IBX(dev_priv->dev)) {
1990                 /*
1991                  * Make the BPC in transcoder be consistent with
1992                  * that in pipeconf reg. For HDMI we must use 8bpc
1993                  * here for both 8bpc and 12bpc.
1994                  */
1995                 val &= ~PIPECONF_BPC_MASK;
1996                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997                         val |= PIPECONF_8BPC;
1998                 else
1999                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2000         }
2001
2002         val &= ~TRANS_INTERLACE_MASK;
2003         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004                 if (HAS_PCH_IBX(dev_priv->dev) &&
2005                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006                         val |= TRANS_LEGACY_INTERLACED_ILK;
2007                 else
2008                         val |= TRANS_INTERLACED;
2009         else
2010                 val |= TRANS_PROGRESSIVE;
2011
2012         I915_WRITE(reg, val | TRANS_ENABLE);
2013         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018                                       enum transcoder cpu_transcoder)
2019 {
2020         u32 val, pipeconf_val;
2021
2022         /* PCH only available on ILK+ */
2023         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025         /* FDI must be feeding us bits for PCH ports */
2026         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029         /* Workaround: set timing override bit. */
2030         val = I915_READ(_TRANSA_CHICKEN2);
2031         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032         I915_WRITE(_TRANSA_CHICKEN2, val);
2033
2034         val = TRANS_ENABLE;
2035         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038             PIPECONF_INTERLACED_ILK)
2039                 val |= TRANS_INTERLACED;
2040         else
2041                 val |= TRANS_PROGRESSIVE;
2042
2043         I915_WRITE(LPT_TRANSCONF, val);
2044         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045                 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049                                             enum pipe pipe)
2050 {
2051         struct drm_device *dev = dev_priv->dev;
2052         uint32_t reg, val;
2053
2054         /* FDI relies on the transcoder */
2055         assert_fdi_tx_disabled(dev_priv, pipe);
2056         assert_fdi_rx_disabled(dev_priv, pipe);
2057
2058         /* Ports must be off as well */
2059         assert_pch_ports_disabled(dev_priv, pipe);
2060
2061         reg = PCH_TRANSCONF(pipe);
2062         val = I915_READ(reg);
2063         val &= ~TRANS_ENABLE;
2064         I915_WRITE(reg, val);
2065         /* wait for PCH transcoder off, transcoder state */
2066         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2067                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2068
2069         if (!HAS_PCH_IBX(dev)) {
2070                 /* Workaround: Clear the timing override chicken bit again. */
2071                 reg = TRANS_CHICKEN2(pipe);
2072                 val = I915_READ(reg);
2073                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074                 I915_WRITE(reg, val);
2075         }
2076 }
2077
2078 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2079 {
2080         u32 val;
2081
2082         val = I915_READ(LPT_TRANSCONF);
2083         val &= ~TRANS_ENABLE;
2084         I915_WRITE(LPT_TRANSCONF, val);
2085         /* wait for PCH transcoder off, transcoder state */
2086         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2087                 DRM_ERROR("Failed to disable PCH transcoder\n");
2088
2089         /* Workaround: clear timing override bit. */
2090         val = I915_READ(_TRANSA_CHICKEN2);
2091         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092         I915_WRITE(_TRANSA_CHICKEN2, val);
2093 }
2094
2095 /**
2096  * intel_enable_pipe - enable a pipe, asserting requirements
2097  * @crtc: crtc responsible for the pipe
2098  *
2099  * Enable @crtc's pipe, making sure that various hardware specific requirements
2100  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2101  */
2102 static void intel_enable_pipe(struct intel_crtc *crtc)
2103 {
2104         struct drm_device *dev = crtc->base.dev;
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         enum pipe pipe = crtc->pipe;
2107         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108                                                                       pipe);
2109         enum pipe pch_transcoder;
2110         int reg;
2111         u32 val;
2112
2113         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2114
2115         assert_planes_disabled(dev_priv, pipe);
2116         assert_cursor_disabled(dev_priv, pipe);
2117         assert_sprites_disabled(dev_priv, pipe);
2118
2119         if (HAS_PCH_LPT(dev_priv->dev))
2120                 pch_transcoder = TRANSCODER_A;
2121         else
2122                 pch_transcoder = pipe;
2123
2124         /*
2125          * A pipe without a PLL won't actually be able to drive bits from
2126          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2127          * need the check.
2128          */
2129         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2130                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2131                         assert_dsi_pll_enabled(dev_priv);
2132                 else
2133                         assert_pll_enabled(dev_priv, pipe);
2134         else {
2135                 if (crtc->config->has_pch_encoder) {
2136                         /* if driving the PCH, we need FDI enabled */
2137                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2138                         assert_fdi_tx_pll_enabled(dev_priv,
2139                                                   (enum pipe) cpu_transcoder);
2140                 }
2141                 /* FIXME: assert CPU port conditions for SNB+ */
2142         }
2143
2144         reg = PIPECONF(cpu_transcoder);
2145         val = I915_READ(reg);
2146         if (val & PIPECONF_ENABLE) {
2147                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2148                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2149                 return;
2150         }
2151
2152         I915_WRITE(reg, val | PIPECONF_ENABLE);
2153         POSTING_READ(reg);
2154 }
2155
2156 /**
2157  * intel_disable_pipe - disable a pipe, asserting requirements
2158  * @crtc: crtc whose pipes is to be disabled
2159  *
2160  * Disable the pipe of @crtc, making sure that various hardware
2161  * specific requirements are met, if applicable, e.g. plane
2162  * disabled, panel fitter off, etc.
2163  *
2164  * Will wait until the pipe has shut down before returning.
2165  */
2166 static void intel_disable_pipe(struct intel_crtc *crtc)
2167 {
2168         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2169         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2170         enum pipe pipe = crtc->pipe;
2171         int reg;
2172         u32 val;
2173
2174         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2175
2176         /*
2177          * Make sure planes won't keep trying to pump pixels to us,
2178          * or we might hang the display.
2179          */
2180         assert_planes_disabled(dev_priv, pipe);
2181         assert_cursor_disabled(dev_priv, pipe);
2182         assert_sprites_disabled(dev_priv, pipe);
2183
2184         reg = PIPECONF(cpu_transcoder);
2185         val = I915_READ(reg);
2186         if ((val & PIPECONF_ENABLE) == 0)
2187                 return;
2188
2189         /*
2190          * Double wide has implications for planes
2191          * so best keep it disabled when not needed.
2192          */
2193         if (crtc->config->double_wide)
2194                 val &= ~PIPECONF_DOUBLE_WIDE;
2195
2196         /* Don't disable pipe or pipe PLLs if needed */
2197         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2198             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2199                 val &= ~PIPECONF_ENABLE;
2200
2201         I915_WRITE(reg, val);
2202         if ((val & PIPECONF_ENABLE) == 0)
2203                 intel_wait_for_pipe_off(crtc);
2204 }
2205
2206 static bool need_vtd_wa(struct drm_device *dev)
2207 {
2208 #ifdef CONFIG_INTEL_IOMMU
2209         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210                 return true;
2211 #endif
2212         return false;
2213 }
2214
2215 unsigned int
2216 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2217                   uint64_t fb_format_modifier)
2218 {
2219         unsigned int tile_height;
2220         uint32_t pixel_bytes;
2221
2222         switch (fb_format_modifier) {
2223         case DRM_FORMAT_MOD_NONE:
2224                 tile_height = 1;
2225                 break;
2226         case I915_FORMAT_MOD_X_TILED:
2227                 tile_height = IS_GEN2(dev) ? 16 : 8;
2228                 break;
2229         case I915_FORMAT_MOD_Y_TILED:
2230                 tile_height = 32;
2231                 break;
2232         case I915_FORMAT_MOD_Yf_TILED:
2233                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2234                 switch (pixel_bytes) {
2235                 default:
2236                 case 1:
2237                         tile_height = 64;
2238                         break;
2239                 case 2:
2240                 case 4:
2241                         tile_height = 32;
2242                         break;
2243                 case 8:
2244                         tile_height = 16;
2245                         break;
2246                 case 16:
2247                         WARN_ONCE(1,
2248                                   "128-bit pixels are not supported for display!");
2249                         tile_height = 16;
2250                         break;
2251                 }
2252                 break;
2253         default:
2254                 MISSING_CASE(fb_format_modifier);
2255                 tile_height = 1;
2256                 break;
2257         }
2258
2259         return tile_height;
2260 }
2261
2262 unsigned int
2263 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2264                       uint32_t pixel_format, uint64_t fb_format_modifier)
2265 {
2266         return ALIGN(height, intel_tile_height(dev, pixel_format,
2267                                                fb_format_modifier));
2268 }
2269
2270 static int
2271 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2272                         const struct drm_plane_state *plane_state)
2273 {
2274         struct intel_rotation_info *info = &view->rotation_info;
2275         unsigned int tile_height, tile_pitch;
2276
2277         *view = i915_ggtt_view_normal;
2278
2279         if (!plane_state)
2280                 return 0;
2281
2282         if (!intel_rotation_90_or_270(plane_state->rotation))
2283                 return 0;
2284
2285         *view = i915_ggtt_view_rotated;
2286
2287         info->height = fb->height;
2288         info->pixel_format = fb->pixel_format;
2289         info->pitch = fb->pitches[0];
2290         info->fb_modifier = fb->modifier[0];
2291
2292         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2293                                         fb->modifier[0]);
2294         tile_pitch = PAGE_SIZE / tile_height;
2295         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2296         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2297         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2298
2299         return 0;
2300 }
2301
2302 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2303 {
2304         if (INTEL_INFO(dev_priv)->gen >= 9)
2305                 return 256 * 1024;
2306         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2307                  IS_VALLEYVIEW(dev_priv))
2308                 return 128 * 1024;
2309         else if (INTEL_INFO(dev_priv)->gen >= 4)
2310                 return 4 * 1024;
2311         else
2312                 return 0;
2313 }
2314
2315 int
2316 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2317                            struct drm_framebuffer *fb,
2318                            const struct drm_plane_state *plane_state,
2319                            struct intel_engine_cs *pipelined,
2320                            struct drm_i915_gem_request **pipelined_request)
2321 {
2322         struct drm_device *dev = fb->dev;
2323         struct drm_i915_private *dev_priv = dev->dev_private;
2324         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2325         struct i915_ggtt_view view;
2326         u32 alignment;
2327         int ret;
2328
2329         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2330
2331         switch (fb->modifier[0]) {
2332         case DRM_FORMAT_MOD_NONE:
2333                 alignment = intel_linear_alignment(dev_priv);
2334                 break;
2335         case I915_FORMAT_MOD_X_TILED:
2336                 if (INTEL_INFO(dev)->gen >= 9)
2337                         alignment = 256 * 1024;
2338                 else {
2339                         /* pin() will align the object as required by fence */
2340                         alignment = 0;
2341                 }
2342                 break;
2343         case I915_FORMAT_MOD_Y_TILED:
2344         case I915_FORMAT_MOD_Yf_TILED:
2345                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2346                           "Y tiling bo slipped through, driver bug!\n"))
2347                         return -EINVAL;
2348                 alignment = 1 * 1024 * 1024;
2349                 break;
2350         default:
2351                 MISSING_CASE(fb->modifier[0]);
2352                 return -EINVAL;
2353         }
2354
2355         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2356         if (ret)
2357                 return ret;
2358
2359         /* Note that the w/a also requires 64 PTE of padding following the
2360          * bo. We currently fill all unused PTE with the shadow page and so
2361          * we should always have valid PTE following the scanout preventing
2362          * the VT-d warning.
2363          */
2364         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2365                 alignment = 256 * 1024;
2366
2367         /*
2368          * Global gtt pte registers are special registers which actually forward
2369          * writes to a chunk of system memory. Which means that there is no risk
2370          * that the register values disappear as soon as we call
2371          * intel_runtime_pm_put(), so it is correct to wrap only the
2372          * pin/unpin/fence and not more.
2373          */
2374         intel_runtime_pm_get(dev_priv);
2375
2376         dev_priv->mm.interruptible = false;
2377         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2378                                                    pipelined_request, &view);
2379         if (ret)
2380                 goto err_interruptible;
2381
2382         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2383          * fence, whereas 965+ only requires a fence if using
2384          * framebuffer compression.  For simplicity, we always install
2385          * a fence as the cost is not that onerous.
2386          */
2387         ret = i915_gem_object_get_fence(obj);
2388         if (ret)
2389                 goto err_unpin;
2390
2391         i915_gem_object_pin_fence(obj);
2392
2393         dev_priv->mm.interruptible = true;
2394         intel_runtime_pm_put(dev_priv);
2395         return 0;
2396
2397 err_unpin:
2398         i915_gem_object_unpin_from_display_plane(obj, &view);
2399 err_interruptible:
2400         dev_priv->mm.interruptible = true;
2401         intel_runtime_pm_put(dev_priv);
2402         return ret;
2403 }
2404
2405 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2406                                const struct drm_plane_state *plane_state)
2407 {
2408         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2409         struct i915_ggtt_view view;
2410         int ret;
2411
2412         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2413
2414         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2415         WARN_ONCE(ret, "Couldn't get view from plane state!");
2416
2417         i915_gem_object_unpin_fence(obj);
2418         i915_gem_object_unpin_from_display_plane(obj, &view);
2419 }
2420
2421 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2422  * is assumed to be a power-of-two. */
2423 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2424                                              int *x, int *y,
2425                                              unsigned int tiling_mode,
2426                                              unsigned int cpp,
2427                                              unsigned int pitch)
2428 {
2429         if (tiling_mode != I915_TILING_NONE) {
2430                 unsigned int tile_rows, tiles;
2431
2432                 tile_rows = *y / 8;
2433                 *y %= 8;
2434
2435                 tiles = *x / (512/cpp);
2436                 *x %= 512/cpp;
2437
2438                 return tile_rows * pitch * 8 + tiles * 4096;
2439         } else {
2440                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2441                 unsigned int offset;
2442
2443                 offset = *y * pitch + *x * cpp;
2444                 *y = (offset & alignment) / pitch;
2445                 *x = ((offset & alignment) - *y * pitch) / cpp;
2446                 return offset & ~alignment;
2447         }
2448 }
2449
2450 static int i9xx_format_to_fourcc(int format)
2451 {
2452         switch (format) {
2453         case DISPPLANE_8BPP:
2454                 return DRM_FORMAT_C8;
2455         case DISPPLANE_BGRX555:
2456                 return DRM_FORMAT_XRGB1555;
2457         case DISPPLANE_BGRX565:
2458                 return DRM_FORMAT_RGB565;
2459         default:
2460         case DISPPLANE_BGRX888:
2461                 return DRM_FORMAT_XRGB8888;
2462         case DISPPLANE_RGBX888:
2463                 return DRM_FORMAT_XBGR8888;
2464         case DISPPLANE_BGRX101010:
2465                 return DRM_FORMAT_XRGB2101010;
2466         case DISPPLANE_RGBX101010:
2467                 return DRM_FORMAT_XBGR2101010;
2468         }
2469 }
2470
2471 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2472 {
2473         switch (format) {
2474         case PLANE_CTL_FORMAT_RGB_565:
2475                 return DRM_FORMAT_RGB565;
2476         default:
2477         case PLANE_CTL_FORMAT_XRGB_8888:
2478                 if (rgb_order) {
2479                         if (alpha)
2480                                 return DRM_FORMAT_ABGR8888;
2481                         else
2482                                 return DRM_FORMAT_XBGR8888;
2483                 } else {
2484                         if (alpha)
2485                                 return DRM_FORMAT_ARGB8888;
2486                         else
2487                                 return DRM_FORMAT_XRGB8888;
2488                 }
2489         case PLANE_CTL_FORMAT_XRGB_2101010:
2490                 if (rgb_order)
2491                         return DRM_FORMAT_XBGR2101010;
2492                 else
2493                         return DRM_FORMAT_XRGB2101010;
2494         }
2495 }
2496
2497 static bool
2498 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2499                               struct intel_initial_plane_config *plane_config)
2500 {
2501         struct drm_device *dev = crtc->base.dev;
2502         struct drm_i915_gem_object *obj = NULL;
2503         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2504         struct drm_framebuffer *fb = &plane_config->fb->base;
2505         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2506         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2507                                     PAGE_SIZE);
2508
2509         size_aligned -= base_aligned;
2510
2511         if (plane_config->size == 0)
2512                 return false;
2513
2514         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2515                                                              base_aligned,
2516                                                              base_aligned,
2517                                                              size_aligned);
2518         if (!obj)
2519                 return false;
2520
2521         obj->tiling_mode = plane_config->tiling;
2522         if (obj->tiling_mode == I915_TILING_X)
2523                 obj->stride = fb->pitches[0];
2524
2525         mode_cmd.pixel_format = fb->pixel_format;
2526         mode_cmd.width = fb->width;
2527         mode_cmd.height = fb->height;
2528         mode_cmd.pitches[0] = fb->pitches[0];
2529         mode_cmd.modifier[0] = fb->modifier[0];
2530         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2531
2532         mutex_lock(&dev->struct_mutex);
2533         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2534                                    &mode_cmd, obj)) {
2535                 DRM_DEBUG_KMS("intel fb init failed\n");
2536                 goto out_unref_obj;
2537         }
2538         mutex_unlock(&dev->struct_mutex);
2539
2540         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2541         return true;
2542
2543 out_unref_obj:
2544         drm_gem_object_unreference(&obj->base);
2545         mutex_unlock(&dev->struct_mutex);
2546         return false;
2547 }
2548
2549 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2550 static void
2551 update_state_fb(struct drm_plane *plane)
2552 {
2553         if (plane->fb == plane->state->fb)
2554                 return;
2555
2556         if (plane->state->fb)
2557                 drm_framebuffer_unreference(plane->state->fb);
2558         plane->state->fb = plane->fb;
2559         if (plane->state->fb)
2560                 drm_framebuffer_reference(plane->state->fb);
2561 }
2562
2563 static void
2564 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2565                              struct intel_initial_plane_config *plane_config)
2566 {
2567         struct drm_device *dev = intel_crtc->base.dev;
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569         struct drm_crtc *c;
2570         struct intel_crtc *i;
2571         struct drm_i915_gem_object *obj;
2572         struct drm_plane *primary = intel_crtc->base.primary;
2573         struct drm_framebuffer *fb;
2574
2575         if (!plane_config->fb)
2576                 return;
2577
2578         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2579                 fb = &plane_config->fb->base;
2580                 goto valid_fb;
2581         }
2582
2583         kfree(plane_config->fb);
2584
2585         /*
2586          * Failed to alloc the obj, check to see if we should share
2587          * an fb with another CRTC instead
2588          */
2589         for_each_crtc(dev, c) {
2590                 i = to_intel_crtc(c);
2591
2592                 if (c == &intel_crtc->base)
2593                         continue;
2594
2595                 if (!i->active)
2596                         continue;
2597
2598                 fb = c->primary->fb;
2599                 if (!fb)
2600                         continue;
2601
2602                 obj = intel_fb_obj(fb);
2603                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2604                         drm_framebuffer_reference(fb);
2605                         goto valid_fb;
2606                 }
2607         }
2608
2609         return;
2610
2611 valid_fb:
2612         obj = intel_fb_obj(fb);
2613         if (obj->tiling_mode != I915_TILING_NONE)
2614                 dev_priv->preserve_bios_swizzle = true;
2615
2616         primary->fb = fb;
2617         primary->crtc = primary->state->crtc = &intel_crtc->base;
2618         update_state_fb(primary);
2619         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2620         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2621 }
2622
2623 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2624                                       struct drm_framebuffer *fb,
2625                                       int x, int y)
2626 {
2627         struct drm_device *dev = crtc->dev;
2628         struct drm_i915_private *dev_priv = dev->dev_private;
2629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2630         struct drm_plane *primary = crtc->primary;
2631         bool visible = to_intel_plane_state(primary->state)->visible;
2632         struct drm_i915_gem_object *obj;
2633         int plane = intel_crtc->plane;
2634         unsigned long linear_offset;
2635         u32 dspcntr;
2636         u32 reg = DSPCNTR(plane);
2637         int pixel_size;
2638
2639         if (!visible || !fb) {
2640                 I915_WRITE(reg, 0);
2641                 if (INTEL_INFO(dev)->gen >= 4)
2642                         I915_WRITE(DSPSURF(plane), 0);
2643                 else
2644                         I915_WRITE(DSPADDR(plane), 0);
2645                 POSTING_READ(reg);
2646                 return;
2647         }
2648
2649         obj = intel_fb_obj(fb);
2650         if (WARN_ON(obj == NULL))
2651                 return;
2652
2653         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2654
2655         dspcntr = DISPPLANE_GAMMA_ENABLE;
2656
2657         dspcntr |= DISPLAY_PLANE_ENABLE;
2658
2659         if (INTEL_INFO(dev)->gen < 4) {
2660                 if (intel_crtc->pipe == PIPE_B)
2661                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2662
2663                 /* pipesrc and dspsize control the size that is scaled from,
2664                  * which should always be the user's requested size.
2665                  */
2666                 I915_WRITE(DSPSIZE(plane),
2667                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2668                            (intel_crtc->config->pipe_src_w - 1));
2669                 I915_WRITE(DSPPOS(plane), 0);
2670         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2671                 I915_WRITE(PRIMSIZE(plane),
2672                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2673                            (intel_crtc->config->pipe_src_w - 1));
2674                 I915_WRITE(PRIMPOS(plane), 0);
2675                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2676         }
2677
2678         switch (fb->pixel_format) {
2679         case DRM_FORMAT_C8:
2680                 dspcntr |= DISPPLANE_8BPP;
2681                 break;
2682         case DRM_FORMAT_XRGB1555:
2683                 dspcntr |= DISPPLANE_BGRX555;
2684                 break;
2685         case DRM_FORMAT_RGB565:
2686                 dspcntr |= DISPPLANE_BGRX565;
2687                 break;
2688         case DRM_FORMAT_XRGB8888:
2689                 dspcntr |= DISPPLANE_BGRX888;
2690                 break;
2691         case DRM_FORMAT_XBGR8888:
2692                 dspcntr |= DISPPLANE_RGBX888;
2693                 break;
2694         case DRM_FORMAT_XRGB2101010:
2695                 dspcntr |= DISPPLANE_BGRX101010;
2696                 break;
2697         case DRM_FORMAT_XBGR2101010:
2698                 dspcntr |= DISPPLANE_RGBX101010;
2699                 break;
2700         default:
2701                 BUG();
2702         }
2703
2704         if (INTEL_INFO(dev)->gen >= 4 &&
2705             obj->tiling_mode != I915_TILING_NONE)
2706                 dspcntr |= DISPPLANE_TILED;
2707
2708         if (IS_G4X(dev))
2709                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2710
2711         linear_offset = y * fb->pitches[0] + x * pixel_size;
2712
2713         if (INTEL_INFO(dev)->gen >= 4) {
2714                 intel_crtc->dspaddr_offset =
2715                         intel_gen4_compute_page_offset(dev_priv,
2716                                                        &x, &y, obj->tiling_mode,
2717                                                        pixel_size,
2718                                                        fb->pitches[0]);
2719                 linear_offset -= intel_crtc->dspaddr_offset;
2720         } else {
2721                 intel_crtc->dspaddr_offset = linear_offset;
2722         }
2723
2724         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2725                 dspcntr |= DISPPLANE_ROTATE_180;
2726
2727                 x += (intel_crtc->config->pipe_src_w - 1);
2728                 y += (intel_crtc->config->pipe_src_h - 1);
2729
2730                 /* Finding the last pixel of the last line of the display
2731                 data and adding to linear_offset*/
2732                 linear_offset +=
2733                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2734                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2735         }
2736
2737         I915_WRITE(reg, dspcntr);
2738
2739         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2740         if (INTEL_INFO(dev)->gen >= 4) {
2741                 I915_WRITE(DSPSURF(plane),
2742                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2743                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2744                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2745         } else
2746                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2747         POSTING_READ(reg);
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2751                                           struct drm_framebuffer *fb,
2752                                           int x, int y)
2753 {
2754         struct drm_device *dev = crtc->dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2757         struct drm_plane *primary = crtc->primary;
2758         bool visible = to_intel_plane_state(primary->state)->visible;
2759         struct drm_i915_gem_object *obj;
2760         int plane = intel_crtc->plane;
2761         unsigned long linear_offset;
2762         u32 dspcntr;
2763         u32 reg = DSPCNTR(plane);
2764         int pixel_size;
2765
2766         if (!visible || !fb) {
2767                 I915_WRITE(reg, 0);
2768                 I915_WRITE(DSPSURF(plane), 0);
2769                 POSTING_READ(reg);
2770                 return;
2771         }
2772
2773         obj = intel_fb_obj(fb);
2774         if (WARN_ON(obj == NULL))
2775                 return;
2776
2777         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2778
2779         dspcntr = DISPPLANE_GAMMA_ENABLE;
2780
2781         dspcntr |= DISPLAY_PLANE_ENABLE;
2782
2783         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2784                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2785
2786         switch (fb->pixel_format) {
2787         case DRM_FORMAT_C8:
2788                 dspcntr |= DISPPLANE_8BPP;
2789                 break;
2790         case DRM_FORMAT_RGB565:
2791                 dspcntr |= DISPPLANE_BGRX565;
2792                 break;
2793         case DRM_FORMAT_XRGB8888:
2794                 dspcntr |= DISPPLANE_BGRX888;
2795                 break;
2796         case DRM_FORMAT_XBGR8888:
2797                 dspcntr |= DISPPLANE_RGBX888;
2798                 break;
2799         case DRM_FORMAT_XRGB2101010:
2800                 dspcntr |= DISPPLANE_BGRX101010;
2801                 break;
2802         case DRM_FORMAT_XBGR2101010:
2803                 dspcntr |= DISPPLANE_RGBX101010;
2804                 break;
2805         default:
2806                 BUG();
2807         }
2808
2809         if (obj->tiling_mode != I915_TILING_NONE)
2810                 dspcntr |= DISPPLANE_TILED;
2811
2812         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2813                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2814
2815         linear_offset = y * fb->pitches[0] + x * pixel_size;
2816         intel_crtc->dspaddr_offset =
2817                 intel_gen4_compute_page_offset(dev_priv,
2818                                                &x, &y, obj->tiling_mode,
2819                                                pixel_size,
2820                                                fb->pitches[0]);
2821         linear_offset -= intel_crtc->dspaddr_offset;
2822         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2823                 dspcntr |= DISPPLANE_ROTATE_180;
2824
2825                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2826                         x += (intel_crtc->config->pipe_src_w - 1);
2827                         y += (intel_crtc->config->pipe_src_h - 1);
2828
2829                         /* Finding the last pixel of the last line of the display
2830                         data and adding to linear_offset*/
2831                         linear_offset +=
2832                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2833                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2834                 }
2835         }
2836
2837         I915_WRITE(reg, dspcntr);
2838
2839         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2840         I915_WRITE(DSPSURF(plane),
2841                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2842         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2843                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2844         } else {
2845                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2846                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2847         }
2848         POSTING_READ(reg);
2849 }
2850
2851 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2852                               uint32_t pixel_format)
2853 {
2854         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2855
2856         /*
2857          * The stride is either expressed as a multiple of 64 bytes
2858          * chunks for linear buffers or in number of tiles for tiled
2859          * buffers.
2860          */
2861         switch (fb_modifier) {
2862         case DRM_FORMAT_MOD_NONE:
2863                 return 64;
2864         case I915_FORMAT_MOD_X_TILED:
2865                 if (INTEL_INFO(dev)->gen == 2)
2866                         return 128;
2867                 return 512;
2868         case I915_FORMAT_MOD_Y_TILED:
2869                 /* No need to check for old gens and Y tiling since this is
2870                  * about the display engine and those will be blocked before
2871                  * we get here.
2872                  */
2873                 return 128;
2874         case I915_FORMAT_MOD_Yf_TILED:
2875                 if (bits_per_pixel == 8)
2876                         return 64;
2877                 else
2878                         return 128;
2879         default:
2880                 MISSING_CASE(fb_modifier);
2881                 return 64;
2882         }
2883 }
2884
2885 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2886                                      struct drm_i915_gem_object *obj)
2887 {
2888         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2889
2890         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2891                 view = &i915_ggtt_view_rotated;
2892
2893         return i915_gem_obj_ggtt_offset_view(obj, view);
2894 }
2895
2896 /*
2897  * This function detaches (aka. unbinds) unused scalers in hardware
2898  */
2899 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2900 {
2901         struct drm_device *dev;
2902         struct drm_i915_private *dev_priv;
2903         struct intel_crtc_scaler_state *scaler_state;
2904         int i;
2905
2906         dev = intel_crtc->base.dev;
2907         dev_priv = dev->dev_private;
2908         scaler_state = &intel_crtc->config->scaler_state;
2909
2910         /* loop through and disable scalers that aren't in use */
2911         for (i = 0; i < intel_crtc->num_scalers; i++) {
2912                 if (!scaler_state->scalers[i].in_use) {
2913                         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2914                         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2915                         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2916                         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2917                                 intel_crtc->base.base.id, intel_crtc->pipe, i);
2918                 }
2919         }
2920 }
2921
2922 u32 skl_plane_ctl_format(uint32_t pixel_format)
2923 {
2924         switch (pixel_format) {
2925         case DRM_FORMAT_C8:
2926                 return PLANE_CTL_FORMAT_INDEXED;
2927         case DRM_FORMAT_RGB565:
2928                 return PLANE_CTL_FORMAT_RGB_565;
2929         case DRM_FORMAT_XBGR8888:
2930                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2931         case DRM_FORMAT_XRGB8888:
2932                 return PLANE_CTL_FORMAT_XRGB_8888;
2933         /*
2934          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2935          * to be already pre-multiplied. We need to add a knob (or a different
2936          * DRM_FORMAT) for user-space to configure that.
2937          */
2938         case DRM_FORMAT_ABGR8888:
2939                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2940                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2941         case DRM_FORMAT_ARGB8888:
2942                 return PLANE_CTL_FORMAT_XRGB_8888 |
2943                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2944         case DRM_FORMAT_XRGB2101010:
2945                 return PLANE_CTL_FORMAT_XRGB_2101010;
2946         case DRM_FORMAT_XBGR2101010:
2947                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2948         case DRM_FORMAT_YUYV:
2949                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2950         case DRM_FORMAT_YVYU:
2951                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2952         case DRM_FORMAT_UYVY:
2953                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2954         case DRM_FORMAT_VYUY:
2955                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2956         default:
2957                 MISSING_CASE(pixel_format);
2958         }
2959
2960         return 0;
2961 }
2962
2963 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2964 {
2965         switch (fb_modifier) {
2966         case DRM_FORMAT_MOD_NONE:
2967                 break;
2968         case I915_FORMAT_MOD_X_TILED:
2969                 return PLANE_CTL_TILED_X;
2970         case I915_FORMAT_MOD_Y_TILED:
2971                 return PLANE_CTL_TILED_Y;
2972         case I915_FORMAT_MOD_Yf_TILED:
2973                 return PLANE_CTL_TILED_YF;
2974         default:
2975                 MISSING_CASE(fb_modifier);
2976         }
2977
2978         return 0;
2979 }
2980
2981 u32 skl_plane_ctl_rotation(unsigned int rotation)
2982 {
2983         switch (rotation) {
2984         case BIT(DRM_ROTATE_0):
2985                 break;
2986         /*
2987          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2988          * while i915 HW rotation is clockwise, thats why this swapping.
2989          */
2990         case BIT(DRM_ROTATE_90):
2991                 return PLANE_CTL_ROTATE_270;
2992         case BIT(DRM_ROTATE_180):
2993                 return PLANE_CTL_ROTATE_180;
2994         case BIT(DRM_ROTATE_270):
2995                 return PLANE_CTL_ROTATE_90;
2996         default:
2997                 MISSING_CASE(rotation);
2998         }
2999
3000         return 0;
3001 }
3002
3003 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3004                                          struct drm_framebuffer *fb,
3005                                          int x, int y)
3006 {
3007         struct drm_device *dev = crtc->dev;
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010         struct drm_plane *plane = crtc->primary;
3011         bool visible = to_intel_plane_state(plane->state)->visible;
3012         struct drm_i915_gem_object *obj;
3013         int pipe = intel_crtc->pipe;
3014         u32 plane_ctl, stride_div, stride;
3015         u32 tile_height, plane_offset, plane_size;
3016         unsigned int rotation;
3017         int x_offset, y_offset;
3018         unsigned long surf_addr;
3019         struct intel_crtc_state *crtc_state = intel_crtc->config;
3020         struct intel_plane_state *plane_state;
3021         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3022         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3023         int scaler_id = -1;
3024
3025         plane_state = to_intel_plane_state(plane->state);
3026
3027         if (!visible || !fb) {
3028                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3029                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3030                 POSTING_READ(PLANE_CTL(pipe, 0));
3031                 return;
3032         }
3033
3034         plane_ctl = PLANE_CTL_ENABLE |
3035                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3036                     PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041
3042         rotation = plane->state->rotation;
3043         plane_ctl |= skl_plane_ctl_rotation(rotation);
3044
3045         obj = intel_fb_obj(fb);
3046         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3047                                                fb->pixel_format);
3048         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3049
3050         /*
3051          * FIXME: intel_plane_state->src, dst aren't set when transitional
3052          * update_plane helpers are called from legacy paths.
3053          * Once full atomic crtc is available, below check can be avoided.
3054          */
3055         if (drm_rect_width(&plane_state->src)) {
3056                 scaler_id = plane_state->scaler_id;
3057                 src_x = plane_state->src.x1 >> 16;
3058                 src_y = plane_state->src.y1 >> 16;
3059                 src_w = drm_rect_width(&plane_state->src) >> 16;
3060                 src_h = drm_rect_height(&plane_state->src) >> 16;
3061                 dst_x = plane_state->dst.x1;
3062                 dst_y = plane_state->dst.y1;
3063                 dst_w = drm_rect_width(&plane_state->dst);
3064                 dst_h = drm_rect_height(&plane_state->dst);
3065
3066                 WARN_ON(x != src_x || y != src_y);
3067         } else {
3068                 src_w = intel_crtc->config->pipe_src_w;
3069                 src_h = intel_crtc->config->pipe_src_h;
3070         }
3071
3072         if (intel_rotation_90_or_270(rotation)) {
3073                 /* stride = Surface height in tiles */
3074                 tile_height = intel_tile_height(dev, fb->pixel_format,
3075                                                 fb->modifier[0]);
3076                 stride = DIV_ROUND_UP(fb->height, tile_height);
3077                 x_offset = stride * tile_height - y - src_h;
3078                 y_offset = x;
3079                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3080         } else {
3081                 stride = fb->pitches[0] / stride_div;
3082                 x_offset = x;
3083                 y_offset = y;
3084                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3085         }
3086         plane_offset = y_offset << 16 | x_offset;
3087
3088         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3089         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3090         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3091         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3092
3093         if (scaler_id >= 0) {
3094                 uint32_t ps_ctrl = 0;
3095
3096                 WARN_ON(!dst_w || !dst_h);
3097                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3098                         crtc_state->scaler_state.scalers[scaler_id].mode;
3099                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3100                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3101                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3102                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3103                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3104         } else {
3105                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3106         }
3107
3108         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3109
3110         POSTING_READ(PLANE_SURF(pipe, 0));
3111 }
3112
3113 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3114 static int
3115 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3116                            int x, int y, enum mode_set_atomic state)
3117 {
3118         struct drm_device *dev = crtc->dev;
3119         struct drm_i915_private *dev_priv = dev->dev_private;
3120
3121         if (dev_priv->display.disable_fbc)
3122                 dev_priv->display.disable_fbc(dev);
3123
3124         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3125
3126         return 0;
3127 }
3128
3129 static void intel_complete_page_flips(struct drm_device *dev)
3130 {
3131         struct drm_crtc *crtc;
3132
3133         for_each_crtc(dev, crtc) {
3134                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135                 enum plane plane = intel_crtc->plane;
3136
3137                 intel_prepare_page_flip(dev, plane);
3138                 intel_finish_page_flip_plane(dev, plane);
3139         }
3140 }
3141
3142 static void intel_update_primary_planes(struct drm_device *dev)
3143 {
3144         struct drm_i915_private *dev_priv = dev->dev_private;
3145         struct drm_crtc *crtc;
3146
3147         for_each_crtc(dev, crtc) {
3148                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149
3150                 drm_modeset_lock(&crtc->mutex, NULL);
3151                 /*
3152                  * FIXME: Once we have proper support for primary planes (and
3153                  * disabling them without disabling the entire crtc) allow again
3154                  * a NULL crtc->primary->fb.
3155                  */
3156                 if (intel_crtc->active && crtc->primary->fb)
3157                         dev_priv->display.update_primary_plane(crtc,
3158                                                                crtc->primary->fb,
3159                                                                crtc->x,
3160                                                                crtc->y);
3161                 drm_modeset_unlock(&crtc->mutex);
3162         }
3163 }
3164
3165 void intel_prepare_reset(struct drm_device *dev)
3166 {
3167         /* no reset support for gen2 */
3168         if (IS_GEN2(dev))
3169                 return;
3170
3171         /* reset doesn't touch the display */
3172         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3173                 return;
3174
3175         drm_modeset_lock_all(dev);
3176         /*
3177          * Disabling the crtcs gracefully seems nicer. Also the
3178          * g33 docs say we should at least disable all the planes.
3179          */
3180         intel_display_suspend(dev);
3181 }
3182
3183 void intel_finish_reset(struct drm_device *dev)
3184 {
3185         struct drm_i915_private *dev_priv = to_i915(dev);
3186
3187         /*
3188          * Flips in the rings will be nuked by the reset,
3189          * so complete all pending flips so that user space
3190          * will get its events and not get stuck.
3191          */
3192         intel_complete_page_flips(dev);
3193
3194         /* no reset support for gen2 */
3195         if (IS_GEN2(dev))
3196                 return;
3197
3198         /* reset doesn't touch the display */
3199         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3200                 /*
3201                  * Flips in the rings have been nuked by the reset,
3202                  * so update the base address of all primary
3203                  * planes to the the last fb to make sure we're
3204                  * showing the correct fb after a reset.
3205                  */
3206                 intel_update_primary_planes(dev);
3207                 return;
3208         }
3209
3210         /*
3211          * The display has been reset as well,
3212          * so need a full re-initialization.
3213          */
3214         intel_runtime_pm_disable_interrupts(dev_priv);
3215         intel_runtime_pm_enable_interrupts(dev_priv);
3216
3217         intel_modeset_init_hw(dev);
3218
3219         spin_lock_irq(&dev_priv->irq_lock);
3220         if (dev_priv->display.hpd_irq_setup)
3221                 dev_priv->display.hpd_irq_setup(dev);
3222         spin_unlock_irq(&dev_priv->irq_lock);
3223
3224         intel_modeset_setup_hw_state(dev, true);
3225
3226         intel_hpd_init(dev_priv);
3227
3228         drm_modeset_unlock_all(dev);
3229 }
3230
3231 static void
3232 intel_finish_fb(struct drm_framebuffer *old_fb)
3233 {
3234         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3235         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3236         bool was_interruptible = dev_priv->mm.interruptible;
3237         int ret;
3238
3239         /* Big Hammer, we also need to ensure that any pending
3240          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3241          * current scanout is retired before unpinning the old
3242          * framebuffer. Note that we rely on userspace rendering
3243          * into the buffer attached to the pipe they are waiting
3244          * on. If not, userspace generates a GPU hang with IPEHR
3245          * point to the MI_WAIT_FOR_EVENT.
3246          *
3247          * This should only fail upon a hung GPU, in which case we
3248          * can safely continue.
3249          */
3250         dev_priv->mm.interruptible = false;
3251         ret = i915_gem_object_wait_rendering(obj, true);
3252         dev_priv->mm.interruptible = was_interruptible;
3253
3254         WARN_ON(ret);
3255 }
3256
3257 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3258 {
3259         struct drm_device *dev = crtc->dev;
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262         bool pending;
3263
3264         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3265             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3266                 return false;
3267
3268         spin_lock_irq(&dev->event_lock);
3269         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3270         spin_unlock_irq(&dev->event_lock);
3271
3272         return pending;
3273 }
3274
3275 static void intel_update_pipe_size(struct intel_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->base.dev;
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         const struct drm_display_mode *adjusted_mode;
3280
3281         if (!i915.fastboot)
3282                 return;
3283
3284         /*
3285          * Update pipe size and adjust fitter if needed: the reason for this is
3286          * that in compute_mode_changes we check the native mode (not the pfit
3287          * mode) to see if we can flip rather than do a full mode set. In the
3288          * fastboot case, we'll flip, but if we don't update the pipesrc and
3289          * pfit state, we'll end up with a big fb scanned out into the wrong
3290          * sized surface.
3291          *
3292          * To fix this properly, we need to hoist the checks up into
3293          * compute_mode_changes (or above), check the actual pfit state and
3294          * whether the platform allows pfit disable with pipe active, and only
3295          * then update the pipesrc and pfit state, even on the flip path.
3296          */
3297
3298         adjusted_mode = &crtc->config->base.adjusted_mode;
3299
3300         I915_WRITE(PIPESRC(crtc->pipe),
3301                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3302                    (adjusted_mode->crtc_vdisplay - 1));
3303         if (!crtc->config->pch_pfit.enabled &&
3304             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3305              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3306                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3307                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3308                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3309         }
3310         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3311         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3312 }
3313
3314 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3315 {
3316         struct drm_device *dev = crtc->dev;
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319         int pipe = intel_crtc->pipe;
3320         u32 reg, temp;
3321
3322         /* enable normal train */
3323         reg = FDI_TX_CTL(pipe);
3324         temp = I915_READ(reg);
3325         if (IS_IVYBRIDGE(dev)) {
3326                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3327                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3328         } else {
3329                 temp &= ~FDI_LINK_TRAIN_NONE;
3330                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3331         }
3332         I915_WRITE(reg, temp);
3333
3334         reg = FDI_RX_CTL(pipe);
3335         temp = I915_READ(reg);
3336         if (HAS_PCH_CPT(dev)) {
3337                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3338                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3339         } else {
3340                 temp &= ~FDI_LINK_TRAIN_NONE;
3341                 temp |= FDI_LINK_TRAIN_NONE;
3342         }
3343         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3344
3345         /* wait one idle pattern time */
3346         POSTING_READ(reg);
3347         udelay(1000);
3348
3349         /* IVB wants error correction enabled */
3350         if (IS_IVYBRIDGE(dev))
3351                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3352                            FDI_FE_ERRC_ENABLE);
3353 }
3354
3355 /* The FDI link training functions for ILK/Ibexpeak. */
3356 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3357 {
3358         struct drm_device *dev = crtc->dev;
3359         struct drm_i915_private *dev_priv = dev->dev_private;
3360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361         int pipe = intel_crtc->pipe;
3362         u32 reg, temp, tries;
3363
3364         /* FDI needs bits from pipe first */
3365         assert_pipe_enabled(dev_priv, pipe);
3366
3367         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3368            for train result */
3369         reg = FDI_RX_IMR(pipe);
3370         temp = I915_READ(reg);
3371         temp &= ~FDI_RX_SYMBOL_LOCK;
3372         temp &= ~FDI_RX_BIT_LOCK;
3373         I915_WRITE(reg, temp);
3374         I915_READ(reg);
3375         udelay(150);
3376
3377         /* enable CPU FDI TX and PCH FDI RX */
3378         reg = FDI_TX_CTL(pipe);
3379         temp = I915_READ(reg);
3380         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3381         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3382         temp &= ~FDI_LINK_TRAIN_NONE;
3383         temp |= FDI_LINK_TRAIN_PATTERN_1;
3384         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3385
3386         reg = FDI_RX_CTL(pipe);
3387         temp = I915_READ(reg);
3388         temp &= ~FDI_LINK_TRAIN_NONE;
3389         temp |= FDI_LINK_TRAIN_PATTERN_1;
3390         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3391
3392         POSTING_READ(reg);
3393         udelay(150);
3394
3395         /* Ironlake workaround, enable clock pointer after FDI enable*/
3396         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3397         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3398                    FDI_RX_PHASE_SYNC_POINTER_EN);
3399
3400         reg = FDI_RX_IIR(pipe);
3401         for (tries = 0; tries < 5; tries++) {
3402                 temp = I915_READ(reg);
3403                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3404
3405                 if ((temp & FDI_RX_BIT_LOCK)) {
3406                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3407                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3408                         break;
3409                 }
3410         }
3411         if (tries == 5)
3412                 DRM_ERROR("FDI train 1 fail!\n");
3413
3414         /* Train 2 */
3415         reg = FDI_TX_CTL(pipe);
3416         temp = I915_READ(reg);
3417         temp &= ~FDI_LINK_TRAIN_NONE;
3418         temp |= FDI_LINK_TRAIN_PATTERN_2;
3419         I915_WRITE(reg, temp);
3420
3421         reg = FDI_RX_CTL(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_LINK_TRAIN_NONE;
3424         temp |= FDI_LINK_TRAIN_PATTERN_2;
3425         I915_WRITE(reg, temp);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         reg = FDI_RX_IIR(pipe);
3431         for (tries = 0; tries < 5; tries++) {
3432                 temp = I915_READ(reg);
3433                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3434
3435                 if (temp & FDI_RX_SYMBOL_LOCK) {
3436                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3437                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3438                         break;
3439                 }
3440         }
3441         if (tries == 5)
3442                 DRM_ERROR("FDI train 2 fail!\n");
3443
3444         DRM_DEBUG_KMS("FDI train done\n");
3445
3446 }
3447
3448 static const int snb_b_fdi_train_param[] = {
3449         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3450         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3451         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3452         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3453 };
3454
3455 /* The FDI link training functions for SNB/Cougarpoint. */
3456 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3457 {
3458         struct drm_device *dev = crtc->dev;
3459         struct drm_i915_private *dev_priv = dev->dev_private;
3460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461         int pipe = intel_crtc->pipe;
3462         u32 reg, temp, i, retry;
3463
3464         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3465            for train result */
3466         reg = FDI_RX_IMR(pipe);
3467         temp = I915_READ(reg);
3468         temp &= ~FDI_RX_SYMBOL_LOCK;
3469         temp &= ~FDI_RX_BIT_LOCK;
3470         I915_WRITE(reg, temp);
3471
3472         POSTING_READ(reg);
3473         udelay(150);
3474
3475         /* enable CPU FDI TX and PCH FDI RX */
3476         reg = FDI_TX_CTL(pipe);
3477         temp = I915_READ(reg);
3478         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3479         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3480         temp &= ~FDI_LINK_TRAIN_NONE;
3481         temp |= FDI_LINK_TRAIN_PATTERN_1;
3482         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3483         /* SNB-B */
3484         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3485         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3486
3487         I915_WRITE(FDI_RX_MISC(pipe),
3488                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3489
3490         reg = FDI_RX_CTL(pipe);
3491         temp = I915_READ(reg);
3492         if (HAS_PCH_CPT(dev)) {
3493                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3495         } else {
3496                 temp &= ~FDI_LINK_TRAIN_NONE;
3497                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3498         }
3499         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3500
3501         POSTING_READ(reg);
3502         udelay(150);
3503
3504         for (i = 0; i < 4; i++) {
3505                 reg = FDI_TX_CTL(pipe);
3506                 temp = I915_READ(reg);
3507                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508                 temp |= snb_b_fdi_train_param[i];
3509                 I915_WRITE(reg, temp);
3510
3511                 POSTING_READ(reg);
3512                 udelay(500);
3513
3514                 for (retry = 0; retry < 5; retry++) {
3515                         reg = FDI_RX_IIR(pipe);
3516                         temp = I915_READ(reg);
3517                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518                         if (temp & FDI_RX_BIT_LOCK) {
3519                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3520                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3521                                 break;
3522                         }
3523                         udelay(50);
3524                 }
3525                 if (retry < 5)
3526                         break;
3527         }
3528         if (i == 4)
3529                 DRM_ERROR("FDI train 1 fail!\n");
3530
3531         /* Train 2 */
3532         reg = FDI_TX_CTL(pipe);
3533         temp = I915_READ(reg);
3534         temp &= ~FDI_LINK_TRAIN_NONE;
3535         temp |= FDI_LINK_TRAIN_PATTERN_2;
3536         if (IS_GEN6(dev)) {
3537                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3538                 /* SNB-B */
3539                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3540         }
3541         I915_WRITE(reg, temp);
3542
3543         reg = FDI_RX_CTL(pipe);
3544         temp = I915_READ(reg);
3545         if (HAS_PCH_CPT(dev)) {
3546                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3547                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3548         } else {
3549                 temp &= ~FDI_LINK_TRAIN_NONE;
3550                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3551         }
3552         I915_WRITE(reg, temp);
3553
3554         POSTING_READ(reg);
3555         udelay(150);
3556
3557         for (i = 0; i < 4; i++) {
3558                 reg = FDI_TX_CTL(pipe);
3559                 temp = I915_READ(reg);
3560                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561                 temp |= snb_b_fdi_train_param[i];
3562                 I915_WRITE(reg, temp);
3563
3564                 POSTING_READ(reg);
3565                 udelay(500);
3566
3567                 for (retry = 0; retry < 5; retry++) {
3568                         reg = FDI_RX_IIR(pipe);
3569                         temp = I915_READ(reg);
3570                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3571                         if (temp & FDI_RX_SYMBOL_LOCK) {
3572                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3573                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3574                                 break;
3575                         }
3576                         udelay(50);
3577                 }
3578                 if (retry < 5)
3579                         break;
3580         }
3581         if (i == 4)
3582                 DRM_ERROR("FDI train 2 fail!\n");
3583
3584         DRM_DEBUG_KMS("FDI train done.\n");
3585 }
3586
3587 /* Manual link training for Ivy Bridge A0 parts */
3588 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3589 {
3590         struct drm_device *dev = crtc->dev;
3591         struct drm_i915_private *dev_priv = dev->dev_private;
3592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593         int pipe = intel_crtc->pipe;
3594         u32 reg, temp, i, j;
3595
3596         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3597            for train result */
3598         reg = FDI_RX_IMR(pipe);
3599         temp = I915_READ(reg);
3600         temp &= ~FDI_RX_SYMBOL_LOCK;
3601         temp &= ~FDI_RX_BIT_LOCK;
3602         I915_WRITE(reg, temp);
3603
3604         POSTING_READ(reg);
3605         udelay(150);
3606
3607         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3608                       I915_READ(FDI_RX_IIR(pipe)));
3609
3610         /* Try each vswing and preemphasis setting twice before moving on */
3611         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3612                 /* disable first in case we need to retry */
3613                 reg = FDI_TX_CTL(pipe);
3614                 temp = I915_READ(reg);
3615                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3616                 temp &= ~FDI_TX_ENABLE;
3617                 I915_WRITE(reg, temp);
3618
3619                 reg = FDI_RX_CTL(pipe);
3620                 temp = I915_READ(reg);
3621                 temp &= ~FDI_LINK_TRAIN_AUTO;
3622                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3623                 temp &= ~FDI_RX_ENABLE;
3624                 I915_WRITE(reg, temp);
3625
3626                 /* enable CPU FDI TX and PCH FDI RX */
3627                 reg = FDI_TX_CTL(pipe);
3628                 temp = I915_READ(reg);
3629                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3630                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3631                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3632                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3633                 temp |= snb_b_fdi_train_param[j/2];
3634                 temp |= FDI_COMPOSITE_SYNC;
3635                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3636
3637                 I915_WRITE(FDI_RX_MISC(pipe),
3638                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3639
3640                 reg = FDI_RX_CTL(pipe);
3641                 temp = I915_READ(reg);
3642                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3643                 temp |= FDI_COMPOSITE_SYNC;
3644                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3645
3646                 POSTING_READ(reg);
3647                 udelay(1); /* should be 0.5us */
3648
3649                 for (i = 0; i < 4; i++) {
3650                         reg = FDI_RX_IIR(pipe);
3651                         temp = I915_READ(reg);
3652                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3653
3654                         if (temp & FDI_RX_BIT_LOCK ||
3655                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3656                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3657                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3658                                               i);
3659                                 break;
3660                         }
3661                         udelay(1); /* should be 0.5us */
3662                 }
3663                 if (i == 4) {
3664                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3665                         continue;
3666                 }
3667
3668                 /* Train 2 */
3669                 reg = FDI_TX_CTL(pipe);
3670                 temp = I915_READ(reg);
3671                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3672                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3673                 I915_WRITE(reg, temp);
3674
3675                 reg = FDI_RX_CTL(pipe);
3676                 temp = I915_READ(reg);
3677                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3678                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3679                 I915_WRITE(reg, temp);
3680
3681                 POSTING_READ(reg);
3682                 udelay(2); /* should be 1.5us */
3683
3684                 for (i = 0; i < 4; i++) {
3685                         reg = FDI_RX_IIR(pipe);
3686                         temp = I915_READ(reg);
3687                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3688
3689                         if (temp & FDI_RX_SYMBOL_LOCK ||
3690                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3691                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3692                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3693                                               i);
3694                                 goto train_done;
3695                         }
3696                         udelay(2); /* should be 1.5us */
3697                 }
3698                 if (i == 4)
3699                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3700         }
3701
3702 train_done:
3703         DRM_DEBUG_KMS("FDI train done.\n");
3704 }
3705
3706 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3707 {
3708         struct drm_device *dev = intel_crtc->base.dev;
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710         int pipe = intel_crtc->pipe;
3711         u32 reg, temp;
3712
3713
3714         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3715         reg = FDI_RX_CTL(pipe);
3716         temp = I915_READ(reg);
3717         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3718         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3719         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3720         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3721
3722         POSTING_READ(reg);
3723         udelay(200);
3724
3725         /* Switch from Rawclk to PCDclk */
3726         temp = I915_READ(reg);
3727         I915_WRITE(reg, temp | FDI_PCDCLK);
3728
3729         POSTING_READ(reg);
3730         udelay(200);
3731
3732         /* Enable CPU FDI TX PLL, always on for Ironlake */
3733         reg = FDI_TX_CTL(pipe);
3734         temp = I915_READ(reg);
3735         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3736                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3737
3738                 POSTING_READ(reg);
3739                 udelay(100);
3740         }
3741 }
3742
3743 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3744 {
3745         struct drm_device *dev = intel_crtc->base.dev;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         int pipe = intel_crtc->pipe;
3748         u32 reg, temp;
3749
3750         /* Switch from PCDclk to Rawclk */
3751         reg = FDI_RX_CTL(pipe);
3752         temp = I915_READ(reg);
3753         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3754
3755         /* Disable CPU FDI TX PLL */
3756         reg = FDI_TX_CTL(pipe);
3757         temp = I915_READ(reg);
3758         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3759
3760         POSTING_READ(reg);
3761         udelay(100);
3762
3763         reg = FDI_RX_CTL(pipe);
3764         temp = I915_READ(reg);
3765         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3766
3767         /* Wait for the clocks to turn off. */
3768         POSTING_READ(reg);
3769         udelay(100);
3770 }
3771
3772 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3773 {
3774         struct drm_device *dev = crtc->dev;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         int pipe = intel_crtc->pipe;
3778         u32 reg, temp;
3779
3780         /* disable CPU FDI tx and PCH FDI rx */
3781         reg = FDI_TX_CTL(pipe);
3782         temp = I915_READ(reg);
3783         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3784         POSTING_READ(reg);
3785
3786         reg = FDI_RX_CTL(pipe);
3787         temp = I915_READ(reg);
3788         temp &= ~(0x7 << 16);
3789         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3790         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3791
3792         POSTING_READ(reg);
3793         udelay(100);
3794
3795         /* Ironlake workaround, disable clock pointer after downing FDI */
3796         if (HAS_PCH_IBX(dev))
3797                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3798
3799         /* still set train pattern 1 */
3800         reg = FDI_TX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         temp &= ~FDI_LINK_TRAIN_NONE;
3803         temp |= FDI_LINK_TRAIN_PATTERN_1;
3804         I915_WRITE(reg, temp);
3805
3806         reg = FDI_RX_CTL(pipe);
3807         temp = I915_READ(reg);
3808         if (HAS_PCH_CPT(dev)) {
3809                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3810                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3811         } else {
3812                 temp &= ~FDI_LINK_TRAIN_NONE;
3813                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3814         }
3815         /* BPC in FDI rx is consistent with that in PIPECONF */
3816         temp &= ~(0x07 << 16);
3817         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3818         I915_WRITE(reg, temp);
3819
3820         POSTING_READ(reg);
3821         udelay(100);
3822 }
3823
3824 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3825 {
3826         struct intel_crtc *crtc;
3827
3828         /* Note that we don't need to be called with mode_config.lock here
3829          * as our list of CRTC objects is static for the lifetime of the
3830          * device and so cannot disappear as we iterate. Similarly, we can
3831          * happily treat the predicates as racy, atomic checks as userspace
3832          * cannot claim and pin a new fb without at least acquring the
3833          * struct_mutex and so serialising with us.
3834          */
3835         for_each_intel_crtc(dev, crtc) {
3836                 if (atomic_read(&crtc->unpin_work_count) == 0)
3837                         continue;
3838
3839                 if (crtc->unpin_work)
3840                         intel_wait_for_vblank(dev, crtc->pipe);
3841
3842                 return true;
3843         }
3844
3845         return false;
3846 }
3847
3848 static void page_flip_completed(struct intel_crtc *intel_crtc)
3849 {
3850         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3851         struct intel_unpin_work *work = intel_crtc->unpin_work;
3852
3853         /* ensure that the unpin work is consistent wrt ->pending. */
3854         smp_rmb();
3855         intel_crtc->unpin_work = NULL;
3856
3857         if (work->event)
3858                 drm_send_vblank_event(intel_crtc->base.dev,
3859                                       intel_crtc->pipe,
3860                                       work->event);
3861
3862         drm_crtc_vblank_put(&intel_crtc->base);
3863
3864         wake_up_all(&dev_priv->pending_flip_queue);
3865         queue_work(dev_priv->wq, &work->work);
3866
3867         trace_i915_flip_complete(intel_crtc->plane,
3868                                  work->pending_flip_obj);
3869 }
3870
3871 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3872 {
3873         struct drm_device *dev = crtc->dev;
3874         struct drm_i915_private *dev_priv = dev->dev_private;
3875
3876         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3877         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3878                                        !intel_crtc_has_pending_flip(crtc),
3879                                        60*HZ) == 0)) {
3880                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881
3882                 spin_lock_irq(&dev->event_lock);
3883                 if (intel_crtc->unpin_work) {
3884                         WARN_ONCE(1, "Removing stuck page flip\n");
3885                         page_flip_completed(intel_crtc);
3886                 }
3887                 spin_unlock_irq(&dev->event_lock);
3888         }
3889
3890         if (crtc->primary->fb) {
3891                 mutex_lock(&dev->struct_mutex);
3892                 intel_finish_fb(crtc->primary->fb);
3893                 mutex_unlock(&dev->struct_mutex);
3894         }
3895 }
3896
3897 /* Program iCLKIP clock to the desired frequency */
3898 static void lpt_program_iclkip(struct drm_crtc *crtc)
3899 {
3900         struct drm_device *dev = crtc->dev;
3901         struct drm_i915_private *dev_priv = dev->dev_private;
3902         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3903         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3904         u32 temp;
3905
3906         mutex_lock(&dev_priv->sb_lock);
3907
3908         /* It is necessary to ungate the pixclk gate prior to programming
3909          * the divisors, and gate it back when it is done.
3910          */
3911         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3912
3913         /* Disable SSCCTL */
3914         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3915                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3916                                 SBI_SSCCTL_DISABLE,
3917                         SBI_ICLK);
3918
3919         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3920         if (clock == 20000) {
3921                 auxdiv = 1;
3922                 divsel = 0x41;
3923                 phaseinc = 0x20;
3924         } else {
3925                 /* The iCLK virtual clock root frequency is in MHz,
3926                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3927                  * divisors, it is necessary to divide one by another, so we
3928                  * convert the virtual clock precision to KHz here for higher
3929                  * precision.
3930                  */
3931                 u32 iclk_virtual_root_freq = 172800 * 1000;
3932                 u32 iclk_pi_range = 64;
3933                 u32 desired_divisor, msb_divisor_value, pi_value;
3934
3935                 desired_divisor = (iclk_virtual_root_freq / clock);
3936                 msb_divisor_value = desired_divisor / iclk_pi_range;
3937                 pi_value = desired_divisor % iclk_pi_range;
3938
3939                 auxdiv = 0;
3940                 divsel = msb_divisor_value - 2;
3941                 phaseinc = pi_value;
3942         }
3943
3944         /* This should not happen with any sane values */
3945         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3946                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3947         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3948                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3949
3950         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3951                         clock,
3952                         auxdiv,
3953                         divsel,
3954                         phasedir,
3955                         phaseinc);
3956
3957         /* Program SSCDIVINTPHASE6 */
3958         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3959         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3960         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3961         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3962         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3963         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3964         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3965         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3966
3967         /* Program SSCAUXDIV */
3968         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3969         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3970         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3971         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3972
3973         /* Enable modulator and associated divider */
3974         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3975         temp &= ~SBI_SSCCTL_DISABLE;
3976         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3977
3978         /* Wait for initialization time */
3979         udelay(24);
3980
3981         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3982
3983         mutex_unlock(&dev_priv->sb_lock);
3984 }
3985
3986 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3987                                                 enum pipe pch_transcoder)
3988 {
3989         struct drm_device *dev = crtc->base.dev;
3990         struct drm_i915_private *dev_priv = dev->dev_private;
3991         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3992
3993         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3994                    I915_READ(HTOTAL(cpu_transcoder)));
3995         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3996                    I915_READ(HBLANK(cpu_transcoder)));
3997         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3998                    I915_READ(HSYNC(cpu_transcoder)));
3999
4000         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4001                    I915_READ(VTOTAL(cpu_transcoder)));
4002         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4003                    I915_READ(VBLANK(cpu_transcoder)));
4004         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4005                    I915_READ(VSYNC(cpu_transcoder)));
4006         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4007                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4008 }
4009
4010 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4011 {
4012         struct drm_i915_private *dev_priv = dev->dev_private;
4013         uint32_t temp;
4014
4015         temp = I915_READ(SOUTH_CHICKEN1);
4016         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4017                 return;
4018
4019         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4020         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4021
4022         temp &= ~FDI_BC_BIFURCATION_SELECT;
4023         if (enable)
4024                 temp |= FDI_BC_BIFURCATION_SELECT;
4025
4026         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4027         I915_WRITE(SOUTH_CHICKEN1, temp);
4028         POSTING_READ(SOUTH_CHICKEN1);
4029 }
4030
4031 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4032 {
4033         struct drm_device *dev = intel_crtc->base.dev;
4034
4035         switch (intel_crtc->pipe) {
4036         case PIPE_A:
4037                 break;
4038         case PIPE_B:
4039                 if (intel_crtc->config->fdi_lanes > 2)
4040                         cpt_set_fdi_bc_bifurcation(dev, false);
4041                 else
4042                         cpt_set_fdi_bc_bifurcation(dev, true);
4043
4044                 break;
4045         case PIPE_C:
4046                 cpt_set_fdi_bc_bifurcation(dev, true);
4047
4048                 break;
4049         default:
4050                 BUG();
4051         }
4052 }
4053
4054 /*
4055  * Enable PCH resources required for PCH ports:
4056  *   - PCH PLLs
4057  *   - FDI training & RX/TX
4058  *   - update transcoder timings
4059  *   - DP transcoding bits
4060  *   - transcoder
4061  */
4062 static void ironlake_pch_enable(struct drm_crtc *crtc)
4063 {
4064         struct drm_device *dev = crtc->dev;
4065         struct drm_i915_private *dev_priv = dev->dev_private;
4066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4067         int pipe = intel_crtc->pipe;
4068         u32 reg, temp;
4069
4070         assert_pch_transcoder_disabled(dev_priv, pipe);
4071
4072         if (IS_IVYBRIDGE(dev))
4073                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4074
4075         /* Write the TU size bits before fdi link training, so that error
4076          * detection works. */
4077         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4078                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4079
4080         /* For PCH output, training FDI link */
4081         dev_priv->display.fdi_link_train(crtc);
4082
4083         /* We need to program the right clock selection before writing the pixel
4084          * mutliplier into the DPLL. */
4085         if (HAS_PCH_CPT(dev)) {
4086                 u32 sel;
4087
4088                 temp = I915_READ(PCH_DPLL_SEL);
4089                 temp |= TRANS_DPLL_ENABLE(pipe);
4090                 sel = TRANS_DPLLB_SEL(pipe);
4091                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4092                         temp |= sel;
4093                 else
4094                         temp &= ~sel;
4095                 I915_WRITE(PCH_DPLL_SEL, temp);
4096         }
4097
4098         /* XXX: pch pll's can be enabled any time before we enable the PCH
4099          * transcoder, and we actually should do this to not upset any PCH
4100          * transcoder that already use the clock when we share it.
4101          *
4102          * Note that enable_shared_dpll tries to do the right thing, but
4103          * get_shared_dpll unconditionally resets the pll - we need that to have
4104          * the right LVDS enable sequence. */
4105         intel_enable_shared_dpll(intel_crtc);
4106
4107         /* set transcoder timing, panel must allow it */
4108         assert_panel_unlocked(dev_priv, pipe);
4109         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4110
4111         intel_fdi_normal_train(crtc);
4112
4113         /* For PCH DP, enable TRANS_DP_CTL */
4114         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4115                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4116                 reg = TRANS_DP_CTL(pipe);
4117                 temp = I915_READ(reg);
4118                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4119                           TRANS_DP_SYNC_MASK |
4120                           TRANS_DP_BPC_MASK);
4121                 temp |= TRANS_DP_OUTPUT_ENABLE;
4122                 temp |= bpc << 9; /* same format but at 11:9 */
4123
4124                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4125                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4126                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4127                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4128
4129                 switch (intel_trans_dp_port_sel(crtc)) {
4130                 case PCH_DP_B:
4131                         temp |= TRANS_DP_PORT_SEL_B;
4132                         break;
4133                 case PCH_DP_C:
4134                         temp |= TRANS_DP_PORT_SEL_C;
4135                         break;
4136                 case PCH_DP_D:
4137                         temp |= TRANS_DP_PORT_SEL_D;
4138                         break;
4139                 default:
4140                         BUG();
4141                 }
4142
4143                 I915_WRITE(reg, temp);
4144         }
4145
4146         ironlake_enable_pch_transcoder(dev_priv, pipe);
4147 }
4148
4149 static void lpt_pch_enable(struct drm_crtc *crtc)
4150 {
4151         struct drm_device *dev = crtc->dev;
4152         struct drm_i915_private *dev_priv = dev->dev_private;
4153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4154         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4155
4156         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4157
4158         lpt_program_iclkip(crtc);
4159
4160         /* Set transcoder timing. */
4161         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4162
4163         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4164 }
4165
4166 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4167                                                 struct intel_crtc_state *crtc_state)
4168 {
4169         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4170         struct intel_shared_dpll *pll;
4171         struct intel_shared_dpll_config *shared_dpll;
4172         enum intel_dpll_id i;
4173
4174         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4175
4176         if (HAS_PCH_IBX(dev_priv->dev)) {
4177                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4178                 i = (enum intel_dpll_id) crtc->pipe;
4179                 pll = &dev_priv->shared_dplls[i];
4180
4181                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4182                               crtc->base.base.id, pll->name);
4183
4184                 WARN_ON(shared_dpll[i].crtc_mask);
4185
4186                 goto found;
4187         }
4188
4189         if (IS_BROXTON(dev_priv->dev)) {
4190                 /* PLL is attached to port in bxt */
4191                 struct intel_encoder *encoder;
4192                 struct intel_digital_port *intel_dig_port;
4193
4194                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4195                 if (WARN_ON(!encoder))
4196                         return NULL;
4197
4198                 intel_dig_port = enc_to_dig_port(&encoder->base);
4199                 /* 1:1 mapping between ports and PLLs */
4200                 i = (enum intel_dpll_id)intel_dig_port->port;
4201                 pll = &dev_priv->shared_dplls[i];
4202                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4203                         crtc->base.base.id, pll->name);
4204                 WARN_ON(shared_dpll[i].crtc_mask);
4205
4206                 goto found;
4207         }
4208
4209         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4210                 pll = &dev_priv->shared_dplls[i];
4211
4212                 /* Only want to check enabled timings first */
4213                 if (shared_dpll[i].crtc_mask == 0)
4214                         continue;
4215
4216                 if (memcmp(&crtc_state->dpll_hw_state,
4217                            &shared_dpll[i].hw_state,
4218                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4219                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4220                                       crtc->base.base.id, pll->name,
4221                                       shared_dpll[i].crtc_mask,
4222                                       pll->active);
4223                         goto found;
4224                 }
4225         }
4226
4227         /* Ok no matching timings, maybe there's a free one? */
4228         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4229                 pll = &dev_priv->shared_dplls[i];
4230                 if (shared_dpll[i].crtc_mask == 0) {
4231                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4232                                       crtc->base.base.id, pll->name);
4233                         goto found;
4234                 }
4235         }
4236
4237         return NULL;
4238
4239 found:
4240         if (shared_dpll[i].crtc_mask == 0)
4241                 shared_dpll[i].hw_state =
4242                         crtc_state->dpll_hw_state;
4243
4244         crtc_state->shared_dpll = i;
4245         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4246                          pipe_name(crtc->pipe));
4247
4248         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4249
4250         return pll;
4251 }
4252
4253 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4254 {
4255         struct drm_i915_private *dev_priv = to_i915(state->dev);
4256         struct intel_shared_dpll_config *shared_dpll;
4257         struct intel_shared_dpll *pll;
4258         enum intel_dpll_id i;
4259
4260         if (!to_intel_atomic_state(state)->dpll_set)
4261                 return;
4262
4263         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4264         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4265                 pll = &dev_priv->shared_dplls[i];
4266                 pll->config = shared_dpll[i];
4267         }
4268 }
4269
4270 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4271 {
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         int dslreg = PIPEDSL(pipe);
4274         u32 temp;
4275
4276         temp = I915_READ(dslreg);
4277         udelay(500);
4278         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4279                 if (wait_for(I915_READ(dslreg) != temp, 5))
4280                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4281         }
4282 }
4283
4284 static int
4285 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4286                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4287                   int src_w, int src_h, int dst_w, int dst_h)
4288 {
4289         struct intel_crtc_scaler_state *scaler_state =
4290                 &crtc_state->scaler_state;
4291         struct intel_crtc *intel_crtc =
4292                 to_intel_crtc(crtc_state->base.crtc);
4293         int need_scaling;
4294
4295         need_scaling = intel_rotation_90_or_270(rotation) ?
4296                 (src_h != dst_w || src_w != dst_h):
4297                 (src_w != dst_w || src_h != dst_h);
4298
4299         /*
4300          * if plane is being disabled or scaler is no more required or force detach
4301          *  - free scaler binded to this plane/crtc
4302          *  - in order to do this, update crtc->scaler_usage
4303          *
4304          * Here scaler state in crtc_state is set free so that
4305          * scaler can be assigned to other user. Actual register
4306          * update to free the scaler is done in plane/panel-fit programming.
4307          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4308          */
4309         if (force_detach || !need_scaling) {
4310                 if (*scaler_id >= 0) {
4311                         scaler_state->scaler_users &= ~(1 << scaler_user);
4312                         scaler_state->scalers[*scaler_id].in_use = 0;
4313
4314                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4315                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4316                                 intel_crtc->pipe, scaler_user, *scaler_id,
4317                                 scaler_state->scaler_users);
4318                         *scaler_id = -1;
4319                 }
4320                 return 0;
4321         }
4322
4323         /* range checks */
4324         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4325                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4326
4327                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4328                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4329                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4330                         "size is out of scaler range\n",
4331                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4332                 return -EINVAL;
4333         }
4334
4335         /* mark this plane as a scaler user in crtc_state */
4336         scaler_state->scaler_users |= (1 << scaler_user);
4337         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4338                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4339                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4340                 scaler_state->scaler_users);
4341
4342         return 0;
4343 }
4344
4345 /**
4346  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4347  *
4348  * @state: crtc's scaler state
4349  * @force_detach: whether to forcibly disable scaler
4350  *
4351  * Return
4352  *     0 - scaler_usage updated successfully
4353  *    error - requested scaling cannot be supported or other error condition
4354  */
4355 int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4356 {
4357         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4358         struct drm_display_mode *adjusted_mode =
4359                 &state->base.adjusted_mode;
4360
4361         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4362                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4363
4364         return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4365                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4366                 state->pipe_src_w, state->pipe_src_h,
4367                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4368 }
4369
4370 /**
4371  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4372  *
4373  * @state: crtc's scaler state
4374  * @plane_state: atomic plane state to update
4375  *
4376  * Return
4377  *     0 - scaler_usage updated successfully
4378  *    error - requested scaling cannot be supported or other error condition
4379  */
4380 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4381                                    struct intel_plane_state *plane_state)
4382 {
4383
4384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4385         struct intel_plane *intel_plane =
4386                 to_intel_plane(plane_state->base.plane);
4387         struct drm_framebuffer *fb = plane_state->base.fb;
4388         int ret;
4389
4390         bool force_detach = !fb || !plane_state->visible;
4391
4392         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4393                       intel_plane->base.base.id, intel_crtc->pipe,
4394                       drm_plane_index(&intel_plane->base));
4395
4396         ret = skl_update_scaler(crtc_state, force_detach,
4397                                 drm_plane_index(&intel_plane->base),
4398                                 &plane_state->scaler_id,
4399                                 plane_state->base.rotation,
4400                                 drm_rect_width(&plane_state->src) >> 16,
4401                                 drm_rect_height(&plane_state->src) >> 16,
4402                                 drm_rect_width(&plane_state->dst),
4403                                 drm_rect_height(&plane_state->dst));
4404
4405         if (ret || plane_state->scaler_id < 0)
4406                 return ret;
4407
4408         /* check colorkey */
4409         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4410                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4411                               intel_plane->base.base.id);
4412                 return -EINVAL;
4413         }
4414
4415         /* Check src format */
4416         switch (fb->pixel_format) {
4417         case DRM_FORMAT_RGB565:
4418         case DRM_FORMAT_XBGR8888:
4419         case DRM_FORMAT_XRGB8888:
4420         case DRM_FORMAT_ABGR8888:
4421         case DRM_FORMAT_ARGB8888:
4422         case DRM_FORMAT_XRGB2101010:
4423         case DRM_FORMAT_XBGR2101010:
4424         case DRM_FORMAT_YUYV:
4425         case DRM_FORMAT_YVYU:
4426         case DRM_FORMAT_UYVY:
4427         case DRM_FORMAT_VYUY:
4428                 break;
4429         default:
4430                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4431                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4432                 return -EINVAL;
4433         }
4434
4435         return 0;
4436 }
4437
4438 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4439 {
4440         struct drm_device *dev = crtc->base.dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         int pipe = crtc->pipe;
4443         struct intel_crtc_scaler_state *scaler_state =
4444                 &crtc->config->scaler_state;
4445
4446         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4447
4448         /* To update pfit, first update scaler state */
4449         skl_update_scaler_crtc(crtc->config, !enable);
4450         intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4451         skl_detach_scalers(crtc);
4452         if (!enable)
4453                 return;
4454
4455         if (crtc->config->pch_pfit.enabled) {
4456                 int id;
4457
4458                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4459                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4460                         return;
4461                 }
4462
4463                 id = scaler_state->scaler_id;
4464                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4465                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4466                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4467                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4468
4469                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4470         }
4471 }
4472
4473 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4474 {
4475         struct drm_device *dev = crtc->base.dev;
4476         struct drm_i915_private *dev_priv = dev->dev_private;
4477         int pipe = crtc->pipe;
4478
4479         if (crtc->config->pch_pfit.enabled) {
4480                 /* Force use of hard-coded filter coefficients
4481                  * as some pre-programmed values are broken,
4482                  * e.g. x201.
4483                  */
4484                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4485                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4486                                                  PF_PIPE_SEL_IVB(pipe));
4487                 else
4488                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4489                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4490                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4491         }
4492 }
4493
4494 void hsw_enable_ips(struct intel_crtc *crtc)
4495 {
4496         struct drm_device *dev = crtc->base.dev;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498
4499         if (!crtc->config->ips_enabled)
4500                 return;
4501
4502         /* We can only enable IPS after we enable a plane and wait for a vblank */
4503         intel_wait_for_vblank(dev, crtc->pipe);
4504
4505         assert_plane_enabled(dev_priv, crtc->plane);
4506         if (IS_BROADWELL(dev)) {
4507                 mutex_lock(&dev_priv->rps.hw_lock);
4508                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4509                 mutex_unlock(&dev_priv->rps.hw_lock);
4510                 /* Quoting Art Runyan: "its not safe to expect any particular
4511                  * value in IPS_CTL bit 31 after enabling IPS through the
4512                  * mailbox." Moreover, the mailbox may return a bogus state,
4513                  * so we need to just enable it and continue on.
4514                  */
4515         } else {
4516                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4517                 /* The bit only becomes 1 in the next vblank, so this wait here
4518                  * is essentially intel_wait_for_vblank. If we don't have this
4519                  * and don't wait for vblanks until the end of crtc_enable, then
4520                  * the HW state readout code will complain that the expected
4521                  * IPS_CTL value is not the one we read. */
4522                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4523                         DRM_ERROR("Timed out waiting for IPS enable\n");
4524         }
4525 }
4526
4527 void hsw_disable_ips(struct intel_crtc *crtc)
4528 {
4529         struct drm_device *dev = crtc->base.dev;
4530         struct drm_i915_private *dev_priv = dev->dev_private;
4531
4532         if (!crtc->config->ips_enabled)
4533                 return;
4534
4535         assert_plane_enabled(dev_priv, crtc->plane);
4536         if (IS_BROADWELL(dev)) {
4537                 mutex_lock(&dev_priv->rps.hw_lock);
4538                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4539                 mutex_unlock(&dev_priv->rps.hw_lock);
4540                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4541                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4542                         DRM_ERROR("Timed out waiting for IPS disable\n");
4543         } else {
4544                 I915_WRITE(IPS_CTL, 0);
4545                 POSTING_READ(IPS_CTL);
4546         }
4547
4548         /* We need to wait for a vblank before we can disable the plane. */
4549         intel_wait_for_vblank(dev, crtc->pipe);
4550 }
4551
4552 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4553 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4554 {
4555         struct drm_device *dev = crtc->dev;
4556         struct drm_i915_private *dev_priv = dev->dev_private;
4557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558         enum pipe pipe = intel_crtc->pipe;
4559         int palreg = PALETTE(pipe);
4560         int i;
4561         bool reenable_ips = false;
4562
4563         /* The clocks have to be on to load the palette. */
4564         if (!crtc->state->active)
4565                 return;
4566
4567         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4568                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4569                         assert_dsi_pll_enabled(dev_priv);
4570                 else
4571                         assert_pll_enabled(dev_priv, pipe);
4572         }
4573
4574         /* use legacy palette for Ironlake */
4575         if (!HAS_GMCH_DISPLAY(dev))
4576                 palreg = LGC_PALETTE(pipe);
4577
4578         /* Workaround : Do not read or write the pipe palette/gamma data while
4579          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4580          */
4581         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4582             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4583              GAMMA_MODE_MODE_SPLIT)) {
4584                 hsw_disable_ips(intel_crtc);
4585                 reenable_ips = true;
4586         }
4587
4588         for (i = 0; i < 256; i++) {
4589                 I915_WRITE(palreg + 4 * i,
4590                            (intel_crtc->lut_r[i] << 16) |
4591                            (intel_crtc->lut_g[i] << 8) |
4592                            intel_crtc->lut_b[i]);
4593         }
4594
4595         if (reenable_ips)
4596                 hsw_enable_ips(intel_crtc);
4597 }
4598
4599 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4600 {
4601         if (intel_crtc->overlay) {
4602                 struct drm_device *dev = intel_crtc->base.dev;
4603                 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605                 mutex_lock(&dev->struct_mutex);
4606                 dev_priv->mm.interruptible = false;
4607                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4608                 dev_priv->mm.interruptible = true;
4609                 mutex_unlock(&dev->struct_mutex);
4610         }
4611
4612         /* Let userspace switch the overlay on again. In most cases userspace
4613          * has to recompute where to put it anyway.
4614          */
4615 }
4616
4617 /**
4618  * intel_post_enable_primary - Perform operations after enabling primary plane
4619  * @crtc: the CRTC whose primary plane was just enabled
4620  *
4621  * Performs potentially sleeping operations that must be done after the primary
4622  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4623  * called due to an explicit primary plane update, or due to an implicit
4624  * re-enable that is caused when a sprite plane is updated to no longer
4625  * completely hide the primary plane.
4626  */
4627 static void
4628 intel_post_enable_primary(struct drm_crtc *crtc)
4629 {
4630         struct drm_device *dev = crtc->dev;
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633         int pipe = intel_crtc->pipe;
4634
4635         /*
4636          * BDW signals flip done immediately if the plane
4637          * is disabled, even if the plane enable is already
4638          * armed to occur at the next vblank :(
4639          */
4640         if (IS_BROADWELL(dev))
4641                 intel_wait_for_vblank(dev, pipe);
4642
4643         /*
4644          * FIXME IPS should be fine as long as one plane is
4645          * enabled, but in practice it seems to have problems
4646          * when going from primary only to sprite only and vice
4647          * versa.
4648          */
4649         hsw_enable_ips(intel_crtc);
4650
4651         /*
4652          * Gen2 reports pipe underruns whenever all planes are disabled.
4653          * So don't enable underrun reporting before at least some planes
4654          * are enabled.
4655          * FIXME: Need to fix the logic to work when we turn off all planes
4656          * but leave the pipe running.
4657          */
4658         if (IS_GEN2(dev))
4659                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4660
4661         /* Underruns don't raise interrupts, so check manually. */
4662         if (HAS_GMCH_DISPLAY(dev))
4663                 i9xx_check_fifo_underruns(dev_priv);
4664 }
4665
4666 /**
4667  * intel_pre_disable_primary - Perform operations before disabling primary plane
4668  * @crtc: the CRTC whose primary plane is to be disabled
4669  *
4670  * Performs potentially sleeping operations that must be done before the
4671  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4672  * be called due to an explicit primary plane update, or due to an implicit
4673  * disable that is caused when a sprite plane completely hides the primary
4674  * plane.
4675  */
4676 static void
4677 intel_pre_disable_primary(struct drm_crtc *crtc)
4678 {
4679         struct drm_device *dev = crtc->dev;
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4682         int pipe = intel_crtc->pipe;
4683
4684         /*
4685          * Gen2 reports pipe underruns whenever all planes are disabled.
4686          * So diasble underrun reporting before all the planes get disabled.
4687          * FIXME: Need to fix the logic to work when we turn off all planes
4688          * but leave the pipe running.
4689          */
4690         if (IS_GEN2(dev))
4691                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4692
4693         /*
4694          * Vblank time updates from the shadow to live plane control register
4695          * are blocked if the memory self-refresh mode is active at that
4696          * moment. So to make sure the plane gets truly disabled, disable
4697          * first the self-refresh mode. The self-refresh enable bit in turn
4698          * will be checked/applied by the HW only at the next frame start
4699          * event which is after the vblank start event, so we need to have a
4700          * wait-for-vblank between disabling the plane and the pipe.
4701          */
4702         if (HAS_GMCH_DISPLAY(dev)) {
4703                 intel_set_memory_cxsr(dev_priv, false);
4704                 dev_priv->wm.vlv.cxsr = false;
4705                 intel_wait_for_vblank(dev, pipe);
4706         }
4707
4708         /*
4709          * FIXME IPS should be fine as long as one plane is
4710          * enabled, but in practice it seems to have problems
4711          * when going from primary only to sprite only and vice
4712          * versa.
4713          */
4714         hsw_disable_ips(intel_crtc);
4715 }
4716
4717 static void intel_post_plane_update(struct intel_crtc *crtc)
4718 {
4719         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4720         struct drm_device *dev = crtc->base.dev;
4721         struct drm_plane *plane;
4722
4723         if (atomic->wait_vblank)
4724                 intel_wait_for_vblank(dev, crtc->pipe);
4725
4726         intel_frontbuffer_flip(dev, atomic->fb_bits);
4727
4728         if (atomic->disable_cxsr)
4729                 crtc->wm.cxsr_allowed = true;
4730
4731         if (crtc->atomic.update_wm_post)
4732                 intel_update_watermarks(&crtc->base);
4733
4734         if (atomic->update_fbc) {
4735                 mutex_lock(&dev->struct_mutex);
4736                 intel_fbc_update(dev);
4737                 mutex_unlock(&dev->struct_mutex);
4738         }
4739
4740         if (atomic->post_enable_primary)
4741                 intel_post_enable_primary(&crtc->base);
4742
4743         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4744                 intel_update_sprite_watermarks(plane, &crtc->base,
4745                                                0, 0, 0, false, false);
4746
4747         memset(atomic, 0, sizeof(*atomic));
4748 }
4749
4750 static void intel_pre_plane_update(struct intel_crtc *crtc)
4751 {
4752         struct drm_device *dev = crtc->base.dev;
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4755         struct drm_plane *p;
4756
4757         /* Track fb's for any planes being disabled */
4758         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4759                 struct intel_plane *plane = to_intel_plane(p);
4760
4761                 mutex_lock(&dev->struct_mutex);
4762                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4763                                   plane->frontbuffer_bit);
4764                 mutex_unlock(&dev->struct_mutex);
4765         }
4766
4767         if (atomic->wait_for_flips)
4768                 intel_crtc_wait_for_pending_flips(&crtc->base);
4769
4770         if (atomic->disable_fbc &&
4771             dev_priv->fbc.crtc == crtc) {
4772                 mutex_lock(&dev->struct_mutex);
4773                 if (dev_priv->fbc.crtc == crtc)
4774                         intel_fbc_disable(dev);
4775                 mutex_unlock(&dev->struct_mutex);
4776         }
4777
4778         if (crtc->atomic.disable_ips)
4779                 hsw_disable_ips(crtc);
4780
4781         if (atomic->pre_disable_primary)
4782                 intel_pre_disable_primary(&crtc->base);
4783
4784         if (atomic->disable_cxsr) {
4785                 crtc->wm.cxsr_allowed = false;
4786                 intel_set_memory_cxsr(dev_priv, false);
4787         }
4788 }
4789
4790 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4791 {
4792         struct drm_device *dev = crtc->dev;
4793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794         struct drm_plane *p;
4795         int pipe = intel_crtc->pipe;
4796
4797         intel_crtc_dpms_overlay_disable(intel_crtc);
4798
4799         drm_for_each_plane_mask(p, dev, plane_mask)
4800                 to_intel_plane(p)->disable_plane(p, crtc);
4801
4802         /*
4803          * FIXME: Once we grow proper nuclear flip support out of this we need
4804          * to compute the mask of flip planes precisely. For the time being
4805          * consider this a flip to a NULL plane.
4806          */
4807         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4808 }
4809
4810 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4811 {
4812         struct drm_device *dev = crtc->dev;
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4815         struct intel_encoder *encoder;
4816         int pipe = intel_crtc->pipe;
4817
4818         if (WARN_ON(intel_crtc->active))
4819                 return;
4820
4821         if (intel_crtc->config->has_pch_encoder)
4822                 intel_prepare_shared_dpll(intel_crtc);
4823
4824         if (intel_crtc->config->has_dp_encoder)
4825                 intel_dp_set_m_n(intel_crtc, M1_N1);
4826
4827         intel_set_pipe_timings(intel_crtc);
4828
4829         if (intel_crtc->config->has_pch_encoder) {
4830                 intel_cpu_transcoder_set_m_n(intel_crtc,
4831                                      &intel_crtc->config->fdi_m_n, NULL);
4832         }
4833
4834         ironlake_set_pipeconf(crtc);
4835
4836         intel_crtc->active = true;
4837
4838         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4839         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4840
4841         for_each_encoder_on_crtc(dev, crtc, encoder)
4842                 if (encoder->pre_enable)
4843                         encoder->pre_enable(encoder);
4844
4845         if (intel_crtc->config->has_pch_encoder) {
4846                 /* Note: FDI PLL enabling _must_ be done before we enable the
4847                  * cpu pipes, hence this is separate from all the other fdi/pch
4848                  * enabling. */
4849                 ironlake_fdi_pll_enable(intel_crtc);
4850         } else {
4851                 assert_fdi_tx_disabled(dev_priv, pipe);
4852                 assert_fdi_rx_disabled(dev_priv, pipe);
4853         }
4854
4855         ironlake_pfit_enable(intel_crtc);
4856
4857         /*
4858          * On ILK+ LUT must be loaded before the pipe is running but with
4859          * clocks enabled
4860          */
4861         intel_crtc_load_lut(crtc);
4862
4863         intel_update_watermarks(crtc);
4864         intel_enable_pipe(intel_crtc);
4865
4866         if (intel_crtc->config->has_pch_encoder)
4867                 ironlake_pch_enable(crtc);
4868
4869         assert_vblank_disabled(crtc);
4870         drm_crtc_vblank_on(crtc);
4871
4872         for_each_encoder_on_crtc(dev, crtc, encoder)
4873                 encoder->enable(encoder);
4874
4875         if (HAS_PCH_CPT(dev))
4876                 cpt_verify_modeset(dev, intel_crtc->pipe);
4877 }
4878
4879 /* IPS only exists on ULT machines and is tied to pipe A. */
4880 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4881 {
4882         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4883 }
4884
4885 static void haswell_crtc_enable(struct drm_crtc *crtc)
4886 {
4887         struct drm_device *dev = crtc->dev;
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4890         struct intel_encoder *encoder;
4891         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4892         struct intel_crtc_state *pipe_config =
4893                 to_intel_crtc_state(crtc->state);
4894
4895         if (WARN_ON(intel_crtc->active))
4896                 return;
4897
4898         if (intel_crtc_to_shared_dpll(intel_crtc))
4899                 intel_enable_shared_dpll(intel_crtc);
4900
4901         if (intel_crtc->config->has_dp_encoder)
4902                 intel_dp_set_m_n(intel_crtc, M1_N1);
4903
4904         intel_set_pipe_timings(intel_crtc);
4905
4906         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4907                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4908                            intel_crtc->config->pixel_multiplier - 1);
4909         }
4910
4911         if (intel_crtc->config->has_pch_encoder) {
4912                 intel_cpu_transcoder_set_m_n(intel_crtc,
4913                                      &intel_crtc->config->fdi_m_n, NULL);
4914         }
4915
4916         haswell_set_pipeconf(crtc);
4917
4918         intel_set_pipe_csc(crtc);
4919
4920         intel_crtc->active = true;
4921
4922         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4923         for_each_encoder_on_crtc(dev, crtc, encoder)
4924                 if (encoder->pre_enable)
4925                         encoder->pre_enable(encoder);
4926
4927         if (intel_crtc->config->has_pch_encoder) {
4928                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4929                                                       true);
4930                 dev_priv->display.fdi_link_train(crtc);
4931         }
4932
4933         intel_ddi_enable_pipe_clock(intel_crtc);
4934
4935         if (INTEL_INFO(dev)->gen == 9)
4936                 skylake_pfit_update(intel_crtc, 1);
4937         else if (INTEL_INFO(dev)->gen < 9)
4938                 ironlake_pfit_enable(intel_crtc);
4939         else
4940                 MISSING_CASE(INTEL_INFO(dev)->gen);
4941
4942         /*
4943          * On ILK+ LUT must be loaded before the pipe is running but with
4944          * clocks enabled
4945          */
4946         intel_crtc_load_lut(crtc);
4947
4948         intel_ddi_set_pipe_settings(crtc);
4949         intel_ddi_enable_transcoder_func(crtc);
4950
4951         intel_update_watermarks(crtc);
4952         intel_enable_pipe(intel_crtc);
4953
4954         if (intel_crtc->config->has_pch_encoder)
4955                 lpt_pch_enable(crtc);
4956
4957         if (intel_crtc->config->dp_encoder_is_mst)
4958                 intel_ddi_set_vc_payload_alloc(crtc, true);
4959
4960         assert_vblank_disabled(crtc);
4961         drm_crtc_vblank_on(crtc);
4962
4963         for_each_encoder_on_crtc(dev, crtc, encoder) {
4964                 encoder->enable(encoder);
4965                 intel_opregion_notify_encoder(encoder, true);
4966         }
4967
4968         /* If we change the relative order between pipe/planes enabling, we need
4969          * to change the workaround. */
4970         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4971         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4972                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4973                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4974         }
4975 }
4976
4977 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4978 {
4979         struct drm_device *dev = crtc->base.dev;
4980         struct drm_i915_private *dev_priv = dev->dev_private;
4981         int pipe = crtc->pipe;
4982
4983         /* To avoid upsetting the power well on haswell only disable the pfit if
4984          * it's in use. The hw state code will make sure we get this right. */
4985         if (crtc->config->pch_pfit.enabled) {
4986                 I915_WRITE(PF_CTL(pipe), 0);
4987                 I915_WRITE(PF_WIN_POS(pipe), 0);
4988                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4989         }
4990 }
4991
4992 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4993 {
4994         struct drm_device *dev = crtc->dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997         struct intel_encoder *encoder;
4998         int pipe = intel_crtc->pipe;
4999         u32 reg, temp;
5000
5001         for_each_encoder_on_crtc(dev, crtc, encoder)
5002                 encoder->disable(encoder);
5003
5004         drm_crtc_vblank_off(crtc);
5005         assert_vblank_disabled(crtc);
5006
5007         if (intel_crtc->config->has_pch_encoder)
5008                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5009
5010         intel_disable_pipe(intel_crtc);
5011
5012         ironlake_pfit_disable(intel_crtc);
5013
5014         if (intel_crtc->config->has_pch_encoder)
5015                 ironlake_fdi_disable(crtc);
5016
5017         for_each_encoder_on_crtc(dev, crtc, encoder)
5018                 if (encoder->post_disable)
5019                         encoder->post_disable(encoder);
5020
5021         if (intel_crtc->config->has_pch_encoder) {
5022                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5023
5024                 if (HAS_PCH_CPT(dev)) {
5025                         /* disable TRANS_DP_CTL */
5026                         reg = TRANS_DP_CTL(pipe);
5027                         temp = I915_READ(reg);
5028                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5029                                   TRANS_DP_PORT_SEL_MASK);
5030                         temp |= TRANS_DP_PORT_SEL_NONE;
5031                         I915_WRITE(reg, temp);
5032
5033                         /* disable DPLL_SEL */
5034                         temp = I915_READ(PCH_DPLL_SEL);
5035                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5036                         I915_WRITE(PCH_DPLL_SEL, temp);
5037                 }
5038
5039                 ironlake_fdi_pll_disable(intel_crtc);
5040         }
5041 }
5042
5043 static void haswell_crtc_disable(struct drm_crtc *crtc)
5044 {
5045         struct drm_device *dev = crtc->dev;
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         struct intel_encoder *encoder;
5049         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5050
5051         for_each_encoder_on_crtc(dev, crtc, encoder) {
5052                 intel_opregion_notify_encoder(encoder, false);
5053                 encoder->disable(encoder);
5054         }
5055
5056         drm_crtc_vblank_off(crtc);
5057         assert_vblank_disabled(crtc);
5058
5059         if (intel_crtc->config->has_pch_encoder)
5060                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5061                                                       false);
5062         intel_disable_pipe(intel_crtc);
5063
5064         if (intel_crtc->config->dp_encoder_is_mst)
5065                 intel_ddi_set_vc_payload_alloc(crtc, false);
5066
5067         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5068
5069         if (INTEL_INFO(dev)->gen == 9)
5070                 skylake_pfit_update(intel_crtc, 0);
5071         else if (INTEL_INFO(dev)->gen < 9)
5072                 ironlake_pfit_disable(intel_crtc);
5073         else
5074                 MISSING_CASE(INTEL_INFO(dev)->gen);
5075
5076         intel_ddi_disable_pipe_clock(intel_crtc);
5077
5078         if (intel_crtc->config->has_pch_encoder) {
5079                 lpt_disable_pch_transcoder(dev_priv);
5080                 intel_ddi_fdi_disable(crtc);
5081         }
5082
5083         for_each_encoder_on_crtc(dev, crtc, encoder)
5084                 if (encoder->post_disable)
5085                         encoder->post_disable(encoder);
5086 }
5087
5088 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5089 {
5090         struct drm_device *dev = crtc->base.dev;
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         struct intel_crtc_state *pipe_config = crtc->config;
5093
5094         if (!pipe_config->gmch_pfit.control)
5095                 return;
5096
5097         /*
5098          * The panel fitter should only be adjusted whilst the pipe is disabled,
5099          * according to register description and PRM.
5100          */
5101         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5102         assert_pipe_disabled(dev_priv, crtc->pipe);
5103
5104         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5105         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5106
5107         /* Border color in case we don't scale up to the full screen. Black by
5108          * default, change to something else for debugging. */
5109         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5110 }
5111
5112 static enum intel_display_power_domain port_to_power_domain(enum port port)
5113 {
5114         switch (port) {
5115         case PORT_A:
5116                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5117         case PORT_B:
5118                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5119         case PORT_C:
5120                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5121         case PORT_D:
5122                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5123         default:
5124                 WARN_ON_ONCE(1);
5125                 return POWER_DOMAIN_PORT_OTHER;
5126         }
5127 }
5128
5129 #define for_each_power_domain(domain, mask)                             \
5130         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5131                 if ((1 << (domain)) & (mask))
5132
5133 enum intel_display_power_domain
5134 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5135 {
5136         struct drm_device *dev = intel_encoder->base.dev;
5137         struct intel_digital_port *intel_dig_port;
5138
5139         switch (intel_encoder->type) {
5140         case INTEL_OUTPUT_UNKNOWN:
5141                 /* Only DDI platforms should ever use this output type */
5142                 WARN_ON_ONCE(!HAS_DDI(dev));
5143         case INTEL_OUTPUT_DISPLAYPORT:
5144         case INTEL_OUTPUT_HDMI:
5145         case INTEL_OUTPUT_EDP:
5146                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5147                 return port_to_power_domain(intel_dig_port->port);
5148         case INTEL_OUTPUT_DP_MST:
5149                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5150                 return port_to_power_domain(intel_dig_port->port);
5151         case INTEL_OUTPUT_ANALOG:
5152                 return POWER_DOMAIN_PORT_CRT;
5153         case INTEL_OUTPUT_DSI:
5154                 return POWER_DOMAIN_PORT_DSI;
5155         default:
5156                 return POWER_DOMAIN_PORT_OTHER;
5157         }
5158 }
5159
5160 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5161 {
5162         struct drm_device *dev = crtc->dev;
5163         struct intel_encoder *intel_encoder;
5164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5165         enum pipe pipe = intel_crtc->pipe;
5166         unsigned long mask;
5167         enum transcoder transcoder;
5168
5169         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5170
5171         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5172         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5173         if (intel_crtc->config->pch_pfit.enabled ||
5174             intel_crtc->config->pch_pfit.force_thru)
5175                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5176
5177         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5178                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5179
5180         return mask;
5181 }
5182
5183 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5184 {
5185         struct drm_device *dev = state->dev;
5186         struct drm_i915_private *dev_priv = dev->dev_private;
5187         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5188         struct intel_crtc *crtc;
5189
5190         /*
5191          * First get all needed power domains, then put all unneeded, to avoid
5192          * any unnecessary toggling of the power wells.
5193          */
5194         for_each_intel_crtc(dev, crtc) {
5195                 enum intel_display_power_domain domain;
5196
5197                 if (!crtc->base.state->enable)
5198                         continue;
5199
5200                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5201
5202                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5203                         intel_display_power_get(dev_priv, domain);
5204         }
5205
5206         if (dev_priv->display.modeset_commit_cdclk) {
5207                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5208
5209                 if (cdclk != dev_priv->cdclk_freq &&
5210                     !WARN_ON(!state->allow_modeset))
5211                         dev_priv->display.modeset_commit_cdclk(state);
5212         }
5213
5214         for_each_intel_crtc(dev, crtc) {
5215                 enum intel_display_power_domain domain;
5216
5217                 for_each_power_domain(domain, crtc->enabled_power_domains)
5218                         intel_display_power_put(dev_priv, domain);
5219
5220                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5221         }
5222
5223         intel_display_set_init_power(dev_priv, false);
5224 }
5225
5226 static void intel_update_max_cdclk(struct drm_device *dev)
5227 {
5228         struct drm_i915_private *dev_priv = dev->dev_private;
5229
5230         if (IS_SKYLAKE(dev)) {
5231                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5232
5233                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5234                         dev_priv->max_cdclk_freq = 675000;
5235                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5236                         dev_priv->max_cdclk_freq = 540000;
5237                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5238                         dev_priv->max_cdclk_freq = 450000;
5239                 else
5240                         dev_priv->max_cdclk_freq = 337500;
5241         } else if (IS_BROADWELL(dev))  {
5242                 /*
5243                  * FIXME with extra cooling we can allow
5244                  * 540 MHz for ULX and 675 Mhz for ULT.
5245                  * How can we know if extra cooling is
5246                  * available? PCI ID, VTB, something else?
5247                  */
5248                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5249                         dev_priv->max_cdclk_freq = 450000;
5250                 else if (IS_BDW_ULX(dev))
5251                         dev_priv->max_cdclk_freq = 450000;
5252                 else if (IS_BDW_ULT(dev))
5253                         dev_priv->max_cdclk_freq = 540000;
5254                 else
5255                         dev_priv->max_cdclk_freq = 675000;
5256         } else if (IS_CHERRYVIEW(dev)) {
5257                 dev_priv->max_cdclk_freq = 320000;
5258         } else if (IS_VALLEYVIEW(dev)) {
5259                 dev_priv->max_cdclk_freq = 400000;
5260         } else {
5261                 /* otherwise assume cdclk is fixed */
5262                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5263         }
5264
5265         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5266                          dev_priv->max_cdclk_freq);
5267 }
5268
5269 static void intel_update_cdclk(struct drm_device *dev)
5270 {
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272
5273         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5274         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5275                          dev_priv->cdclk_freq);
5276
5277         /*
5278          * Program the gmbus_freq based on the cdclk frequency.
5279          * BSpec erroneously claims we should aim for 4MHz, but
5280          * in fact 1MHz is the correct frequency.
5281          */
5282         if (IS_VALLEYVIEW(dev)) {
5283                 /*
5284                  * Program the gmbus_freq based on the cdclk frequency.
5285                  * BSpec erroneously claims we should aim for 4MHz, but
5286                  * in fact 1MHz is the correct frequency.
5287                  */
5288                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5289         }
5290
5291         if (dev_priv->max_cdclk_freq == 0)
5292                 intel_update_max_cdclk(dev);
5293 }
5294
5295 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5296 {
5297         struct drm_i915_private *dev_priv = dev->dev_private;
5298         uint32_t divider;
5299         uint32_t ratio;
5300         uint32_t current_freq;
5301         int ret;
5302
5303         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5304         switch (frequency) {
5305         case 144000:
5306                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5307                 ratio = BXT_DE_PLL_RATIO(60);
5308                 break;
5309         case 288000:
5310                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5311                 ratio = BXT_DE_PLL_RATIO(60);
5312                 break;
5313         case 384000:
5314                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5315                 ratio = BXT_DE_PLL_RATIO(60);
5316                 break;
5317         case 576000:
5318                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5319                 ratio = BXT_DE_PLL_RATIO(60);
5320                 break;
5321         case 624000:
5322                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5323                 ratio = BXT_DE_PLL_RATIO(65);
5324                 break;
5325         case 19200:
5326                 /*
5327                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5328                  * to suppress GCC warning.
5329                  */
5330                 ratio = 0;
5331                 divider = 0;
5332                 break;
5333         default:
5334                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5335
5336                 return;
5337         }
5338
5339         mutex_lock(&dev_priv->rps.hw_lock);
5340         /* Inform power controller of upcoming frequency change */
5341         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5342                                       0x80000000);
5343         mutex_unlock(&dev_priv->rps.hw_lock);
5344
5345         if (ret) {
5346                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5347                           ret, frequency);
5348                 return;
5349         }
5350
5351         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5352         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5353         current_freq = current_freq * 500 + 1000;
5354
5355         /*
5356          * DE PLL has to be disabled when
5357          * - setting to 19.2MHz (bypass, PLL isn't used)
5358          * - before setting to 624MHz (PLL needs toggling)
5359          * - before setting to any frequency from 624MHz (PLL needs toggling)
5360          */
5361         if (frequency == 19200 || frequency == 624000 ||
5362             current_freq == 624000) {
5363                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5364                 /* Timeout 200us */
5365                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5366                              1))
5367                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5368         }
5369
5370         if (frequency != 19200) {
5371                 uint32_t val;
5372
5373                 val = I915_READ(BXT_DE_PLL_CTL);
5374                 val &= ~BXT_DE_PLL_RATIO_MASK;
5375                 val |= ratio;
5376                 I915_WRITE(BXT_DE_PLL_CTL, val);
5377
5378                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5379                 /* Timeout 200us */
5380                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5381                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5382
5383                 val = I915_READ(CDCLK_CTL);
5384                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5385                 val |= divider;
5386                 /*
5387                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5388                  * enable otherwise.
5389                  */
5390                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5391                 if (frequency >= 500000)
5392                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5393
5394                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5395                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5396                 val |= (frequency - 1000) / 500;
5397                 I915_WRITE(CDCLK_CTL, val);
5398         }
5399
5400         mutex_lock(&dev_priv->rps.hw_lock);
5401         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5402                                       DIV_ROUND_UP(frequency, 25000));
5403         mutex_unlock(&dev_priv->rps.hw_lock);
5404
5405         if (ret) {
5406                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5407                           ret, frequency);
5408                 return;
5409         }
5410
5411         intel_update_cdclk(dev);
5412 }
5413
5414 void broxton_init_cdclk(struct drm_device *dev)
5415 {
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         uint32_t val;
5418
5419         /*
5420          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5421          * or else the reset will hang because there is no PCH to respond.
5422          * Move the handshake programming to initialization sequence.
5423          * Previously was left up to BIOS.
5424          */
5425         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5426         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5427         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5428
5429         /* Enable PG1 for cdclk */
5430         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5431
5432         /* check if cd clock is enabled */
5433         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5434                 DRM_DEBUG_KMS("Display already initialized\n");
5435                 return;
5436         }
5437
5438         /*
5439          * FIXME:
5440          * - The initial CDCLK needs to be read from VBT.
5441          *   Need to make this change after VBT has changes for BXT.
5442          * - check if setting the max (or any) cdclk freq is really necessary
5443          *   here, it belongs to modeset time
5444          */
5445         broxton_set_cdclk(dev, 624000);
5446
5447         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5448         POSTING_READ(DBUF_CTL);
5449
5450         udelay(10);
5451
5452         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5453                 DRM_ERROR("DBuf power enable timeout!\n");
5454 }
5455
5456 void broxton_uninit_cdclk(struct drm_device *dev)
5457 {
5458         struct drm_i915_private *dev_priv = dev->dev_private;
5459
5460         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5461         POSTING_READ(DBUF_CTL);
5462
5463         udelay(10);
5464
5465         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5466                 DRM_ERROR("DBuf power disable timeout!\n");
5467
5468         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5469         broxton_set_cdclk(dev, 19200);
5470
5471         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5472 }
5473
5474 static const struct skl_cdclk_entry {
5475         unsigned int freq;
5476         unsigned int vco;
5477 } skl_cdclk_frequencies[] = {
5478         { .freq = 308570, .vco = 8640 },
5479         { .freq = 337500, .vco = 8100 },
5480         { .freq = 432000, .vco = 8640 },
5481         { .freq = 450000, .vco = 8100 },
5482         { .freq = 540000, .vco = 8100 },
5483         { .freq = 617140, .vco = 8640 },
5484         { .freq = 675000, .vco = 8100 },
5485 };
5486
5487 static unsigned int skl_cdclk_decimal(unsigned int freq)
5488 {
5489         return (freq - 1000) / 500;
5490 }
5491
5492 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5493 {
5494         unsigned int i;
5495
5496         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5497                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5498
5499                 if (e->freq == freq)
5500                         return e->vco;
5501         }
5502
5503         return 8100;
5504 }
5505
5506 static void
5507 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5508 {
5509         unsigned int min_freq;
5510         u32 val;
5511
5512         /* select the minimum CDCLK before enabling DPLL 0 */
5513         val = I915_READ(CDCLK_CTL);
5514         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5515         val |= CDCLK_FREQ_337_308;
5516
5517         if (required_vco == 8640)
5518                 min_freq = 308570;
5519         else
5520                 min_freq = 337500;
5521
5522         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5523
5524         I915_WRITE(CDCLK_CTL, val);
5525         POSTING_READ(CDCLK_CTL);
5526
5527         /*
5528          * We always enable DPLL0 with the lowest link rate possible, but still
5529          * taking into account the VCO required to operate the eDP panel at the
5530          * desired frequency. The usual DP link rates operate with a VCO of
5531          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5532          * The modeset code is responsible for the selection of the exact link
5533          * rate later on, with the constraint of choosing a frequency that
5534          * works with required_vco.
5535          */
5536         val = I915_READ(DPLL_CTRL1);
5537
5538         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5539                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5540         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5541         if (required_vco == 8640)
5542                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5543                                             SKL_DPLL0);
5544         else
5545                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5546                                             SKL_DPLL0);
5547
5548         I915_WRITE(DPLL_CTRL1, val);
5549         POSTING_READ(DPLL_CTRL1);
5550
5551         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5552
5553         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5554                 DRM_ERROR("DPLL0 not locked\n");
5555 }
5556
5557 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5558 {
5559         int ret;
5560         u32 val;
5561
5562         /* inform PCU we want to change CDCLK */
5563         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5564         mutex_lock(&dev_priv->rps.hw_lock);
5565         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5566         mutex_unlock(&dev_priv->rps.hw_lock);
5567
5568         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5569 }
5570
5571 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5572 {
5573         unsigned int i;
5574
5575         for (i = 0; i < 15; i++) {
5576                 if (skl_cdclk_pcu_ready(dev_priv))
5577                         return true;
5578                 udelay(10);
5579         }
5580
5581         return false;
5582 }
5583
5584 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5585 {
5586         struct drm_device *dev = dev_priv->dev;
5587         u32 freq_select, pcu_ack;
5588
5589         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5590
5591         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5592                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5593                 return;
5594         }
5595
5596         /* set CDCLK_CTL */
5597         switch(freq) {
5598         case 450000:
5599         case 432000:
5600                 freq_select = CDCLK_FREQ_450_432;
5601                 pcu_ack = 1;
5602                 break;
5603         case 540000:
5604                 freq_select = CDCLK_FREQ_540;
5605                 pcu_ack = 2;
5606                 break;
5607         case 308570:
5608         case 337500:
5609         default:
5610                 freq_select = CDCLK_FREQ_337_308;
5611                 pcu_ack = 0;
5612                 break;
5613         case 617140:
5614         case 675000:
5615                 freq_select = CDCLK_FREQ_675_617;
5616                 pcu_ack = 3;
5617                 break;
5618         }
5619
5620         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5621         POSTING_READ(CDCLK_CTL);
5622
5623         /* inform PCU of the change */
5624         mutex_lock(&dev_priv->rps.hw_lock);
5625         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5626         mutex_unlock(&dev_priv->rps.hw_lock);
5627
5628         intel_update_cdclk(dev);
5629 }
5630
5631 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5632 {
5633         /* disable DBUF power */
5634         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5635         POSTING_READ(DBUF_CTL);
5636
5637         udelay(10);
5638
5639         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5640                 DRM_ERROR("DBuf power disable timeout\n");
5641
5642         /* disable DPLL0 */
5643         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5644         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5645                 DRM_ERROR("Couldn't disable DPLL0\n");
5646
5647         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5648 }
5649
5650 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5651 {
5652         u32 val;
5653         unsigned int required_vco;
5654
5655         /* enable PCH reset handshake */
5656         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5657         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5658
5659         /* enable PG1 and Misc I/O */
5660         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5661
5662         /* DPLL0 already enabed !? */
5663         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5664                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5665                 return;
5666         }
5667
5668         /* enable DPLL0 */
5669         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5670         skl_dpll0_enable(dev_priv, required_vco);
5671
5672         /* set CDCLK to the frequency the BIOS chose */
5673         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5674
5675         /* enable DBUF power */
5676         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5677         POSTING_READ(DBUF_CTL);
5678
5679         udelay(10);
5680
5681         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5682                 DRM_ERROR("DBuf power enable timeout\n");
5683 }
5684
5685 /* returns HPLL frequency in kHz */
5686 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5687 {
5688         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5689
5690         /* Obtain SKU information */
5691         mutex_lock(&dev_priv->sb_lock);
5692         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5693                 CCK_FUSE_HPLL_FREQ_MASK;
5694         mutex_unlock(&dev_priv->sb_lock);
5695
5696         return vco_freq[hpll_freq] * 1000;
5697 }
5698
5699 /* Adjust CDclk dividers to allow high res or save power if possible */
5700 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5701 {
5702         struct drm_i915_private *dev_priv = dev->dev_private;
5703         u32 val, cmd;
5704
5705         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5706                                         != dev_priv->cdclk_freq);
5707
5708         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5709                 cmd = 2;
5710         else if (cdclk == 266667)
5711                 cmd = 1;
5712         else
5713                 cmd = 0;
5714
5715         mutex_lock(&dev_priv->rps.hw_lock);
5716         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5717         val &= ~DSPFREQGUAR_MASK;
5718         val |= (cmd << DSPFREQGUAR_SHIFT);
5719         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5720         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5721                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5722                      50)) {
5723                 DRM_ERROR("timed out waiting for CDclk change\n");
5724         }
5725         mutex_unlock(&dev_priv->rps.hw_lock);
5726
5727         mutex_lock(&dev_priv->sb_lock);
5728
5729         if (cdclk == 400000) {
5730                 u32 divider;
5731
5732                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5733
5734                 /* adjust cdclk divider */
5735                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5736                 val &= ~DISPLAY_FREQUENCY_VALUES;
5737                 val |= divider;
5738                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5739
5740                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5741                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5742                              50))
5743                         DRM_ERROR("timed out waiting for CDclk change\n");
5744         }
5745
5746         /* adjust self-refresh exit latency value */
5747         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5748         val &= ~0x7f;
5749
5750         /*
5751          * For high bandwidth configs, we set a higher latency in the bunit
5752          * so that the core display fetch happens in time to avoid underruns.
5753          */
5754         if (cdclk == 400000)
5755                 val |= 4500 / 250; /* 4.5 usec */
5756         else
5757                 val |= 3000 / 250; /* 3.0 usec */
5758         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5759
5760         mutex_unlock(&dev_priv->sb_lock);
5761
5762         intel_update_cdclk(dev);
5763 }
5764
5765 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5766 {
5767         struct drm_i915_private *dev_priv = dev->dev_private;
5768         u32 val, cmd;
5769
5770         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5771                                                 != dev_priv->cdclk_freq);
5772
5773         switch (cdclk) {
5774         case 333333:
5775         case 320000:
5776         case 266667:
5777         case 200000:
5778                 break;
5779         default:
5780                 MISSING_CASE(cdclk);
5781                 return;
5782         }
5783
5784         /*
5785          * Specs are full of misinformation, but testing on actual
5786          * hardware has shown that we just need to write the desired
5787          * CCK divider into the Punit register.
5788          */
5789         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5790
5791         mutex_lock(&dev_priv->rps.hw_lock);
5792         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5793         val &= ~DSPFREQGUAR_MASK_CHV;
5794         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5795         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5796         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5797                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5798                      50)) {
5799                 DRM_ERROR("timed out waiting for CDclk change\n");
5800         }
5801         mutex_unlock(&dev_priv->rps.hw_lock);
5802
5803         intel_update_cdclk(dev);
5804 }
5805
5806 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5807                                  int max_pixclk)
5808 {
5809         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5810         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5811
5812         /*
5813          * Really only a few cases to deal with, as only 4 CDclks are supported:
5814          *   200MHz
5815          *   267MHz
5816          *   320/333MHz (depends on HPLL freq)
5817          *   400MHz (VLV only)
5818          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5819          * of the lower bin and adjust if needed.
5820          *
5821          * We seem to get an unstable or solid color picture at 200MHz.
5822          * Not sure what's wrong. For now use 200MHz only when all pipes
5823          * are off.
5824          */
5825         if (!IS_CHERRYVIEW(dev_priv) &&
5826             max_pixclk > freq_320*limit/100)
5827                 return 400000;
5828         else if (max_pixclk > 266667*limit/100)
5829                 return freq_320;
5830         else if (max_pixclk > 0)
5831                 return 266667;
5832         else
5833                 return 200000;
5834 }
5835
5836 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5837                               int max_pixclk)
5838 {
5839         /*
5840          * FIXME:
5841          * - remove the guardband, it's not needed on BXT
5842          * - set 19.2MHz bypass frequency if there are no active pipes
5843          */
5844         if (max_pixclk > 576000*9/10)
5845                 return 624000;
5846         else if (max_pixclk > 384000*9/10)
5847                 return 576000;
5848         else if (max_pixclk > 288000*9/10)
5849                 return 384000;
5850         else if (max_pixclk > 144000*9/10)
5851                 return 288000;
5852         else
5853                 return 144000;
5854 }
5855
5856 /* Compute the max pixel clock for new configuration. Uses atomic state if
5857  * that's non-NULL, look at current state otherwise. */
5858 static int intel_mode_max_pixclk(struct drm_device *dev,
5859                                  struct drm_atomic_state *state)
5860 {
5861         struct intel_crtc *intel_crtc;
5862         struct intel_crtc_state *crtc_state;
5863         int max_pixclk = 0;
5864
5865         for_each_intel_crtc(dev, intel_crtc) {
5866                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5867                 if (IS_ERR(crtc_state))
5868                         return PTR_ERR(crtc_state);
5869
5870                 if (!crtc_state->base.enable)
5871                         continue;
5872
5873                 max_pixclk = max(max_pixclk,
5874                                  crtc_state->base.adjusted_mode.crtc_clock);
5875         }
5876
5877         return max_pixclk;
5878 }
5879
5880 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5881 {
5882         struct drm_device *dev = state->dev;
5883         struct drm_i915_private *dev_priv = dev->dev_private;
5884         int max_pixclk = intel_mode_max_pixclk(dev, state);
5885
5886         if (max_pixclk < 0)
5887                 return max_pixclk;
5888
5889         to_intel_atomic_state(state)->cdclk =
5890                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5891
5892         return 0;
5893 }
5894
5895 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5896 {
5897         struct drm_device *dev = state->dev;
5898         struct drm_i915_private *dev_priv = dev->dev_private;
5899         int max_pixclk = intel_mode_max_pixclk(dev, state);
5900
5901         if (max_pixclk < 0)
5902                 return max_pixclk;
5903
5904         to_intel_atomic_state(state)->cdclk =
5905                 broxton_calc_cdclk(dev_priv, max_pixclk);
5906
5907         return 0;
5908 }
5909
5910 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5911 {
5912         unsigned int credits, default_credits;
5913
5914         if (IS_CHERRYVIEW(dev_priv))
5915                 default_credits = PFI_CREDIT(12);
5916         else
5917                 default_credits = PFI_CREDIT(8);
5918
5919         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5920                 /* CHV suggested value is 31 or 63 */
5921                 if (IS_CHERRYVIEW(dev_priv))
5922                         credits = PFI_CREDIT_63;
5923                 else
5924                         credits = PFI_CREDIT(15);
5925         } else {
5926                 credits = default_credits;
5927         }
5928
5929         /*
5930          * WA - write default credits before re-programming
5931          * FIXME: should we also set the resend bit here?
5932          */
5933         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5934                    default_credits);
5935
5936         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5937                    credits | PFI_CREDIT_RESEND);
5938
5939         /*
5940          * FIXME is this guaranteed to clear
5941          * immediately or should we poll for it?
5942          */
5943         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5944 }
5945
5946 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5947 {
5948         struct drm_device *dev = old_state->dev;
5949         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951
5952         /*
5953          * FIXME: We can end up here with all power domains off, yet
5954          * with a CDCLK frequency other than the minimum. To account
5955          * for this take the PIPE-A power domain, which covers the HW
5956          * blocks needed for the following programming. This can be
5957          * removed once it's guaranteed that we get here either with
5958          * the minimum CDCLK set, or the required power domains
5959          * enabled.
5960          */
5961         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5962
5963         if (IS_CHERRYVIEW(dev))
5964                 cherryview_set_cdclk(dev, req_cdclk);
5965         else
5966                 valleyview_set_cdclk(dev, req_cdclk);
5967
5968         vlv_program_pfi_credits(dev_priv);
5969
5970         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5971 }
5972
5973 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5974 {
5975         struct drm_device *dev = crtc->dev;
5976         struct drm_i915_private *dev_priv = to_i915(dev);
5977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5978         struct intel_encoder *encoder;
5979         int pipe = intel_crtc->pipe;
5980         bool is_dsi;
5981
5982         if (WARN_ON(intel_crtc->active))
5983                 return;
5984
5985         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5986
5987         if (!is_dsi) {
5988                 if (IS_CHERRYVIEW(dev))
5989                         chv_prepare_pll(intel_crtc, intel_crtc->config);
5990                 else
5991                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
5992         }
5993
5994         if (intel_crtc->config->has_dp_encoder)
5995                 intel_dp_set_m_n(intel_crtc, M1_N1);
5996
5997         intel_set_pipe_timings(intel_crtc);
5998
5999         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6000                 struct drm_i915_private *dev_priv = dev->dev_private;
6001
6002                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6003                 I915_WRITE(CHV_CANVAS(pipe), 0);
6004         }
6005
6006         i9xx_set_pipeconf(intel_crtc);
6007
6008         intel_crtc->active = true;
6009
6010         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6011
6012         for_each_encoder_on_crtc(dev, crtc, encoder)
6013                 if (encoder->pre_pll_enable)
6014                         encoder->pre_pll_enable(encoder);
6015
6016         if (!is_dsi) {
6017                 if (IS_CHERRYVIEW(dev))
6018                         chv_enable_pll(intel_crtc, intel_crtc->config);
6019                 else
6020                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6021         }
6022
6023         for_each_encoder_on_crtc(dev, crtc, encoder)
6024                 if (encoder->pre_enable)
6025                         encoder->pre_enable(encoder);
6026
6027         i9xx_pfit_enable(intel_crtc);
6028
6029         intel_crtc_load_lut(crtc);
6030
6031         intel_enable_pipe(intel_crtc);
6032
6033         assert_vblank_disabled(crtc);
6034         drm_crtc_vblank_on(crtc);
6035
6036         for_each_encoder_on_crtc(dev, crtc, encoder)
6037                 encoder->enable(encoder);
6038 }
6039
6040 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6041 {
6042         struct drm_device *dev = crtc->base.dev;
6043         struct drm_i915_private *dev_priv = dev->dev_private;
6044
6045         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6046         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6047 }
6048
6049 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6050 {
6051         struct drm_device *dev = crtc->dev;
6052         struct drm_i915_private *dev_priv = to_i915(dev);
6053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6054         struct intel_encoder *encoder;
6055         int pipe = intel_crtc->pipe;
6056
6057         if (WARN_ON(intel_crtc->active))
6058                 return;
6059
6060         i9xx_set_pll_dividers(intel_crtc);
6061
6062         if (intel_crtc->config->has_dp_encoder)
6063                 intel_dp_set_m_n(intel_crtc, M1_N1);
6064
6065         intel_set_pipe_timings(intel_crtc);
6066
6067         i9xx_set_pipeconf(intel_crtc);
6068
6069         intel_crtc->active = true;
6070
6071         if (!IS_GEN2(dev))
6072                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6073
6074         for_each_encoder_on_crtc(dev, crtc, encoder)
6075                 if (encoder->pre_enable)
6076                         encoder->pre_enable(encoder);
6077
6078         i9xx_enable_pll(intel_crtc);
6079
6080         i9xx_pfit_enable(intel_crtc);
6081
6082         intel_crtc_load_lut(crtc);
6083
6084         intel_update_watermarks(crtc);
6085         intel_enable_pipe(intel_crtc);
6086
6087         assert_vblank_disabled(crtc);
6088         drm_crtc_vblank_on(crtc);
6089
6090         for_each_encoder_on_crtc(dev, crtc, encoder)
6091                 encoder->enable(encoder);
6092 }
6093
6094 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6095 {
6096         struct drm_device *dev = crtc->base.dev;
6097         struct drm_i915_private *dev_priv = dev->dev_private;
6098
6099         if (!crtc->config->gmch_pfit.control)
6100                 return;
6101
6102         assert_pipe_disabled(dev_priv, crtc->pipe);
6103
6104         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6105                          I915_READ(PFIT_CONTROL));
6106         I915_WRITE(PFIT_CONTROL, 0);
6107 }
6108
6109 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6110 {
6111         struct drm_device *dev = crtc->dev;
6112         struct drm_i915_private *dev_priv = dev->dev_private;
6113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6114         struct intel_encoder *encoder;
6115         int pipe = intel_crtc->pipe;
6116
6117         /*
6118          * On gen2 planes are double buffered but the pipe isn't, so we must
6119          * wait for planes to fully turn off before disabling the pipe.
6120          * We also need to wait on all gmch platforms because of the
6121          * self-refresh mode constraint explained above.
6122          */
6123         intel_wait_for_vblank(dev, pipe);
6124
6125         for_each_encoder_on_crtc(dev, crtc, encoder)
6126                 encoder->disable(encoder);
6127
6128         drm_crtc_vblank_off(crtc);
6129         assert_vblank_disabled(crtc);
6130
6131         intel_disable_pipe(intel_crtc);
6132
6133         i9xx_pfit_disable(intel_crtc);
6134
6135         for_each_encoder_on_crtc(dev, crtc, encoder)
6136                 if (encoder->post_disable)
6137                         encoder->post_disable(encoder);
6138
6139         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6140                 if (IS_CHERRYVIEW(dev))
6141                         chv_disable_pll(dev_priv, pipe);
6142                 else if (IS_VALLEYVIEW(dev))
6143                         vlv_disable_pll(dev_priv, pipe);
6144                 else
6145                         i9xx_disable_pll(intel_crtc);
6146         }
6147
6148         if (!IS_GEN2(dev))
6149                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6150 }
6151
6152 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6153 {
6154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6156         enum intel_display_power_domain domain;
6157         unsigned long domains;
6158
6159         if (!intel_crtc->active)
6160                 return;
6161
6162         if (to_intel_plane_state(crtc->primary->state)->visible) {
6163                 intel_crtc_wait_for_pending_flips(crtc);
6164                 intel_pre_disable_primary(crtc);
6165         }
6166
6167         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6168         dev_priv->display.crtc_disable(crtc);
6169
6170         domains = intel_crtc->enabled_power_domains;
6171         for_each_power_domain(domain, domains)
6172                 intel_display_power_put(dev_priv, domain);
6173         intel_crtc->enabled_power_domains = 0;
6174 }
6175
6176 /*
6177  * turn all crtc's off, but do not adjust state
6178  * This has to be paired with a call to intel_modeset_setup_hw_state.
6179  */
6180 void intel_display_suspend(struct drm_device *dev)
6181 {
6182         struct drm_crtc *crtc;
6183
6184         for_each_crtc(dev, crtc)
6185                 intel_crtc_disable_noatomic(crtc);
6186 }
6187
6188 /* Master function to enable/disable CRTC and corresponding power wells */
6189 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6190 {
6191         struct drm_device *dev = crtc->dev;
6192         struct drm_mode_config *config = &dev->mode_config;
6193         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195         struct intel_crtc_state *pipe_config;
6196         struct drm_atomic_state *state;
6197         int ret;
6198
6199         if (enable == intel_crtc->active)
6200                 return 0;
6201
6202         if (enable && !crtc->state->enable)
6203                 return 0;
6204
6205         /* this function should be called with drm_modeset_lock_all for now */
6206         if (WARN_ON(!ctx))
6207                 return -EIO;
6208         lockdep_assert_held(&ctx->ww_ctx);
6209
6210         state = drm_atomic_state_alloc(dev);
6211         if (WARN_ON(!state))
6212                 return -ENOMEM;
6213
6214         state->acquire_ctx = ctx;
6215         state->allow_modeset = true;
6216
6217         pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6218         if (IS_ERR(pipe_config)) {
6219                 ret = PTR_ERR(pipe_config);
6220                 goto err;
6221         }
6222         pipe_config->base.active = enable;
6223
6224         ret = intel_set_mode(state);
6225         if (!ret)
6226                 return ret;
6227
6228 err:
6229         DRM_ERROR("Updating crtc active failed with %i\n", ret);
6230         drm_atomic_state_free(state);
6231         return ret;
6232 }
6233
6234 /**
6235  * Sets the power management mode of the pipe and plane.
6236  */
6237 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6238 {
6239         struct drm_device *dev = crtc->dev;
6240         struct intel_encoder *intel_encoder;
6241         bool enable = false;
6242
6243         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6244                 enable |= intel_encoder->connectors_active;
6245
6246         intel_crtc_control(crtc, enable);
6247 }
6248
6249 void intel_encoder_destroy(struct drm_encoder *encoder)
6250 {
6251         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6252
6253         drm_encoder_cleanup(encoder);
6254         kfree(intel_encoder);
6255 }
6256
6257 /* Simple dpms helper for encoders with just one connector, no cloning and only
6258  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6259  * state of the entire output pipe. */
6260 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6261 {
6262         if (mode == DRM_MODE_DPMS_ON) {
6263                 encoder->connectors_active = true;
6264
6265                 intel_crtc_update_dpms(encoder->base.crtc);
6266         } else {
6267                 encoder->connectors_active = false;
6268
6269                 intel_crtc_update_dpms(encoder->base.crtc);
6270         }
6271 }
6272
6273 /* Cross check the actual hw state with our own modeset state tracking (and it's
6274  * internal consistency). */
6275 static void intel_connector_check_state(struct intel_connector *connector)
6276 {
6277         if (connector->get_hw_state(connector)) {
6278                 struct intel_encoder *encoder = connector->encoder;
6279                 struct drm_crtc *crtc;
6280                 bool encoder_enabled;
6281                 enum pipe pipe;
6282
6283                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6284                               connector->base.base.id,
6285                               connector->base.name);
6286
6287                 /* there is no real hw state for MST connectors */
6288                 if (connector->mst_port)
6289                         return;
6290
6291                 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6292                      "wrong connector dpms state\n");
6293                 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6294                      "active connector not linked to encoder\n");
6295
6296                 if (encoder) {
6297                         I915_STATE_WARN(!encoder->connectors_active,
6298                              "encoder->connectors_active not set\n");
6299
6300                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6301                         I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6302                         if (I915_STATE_WARN_ON(!encoder->base.crtc))
6303                                 return;
6304
6305                         crtc = encoder->base.crtc;
6306
6307                         I915_STATE_WARN(!crtc->state->enable,
6308                                         "crtc not enabled\n");
6309                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6310                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6311                              "encoder active on the wrong pipe\n");
6312                 }
6313         }
6314 }
6315
6316 int intel_connector_init(struct intel_connector *connector)
6317 {
6318         struct drm_connector_state *connector_state;
6319
6320         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6321         if (!connector_state)
6322                 return -ENOMEM;
6323
6324         connector->base.state = connector_state;
6325         return 0;
6326 }
6327
6328 struct intel_connector *intel_connector_alloc(void)
6329 {
6330         struct intel_connector *connector;
6331
6332         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6333         if (!connector)
6334                 return NULL;
6335
6336         if (intel_connector_init(connector) < 0) {
6337                 kfree(connector);
6338                 return NULL;
6339         }
6340
6341         return connector;
6342 }
6343
6344 /* Even simpler default implementation, if there's really no special case to
6345  * consider. */
6346 void intel_connector_dpms(struct drm_connector *connector, int mode)
6347 {
6348         /* All the simple cases only support two dpms states. */
6349         if (mode != DRM_MODE_DPMS_ON)
6350                 mode = DRM_MODE_DPMS_OFF;
6351
6352         if (mode == connector->dpms)
6353                 return;
6354
6355         connector->dpms = mode;
6356
6357         /* Only need to change hw state when actually enabled */
6358         if (connector->encoder)
6359                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6360
6361         intel_modeset_check_state(connector->dev);
6362 }
6363
6364 /* Simple connector->get_hw_state implementation for encoders that support only
6365  * one connector and no cloning and hence the encoder state determines the state
6366  * of the connector. */
6367 bool intel_connector_get_hw_state(struct intel_connector *connector)
6368 {
6369         enum pipe pipe = 0;
6370         struct intel_encoder *encoder = connector->encoder;
6371
6372         return encoder->get_hw_state(encoder, &pipe);
6373 }
6374
6375 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6376 {
6377         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6378                 return crtc_state->fdi_lanes;
6379
6380         return 0;
6381 }
6382
6383 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6384                                      struct intel_crtc_state *pipe_config)
6385 {
6386         struct drm_atomic_state *state = pipe_config->base.state;
6387         struct intel_crtc *other_crtc;
6388         struct intel_crtc_state *other_crtc_state;
6389
6390         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6391                       pipe_name(pipe), pipe_config->fdi_lanes);
6392         if (pipe_config->fdi_lanes > 4) {
6393                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6394                               pipe_name(pipe), pipe_config->fdi_lanes);
6395                 return -EINVAL;
6396         }
6397
6398         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6399                 if (pipe_config->fdi_lanes > 2) {
6400                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6401                                       pipe_config->fdi_lanes);
6402                         return -EINVAL;
6403                 } else {
6404                         return 0;
6405                 }
6406         }
6407
6408         if (INTEL_INFO(dev)->num_pipes == 2)
6409                 return 0;
6410
6411         /* Ivybridge 3 pipe is really complicated */
6412         switch (pipe) {
6413         case PIPE_A:
6414                 return 0;
6415         case PIPE_B:
6416                 if (pipe_config->fdi_lanes <= 2)
6417                         return 0;
6418
6419                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6420                 other_crtc_state =
6421                         intel_atomic_get_crtc_state(state, other_crtc);
6422                 if (IS_ERR(other_crtc_state))
6423                         return PTR_ERR(other_crtc_state);
6424
6425                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6426                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6427                                       pipe_name(pipe), pipe_config->fdi_lanes);
6428                         return -EINVAL;
6429                 }
6430                 return 0;
6431         case PIPE_C:
6432                 if (pipe_config->fdi_lanes > 2) {
6433                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6434                                       pipe_name(pipe), pipe_config->fdi_lanes);
6435                         return -EINVAL;
6436                 }
6437
6438                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6439                 other_crtc_state =
6440                         intel_atomic_get_crtc_state(state, other_crtc);
6441                 if (IS_ERR(other_crtc_state))
6442                         return PTR_ERR(other_crtc_state);
6443
6444                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6445                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6446                         return -EINVAL;
6447                 }
6448                 return 0;
6449         default:
6450                 BUG();
6451         }
6452 }
6453
6454 #define RETRY 1
6455 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6456                                        struct intel_crtc_state *pipe_config)
6457 {
6458         struct drm_device *dev = intel_crtc->base.dev;
6459         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6460         int lane, link_bw, fdi_dotclock, ret;
6461         bool needs_recompute = false;
6462
6463 retry:
6464         /* FDI is a binary signal running at ~2.7GHz, encoding
6465          * each output octet as 10 bits. The actual frequency
6466          * is stored as a divider into a 100MHz clock, and the
6467          * mode pixel clock is stored in units of 1KHz.
6468          * Hence the bw of each lane in terms of the mode signal
6469          * is:
6470          */
6471         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6472
6473         fdi_dotclock = adjusted_mode->crtc_clock;
6474
6475         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6476                                            pipe_config->pipe_bpp);
6477
6478         pipe_config->fdi_lanes = lane;
6479
6480         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6481                                link_bw, &pipe_config->fdi_m_n);
6482
6483         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6484                                        intel_crtc->pipe, pipe_config);
6485         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6486                 pipe_config->pipe_bpp -= 2*3;
6487                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6488                               pipe_config->pipe_bpp);
6489                 needs_recompute = true;
6490                 pipe_config->bw_constrained = true;
6491
6492                 goto retry;
6493         }
6494
6495         if (needs_recompute)
6496                 return RETRY;
6497
6498         return ret;
6499 }
6500
6501 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6502                                      struct intel_crtc_state *pipe_config)
6503 {
6504         if (pipe_config->pipe_bpp > 24)
6505                 return false;
6506
6507         /* HSW can handle pixel rate up to cdclk? */
6508         if (IS_HASWELL(dev_priv->dev))
6509                 return true;
6510
6511         /*
6512          * We compare against max which means we must take
6513          * the increased cdclk requirement into account when
6514          * calculating the new cdclk.
6515          *
6516          * Should measure whether using a lower cdclk w/o IPS
6517          */
6518         return ilk_pipe_pixel_rate(pipe_config) <=
6519                 dev_priv->max_cdclk_freq * 95 / 100;
6520 }
6521
6522 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6523                                    struct intel_crtc_state *pipe_config)
6524 {
6525         struct drm_device *dev = crtc->base.dev;
6526         struct drm_i915_private *dev_priv = dev->dev_private;
6527
6528         pipe_config->ips_enabled = i915.enable_ips &&
6529                 hsw_crtc_supports_ips(crtc) &&
6530                 pipe_config_supports_ips(dev_priv, pipe_config);
6531 }
6532
6533 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6534                                      struct intel_crtc_state *pipe_config)
6535 {
6536         struct drm_device *dev = crtc->base.dev;
6537         struct drm_i915_private *dev_priv = dev->dev_private;
6538         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6539
6540         /* FIXME should check pixel clock limits on all platforms */
6541         if (INTEL_INFO(dev)->gen < 4) {
6542                 int clock_limit = dev_priv->max_cdclk_freq;
6543
6544                 /*
6545                  * Enable pixel doubling when the dot clock
6546                  * is > 90% of the (display) core speed.
6547                  *
6548                  * GDG double wide on either pipe,
6549                  * otherwise pipe A only.
6550                  */
6551                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6552                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6553                         clock_limit *= 2;
6554                         pipe_config->double_wide = true;
6555                 }
6556
6557                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6558                         return -EINVAL;
6559         }
6560
6561         /*
6562          * Pipe horizontal size must be even in:
6563          * - DVO ganged mode
6564          * - LVDS dual channel mode
6565          * - Double wide pipe
6566          */
6567         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6568              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6569                 pipe_config->pipe_src_w &= ~1;
6570
6571         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6572          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6573          */
6574         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6575                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6576                 return -EINVAL;
6577
6578         if (HAS_IPS(dev))
6579                 hsw_compute_ips_config(crtc, pipe_config);
6580
6581         if (pipe_config->has_pch_encoder)
6582                 return ironlake_fdi_compute_config(crtc, pipe_config);
6583
6584         return 0;
6585 }
6586
6587 static int skylake_get_display_clock_speed(struct drm_device *dev)
6588 {
6589         struct drm_i915_private *dev_priv = to_i915(dev);
6590         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6591         uint32_t cdctl = I915_READ(CDCLK_CTL);
6592         uint32_t linkrate;
6593
6594         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6595                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6596
6597         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6598                 return 540000;
6599
6600         linkrate = (I915_READ(DPLL_CTRL1) &
6601                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6602
6603         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6604             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6605                 /* vco 8640 */
6606                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6607                 case CDCLK_FREQ_450_432:
6608                         return 432000;
6609                 case CDCLK_FREQ_337_308:
6610                         return 308570;
6611                 case CDCLK_FREQ_675_617:
6612                         return 617140;
6613                 default:
6614                         WARN(1, "Unknown cd freq selection\n");
6615                 }
6616         } else {
6617                 /* vco 8100 */
6618                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6619                 case CDCLK_FREQ_450_432:
6620                         return 450000;
6621                 case CDCLK_FREQ_337_308:
6622                         return 337500;
6623                 case CDCLK_FREQ_675_617:
6624                         return 675000;
6625                 default:
6626                         WARN(1, "Unknown cd freq selection\n");
6627                 }
6628         }
6629
6630         /* error case, do as if DPLL0 isn't enabled */
6631         return 24000;
6632 }
6633
6634 static int broxton_get_display_clock_speed(struct drm_device *dev)
6635 {
6636         struct drm_i915_private *dev_priv = to_i915(dev);
6637         uint32_t cdctl = I915_READ(CDCLK_CTL);
6638         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6639         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6640         int cdclk;
6641
6642         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6643                 return 19200;
6644
6645         cdclk = 19200 * pll_ratio / 2;
6646
6647         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6648         case BXT_CDCLK_CD2X_DIV_SEL_1:
6649                 return cdclk;  /* 576MHz or 624MHz */
6650         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6651                 return cdclk * 2 / 3; /* 384MHz */
6652         case BXT_CDCLK_CD2X_DIV_SEL_2:
6653                 return cdclk / 2; /* 288MHz */
6654         case BXT_CDCLK_CD2X_DIV_SEL_4:
6655                 return cdclk / 4; /* 144MHz */
6656         }
6657
6658         /* error case, do as if DE PLL isn't enabled */
6659         return 19200;
6660 }
6661
6662 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6663 {
6664         struct drm_i915_private *dev_priv = dev->dev_private;
6665         uint32_t lcpll = I915_READ(LCPLL_CTL);
6666         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667
6668         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669                 return 800000;
6670         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671                 return 450000;
6672         else if (freq == LCPLL_CLK_FREQ_450)
6673                 return 450000;
6674         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6675                 return 540000;
6676         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6677                 return 337500;
6678         else
6679                 return 675000;
6680 }
6681
6682 static int haswell_get_display_clock_speed(struct drm_device *dev)
6683 {
6684         struct drm_i915_private *dev_priv = dev->dev_private;
6685         uint32_t lcpll = I915_READ(LCPLL_CTL);
6686         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687
6688         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689                 return 800000;
6690         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691                 return 450000;
6692         else if (freq == LCPLL_CLK_FREQ_450)
6693                 return 450000;
6694         else if (IS_HSW_ULT(dev))
6695                 return 337500;
6696         else
6697                 return 540000;
6698 }
6699
6700 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6701 {
6702         struct drm_i915_private *dev_priv = dev->dev_private;
6703         u32 val;
6704         int divider;
6705
6706         if (dev_priv->hpll_freq == 0)
6707                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6708
6709         mutex_lock(&dev_priv->sb_lock);
6710         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6711         mutex_unlock(&dev_priv->sb_lock);
6712
6713         divider = val & DISPLAY_FREQUENCY_VALUES;
6714
6715         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6716              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6717              "cdclk change in progress\n");
6718
6719         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6720 }
6721
6722 static int ilk_get_display_clock_speed(struct drm_device *dev)
6723 {
6724         return 450000;
6725 }
6726
6727 static int i945_get_display_clock_speed(struct drm_device *dev)
6728 {
6729         return 400000;
6730 }
6731
6732 static int i915_get_display_clock_speed(struct drm_device *dev)
6733 {
6734         return 333333;
6735 }
6736
6737 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6738 {
6739         return 200000;
6740 }
6741
6742 static int pnv_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         u16 gcfgc = 0;
6745
6746         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747
6748         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6749         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6750                 return 266667;
6751         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6752                 return 333333;
6753         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6754                 return 444444;
6755         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6756                 return 200000;
6757         default:
6758                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6759         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6760                 return 133333;
6761         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6762                 return 166667;
6763         }
6764 }
6765
6766 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         u16 gcfgc = 0;
6769
6770         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771
6772         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6773                 return 133333;
6774         else {
6775                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6776                 case GC_DISPLAY_CLOCK_333_MHZ:
6777                         return 333333;
6778                 default:
6779                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6780                         return 190000;
6781                 }
6782         }
6783 }
6784
6785 static int i865_get_display_clock_speed(struct drm_device *dev)
6786 {
6787         return 266667;
6788 }
6789
6790 static int i85x_get_display_clock_speed(struct drm_device *dev)
6791 {
6792         u16 hpllcc = 0;
6793
6794         /*
6795          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6796          * encoding is different :(
6797          * FIXME is this the right way to detect 852GM/852GMV?
6798          */
6799         if (dev->pdev->revision == 0x1)
6800                 return 133333;
6801
6802         pci_bus_read_config_word(dev->pdev->bus,
6803                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6804
6805         /* Assume that the hardware is in the high speed state.  This
6806          * should be the default.
6807          */
6808         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6809         case GC_CLOCK_133_200:
6810         case GC_CLOCK_133_200_2:
6811         case GC_CLOCK_100_200:
6812                 return 200000;
6813         case GC_CLOCK_166_250:
6814                 return 250000;
6815         case GC_CLOCK_100_133:
6816                 return 133333;
6817         case GC_CLOCK_133_266:
6818         case GC_CLOCK_133_266_2:
6819         case GC_CLOCK_166_266:
6820                 return 266667;
6821         }
6822
6823         /* Shouldn't happen */
6824         return 0;
6825 }
6826
6827 static int i830_get_display_clock_speed(struct drm_device *dev)
6828 {
6829         return 133333;
6830 }
6831
6832 static unsigned int intel_hpll_vco(struct drm_device *dev)
6833 {
6834         struct drm_i915_private *dev_priv = dev->dev_private;
6835         static const unsigned int blb_vco[8] = {
6836                 [0] = 3200000,
6837                 [1] = 4000000,
6838                 [2] = 5333333,
6839                 [3] = 4800000,
6840                 [4] = 6400000,
6841         };
6842         static const unsigned int pnv_vco[8] = {
6843                 [0] = 3200000,
6844                 [1] = 4000000,
6845                 [2] = 5333333,
6846                 [3] = 4800000,
6847                 [4] = 2666667,
6848         };
6849         static const unsigned int cl_vco[8] = {
6850                 [0] = 3200000,
6851                 [1] = 4000000,
6852                 [2] = 5333333,
6853                 [3] = 6400000,
6854                 [4] = 3333333,
6855                 [5] = 3566667,
6856                 [6] = 4266667,
6857         };
6858         static const unsigned int elk_vco[8] = {
6859                 [0] = 3200000,
6860                 [1] = 4000000,
6861                 [2] = 5333333,
6862                 [3] = 4800000,
6863         };
6864         static const unsigned int ctg_vco[8] = {
6865                 [0] = 3200000,
6866                 [1] = 4000000,
6867                 [2] = 5333333,
6868                 [3] = 6400000,
6869                 [4] = 2666667,
6870                 [5] = 4266667,
6871         };
6872         const unsigned int *vco_table;
6873         unsigned int vco;
6874         uint8_t tmp = 0;
6875
6876         /* FIXME other chipsets? */
6877         if (IS_GM45(dev))
6878                 vco_table = ctg_vco;
6879         else if (IS_G4X(dev))
6880                 vco_table = elk_vco;
6881         else if (IS_CRESTLINE(dev))
6882                 vco_table = cl_vco;
6883         else if (IS_PINEVIEW(dev))
6884                 vco_table = pnv_vco;
6885         else if (IS_G33(dev))
6886                 vco_table = blb_vco;
6887         else
6888                 return 0;
6889
6890         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6891
6892         vco = vco_table[tmp & 0x7];
6893         if (vco == 0)
6894                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6895         else
6896                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6897
6898         return vco;
6899 }
6900
6901 static int gm45_get_display_clock_speed(struct drm_device *dev)
6902 {
6903         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6904         uint16_t tmp = 0;
6905
6906         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907
6908         cdclk_sel = (tmp >> 12) & 0x1;
6909
6910         switch (vco) {
6911         case 2666667:
6912         case 4000000:
6913         case 5333333:
6914                 return cdclk_sel ? 333333 : 222222;
6915         case 3200000:
6916                 return cdclk_sel ? 320000 : 228571;
6917         default:
6918                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6919                 return 222222;
6920         }
6921 }
6922
6923 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6924 {
6925         static const uint8_t div_3200[] = { 16, 10,  8 };
6926         static const uint8_t div_4000[] = { 20, 12, 10 };
6927         static const uint8_t div_5333[] = { 24, 16, 14 };
6928         const uint8_t *div_table;
6929         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6930         uint16_t tmp = 0;
6931
6932         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933
6934         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6935
6936         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6937                 goto fail;
6938
6939         switch (vco) {
6940         case 3200000:
6941                 div_table = div_3200;
6942                 break;
6943         case 4000000:
6944                 div_table = div_4000;
6945                 break;
6946         case 5333333:
6947                 div_table = div_5333;
6948                 break;
6949         default:
6950                 goto fail;
6951         }
6952
6953         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6954
6955 fail:
6956         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6957         return 200000;
6958 }
6959
6960 static int g33_get_display_clock_speed(struct drm_device *dev)
6961 {
6962         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6963         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6964         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6965         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6966         const uint8_t *div_table;
6967         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6968         uint16_t tmp = 0;
6969
6970         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6971
6972         cdclk_sel = (tmp >> 4) & 0x7;
6973
6974         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6975                 goto fail;
6976
6977         switch (vco) {
6978         case 3200000:
6979                 div_table = div_3200;
6980                 break;
6981         case 4000000:
6982                 div_table = div_4000;
6983                 break;
6984         case 4800000:
6985                 div_table = div_4800;
6986                 break;
6987         case 5333333:
6988                 div_table = div_5333;
6989                 break;
6990         default:
6991                 goto fail;
6992         }
6993
6994         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6995
6996 fail:
6997         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6998         return 190476;
6999 }
7000
7001 static void
7002 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7003 {
7004         while (*num > DATA_LINK_M_N_MASK ||
7005                *den > DATA_LINK_M_N_MASK) {
7006                 *num >>= 1;
7007                 *den >>= 1;
7008         }
7009 }
7010
7011 static void compute_m_n(unsigned int m, unsigned int n,
7012                         uint32_t *ret_m, uint32_t *ret_n)
7013 {
7014         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7015         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7016         intel_reduce_m_n_ratio(ret_m, ret_n);
7017 }
7018
7019 void
7020 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7021                        int pixel_clock, int link_clock,
7022                        struct intel_link_m_n *m_n)
7023 {
7024         m_n->tu = 64;
7025
7026         compute_m_n(bits_per_pixel * pixel_clock,
7027                     link_clock * nlanes * 8,
7028                     &m_n->gmch_m, &m_n->gmch_n);
7029
7030         compute_m_n(pixel_clock, link_clock,
7031                     &m_n->link_m, &m_n->link_n);
7032 }
7033
7034 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7035 {
7036         if (i915.panel_use_ssc >= 0)
7037                 return i915.panel_use_ssc != 0;
7038         return dev_priv->vbt.lvds_use_ssc
7039                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7040 }
7041
7042 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7043                            int num_connectors)
7044 {
7045         struct drm_device *dev = crtc_state->base.crtc->dev;
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047         int refclk;
7048
7049         WARN_ON(!crtc_state->base.state);
7050
7051         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7052                 refclk = 100000;
7053         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7054             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7055                 refclk = dev_priv->vbt.lvds_ssc_freq;
7056                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7057         } else if (!IS_GEN2(dev)) {
7058                 refclk = 96000;
7059         } else {
7060                 refclk = 48000;
7061         }
7062
7063         return refclk;
7064 }
7065
7066 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7067 {
7068         return (1 << dpll->n) << 16 | dpll->m2;
7069 }
7070
7071 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7072 {
7073         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7074 }
7075
7076 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7077                                      struct intel_crtc_state *crtc_state,
7078                                      intel_clock_t *reduced_clock)
7079 {
7080         struct drm_device *dev = crtc->base.dev;
7081         u32 fp, fp2 = 0;
7082
7083         if (IS_PINEVIEW(dev)) {
7084                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7085                 if (reduced_clock)
7086                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7087         } else {
7088                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7089                 if (reduced_clock)
7090                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7091         }
7092
7093         crtc_state->dpll_hw_state.fp0 = fp;
7094
7095         crtc->lowfreq_avail = false;
7096         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7097             reduced_clock) {
7098                 crtc_state->dpll_hw_state.fp1 = fp2;
7099                 crtc->lowfreq_avail = true;
7100         } else {
7101                 crtc_state->dpll_hw_state.fp1 = fp;
7102         }
7103 }
7104
7105 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7106                 pipe)
7107 {
7108         u32 reg_val;
7109
7110         /*
7111          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7112          * and set it to a reasonable value instead.
7113          */
7114         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7115         reg_val &= 0xffffff00;
7116         reg_val |= 0x00000030;
7117         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7118
7119         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7120         reg_val &= 0x8cffffff;
7121         reg_val = 0x8c000000;
7122         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7123
7124         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7125         reg_val &= 0xffffff00;
7126         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7127
7128         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7129         reg_val &= 0x00ffffff;
7130         reg_val |= 0xb0000000;
7131         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7132 }
7133
7134 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7135                                          struct intel_link_m_n *m_n)
7136 {
7137         struct drm_device *dev = crtc->base.dev;
7138         struct drm_i915_private *dev_priv = dev->dev_private;
7139         int pipe = crtc->pipe;
7140
7141         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7143         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7144         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7145 }
7146
7147 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7148                                          struct intel_link_m_n *m_n,
7149                                          struct intel_link_m_n *m2_n2)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = dev->dev_private;
7153         int pipe = crtc->pipe;
7154         enum transcoder transcoder = crtc->config->cpu_transcoder;
7155
7156         if (INTEL_INFO(dev)->gen >= 5) {
7157                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7159                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7160                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7161                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7162                  * for gen < 8) and if DRRS is supported (to make sure the
7163                  * registers are not unnecessarily accessed).
7164                  */
7165                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7166                         crtc->config->has_drrs) {
7167                         I915_WRITE(PIPE_DATA_M2(transcoder),
7168                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7169                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7170                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7171                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7172                 }
7173         } else {
7174                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7176                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7177                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7178         }
7179 }
7180
7181 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7182 {
7183         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7184
7185         if (m_n == M1_N1) {
7186                 dp_m_n = &crtc->config->dp_m_n;
7187                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7188         } else if (m_n == M2_N2) {
7189
7190                 /*
7191                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7192                  * needs to be programmed into M1_N1.
7193                  */
7194                 dp_m_n = &crtc->config->dp_m2_n2;
7195         } else {
7196                 DRM_ERROR("Unsupported divider value\n");
7197                 return;
7198         }
7199
7200         if (crtc->config->has_pch_encoder)
7201                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7202         else
7203                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7204 }
7205
7206 static void vlv_compute_dpll(struct intel_crtc *crtc,
7207                              struct intel_crtc_state *pipe_config)
7208 {
7209         u32 dpll, dpll_md;
7210
7211         /*
7212          * Enable DPIO clock input. We should never disable the reference
7213          * clock for pipe B, since VGA hotplug / manual detection depends
7214          * on it.
7215          */
7216         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7217                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7218         /* We should never disable this, set it here for state tracking */
7219         if (crtc->pipe == PIPE_B)
7220                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7221         dpll |= DPLL_VCO_ENABLE;
7222         pipe_config->dpll_hw_state.dpll = dpll;
7223
7224         dpll_md = (pipe_config->pixel_multiplier - 1)
7225                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7226         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7227 }
7228
7229 static void vlv_prepare_pll(struct intel_crtc *crtc,
7230                             const struct intel_crtc_state *pipe_config)
7231 {
7232         struct drm_device *dev = crtc->base.dev;
7233         struct drm_i915_private *dev_priv = dev->dev_private;
7234         int pipe = crtc->pipe;
7235         u32 mdiv;
7236         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7237         u32 coreclk, reg_val;
7238
7239         mutex_lock(&dev_priv->sb_lock);
7240
7241         bestn = pipe_config->dpll.n;
7242         bestm1 = pipe_config->dpll.m1;
7243         bestm2 = pipe_config->dpll.m2;
7244         bestp1 = pipe_config->dpll.p1;
7245         bestp2 = pipe_config->dpll.p2;
7246
7247         /* See eDP HDMI DPIO driver vbios notes doc */
7248
7249         /* PLL B needs special handling */
7250         if (pipe == PIPE_B)
7251                 vlv_pllb_recal_opamp(dev_priv, pipe);
7252
7253         /* Set up Tx target for periodic Rcomp update */
7254         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7255
7256         /* Disable target IRef on PLL */
7257         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7258         reg_val &= 0x00ffffff;
7259         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7260
7261         /* Disable fast lock */
7262         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7263
7264         /* Set idtafcrecal before PLL is enabled */
7265         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7266         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7267         mdiv |= ((bestn << DPIO_N_SHIFT));
7268         mdiv |= (1 << DPIO_K_SHIFT);
7269
7270         /*
7271          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7272          * but we don't support that).
7273          * Note: don't use the DAC post divider as it seems unstable.
7274          */
7275         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7276         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7277
7278         mdiv |= DPIO_ENABLE_CALIBRATION;
7279         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7280
7281         /* Set HBR and RBR LPF coefficients */
7282         if (pipe_config->port_clock == 162000 ||
7283             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7284             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7285                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7286                                  0x009f0003);
7287         else
7288                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7289                                  0x00d0000f);
7290
7291         if (pipe_config->has_dp_encoder) {
7292                 /* Use SSC source */
7293                 if (pipe == PIPE_A)
7294                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7295                                          0x0df40000);
7296                 else
7297                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7298                                          0x0df70000);
7299         } else { /* HDMI or VGA */
7300                 /* Use bend source */
7301                 if (pipe == PIPE_A)
7302                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7303                                          0x0df70000);
7304                 else
7305                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7306                                          0x0df40000);
7307         }
7308
7309         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7310         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7311         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7312             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7313                 coreclk |= 0x01000000;
7314         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7315
7316         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7317         mutex_unlock(&dev_priv->sb_lock);
7318 }
7319
7320 static void chv_compute_dpll(struct intel_crtc *crtc,
7321                              struct intel_crtc_state *pipe_config)
7322 {
7323         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
7324                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7325                 DPLL_VCO_ENABLE;
7326         if (crtc->pipe != PIPE_A)
7327                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7328
7329         pipe_config->dpll_hw_state.dpll_md =
7330                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7331 }
7332
7333 static void chv_prepare_pll(struct intel_crtc *crtc,
7334                             const struct intel_crtc_state *pipe_config)
7335 {
7336         struct drm_device *dev = crtc->base.dev;
7337         struct drm_i915_private *dev_priv = dev->dev_private;
7338         int pipe = crtc->pipe;
7339         int dpll_reg = DPLL(crtc->pipe);
7340         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7341         u32 loopfilter, tribuf_calcntr;
7342         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7343         u32 dpio_val;
7344         int vco;
7345
7346         bestn = pipe_config->dpll.n;
7347         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7348         bestm1 = pipe_config->dpll.m1;
7349         bestm2 = pipe_config->dpll.m2 >> 22;
7350         bestp1 = pipe_config->dpll.p1;
7351         bestp2 = pipe_config->dpll.p2;
7352         vco = pipe_config->dpll.vco;
7353         dpio_val = 0;
7354         loopfilter = 0;
7355
7356         /*
7357          * Enable Refclk and SSC
7358          */
7359         I915_WRITE(dpll_reg,
7360                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7361
7362         mutex_lock(&dev_priv->sb_lock);
7363
7364         /* p1 and p2 divider */
7365         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7366                         5 << DPIO_CHV_S1_DIV_SHIFT |
7367                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7368                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7369                         1 << DPIO_CHV_K_DIV_SHIFT);
7370
7371         /* Feedback post-divider - m2 */
7372         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7373
7374         /* Feedback refclk divider - n and m1 */
7375         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7376                         DPIO_CHV_M1_DIV_BY_2 |
7377                         1 << DPIO_CHV_N_DIV_SHIFT);
7378
7379         /* M2 fraction division */
7380         if (bestm2_frac)
7381                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7382
7383         /* M2 fraction division enable */
7384         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7385         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7386         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7387         if (bestm2_frac)
7388                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7389         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7390
7391         /* Program digital lock detect threshold */
7392         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7393         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7394                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7395         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7396         if (!bestm2_frac)
7397                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7398         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7399
7400         /* Loop filter */
7401         if (vco == 5400000) {
7402                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7403                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7404                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405                 tribuf_calcntr = 0x9;
7406         } else if (vco <= 6200000) {
7407                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7408                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7409                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410                 tribuf_calcntr = 0x9;
7411         } else if (vco <= 6480000) {
7412                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7413                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7414                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7415                 tribuf_calcntr = 0x8;
7416         } else {
7417                 /* Not supported. Apply the same limits as in the max case */
7418                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7419                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7420                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421                 tribuf_calcntr = 0;
7422         }
7423         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7424
7425         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7426         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7427         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7428         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7429
7430         /* AFC Recal */
7431         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7432                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7433                         DPIO_AFC_RECAL);
7434
7435         mutex_unlock(&dev_priv->sb_lock);
7436 }
7437
7438 /**
7439  * vlv_force_pll_on - forcibly enable just the PLL
7440  * @dev_priv: i915 private structure
7441  * @pipe: pipe PLL to enable
7442  * @dpll: PLL configuration
7443  *
7444  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7445  * in cases where we need the PLL enabled even when @pipe is not going to
7446  * be enabled.
7447  */
7448 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7449                       const struct dpll *dpll)
7450 {
7451         struct intel_crtc *crtc =
7452                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7453         struct intel_crtc_state pipe_config = {
7454                 .base.crtc = &crtc->base,
7455                 .pixel_multiplier = 1,
7456                 .dpll = *dpll,
7457         };
7458
7459         if (IS_CHERRYVIEW(dev)) {
7460                 chv_compute_dpll(crtc, &pipe_config);
7461                 chv_prepare_pll(crtc, &pipe_config);
7462                 chv_enable_pll(crtc, &pipe_config);
7463         } else {
7464                 vlv_compute_dpll(crtc, &pipe_config);
7465                 vlv_prepare_pll(crtc, &pipe_config);
7466                 vlv_enable_pll(crtc, &pipe_config);
7467         }
7468 }
7469
7470 /**
7471  * vlv_force_pll_off - forcibly disable just the PLL
7472  * @dev_priv: i915 private structure
7473  * @pipe: pipe PLL to disable
7474  *
7475  * Disable the PLL for @pipe. To be used in cases where we need
7476  * the PLL enabled even when @pipe is not going to be enabled.
7477  */
7478 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7479 {
7480         if (IS_CHERRYVIEW(dev))
7481                 chv_disable_pll(to_i915(dev), pipe);
7482         else
7483                 vlv_disable_pll(to_i915(dev), pipe);
7484 }
7485
7486 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7487                               struct intel_crtc_state *crtc_state,
7488                               intel_clock_t *reduced_clock,
7489                               int num_connectors)
7490 {
7491         struct drm_device *dev = crtc->base.dev;
7492         struct drm_i915_private *dev_priv = dev->dev_private;
7493         u32 dpll;
7494         bool is_sdvo;
7495         struct dpll *clock = &crtc_state->dpll;
7496
7497         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7498
7499         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7500                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7501
7502         dpll = DPLL_VGA_MODE_DIS;
7503
7504         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7505                 dpll |= DPLLB_MODE_LVDS;
7506         else
7507                 dpll |= DPLLB_MODE_DAC_SERIAL;
7508
7509         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7510                 dpll |= (crtc_state->pixel_multiplier - 1)
7511                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7512         }
7513
7514         if (is_sdvo)
7515                 dpll |= DPLL_SDVO_HIGH_SPEED;
7516
7517         if (crtc_state->has_dp_encoder)
7518                 dpll |= DPLL_SDVO_HIGH_SPEED;
7519
7520         /* compute bitmask from p1 value */
7521         if (IS_PINEVIEW(dev))
7522                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7523         else {
7524                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7525                 if (IS_G4X(dev) && reduced_clock)
7526                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7527         }
7528         switch (clock->p2) {
7529         case 5:
7530                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7531                 break;
7532         case 7:
7533                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7534                 break;
7535         case 10:
7536                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7537                 break;
7538         case 14:
7539                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7540                 break;
7541         }
7542         if (INTEL_INFO(dev)->gen >= 4)
7543                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7544
7545         if (crtc_state->sdvo_tv_clock)
7546                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7547         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7548                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7549                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7550         else
7551                 dpll |= PLL_REF_INPUT_DREFCLK;
7552
7553         dpll |= DPLL_VCO_ENABLE;
7554         crtc_state->dpll_hw_state.dpll = dpll;
7555
7556         if (INTEL_INFO(dev)->gen >= 4) {
7557                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7558                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7559                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7560         }
7561 }
7562
7563 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7564                               struct intel_crtc_state *crtc_state,
7565                               intel_clock_t *reduced_clock,
7566                               int num_connectors)
7567 {
7568         struct drm_device *dev = crtc->base.dev;
7569         struct drm_i915_private *dev_priv = dev->dev_private;
7570         u32 dpll;
7571         struct dpll *clock = &crtc_state->dpll;
7572
7573         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7574
7575         dpll = DPLL_VGA_MODE_DIS;
7576
7577         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7578                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579         } else {
7580                 if (clock->p1 == 2)
7581                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7582                 else
7583                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584                 if (clock->p2 == 4)
7585                         dpll |= PLL_P2_DIVIDE_BY_4;
7586         }
7587
7588         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7589                 dpll |= DPLL_DVO_2X_MODE;
7590
7591         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7592                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7593                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7594         else
7595                 dpll |= PLL_REF_INPUT_DREFCLK;
7596
7597         dpll |= DPLL_VCO_ENABLE;
7598         crtc_state->dpll_hw_state.dpll = dpll;
7599 }
7600
7601 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7602 {
7603         struct drm_device *dev = intel_crtc->base.dev;
7604         struct drm_i915_private *dev_priv = dev->dev_private;
7605         enum pipe pipe = intel_crtc->pipe;
7606         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7607         struct drm_display_mode *adjusted_mode =
7608                 &intel_crtc->config->base.adjusted_mode;
7609         uint32_t crtc_vtotal, crtc_vblank_end;
7610         int vsyncshift = 0;
7611
7612         /* We need to be careful not to changed the adjusted mode, for otherwise
7613          * the hw state checker will get angry at the mismatch. */
7614         crtc_vtotal = adjusted_mode->crtc_vtotal;
7615         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7616
7617         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7618                 /* the chip adds 2 halflines automatically */
7619                 crtc_vtotal -= 1;
7620                 crtc_vblank_end -= 1;
7621
7622                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7623                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7624                 else
7625                         vsyncshift = adjusted_mode->crtc_hsync_start -
7626                                 adjusted_mode->crtc_htotal / 2;
7627                 if (vsyncshift < 0)
7628                         vsyncshift += adjusted_mode->crtc_htotal;
7629         }
7630
7631         if (INTEL_INFO(dev)->gen > 3)
7632                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7633
7634         I915_WRITE(HTOTAL(cpu_transcoder),
7635                    (adjusted_mode->crtc_hdisplay - 1) |
7636                    ((adjusted_mode->crtc_htotal - 1) << 16));
7637         I915_WRITE(HBLANK(cpu_transcoder),
7638                    (adjusted_mode->crtc_hblank_start - 1) |
7639                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7640         I915_WRITE(HSYNC(cpu_transcoder),
7641                    (adjusted_mode->crtc_hsync_start - 1) |
7642                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7643
7644         I915_WRITE(VTOTAL(cpu_transcoder),
7645                    (adjusted_mode->crtc_vdisplay - 1) |
7646                    ((crtc_vtotal - 1) << 16));
7647         I915_WRITE(VBLANK(cpu_transcoder),
7648                    (adjusted_mode->crtc_vblank_start - 1) |
7649                    ((crtc_vblank_end - 1) << 16));
7650         I915_WRITE(VSYNC(cpu_transcoder),
7651                    (adjusted_mode->crtc_vsync_start - 1) |
7652                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7653
7654         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7655          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7656          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7657          * bits. */
7658         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7659             (pipe == PIPE_B || pipe == PIPE_C))
7660                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7661
7662         /* pipesrc controls the size that is scaled from, which should
7663          * always be the user's requested size.
7664          */
7665         I915_WRITE(PIPESRC(pipe),
7666                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7667                    (intel_crtc->config->pipe_src_h - 1));
7668 }
7669
7670 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7671                                    struct intel_crtc_state *pipe_config)
7672 {
7673         struct drm_device *dev = crtc->base.dev;
7674         struct drm_i915_private *dev_priv = dev->dev_private;
7675         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7676         uint32_t tmp;
7677
7678         tmp = I915_READ(HTOTAL(cpu_transcoder));
7679         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7680         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7681         tmp = I915_READ(HBLANK(cpu_transcoder));
7682         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7683         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7684         tmp = I915_READ(HSYNC(cpu_transcoder));
7685         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7686         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7687
7688         tmp = I915_READ(VTOTAL(cpu_transcoder));
7689         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7690         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7691         tmp = I915_READ(VBLANK(cpu_transcoder));
7692         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7693         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7694         tmp = I915_READ(VSYNC(cpu_transcoder));
7695         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7696         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7697
7698         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7699                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7700                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7701                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7702         }
7703
7704         tmp = I915_READ(PIPESRC(crtc->pipe));
7705         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7706         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7707
7708         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7709         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7710 }
7711
7712 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7713                                  struct intel_crtc_state *pipe_config)
7714 {
7715         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7716         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7717         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7718         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7719
7720         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7721         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7722         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7723         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7724
7725         mode->flags = pipe_config->base.adjusted_mode.flags;
7726
7727         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7728         mode->flags |= pipe_config->base.adjusted_mode.flags;
7729 }
7730
7731 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7732 {
7733         struct drm_device *dev = intel_crtc->base.dev;
7734         struct drm_i915_private *dev_priv = dev->dev_private;
7735         uint32_t pipeconf;
7736
7737         pipeconf = 0;
7738
7739         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7740             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7741                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7742
7743         if (intel_crtc->config->double_wide)
7744                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7745
7746         /* only g4x and later have fancy bpc/dither controls */
7747         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7748                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7749                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7750                         pipeconf |= PIPECONF_DITHER_EN |
7751                                     PIPECONF_DITHER_TYPE_SP;
7752
7753                 switch (intel_crtc->config->pipe_bpp) {
7754                 case 18:
7755                         pipeconf |= PIPECONF_6BPC;
7756                         break;
7757                 case 24:
7758                         pipeconf |= PIPECONF_8BPC;
7759                         break;
7760                 case 30:
7761                         pipeconf |= PIPECONF_10BPC;
7762                         break;
7763                 default:
7764                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7765                         BUG();
7766                 }
7767         }
7768
7769         if (HAS_PIPE_CXSR(dev)) {
7770                 if (intel_crtc->lowfreq_avail) {
7771                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7772                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7773                 } else {
7774                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7775                 }
7776         }
7777
7778         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7779                 if (INTEL_INFO(dev)->gen < 4 ||
7780                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7781                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7782                 else
7783                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7784         } else
7785                 pipeconf |= PIPECONF_PROGRESSIVE;
7786
7787         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7788                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7789
7790         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7791         POSTING_READ(PIPECONF(intel_crtc->pipe));
7792 }
7793
7794 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7795                                    struct intel_crtc_state *crtc_state)
7796 {
7797         struct drm_device *dev = crtc->base.dev;
7798         struct drm_i915_private *dev_priv = dev->dev_private;
7799         int refclk, num_connectors = 0;
7800         intel_clock_t clock;
7801         bool ok;
7802         bool is_dsi = false;
7803         struct intel_encoder *encoder;
7804         const intel_limit_t *limit;
7805         struct drm_atomic_state *state = crtc_state->base.state;
7806         struct drm_connector *connector;
7807         struct drm_connector_state *connector_state;
7808         int i;
7809
7810         memset(&crtc_state->dpll_hw_state, 0,
7811                sizeof(crtc_state->dpll_hw_state));
7812
7813         for_each_connector_in_state(state, connector, connector_state, i) {
7814                 if (connector_state->crtc != &crtc->base)
7815                         continue;
7816
7817                 encoder = to_intel_encoder(connector_state->best_encoder);
7818
7819                 switch (encoder->type) {
7820                 case INTEL_OUTPUT_DSI:
7821                         is_dsi = true;
7822                         break;
7823                 default:
7824                         break;
7825                 }
7826
7827                 num_connectors++;
7828         }
7829
7830         if (is_dsi)
7831                 return 0;
7832
7833         if (!crtc_state->clock_set) {
7834                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7835
7836                 /*
7837                  * Returns a set of divisors for the desired target clock with
7838                  * the given refclk, or FALSE.  The returned values represent
7839                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7840                  * 2) / p1 / p2.
7841                  */
7842                 limit = intel_limit(crtc_state, refclk);
7843                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7844                                                  crtc_state->port_clock,
7845                                                  refclk, NULL, &clock);
7846                 if (!ok) {
7847                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7848                         return -EINVAL;
7849                 }
7850
7851                 /* Compat-code for transition, will disappear. */
7852                 crtc_state->dpll.n = clock.n;
7853                 crtc_state->dpll.m1 = clock.m1;
7854                 crtc_state->dpll.m2 = clock.m2;
7855                 crtc_state->dpll.p1 = clock.p1;
7856                 crtc_state->dpll.p2 = clock.p2;
7857         }
7858
7859         if (IS_GEN2(dev)) {
7860                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7861                                   num_connectors);
7862         } else if (IS_CHERRYVIEW(dev)) {
7863                 chv_compute_dpll(crtc, crtc_state);
7864         } else if (IS_VALLEYVIEW(dev)) {
7865                 vlv_compute_dpll(crtc, crtc_state);
7866         } else {
7867                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7868                                   num_connectors);
7869         }
7870
7871         return 0;
7872 }
7873
7874 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7875                                  struct intel_crtc_state *pipe_config)
7876 {
7877         struct drm_device *dev = crtc->base.dev;
7878         struct drm_i915_private *dev_priv = dev->dev_private;
7879         uint32_t tmp;
7880
7881         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7882                 return;
7883
7884         tmp = I915_READ(PFIT_CONTROL);
7885         if (!(tmp & PFIT_ENABLE))
7886                 return;
7887
7888         /* Check whether the pfit is attached to our pipe. */
7889         if (INTEL_INFO(dev)->gen < 4) {
7890                 if (crtc->pipe != PIPE_B)
7891                         return;
7892         } else {
7893                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7894                         return;
7895         }
7896
7897         pipe_config->gmch_pfit.control = tmp;
7898         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7899         if (INTEL_INFO(dev)->gen < 5)
7900                 pipe_config->gmch_pfit.lvds_border_bits =
7901                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7902 }
7903
7904 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7905                                struct intel_crtc_state *pipe_config)
7906 {
7907         struct drm_device *dev = crtc->base.dev;
7908         struct drm_i915_private *dev_priv = dev->dev_private;
7909         int pipe = pipe_config->cpu_transcoder;
7910         intel_clock_t clock;
7911         u32 mdiv;
7912         int refclk = 100000;
7913
7914         /* In case of MIPI DPLL will not even be used */
7915         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7916                 return;
7917
7918         mutex_lock(&dev_priv->sb_lock);
7919         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7920         mutex_unlock(&dev_priv->sb_lock);
7921
7922         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7923         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7924         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7925         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7926         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7927
7928         vlv_clock(refclk, &clock);
7929
7930         /* clock.dot is the fast clock */
7931         pipe_config->port_clock = clock.dot / 5;
7932 }
7933
7934 static void
7935 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7936                               struct intel_initial_plane_config *plane_config)
7937 {
7938         struct drm_device *dev = crtc->base.dev;
7939         struct drm_i915_private *dev_priv = dev->dev_private;
7940         u32 val, base, offset;
7941         int pipe = crtc->pipe, plane = crtc->plane;
7942         int fourcc, pixel_format;
7943         unsigned int aligned_height;
7944         struct drm_framebuffer *fb;
7945         struct intel_framebuffer *intel_fb;
7946
7947         val = I915_READ(DSPCNTR(plane));
7948         if (!(val & DISPLAY_PLANE_ENABLE))
7949                 return;
7950
7951         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7952         if (!intel_fb) {
7953                 DRM_DEBUG_KMS("failed to alloc fb\n");
7954                 return;
7955         }
7956
7957         fb = &intel_fb->base;
7958
7959         if (INTEL_INFO(dev)->gen >= 4) {
7960                 if (val & DISPPLANE_TILED) {
7961                         plane_config->tiling = I915_TILING_X;
7962                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7963                 }
7964         }
7965
7966         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7967         fourcc = i9xx_format_to_fourcc(pixel_format);
7968         fb->pixel_format = fourcc;
7969         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7970
7971         if (INTEL_INFO(dev)->gen >= 4) {
7972                 if (plane_config->tiling)
7973                         offset = I915_READ(DSPTILEOFF(plane));
7974                 else
7975                         offset = I915_READ(DSPLINOFF(plane));
7976                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7977         } else {
7978                 base = I915_READ(DSPADDR(plane));
7979         }
7980         plane_config->base = base;
7981
7982         val = I915_READ(PIPESRC(pipe));
7983         fb->width = ((val >> 16) & 0xfff) + 1;
7984         fb->height = ((val >> 0) & 0xfff) + 1;
7985
7986         val = I915_READ(DSPSTRIDE(pipe));
7987         fb->pitches[0] = val & 0xffffffc0;
7988
7989         aligned_height = intel_fb_align_height(dev, fb->height,
7990                                                fb->pixel_format,
7991                                                fb->modifier[0]);
7992
7993         plane_config->size = fb->pitches[0] * aligned_height;
7994
7995         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7996                       pipe_name(pipe), plane, fb->width, fb->height,
7997                       fb->bits_per_pixel, base, fb->pitches[0],
7998                       plane_config->size);
7999
8000         plane_config->fb = intel_fb;
8001 }
8002
8003 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8004                                struct intel_crtc_state *pipe_config)
8005 {
8006         struct drm_device *dev = crtc->base.dev;
8007         struct drm_i915_private *dev_priv = dev->dev_private;
8008         int pipe = pipe_config->cpu_transcoder;
8009         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8010         intel_clock_t clock;
8011         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8012         int refclk = 100000;
8013
8014         mutex_lock(&dev_priv->sb_lock);
8015         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8016         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8017         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8018         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8019         mutex_unlock(&dev_priv->sb_lock);
8020
8021         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8022         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8023         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8024         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8025         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8026
8027         chv_clock(refclk, &clock);
8028
8029         /* clock.dot is the fast clock */
8030         pipe_config->port_clock = clock.dot / 5;
8031 }
8032
8033 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8034                                  struct intel_crtc_state *pipe_config)
8035 {
8036         struct drm_device *dev = crtc->base.dev;
8037         struct drm_i915_private *dev_priv = dev->dev_private;
8038         uint32_t tmp;
8039
8040         if (!intel_display_power_is_enabled(dev_priv,
8041                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8042                 return false;
8043
8044         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8045         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8046
8047         tmp = I915_READ(PIPECONF(crtc->pipe));
8048         if (!(tmp & PIPECONF_ENABLE))
8049                 return false;
8050
8051         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8052                 switch (tmp & PIPECONF_BPC_MASK) {
8053                 case PIPECONF_6BPC:
8054                         pipe_config->pipe_bpp = 18;
8055                         break;
8056                 case PIPECONF_8BPC:
8057                         pipe_config->pipe_bpp = 24;
8058                         break;
8059                 case PIPECONF_10BPC:
8060                         pipe_config->pipe_bpp = 30;
8061                         break;
8062                 default:
8063                         break;
8064                 }
8065         }
8066
8067         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8068                 pipe_config->limited_color_range = true;
8069
8070         if (INTEL_INFO(dev)->gen < 4)
8071                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8072
8073         intel_get_pipe_timings(crtc, pipe_config);
8074
8075         i9xx_get_pfit_config(crtc, pipe_config);
8076
8077         if (INTEL_INFO(dev)->gen >= 4) {
8078                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8079                 pipe_config->pixel_multiplier =
8080                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8081                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8082                 pipe_config->dpll_hw_state.dpll_md = tmp;
8083         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8084                 tmp = I915_READ(DPLL(crtc->pipe));
8085                 pipe_config->pixel_multiplier =
8086                         ((tmp & SDVO_MULTIPLIER_MASK)
8087                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8088         } else {
8089                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8090                  * port and will be fixed up in the encoder->get_config
8091                  * function. */
8092                 pipe_config->pixel_multiplier = 1;
8093         }
8094         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8095         if (!IS_VALLEYVIEW(dev)) {
8096                 /*
8097                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8098                  * on 830. Filter it out here so that we don't
8099                  * report errors due to that.
8100                  */
8101                 if (IS_I830(dev))
8102                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8103
8104                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8105                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8106         } else {
8107                 /* Mask out read-only status bits. */
8108                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8109                                                      DPLL_PORTC_READY_MASK |
8110                                                      DPLL_PORTB_READY_MASK);
8111         }
8112
8113         if (IS_CHERRYVIEW(dev))
8114                 chv_crtc_clock_get(crtc, pipe_config);
8115         else if (IS_VALLEYVIEW(dev))
8116                 vlv_crtc_clock_get(crtc, pipe_config);
8117         else
8118                 i9xx_crtc_clock_get(crtc, pipe_config);
8119
8120         return true;
8121 }
8122
8123 static void ironlake_init_pch_refclk(struct drm_device *dev)
8124 {
8125         struct drm_i915_private *dev_priv = dev->dev_private;
8126         struct intel_encoder *encoder;
8127         u32 val, final;
8128         bool has_lvds = false;
8129         bool has_cpu_edp = false;
8130         bool has_panel = false;
8131         bool has_ck505 = false;
8132         bool can_ssc = false;
8133
8134         /* We need to take the global config into account */
8135         for_each_intel_encoder(dev, encoder) {
8136                 switch (encoder->type) {
8137                 case INTEL_OUTPUT_LVDS:
8138                         has_panel = true;
8139                         has_lvds = true;
8140                         break;
8141                 case INTEL_OUTPUT_EDP:
8142                         has_panel = true;
8143                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8144                                 has_cpu_edp = true;
8145                         break;
8146                 default:
8147                         break;
8148                 }
8149         }
8150
8151         if (HAS_PCH_IBX(dev)) {
8152                 has_ck505 = dev_priv->vbt.display_clock_mode;
8153                 can_ssc = has_ck505;
8154         } else {
8155                 has_ck505 = false;
8156                 can_ssc = true;
8157         }
8158
8159         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8160                       has_panel, has_lvds, has_ck505);
8161
8162         /* Ironlake: try to setup display ref clock before DPLL
8163          * enabling. This is only under driver's control after
8164          * PCH B stepping, previous chipset stepping should be
8165          * ignoring this setting.
8166          */
8167         val = I915_READ(PCH_DREF_CONTROL);
8168
8169         /* As we must carefully and slowly disable/enable each source in turn,
8170          * compute the final state we want first and check if we need to
8171          * make any changes at all.
8172          */
8173         final = val;
8174         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8175         if (has_ck505)
8176                 final |= DREF_NONSPREAD_CK505_ENABLE;
8177         else
8178                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8179
8180         final &= ~DREF_SSC_SOURCE_MASK;
8181         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8182         final &= ~DREF_SSC1_ENABLE;
8183
8184         if (has_panel) {
8185                 final |= DREF_SSC_SOURCE_ENABLE;
8186
8187                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8188                         final |= DREF_SSC1_ENABLE;
8189
8190                 if (has_cpu_edp) {
8191                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8192                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8193                         else
8194                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8195                 } else
8196                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8197         } else {
8198                 final |= DREF_SSC_SOURCE_DISABLE;
8199                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8200         }
8201
8202         if (final == val)
8203                 return;
8204
8205         /* Always enable nonspread source */
8206         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8207
8208         if (has_ck505)
8209                 val |= DREF_NONSPREAD_CK505_ENABLE;
8210         else
8211                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8212
8213         if (has_panel) {
8214                 val &= ~DREF_SSC_SOURCE_MASK;
8215                 val |= DREF_SSC_SOURCE_ENABLE;
8216
8217                 /* SSC must be turned on before enabling the CPU output  */
8218                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8219                         DRM_DEBUG_KMS("Using SSC on panel\n");
8220                         val |= DREF_SSC1_ENABLE;
8221                 } else
8222                         val &= ~DREF_SSC1_ENABLE;
8223
8224                 /* Get SSC going before enabling the outputs */
8225                 I915_WRITE(PCH_DREF_CONTROL, val);
8226                 POSTING_READ(PCH_DREF_CONTROL);
8227                 udelay(200);
8228
8229                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230
8231                 /* Enable CPU source on CPU attached eDP */
8232                 if (has_cpu_edp) {
8233                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8234                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8235                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8236                         } else
8237                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8238                 } else
8239                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8240
8241                 I915_WRITE(PCH_DREF_CONTROL, val);
8242                 POSTING_READ(PCH_DREF_CONTROL);
8243                 udelay(200);
8244         } else {
8245                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8246
8247                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8248
8249                 /* Turn off CPU output */
8250                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8251
8252                 I915_WRITE(PCH_DREF_CONTROL, val);
8253                 POSTING_READ(PCH_DREF_CONTROL);
8254                 udelay(200);
8255
8256                 /* Turn off the SSC source */
8257                 val &= ~DREF_SSC_SOURCE_MASK;
8258                 val |= DREF_SSC_SOURCE_DISABLE;
8259
8260                 /* Turn off SSC1 */
8261                 val &= ~DREF_SSC1_ENABLE;
8262
8263                 I915_WRITE(PCH_DREF_CONTROL, val);
8264                 POSTING_READ(PCH_DREF_CONTROL);
8265                 udelay(200);
8266         }
8267
8268         BUG_ON(val != final);
8269 }
8270
8271 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8272 {
8273         uint32_t tmp;
8274
8275         tmp = I915_READ(SOUTH_CHICKEN2);
8276         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8277         I915_WRITE(SOUTH_CHICKEN2, tmp);
8278
8279         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8280                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8281                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8282
8283         tmp = I915_READ(SOUTH_CHICKEN2);
8284         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8285         I915_WRITE(SOUTH_CHICKEN2, tmp);
8286
8287         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8288                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8289                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8290 }
8291
8292 /* WaMPhyProgramming:hsw */
8293 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8294 {
8295         uint32_t tmp;
8296
8297         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8298         tmp &= ~(0xFF << 24);
8299         tmp |= (0x12 << 24);
8300         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8301
8302         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8303         tmp |= (1 << 11);
8304         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8305
8306         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8307         tmp |= (1 << 11);
8308         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8309
8310         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8311         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8312         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8313
8314         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8315         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8316         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8317
8318         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8319         tmp &= ~(7 << 13);
8320         tmp |= (5 << 13);
8321         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8322
8323         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8324         tmp &= ~(7 << 13);
8325         tmp |= (5 << 13);
8326         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8327
8328         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8329         tmp &= ~0xFF;
8330         tmp |= 0x1C;
8331         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8332
8333         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8334         tmp &= ~0xFF;
8335         tmp |= 0x1C;
8336         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8337
8338         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8339         tmp &= ~(0xFF << 16);
8340         tmp |= (0x1C << 16);
8341         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8342
8343         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8344         tmp &= ~(0xFF << 16);
8345         tmp |= (0x1C << 16);
8346         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8347
8348         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8349         tmp |= (1 << 27);
8350         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8351
8352         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8353         tmp |= (1 << 27);
8354         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8355
8356         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8357         tmp &= ~(0xF << 28);
8358         tmp |= (4 << 28);
8359         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8360
8361         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8362         tmp &= ~(0xF << 28);
8363         tmp |= (4 << 28);
8364         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8365 }
8366
8367 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8368  * Programming" based on the parameters passed:
8369  * - Sequence to enable CLKOUT_DP
8370  * - Sequence to enable CLKOUT_DP without spread
8371  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8372  */
8373 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8374                                  bool with_fdi)
8375 {
8376         struct drm_i915_private *dev_priv = dev->dev_private;
8377         uint32_t reg, tmp;
8378
8379         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8380                 with_spread = true;
8381         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8382                  with_fdi, "LP PCH doesn't have FDI\n"))
8383                 with_fdi = false;
8384
8385         mutex_lock(&dev_priv->sb_lock);
8386
8387         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8388         tmp &= ~SBI_SSCCTL_DISABLE;
8389         tmp |= SBI_SSCCTL_PATHALT;
8390         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8391
8392         udelay(24);
8393
8394         if (with_spread) {
8395                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8396                 tmp &= ~SBI_SSCCTL_PATHALT;
8397                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8398
8399                 if (with_fdi) {
8400                         lpt_reset_fdi_mphy(dev_priv);
8401                         lpt_program_fdi_mphy(dev_priv);
8402                 }
8403         }
8404
8405         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8406                SBI_GEN0 : SBI_DBUFF0;
8407         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8408         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8409         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8410
8411         mutex_unlock(&dev_priv->sb_lock);
8412 }
8413
8414 /* Sequence to disable CLKOUT_DP */
8415 static void lpt_disable_clkout_dp(struct drm_device *dev)
8416 {
8417         struct drm_i915_private *dev_priv = dev->dev_private;
8418         uint32_t reg, tmp;
8419
8420         mutex_lock(&dev_priv->sb_lock);
8421
8422         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8423                SBI_GEN0 : SBI_DBUFF0;
8424         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8425         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8426         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8427
8428         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8429         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8430                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8431                         tmp |= SBI_SSCCTL_PATHALT;
8432                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8433                         udelay(32);
8434                 }
8435                 tmp |= SBI_SSCCTL_DISABLE;
8436                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8437         }
8438
8439         mutex_unlock(&dev_priv->sb_lock);
8440 }
8441
8442 static void lpt_init_pch_refclk(struct drm_device *dev)
8443 {
8444         struct intel_encoder *encoder;
8445         bool has_vga = false;
8446
8447         for_each_intel_encoder(dev, encoder) {
8448                 switch (encoder->type) {
8449                 case INTEL_OUTPUT_ANALOG:
8450                         has_vga = true;
8451                         break;
8452                 default:
8453                         break;
8454                 }
8455         }
8456
8457         if (has_vga)
8458                 lpt_enable_clkout_dp(dev, true, true);
8459         else
8460                 lpt_disable_clkout_dp(dev);
8461 }
8462
8463 /*
8464  * Initialize reference clocks when the driver loads
8465  */
8466 void intel_init_pch_refclk(struct drm_device *dev)
8467 {
8468         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8469                 ironlake_init_pch_refclk(dev);
8470         else if (HAS_PCH_LPT(dev))
8471                 lpt_init_pch_refclk(dev);
8472 }
8473
8474 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8475 {
8476         struct drm_device *dev = crtc_state->base.crtc->dev;
8477         struct drm_i915_private *dev_priv = dev->dev_private;
8478         struct drm_atomic_state *state = crtc_state->base.state;
8479         struct drm_connector *connector;
8480         struct drm_connector_state *connector_state;
8481         struct intel_encoder *encoder;
8482         int num_connectors = 0, i;
8483         bool is_lvds = false;
8484
8485         for_each_connector_in_state(state, connector, connector_state, i) {
8486                 if (connector_state->crtc != crtc_state->base.crtc)
8487                         continue;
8488
8489                 encoder = to_intel_encoder(connector_state->best_encoder);
8490
8491                 switch (encoder->type) {
8492                 case INTEL_OUTPUT_LVDS:
8493                         is_lvds = true;
8494                         break;
8495                 default:
8496                         break;
8497                 }
8498                 num_connectors++;
8499         }
8500
8501         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8502                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8503                               dev_priv->vbt.lvds_ssc_freq);
8504                 return dev_priv->vbt.lvds_ssc_freq;
8505         }
8506
8507         return 120000;
8508 }
8509
8510 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8511 {
8512         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8514         int pipe = intel_crtc->pipe;
8515         uint32_t val;
8516
8517         val = 0;
8518
8519         switch (intel_crtc->config->pipe_bpp) {
8520         case 18:
8521                 val |= PIPECONF_6BPC;
8522                 break;
8523         case 24:
8524                 val |= PIPECONF_8BPC;
8525                 break;
8526         case 30:
8527                 val |= PIPECONF_10BPC;
8528                 break;
8529         case 36:
8530                 val |= PIPECONF_12BPC;
8531                 break;
8532         default:
8533                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8534                 BUG();
8535         }
8536
8537         if (intel_crtc->config->dither)
8538                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8539
8540         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8541                 val |= PIPECONF_INTERLACED_ILK;
8542         else
8543                 val |= PIPECONF_PROGRESSIVE;
8544
8545         if (intel_crtc->config->limited_color_range)
8546                 val |= PIPECONF_COLOR_RANGE_SELECT;
8547
8548         I915_WRITE(PIPECONF(pipe), val);
8549         POSTING_READ(PIPECONF(pipe));
8550 }
8551
8552 /*
8553  * Set up the pipe CSC unit.
8554  *
8555  * Currently only full range RGB to limited range RGB conversion
8556  * is supported, but eventually this should handle various
8557  * RGB<->YCbCr scenarios as well.
8558  */
8559 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8560 {
8561         struct drm_device *dev = crtc->dev;
8562         struct drm_i915_private *dev_priv = dev->dev_private;
8563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8564         int pipe = intel_crtc->pipe;
8565         uint16_t coeff = 0x7800; /* 1.0 */
8566
8567         /*
8568          * TODO: Check what kind of values actually come out of the pipe
8569          * with these coeff/postoff values and adjust to get the best
8570          * accuracy. Perhaps we even need to take the bpc value into
8571          * consideration.
8572          */
8573
8574         if (intel_crtc->config->limited_color_range)
8575                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8576
8577         /*
8578          * GY/GU and RY/RU should be the other way around according
8579          * to BSpec, but reality doesn't agree. Just set them up in
8580          * a way that results in the correct picture.
8581          */
8582         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8583         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8584
8585         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8586         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8587
8588         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8589         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8590
8591         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8592         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8593         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8594
8595         if (INTEL_INFO(dev)->gen > 6) {
8596                 uint16_t postoff = 0;
8597
8598                 if (intel_crtc->config->limited_color_range)
8599                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8600
8601                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8602                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8603                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8604
8605                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8606         } else {
8607                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8608
8609                 if (intel_crtc->config->limited_color_range)
8610                         mode |= CSC_BLACK_SCREEN_OFFSET;
8611
8612                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8613         }
8614 }
8615
8616 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8617 {
8618         struct drm_device *dev = crtc->dev;
8619         struct drm_i915_private *dev_priv = dev->dev_private;
8620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8621         enum pipe pipe = intel_crtc->pipe;
8622         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8623         uint32_t val;
8624
8625         val = 0;
8626
8627         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8628                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8629
8630         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8631                 val |= PIPECONF_INTERLACED_ILK;
8632         else
8633                 val |= PIPECONF_PROGRESSIVE;
8634
8635         I915_WRITE(PIPECONF(cpu_transcoder), val);
8636         POSTING_READ(PIPECONF(cpu_transcoder));
8637
8638         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8639         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8640
8641         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8642                 val = 0;
8643
8644                 switch (intel_crtc->config->pipe_bpp) {
8645                 case 18:
8646                         val |= PIPEMISC_DITHER_6_BPC;
8647                         break;
8648                 case 24:
8649                         val |= PIPEMISC_DITHER_8_BPC;
8650                         break;
8651                 case 30:
8652                         val |= PIPEMISC_DITHER_10_BPC;
8653                         break;
8654                 case 36:
8655                         val |= PIPEMISC_DITHER_12_BPC;
8656                         break;
8657                 default:
8658                         /* Case prevented by pipe_config_set_bpp. */
8659                         BUG();
8660                 }
8661
8662                 if (intel_crtc->config->dither)
8663                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8664
8665                 I915_WRITE(PIPEMISC(pipe), val);
8666         }
8667 }
8668
8669 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8670                                     struct intel_crtc_state *crtc_state,
8671                                     intel_clock_t *clock,
8672                                     bool *has_reduced_clock,
8673                                     intel_clock_t *reduced_clock)
8674 {
8675         struct drm_device *dev = crtc->dev;
8676         struct drm_i915_private *dev_priv = dev->dev_private;
8677         int refclk;
8678         const intel_limit_t *limit;
8679         bool ret;
8680
8681         refclk = ironlake_get_refclk(crtc_state);
8682
8683         /*
8684          * Returns a set of divisors for the desired target clock with the given
8685          * refclk, or FALSE.  The returned values represent the clock equation:
8686          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8687          */
8688         limit = intel_limit(crtc_state, refclk);
8689         ret = dev_priv->display.find_dpll(limit, crtc_state,
8690                                           crtc_state->port_clock,
8691                                           refclk, NULL, clock);
8692         if (!ret)
8693                 return false;
8694
8695         return true;
8696 }
8697
8698 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8699 {
8700         /*
8701          * Account for spread spectrum to avoid
8702          * oversubscribing the link. Max center spread
8703          * is 2.5%; use 5% for safety's sake.
8704          */
8705         u32 bps = target_clock * bpp * 21 / 20;
8706         return DIV_ROUND_UP(bps, link_bw * 8);
8707 }
8708
8709 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8710 {
8711         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8712 }
8713
8714 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8715                                       struct intel_crtc_state *crtc_state,
8716                                       u32 *fp,
8717                                       intel_clock_t *reduced_clock, u32 *fp2)
8718 {
8719         struct drm_crtc *crtc = &intel_crtc->base;
8720         struct drm_device *dev = crtc->dev;
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         struct drm_atomic_state *state = crtc_state->base.state;
8723         struct drm_connector *connector;
8724         struct drm_connector_state *connector_state;
8725         struct intel_encoder *encoder;
8726         uint32_t dpll;
8727         int factor, num_connectors = 0, i;
8728         bool is_lvds = false, is_sdvo = false;
8729
8730         for_each_connector_in_state(state, connector, connector_state, i) {
8731                 if (connector_state->crtc != crtc_state->base.crtc)
8732                         continue;
8733
8734                 encoder = to_intel_encoder(connector_state->best_encoder);
8735
8736                 switch (encoder->type) {
8737                 case INTEL_OUTPUT_LVDS:
8738                         is_lvds = true;
8739                         break;
8740                 case INTEL_OUTPUT_SDVO:
8741                 case INTEL_OUTPUT_HDMI:
8742                         is_sdvo = true;
8743                         break;
8744                 default:
8745                         break;
8746                 }
8747
8748                 num_connectors++;
8749         }
8750
8751         /* Enable autotuning of the PLL clock (if permissible) */
8752         factor = 21;
8753         if (is_lvds) {
8754                 if ((intel_panel_use_ssc(dev_priv) &&
8755                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8756                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8757                         factor = 25;
8758         } else if (crtc_state->sdvo_tv_clock)
8759                 factor = 20;
8760
8761         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8762                 *fp |= FP_CB_TUNE;
8763
8764         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8765                 *fp2 |= FP_CB_TUNE;
8766
8767         dpll = 0;
8768
8769         if (is_lvds)
8770                 dpll |= DPLLB_MODE_LVDS;
8771         else
8772                 dpll |= DPLLB_MODE_DAC_SERIAL;
8773
8774         dpll |= (crtc_state->pixel_multiplier - 1)
8775                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8776
8777         if (is_sdvo)
8778                 dpll |= DPLL_SDVO_HIGH_SPEED;
8779         if (crtc_state->has_dp_encoder)
8780                 dpll |= DPLL_SDVO_HIGH_SPEED;
8781
8782         /* compute bitmask from p1 value */
8783         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8784         /* also FPA1 */
8785         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8786
8787         switch (crtc_state->dpll.p2) {
8788         case 5:
8789                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8790                 break;
8791         case 7:
8792                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8793                 break;
8794         case 10:
8795                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8796                 break;
8797         case 14:
8798                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8799                 break;
8800         }
8801
8802         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8803                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8804         else
8805                 dpll |= PLL_REF_INPUT_DREFCLK;
8806
8807         return dpll | DPLL_VCO_ENABLE;
8808 }
8809
8810 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8811                                        struct intel_crtc_state *crtc_state)
8812 {
8813         struct drm_device *dev = crtc->base.dev;
8814         intel_clock_t clock, reduced_clock;
8815         u32 dpll = 0, fp = 0, fp2 = 0;
8816         bool ok, has_reduced_clock = false;
8817         bool is_lvds = false;
8818         struct intel_shared_dpll *pll;
8819
8820         memset(&crtc_state->dpll_hw_state, 0,
8821                sizeof(crtc_state->dpll_hw_state));
8822
8823         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8824
8825         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8826              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8827
8828         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8829                                      &has_reduced_clock, &reduced_clock);
8830         if (!ok && !crtc_state->clock_set) {
8831                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8832                 return -EINVAL;
8833         }
8834         /* Compat-code for transition, will disappear. */
8835         if (!crtc_state->clock_set) {
8836                 crtc_state->dpll.n = clock.n;
8837                 crtc_state->dpll.m1 = clock.m1;
8838                 crtc_state->dpll.m2 = clock.m2;
8839                 crtc_state->dpll.p1 = clock.p1;
8840                 crtc_state->dpll.p2 = clock.p2;
8841         }
8842
8843         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8844         if (crtc_state->has_pch_encoder) {
8845                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8846                 if (has_reduced_clock)
8847                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8848
8849                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8850                                              &fp, &reduced_clock,
8851                                              has_reduced_clock ? &fp2 : NULL);
8852
8853                 crtc_state->dpll_hw_state.dpll = dpll;
8854                 crtc_state->dpll_hw_state.fp0 = fp;
8855                 if (has_reduced_clock)
8856                         crtc_state->dpll_hw_state.fp1 = fp2;
8857                 else
8858                         crtc_state->dpll_hw_state.fp1 = fp;
8859
8860                 pll = intel_get_shared_dpll(crtc, crtc_state);
8861                 if (pll == NULL) {
8862                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8863                                          pipe_name(crtc->pipe));
8864                         return -EINVAL;
8865                 }
8866         }
8867
8868         if (is_lvds && has_reduced_clock)
8869                 crtc->lowfreq_avail = true;
8870         else
8871                 crtc->lowfreq_avail = false;
8872
8873         return 0;
8874 }
8875
8876 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8877                                          struct intel_link_m_n *m_n)
8878 {
8879         struct drm_device *dev = crtc->base.dev;
8880         struct drm_i915_private *dev_priv = dev->dev_private;
8881         enum pipe pipe = crtc->pipe;
8882
8883         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8884         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8885         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8886                 & ~TU_SIZE_MASK;
8887         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8888         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8889                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8890 }
8891
8892 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8893                                          enum transcoder transcoder,
8894                                          struct intel_link_m_n *m_n,
8895                                          struct intel_link_m_n *m2_n2)
8896 {
8897         struct drm_device *dev = crtc->base.dev;
8898         struct drm_i915_private *dev_priv = dev->dev_private;
8899         enum pipe pipe = crtc->pipe;
8900
8901         if (INTEL_INFO(dev)->gen >= 5) {
8902                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8903                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8904                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8905                         & ~TU_SIZE_MASK;
8906                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8907                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8908                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8909                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8910                  * gen < 8) and if DRRS is supported (to make sure the
8911                  * registers are not unnecessarily read).
8912                  */
8913                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8914                         crtc->config->has_drrs) {
8915                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8916                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8917                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8918                                         & ~TU_SIZE_MASK;
8919                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8920                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8921                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8922                 }
8923         } else {
8924                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8925                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8926                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8927                         & ~TU_SIZE_MASK;
8928                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8929                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8930                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8931         }
8932 }
8933
8934 void intel_dp_get_m_n(struct intel_crtc *crtc,
8935                       struct intel_crtc_state *pipe_config)
8936 {
8937         if (pipe_config->has_pch_encoder)
8938                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8939         else
8940                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8941                                              &pipe_config->dp_m_n,
8942                                              &pipe_config->dp_m2_n2);
8943 }
8944
8945 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8946                                         struct intel_crtc_state *pipe_config)
8947 {
8948         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8949                                      &pipe_config->fdi_m_n, NULL);
8950 }
8951
8952 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8953                                     struct intel_crtc_state *pipe_config)
8954 {
8955         struct drm_device *dev = crtc->base.dev;
8956         struct drm_i915_private *dev_priv = dev->dev_private;
8957         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8958         uint32_t ps_ctrl = 0;
8959         int id = -1;
8960         int i;
8961
8962         /* find scaler attached to this pipe */
8963         for (i = 0; i < crtc->num_scalers; i++) {
8964                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8965                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8966                         id = i;
8967                         pipe_config->pch_pfit.enabled = true;
8968                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8969                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8970                         break;
8971                 }
8972         }
8973
8974         scaler_state->scaler_id = id;
8975         if (id >= 0) {
8976                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8977         } else {
8978                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8979         }
8980 }
8981
8982 static void
8983 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8984                                  struct intel_initial_plane_config *plane_config)
8985 {
8986         struct drm_device *dev = crtc->base.dev;
8987         struct drm_i915_private *dev_priv = dev->dev_private;
8988         u32 val, base, offset, stride_mult, tiling;
8989         int pipe = crtc->pipe;
8990         int fourcc, pixel_format;
8991         unsigned int aligned_height;
8992         struct drm_framebuffer *fb;
8993         struct intel_framebuffer *intel_fb;
8994
8995         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8996         if (!intel_fb) {
8997                 DRM_DEBUG_KMS("failed to alloc fb\n");
8998                 return;
8999         }
9000
9001         fb = &intel_fb->base;
9002
9003         val = I915_READ(PLANE_CTL(pipe, 0));
9004         if (!(val & PLANE_CTL_ENABLE))
9005                 goto error;
9006
9007         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9008         fourcc = skl_format_to_fourcc(pixel_format,
9009                                       val & PLANE_CTL_ORDER_RGBX,
9010                                       val & PLANE_CTL_ALPHA_MASK);
9011         fb->pixel_format = fourcc;
9012         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9013
9014         tiling = val & PLANE_CTL_TILED_MASK;
9015         switch (tiling) {
9016         case PLANE_CTL_TILED_LINEAR:
9017                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9018                 break;
9019         case PLANE_CTL_TILED_X:
9020                 plane_config->tiling = I915_TILING_X;
9021                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9022                 break;
9023         case PLANE_CTL_TILED_Y:
9024                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9025                 break;
9026         case PLANE_CTL_TILED_YF:
9027                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9028                 break;
9029         default:
9030                 MISSING_CASE(tiling);
9031                 goto error;
9032         }
9033
9034         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9035         plane_config->base = base;
9036
9037         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9038
9039         val = I915_READ(PLANE_SIZE(pipe, 0));
9040         fb->height = ((val >> 16) & 0xfff) + 1;
9041         fb->width = ((val >> 0) & 0x1fff) + 1;
9042
9043         val = I915_READ(PLANE_STRIDE(pipe, 0));
9044         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9045                                                 fb->pixel_format);
9046         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9047
9048         aligned_height = intel_fb_align_height(dev, fb->height,
9049                                                fb->pixel_format,
9050                                                fb->modifier[0]);
9051
9052         plane_config->size = fb->pitches[0] * aligned_height;
9053
9054         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9055                       pipe_name(pipe), fb->width, fb->height,
9056                       fb->bits_per_pixel, base, fb->pitches[0],
9057                       plane_config->size);
9058
9059         plane_config->fb = intel_fb;
9060         return;
9061
9062 error:
9063         kfree(fb);
9064 }
9065
9066 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9067                                      struct intel_crtc_state *pipe_config)
9068 {
9069         struct drm_device *dev = crtc->base.dev;
9070         struct drm_i915_private *dev_priv = dev->dev_private;
9071         uint32_t tmp;
9072
9073         tmp = I915_READ(PF_CTL(crtc->pipe));
9074
9075         if (tmp & PF_ENABLE) {
9076                 pipe_config->pch_pfit.enabled = true;
9077                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9078                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9079
9080                 /* We currently do not free assignements of panel fitters on
9081                  * ivb/hsw (since we don't use the higher upscaling modes which
9082                  * differentiates them) so just WARN about this case for now. */
9083                 if (IS_GEN7(dev)) {
9084                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9085                                 PF_PIPE_SEL_IVB(crtc->pipe));
9086                 }
9087         }
9088 }
9089
9090 static void
9091 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9092                                   struct intel_initial_plane_config *plane_config)
9093 {
9094         struct drm_device *dev = crtc->base.dev;
9095         struct drm_i915_private *dev_priv = dev->dev_private;
9096         u32 val, base, offset;
9097         int pipe = crtc->pipe;
9098         int fourcc, pixel_format;
9099         unsigned int aligned_height;
9100         struct drm_framebuffer *fb;
9101         struct intel_framebuffer *intel_fb;
9102
9103         val = I915_READ(DSPCNTR(pipe));
9104         if (!(val & DISPLAY_PLANE_ENABLE))
9105                 return;
9106
9107         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9108         if (!intel_fb) {
9109                 DRM_DEBUG_KMS("failed to alloc fb\n");
9110                 return;
9111         }
9112
9113         fb = &intel_fb->base;
9114
9115         if (INTEL_INFO(dev)->gen >= 4) {
9116                 if (val & DISPPLANE_TILED) {
9117                         plane_config->tiling = I915_TILING_X;
9118                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9119                 }
9120         }
9121
9122         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9123         fourcc = i9xx_format_to_fourcc(pixel_format);
9124         fb->pixel_format = fourcc;
9125         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9126
9127         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9128         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9129                 offset = I915_READ(DSPOFFSET(pipe));
9130         } else {
9131                 if (plane_config->tiling)
9132                         offset = I915_READ(DSPTILEOFF(pipe));
9133                 else
9134                         offset = I915_READ(DSPLINOFF(pipe));
9135         }
9136         plane_config->base = base;
9137
9138         val = I915_READ(PIPESRC(pipe));
9139         fb->width = ((val >> 16) & 0xfff) + 1;
9140         fb->height = ((val >> 0) & 0xfff) + 1;
9141
9142         val = I915_READ(DSPSTRIDE(pipe));
9143         fb->pitches[0] = val & 0xffffffc0;
9144
9145         aligned_height = intel_fb_align_height(dev, fb->height,
9146                                                fb->pixel_format,
9147                                                fb->modifier[0]);
9148
9149         plane_config->size = fb->pitches[0] * aligned_height;
9150
9151         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9152                       pipe_name(pipe), fb->width, fb->height,
9153                       fb->bits_per_pixel, base, fb->pitches[0],
9154                       plane_config->size);
9155
9156         plane_config->fb = intel_fb;
9157 }
9158
9159 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9160                                      struct intel_crtc_state *pipe_config)
9161 {
9162         struct drm_device *dev = crtc->base.dev;
9163         struct drm_i915_private *dev_priv = dev->dev_private;
9164         uint32_t tmp;
9165
9166         if (!intel_display_power_is_enabled(dev_priv,
9167                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9168                 return false;
9169
9170         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9171         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9172
9173         tmp = I915_READ(PIPECONF(crtc->pipe));
9174         if (!(tmp & PIPECONF_ENABLE))
9175                 return false;
9176
9177         switch (tmp & PIPECONF_BPC_MASK) {
9178         case PIPECONF_6BPC:
9179                 pipe_config->pipe_bpp = 18;
9180                 break;
9181         case PIPECONF_8BPC:
9182                 pipe_config->pipe_bpp = 24;
9183                 break;
9184         case PIPECONF_10BPC:
9185                 pipe_config->pipe_bpp = 30;
9186                 break;
9187         case PIPECONF_12BPC:
9188                 pipe_config->pipe_bpp = 36;
9189                 break;
9190         default:
9191                 break;
9192         }
9193
9194         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9195                 pipe_config->limited_color_range = true;
9196
9197         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9198                 struct intel_shared_dpll *pll;
9199
9200                 pipe_config->has_pch_encoder = true;
9201
9202                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9203                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9204                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9205
9206                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9207
9208                 if (HAS_PCH_IBX(dev_priv->dev)) {
9209                         pipe_config->shared_dpll =
9210                                 (enum intel_dpll_id) crtc->pipe;
9211                 } else {
9212                         tmp = I915_READ(PCH_DPLL_SEL);
9213                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9214                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9215                         else
9216                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9217                 }
9218
9219                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9220
9221                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9222                                            &pipe_config->dpll_hw_state));
9223
9224                 tmp = pipe_config->dpll_hw_state.dpll;
9225                 pipe_config->pixel_multiplier =
9226                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9227                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9228
9229                 ironlake_pch_clock_get(crtc, pipe_config);
9230         } else {
9231                 pipe_config->pixel_multiplier = 1;
9232         }
9233
9234         intel_get_pipe_timings(crtc, pipe_config);
9235
9236         ironlake_get_pfit_config(crtc, pipe_config);
9237
9238         return true;
9239 }
9240
9241 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9242 {
9243         struct drm_device *dev = dev_priv->dev;
9244         struct intel_crtc *crtc;
9245
9246         for_each_intel_crtc(dev, crtc)
9247                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9248                      pipe_name(crtc->pipe));
9249
9250         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9251         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9252         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9253         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9254         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9255         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9256              "CPU PWM1 enabled\n");
9257         if (IS_HASWELL(dev))
9258                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9259                      "CPU PWM2 enabled\n");
9260         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9261              "PCH PWM1 enabled\n");
9262         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9263              "Utility pin enabled\n");
9264         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9265
9266         /*
9267          * In theory we can still leave IRQs enabled, as long as only the HPD
9268          * interrupts remain enabled. We used to check for that, but since it's
9269          * gen-specific and since we only disable LCPLL after we fully disable
9270          * the interrupts, the check below should be enough.
9271          */
9272         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9273 }
9274
9275 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9276 {
9277         struct drm_device *dev = dev_priv->dev;
9278
9279         if (IS_HASWELL(dev))
9280                 return I915_READ(D_COMP_HSW);
9281         else
9282                 return I915_READ(D_COMP_BDW);
9283 }
9284
9285 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9286 {
9287         struct drm_device *dev = dev_priv->dev;
9288
9289         if (IS_HASWELL(dev)) {
9290                 mutex_lock(&dev_priv->rps.hw_lock);
9291                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9292                                             val))
9293                         DRM_ERROR("Failed to write to D_COMP\n");
9294                 mutex_unlock(&dev_priv->rps.hw_lock);
9295         } else {
9296                 I915_WRITE(D_COMP_BDW, val);
9297                 POSTING_READ(D_COMP_BDW);
9298         }
9299 }
9300
9301 /*
9302  * This function implements pieces of two sequences from BSpec:
9303  * - Sequence for display software to disable LCPLL
9304  * - Sequence for display software to allow package C8+
9305  * The steps implemented here are just the steps that actually touch the LCPLL
9306  * register. Callers should take care of disabling all the display engine
9307  * functions, doing the mode unset, fixing interrupts, etc.
9308  */
9309 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9310                               bool switch_to_fclk, bool allow_power_down)
9311 {
9312         uint32_t val;
9313
9314         assert_can_disable_lcpll(dev_priv);
9315
9316         val = I915_READ(LCPLL_CTL);
9317
9318         if (switch_to_fclk) {
9319                 val |= LCPLL_CD_SOURCE_FCLK;
9320                 I915_WRITE(LCPLL_CTL, val);
9321
9322                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9323                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9324                         DRM_ERROR("Switching to FCLK failed\n");
9325
9326                 val = I915_READ(LCPLL_CTL);
9327         }
9328
9329         val |= LCPLL_PLL_DISABLE;
9330         I915_WRITE(LCPLL_CTL, val);
9331         POSTING_READ(LCPLL_CTL);
9332
9333         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9334                 DRM_ERROR("LCPLL still locked\n");
9335
9336         val = hsw_read_dcomp(dev_priv);
9337         val |= D_COMP_COMP_DISABLE;
9338         hsw_write_dcomp(dev_priv, val);
9339         ndelay(100);
9340
9341         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9342                      1))
9343                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9344
9345         if (allow_power_down) {
9346                 val = I915_READ(LCPLL_CTL);
9347                 val |= LCPLL_POWER_DOWN_ALLOW;
9348                 I915_WRITE(LCPLL_CTL, val);
9349                 POSTING_READ(LCPLL_CTL);
9350         }
9351 }
9352
9353 /*
9354  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9355  * source.
9356  */
9357 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9358 {
9359         uint32_t val;
9360
9361         val = I915_READ(LCPLL_CTL);
9362
9363         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9364                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9365                 return;
9366
9367         /*
9368          * Make sure we're not on PC8 state before disabling PC8, otherwise
9369          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9370          */
9371         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9372
9373         if (val & LCPLL_POWER_DOWN_ALLOW) {
9374                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9375                 I915_WRITE(LCPLL_CTL, val);
9376                 POSTING_READ(LCPLL_CTL);
9377         }
9378
9379         val = hsw_read_dcomp(dev_priv);
9380         val |= D_COMP_COMP_FORCE;
9381         val &= ~D_COMP_COMP_DISABLE;
9382         hsw_write_dcomp(dev_priv, val);
9383
9384         val = I915_READ(LCPLL_CTL);
9385         val &= ~LCPLL_PLL_DISABLE;
9386         I915_WRITE(LCPLL_CTL, val);
9387
9388         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9389                 DRM_ERROR("LCPLL not locked yet\n");
9390
9391         if (val & LCPLL_CD_SOURCE_FCLK) {
9392                 val = I915_READ(LCPLL_CTL);
9393                 val &= ~LCPLL_CD_SOURCE_FCLK;
9394                 I915_WRITE(LCPLL_CTL, val);
9395
9396                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9397                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9398                         DRM_ERROR("Switching back to LCPLL failed\n");
9399         }
9400
9401         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9402         intel_update_cdclk(dev_priv->dev);
9403 }
9404
9405 /*
9406  * Package states C8 and deeper are really deep PC states that can only be
9407  * reached when all the devices on the system allow it, so even if the graphics
9408  * device allows PC8+, it doesn't mean the system will actually get to these
9409  * states. Our driver only allows PC8+ when going into runtime PM.
9410  *
9411  * The requirements for PC8+ are that all the outputs are disabled, the power
9412  * well is disabled and most interrupts are disabled, and these are also
9413  * requirements for runtime PM. When these conditions are met, we manually do
9414  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9415  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9416  * hang the machine.
9417  *
9418  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9419  * the state of some registers, so when we come back from PC8+ we need to
9420  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9421  * need to take care of the registers kept by RC6. Notice that this happens even
9422  * if we don't put the device in PCI D3 state (which is what currently happens
9423  * because of the runtime PM support).
9424  *
9425  * For more, read "Display Sequences for Package C8" on the hardware
9426  * documentation.
9427  */
9428 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9429 {
9430         struct drm_device *dev = dev_priv->dev;
9431         uint32_t val;
9432
9433         DRM_DEBUG_KMS("Enabling package C8+\n");
9434
9435         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9436                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9437                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9438                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9439         }
9440
9441         lpt_disable_clkout_dp(dev);
9442         hsw_disable_lcpll(dev_priv, true, true);
9443 }
9444
9445 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9446 {
9447         struct drm_device *dev = dev_priv->dev;
9448         uint32_t val;
9449
9450         DRM_DEBUG_KMS("Disabling package C8+\n");
9451
9452         hsw_restore_lcpll(dev_priv);
9453         lpt_init_pch_refclk(dev);
9454
9455         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9456                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9457                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9458                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9459         }
9460
9461         intel_prepare_ddi(dev);
9462 }
9463
9464 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9465 {
9466         struct drm_device *dev = old_state->dev;
9467         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9468
9469         broxton_set_cdclk(dev, req_cdclk);
9470 }
9471
9472 /* compute the max rate for new configuration */
9473 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9474 {
9475         struct intel_crtc *intel_crtc;
9476         struct intel_crtc_state *crtc_state;
9477         int max_pixel_rate = 0;
9478
9479         for_each_intel_crtc(state->dev, intel_crtc) {
9480                 int pixel_rate;
9481
9482                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9483                 if (IS_ERR(crtc_state))
9484                         return PTR_ERR(crtc_state);
9485
9486                 if (!crtc_state->base.enable)
9487                         continue;
9488
9489                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9490
9491                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9492                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9493                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9494
9495                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9496         }
9497
9498         return max_pixel_rate;
9499 }
9500
9501 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9502 {
9503         struct drm_i915_private *dev_priv = dev->dev_private;
9504         uint32_t val, data;
9505         int ret;
9506
9507         if (WARN((I915_READ(LCPLL_CTL) &
9508                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9509                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9510                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9511                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9512                  "trying to change cdclk frequency with cdclk not enabled\n"))
9513                 return;
9514
9515         mutex_lock(&dev_priv->rps.hw_lock);
9516         ret = sandybridge_pcode_write(dev_priv,
9517                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9518         mutex_unlock(&dev_priv->rps.hw_lock);
9519         if (ret) {
9520                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9521                 return;
9522         }
9523
9524         val = I915_READ(LCPLL_CTL);
9525         val |= LCPLL_CD_SOURCE_FCLK;
9526         I915_WRITE(LCPLL_CTL, val);
9527
9528         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9529                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9530                 DRM_ERROR("Switching to FCLK failed\n");
9531
9532         val = I915_READ(LCPLL_CTL);
9533         val &= ~LCPLL_CLK_FREQ_MASK;
9534
9535         switch (cdclk) {
9536         case 450000:
9537                 val |= LCPLL_CLK_FREQ_450;
9538                 data = 0;
9539                 break;
9540         case 540000:
9541                 val |= LCPLL_CLK_FREQ_54O_BDW;
9542                 data = 1;
9543                 break;
9544         case 337500:
9545                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9546                 data = 2;
9547                 break;
9548         case 675000:
9549                 val |= LCPLL_CLK_FREQ_675_BDW;
9550                 data = 3;
9551                 break;
9552         default:
9553                 WARN(1, "invalid cdclk frequency\n");
9554                 return;
9555         }
9556
9557         I915_WRITE(LCPLL_CTL, val);
9558
9559         val = I915_READ(LCPLL_CTL);
9560         val &= ~LCPLL_CD_SOURCE_FCLK;
9561         I915_WRITE(LCPLL_CTL, val);
9562
9563         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9564                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9565                 DRM_ERROR("Switching back to LCPLL failed\n");
9566
9567         mutex_lock(&dev_priv->rps.hw_lock);
9568         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9569         mutex_unlock(&dev_priv->rps.hw_lock);
9570
9571         intel_update_cdclk(dev);
9572
9573         WARN(cdclk != dev_priv->cdclk_freq,
9574              "cdclk requested %d kHz but got %d kHz\n",
9575              cdclk, dev_priv->cdclk_freq);
9576 }
9577
9578 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9579 {
9580         struct drm_i915_private *dev_priv = to_i915(state->dev);
9581         int max_pixclk = ilk_max_pixel_rate(state);
9582         int cdclk;
9583
9584         /*
9585          * FIXME should also account for plane ratio
9586          * once 64bpp pixel formats are supported.
9587          */
9588         if (max_pixclk > 540000)
9589                 cdclk = 675000;
9590         else if (max_pixclk > 450000)
9591                 cdclk = 540000;
9592         else if (max_pixclk > 337500)
9593                 cdclk = 450000;
9594         else
9595                 cdclk = 337500;
9596
9597         /*
9598          * FIXME move the cdclk caclulation to
9599          * compute_config() so we can fail gracegully.
9600          */
9601         if (cdclk > dev_priv->max_cdclk_freq) {
9602                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9603                           cdclk, dev_priv->max_cdclk_freq);
9604                 cdclk = dev_priv->max_cdclk_freq;
9605         }
9606
9607         to_intel_atomic_state(state)->cdclk = cdclk;
9608
9609         return 0;
9610 }
9611
9612 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9613 {
9614         struct drm_device *dev = old_state->dev;
9615         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9616
9617         broadwell_set_cdclk(dev, req_cdclk);
9618 }
9619
9620 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9621                                       struct intel_crtc_state *crtc_state)
9622 {
9623         if (!intel_ddi_pll_select(crtc, crtc_state))
9624                 return -EINVAL;
9625
9626         crtc->lowfreq_avail = false;
9627
9628         return 0;
9629 }
9630
9631 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9632                                 enum port port,
9633                                 struct intel_crtc_state *pipe_config)
9634 {
9635         switch (port) {
9636         case PORT_A:
9637                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9638                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9639                 break;
9640         case PORT_B:
9641                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9642                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9643                 break;
9644         case PORT_C:
9645                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9646                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9647                 break;
9648         default:
9649                 DRM_ERROR("Incorrect port type\n");
9650         }
9651 }
9652
9653 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9654                                 enum port port,
9655                                 struct intel_crtc_state *pipe_config)
9656 {
9657         u32 temp, dpll_ctl1;
9658
9659         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9660         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9661
9662         switch (pipe_config->ddi_pll_sel) {
9663         case SKL_DPLL0:
9664                 /*
9665                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9666                  * of the shared DPLL framework and thus needs to be read out
9667                  * separately
9668                  */
9669                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9670                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9671                 break;
9672         case SKL_DPLL1:
9673                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9674                 break;
9675         case SKL_DPLL2:
9676                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9677                 break;
9678         case SKL_DPLL3:
9679                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9680                 break;
9681         }
9682 }
9683
9684 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9685                                 enum port port,
9686                                 struct intel_crtc_state *pipe_config)
9687 {
9688         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9689
9690         switch (pipe_config->ddi_pll_sel) {
9691         case PORT_CLK_SEL_WRPLL1:
9692                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9693                 break;
9694         case PORT_CLK_SEL_WRPLL2:
9695                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9696                 break;
9697         }
9698 }
9699
9700 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9701                                        struct intel_crtc_state *pipe_config)
9702 {
9703         struct drm_device *dev = crtc->base.dev;
9704         struct drm_i915_private *dev_priv = dev->dev_private;
9705         struct intel_shared_dpll *pll;
9706         enum port port;
9707         uint32_t tmp;
9708
9709         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9710
9711         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9712
9713         if (IS_SKYLAKE(dev))
9714                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9715         else if (IS_BROXTON(dev))
9716                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9717         else
9718                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9719
9720         if (pipe_config->shared_dpll >= 0) {
9721                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9722
9723                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9724                                            &pipe_config->dpll_hw_state));
9725         }
9726
9727         /*
9728          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9729          * DDI E. So just check whether this pipe is wired to DDI E and whether
9730          * the PCH transcoder is on.
9731          */
9732         if (INTEL_INFO(dev)->gen < 9 &&
9733             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9734                 pipe_config->has_pch_encoder = true;
9735
9736                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9737                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9738                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9739
9740                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9741         }
9742 }
9743
9744 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9745                                     struct intel_crtc_state *pipe_config)
9746 {
9747         struct drm_device *dev = crtc->base.dev;
9748         struct drm_i915_private *dev_priv = dev->dev_private;
9749         enum intel_display_power_domain pfit_domain;
9750         uint32_t tmp;
9751
9752         if (!intel_display_power_is_enabled(dev_priv,
9753                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9754                 return false;
9755
9756         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9757         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9758
9759         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9760         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9761                 enum pipe trans_edp_pipe;
9762                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9763                 default:
9764                         WARN(1, "unknown pipe linked to edp transcoder\n");
9765                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9766                 case TRANS_DDI_EDP_INPUT_A_ON:
9767                         trans_edp_pipe = PIPE_A;
9768                         break;
9769                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9770                         trans_edp_pipe = PIPE_B;
9771                         break;
9772                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9773                         trans_edp_pipe = PIPE_C;
9774                         break;
9775                 }
9776
9777                 if (trans_edp_pipe == crtc->pipe)
9778                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9779         }
9780
9781         if (!intel_display_power_is_enabled(dev_priv,
9782                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9783                 return false;
9784
9785         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9786         if (!(tmp & PIPECONF_ENABLE))
9787                 return false;
9788
9789         haswell_get_ddi_port_state(crtc, pipe_config);
9790
9791         intel_get_pipe_timings(crtc, pipe_config);
9792
9793         if (INTEL_INFO(dev)->gen >= 9) {
9794                 skl_init_scalers(dev, crtc, pipe_config);
9795         }
9796
9797         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9798
9799         if (INTEL_INFO(dev)->gen >= 9) {
9800                 pipe_config->scaler_state.scaler_id = -1;
9801                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9802         }
9803
9804         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9805                 if (INTEL_INFO(dev)->gen == 9)
9806                         skylake_get_pfit_config(crtc, pipe_config);
9807                 else if (INTEL_INFO(dev)->gen < 9)
9808                         ironlake_get_pfit_config(crtc, pipe_config);
9809                 else
9810                         MISSING_CASE(INTEL_INFO(dev)->gen);
9811         }
9812
9813         if (IS_HASWELL(dev))
9814                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9815                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9816
9817         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9818                 pipe_config->pixel_multiplier =
9819                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9820         } else {
9821                 pipe_config->pixel_multiplier = 1;
9822         }
9823
9824         return true;
9825 }
9826
9827 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9828 {
9829         struct drm_device *dev = crtc->dev;
9830         struct drm_i915_private *dev_priv = dev->dev_private;
9831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9832         uint32_t cntl = 0, size = 0;
9833
9834         if (base) {
9835                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9836                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9837                 unsigned int stride = roundup_pow_of_two(width) * 4;
9838
9839                 switch (stride) {
9840                 default:
9841                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9842                                   width, stride);
9843                         stride = 256;
9844                         /* fallthrough */
9845                 case 256:
9846                 case 512:
9847                 case 1024:
9848                 case 2048:
9849                         break;
9850                 }
9851
9852                 cntl |= CURSOR_ENABLE |
9853                         CURSOR_GAMMA_ENABLE |
9854                         CURSOR_FORMAT_ARGB |
9855                         CURSOR_STRIDE(stride);
9856
9857                 size = (height << 12) | width;
9858         }
9859
9860         if (intel_crtc->cursor_cntl != 0 &&
9861             (intel_crtc->cursor_base != base ||
9862              intel_crtc->cursor_size != size ||
9863              intel_crtc->cursor_cntl != cntl)) {
9864                 /* On these chipsets we can only modify the base/size/stride
9865                  * whilst the cursor is disabled.
9866                  */
9867                 I915_WRITE(_CURACNTR, 0);
9868                 POSTING_READ(_CURACNTR);
9869                 intel_crtc->cursor_cntl = 0;
9870         }
9871
9872         if (intel_crtc->cursor_base != base) {
9873                 I915_WRITE(_CURABASE, base);
9874                 intel_crtc->cursor_base = base;
9875         }
9876
9877         if (intel_crtc->cursor_size != size) {
9878                 I915_WRITE(CURSIZE, size);
9879                 intel_crtc->cursor_size = size;
9880         }
9881
9882         if (intel_crtc->cursor_cntl != cntl) {
9883                 I915_WRITE(_CURACNTR, cntl);
9884                 POSTING_READ(_CURACNTR);
9885                 intel_crtc->cursor_cntl = cntl;
9886         }
9887 }
9888
9889 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9890 {
9891         struct drm_device *dev = crtc->dev;
9892         struct drm_i915_private *dev_priv = dev->dev_private;
9893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9894         int pipe = intel_crtc->pipe;
9895         uint32_t cntl;
9896
9897         cntl = 0;
9898         if (base) {
9899                 cntl = MCURSOR_GAMMA_ENABLE;
9900                 switch (intel_crtc->base.cursor->state->crtc_w) {
9901                         case 64:
9902                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9903                                 break;
9904                         case 128:
9905                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9906                                 break;
9907                         case 256:
9908                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9909                                 break;
9910                         default:
9911                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9912                                 return;
9913                 }
9914                 cntl |= pipe << 28; /* Connect to correct pipe */
9915
9916                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9917                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9918         }
9919
9920         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9921                 cntl |= CURSOR_ROTATE_180;
9922
9923         if (intel_crtc->cursor_cntl != cntl) {
9924                 I915_WRITE(CURCNTR(pipe), cntl);
9925                 POSTING_READ(CURCNTR(pipe));
9926                 intel_crtc->cursor_cntl = cntl;
9927         }
9928
9929         /* and commit changes on next vblank */
9930         I915_WRITE(CURBASE(pipe), base);
9931         POSTING_READ(CURBASE(pipe));
9932
9933         intel_crtc->cursor_base = base;
9934 }
9935
9936 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9937 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9938                                      bool on)
9939 {
9940         struct drm_device *dev = crtc->dev;
9941         struct drm_i915_private *dev_priv = dev->dev_private;
9942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9943         int pipe = intel_crtc->pipe;
9944         int x = crtc->cursor_x;
9945         int y = crtc->cursor_y;
9946         u32 base = 0, pos = 0;
9947
9948         if (on)
9949                 base = intel_crtc->cursor_addr;
9950
9951         if (x >= intel_crtc->config->pipe_src_w)
9952                 base = 0;
9953
9954         if (y >= intel_crtc->config->pipe_src_h)
9955                 base = 0;
9956
9957         if (x < 0) {
9958                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9959                         base = 0;
9960
9961                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9962                 x = -x;
9963         }
9964         pos |= x << CURSOR_X_SHIFT;
9965
9966         if (y < 0) {
9967                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9968                         base = 0;
9969
9970                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9971                 y = -y;
9972         }
9973         pos |= y << CURSOR_Y_SHIFT;
9974
9975         if (base == 0 && intel_crtc->cursor_base == 0)
9976                 return;
9977
9978         I915_WRITE(CURPOS(pipe), pos);
9979
9980         /* ILK+ do this automagically */
9981         if (HAS_GMCH_DISPLAY(dev) &&
9982             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9983                 base += (intel_crtc->base.cursor->state->crtc_h *
9984                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9985         }
9986
9987         if (IS_845G(dev) || IS_I865G(dev))
9988                 i845_update_cursor(crtc, base);
9989         else
9990                 i9xx_update_cursor(crtc, base);
9991 }
9992
9993 static bool cursor_size_ok(struct drm_device *dev,
9994                            uint32_t width, uint32_t height)
9995 {
9996         if (width == 0 || height == 0)
9997                 return false;
9998
9999         /*
10000          * 845g/865g are special in that they are only limited by
10001          * the width of their cursors, the height is arbitrary up to
10002          * the precision of the register. Everything else requires
10003          * square cursors, limited to a few power-of-two sizes.
10004          */
10005         if (IS_845G(dev) || IS_I865G(dev)) {
10006                 if ((width & 63) != 0)
10007                         return false;
10008
10009                 if (width > (IS_845G(dev) ? 64 : 512))
10010                         return false;
10011
10012                 if (height > 1023)
10013                         return false;
10014         } else {
10015                 switch (width | height) {
10016                 case 256:
10017                 case 128:
10018                         if (IS_GEN2(dev))
10019                                 return false;
10020                 case 64:
10021                         break;
10022                 default:
10023                         return false;
10024                 }
10025         }
10026
10027         return true;
10028 }
10029
10030 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10031                                  u16 *blue, uint32_t start, uint32_t size)
10032 {
10033         int end = (start + size > 256) ? 256 : start + size, i;
10034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10035
10036         for (i = start; i < end; i++) {
10037                 intel_crtc->lut_r[i] = red[i] >> 8;
10038                 intel_crtc->lut_g[i] = green[i] >> 8;
10039                 intel_crtc->lut_b[i] = blue[i] >> 8;
10040         }
10041
10042         intel_crtc_load_lut(crtc);
10043 }
10044
10045 /* VESA 640x480x72Hz mode to set on the pipe */
10046 static struct drm_display_mode load_detect_mode = {
10047         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10048                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10049 };
10050
10051 struct drm_framebuffer *
10052 __intel_framebuffer_create(struct drm_device *dev,
10053                            struct drm_mode_fb_cmd2 *mode_cmd,
10054                            struct drm_i915_gem_object *obj)
10055 {
10056         struct intel_framebuffer *intel_fb;
10057         int ret;
10058
10059         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10060         if (!intel_fb) {
10061                 drm_gem_object_unreference(&obj->base);
10062                 return ERR_PTR(-ENOMEM);
10063         }
10064
10065         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10066         if (ret)
10067                 goto err;
10068
10069         return &intel_fb->base;
10070 err:
10071         drm_gem_object_unreference(&obj->base);
10072         kfree(intel_fb);
10073
10074         return ERR_PTR(ret);
10075 }
10076
10077 static struct drm_framebuffer *
10078 intel_framebuffer_create(struct drm_device *dev,
10079                          struct drm_mode_fb_cmd2 *mode_cmd,
10080                          struct drm_i915_gem_object *obj)
10081 {
10082         struct drm_framebuffer *fb;
10083         int ret;
10084
10085         ret = i915_mutex_lock_interruptible(dev);
10086         if (ret)
10087                 return ERR_PTR(ret);
10088         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10089         mutex_unlock(&dev->struct_mutex);
10090
10091         return fb;
10092 }
10093
10094 static u32
10095 intel_framebuffer_pitch_for_width(int width, int bpp)
10096 {
10097         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10098         return ALIGN(pitch, 64);
10099 }
10100
10101 static u32
10102 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10103 {
10104         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10105         return PAGE_ALIGN(pitch * mode->vdisplay);
10106 }
10107
10108 static struct drm_framebuffer *
10109 intel_framebuffer_create_for_mode(struct drm_device *dev,
10110                                   struct drm_display_mode *mode,
10111                                   int depth, int bpp)
10112 {
10113         struct drm_i915_gem_object *obj;
10114         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10115
10116         obj = i915_gem_alloc_object(dev,
10117                                     intel_framebuffer_size_for_mode(mode, bpp));
10118         if (obj == NULL)
10119                 return ERR_PTR(-ENOMEM);
10120
10121         mode_cmd.width = mode->hdisplay;
10122         mode_cmd.height = mode->vdisplay;
10123         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10124                                                                 bpp);
10125         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10126
10127         return intel_framebuffer_create(dev, &mode_cmd, obj);
10128 }
10129
10130 static struct drm_framebuffer *
10131 mode_fits_in_fbdev(struct drm_device *dev,
10132                    struct drm_display_mode *mode)
10133 {
10134 #ifdef CONFIG_DRM_I915_FBDEV
10135         struct drm_i915_private *dev_priv = dev->dev_private;
10136         struct drm_i915_gem_object *obj;
10137         struct drm_framebuffer *fb;
10138
10139         if (!dev_priv->fbdev)
10140                 return NULL;
10141
10142         if (!dev_priv->fbdev->fb)
10143                 return NULL;
10144
10145         obj = dev_priv->fbdev->fb->obj;
10146         BUG_ON(!obj);
10147
10148         fb = &dev_priv->fbdev->fb->base;
10149         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10150                                                                fb->bits_per_pixel))
10151                 return NULL;
10152
10153         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10154                 return NULL;
10155
10156         return fb;
10157 #else
10158         return NULL;
10159 #endif
10160 }
10161
10162 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10163                                            struct drm_crtc *crtc,
10164                                            struct drm_display_mode *mode,
10165                                            struct drm_framebuffer *fb,
10166                                            int x, int y)
10167 {
10168         struct drm_plane_state *plane_state;
10169         int hdisplay, vdisplay;
10170         int ret;
10171
10172         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10173         if (IS_ERR(plane_state))
10174                 return PTR_ERR(plane_state);
10175
10176         if (mode)
10177                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10178         else
10179                 hdisplay = vdisplay = 0;
10180
10181         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10182         if (ret)
10183                 return ret;
10184         drm_atomic_set_fb_for_plane(plane_state, fb);
10185         plane_state->crtc_x = 0;
10186         plane_state->crtc_y = 0;
10187         plane_state->crtc_w = hdisplay;
10188         plane_state->crtc_h = vdisplay;
10189         plane_state->src_x = x << 16;
10190         plane_state->src_y = y << 16;
10191         plane_state->src_w = hdisplay << 16;
10192         plane_state->src_h = vdisplay << 16;
10193
10194         return 0;
10195 }
10196
10197 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10198                                 struct drm_display_mode *mode,
10199                                 struct intel_load_detect_pipe *old,
10200                                 struct drm_modeset_acquire_ctx *ctx)
10201 {
10202         struct intel_crtc *intel_crtc;
10203         struct intel_encoder *intel_encoder =
10204                 intel_attached_encoder(connector);
10205         struct drm_crtc *possible_crtc;
10206         struct drm_encoder *encoder = &intel_encoder->base;
10207         struct drm_crtc *crtc = NULL;
10208         struct drm_device *dev = encoder->dev;
10209         struct drm_framebuffer *fb;
10210         struct drm_mode_config *config = &dev->mode_config;
10211         struct drm_atomic_state *state = NULL;
10212         struct drm_connector_state *connector_state;
10213         struct intel_crtc_state *crtc_state;
10214         int ret, i = -1;
10215
10216         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10217                       connector->base.id, connector->name,
10218                       encoder->base.id, encoder->name);
10219
10220 retry:
10221         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10222         if (ret)
10223                 goto fail_unlock;
10224
10225         /*
10226          * Algorithm gets a little messy:
10227          *
10228          *   - if the connector already has an assigned crtc, use it (but make
10229          *     sure it's on first)
10230          *
10231          *   - try to find the first unused crtc that can drive this connector,
10232          *     and use that if we find one
10233          */
10234
10235         /* See if we already have a CRTC for this connector */
10236         if (encoder->crtc) {
10237                 crtc = encoder->crtc;
10238
10239                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10240                 if (ret)
10241                         goto fail_unlock;
10242                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10243                 if (ret)
10244                         goto fail_unlock;
10245
10246                 old->dpms_mode = connector->dpms;
10247                 old->load_detect_temp = false;
10248
10249                 /* Make sure the crtc and connector are running */
10250                 if (connector->dpms != DRM_MODE_DPMS_ON)
10251                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10252
10253                 return true;
10254         }
10255
10256         /* Find an unused one (if possible) */
10257         for_each_crtc(dev, possible_crtc) {
10258                 i++;
10259                 if (!(encoder->possible_crtcs & (1 << i)))
10260                         continue;
10261                 if (possible_crtc->state->enable)
10262                         continue;
10263                 /* This can occur when applying the pipe A quirk on resume. */
10264                 if (to_intel_crtc(possible_crtc)->new_enabled)
10265                         continue;
10266
10267                 crtc = possible_crtc;
10268                 break;
10269         }
10270
10271         /*
10272          * If we didn't find an unused CRTC, don't use any.
10273          */
10274         if (!crtc) {
10275                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10276                 goto fail_unlock;
10277         }
10278
10279         ret = drm_modeset_lock(&crtc->mutex, ctx);
10280         if (ret)
10281                 goto fail_unlock;
10282         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10283         if (ret)
10284                 goto fail_unlock;
10285         intel_encoder->new_crtc = to_intel_crtc(crtc);
10286         to_intel_connector(connector)->new_encoder = intel_encoder;
10287
10288         intel_crtc = to_intel_crtc(crtc);
10289         intel_crtc->new_enabled = true;
10290         old->dpms_mode = connector->dpms;
10291         old->load_detect_temp = true;
10292         old->release_fb = NULL;
10293
10294         state = drm_atomic_state_alloc(dev);
10295         if (!state)
10296                 return false;
10297
10298         state->acquire_ctx = ctx;
10299
10300         connector_state = drm_atomic_get_connector_state(state, connector);
10301         if (IS_ERR(connector_state)) {
10302                 ret = PTR_ERR(connector_state);
10303                 goto fail;
10304         }
10305
10306         connector_state->crtc = crtc;
10307         connector_state->best_encoder = &intel_encoder->base;
10308
10309         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10310         if (IS_ERR(crtc_state)) {
10311                 ret = PTR_ERR(crtc_state);
10312                 goto fail;
10313         }
10314
10315         crtc_state->base.active = crtc_state->base.enable = true;
10316
10317         if (!mode)
10318                 mode = &load_detect_mode;
10319
10320         /* We need a framebuffer large enough to accommodate all accesses
10321          * that the plane may generate whilst we perform load detection.
10322          * We can not rely on the fbcon either being present (we get called
10323          * during its initialisation to detect all boot displays, or it may
10324          * not even exist) or that it is large enough to satisfy the
10325          * requested mode.
10326          */
10327         fb = mode_fits_in_fbdev(dev, mode);
10328         if (fb == NULL) {
10329                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10330                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10331                 old->release_fb = fb;
10332         } else
10333                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10334         if (IS_ERR(fb)) {
10335                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10336                 goto fail;
10337         }
10338
10339         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10340         if (ret)
10341                 goto fail;
10342
10343         drm_mode_copy(&crtc_state->base.mode, mode);
10344
10345         if (intel_set_mode(state)) {
10346                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10347                 if (old->release_fb)
10348                         old->release_fb->funcs->destroy(old->release_fb);
10349                 goto fail;
10350         }
10351         crtc->primary->crtc = crtc;
10352
10353         /* let the connector get through one full cycle before testing */
10354         intel_wait_for_vblank(dev, intel_crtc->pipe);
10355         return true;
10356
10357  fail:
10358         intel_crtc->new_enabled = crtc->state->enable;
10359 fail_unlock:
10360         drm_atomic_state_free(state);
10361         state = NULL;
10362
10363         if (ret == -EDEADLK) {
10364                 drm_modeset_backoff(ctx);
10365                 goto retry;
10366         }
10367
10368         return false;
10369 }
10370
10371 void intel_release_load_detect_pipe(struct drm_connector *connector,
10372                                     struct intel_load_detect_pipe *old,
10373                                     struct drm_modeset_acquire_ctx *ctx)
10374 {
10375         struct drm_device *dev = connector->dev;
10376         struct intel_encoder *intel_encoder =
10377                 intel_attached_encoder(connector);
10378         struct drm_encoder *encoder = &intel_encoder->base;
10379         struct drm_crtc *crtc = encoder->crtc;
10380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10381         struct drm_atomic_state *state;
10382         struct drm_connector_state *connector_state;
10383         struct intel_crtc_state *crtc_state;
10384         int ret;
10385
10386         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10387                       connector->base.id, connector->name,
10388                       encoder->base.id, encoder->name);
10389
10390         if (old->load_detect_temp) {
10391                 state = drm_atomic_state_alloc(dev);
10392                 if (!state)
10393                         goto fail;
10394
10395                 state->acquire_ctx = ctx;
10396
10397                 connector_state = drm_atomic_get_connector_state(state, connector);
10398                 if (IS_ERR(connector_state))
10399                         goto fail;
10400
10401                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10402                 if (IS_ERR(crtc_state))
10403                         goto fail;
10404
10405                 to_intel_connector(connector)->new_encoder = NULL;
10406                 intel_encoder->new_crtc = NULL;
10407                 intel_crtc->new_enabled = false;
10408
10409                 connector_state->best_encoder = NULL;
10410                 connector_state->crtc = NULL;
10411
10412                 crtc_state->base.enable = crtc_state->base.active = false;
10413
10414                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10415                                                       0, 0);
10416                 if (ret)
10417                         goto fail;
10418
10419                 ret = intel_set_mode(state);
10420                 if (ret)
10421                         goto fail;
10422
10423                 if (old->release_fb) {
10424                         drm_framebuffer_unregister_private(old->release_fb);
10425                         drm_framebuffer_unreference(old->release_fb);
10426                 }
10427
10428                 return;
10429         }
10430
10431         /* Switch crtc and encoder back off if necessary */
10432         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10433                 connector->funcs->dpms(connector, old->dpms_mode);
10434
10435         return;
10436 fail:
10437         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10438         drm_atomic_state_free(state);
10439 }
10440
10441 static int i9xx_pll_refclk(struct drm_device *dev,
10442                            const struct intel_crtc_state *pipe_config)
10443 {
10444         struct drm_i915_private *dev_priv = dev->dev_private;
10445         u32 dpll = pipe_config->dpll_hw_state.dpll;
10446
10447         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10448                 return dev_priv->vbt.lvds_ssc_freq;
10449         else if (HAS_PCH_SPLIT(dev))
10450                 return 120000;
10451         else if (!IS_GEN2(dev))
10452                 return 96000;
10453         else
10454                 return 48000;
10455 }
10456
10457 /* Returns the clock of the currently programmed mode of the given pipe. */
10458 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10459                                 struct intel_crtc_state *pipe_config)
10460 {
10461         struct drm_device *dev = crtc->base.dev;
10462         struct drm_i915_private *dev_priv = dev->dev_private;
10463         int pipe = pipe_config->cpu_transcoder;
10464         u32 dpll = pipe_config->dpll_hw_state.dpll;
10465         u32 fp;
10466         intel_clock_t clock;
10467         int refclk = i9xx_pll_refclk(dev, pipe_config);
10468
10469         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10470                 fp = pipe_config->dpll_hw_state.fp0;
10471         else
10472                 fp = pipe_config->dpll_hw_state.fp1;
10473
10474         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10475         if (IS_PINEVIEW(dev)) {
10476                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10477                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10478         } else {
10479                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10480                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10481         }
10482
10483         if (!IS_GEN2(dev)) {
10484                 if (IS_PINEVIEW(dev))
10485                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10486                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10487                 else
10488                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10489                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10490
10491                 switch (dpll & DPLL_MODE_MASK) {
10492                 case DPLLB_MODE_DAC_SERIAL:
10493                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10494                                 5 : 10;
10495                         break;
10496                 case DPLLB_MODE_LVDS:
10497                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10498                                 7 : 14;
10499                         break;
10500                 default:
10501                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10502                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10503                         return;
10504                 }
10505
10506                 if (IS_PINEVIEW(dev))
10507                         pineview_clock(refclk, &clock);
10508                 else
10509                         i9xx_clock(refclk, &clock);
10510         } else {
10511                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10512                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10513
10514                 if (is_lvds) {
10515                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10516                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10517
10518                         if (lvds & LVDS_CLKB_POWER_UP)
10519                                 clock.p2 = 7;
10520                         else
10521                                 clock.p2 = 14;
10522                 } else {
10523                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10524                                 clock.p1 = 2;
10525                         else {
10526                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10527                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10528                         }
10529                         if (dpll & PLL_P2_DIVIDE_BY_4)
10530                                 clock.p2 = 4;
10531                         else
10532                                 clock.p2 = 2;
10533                 }
10534
10535                 i9xx_clock(refclk, &clock);
10536         }
10537
10538         /*
10539          * This value includes pixel_multiplier. We will use
10540          * port_clock to compute adjusted_mode.crtc_clock in the
10541          * encoder's get_config() function.
10542          */
10543         pipe_config->port_clock = clock.dot;
10544 }
10545
10546 int intel_dotclock_calculate(int link_freq,
10547                              const struct intel_link_m_n *m_n)
10548 {
10549         /*
10550          * The calculation for the data clock is:
10551          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10552          * But we want to avoid losing precison if possible, so:
10553          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10554          *
10555          * and the link clock is simpler:
10556          * link_clock = (m * link_clock) / n
10557          */
10558
10559         if (!m_n->link_n)
10560                 return 0;
10561
10562         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10563 }
10564
10565 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10566                                    struct intel_crtc_state *pipe_config)
10567 {
10568         struct drm_device *dev = crtc->base.dev;
10569
10570         /* read out port_clock from the DPLL */
10571         i9xx_crtc_clock_get(crtc, pipe_config);
10572
10573         /*
10574          * This value does not include pixel_multiplier.
10575          * We will check that port_clock and adjusted_mode.crtc_clock
10576          * agree once we know their relationship in the encoder's
10577          * get_config() function.
10578          */
10579         pipe_config->base.adjusted_mode.crtc_clock =
10580                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10581                                          &pipe_config->fdi_m_n);
10582 }
10583
10584 /** Returns the currently programmed mode of the given pipe. */
10585 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10586                                              struct drm_crtc *crtc)
10587 {
10588         struct drm_i915_private *dev_priv = dev->dev_private;
10589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10590         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10591         struct drm_display_mode *mode;
10592         struct intel_crtc_state pipe_config;
10593         int htot = I915_READ(HTOTAL(cpu_transcoder));
10594         int hsync = I915_READ(HSYNC(cpu_transcoder));
10595         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10596         int vsync = I915_READ(VSYNC(cpu_transcoder));
10597         enum pipe pipe = intel_crtc->pipe;
10598
10599         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10600         if (!mode)
10601                 return NULL;
10602
10603         /*
10604          * Construct a pipe_config sufficient for getting the clock info
10605          * back out of crtc_clock_get.
10606          *
10607          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10608          * to use a real value here instead.
10609          */
10610         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10611         pipe_config.pixel_multiplier = 1;
10612         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10613         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10614         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10615         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10616
10617         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10618         mode->hdisplay = (htot & 0xffff) + 1;
10619         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10620         mode->hsync_start = (hsync & 0xffff) + 1;
10621         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10622         mode->vdisplay = (vtot & 0xffff) + 1;
10623         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10624         mode->vsync_start = (vsync & 0xffff) + 1;
10625         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10626
10627         drm_mode_set_name(mode);
10628
10629         return mode;
10630 }
10631
10632 void intel_mark_busy(struct drm_device *dev)
10633 {
10634         struct drm_i915_private *dev_priv = dev->dev_private;
10635
10636         if (dev_priv->mm.busy)
10637                 return;
10638
10639         intel_runtime_pm_get(dev_priv);
10640         i915_update_gfx_val(dev_priv);
10641         if (INTEL_INFO(dev)->gen >= 6)
10642                 gen6_rps_busy(dev_priv);
10643         dev_priv->mm.busy = true;
10644 }
10645
10646 void intel_mark_idle(struct drm_device *dev)
10647 {
10648         struct drm_i915_private *dev_priv = dev->dev_private;
10649
10650         if (!dev_priv->mm.busy)
10651                 return;
10652
10653         dev_priv->mm.busy = false;
10654
10655         if (INTEL_INFO(dev)->gen >= 6)
10656                 gen6_rps_idle(dev->dev_private);
10657
10658         intel_runtime_pm_put(dev_priv);
10659 }
10660
10661 static void intel_crtc_destroy(struct drm_crtc *crtc)
10662 {
10663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10664         struct drm_device *dev = crtc->dev;
10665         struct intel_unpin_work *work;
10666
10667         spin_lock_irq(&dev->event_lock);
10668         work = intel_crtc->unpin_work;
10669         intel_crtc->unpin_work = NULL;
10670         spin_unlock_irq(&dev->event_lock);
10671
10672         if (work) {
10673                 cancel_work_sync(&work->work);
10674                 kfree(work);
10675         }
10676
10677         drm_crtc_cleanup(crtc);
10678
10679         kfree(intel_crtc);
10680 }
10681
10682 static void intel_unpin_work_fn(struct work_struct *__work)
10683 {
10684         struct intel_unpin_work *work =
10685                 container_of(__work, struct intel_unpin_work, work);
10686         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10687         struct drm_device *dev = crtc->base.dev;
10688         struct drm_plane *primary = crtc->base.primary;
10689
10690         mutex_lock(&dev->struct_mutex);
10691         intel_unpin_fb_obj(work->old_fb, primary->state);
10692         drm_gem_object_unreference(&work->pending_flip_obj->base);
10693
10694         intel_fbc_update(dev);
10695
10696         if (work->flip_queued_req)
10697                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10698         mutex_unlock(&dev->struct_mutex);
10699
10700         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10701         drm_framebuffer_unreference(work->old_fb);
10702
10703         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10704         atomic_dec(&crtc->unpin_work_count);
10705
10706         kfree(work);
10707 }
10708
10709 static void do_intel_finish_page_flip(struct drm_device *dev,
10710                                       struct drm_crtc *crtc)
10711 {
10712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10713         struct intel_unpin_work *work;
10714         unsigned long flags;
10715
10716         /* Ignore early vblank irqs */
10717         if (intel_crtc == NULL)
10718                 return;
10719
10720         /*
10721          * This is called both by irq handlers and the reset code (to complete
10722          * lost pageflips) so needs the full irqsave spinlocks.
10723          */
10724         spin_lock_irqsave(&dev->event_lock, flags);
10725         work = intel_crtc->unpin_work;
10726
10727         /* Ensure we don't miss a work->pending update ... */
10728         smp_rmb();
10729
10730         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10731                 spin_unlock_irqrestore(&dev->event_lock, flags);
10732                 return;
10733         }
10734
10735         page_flip_completed(intel_crtc);
10736
10737         spin_unlock_irqrestore(&dev->event_lock, flags);
10738 }
10739
10740 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10741 {
10742         struct drm_i915_private *dev_priv = dev->dev_private;
10743         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10744
10745         do_intel_finish_page_flip(dev, crtc);
10746 }
10747
10748 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10749 {
10750         struct drm_i915_private *dev_priv = dev->dev_private;
10751         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10752
10753         do_intel_finish_page_flip(dev, crtc);
10754 }
10755
10756 /* Is 'a' after or equal to 'b'? */
10757 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10758 {
10759         return !((a - b) & 0x80000000);
10760 }
10761
10762 static bool page_flip_finished(struct intel_crtc *crtc)
10763 {
10764         struct drm_device *dev = crtc->base.dev;
10765         struct drm_i915_private *dev_priv = dev->dev_private;
10766
10767         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10768             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10769                 return true;
10770
10771         /*
10772          * The relevant registers doen't exist on pre-ctg.
10773          * As the flip done interrupt doesn't trigger for mmio
10774          * flips on gmch platforms, a flip count check isn't
10775          * really needed there. But since ctg has the registers,
10776          * include it in the check anyway.
10777          */
10778         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10779                 return true;
10780
10781         /*
10782          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10783          * used the same base address. In that case the mmio flip might
10784          * have completed, but the CS hasn't even executed the flip yet.
10785          *
10786          * A flip count check isn't enough as the CS might have updated
10787          * the base address just after start of vblank, but before we
10788          * managed to process the interrupt. This means we'd complete the
10789          * CS flip too soon.
10790          *
10791          * Combining both checks should get us a good enough result. It may
10792          * still happen that the CS flip has been executed, but has not
10793          * yet actually completed. But in case the base address is the same
10794          * anyway, we don't really care.
10795          */
10796         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10797                 crtc->unpin_work->gtt_offset &&
10798                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10799                                     crtc->unpin_work->flip_count);
10800 }
10801
10802 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10803 {
10804         struct drm_i915_private *dev_priv = dev->dev_private;
10805         struct intel_crtc *intel_crtc =
10806                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10807         unsigned long flags;
10808
10809
10810         /*
10811          * This is called both by irq handlers and the reset code (to complete
10812          * lost pageflips) so needs the full irqsave spinlocks.
10813          *
10814          * NB: An MMIO update of the plane base pointer will also
10815          * generate a page-flip completion irq, i.e. every modeset
10816          * is also accompanied by a spurious intel_prepare_page_flip().
10817          */
10818         spin_lock_irqsave(&dev->event_lock, flags);
10819         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10820                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10821         spin_unlock_irqrestore(&dev->event_lock, flags);
10822 }
10823
10824 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10825 {
10826         /* Ensure that the work item is consistent when activating it ... */
10827         smp_wmb();
10828         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10829         /* and that it is marked active as soon as the irq could fire. */
10830         smp_wmb();
10831 }
10832
10833 static int intel_gen2_queue_flip(struct drm_device *dev,
10834                                  struct drm_crtc *crtc,
10835                                  struct drm_framebuffer *fb,
10836                                  struct drm_i915_gem_object *obj,
10837                                  struct drm_i915_gem_request *req,
10838                                  uint32_t flags)
10839 {
10840         struct intel_engine_cs *ring = req->ring;
10841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10842         u32 flip_mask;
10843         int ret;
10844
10845         ret = intel_ring_begin(req, 6);
10846         if (ret)
10847                 return ret;
10848
10849         /* Can't queue multiple flips, so wait for the previous
10850          * one to finish before executing the next.
10851          */
10852         if (intel_crtc->plane)
10853                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10854         else
10855                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10856         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10857         intel_ring_emit(ring, MI_NOOP);
10858         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10859                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10860         intel_ring_emit(ring, fb->pitches[0]);
10861         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10862         intel_ring_emit(ring, 0); /* aux display base address, unused */
10863
10864         intel_mark_page_flip_active(intel_crtc);
10865         return 0;
10866 }
10867
10868 static int intel_gen3_queue_flip(struct drm_device *dev,
10869                                  struct drm_crtc *crtc,
10870                                  struct drm_framebuffer *fb,
10871                                  struct drm_i915_gem_object *obj,
10872                                  struct drm_i915_gem_request *req,
10873                                  uint32_t flags)
10874 {
10875         struct intel_engine_cs *ring = req->ring;
10876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10877         u32 flip_mask;
10878         int ret;
10879
10880         ret = intel_ring_begin(req, 6);
10881         if (ret)
10882                 return ret;
10883
10884         if (intel_crtc->plane)
10885                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10886         else
10887                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10888         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10889         intel_ring_emit(ring, MI_NOOP);
10890         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10891                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10892         intel_ring_emit(ring, fb->pitches[0]);
10893         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10894         intel_ring_emit(ring, MI_NOOP);
10895
10896         intel_mark_page_flip_active(intel_crtc);
10897         return 0;
10898 }
10899
10900 static int intel_gen4_queue_flip(struct drm_device *dev,
10901                                  struct drm_crtc *crtc,
10902                                  struct drm_framebuffer *fb,
10903                                  struct drm_i915_gem_object *obj,
10904                                  struct drm_i915_gem_request *req,
10905                                  uint32_t flags)
10906 {
10907         struct intel_engine_cs *ring = req->ring;
10908         struct drm_i915_private *dev_priv = dev->dev_private;
10909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10910         uint32_t pf, pipesrc;
10911         int ret;
10912
10913         ret = intel_ring_begin(req, 4);
10914         if (ret)
10915                 return ret;
10916
10917         /* i965+ uses the linear or tiled offsets from the
10918          * Display Registers (which do not change across a page-flip)
10919          * so we need only reprogram the base address.
10920          */
10921         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10922                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10923         intel_ring_emit(ring, fb->pitches[0]);
10924         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10925                         obj->tiling_mode);
10926
10927         /* XXX Enabling the panel-fitter across page-flip is so far
10928          * untested on non-native modes, so ignore it for now.
10929          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10930          */
10931         pf = 0;
10932         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10933         intel_ring_emit(ring, pf | pipesrc);
10934
10935         intel_mark_page_flip_active(intel_crtc);
10936         return 0;
10937 }
10938
10939 static int intel_gen6_queue_flip(struct drm_device *dev,
10940                                  struct drm_crtc *crtc,
10941                                  struct drm_framebuffer *fb,
10942                                  struct drm_i915_gem_object *obj,
10943                                  struct drm_i915_gem_request *req,
10944                                  uint32_t flags)
10945 {
10946         struct intel_engine_cs *ring = req->ring;
10947         struct drm_i915_private *dev_priv = dev->dev_private;
10948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10949         uint32_t pf, pipesrc;
10950         int ret;
10951
10952         ret = intel_ring_begin(req, 4);
10953         if (ret)
10954                 return ret;
10955
10956         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10957                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10958         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10959         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10960
10961         /* Contrary to the suggestions in the documentation,
10962          * "Enable Panel Fitter" does not seem to be required when page
10963          * flipping with a non-native mode, and worse causes a normal
10964          * modeset to fail.
10965          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10966          */
10967         pf = 0;
10968         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10969         intel_ring_emit(ring, pf | pipesrc);
10970
10971         intel_mark_page_flip_active(intel_crtc);
10972         return 0;
10973 }
10974
10975 static int intel_gen7_queue_flip(struct drm_device *dev,
10976                                  struct drm_crtc *crtc,
10977                                  struct drm_framebuffer *fb,
10978                                  struct drm_i915_gem_object *obj,
10979                                  struct drm_i915_gem_request *req,
10980                                  uint32_t flags)
10981 {
10982         struct intel_engine_cs *ring = req->ring;
10983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10984         uint32_t plane_bit = 0;
10985         int len, ret;
10986
10987         switch (intel_crtc->plane) {
10988         case PLANE_A:
10989                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10990                 break;
10991         case PLANE_B:
10992                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10993                 break;
10994         case PLANE_C:
10995                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10996                 break;
10997         default:
10998                 WARN_ONCE(1, "unknown plane in flip command\n");
10999                 return -ENODEV;
11000         }
11001
11002         len = 4;
11003         if (ring->id == RCS) {
11004                 len += 6;
11005                 /*
11006                  * On Gen 8, SRM is now taking an extra dword to accommodate
11007                  * 48bits addresses, and we need a NOOP for the batch size to
11008                  * stay even.
11009                  */
11010                 if (IS_GEN8(dev))
11011                         len += 2;
11012         }
11013
11014         /*
11015          * BSpec MI_DISPLAY_FLIP for IVB:
11016          * "The full packet must be contained within the same cache line."
11017          *
11018          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11019          * cacheline, if we ever start emitting more commands before
11020          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11021          * then do the cacheline alignment, and finally emit the
11022          * MI_DISPLAY_FLIP.
11023          */
11024         ret = intel_ring_cacheline_align(req);
11025         if (ret)
11026                 return ret;
11027
11028         ret = intel_ring_begin(req, len);
11029         if (ret)
11030                 return ret;
11031
11032         /* Unmask the flip-done completion message. Note that the bspec says that
11033          * we should do this for both the BCS and RCS, and that we must not unmask
11034          * more than one flip event at any time (or ensure that one flip message
11035          * can be sent by waiting for flip-done prior to queueing new flips).
11036          * Experimentation says that BCS works despite DERRMR masking all
11037          * flip-done completion events and that unmasking all planes at once
11038          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11039          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11040          */
11041         if (ring->id == RCS) {
11042                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11043                 intel_ring_emit(ring, DERRMR);
11044                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11045                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11046                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11047                 if (IS_GEN8(dev))
11048                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11049                                               MI_SRM_LRM_GLOBAL_GTT);
11050                 else
11051                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11052                                               MI_SRM_LRM_GLOBAL_GTT);
11053                 intel_ring_emit(ring, DERRMR);
11054                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11055                 if (IS_GEN8(dev)) {
11056                         intel_ring_emit(ring, 0);
11057                         intel_ring_emit(ring, MI_NOOP);
11058                 }
11059         }
11060
11061         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11062         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11063         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11064         intel_ring_emit(ring, (MI_NOOP));
11065
11066         intel_mark_page_flip_active(intel_crtc);
11067         return 0;
11068 }
11069
11070 static bool use_mmio_flip(struct intel_engine_cs *ring,
11071                           struct drm_i915_gem_object *obj)
11072 {
11073         /*
11074          * This is not being used for older platforms, because
11075          * non-availability of flip done interrupt forces us to use
11076          * CS flips. Older platforms derive flip done using some clever
11077          * tricks involving the flip_pending status bits and vblank irqs.
11078          * So using MMIO flips there would disrupt this mechanism.
11079          */
11080
11081         if (ring == NULL)
11082                 return true;
11083
11084         if (INTEL_INFO(ring->dev)->gen < 5)
11085                 return false;
11086
11087         if (i915.use_mmio_flip < 0)
11088                 return false;
11089         else if (i915.use_mmio_flip > 0)
11090                 return true;
11091         else if (i915.enable_execlists)
11092                 return true;
11093         else
11094                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11095 }
11096
11097 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11098 {
11099         struct drm_device *dev = intel_crtc->base.dev;
11100         struct drm_i915_private *dev_priv = dev->dev_private;
11101         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11102         const enum pipe pipe = intel_crtc->pipe;
11103         u32 ctl, stride;
11104
11105         ctl = I915_READ(PLANE_CTL(pipe, 0));
11106         ctl &= ~PLANE_CTL_TILED_MASK;
11107         switch (fb->modifier[0]) {
11108         case DRM_FORMAT_MOD_NONE:
11109                 break;
11110         case I915_FORMAT_MOD_X_TILED:
11111                 ctl |= PLANE_CTL_TILED_X;
11112                 break;
11113         case I915_FORMAT_MOD_Y_TILED:
11114                 ctl |= PLANE_CTL_TILED_Y;
11115                 break;
11116         case I915_FORMAT_MOD_Yf_TILED:
11117                 ctl |= PLANE_CTL_TILED_YF;
11118                 break;
11119         default:
11120                 MISSING_CASE(fb->modifier[0]);
11121         }
11122
11123         /*
11124          * The stride is either expressed as a multiple of 64 bytes chunks for
11125          * linear buffers or in number of tiles for tiled buffers.
11126          */
11127         stride = fb->pitches[0] /
11128                  intel_fb_stride_alignment(dev, fb->modifier[0],
11129                                            fb->pixel_format);
11130
11131         /*
11132          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11133          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11134          */
11135         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11136         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11137
11138         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11139         POSTING_READ(PLANE_SURF(pipe, 0));
11140 }
11141
11142 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11143 {
11144         struct drm_device *dev = intel_crtc->base.dev;
11145         struct drm_i915_private *dev_priv = dev->dev_private;
11146         struct intel_framebuffer *intel_fb =
11147                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11148         struct drm_i915_gem_object *obj = intel_fb->obj;
11149         u32 dspcntr;
11150         u32 reg;
11151
11152         reg = DSPCNTR(intel_crtc->plane);
11153         dspcntr = I915_READ(reg);
11154
11155         if (obj->tiling_mode != I915_TILING_NONE)
11156                 dspcntr |= DISPPLANE_TILED;
11157         else
11158                 dspcntr &= ~DISPPLANE_TILED;
11159
11160         I915_WRITE(reg, dspcntr);
11161
11162         I915_WRITE(DSPSURF(intel_crtc->plane),
11163                    intel_crtc->unpin_work->gtt_offset);
11164         POSTING_READ(DSPSURF(intel_crtc->plane));
11165
11166 }
11167
11168 /*
11169  * XXX: This is the temporary way to update the plane registers until we get
11170  * around to using the usual plane update functions for MMIO flips
11171  */
11172 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11173 {
11174         struct drm_device *dev = intel_crtc->base.dev;
11175         bool atomic_update;
11176         u32 start_vbl_count;
11177
11178         intel_mark_page_flip_active(intel_crtc);
11179
11180         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11181
11182         if (INTEL_INFO(dev)->gen >= 9)
11183                 skl_do_mmio_flip(intel_crtc);
11184         else
11185                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11186                 ilk_do_mmio_flip(intel_crtc);
11187
11188         if (atomic_update)
11189                 intel_pipe_update_end(intel_crtc, start_vbl_count);
11190 }
11191
11192 static void intel_mmio_flip_work_func(struct work_struct *work)
11193 {
11194         struct intel_mmio_flip *mmio_flip =
11195                 container_of(work, struct intel_mmio_flip, work);
11196
11197         if (mmio_flip->req)
11198                 WARN_ON(__i915_wait_request(mmio_flip->req,
11199                                             mmio_flip->crtc->reset_counter,
11200                                             false, NULL,
11201                                             &mmio_flip->i915->rps.mmioflips));
11202
11203         intel_do_mmio_flip(mmio_flip->crtc);
11204
11205         i915_gem_request_unreference__unlocked(mmio_flip->req);
11206         kfree(mmio_flip);
11207 }
11208
11209 static int intel_queue_mmio_flip(struct drm_device *dev,
11210                                  struct drm_crtc *crtc,
11211                                  struct drm_framebuffer *fb,
11212                                  struct drm_i915_gem_object *obj,
11213                                  struct intel_engine_cs *ring,
11214                                  uint32_t flags)
11215 {
11216         struct intel_mmio_flip *mmio_flip;
11217
11218         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11219         if (mmio_flip == NULL)
11220                 return -ENOMEM;
11221
11222         mmio_flip->i915 = to_i915(dev);
11223         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11224         mmio_flip->crtc = to_intel_crtc(crtc);
11225
11226         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11227         schedule_work(&mmio_flip->work);
11228
11229         return 0;
11230 }
11231
11232 static int intel_default_queue_flip(struct drm_device *dev,
11233                                     struct drm_crtc *crtc,
11234                                     struct drm_framebuffer *fb,
11235                                     struct drm_i915_gem_object *obj,
11236                                     struct drm_i915_gem_request *req,
11237                                     uint32_t flags)
11238 {
11239         return -ENODEV;
11240 }
11241
11242 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11243                                          struct drm_crtc *crtc)
11244 {
11245         struct drm_i915_private *dev_priv = dev->dev_private;
11246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11247         struct intel_unpin_work *work = intel_crtc->unpin_work;
11248         u32 addr;
11249
11250         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11251                 return true;
11252
11253         if (!work->enable_stall_check)
11254                 return false;
11255
11256         if (work->flip_ready_vblank == 0) {
11257                 if (work->flip_queued_req &&
11258                     !i915_gem_request_completed(work->flip_queued_req, true))
11259                         return false;
11260
11261                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11262         }
11263
11264         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11265                 return false;
11266
11267         /* Potential stall - if we see that the flip has happened,
11268          * assume a missed interrupt. */
11269         if (INTEL_INFO(dev)->gen >= 4)
11270                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11271         else
11272                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11273
11274         /* There is a potential issue here with a false positive after a flip
11275          * to the same address. We could address this by checking for a
11276          * non-incrementing frame counter.
11277          */
11278         return addr == work->gtt_offset;
11279 }
11280
11281 void intel_check_page_flip(struct drm_device *dev, int pipe)
11282 {
11283         struct drm_i915_private *dev_priv = dev->dev_private;
11284         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11286         struct intel_unpin_work *work;
11287
11288         WARN_ON(!in_interrupt());
11289
11290         if (crtc == NULL)
11291                 return;
11292
11293         spin_lock(&dev->event_lock);
11294         work = intel_crtc->unpin_work;
11295         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11296                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11297                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11298                 page_flip_completed(intel_crtc);
11299                 work = NULL;
11300         }
11301         if (work != NULL &&
11302             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11303                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11304         spin_unlock(&dev->event_lock);
11305 }
11306
11307 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11308                                 struct drm_framebuffer *fb,
11309                                 struct drm_pending_vblank_event *event,
11310                                 uint32_t page_flip_flags)
11311 {
11312         struct drm_device *dev = crtc->dev;
11313         struct drm_i915_private *dev_priv = dev->dev_private;
11314         struct drm_framebuffer *old_fb = crtc->primary->fb;
11315         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11317         struct drm_plane *primary = crtc->primary;
11318         enum pipe pipe = intel_crtc->pipe;
11319         struct intel_unpin_work *work;
11320         struct intel_engine_cs *ring;
11321         bool mmio_flip;
11322         struct drm_i915_gem_request *request = NULL;
11323         int ret;
11324
11325         /*
11326          * drm_mode_page_flip_ioctl() should already catch this, but double
11327          * check to be safe.  In the future we may enable pageflipping from
11328          * a disabled primary plane.
11329          */
11330         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11331                 return -EBUSY;
11332
11333         /* Can't change pixel format via MI display flips. */
11334         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11335                 return -EINVAL;
11336
11337         /*
11338          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11339          * Note that pitch changes could also affect these register.
11340          */
11341         if (INTEL_INFO(dev)->gen > 3 &&
11342             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11343              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11344                 return -EINVAL;
11345
11346         if (i915_terminally_wedged(&dev_priv->gpu_error))
11347                 goto out_hang;
11348
11349         work = kzalloc(sizeof(*work), GFP_KERNEL);
11350         if (work == NULL)
11351                 return -ENOMEM;
11352
11353         work->event = event;
11354         work->crtc = crtc;
11355         work->old_fb = old_fb;
11356         INIT_WORK(&work->work, intel_unpin_work_fn);
11357
11358         ret = drm_crtc_vblank_get(crtc);
11359         if (ret)
11360                 goto free_work;
11361
11362         /* We borrow the event spin lock for protecting unpin_work */
11363         spin_lock_irq(&dev->event_lock);
11364         if (intel_crtc->unpin_work) {
11365                 /* Before declaring the flip queue wedged, check if
11366                  * the hardware completed the operation behind our backs.
11367                  */
11368                 if (__intel_pageflip_stall_check(dev, crtc)) {
11369                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11370                         page_flip_completed(intel_crtc);
11371                 } else {
11372                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11373                         spin_unlock_irq(&dev->event_lock);
11374
11375                         drm_crtc_vblank_put(crtc);
11376                         kfree(work);
11377                         return -EBUSY;
11378                 }
11379         }
11380         intel_crtc->unpin_work = work;
11381         spin_unlock_irq(&dev->event_lock);
11382
11383         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11384                 flush_workqueue(dev_priv->wq);
11385
11386         /* Reference the objects for the scheduled work. */
11387         drm_framebuffer_reference(work->old_fb);
11388         drm_gem_object_reference(&obj->base);
11389
11390         crtc->primary->fb = fb;
11391         update_state_fb(crtc->primary);
11392
11393         work->pending_flip_obj = obj;
11394
11395         ret = i915_mutex_lock_interruptible(dev);
11396         if (ret)
11397                 goto cleanup;
11398
11399         atomic_inc(&intel_crtc->unpin_work_count);
11400         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11401
11402         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11403                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11404
11405         if (IS_VALLEYVIEW(dev)) {
11406                 ring = &dev_priv->ring[BCS];
11407                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11408                         /* vlv: DISPLAY_FLIP fails to change tiling */
11409                         ring = NULL;
11410         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11411                 ring = &dev_priv->ring[BCS];
11412         } else if (INTEL_INFO(dev)->gen >= 7) {
11413                 ring = i915_gem_request_get_ring(obj->last_write_req);
11414                 if (ring == NULL || ring->id != RCS)
11415                         ring = &dev_priv->ring[BCS];
11416         } else {
11417                 ring = &dev_priv->ring[RCS];
11418         }
11419
11420         mmio_flip = use_mmio_flip(ring, obj);
11421
11422         /* When using CS flips, we want to emit semaphores between rings.
11423          * However, when using mmio flips we will create a task to do the
11424          * synchronisation, so all we want here is to pin the framebuffer
11425          * into the display plane and skip any waits.
11426          */
11427         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11428                                          crtc->primary->state,
11429                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11430         if (ret)
11431                 goto cleanup_pending;
11432
11433         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11434                                                   + intel_crtc->dspaddr_offset;
11435
11436         if (mmio_flip) {
11437                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11438                                             page_flip_flags);
11439                 if (ret)
11440                         goto cleanup_unpin;
11441
11442                 i915_gem_request_assign(&work->flip_queued_req,
11443                                         obj->last_write_req);
11444         } else {
11445                 if (!request) {
11446                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11447                         if (ret)
11448                                 goto cleanup_unpin;
11449                 }
11450
11451                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11452                                                    page_flip_flags);
11453                 if (ret)
11454                         goto cleanup_unpin;
11455
11456                 i915_gem_request_assign(&work->flip_queued_req, request);
11457         }
11458
11459         if (request)
11460                 i915_add_request_no_flush(request);
11461
11462         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11463         work->enable_stall_check = true;
11464
11465         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11466                           to_intel_plane(primary)->frontbuffer_bit);
11467
11468         intel_fbc_disable(dev);
11469         intel_frontbuffer_flip_prepare(dev,
11470                                        to_intel_plane(primary)->frontbuffer_bit);
11471         mutex_unlock(&dev->struct_mutex);
11472
11473         trace_i915_flip_request(intel_crtc->plane, obj);
11474
11475         return 0;
11476
11477 cleanup_unpin:
11478         intel_unpin_fb_obj(fb, crtc->primary->state);
11479 cleanup_pending:
11480         if (request)
11481                 i915_gem_request_cancel(request);
11482         atomic_dec(&intel_crtc->unpin_work_count);
11483         mutex_unlock(&dev->struct_mutex);
11484 cleanup:
11485         crtc->primary->fb = old_fb;
11486         update_state_fb(crtc->primary);
11487
11488         drm_gem_object_unreference_unlocked(&obj->base);
11489         drm_framebuffer_unreference(work->old_fb);
11490
11491         spin_lock_irq(&dev->event_lock);
11492         intel_crtc->unpin_work = NULL;
11493         spin_unlock_irq(&dev->event_lock);
11494
11495         drm_crtc_vblank_put(crtc);
11496 free_work:
11497         kfree(work);
11498
11499         if (ret == -EIO) {
11500                 struct drm_atomic_state *state;
11501                 struct drm_plane_state *plane_state;
11502
11503 out_hang:
11504                 state = drm_atomic_state_alloc(dev);
11505                 if (!state)
11506                         return -ENOMEM;
11507                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11508
11509 retry:
11510                 plane_state = drm_atomic_get_plane_state(state, primary);
11511                 ret = PTR_ERR_OR_ZERO(plane_state);
11512                 if (!ret) {
11513                         drm_atomic_set_fb_for_plane(plane_state, fb);
11514
11515                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11516                         if (!ret)
11517                                 ret = drm_atomic_commit(state);
11518                 }
11519
11520                 if (ret == -EDEADLK) {
11521                         drm_modeset_backoff(state->acquire_ctx);
11522                         drm_atomic_state_clear(state);
11523                         goto retry;
11524                 }
11525
11526                 if (ret)
11527                         drm_atomic_state_free(state);
11528
11529                 if (ret == 0 && event) {
11530                         spin_lock_irq(&dev->event_lock);
11531                         drm_send_vblank_event(dev, pipe, event);
11532                         spin_unlock_irq(&dev->event_lock);
11533                 }
11534         }
11535         return ret;
11536 }
11537
11538
11539 /**
11540  * intel_wm_need_update - Check whether watermarks need updating
11541  * @plane: drm plane
11542  * @state: new plane state
11543  *
11544  * Check current plane state versus the new one to determine whether
11545  * watermarks need to be recalculated.
11546  *
11547  * Returns true or false.
11548  */
11549 static bool intel_wm_need_update(struct drm_plane *plane,
11550                                  struct drm_plane_state *state)
11551 {
11552         /* Update watermarks on tiling changes. */
11553         if (!plane->state->fb || !state->fb ||
11554             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11555             plane->state->rotation != state->rotation)
11556                 return true;
11557
11558         if (plane->state->crtc_w != state->crtc_w)
11559                 return true;
11560
11561         return false;
11562 }
11563
11564 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11565                                     struct drm_plane_state *plane_state)
11566 {
11567         struct drm_crtc *crtc = crtc_state->crtc;
11568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11569         struct drm_plane *plane = plane_state->plane;
11570         struct drm_device *dev = crtc->dev;
11571         struct drm_i915_private *dev_priv = dev->dev_private;
11572         struct intel_plane_state *old_plane_state =
11573                 to_intel_plane_state(plane->state);
11574         int idx = intel_crtc->base.base.id, ret;
11575         int i = drm_plane_index(plane);
11576         bool mode_changed = needs_modeset(crtc_state);
11577         bool was_crtc_enabled = crtc->state->active;
11578         bool is_crtc_enabled = crtc_state->active;
11579
11580         bool turn_off, turn_on, visible, was_visible;
11581         struct drm_framebuffer *fb = plane_state->fb;
11582
11583         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11584             plane->type != DRM_PLANE_TYPE_CURSOR) {
11585                 ret = skl_update_scaler_plane(
11586                         to_intel_crtc_state(crtc_state),
11587                         to_intel_plane_state(plane_state));
11588                 if (ret)
11589                         return ret;
11590         }
11591
11592         /*
11593          * Disabling a plane is always okay; we just need to update
11594          * fb tracking in a special way since cleanup_fb() won't
11595          * get called by the plane helpers.
11596          */
11597         if (old_plane_state->base.fb && !fb)
11598                 intel_crtc->atomic.disabled_planes |= 1 << i;
11599
11600         was_visible = old_plane_state->visible;
11601         visible = to_intel_plane_state(plane_state)->visible;
11602
11603         if (!was_crtc_enabled && WARN_ON(was_visible))
11604                 was_visible = false;
11605
11606         if (!is_crtc_enabled && WARN_ON(visible))
11607                 visible = false;
11608
11609         if (!was_visible && !visible)
11610                 return 0;
11611
11612         turn_off = was_visible && (!visible || mode_changed);
11613         turn_on = visible && (!was_visible || mode_changed);
11614
11615         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11616                          plane->base.id, fb ? fb->base.id : -1);
11617
11618         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11619                          plane->base.id, was_visible, visible,
11620                          turn_off, turn_on, mode_changed);
11621
11622         if (turn_on) {
11623                 intel_crtc->atomic.update_wm_pre = true;
11624                 /* must disable cxsr around plane enable/disable */
11625                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11626                         intel_crtc->atomic.disable_cxsr = true;
11627                         /* to potentially re-enable cxsr */
11628                         intel_crtc->atomic.wait_vblank = true;
11629                         intel_crtc->atomic.update_wm_post = true;
11630                 }
11631         } else if (turn_off) {
11632                 intel_crtc->atomic.update_wm_post = true;
11633                 /* must disable cxsr around plane enable/disable */
11634                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11635                         if (is_crtc_enabled)
11636                                 intel_crtc->atomic.wait_vblank = true;
11637                         intel_crtc->atomic.disable_cxsr = true;
11638                 }
11639         } else if (intel_wm_need_update(plane, plane_state)) {
11640                 intel_crtc->atomic.update_wm_pre = true;
11641         }
11642
11643         if (visible)
11644                 intel_crtc->atomic.fb_bits |=
11645                         to_intel_plane(plane)->frontbuffer_bit;
11646
11647         switch (plane->type) {
11648         case DRM_PLANE_TYPE_PRIMARY:
11649                 intel_crtc->atomic.wait_for_flips = true;
11650                 intel_crtc->atomic.pre_disable_primary = turn_off;
11651                 intel_crtc->atomic.post_enable_primary = turn_on;
11652
11653                 if (turn_off) {
11654                         /*
11655                          * FIXME: Actually if we will still have any other
11656                          * plane enabled on the pipe we could let IPS enabled
11657                          * still, but for now lets consider that when we make
11658                          * primary invisible by setting DSPCNTR to 0 on
11659                          * update_primary_plane function IPS needs to be
11660                          * disable.
11661                          */
11662                         intel_crtc->atomic.disable_ips = true;
11663
11664                         intel_crtc->atomic.disable_fbc = true;
11665                 }
11666
11667                 /*
11668                  * FBC does not work on some platforms for rotated
11669                  * planes, so disable it when rotation is not 0 and
11670                  * update it when rotation is set back to 0.
11671                  *
11672                  * FIXME: This is redundant with the fbc update done in
11673                  * the primary plane enable function except that that
11674                  * one is done too late. We eventually need to unify
11675                  * this.
11676                  */
11677
11678                 if (visible &&
11679                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11680                     dev_priv->fbc.crtc == intel_crtc &&
11681                     plane_state->rotation != BIT(DRM_ROTATE_0))
11682                         intel_crtc->atomic.disable_fbc = true;
11683
11684                 /*
11685                  * BDW signals flip done immediately if the plane
11686                  * is disabled, even if the plane enable is already
11687                  * armed to occur at the next vblank :(
11688                  */
11689                 if (turn_on && IS_BROADWELL(dev))
11690                         intel_crtc->atomic.wait_vblank = true;
11691
11692                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11693                 break;
11694         case DRM_PLANE_TYPE_CURSOR:
11695                 break;
11696         case DRM_PLANE_TYPE_OVERLAY:
11697                 if (turn_off && !mode_changed) {
11698                         intel_crtc->atomic.wait_vblank = true;
11699                         intel_crtc->atomic.update_sprite_watermarks |=
11700                                 1 << i;
11701                 }
11702         }
11703         return 0;
11704 }
11705
11706 static bool encoders_cloneable(const struct intel_encoder *a,
11707                                const struct intel_encoder *b)
11708 {
11709         /* masks could be asymmetric, so check both ways */
11710         return a == b || (a->cloneable & (1 << b->type) &&
11711                           b->cloneable & (1 << a->type));
11712 }
11713
11714 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11715                                          struct intel_crtc *crtc,
11716                                          struct intel_encoder *encoder)
11717 {
11718         struct intel_encoder *source_encoder;
11719         struct drm_connector *connector;
11720         struct drm_connector_state *connector_state;
11721         int i;
11722
11723         for_each_connector_in_state(state, connector, connector_state, i) {
11724                 if (connector_state->crtc != &crtc->base)
11725                         continue;
11726
11727                 source_encoder =
11728                         to_intel_encoder(connector_state->best_encoder);
11729                 if (!encoders_cloneable(encoder, source_encoder))
11730                         return false;
11731         }
11732
11733         return true;
11734 }
11735
11736 static bool check_encoder_cloning(struct drm_atomic_state *state,
11737                                   struct intel_crtc *crtc)
11738 {
11739         struct intel_encoder *encoder;
11740         struct drm_connector *connector;
11741         struct drm_connector_state *connector_state;
11742         int i;
11743
11744         for_each_connector_in_state(state, connector, connector_state, i) {
11745                 if (connector_state->crtc != &crtc->base)
11746                         continue;
11747
11748                 encoder = to_intel_encoder(connector_state->best_encoder);
11749                 if (!check_single_encoder_cloning(state, crtc, encoder))
11750                         return false;
11751         }
11752
11753         return true;
11754 }
11755
11756 static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11757                                             struct drm_crtc_state *crtc_state)
11758 {
11759         struct intel_crtc_state *pipe_config =
11760                 to_intel_crtc_state(crtc_state);
11761         struct drm_plane *p;
11762         unsigned visible_mask = 0;
11763
11764         drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11765                 struct drm_plane_state *plane_state =
11766                         drm_atomic_get_existing_plane_state(crtc_state->state, p);
11767
11768                 if (WARN_ON(!plane_state))
11769                         continue;
11770
11771                 if (!plane_state->fb)
11772                         crtc_state->plane_mask &=
11773                                 ~(1 << drm_plane_index(p));
11774                 else if (to_intel_plane_state(plane_state)->visible)
11775                         visible_mask |= 1 << drm_plane_index(p);
11776         }
11777
11778         if (!visible_mask)
11779                 return;
11780
11781         pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11782 }
11783
11784 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11785                                    struct drm_crtc_state *crtc_state)
11786 {
11787         struct drm_device *dev = crtc->dev;
11788         struct drm_i915_private *dev_priv = dev->dev_private;
11789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11790         struct intel_crtc_state *pipe_config =
11791                 to_intel_crtc_state(crtc_state);
11792         struct drm_atomic_state *state = crtc_state->state;
11793         int ret, idx = crtc->base.id;
11794         bool mode_changed = needs_modeset(crtc_state);
11795
11796         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11797                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11798                 return -EINVAL;
11799         }
11800
11801         I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11802                 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11803                 idx, crtc->state->active, intel_crtc->active);
11804
11805         /* plane mask is fixed up after all initial planes are calculated */
11806         if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11807                 intel_crtc_check_initial_planes(crtc, crtc_state);
11808
11809         if (mode_changed && !crtc_state->active)
11810                 intel_crtc->atomic.update_wm_post = true;
11811
11812         if (mode_changed && crtc_state->enable &&
11813             dev_priv->display.crtc_compute_clock &&
11814             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11815                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11816                                                            pipe_config);
11817                 if (ret)
11818                         return ret;
11819         }
11820
11821         return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
11822 }
11823
11824 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11825         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11826         .load_lut = intel_crtc_load_lut,
11827         .atomic_begin = intel_begin_crtc_commit,
11828         .atomic_flush = intel_finish_crtc_commit,
11829         .atomic_check = intel_crtc_atomic_check,
11830 };
11831
11832 /**
11833  * intel_modeset_update_staged_output_state
11834  *
11835  * Updates the staged output configuration state, e.g. after we've read out the
11836  * current hw state.
11837  */
11838 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11839 {
11840         struct intel_crtc *crtc;
11841         struct intel_encoder *encoder;
11842         struct intel_connector *connector;
11843
11844         for_each_intel_connector(dev, connector) {
11845                 connector->new_encoder =
11846                         to_intel_encoder(connector->base.encoder);
11847         }
11848
11849         for_each_intel_encoder(dev, encoder) {
11850                 encoder->new_crtc =
11851                         to_intel_crtc(encoder->base.crtc);
11852         }
11853
11854         for_each_intel_crtc(dev, crtc) {
11855                 crtc->new_enabled = crtc->base.state->enable;
11856         }
11857 }
11858
11859 /* Transitional helper to copy current connector/encoder state to
11860  * connector->state. This is needed so that code that is partially
11861  * converted to atomic does the right thing.
11862  */
11863 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11864 {
11865         struct intel_connector *connector;
11866
11867         for_each_intel_connector(dev, connector) {
11868                 if (connector->base.encoder) {
11869                         connector->base.state->best_encoder =
11870                                 connector->base.encoder;
11871                         connector->base.state->crtc =
11872                                 connector->base.encoder->crtc;
11873                 } else {
11874                         connector->base.state->best_encoder = NULL;
11875                         connector->base.state->crtc = NULL;
11876                 }
11877         }
11878 }
11879
11880 static void
11881 connected_sink_compute_bpp(struct intel_connector *connector,
11882                            struct intel_crtc_state *pipe_config)
11883 {
11884         int bpp = pipe_config->pipe_bpp;
11885
11886         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11887                 connector->base.base.id,
11888                 connector->base.name);
11889
11890         /* Don't use an invalid EDID bpc value */
11891         if (connector->base.display_info.bpc &&
11892             connector->base.display_info.bpc * 3 < bpp) {
11893                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11894                               bpp, connector->base.display_info.bpc*3);
11895                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11896         }
11897
11898         /* Clamp bpp to 8 on screens without EDID 1.4 */
11899         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11900                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11901                               bpp);
11902                 pipe_config->pipe_bpp = 24;
11903         }
11904 }
11905
11906 static int
11907 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11908                           struct intel_crtc_state *pipe_config)
11909 {
11910         struct drm_device *dev = crtc->base.dev;
11911         struct drm_atomic_state *state;
11912         struct drm_connector *connector;
11913         struct drm_connector_state *connector_state;
11914         int bpp, i;
11915
11916         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11917                 bpp = 10*3;
11918         else if (INTEL_INFO(dev)->gen >= 5)
11919                 bpp = 12*3;
11920         else
11921                 bpp = 8*3;
11922
11923
11924         pipe_config->pipe_bpp = bpp;
11925
11926         state = pipe_config->base.state;
11927
11928         /* Clamp display bpp to EDID value */
11929         for_each_connector_in_state(state, connector, connector_state, i) {
11930                 if (connector_state->crtc != &crtc->base)
11931                         continue;
11932
11933                 connected_sink_compute_bpp(to_intel_connector(connector),
11934                                            pipe_config);
11935         }
11936
11937         return bpp;
11938 }
11939
11940 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11941 {
11942         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11943                         "type: 0x%x flags: 0x%x\n",
11944                 mode->crtc_clock,
11945                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11946                 mode->crtc_hsync_end, mode->crtc_htotal,
11947                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11948                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11949 }
11950
11951 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11952                                    struct intel_crtc_state *pipe_config,
11953                                    const char *context)
11954 {
11955         struct drm_device *dev = crtc->base.dev;
11956         struct drm_plane *plane;
11957         struct intel_plane *intel_plane;
11958         struct intel_plane_state *state;
11959         struct drm_framebuffer *fb;
11960
11961         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11962                       context, pipe_config, pipe_name(crtc->pipe));
11963
11964         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11965         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11966                       pipe_config->pipe_bpp, pipe_config->dither);
11967         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11968                       pipe_config->has_pch_encoder,
11969                       pipe_config->fdi_lanes,
11970                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11971                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11972                       pipe_config->fdi_m_n.tu);
11973         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11974                       pipe_config->has_dp_encoder,
11975                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11976                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11977                       pipe_config->dp_m_n.tu);
11978
11979         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11980                       pipe_config->has_dp_encoder,
11981                       pipe_config->dp_m2_n2.gmch_m,
11982                       pipe_config->dp_m2_n2.gmch_n,
11983                       pipe_config->dp_m2_n2.link_m,
11984                       pipe_config->dp_m2_n2.link_n,
11985                       pipe_config->dp_m2_n2.tu);
11986
11987         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11988                       pipe_config->has_audio,
11989                       pipe_config->has_infoframe);
11990
11991         DRM_DEBUG_KMS("requested mode:\n");
11992         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11993         DRM_DEBUG_KMS("adjusted mode:\n");
11994         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11995         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11996         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11997         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11998                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11999         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12000                       crtc->num_scalers,
12001                       pipe_config->scaler_state.scaler_users,
12002                       pipe_config->scaler_state.scaler_id);
12003         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12004                       pipe_config->gmch_pfit.control,
12005                       pipe_config->gmch_pfit.pgm_ratios,
12006                       pipe_config->gmch_pfit.lvds_border_bits);
12007         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12008                       pipe_config->pch_pfit.pos,
12009                       pipe_config->pch_pfit.size,
12010                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12011         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12012         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12013
12014         if (IS_BROXTON(dev)) {
12015                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12016                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12017                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pcsdw12: 0x%x\n",
12018                               pipe_config->ddi_pll_sel,
12019                               pipe_config->dpll_hw_state.ebb0,
12020                               pipe_config->dpll_hw_state.ebb4,
12021                               pipe_config->dpll_hw_state.pll0,
12022                               pipe_config->dpll_hw_state.pll1,
12023                               pipe_config->dpll_hw_state.pll2,
12024                               pipe_config->dpll_hw_state.pll3,
12025                               pipe_config->dpll_hw_state.pll6,
12026                               pipe_config->dpll_hw_state.pll8,
12027                               pipe_config->dpll_hw_state.pll9,
12028                               pipe_config->dpll_hw_state.pcsdw12);
12029         } else if (IS_SKYLAKE(dev)) {
12030                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12031                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12032                               pipe_config->ddi_pll_sel,
12033                               pipe_config->dpll_hw_state.ctrl1,
12034                               pipe_config->dpll_hw_state.cfgcr1,
12035                               pipe_config->dpll_hw_state.cfgcr2);
12036         } else if (HAS_DDI(dev)) {
12037                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12038                               pipe_config->ddi_pll_sel,
12039                               pipe_config->dpll_hw_state.wrpll);
12040         } else {
12041                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12042                               "fp0: 0x%x, fp1: 0x%x\n",
12043                               pipe_config->dpll_hw_state.dpll,
12044                               pipe_config->dpll_hw_state.dpll_md,
12045                               pipe_config->dpll_hw_state.fp0,
12046                               pipe_config->dpll_hw_state.fp1);
12047         }
12048
12049         DRM_DEBUG_KMS("planes on this crtc\n");
12050         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12051                 intel_plane = to_intel_plane(plane);
12052                 if (intel_plane->pipe != crtc->pipe)
12053                         continue;
12054
12055                 state = to_intel_plane_state(plane->state);
12056                 fb = state->base.fb;
12057                 if (!fb) {
12058                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12059                                 "disabled, scaler_id = %d\n",
12060                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12061                                 plane->base.id, intel_plane->pipe,
12062                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12063                                 drm_plane_index(plane), state->scaler_id);
12064                         continue;
12065                 }
12066
12067                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12068                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12069                         plane->base.id, intel_plane->pipe,
12070                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12071                         drm_plane_index(plane));
12072                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12073                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12074                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12075                         state->scaler_id,
12076                         state->src.x1 >> 16, state->src.y1 >> 16,
12077                         drm_rect_width(&state->src) >> 16,
12078                         drm_rect_height(&state->src) >> 16,
12079                         state->dst.x1, state->dst.y1,
12080                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12081         }
12082 }
12083
12084 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12085 {
12086         struct drm_device *dev = state->dev;
12087         struct intel_encoder *encoder;
12088         struct drm_connector *connector;
12089         struct drm_connector_state *connector_state;
12090         unsigned int used_ports = 0;
12091         int i;
12092
12093         /*
12094          * Walk the connector list instead of the encoder
12095          * list to detect the problem on ddi platforms
12096          * where there's just one encoder per digital port.
12097          */
12098         for_each_connector_in_state(state, connector, connector_state, i) {
12099                 if (!connector_state->best_encoder)
12100                         continue;
12101
12102                 encoder = to_intel_encoder(connector_state->best_encoder);
12103
12104                 WARN_ON(!connector_state->crtc);
12105
12106                 switch (encoder->type) {
12107                         unsigned int port_mask;
12108                 case INTEL_OUTPUT_UNKNOWN:
12109                         if (WARN_ON(!HAS_DDI(dev)))
12110                                 break;
12111                 case INTEL_OUTPUT_DISPLAYPORT:
12112                 case INTEL_OUTPUT_HDMI:
12113                 case INTEL_OUTPUT_EDP:
12114                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12115
12116                         /* the same port mustn't appear more than once */
12117                         if (used_ports & port_mask)
12118                                 return false;
12119
12120                         used_ports |= port_mask;
12121                 default:
12122                         break;
12123                 }
12124         }
12125
12126         return true;
12127 }
12128
12129 static void
12130 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12131 {
12132         struct drm_crtc_state tmp_state;
12133         struct intel_crtc_scaler_state scaler_state;
12134         struct intel_dpll_hw_state dpll_hw_state;
12135         enum intel_dpll_id shared_dpll;
12136         uint32_t ddi_pll_sel;
12137
12138         /* FIXME: before the switch to atomic started, a new pipe_config was
12139          * kzalloc'd. Code that depends on any field being zero should be
12140          * fixed, so that the crtc_state can be safely duplicated. For now,
12141          * only fields that are know to not cause problems are preserved. */
12142
12143         tmp_state = crtc_state->base;
12144         scaler_state = crtc_state->scaler_state;
12145         shared_dpll = crtc_state->shared_dpll;
12146         dpll_hw_state = crtc_state->dpll_hw_state;
12147         ddi_pll_sel = crtc_state->ddi_pll_sel;
12148
12149         memset(crtc_state, 0, sizeof *crtc_state);
12150
12151         crtc_state->base = tmp_state;
12152         crtc_state->scaler_state = scaler_state;
12153         crtc_state->shared_dpll = shared_dpll;
12154         crtc_state->dpll_hw_state = dpll_hw_state;
12155         crtc_state->ddi_pll_sel = ddi_pll_sel;
12156 }
12157
12158 static int
12159 intel_modeset_pipe_config(struct drm_crtc *crtc,
12160                           struct intel_crtc_state *pipe_config)
12161 {
12162         struct drm_atomic_state *state = pipe_config->base.state;
12163         struct intel_encoder *encoder;
12164         struct drm_connector *connector;
12165         struct drm_connector_state *connector_state;
12166         int base_bpp, ret = -EINVAL;
12167         int i;
12168         bool retry = true;
12169
12170         clear_intel_crtc_state(pipe_config);
12171
12172         pipe_config->cpu_transcoder =
12173                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12174
12175         /*
12176          * Sanitize sync polarity flags based on requested ones. If neither
12177          * positive or negative polarity is requested, treat this as meaning
12178          * negative polarity.
12179          */
12180         if (!(pipe_config->base.adjusted_mode.flags &
12181               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12182                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12183
12184         if (!(pipe_config->base.adjusted_mode.flags &
12185               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12186                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12187
12188         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12189          * plane pixel format and any sink constraints into account. Returns the
12190          * source plane bpp so that dithering can be selected on mismatches
12191          * after encoders and crtc also have had their say. */
12192         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12193                                              pipe_config);
12194         if (base_bpp < 0)
12195                 goto fail;
12196
12197         /*
12198          * Determine the real pipe dimensions. Note that stereo modes can
12199          * increase the actual pipe size due to the frame doubling and
12200          * insertion of additional space for blanks between the frame. This
12201          * is stored in the crtc timings. We use the requested mode to do this
12202          * computation to clearly distinguish it from the adjusted mode, which
12203          * can be changed by the connectors in the below retry loop.
12204          */
12205         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12206                                &pipe_config->pipe_src_w,
12207                                &pipe_config->pipe_src_h);
12208
12209 encoder_retry:
12210         /* Ensure the port clock defaults are reset when retrying. */
12211         pipe_config->port_clock = 0;
12212         pipe_config->pixel_multiplier = 1;
12213
12214         /* Fill in default crtc timings, allow encoders to overwrite them. */
12215         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12216                               CRTC_STEREO_DOUBLE);
12217
12218         /* Pass our mode to the connectors and the CRTC to give them a chance to
12219          * adjust it according to limitations or connector properties, and also
12220          * a chance to reject the mode entirely.
12221          */
12222         for_each_connector_in_state(state, connector, connector_state, i) {
12223                 if (connector_state->crtc != crtc)
12224                         continue;
12225
12226                 encoder = to_intel_encoder(connector_state->best_encoder);
12227
12228                 if (!(encoder->compute_config(encoder, pipe_config))) {
12229                         DRM_DEBUG_KMS("Encoder config failure\n");
12230                         goto fail;
12231                 }
12232         }
12233
12234         /* Set default port clock if not overwritten by the encoder. Needs to be
12235          * done afterwards in case the encoder adjusts the mode. */
12236         if (!pipe_config->port_clock)
12237                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12238                         * pipe_config->pixel_multiplier;
12239
12240         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12241         if (ret < 0) {
12242                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12243                 goto fail;
12244         }
12245
12246         if (ret == RETRY) {
12247                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12248                         ret = -EINVAL;
12249                         goto fail;
12250                 }
12251
12252                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12253                 retry = false;
12254                 goto encoder_retry;
12255         }
12256
12257         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12258         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12259                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12260
12261         /* Check if we need to force a modeset */
12262         if (pipe_config->has_audio !=
12263             to_intel_crtc_state(crtc->state)->has_audio) {
12264                 pipe_config->base.mode_changed = true;
12265                 ret = drm_atomic_add_affected_planes(state, crtc);
12266         }
12267
12268         /*
12269          * Note we have an issue here with infoframes: current code
12270          * only updates them on the full mode set path per hw
12271          * requirements.  So here we should be checking for any
12272          * required changes and forcing a mode set.
12273          */
12274 fail:
12275         return ret;
12276 }
12277
12278 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12279 {
12280         struct drm_encoder *encoder;
12281         struct drm_device *dev = crtc->dev;
12282
12283         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12284                 if (encoder->crtc == crtc)
12285                         return true;
12286
12287         return false;
12288 }
12289
12290 static void
12291 intel_modeset_update_state(struct drm_atomic_state *state)
12292 {
12293         struct drm_device *dev = state->dev;
12294         struct intel_encoder *intel_encoder;
12295         struct drm_crtc *crtc;
12296         struct drm_crtc_state *crtc_state;
12297         struct drm_connector *connector;
12298
12299         intel_shared_dpll_commit(state);
12300
12301         for_each_intel_encoder(dev, intel_encoder) {
12302                 if (!intel_encoder->base.crtc)
12303                         continue;
12304
12305                 crtc = intel_encoder->base.crtc;
12306                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12307                 if (!crtc_state || !needs_modeset(crtc->state))
12308                         continue;
12309
12310                 intel_encoder->connectors_active = false;
12311         }
12312
12313         drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12314         intel_modeset_update_staged_output_state(state->dev);
12315
12316         /* Double check state. */
12317         for_each_crtc(dev, crtc) {
12318                 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12319
12320                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12321
12322                 /* Update hwmode for vblank functions */
12323                 if (crtc->state->active)
12324                         crtc->hwmode = crtc->state->adjusted_mode;
12325                 else
12326                         crtc->hwmode.crtc_clock = 0;
12327         }
12328
12329         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12330                 if (!connector->encoder || !connector->encoder->crtc)
12331                         continue;
12332
12333                 crtc = connector->encoder->crtc;
12334                 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12335                 if (!crtc_state || !needs_modeset(crtc->state))
12336                         continue;
12337
12338                 if (crtc->state->active) {
12339                         struct drm_property *dpms_property =
12340                                 dev->mode_config.dpms_property;
12341
12342                         connector->dpms = DRM_MODE_DPMS_ON;
12343                         drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12344
12345                         intel_encoder = to_intel_encoder(connector->encoder);
12346                         intel_encoder->connectors_active = true;
12347                 } else
12348                         connector->dpms = DRM_MODE_DPMS_OFF;
12349         }
12350 }
12351
12352 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12353 {
12354         int diff;
12355
12356         if (clock1 == clock2)
12357                 return true;
12358
12359         if (!clock1 || !clock2)
12360                 return false;
12361
12362         diff = abs(clock1 - clock2);
12363
12364         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12365                 return true;
12366
12367         return false;
12368 }
12369
12370 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12371         list_for_each_entry((intel_crtc), \
12372                             &(dev)->mode_config.crtc_list, \
12373                             base.head) \
12374                 if (mask & (1 <<(intel_crtc)->pipe))
12375
12376 static bool
12377 intel_pipe_config_compare(struct drm_device *dev,
12378                           struct intel_crtc_state *current_config,
12379                           struct intel_crtc_state *pipe_config)
12380 {
12381 #define PIPE_CONF_CHECK_X(name) \
12382         if (current_config->name != pipe_config->name) { \
12383                 DRM_ERROR("mismatch in " #name " " \
12384                           "(expected 0x%08x, found 0x%08x)\n", \
12385                           current_config->name, \
12386                           pipe_config->name); \
12387                 return false; \
12388         }
12389
12390 #define PIPE_CONF_CHECK_I(name) \
12391         if (current_config->name != pipe_config->name) { \
12392                 DRM_ERROR("mismatch in " #name " " \
12393                           "(expected %i, found %i)\n", \
12394                           current_config->name, \
12395                           pipe_config->name); \
12396                 return false; \
12397         }
12398
12399 /* This is required for BDW+ where there is only one set of registers for
12400  * switching between high and low RR.
12401  * This macro can be used whenever a comparison has to be made between one
12402  * hw state and multiple sw state variables.
12403  */
12404 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12405         if ((current_config->name != pipe_config->name) && \
12406                 (current_config->alt_name != pipe_config->name)) { \
12407                         DRM_ERROR("mismatch in " #name " " \
12408                                   "(expected %i or %i, found %i)\n", \
12409                                   current_config->name, \
12410                                   current_config->alt_name, \
12411                                   pipe_config->name); \
12412                         return false; \
12413         }
12414
12415 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12416         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12417                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
12418                           "(expected %i, found %i)\n", \
12419                           current_config->name & (mask), \
12420                           pipe_config->name & (mask)); \
12421                 return false; \
12422         }
12423
12424 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12425         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12426                 DRM_ERROR("mismatch in " #name " " \
12427                           "(expected %i, found %i)\n", \
12428                           current_config->name, \
12429                           pipe_config->name); \
12430                 return false; \
12431         }
12432
12433 #define PIPE_CONF_QUIRK(quirk)  \
12434         ((current_config->quirks | pipe_config->quirks) & (quirk))
12435
12436         PIPE_CONF_CHECK_I(cpu_transcoder);
12437
12438         PIPE_CONF_CHECK_I(has_pch_encoder);
12439         PIPE_CONF_CHECK_I(fdi_lanes);
12440         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12441         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12442         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12443         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12444         PIPE_CONF_CHECK_I(fdi_m_n.tu);
12445
12446         PIPE_CONF_CHECK_I(has_dp_encoder);
12447
12448         if (INTEL_INFO(dev)->gen < 8) {
12449                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12450                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12451                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12452                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12453                 PIPE_CONF_CHECK_I(dp_m_n.tu);
12454
12455                 if (current_config->has_drrs) {
12456                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12457                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12458                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12459                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12460                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12461                 }
12462         } else {
12463                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12464                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12465                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12466                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12467                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12468         }
12469
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12474         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12475         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12476
12477         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12478         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12479         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12480         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12481         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12482         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12483
12484         PIPE_CONF_CHECK_I(pixel_multiplier);
12485         PIPE_CONF_CHECK_I(has_hdmi_sink);
12486         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12487             IS_VALLEYVIEW(dev))
12488                 PIPE_CONF_CHECK_I(limited_color_range);
12489         PIPE_CONF_CHECK_I(has_infoframe);
12490
12491         PIPE_CONF_CHECK_I(has_audio);
12492
12493         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12494                               DRM_MODE_FLAG_INTERLACE);
12495
12496         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12497                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12498                                       DRM_MODE_FLAG_PHSYNC);
12499                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12500                                       DRM_MODE_FLAG_NHSYNC);
12501                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502                                       DRM_MODE_FLAG_PVSYNC);
12503                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12504                                       DRM_MODE_FLAG_NVSYNC);
12505         }
12506
12507         PIPE_CONF_CHECK_I(pipe_src_w);
12508         PIPE_CONF_CHECK_I(pipe_src_h);
12509
12510         /*
12511          * FIXME: BIOS likes to set up a cloned config with lvds+external
12512          * screen. Since we don't yet re-compute the pipe config when moving
12513          * just the lvds port away to another pipe the sw tracking won't match.
12514          *
12515          * Proper atomic modesets with recomputed global state will fix this.
12516          * Until then just don't check gmch state for inherited modes.
12517          */
12518         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12519                 PIPE_CONF_CHECK_I(gmch_pfit.control);
12520                 /* pfit ratios are autocomputed by the hw on gen4+ */
12521                 if (INTEL_INFO(dev)->gen < 4)
12522                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12523                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12524         }
12525
12526         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12527         if (current_config->pch_pfit.enabled) {
12528                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12529                 PIPE_CONF_CHECK_I(pch_pfit.size);
12530         }
12531
12532         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12533
12534         /* BDW+ don't expose a synchronous way to read the state */
12535         if (IS_HASWELL(dev))
12536                 PIPE_CONF_CHECK_I(ips_enabled);
12537
12538         PIPE_CONF_CHECK_I(double_wide);
12539
12540         PIPE_CONF_CHECK_X(ddi_pll_sel);
12541
12542         PIPE_CONF_CHECK_I(shared_dpll);
12543         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12544         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12545         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12546         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12547         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12548         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12549         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12550         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12551
12552         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12553                 PIPE_CONF_CHECK_I(pipe_bpp);
12554
12555         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12556         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12557
12558 #undef PIPE_CONF_CHECK_X
12559 #undef PIPE_CONF_CHECK_I
12560 #undef PIPE_CONF_CHECK_I_ALT
12561 #undef PIPE_CONF_CHECK_FLAGS
12562 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12563 #undef PIPE_CONF_QUIRK
12564
12565         return true;
12566 }
12567
12568 static void check_wm_state(struct drm_device *dev)
12569 {
12570         struct drm_i915_private *dev_priv = dev->dev_private;
12571         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12572         struct intel_crtc *intel_crtc;
12573         int plane;
12574
12575         if (INTEL_INFO(dev)->gen < 9)
12576                 return;
12577
12578         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12579         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12580
12581         for_each_intel_crtc(dev, intel_crtc) {
12582                 struct skl_ddb_entry *hw_entry, *sw_entry;
12583                 const enum pipe pipe = intel_crtc->pipe;
12584
12585                 if (!intel_crtc->active)
12586                         continue;
12587
12588                 /* planes */
12589                 for_each_plane(dev_priv, pipe, plane) {
12590                         hw_entry = &hw_ddb.plane[pipe][plane];
12591                         sw_entry = &sw_ddb->plane[pipe][plane];
12592
12593                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12594                                 continue;
12595
12596                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12597                                   "(expected (%u,%u), found (%u,%u))\n",
12598                                   pipe_name(pipe), plane + 1,
12599                                   sw_entry->start, sw_entry->end,
12600                                   hw_entry->start, hw_entry->end);
12601                 }
12602
12603                 /* cursor */
12604                 hw_entry = &hw_ddb.cursor[pipe];
12605                 sw_entry = &sw_ddb->cursor[pipe];
12606
12607                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12608                         continue;
12609
12610                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12611                           "(expected (%u,%u), found (%u,%u))\n",
12612                           pipe_name(pipe),
12613                           sw_entry->start, sw_entry->end,
12614                           hw_entry->start, hw_entry->end);
12615         }
12616 }
12617
12618 static void
12619 check_connector_state(struct drm_device *dev)
12620 {
12621         struct intel_connector *connector;
12622
12623         for_each_intel_connector(dev, connector) {
12624                 /* This also checks the encoder/connector hw state with the
12625                  * ->get_hw_state callbacks. */
12626                 intel_connector_check_state(connector);
12627
12628                 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
12629                      "connector's staged encoder doesn't match current encoder\n");
12630         }
12631 }
12632
12633 static void
12634 check_encoder_state(struct drm_device *dev)
12635 {
12636         struct intel_encoder *encoder;
12637         struct intel_connector *connector;
12638
12639         for_each_intel_encoder(dev, encoder) {
12640                 bool enabled = false;
12641                 bool active = false;
12642                 enum pipe pipe, tracked_pipe;
12643
12644                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12645                               encoder->base.base.id,
12646                               encoder->base.name);
12647
12648                 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12649                      "encoder's stage crtc doesn't match current crtc\n");
12650                 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12651                      "encoder's active_connectors set, but no crtc\n");
12652
12653                 for_each_intel_connector(dev, connector) {
12654                         if (connector->base.encoder != &encoder->base)
12655                                 continue;
12656                         enabled = true;
12657                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12658                                 active = true;
12659                 }
12660                 /*
12661                  * for MST connectors if we unplug the connector is gone
12662                  * away but the encoder is still connected to a crtc
12663                  * until a modeset happens in response to the hotplug.
12664                  */
12665                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12666                         continue;
12667
12668                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12669                      "encoder's enabled state mismatch "
12670                      "(expected %i, found %i)\n",
12671                      !!encoder->base.crtc, enabled);
12672                 I915_STATE_WARN(active && !encoder->base.crtc,
12673                      "active encoder with no crtc\n");
12674
12675                 I915_STATE_WARN(encoder->connectors_active != active,
12676                      "encoder's computed active state doesn't match tracked active state "
12677                      "(expected %i, found %i)\n", active, encoder->connectors_active);
12678
12679                 active = encoder->get_hw_state(encoder, &pipe);
12680                 I915_STATE_WARN(active != encoder->connectors_active,
12681                      "encoder's hw state doesn't match sw tracking "
12682                      "(expected %i, found %i)\n",
12683                      encoder->connectors_active, active);
12684
12685                 if (!encoder->base.crtc)
12686                         continue;
12687
12688                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12689                 I915_STATE_WARN(active && pipe != tracked_pipe,
12690                      "active encoder's pipe doesn't match"
12691                      "(expected %i, found %i)\n",
12692                      tracked_pipe, pipe);
12693
12694         }
12695 }
12696
12697 static void
12698 check_crtc_state(struct drm_device *dev)
12699 {
12700         struct drm_i915_private *dev_priv = dev->dev_private;
12701         struct intel_crtc *crtc;
12702         struct intel_encoder *encoder;
12703         struct intel_crtc_state pipe_config;
12704
12705         for_each_intel_crtc(dev, crtc) {
12706                 bool enabled = false;
12707                 bool active = false;
12708
12709                 memset(&pipe_config, 0, sizeof(pipe_config));
12710
12711                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12712                               crtc->base.base.id);
12713
12714                 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12715                      "active crtc, but not enabled in sw tracking\n");
12716
12717                 for_each_intel_encoder(dev, encoder) {
12718                         if (encoder->base.crtc != &crtc->base)
12719                                 continue;
12720                         enabled = true;
12721                         if (encoder->connectors_active)
12722                                 active = true;
12723                 }
12724
12725                 I915_STATE_WARN(active != crtc->active,
12726                      "crtc's computed active state doesn't match tracked active state "
12727                      "(expected %i, found %i)\n", active, crtc->active);
12728                 I915_STATE_WARN(enabled != crtc->base.state->enable,
12729                      "crtc's computed enabled state doesn't match tracked enabled state "
12730                      "(expected %i, found %i)\n", enabled,
12731                                 crtc->base.state->enable);
12732
12733                 active = dev_priv->display.get_pipe_config(crtc,
12734                                                            &pipe_config);
12735
12736                 /* hw state is inconsistent with the pipe quirk */
12737                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12738                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12739                         active = crtc->active;
12740
12741                 for_each_intel_encoder(dev, encoder) {
12742                         enum pipe pipe;
12743                         if (encoder->base.crtc != &crtc->base)
12744                                 continue;
12745                         if (encoder->get_hw_state(encoder, &pipe))
12746                                 encoder->get_config(encoder, &pipe_config);
12747                 }
12748
12749                 I915_STATE_WARN(crtc->active != active,
12750                      "crtc active state doesn't match with hw state "
12751                      "(expected %i, found %i)\n", crtc->active, active);
12752
12753                 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12754                      "transitional active state does not match atomic hw state "
12755                      "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12756
12757                 if (active &&
12758                     !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12759                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12760                         intel_dump_pipe_config(crtc, &pipe_config,
12761                                                "[hw state]");
12762                         intel_dump_pipe_config(crtc, crtc->config,
12763                                                "[sw state]");
12764                 }
12765         }
12766 }
12767
12768 static void
12769 check_shared_dpll_state(struct drm_device *dev)
12770 {
12771         struct drm_i915_private *dev_priv = dev->dev_private;
12772         struct intel_crtc *crtc;
12773         struct intel_dpll_hw_state dpll_hw_state;
12774         int i;
12775
12776         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12777                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12778                 int enabled_crtcs = 0, active_crtcs = 0;
12779                 bool active;
12780
12781                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12782
12783                 DRM_DEBUG_KMS("%s\n", pll->name);
12784
12785                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12786
12787                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12788                      "more active pll users than references: %i vs %i\n",
12789                      pll->active, hweight32(pll->config.crtc_mask));
12790                 I915_STATE_WARN(pll->active && !pll->on,
12791                      "pll in active use but not on in sw tracking\n");
12792                 I915_STATE_WARN(pll->on && !pll->active,
12793                      "pll in on but not on in use in sw tracking\n");
12794                 I915_STATE_WARN(pll->on != active,
12795                      "pll on state mismatch (expected %i, found %i)\n",
12796                      pll->on, active);
12797
12798                 for_each_intel_crtc(dev, crtc) {
12799                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12800                                 enabled_crtcs++;
12801                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12802                                 active_crtcs++;
12803                 }
12804                 I915_STATE_WARN(pll->active != active_crtcs,
12805                      "pll active crtcs mismatch (expected %i, found %i)\n",
12806                      pll->active, active_crtcs);
12807                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12808                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12809                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12810
12811                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12812                                        sizeof(dpll_hw_state)),
12813                      "pll hw state mismatch\n");
12814         }
12815 }
12816
12817 void
12818 intel_modeset_check_state(struct drm_device *dev)
12819 {
12820         check_wm_state(dev);
12821         check_connector_state(dev);
12822         check_encoder_state(dev);
12823         check_crtc_state(dev);
12824         check_shared_dpll_state(dev);
12825 }
12826
12827 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12828                                      int dotclock)
12829 {
12830         /*
12831          * FDI already provided one idea for the dotclock.
12832          * Yell if the encoder disagrees.
12833          */
12834         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12835              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12836              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12837 }
12838
12839 static void update_scanline_offset(struct intel_crtc *crtc)
12840 {
12841         struct drm_device *dev = crtc->base.dev;
12842
12843         /*
12844          * The scanline counter increments at the leading edge of hsync.
12845          *
12846          * On most platforms it starts counting from vtotal-1 on the
12847          * first active line. That means the scanline counter value is
12848          * always one less than what we would expect. Ie. just after
12849          * start of vblank, which also occurs at start of hsync (on the
12850          * last active line), the scanline counter will read vblank_start-1.
12851          *
12852          * On gen2 the scanline counter starts counting from 1 instead
12853          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12854          * to keep the value positive), instead of adding one.
12855          *
12856          * On HSW+ the behaviour of the scanline counter depends on the output
12857          * type. For DP ports it behaves like most other platforms, but on HDMI
12858          * there's an extra 1 line difference. So we need to add two instead of
12859          * one to the value.
12860          */
12861         if (IS_GEN2(dev)) {
12862                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12863                 int vtotal;
12864
12865                 vtotal = mode->crtc_vtotal;
12866                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12867                         vtotal /= 2;
12868
12869                 crtc->scanline_offset = vtotal - 1;
12870         } else if (HAS_DDI(dev) &&
12871                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12872                 crtc->scanline_offset = 2;
12873         } else
12874                 crtc->scanline_offset = 1;
12875 }
12876
12877 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12878 {
12879         struct drm_device *dev = state->dev;
12880         struct drm_i915_private *dev_priv = to_i915(dev);
12881         struct intel_shared_dpll_config *shared_dpll = NULL;
12882         struct intel_crtc *intel_crtc;
12883         struct intel_crtc_state *intel_crtc_state;
12884         struct drm_crtc *crtc;
12885         struct drm_crtc_state *crtc_state;
12886         int i;
12887
12888         if (!dev_priv->display.crtc_compute_clock)
12889                 return;
12890
12891         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12892                 int dpll;
12893
12894                 intel_crtc = to_intel_crtc(crtc);
12895                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12896                 dpll = intel_crtc_state->shared_dpll;
12897
12898                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12899                         continue;
12900
12901                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12902
12903                 if (!shared_dpll)
12904                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12905
12906                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12907         }
12908 }
12909
12910 /*
12911  * This implements the workaround described in the "notes" section of the mode
12912  * set sequence documentation. When going from no pipes or single pipe to
12913  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12914  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12915  */
12916 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12917 {
12918         struct drm_crtc_state *crtc_state;
12919         struct intel_crtc *intel_crtc;
12920         struct drm_crtc *crtc;
12921         struct intel_crtc_state *first_crtc_state = NULL;
12922         struct intel_crtc_state *other_crtc_state = NULL;
12923         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12924         int i;
12925
12926         /* look at all crtc's that are going to be enabled in during modeset */
12927         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12928                 intel_crtc = to_intel_crtc(crtc);
12929
12930                 if (!crtc_state->active || !needs_modeset(crtc_state))
12931                         continue;
12932
12933                 if (first_crtc_state) {
12934                         other_crtc_state = to_intel_crtc_state(crtc_state);
12935                         break;
12936                 } else {
12937                         first_crtc_state = to_intel_crtc_state(crtc_state);
12938                         first_pipe = intel_crtc->pipe;
12939                 }
12940         }
12941
12942         /* No workaround needed? */
12943         if (!first_crtc_state)
12944                 return 0;
12945
12946         /* w/a possibly needed, check how many crtc's are already enabled. */
12947         for_each_intel_crtc(state->dev, intel_crtc) {
12948                 struct intel_crtc_state *pipe_config;
12949
12950                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12951                 if (IS_ERR(pipe_config))
12952                         return PTR_ERR(pipe_config);
12953
12954                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12955
12956                 if (!pipe_config->base.active ||
12957                     needs_modeset(&pipe_config->base))
12958                         continue;
12959
12960                 /* 2 or more enabled crtcs means no need for w/a */
12961                 if (enabled_pipe != INVALID_PIPE)
12962                         return 0;
12963
12964                 enabled_pipe = intel_crtc->pipe;
12965         }
12966
12967         if (enabled_pipe != INVALID_PIPE)
12968                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12969         else if (other_crtc_state)
12970                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12971
12972         return 0;
12973 }
12974
12975 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12976 {
12977         struct drm_crtc *crtc;
12978         struct drm_crtc_state *crtc_state;
12979         int ret = 0;
12980
12981         /* add all active pipes to the state */
12982         for_each_crtc(state->dev, crtc) {
12983                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12984                 if (IS_ERR(crtc_state))
12985                         return PTR_ERR(crtc_state);
12986
12987                 if (!crtc_state->active || needs_modeset(crtc_state))
12988                         continue;
12989
12990                 crtc_state->mode_changed = true;
12991
12992                 ret = drm_atomic_add_affected_connectors(state, crtc);
12993                 if (ret)
12994                         break;
12995
12996                 ret = drm_atomic_add_affected_planes(state, crtc);
12997                 if (ret)
12998                         break;
12999         }
13000
13001         return ret;
13002 }
13003
13004
13005 /* Code that should eventually be part of atomic_check() */
13006 static int intel_modeset_checks(struct drm_atomic_state *state)
13007 {
13008         struct drm_device *dev = state->dev;
13009         struct drm_i915_private *dev_priv = dev->dev_private;
13010         int ret;
13011
13012         if (!check_digital_port_conflicts(state)) {
13013                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13014                 return -EINVAL;
13015         }
13016
13017         /*
13018          * See if the config requires any additional preparation, e.g.
13019          * to adjust global state with pipes off.  We need to do this
13020          * here so we can get the modeset_pipe updated config for the new
13021          * mode set on this crtc.  For other crtcs we need to use the
13022          * adjusted_mode bits in the crtc directly.
13023          */
13024         if (dev_priv->display.modeset_calc_cdclk) {
13025                 unsigned int cdclk;
13026
13027                 ret = dev_priv->display.modeset_calc_cdclk(state);
13028
13029                 cdclk = to_intel_atomic_state(state)->cdclk;
13030                 if (!ret && cdclk != dev_priv->cdclk_freq)
13031                         ret = intel_modeset_all_pipes(state);
13032
13033                 if (ret < 0)
13034                         return ret;
13035         } else
13036                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13037
13038         intel_modeset_clear_plls(state);
13039
13040         if (IS_HASWELL(dev))
13041                 return haswell_mode_set_planes_workaround(state);
13042
13043         return 0;
13044 }
13045
13046 static int
13047 intel_modeset_compute_config(struct drm_atomic_state *state)
13048 {
13049         struct drm_crtc *crtc;
13050         struct drm_crtc_state *crtc_state;
13051         int ret, i;
13052         bool any_ms = false;
13053
13054         ret = drm_atomic_helper_check_modeset(state->dev, state);
13055         if (ret)
13056                 return ret;
13057
13058         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13059                 if (!crtc_state->enable) {
13060                         if (needs_modeset(crtc_state))
13061                                 any_ms = true;
13062                         continue;
13063                 }
13064
13065                 if (to_intel_crtc_state(crtc_state)->quirks &
13066                     PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13067                         ret = drm_atomic_add_affected_planes(state, crtc);
13068                         if (ret)
13069                                 return ret;
13070
13071                         /*
13072                          * We ought to handle i915.fastboot here.
13073                          * If no modeset is required and the primary plane has
13074                          * a fb, update the members of crtc_state as needed,
13075                          * and run the necessary updates during vblank evasion.
13076                          */
13077                 }
13078
13079                 if (!needs_modeset(crtc_state)) {
13080                         ret = drm_atomic_add_affected_connectors(state, crtc);
13081                         if (ret)
13082                                 return ret;
13083                 }
13084
13085                 ret = intel_modeset_pipe_config(crtc,
13086                                         to_intel_crtc_state(crtc_state));
13087                 if (ret)
13088                         return ret;
13089
13090                 if (needs_modeset(crtc_state))
13091                         any_ms = true;
13092
13093                 intel_dump_pipe_config(to_intel_crtc(crtc),
13094                                        to_intel_crtc_state(crtc_state),
13095                                        "[modeset]");
13096         }
13097
13098         if (any_ms) {
13099                 ret = intel_modeset_checks(state);
13100
13101                 if (ret)
13102                         return ret;
13103         } else
13104                 to_intel_atomic_state(state)->cdclk =
13105                         to_i915(state->dev)->cdclk_freq;
13106
13107         return drm_atomic_helper_check_planes(state->dev, state);
13108 }
13109
13110 static int __intel_set_mode(struct drm_atomic_state *state)
13111 {
13112         struct drm_device *dev = state->dev;
13113         struct drm_i915_private *dev_priv = dev->dev_private;
13114         struct drm_crtc *crtc;
13115         struct drm_crtc_state *crtc_state;
13116         int ret = 0;
13117         int i;
13118         bool any_ms = false;
13119
13120         ret = drm_atomic_helper_prepare_planes(dev, state);
13121         if (ret)
13122                 return ret;
13123
13124         drm_atomic_helper_swap_state(dev, state);
13125
13126         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13127                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13128
13129                 if (!needs_modeset(crtc->state))
13130                         continue;
13131
13132                 intel_pre_plane_update(intel_crtc);
13133
13134                 any_ms = true;
13135                 intel_pre_plane_update(intel_crtc);
13136
13137                 if (crtc_state->active) {
13138                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13139                         dev_priv->display.crtc_disable(crtc);
13140                         intel_crtc->active = false;
13141                         intel_disable_shared_dpll(intel_crtc);
13142                 }
13143         }
13144
13145         /* Only after disabling all output pipelines that will be changed can we
13146          * update the the output configuration. */
13147         intel_modeset_update_state(state);
13148
13149         /* The state has been swaped above, so state actually contains the
13150          * old state now. */
13151         if (any_ms)
13152                 modeset_update_crtc_power_domains(state);
13153
13154         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13155         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13156                 if (needs_modeset(crtc->state) && crtc->state->active) {
13157                         update_scanline_offset(to_intel_crtc(crtc));
13158                         dev_priv->display.crtc_enable(crtc);
13159                 }
13160
13161                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13162         }
13163
13164         /* FIXME: add subpixel order */
13165
13166         drm_atomic_helper_cleanup_planes(dev, state);
13167
13168         drm_atomic_state_free(state);
13169
13170         return 0;
13171 }
13172
13173 static int intel_set_mode_checked(struct drm_atomic_state *state)
13174 {
13175         struct drm_device *dev = state->dev;
13176         int ret;
13177
13178         ret = __intel_set_mode(state);
13179         if (ret == 0)
13180                 intel_modeset_check_state(dev);
13181
13182         return ret;
13183 }
13184
13185 static int intel_set_mode(struct drm_atomic_state *state)
13186 {
13187         int ret;
13188
13189         ret = intel_modeset_compute_config(state);
13190         if (ret)
13191                 return ret;
13192
13193         return intel_set_mode_checked(state);
13194 }
13195
13196 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13197 {
13198         struct drm_device *dev = crtc->dev;
13199         struct drm_atomic_state *state;
13200         struct intel_encoder *encoder;
13201         struct intel_connector *connector;
13202         struct drm_connector_state *connector_state;
13203         struct intel_crtc_state *crtc_state;
13204         int ret;
13205
13206         state = drm_atomic_state_alloc(dev);
13207         if (!state) {
13208                 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13209                               crtc->base.id);
13210                 return;
13211         }
13212
13213         state->acquire_ctx = dev->mode_config.acquire_ctx;
13214
13215         /* The force restore path in the HW readout code relies on the staged
13216          * config still keeping the user requested config while the actual
13217          * state has been overwritten by the configuration read from HW. We
13218          * need to copy the staged config to the atomic state, otherwise the
13219          * mode set will just reapply the state the HW is already in. */
13220         for_each_intel_encoder(dev, encoder) {
13221                 if (&encoder->new_crtc->base != crtc)
13222                         continue;
13223
13224                 for_each_intel_connector(dev, connector) {
13225                         if (connector->new_encoder != encoder)
13226                                 continue;
13227
13228                         connector_state = drm_atomic_get_connector_state(state, &connector->base);
13229                         if (IS_ERR(connector_state)) {
13230                                 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13231                                               connector->base.base.id,
13232                                               connector->base.name,
13233                                               PTR_ERR(connector_state));
13234                                 continue;
13235                         }
13236
13237                         connector_state->crtc = crtc;
13238                         connector_state->best_encoder = &encoder->base;
13239                 }
13240         }
13241
13242         crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13243         if (IS_ERR(crtc_state)) {
13244                 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13245                               crtc->base.id, PTR_ERR(crtc_state));
13246                 drm_atomic_state_free(state);
13247                 return;
13248         }
13249
13250         crtc_state->base.active = crtc_state->base.enable =
13251                 to_intel_crtc(crtc)->new_enabled;
13252
13253         drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
13254
13255         intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13256                                         crtc->primary->fb, crtc->x, crtc->y);
13257
13258         ret = intel_set_mode(state);
13259         if (ret)
13260                 drm_atomic_state_free(state);
13261 }
13262
13263 #undef for_each_intel_crtc_masked
13264
13265 static bool intel_connector_in_mode_set(struct intel_connector *connector,
13266                                         struct drm_mode_set *set)
13267 {
13268         int ro;
13269
13270         for (ro = 0; ro < set->num_connectors; ro++)
13271                 if (set->connectors[ro] == &connector->base)
13272                         return true;
13273
13274         return false;
13275 }
13276
13277 static int
13278 intel_modeset_stage_output_state(struct drm_device *dev,
13279                                  struct drm_mode_set *set,
13280                                  struct drm_atomic_state *state)
13281 {
13282         struct intel_connector *connector;
13283         struct drm_connector *drm_connector;
13284         struct drm_connector_state *connector_state;
13285         struct drm_crtc *crtc;
13286         struct drm_crtc_state *crtc_state;
13287         int i, ret;
13288
13289         /* The upper layers ensure that we either disable a crtc or have a list
13290          * of connectors. For paranoia, double-check this. */
13291         WARN_ON(!set->fb && (set->num_connectors != 0));
13292         WARN_ON(set->fb && (set->num_connectors == 0));
13293
13294         for_each_intel_connector(dev, connector) {
13295                 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13296
13297                 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13298                         continue;
13299
13300                 connector_state =
13301                         drm_atomic_get_connector_state(state, &connector->base);
13302                 if (IS_ERR(connector_state))
13303                         return PTR_ERR(connector_state);
13304
13305                 if (in_mode_set) {
13306                         int pipe = to_intel_crtc(set->crtc)->pipe;
13307                         connector_state->best_encoder =
13308                                 &intel_find_encoder(connector, pipe)->base;
13309                 }
13310
13311                 if (connector->base.state->crtc != set->crtc)
13312                         continue;
13313
13314                 /* If we disable the crtc, disable all its connectors. Also, if
13315                  * the connector is on the changing crtc but not on the new
13316                  * connector list, disable it. */
13317                 if (!set->fb || !in_mode_set) {
13318                         connector_state->best_encoder = NULL;
13319
13320                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13321                                 connector->base.base.id,
13322                                 connector->base.name);
13323                 }
13324         }
13325         /* connector->new_encoder is now updated for all connectors. */
13326
13327         for_each_connector_in_state(state, drm_connector, connector_state, i) {
13328                 connector = to_intel_connector(drm_connector);
13329
13330                 if (!connector_state->best_encoder) {
13331                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13332                                                                 NULL);
13333                         if (ret)
13334                                 return ret;
13335
13336                         continue;
13337                 }
13338
13339                 if (intel_connector_in_mode_set(connector, set)) {
13340                         struct drm_crtc *crtc = connector->base.state->crtc;
13341
13342                         /* If this connector was in a previous crtc, add it
13343                          * to the state. We might need to disable it. */
13344                         if (crtc) {
13345                                 crtc_state =
13346                                         drm_atomic_get_crtc_state(state, crtc);
13347                                 if (IS_ERR(crtc_state))
13348                                         return PTR_ERR(crtc_state);
13349                         }
13350
13351                         ret = drm_atomic_set_crtc_for_connector(connector_state,
13352                                                                 set->crtc);
13353                         if (ret)
13354                                 return ret;
13355                 }
13356
13357                 /* Make sure the new CRTC will work with the encoder */
13358                 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13359                                          connector_state->crtc)) {
13360                         return -EINVAL;
13361                 }
13362
13363                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13364                         connector->base.base.id,
13365                         connector->base.name,
13366                         connector_state->crtc->base.id);
13367
13368                 if (connector_state->best_encoder != &connector->encoder->base)
13369                         connector->encoder =
13370                                 to_intel_encoder(connector_state->best_encoder);
13371         }
13372
13373         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13374                 bool has_connectors;
13375
13376                 ret = drm_atomic_add_affected_connectors(state, crtc);
13377                 if (ret)
13378                         return ret;
13379
13380                 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13381                 if (has_connectors != crtc_state->enable)
13382                         crtc_state->enable =
13383                         crtc_state->active = has_connectors;
13384         }
13385
13386         ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13387                                               set->fb, set->x, set->y);
13388         if (ret)
13389                 return ret;
13390
13391         crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13392         if (IS_ERR(crtc_state))
13393                 return PTR_ERR(crtc_state);
13394
13395         ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13396         if (ret)
13397                 return ret;
13398
13399         if (set->num_connectors)
13400                 crtc_state->active = true;
13401
13402         return 0;
13403 }
13404
13405 static int intel_crtc_set_config(struct drm_mode_set *set)
13406 {
13407         struct drm_device *dev;
13408         struct drm_atomic_state *state = NULL;
13409         int ret;
13410
13411         BUG_ON(!set);
13412         BUG_ON(!set->crtc);
13413         BUG_ON(!set->crtc->helper_private);
13414
13415         /* Enforce sane interface api - has been abused by the fb helper. */
13416         BUG_ON(!set->mode && set->fb);
13417         BUG_ON(set->fb && set->num_connectors == 0);
13418
13419         if (set->fb) {
13420                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13421                                 set->crtc->base.id, set->fb->base.id,
13422                                 (int)set->num_connectors, set->x, set->y);
13423         } else {
13424                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
13425         }
13426
13427         dev = set->crtc->dev;
13428
13429         state = drm_atomic_state_alloc(dev);
13430         if (!state)
13431                 return -ENOMEM;
13432
13433         state->acquire_ctx = dev->mode_config.acquire_ctx;
13434
13435         ret = intel_modeset_stage_output_state(dev, set, state);
13436         if (ret)
13437                 goto out;
13438
13439         ret = intel_modeset_compute_config(state);
13440         if (ret)
13441                 goto out;
13442
13443         intel_update_pipe_size(to_intel_crtc(set->crtc));
13444
13445         ret = intel_set_mode_checked(state);
13446         if (ret) {
13447                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13448                               set->crtc->base.id, ret);
13449         }
13450
13451 out:
13452         if (ret)
13453                 drm_atomic_state_free(state);
13454         return ret;
13455 }
13456
13457 static const struct drm_crtc_funcs intel_crtc_funcs = {
13458         .gamma_set = intel_crtc_gamma_set,
13459         .set_config = intel_crtc_set_config,
13460         .destroy = intel_crtc_destroy,
13461         .page_flip = intel_crtc_page_flip,
13462         .atomic_duplicate_state = intel_crtc_duplicate_state,
13463         .atomic_destroy_state = intel_crtc_destroy_state,
13464 };
13465
13466 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13467                                       struct intel_shared_dpll *pll,
13468                                       struct intel_dpll_hw_state *hw_state)
13469 {
13470         uint32_t val;
13471
13472         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13473                 return false;
13474
13475         val = I915_READ(PCH_DPLL(pll->id));
13476         hw_state->dpll = val;
13477         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13478         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13479
13480         return val & DPLL_VCO_ENABLE;
13481 }
13482
13483 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13484                                   struct intel_shared_dpll *pll)
13485 {
13486         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13487         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13488 }
13489
13490 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13491                                 struct intel_shared_dpll *pll)
13492 {
13493         /* PCH refclock must be enabled first */
13494         ibx_assert_pch_refclk_enabled(dev_priv);
13495
13496         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13497
13498         /* Wait for the clocks to stabilize. */
13499         POSTING_READ(PCH_DPLL(pll->id));
13500         udelay(150);
13501
13502         /* The pixel multiplier can only be updated once the
13503          * DPLL is enabled and the clocks are stable.
13504          *
13505          * So write it again.
13506          */
13507         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13508         POSTING_READ(PCH_DPLL(pll->id));
13509         udelay(200);
13510 }
13511
13512 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13513                                  struct intel_shared_dpll *pll)
13514 {
13515         struct drm_device *dev = dev_priv->dev;
13516         struct intel_crtc *crtc;
13517
13518         /* Make sure no transcoder isn't still depending on us. */
13519         for_each_intel_crtc(dev, crtc) {
13520                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13521                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13522         }
13523
13524         I915_WRITE(PCH_DPLL(pll->id), 0);
13525         POSTING_READ(PCH_DPLL(pll->id));
13526         udelay(200);
13527 }
13528
13529 static char *ibx_pch_dpll_names[] = {
13530         "PCH DPLL A",
13531         "PCH DPLL B",
13532 };
13533
13534 static void ibx_pch_dpll_init(struct drm_device *dev)
13535 {
13536         struct drm_i915_private *dev_priv = dev->dev_private;
13537         int i;
13538
13539         dev_priv->num_shared_dpll = 2;
13540
13541         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13542                 dev_priv->shared_dplls[i].id = i;
13543                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13544                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13545                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13546                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13547                 dev_priv->shared_dplls[i].get_hw_state =
13548                         ibx_pch_dpll_get_hw_state;
13549         }
13550 }
13551
13552 static void intel_shared_dpll_init(struct drm_device *dev)
13553 {
13554         struct drm_i915_private *dev_priv = dev->dev_private;
13555
13556         intel_update_cdclk(dev);
13557
13558         if (HAS_DDI(dev))
13559                 intel_ddi_pll_init(dev);
13560         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13561                 ibx_pch_dpll_init(dev);
13562         else
13563                 dev_priv->num_shared_dpll = 0;
13564
13565         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13566 }
13567
13568 /**
13569  * intel_prepare_plane_fb - Prepare fb for usage on plane
13570  * @plane: drm plane to prepare for
13571  * @fb: framebuffer to prepare for presentation
13572  *
13573  * Prepares a framebuffer for usage on a display plane.  Generally this
13574  * involves pinning the underlying object and updating the frontbuffer tracking
13575  * bits.  Some older platforms need special physical address handling for
13576  * cursor planes.
13577  *
13578  * Returns 0 on success, negative error code on failure.
13579  */
13580 int
13581 intel_prepare_plane_fb(struct drm_plane *plane,
13582                        struct drm_framebuffer *fb,
13583                        const struct drm_plane_state *new_state)
13584 {
13585         struct drm_device *dev = plane->dev;
13586         struct intel_plane *intel_plane = to_intel_plane(plane);
13587         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13588         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13589         int ret = 0;
13590
13591         if (!obj)
13592                 return 0;
13593
13594         mutex_lock(&dev->struct_mutex);
13595
13596         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13597             INTEL_INFO(dev)->cursor_needs_physical) {
13598                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13599                 ret = i915_gem_object_attach_phys(obj, align);
13600                 if (ret)
13601                         DRM_DEBUG_KMS("failed to attach phys object\n");
13602         } else {
13603                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13604         }
13605
13606         if (ret == 0)
13607                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13608
13609         mutex_unlock(&dev->struct_mutex);
13610
13611         return ret;
13612 }
13613
13614 /**
13615  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13616  * @plane: drm plane to clean up for
13617  * @fb: old framebuffer that was on plane
13618  *
13619  * Cleans up a framebuffer that has just been removed from a plane.
13620  */
13621 void
13622 intel_cleanup_plane_fb(struct drm_plane *plane,
13623                        struct drm_framebuffer *fb,
13624                        const struct drm_plane_state *old_state)
13625 {
13626         struct drm_device *dev = plane->dev;
13627         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13628
13629         if (WARN_ON(!obj))
13630                 return;
13631
13632         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13633             !INTEL_INFO(dev)->cursor_needs_physical) {
13634                 mutex_lock(&dev->struct_mutex);
13635                 intel_unpin_fb_obj(fb, old_state);
13636                 mutex_unlock(&dev->struct_mutex);
13637         }
13638 }
13639
13640 int
13641 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13642 {
13643         int max_scale;
13644         struct drm_device *dev;
13645         struct drm_i915_private *dev_priv;
13646         int crtc_clock, cdclk;
13647
13648         if (!intel_crtc || !crtc_state)
13649                 return DRM_PLANE_HELPER_NO_SCALING;
13650
13651         dev = intel_crtc->base.dev;
13652         dev_priv = dev->dev_private;
13653         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13654         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13655
13656         if (!crtc_clock || !cdclk)
13657                 return DRM_PLANE_HELPER_NO_SCALING;
13658
13659         /*
13660          * skl max scale is lower of:
13661          *    close to 3 but not 3, -1 is for that purpose
13662          *            or
13663          *    cdclk/crtc_clock
13664          */
13665         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13666
13667         return max_scale;
13668 }
13669
13670 static int
13671 intel_check_primary_plane(struct drm_plane *plane,
13672                           struct intel_crtc_state *crtc_state,
13673                           struct intel_plane_state *state)
13674 {
13675         struct drm_crtc *crtc = state->base.crtc;
13676         struct drm_framebuffer *fb = state->base.fb;
13677         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13678         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13679         bool can_position = false;
13680
13681         /* use scaler when colorkey is not required */
13682         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13683             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13684                 min_scale = 1;
13685                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13686                 can_position = true;
13687         }
13688
13689         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13690                                              &state->dst, &state->clip,
13691                                              min_scale, max_scale,
13692                                              can_position, true,
13693                                              &state->visible);
13694 }
13695
13696 static void
13697 intel_commit_primary_plane(struct drm_plane *plane,
13698                            struct intel_plane_state *state)
13699 {
13700         struct drm_crtc *crtc = state->base.crtc;
13701         struct drm_framebuffer *fb = state->base.fb;
13702         struct drm_device *dev = plane->dev;
13703         struct drm_i915_private *dev_priv = dev->dev_private;
13704         struct intel_crtc *intel_crtc;
13705         struct drm_rect *src = &state->src;
13706
13707         crtc = crtc ? crtc : plane->crtc;
13708         intel_crtc = to_intel_crtc(crtc);
13709
13710         plane->fb = fb;
13711         crtc->x = src->x1 >> 16;
13712         crtc->y = src->y1 >> 16;
13713
13714         if (!crtc->state->active)
13715                 return;
13716
13717         if (state->visible)
13718                 /* FIXME: kill this fastboot hack */
13719                 intel_update_pipe_size(intel_crtc);
13720
13721         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13722 }
13723
13724 static void
13725 intel_disable_primary_plane(struct drm_plane *plane,
13726                             struct drm_crtc *crtc)
13727 {
13728         struct drm_device *dev = plane->dev;
13729         struct drm_i915_private *dev_priv = dev->dev_private;
13730
13731         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13732 }
13733
13734 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13735 {
13736         struct drm_device *dev = crtc->dev;
13737         struct drm_i915_private *dev_priv = dev->dev_private;
13738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13739
13740         if (!needs_modeset(crtc->state))
13741                 intel_pre_plane_update(intel_crtc);
13742
13743         if (intel_crtc->atomic.update_wm_pre)
13744                 intel_update_watermarks(crtc);
13745
13746         intel_runtime_pm_get(dev_priv);
13747
13748         /* Perform vblank evasion around commit operation */
13749         if (crtc->state->active)
13750                 intel_crtc->atomic.evade =
13751                         intel_pipe_update_start(intel_crtc,
13752                                                 &intel_crtc->atomic.start_vbl_count);
13753
13754         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13755                 skl_detach_scalers(intel_crtc);
13756 }
13757
13758 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13759 {
13760         struct drm_device *dev = crtc->dev;
13761         struct drm_i915_private *dev_priv = dev->dev_private;
13762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13763
13764         if (intel_crtc->atomic.evade)
13765                 intel_pipe_update_end(intel_crtc,
13766                                       intel_crtc->atomic.start_vbl_count);
13767
13768         intel_runtime_pm_put(dev_priv);
13769
13770         intel_post_plane_update(intel_crtc);
13771 }
13772
13773 /**
13774  * intel_plane_destroy - destroy a plane
13775  * @plane: plane to destroy
13776  *
13777  * Common destruction function for all types of planes (primary, cursor,
13778  * sprite).
13779  */
13780 void intel_plane_destroy(struct drm_plane *plane)
13781 {
13782         struct intel_plane *intel_plane = to_intel_plane(plane);
13783         drm_plane_cleanup(plane);
13784         kfree(intel_plane);
13785 }
13786
13787 const struct drm_plane_funcs intel_plane_funcs = {
13788         .update_plane = drm_atomic_helper_update_plane,
13789         .disable_plane = drm_atomic_helper_disable_plane,
13790         .destroy = intel_plane_destroy,
13791         .set_property = drm_atomic_helper_plane_set_property,
13792         .atomic_get_property = intel_plane_atomic_get_property,
13793         .atomic_set_property = intel_plane_atomic_set_property,
13794         .atomic_duplicate_state = intel_plane_duplicate_state,
13795         .atomic_destroy_state = intel_plane_destroy_state,
13796
13797 };
13798
13799 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13800                                                     int pipe)
13801 {
13802         struct intel_plane *primary;
13803         struct intel_plane_state *state;
13804         const uint32_t *intel_primary_formats;
13805         int num_formats;
13806
13807         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13808         if (primary == NULL)
13809                 return NULL;
13810
13811         state = intel_create_plane_state(&primary->base);
13812         if (!state) {
13813                 kfree(primary);
13814                 return NULL;
13815         }
13816         primary->base.state = &state->base;
13817
13818         primary->can_scale = false;
13819         primary->max_downscale = 1;
13820         if (INTEL_INFO(dev)->gen >= 9) {
13821                 primary->can_scale = true;
13822                 state->scaler_id = -1;
13823         }
13824         primary->pipe = pipe;
13825         primary->plane = pipe;
13826         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13827         primary->check_plane = intel_check_primary_plane;
13828         primary->commit_plane = intel_commit_primary_plane;
13829         primary->disable_plane = intel_disable_primary_plane;
13830         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13831                 primary->plane = !pipe;
13832
13833         if (INTEL_INFO(dev)->gen >= 9) {
13834                 intel_primary_formats = skl_primary_formats;
13835                 num_formats = ARRAY_SIZE(skl_primary_formats);
13836         } else if (INTEL_INFO(dev)->gen >= 4) {
13837                 intel_primary_formats = i965_primary_formats;
13838                 num_formats = ARRAY_SIZE(i965_primary_formats);
13839         } else {
13840                 intel_primary_formats = i8xx_primary_formats;
13841                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13842         }
13843
13844         drm_universal_plane_init(dev, &primary->base, 0,
13845                                  &intel_plane_funcs,
13846                                  intel_primary_formats, num_formats,
13847                                  DRM_PLANE_TYPE_PRIMARY);
13848
13849         if (INTEL_INFO(dev)->gen >= 4)
13850                 intel_create_rotation_property(dev, primary);
13851
13852         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13853
13854         return &primary->base;
13855 }
13856
13857 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13858 {
13859         if (!dev->mode_config.rotation_property) {
13860                 unsigned long flags = BIT(DRM_ROTATE_0) |
13861                         BIT(DRM_ROTATE_180);
13862
13863                 if (INTEL_INFO(dev)->gen >= 9)
13864                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13865
13866                 dev->mode_config.rotation_property =
13867                         drm_mode_create_rotation_property(dev, flags);
13868         }
13869         if (dev->mode_config.rotation_property)
13870                 drm_object_attach_property(&plane->base.base,
13871                                 dev->mode_config.rotation_property,
13872                                 plane->base.state->rotation);
13873 }
13874
13875 static int
13876 intel_check_cursor_plane(struct drm_plane *plane,
13877                          struct intel_crtc_state *crtc_state,
13878                          struct intel_plane_state *state)
13879 {
13880         struct drm_crtc *crtc = crtc_state->base.crtc;
13881         struct drm_framebuffer *fb = state->base.fb;
13882         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13883         unsigned stride;
13884         int ret;
13885
13886         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13887                                             &state->dst, &state->clip,
13888                                             DRM_PLANE_HELPER_NO_SCALING,
13889                                             DRM_PLANE_HELPER_NO_SCALING,
13890                                             true, true, &state->visible);
13891         if (ret)
13892                 return ret;
13893
13894         /* if we want to turn off the cursor ignore width and height */
13895         if (!obj)
13896                 return 0;
13897
13898         /* Check for which cursor types we support */
13899         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13900                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13901                           state->base.crtc_w, state->base.crtc_h);
13902                 return -EINVAL;
13903         }
13904
13905         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13906         if (obj->base.size < stride * state->base.crtc_h) {
13907                 DRM_DEBUG_KMS("buffer is too small\n");
13908                 return -ENOMEM;
13909         }
13910
13911         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13912                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13913                 return -EINVAL;
13914         }
13915
13916         return 0;
13917 }
13918
13919 static void
13920 intel_disable_cursor_plane(struct drm_plane *plane,
13921                            struct drm_crtc *crtc)
13922 {
13923         intel_crtc_update_cursor(crtc, false);
13924 }
13925
13926 static void
13927 intel_commit_cursor_plane(struct drm_plane *plane,
13928                           struct intel_plane_state *state)
13929 {
13930         struct drm_crtc *crtc = state->base.crtc;
13931         struct drm_device *dev = plane->dev;
13932         struct intel_crtc *intel_crtc;
13933         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13934         uint32_t addr;
13935
13936         crtc = crtc ? crtc : plane->crtc;
13937         intel_crtc = to_intel_crtc(crtc);
13938
13939         plane->fb = state->base.fb;
13940         crtc->cursor_x = state->base.crtc_x;
13941         crtc->cursor_y = state->base.crtc_y;
13942
13943         if (intel_crtc->cursor_bo == obj)
13944                 goto update;
13945
13946         if (!obj)
13947                 addr = 0;
13948         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13949                 addr = i915_gem_obj_ggtt_offset(obj);
13950         else
13951                 addr = obj->phys_handle->busaddr;
13952
13953         intel_crtc->cursor_addr = addr;
13954         intel_crtc->cursor_bo = obj;
13955
13956 update:
13957         if (crtc->state->active)
13958                 intel_crtc_update_cursor(crtc, state->visible);
13959 }
13960
13961 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13962                                                    int pipe)
13963 {
13964         struct intel_plane *cursor;
13965         struct intel_plane_state *state;
13966
13967         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13968         if (cursor == NULL)
13969                 return NULL;
13970
13971         state = intel_create_plane_state(&cursor->base);
13972         if (!state) {
13973                 kfree(cursor);
13974                 return NULL;
13975         }
13976         cursor->base.state = &state->base;
13977
13978         cursor->can_scale = false;
13979         cursor->max_downscale = 1;
13980         cursor->pipe = pipe;
13981         cursor->plane = pipe;
13982         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13983         cursor->check_plane = intel_check_cursor_plane;
13984         cursor->commit_plane = intel_commit_cursor_plane;
13985         cursor->disable_plane = intel_disable_cursor_plane;
13986
13987         drm_universal_plane_init(dev, &cursor->base, 0,
13988                                  &intel_plane_funcs,
13989                                  intel_cursor_formats,
13990                                  ARRAY_SIZE(intel_cursor_formats),
13991                                  DRM_PLANE_TYPE_CURSOR);
13992
13993         if (INTEL_INFO(dev)->gen >= 4) {
13994                 if (!dev->mode_config.rotation_property)
13995                         dev->mode_config.rotation_property =
13996                                 drm_mode_create_rotation_property(dev,
13997                                                         BIT(DRM_ROTATE_0) |
13998                                                         BIT(DRM_ROTATE_180));
13999                 if (dev->mode_config.rotation_property)
14000                         drm_object_attach_property(&cursor->base.base,
14001                                 dev->mode_config.rotation_property,
14002                                 state->base.rotation);
14003         }
14004
14005         if (INTEL_INFO(dev)->gen >=9)
14006                 state->scaler_id = -1;
14007
14008         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14009
14010         return &cursor->base;
14011 }
14012
14013 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14014         struct intel_crtc_state *crtc_state)
14015 {
14016         int i;
14017         struct intel_scaler *intel_scaler;
14018         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14019
14020         for (i = 0; i < intel_crtc->num_scalers; i++) {
14021                 intel_scaler = &scaler_state->scalers[i];
14022                 intel_scaler->in_use = 0;
14023                 intel_scaler->mode = PS_SCALER_MODE_DYN;
14024         }
14025
14026         scaler_state->scaler_id = -1;
14027 }
14028
14029 static void intel_crtc_init(struct drm_device *dev, int pipe)
14030 {
14031         struct drm_i915_private *dev_priv = dev->dev_private;
14032         struct intel_crtc *intel_crtc;
14033         struct intel_crtc_state *crtc_state = NULL;
14034         struct drm_plane *primary = NULL;
14035         struct drm_plane *cursor = NULL;
14036         int i, ret;
14037
14038         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14039         if (intel_crtc == NULL)
14040                 return;
14041
14042         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14043         if (!crtc_state)
14044                 goto fail;
14045         intel_crtc->config = crtc_state;
14046         intel_crtc->base.state = &crtc_state->base;
14047         crtc_state->base.crtc = &intel_crtc->base;
14048
14049         /* initialize shared scalers */
14050         if (INTEL_INFO(dev)->gen >= 9) {
14051                 if (pipe == PIPE_C)
14052                         intel_crtc->num_scalers = 1;
14053                 else
14054                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
14055
14056                 skl_init_scalers(dev, intel_crtc, crtc_state);
14057         }
14058
14059         primary = intel_primary_plane_create(dev, pipe);
14060         if (!primary)
14061                 goto fail;
14062
14063         cursor = intel_cursor_plane_create(dev, pipe);
14064         if (!cursor)
14065                 goto fail;
14066
14067         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14068                                         cursor, &intel_crtc_funcs);
14069         if (ret)
14070                 goto fail;
14071
14072         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14073         for (i = 0; i < 256; i++) {
14074                 intel_crtc->lut_r[i] = i;
14075                 intel_crtc->lut_g[i] = i;
14076                 intel_crtc->lut_b[i] = i;
14077         }
14078
14079         /*
14080          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14081          * is hooked to pipe B. Hence we want plane A feeding pipe B.
14082          */
14083         intel_crtc->pipe = pipe;
14084         intel_crtc->plane = pipe;
14085         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14086                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14087                 intel_crtc->plane = !pipe;
14088         }
14089
14090         intel_crtc->cursor_base = ~0;
14091         intel_crtc->cursor_cntl = ~0;
14092         intel_crtc->cursor_size = ~0;
14093
14094         intel_crtc->wm.cxsr_allowed = true;
14095
14096         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14097                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14098         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14099         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14100
14101         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14102
14103         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14104         return;
14105
14106 fail:
14107         if (primary)
14108                 drm_plane_cleanup(primary);
14109         if (cursor)
14110                 drm_plane_cleanup(cursor);
14111         kfree(crtc_state);
14112         kfree(intel_crtc);
14113 }
14114
14115 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14116 {
14117         struct drm_encoder *encoder = connector->base.encoder;
14118         struct drm_device *dev = connector->base.dev;
14119
14120         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14121
14122         if (!encoder || WARN_ON(!encoder->crtc))
14123                 return INVALID_PIPE;
14124
14125         return to_intel_crtc(encoder->crtc)->pipe;
14126 }
14127
14128 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14129                                 struct drm_file *file)
14130 {
14131         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14132         struct drm_crtc *drmmode_crtc;
14133         struct intel_crtc *crtc;
14134
14135         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14136
14137         if (!drmmode_crtc) {
14138                 DRM_ERROR("no such CRTC id\n");
14139                 return -ENOENT;
14140         }
14141
14142         crtc = to_intel_crtc(drmmode_crtc);
14143         pipe_from_crtc_id->pipe = crtc->pipe;
14144
14145         return 0;
14146 }
14147
14148 static int intel_encoder_clones(struct intel_encoder *encoder)
14149 {
14150         struct drm_device *dev = encoder->base.dev;
14151         struct intel_encoder *source_encoder;
14152         int index_mask = 0;
14153         int entry = 0;
14154
14155         for_each_intel_encoder(dev, source_encoder) {
14156                 if (encoders_cloneable(encoder, source_encoder))
14157                         index_mask |= (1 << entry);
14158
14159                 entry++;
14160         }
14161
14162         return index_mask;
14163 }
14164
14165 static bool has_edp_a(struct drm_device *dev)
14166 {
14167         struct drm_i915_private *dev_priv = dev->dev_private;
14168
14169         if (!IS_MOBILE(dev))
14170                 return false;
14171
14172         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14173                 return false;
14174
14175         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14176                 return false;
14177
14178         return true;
14179 }
14180
14181 static bool intel_crt_present(struct drm_device *dev)
14182 {
14183         struct drm_i915_private *dev_priv = dev->dev_private;
14184
14185         if (INTEL_INFO(dev)->gen >= 9)
14186                 return false;
14187
14188         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14189                 return false;
14190
14191         if (IS_CHERRYVIEW(dev))
14192                 return false;
14193
14194         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14195                 return false;
14196
14197         return true;
14198 }
14199
14200 static void intel_setup_outputs(struct drm_device *dev)
14201 {
14202         struct drm_i915_private *dev_priv = dev->dev_private;
14203         struct intel_encoder *encoder;
14204         bool dpd_is_edp = false;
14205
14206         intel_lvds_init(dev);
14207
14208         if (intel_crt_present(dev))
14209                 intel_crt_init(dev);
14210
14211         if (IS_BROXTON(dev)) {
14212                 /*
14213                  * FIXME: Broxton doesn't support port detection via the
14214                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14215                  * detect the ports.
14216                  */
14217                 intel_ddi_init(dev, PORT_A);
14218                 intel_ddi_init(dev, PORT_B);
14219                 intel_ddi_init(dev, PORT_C);
14220         } else if (HAS_DDI(dev)) {
14221                 int found;
14222
14223                 /*
14224                  * Haswell uses DDI functions to detect digital outputs.
14225                  * On SKL pre-D0 the strap isn't connected, so we assume
14226                  * it's there.
14227                  */
14228                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14229                 /* WaIgnoreDDIAStrap: skl */
14230                 if (found ||
14231                     (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14232                         intel_ddi_init(dev, PORT_A);
14233
14234                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14235                  * register */
14236                 found = I915_READ(SFUSE_STRAP);
14237
14238                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14239                         intel_ddi_init(dev, PORT_B);
14240                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14241                         intel_ddi_init(dev, PORT_C);
14242                 if (found & SFUSE_STRAP_DDID_DETECTED)
14243                         intel_ddi_init(dev, PORT_D);
14244         } else if (HAS_PCH_SPLIT(dev)) {
14245                 int found;
14246                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14247
14248                 if (has_edp_a(dev))
14249                         intel_dp_init(dev, DP_A, PORT_A);
14250
14251                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14252                         /* PCH SDVOB multiplex with HDMIB */
14253                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14254                         if (!found)
14255                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14256                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14257                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14258                 }
14259
14260                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14261                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14262
14263                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14264                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14265
14266                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14267                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14268
14269                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14270                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14271         } else if (IS_VALLEYVIEW(dev)) {
14272                 /*
14273                  * The DP_DETECTED bit is the latched state of the DDC
14274                  * SDA pin at boot. However since eDP doesn't require DDC
14275                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14276                  * eDP ports may have been muxed to an alternate function.
14277                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14278                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14279                  * detect eDP ports.
14280                  */
14281                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14282                     !intel_dp_is_edp(dev, PORT_B))
14283                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14284                                         PORT_B);
14285                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14286                     intel_dp_is_edp(dev, PORT_B))
14287                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14288
14289                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14290                     !intel_dp_is_edp(dev, PORT_C))
14291                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14292                                         PORT_C);
14293                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14294                     intel_dp_is_edp(dev, PORT_C))
14295                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14296
14297                 if (IS_CHERRYVIEW(dev)) {
14298                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14299                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14300                                                 PORT_D);
14301                         /* eDP not supported on port D, so don't check VBT */
14302                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14303                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14304                 }
14305
14306                 intel_dsi_init(dev);
14307         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
14308                 bool found = false;
14309
14310                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14311                         DRM_DEBUG_KMS("probing SDVOB\n");
14312                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14313                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14314                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14315                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14316                         }
14317
14318                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
14319                                 intel_dp_init(dev, DP_B, PORT_B);
14320                 }
14321
14322                 /* Before G4X SDVOC doesn't have its own detect register */
14323
14324                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14325                         DRM_DEBUG_KMS("probing SDVOC\n");
14326                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14327                 }
14328
14329                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14330
14331                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14332                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14333                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14334                         }
14335                         if (SUPPORTS_INTEGRATED_DP(dev))
14336                                 intel_dp_init(dev, DP_C, PORT_C);
14337                 }
14338
14339                 if (SUPPORTS_INTEGRATED_DP(dev) &&
14340                     (I915_READ(DP_D) & DP_DETECTED))
14341                         intel_dp_init(dev, DP_D, PORT_D);
14342         } else if (IS_GEN2(dev))
14343                 intel_dvo_init(dev);
14344
14345         if (SUPPORTS_TV(dev))
14346                 intel_tv_init(dev);
14347
14348         intel_psr_init(dev);
14349
14350         for_each_intel_encoder(dev, encoder) {
14351                 encoder->base.possible_crtcs = encoder->crtc_mask;
14352                 encoder->base.possible_clones =
14353                         intel_encoder_clones(encoder);
14354         }
14355
14356         intel_init_pch_refclk(dev);
14357
14358         drm_helper_move_panel_connectors_to_head(dev);
14359 }
14360
14361 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14362 {
14363         struct drm_device *dev = fb->dev;
14364         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14365
14366         drm_framebuffer_cleanup(fb);
14367         mutex_lock(&dev->struct_mutex);
14368         WARN_ON(!intel_fb->obj->framebuffer_references--);
14369         drm_gem_object_unreference(&intel_fb->obj->base);
14370         mutex_unlock(&dev->struct_mutex);
14371         kfree(intel_fb);
14372 }
14373
14374 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14375                                                 struct drm_file *file,
14376                                                 unsigned int *handle)
14377 {
14378         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14379         struct drm_i915_gem_object *obj = intel_fb->obj;
14380
14381         return drm_gem_handle_create(file, &obj->base, handle);
14382 }
14383
14384 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14385         .destroy = intel_user_framebuffer_destroy,
14386         .create_handle = intel_user_framebuffer_create_handle,
14387 };
14388
14389 static
14390 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14391                          uint32_t pixel_format)
14392 {
14393         u32 gen = INTEL_INFO(dev)->gen;
14394
14395         if (gen >= 9) {
14396                 /* "The stride in bytes must not exceed the of the size of 8K
14397                  *  pixels and 32K bytes."
14398                  */
14399                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14400         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14401                 return 32*1024;
14402         } else if (gen >= 4) {
14403                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14404                         return 16*1024;
14405                 else
14406                         return 32*1024;
14407         } else if (gen >= 3) {
14408                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14409                         return 8*1024;
14410                 else
14411                         return 16*1024;
14412         } else {
14413                 /* XXX DSPC is limited to 4k tiled */
14414                 return 8*1024;
14415         }
14416 }
14417
14418 static int intel_framebuffer_init(struct drm_device *dev,
14419                                   struct intel_framebuffer *intel_fb,
14420                                   struct drm_mode_fb_cmd2 *mode_cmd,
14421                                   struct drm_i915_gem_object *obj)
14422 {
14423         unsigned int aligned_height;
14424         int ret;
14425         u32 pitch_limit, stride_alignment;
14426
14427         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14428
14429         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14430                 /* Enforce that fb modifier and tiling mode match, but only for
14431                  * X-tiled. This is needed for FBC. */
14432                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14433                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14434                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14435                         return -EINVAL;
14436                 }
14437         } else {
14438                 if (obj->tiling_mode == I915_TILING_X)
14439                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14440                 else if (obj->tiling_mode == I915_TILING_Y) {
14441                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14442                         return -EINVAL;
14443                 }
14444         }
14445
14446         /* Passed in modifier sanity checking. */
14447         switch (mode_cmd->modifier[0]) {
14448         case I915_FORMAT_MOD_Y_TILED:
14449         case I915_FORMAT_MOD_Yf_TILED:
14450                 if (INTEL_INFO(dev)->gen < 9) {
14451                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14452                                   mode_cmd->modifier[0]);
14453                         return -EINVAL;
14454                 }
14455         case DRM_FORMAT_MOD_NONE:
14456         case I915_FORMAT_MOD_X_TILED:
14457                 break;
14458         default:
14459                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14460                           mode_cmd->modifier[0]);
14461                 return -EINVAL;
14462         }
14463
14464         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14465                                                      mode_cmd->pixel_format);
14466         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14467                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14468                           mode_cmd->pitches[0], stride_alignment);
14469                 return -EINVAL;
14470         }
14471
14472         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14473                                            mode_cmd->pixel_format);
14474         if (mode_cmd->pitches[0] > pitch_limit) {
14475                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14476                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14477                           "tiled" : "linear",
14478                           mode_cmd->pitches[0], pitch_limit);
14479                 return -EINVAL;
14480         }
14481
14482         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14483             mode_cmd->pitches[0] != obj->stride) {
14484                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14485                           mode_cmd->pitches[0], obj->stride);
14486                 return -EINVAL;
14487         }
14488
14489         /* Reject formats not supported by any plane early. */
14490         switch (mode_cmd->pixel_format) {
14491         case DRM_FORMAT_C8:
14492         case DRM_FORMAT_RGB565:
14493         case DRM_FORMAT_XRGB8888:
14494         case DRM_FORMAT_ARGB8888:
14495                 break;
14496         case DRM_FORMAT_XRGB1555:
14497                 if (INTEL_INFO(dev)->gen > 3) {
14498                         DRM_DEBUG("unsupported pixel format: %s\n",
14499                                   drm_get_format_name(mode_cmd->pixel_format));
14500                         return -EINVAL;
14501                 }
14502                 break;
14503         case DRM_FORMAT_ABGR8888:
14504                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14505                         DRM_DEBUG("unsupported pixel format: %s\n",
14506                                   drm_get_format_name(mode_cmd->pixel_format));
14507                         return -EINVAL;
14508                 }
14509                 break;
14510         case DRM_FORMAT_XBGR8888:
14511         case DRM_FORMAT_XRGB2101010:
14512         case DRM_FORMAT_XBGR2101010:
14513                 if (INTEL_INFO(dev)->gen < 4) {
14514                         DRM_DEBUG("unsupported pixel format: %s\n",
14515                                   drm_get_format_name(mode_cmd->pixel_format));
14516                         return -EINVAL;
14517                 }
14518                 break;
14519         case DRM_FORMAT_ABGR2101010:
14520                 if (!IS_VALLEYVIEW(dev)) {
14521                         DRM_DEBUG("unsupported pixel format: %s\n",
14522                                   drm_get_format_name(mode_cmd->pixel_format));
14523                         return -EINVAL;
14524                 }
14525                 break;
14526         case DRM_FORMAT_YUYV:
14527         case DRM_FORMAT_UYVY:
14528         case DRM_FORMAT_YVYU:
14529         case DRM_FORMAT_VYUY:
14530                 if (INTEL_INFO(dev)->gen < 5) {
14531                         DRM_DEBUG("unsupported pixel format: %s\n",
14532                                   drm_get_format_name(mode_cmd->pixel_format));
14533                         return -EINVAL;
14534                 }
14535                 break;
14536         default:
14537                 DRM_DEBUG("unsupported pixel format: %s\n",
14538                           drm_get_format_name(mode_cmd->pixel_format));
14539                 return -EINVAL;
14540         }
14541
14542         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14543         if (mode_cmd->offsets[0] != 0)
14544                 return -EINVAL;
14545
14546         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14547                                                mode_cmd->pixel_format,
14548                                                mode_cmd->modifier[0]);
14549         /* FIXME drm helper for size checks (especially planar formats)? */
14550         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14551                 return -EINVAL;
14552
14553         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14554         intel_fb->obj = obj;
14555         intel_fb->obj->framebuffer_references++;
14556
14557         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14558         if (ret) {
14559                 DRM_ERROR("framebuffer init failed %d\n", ret);
14560                 return ret;
14561         }
14562
14563         return 0;
14564 }
14565
14566 static struct drm_framebuffer *
14567 intel_user_framebuffer_create(struct drm_device *dev,
14568                               struct drm_file *filp,
14569                               struct drm_mode_fb_cmd2 *mode_cmd)
14570 {
14571         struct drm_i915_gem_object *obj;
14572
14573         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14574                                                 mode_cmd->handles[0]));
14575         if (&obj->base == NULL)
14576                 return ERR_PTR(-ENOENT);
14577
14578         return intel_framebuffer_create(dev, mode_cmd, obj);
14579 }
14580
14581 #ifndef CONFIG_DRM_I915_FBDEV
14582 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14583 {
14584 }
14585 #endif
14586
14587 static const struct drm_mode_config_funcs intel_mode_funcs = {
14588         .fb_create = intel_user_framebuffer_create,
14589         .output_poll_changed = intel_fbdev_output_poll_changed,
14590         .atomic_check = intel_atomic_check,
14591         .atomic_commit = intel_atomic_commit,
14592         .atomic_state_alloc = intel_atomic_state_alloc,
14593         .atomic_state_clear = intel_atomic_state_clear,
14594 };
14595
14596 /* Set up chip specific display functions */
14597 static void intel_init_display(struct drm_device *dev)
14598 {
14599         struct drm_i915_private *dev_priv = dev->dev_private;
14600
14601         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14602                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14603         else if (IS_CHERRYVIEW(dev))
14604                 dev_priv->display.find_dpll = chv_find_best_dpll;
14605         else if (IS_VALLEYVIEW(dev))
14606                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14607         else if (IS_PINEVIEW(dev))
14608                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14609         else
14610                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14611
14612         if (INTEL_INFO(dev)->gen >= 9) {
14613                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14614                 dev_priv->display.get_initial_plane_config =
14615                         skylake_get_initial_plane_config;
14616                 dev_priv->display.crtc_compute_clock =
14617                         haswell_crtc_compute_clock;
14618                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14619                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14620                 dev_priv->display.update_primary_plane =
14621                         skylake_update_primary_plane;
14622         } else if (HAS_DDI(dev)) {
14623                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14624                 dev_priv->display.get_initial_plane_config =
14625                         ironlake_get_initial_plane_config;
14626                 dev_priv->display.crtc_compute_clock =
14627                         haswell_crtc_compute_clock;
14628                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14629                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14630                 dev_priv->display.update_primary_plane =
14631                         ironlake_update_primary_plane;
14632         } else if (HAS_PCH_SPLIT(dev)) {
14633                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14634                 dev_priv->display.get_initial_plane_config =
14635                         ironlake_get_initial_plane_config;
14636                 dev_priv->display.crtc_compute_clock =
14637                         ironlake_crtc_compute_clock;
14638                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14639                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14640                 dev_priv->display.update_primary_plane =
14641                         ironlake_update_primary_plane;
14642         } else if (IS_VALLEYVIEW(dev)) {
14643                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14644                 dev_priv->display.get_initial_plane_config =
14645                         i9xx_get_initial_plane_config;
14646                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14647                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14648                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14649                 dev_priv->display.update_primary_plane =
14650                         i9xx_update_primary_plane;
14651         } else {
14652                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14653                 dev_priv->display.get_initial_plane_config =
14654                         i9xx_get_initial_plane_config;
14655                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14656                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14657                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14658                 dev_priv->display.update_primary_plane =
14659                         i9xx_update_primary_plane;
14660         }
14661
14662         /* Returns the core display clock speed */
14663         if (IS_SKYLAKE(dev))
14664                 dev_priv->display.get_display_clock_speed =
14665                         skylake_get_display_clock_speed;
14666         else if (IS_BROXTON(dev))
14667                 dev_priv->display.get_display_clock_speed =
14668                         broxton_get_display_clock_speed;
14669         else if (IS_BROADWELL(dev))
14670                 dev_priv->display.get_display_clock_speed =
14671                         broadwell_get_display_clock_speed;
14672         else if (IS_HASWELL(dev))
14673                 dev_priv->display.get_display_clock_speed =
14674                         haswell_get_display_clock_speed;
14675         else if (IS_VALLEYVIEW(dev))
14676                 dev_priv->display.get_display_clock_speed =
14677                         valleyview_get_display_clock_speed;
14678         else if (IS_GEN5(dev))
14679                 dev_priv->display.get_display_clock_speed =
14680                         ilk_get_display_clock_speed;
14681         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14682                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14683                 dev_priv->display.get_display_clock_speed =
14684                         i945_get_display_clock_speed;
14685         else if (IS_GM45(dev))
14686                 dev_priv->display.get_display_clock_speed =
14687                         gm45_get_display_clock_speed;
14688         else if (IS_CRESTLINE(dev))
14689                 dev_priv->display.get_display_clock_speed =
14690                         i965gm_get_display_clock_speed;
14691         else if (IS_PINEVIEW(dev))
14692                 dev_priv->display.get_display_clock_speed =
14693                         pnv_get_display_clock_speed;
14694         else if (IS_G33(dev) || IS_G4X(dev))
14695                 dev_priv->display.get_display_clock_speed =
14696                         g33_get_display_clock_speed;
14697         else if (IS_I915G(dev))
14698                 dev_priv->display.get_display_clock_speed =
14699                         i915_get_display_clock_speed;
14700         else if (IS_I945GM(dev) || IS_845G(dev))
14701                 dev_priv->display.get_display_clock_speed =
14702                         i9xx_misc_get_display_clock_speed;
14703         else if (IS_PINEVIEW(dev))
14704                 dev_priv->display.get_display_clock_speed =
14705                         pnv_get_display_clock_speed;
14706         else if (IS_I915GM(dev))
14707                 dev_priv->display.get_display_clock_speed =
14708                         i915gm_get_display_clock_speed;
14709         else if (IS_I865G(dev))
14710                 dev_priv->display.get_display_clock_speed =
14711                         i865_get_display_clock_speed;
14712         else if (IS_I85X(dev))
14713                 dev_priv->display.get_display_clock_speed =
14714                         i85x_get_display_clock_speed;
14715         else { /* 830 */
14716                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14717                 dev_priv->display.get_display_clock_speed =
14718                         i830_get_display_clock_speed;
14719         }
14720
14721         if (IS_GEN5(dev)) {
14722                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14723         } else if (IS_GEN6(dev)) {
14724                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14725         } else if (IS_IVYBRIDGE(dev)) {
14726                 /* FIXME: detect B0+ stepping and use auto training */
14727                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14728         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14729                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14730                 if (IS_BROADWELL(dev)) {
14731                         dev_priv->display.modeset_commit_cdclk =
14732                                 broadwell_modeset_commit_cdclk;
14733                         dev_priv->display.modeset_calc_cdclk =
14734                                 broadwell_modeset_calc_cdclk;
14735                 }
14736         } else if (IS_VALLEYVIEW(dev)) {
14737                 dev_priv->display.modeset_commit_cdclk =
14738                         valleyview_modeset_commit_cdclk;
14739                 dev_priv->display.modeset_calc_cdclk =
14740                         valleyview_modeset_calc_cdclk;
14741         } else if (IS_BROXTON(dev)) {
14742                 dev_priv->display.modeset_commit_cdclk =
14743                         broxton_modeset_commit_cdclk;
14744                 dev_priv->display.modeset_calc_cdclk =
14745                         broxton_modeset_calc_cdclk;
14746         }
14747
14748         switch (INTEL_INFO(dev)->gen) {
14749         case 2:
14750                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14751                 break;
14752
14753         case 3:
14754                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14755                 break;
14756
14757         case 4:
14758         case 5:
14759                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14760                 break;
14761
14762         case 6:
14763                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14764                 break;
14765         case 7:
14766         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14767                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14768                 break;
14769         case 9:
14770                 /* Drop through - unsupported since execlist only. */
14771         default:
14772                 /* Default just returns -ENODEV to indicate unsupported */
14773                 dev_priv->display.queue_flip = intel_default_queue_flip;
14774         }
14775
14776         intel_panel_init_backlight_funcs(dev);
14777
14778         mutex_init(&dev_priv->pps_mutex);
14779 }
14780
14781 /*
14782  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14783  * resume, or other times.  This quirk makes sure that's the case for
14784  * affected systems.
14785  */
14786 static void quirk_pipea_force(struct drm_device *dev)
14787 {
14788         struct drm_i915_private *dev_priv = dev->dev_private;
14789
14790         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14791         DRM_INFO("applying pipe a force quirk\n");
14792 }
14793
14794 static void quirk_pipeb_force(struct drm_device *dev)
14795 {
14796         struct drm_i915_private *dev_priv = dev->dev_private;
14797
14798         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14799         DRM_INFO("applying pipe b force quirk\n");
14800 }
14801
14802 /*
14803  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14804  */
14805 static void quirk_ssc_force_disable(struct drm_device *dev)
14806 {
14807         struct drm_i915_private *dev_priv = dev->dev_private;
14808         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14809         DRM_INFO("applying lvds SSC disable quirk\n");
14810 }
14811
14812 /*
14813  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14814  * brightness value
14815  */
14816 static void quirk_invert_brightness(struct drm_device *dev)
14817 {
14818         struct drm_i915_private *dev_priv = dev->dev_private;
14819         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14820         DRM_INFO("applying inverted panel brightness quirk\n");
14821 }
14822
14823 /* Some VBT's incorrectly indicate no backlight is present */
14824 static void quirk_backlight_present(struct drm_device *dev)
14825 {
14826         struct drm_i915_private *dev_priv = dev->dev_private;
14827         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14828         DRM_INFO("applying backlight present quirk\n");
14829 }
14830
14831 struct intel_quirk {
14832         int device;
14833         int subsystem_vendor;
14834         int subsystem_device;
14835         void (*hook)(struct drm_device *dev);
14836 };
14837
14838 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14839 struct intel_dmi_quirk {
14840         void (*hook)(struct drm_device *dev);
14841         const struct dmi_system_id (*dmi_id_list)[];
14842 };
14843
14844 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14845 {
14846         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14847         return 1;
14848 }
14849
14850 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14851         {
14852                 .dmi_id_list = &(const struct dmi_system_id[]) {
14853                         {
14854                                 .callback = intel_dmi_reverse_brightness,
14855                                 .ident = "NCR Corporation",
14856                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14857                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14858                                 },
14859                         },
14860                         { }  /* terminating entry */
14861                 },
14862                 .hook = quirk_invert_brightness,
14863         },
14864 };
14865
14866 static struct intel_quirk intel_quirks[] = {
14867         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14868         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14869
14870         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14871         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14872
14873         /* 830 needs to leave pipe A & dpll A up */
14874         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14875
14876         /* 830 needs to leave pipe B & dpll B up */
14877         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14878
14879         /* Lenovo U160 cannot use SSC on LVDS */
14880         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14881
14882         /* Sony Vaio Y cannot use SSC on LVDS */
14883         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14884
14885         /* Acer Aspire 5734Z must invert backlight brightness */
14886         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14887
14888         /* Acer/eMachines G725 */
14889         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14890
14891         /* Acer/eMachines e725 */
14892         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14893
14894         /* Acer/Packard Bell NCL20 */
14895         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14896
14897         /* Acer Aspire 4736Z */
14898         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14899
14900         /* Acer Aspire 5336 */
14901         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14902
14903         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14904         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14905
14906         /* Acer C720 Chromebook (Core i3 4005U) */
14907         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14908
14909         /* Apple Macbook 2,1 (Core 2 T7400) */
14910         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14911
14912         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14913         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14914
14915         /* HP Chromebook 14 (Celeron 2955U) */
14916         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14917
14918         /* Dell Chromebook 11 */
14919         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14920 };
14921
14922 static void intel_init_quirks(struct drm_device *dev)
14923 {
14924         struct pci_dev *d = dev->pdev;
14925         int i;
14926
14927         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14928                 struct intel_quirk *q = &intel_quirks[i];
14929
14930                 if (d->device == q->device &&
14931                     (d->subsystem_vendor == q->subsystem_vendor ||
14932                      q->subsystem_vendor == PCI_ANY_ID) &&
14933                     (d->subsystem_device == q->subsystem_device ||
14934                      q->subsystem_device == PCI_ANY_ID))
14935                         q->hook(dev);
14936         }
14937         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14938                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14939                         intel_dmi_quirks[i].hook(dev);
14940         }
14941 }
14942
14943 /* Disable the VGA plane that we never use */
14944 static void i915_disable_vga(struct drm_device *dev)
14945 {
14946         struct drm_i915_private *dev_priv = dev->dev_private;
14947         u8 sr1;
14948         u32 vga_reg = i915_vgacntrl_reg(dev);
14949
14950         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14951         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14952         outb(SR01, VGA_SR_INDEX);
14953         sr1 = inb(VGA_SR_DATA);
14954         outb(sr1 | 1<<5, VGA_SR_DATA);
14955         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14956         udelay(300);
14957
14958         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14959         POSTING_READ(vga_reg);
14960 }
14961
14962 void intel_modeset_init_hw(struct drm_device *dev)
14963 {
14964         intel_update_cdclk(dev);
14965         intel_prepare_ddi(dev);
14966         intel_init_clock_gating(dev);
14967         intel_enable_gt_powersave(dev);
14968 }
14969
14970 void intel_modeset_init(struct drm_device *dev)
14971 {
14972         struct drm_i915_private *dev_priv = dev->dev_private;
14973         int sprite, ret;
14974         enum pipe pipe;
14975         struct intel_crtc *crtc;
14976
14977         drm_mode_config_init(dev);
14978
14979         dev->mode_config.min_width = 0;
14980         dev->mode_config.min_height = 0;
14981
14982         dev->mode_config.preferred_depth = 24;
14983         dev->mode_config.prefer_shadow = 1;
14984
14985         dev->mode_config.allow_fb_modifiers = true;
14986
14987         dev->mode_config.funcs = &intel_mode_funcs;
14988
14989         intel_init_quirks(dev);
14990
14991         intel_init_pm(dev);
14992
14993         if (INTEL_INFO(dev)->num_pipes == 0)
14994                 return;
14995
14996         intel_init_display(dev);
14997         intel_init_audio(dev);
14998
14999         if (IS_GEN2(dev)) {
15000                 dev->mode_config.max_width = 2048;
15001                 dev->mode_config.max_height = 2048;
15002         } else if (IS_GEN3(dev)) {
15003                 dev->mode_config.max_width = 4096;
15004                 dev->mode_config.max_height = 4096;
15005         } else {
15006                 dev->mode_config.max_width = 8192;
15007                 dev->mode_config.max_height = 8192;
15008         }
15009
15010         if (IS_845G(dev) || IS_I865G(dev)) {
15011                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15012                 dev->mode_config.cursor_height = 1023;
15013         } else if (IS_GEN2(dev)) {
15014                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15015                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15016         } else {
15017                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15018                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15019         }
15020
15021         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15022
15023         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15024                       INTEL_INFO(dev)->num_pipes,
15025                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15026
15027         for_each_pipe(dev_priv, pipe) {
15028                 intel_crtc_init(dev, pipe);
15029                 for_each_sprite(dev_priv, pipe, sprite) {
15030                         ret = intel_plane_init(dev, pipe, sprite);
15031                         if (ret)
15032                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15033                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
15034                 }
15035         }
15036
15037         intel_init_dpio(dev);
15038
15039         intel_shared_dpll_init(dev);
15040
15041         /* Just disable it once at startup */
15042         i915_disable_vga(dev);
15043         intel_setup_outputs(dev);
15044
15045         /* Just in case the BIOS is doing something questionable. */
15046         intel_fbc_disable(dev);
15047
15048         drm_modeset_lock_all(dev);
15049         intel_modeset_setup_hw_state(dev, false);
15050         drm_modeset_unlock_all(dev);
15051
15052         for_each_intel_crtc(dev, crtc) {
15053                 if (!crtc->active)
15054                         continue;
15055
15056                 /*
15057                  * Note that reserving the BIOS fb up front prevents us
15058                  * from stuffing other stolen allocations like the ring
15059                  * on top.  This prevents some ugliness at boot time, and
15060                  * can even allow for smooth boot transitions if the BIOS
15061                  * fb is large enough for the active pipe configuration.
15062                  */
15063                 if (dev_priv->display.get_initial_plane_config) {
15064                         dev_priv->display.get_initial_plane_config(crtc,
15065                                                            &crtc->plane_config);
15066                         /*
15067                          * If the fb is shared between multiple heads, we'll
15068                          * just get the first one.
15069                          */
15070                         intel_find_initial_plane_obj(crtc, &crtc->plane_config);
15071                 }
15072         }
15073 }
15074
15075 static void intel_enable_pipe_a(struct drm_device *dev)
15076 {
15077         struct intel_connector *connector;
15078         struct drm_connector *crt = NULL;
15079         struct intel_load_detect_pipe load_detect_temp;
15080         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15081
15082         /* We can't just switch on the pipe A, we need to set things up with a
15083          * proper mode and output configuration. As a gross hack, enable pipe A
15084          * by enabling the load detect pipe once. */
15085         for_each_intel_connector(dev, connector) {
15086                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15087                         crt = &connector->base;
15088                         break;
15089                 }
15090         }
15091
15092         if (!crt)
15093                 return;
15094
15095         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15096                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15097 }
15098
15099 static bool
15100 intel_check_plane_mapping(struct intel_crtc *crtc)
15101 {
15102         struct drm_device *dev = crtc->base.dev;
15103         struct drm_i915_private *dev_priv = dev->dev_private;
15104         u32 reg, val;
15105
15106         if (INTEL_INFO(dev)->num_pipes == 1)
15107                 return true;
15108
15109         reg = DSPCNTR(!crtc->plane);
15110         val = I915_READ(reg);
15111
15112         if ((val & DISPLAY_PLANE_ENABLE) &&
15113             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15114                 return false;
15115
15116         return true;
15117 }
15118
15119 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15120 {
15121         struct drm_device *dev = crtc->base.dev;
15122         struct drm_i915_private *dev_priv = dev->dev_private;
15123         struct intel_encoder *encoder;
15124         u32 reg;
15125         bool enable;
15126
15127         /* Clear any frame start delays used for debugging left by the BIOS */
15128         reg = PIPECONF(crtc->config->cpu_transcoder);
15129         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15130
15131         /* restore vblank interrupts to correct state */
15132         drm_crtc_vblank_reset(&crtc->base);
15133         if (crtc->active) {
15134                 update_scanline_offset(crtc);
15135                 drm_crtc_vblank_on(&crtc->base);
15136         }
15137
15138         /* We need to sanitize the plane -> pipe mapping first because this will
15139          * disable the crtc (and hence change the state) if it is wrong. Note
15140          * that gen4+ has a fixed plane -> pipe mapping.  */
15141         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15142                 bool plane;
15143
15144                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15145                               crtc->base.base.id);
15146
15147                 /* Pipe has the wrong plane attached and the plane is active.
15148                  * Temporarily change the plane mapping and disable everything
15149                  * ...  */
15150                 plane = crtc->plane;
15151                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15152                 crtc->plane = !plane;
15153                 intel_crtc_disable_noatomic(&crtc->base);
15154                 crtc->plane = plane;
15155         }
15156
15157         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15158             crtc->pipe == PIPE_A && !crtc->active) {
15159                 /* BIOS forgot to enable pipe A, this mostly happens after
15160                  * resume. Force-enable the pipe to fix this, the update_dpms
15161                  * call below we restore the pipe to the right state, but leave
15162                  * the required bits on. */
15163                 intel_enable_pipe_a(dev);
15164         }
15165
15166         /* Adjust the state of the output pipe according to whether we
15167          * have active connectors/encoders. */
15168         enable = false;
15169         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15170                 enable |= encoder->connectors_active;
15171
15172         if (!enable)
15173                 intel_crtc_disable_noatomic(&crtc->base);
15174
15175         if (crtc->active != crtc->base.state->active) {
15176
15177                 /* This can happen either due to bugs in the get_hw_state
15178                  * functions or because of calls to intel_crtc_disable_noatomic,
15179                  * or because the pipe is force-enabled due to the
15180                  * pipe A quirk. */
15181                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15182                               crtc->base.base.id,
15183                               crtc->base.state->enable ? "enabled" : "disabled",
15184                               crtc->active ? "enabled" : "disabled");
15185
15186                 crtc->base.state->enable = crtc->active;
15187                 crtc->base.state->active = crtc->active;
15188                 crtc->base.enabled = crtc->active;
15189
15190                 /* Because we only establish the connector -> encoder ->
15191                  * crtc links if something is active, this means the
15192                  * crtc is now deactivated. Break the links. connector
15193                  * -> encoder links are only establish when things are
15194                  *  actually up, hence no need to break them. */
15195                 WARN_ON(crtc->active);
15196
15197                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15198                         WARN_ON(encoder->connectors_active);
15199                         encoder->base.crtc = NULL;
15200                 }
15201         }
15202
15203         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15204                 /*
15205                  * We start out with underrun reporting disabled to avoid races.
15206                  * For correct bookkeeping mark this on active crtcs.
15207                  *
15208                  * Also on gmch platforms we dont have any hardware bits to
15209                  * disable the underrun reporting. Which means we need to start
15210                  * out with underrun reporting disabled also on inactive pipes,
15211                  * since otherwise we'll complain about the garbage we read when
15212                  * e.g. coming up after runtime pm.
15213                  *
15214                  * No protection against concurrent access is required - at
15215                  * worst a fifo underrun happens which also sets this to false.
15216                  */
15217                 crtc->cpu_fifo_underrun_disabled = true;
15218                 crtc->pch_fifo_underrun_disabled = true;
15219         }
15220 }
15221
15222 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15223 {
15224         struct intel_connector *connector;
15225         struct drm_device *dev = encoder->base.dev;
15226
15227         /* We need to check both for a crtc link (meaning that the
15228          * encoder is active and trying to read from a pipe) and the
15229          * pipe itself being active. */
15230         bool has_active_crtc = encoder->base.crtc &&
15231                 to_intel_crtc(encoder->base.crtc)->active;
15232
15233         if (encoder->connectors_active && !has_active_crtc) {
15234                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15235                               encoder->base.base.id,
15236                               encoder->base.name);
15237
15238                 /* Connector is active, but has no active pipe. This is
15239                  * fallout from our resume register restoring. Disable
15240                  * the encoder manually again. */
15241                 if (encoder->base.crtc) {
15242                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15243                                       encoder->base.base.id,
15244                                       encoder->base.name);
15245                         encoder->disable(encoder);
15246                         if (encoder->post_disable)
15247                                 encoder->post_disable(encoder);
15248                 }
15249                 encoder->base.crtc = NULL;
15250                 encoder->connectors_active = false;
15251
15252                 /* Inconsistent output/port/pipe state happens presumably due to
15253                  * a bug in one of the get_hw_state functions. Or someplace else
15254                  * in our code, like the register restore mess on resume. Clamp
15255                  * things to off as a safer default. */
15256                 for_each_intel_connector(dev, connector) {
15257                         if (connector->encoder != encoder)
15258                                 continue;
15259                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15260                         connector->base.encoder = NULL;
15261                 }
15262         }
15263         /* Enabled encoders without active connectors will be fixed in
15264          * the crtc fixup. */
15265 }
15266
15267 void i915_redisable_vga_power_on(struct drm_device *dev)
15268 {
15269         struct drm_i915_private *dev_priv = dev->dev_private;
15270         u32 vga_reg = i915_vgacntrl_reg(dev);
15271
15272         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15273                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15274                 i915_disable_vga(dev);
15275         }
15276 }
15277
15278 void i915_redisable_vga(struct drm_device *dev)
15279 {
15280         struct drm_i915_private *dev_priv = dev->dev_private;
15281
15282         /* This function can be called both from intel_modeset_setup_hw_state or
15283          * at a very early point in our resume sequence, where the power well
15284          * structures are not yet restored. Since this function is at a very
15285          * paranoid "someone might have enabled VGA while we were not looking"
15286          * level, just check if the power well is enabled instead of trying to
15287          * follow the "don't touch the power well if we don't need it" policy
15288          * the rest of the driver uses. */
15289         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15290                 return;
15291
15292         i915_redisable_vga_power_on(dev);
15293 }
15294
15295 static bool primary_get_hw_state(struct intel_crtc *crtc)
15296 {
15297         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15298
15299         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15300 }
15301
15302 static void readout_plane_state(struct intel_crtc *crtc,
15303                                 struct intel_crtc_state *crtc_state)
15304 {
15305         struct intel_plane *p;
15306         struct drm_plane_state *drm_plane_state;
15307         bool active = crtc_state->base.active;
15308
15309         if (active) {
15310                 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15311
15312                 /* apply to previous sw state too */
15313                 to_intel_crtc_state(crtc->base.state)->quirks |=
15314                         PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15315         }
15316
15317         for_each_intel_plane(crtc->base.dev, p) {
15318                 bool visible = active;
15319
15320                 if (crtc->pipe != p->pipe)
15321                         continue;
15322
15323                 drm_plane_state = p->base.state;
15324                 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15325                         visible = primary_get_hw_state(crtc);
15326                         to_intel_plane_state(drm_plane_state)->visible = visible;
15327                 } else {
15328                         /*
15329                          * unknown state, assume it's off to force a transition
15330                          * to on when calculating state changes.
15331                          */
15332                         to_intel_plane_state(drm_plane_state)->visible = false;
15333                 }
15334
15335                 if (visible) {
15336                         crtc_state->base.plane_mask |=
15337                                 1 << drm_plane_index(&p->base);
15338                 } else if (crtc_state->base.state) {
15339                         /* Make this unconditional for atomic hw readout. */
15340                         crtc_state->base.plane_mask &=
15341                                 ~(1 << drm_plane_index(&p->base));
15342                 }
15343         }
15344 }
15345
15346 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15347 {
15348         struct drm_i915_private *dev_priv = dev->dev_private;
15349         enum pipe pipe;
15350         struct intel_crtc *crtc;
15351         struct intel_encoder *encoder;
15352         struct intel_connector *connector;
15353         int i;
15354
15355         for_each_intel_crtc(dev, crtc) {
15356                 memset(crtc->config, 0, sizeof(*crtc->config));
15357                 crtc->config->base.crtc = &crtc->base;
15358
15359                 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15360
15361                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15362                                                                  crtc->config);
15363
15364                 crtc->base.state->enable = crtc->active;
15365                 crtc->base.state->active = crtc->active;
15366                 crtc->base.enabled = crtc->active;
15367                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15368
15369                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15370
15371                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15372                               crtc->base.base.id,
15373                               crtc->active ? "enabled" : "disabled");
15374         }
15375
15376         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15377                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15378
15379                 pll->on = pll->get_hw_state(dev_priv, pll,
15380                                             &pll->config.hw_state);
15381                 pll->active = 0;
15382                 pll->config.crtc_mask = 0;
15383                 for_each_intel_crtc(dev, crtc) {
15384                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15385                                 pll->active++;
15386                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15387                         }
15388                 }
15389
15390                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15391                               pll->name, pll->config.crtc_mask, pll->on);
15392
15393                 if (pll->config.crtc_mask)
15394                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15395         }
15396
15397         for_each_intel_encoder(dev, encoder) {
15398                 pipe = 0;
15399
15400                 if (encoder->get_hw_state(encoder, &pipe)) {
15401                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15402                         encoder->base.crtc = &crtc->base;
15403                         encoder->get_config(encoder, crtc->config);
15404                 } else {
15405                         encoder->base.crtc = NULL;
15406                 }
15407
15408                 encoder->connectors_active = false;
15409                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15410                               encoder->base.base.id,
15411                               encoder->base.name,
15412                               encoder->base.crtc ? "enabled" : "disabled",
15413                               pipe_name(pipe));
15414         }
15415
15416         for_each_intel_connector(dev, connector) {
15417                 if (connector->get_hw_state(connector)) {
15418                         connector->base.dpms = DRM_MODE_DPMS_ON;
15419                         connector->encoder->connectors_active = true;
15420                         connector->base.encoder = &connector->encoder->base;
15421                 } else {
15422                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15423                         connector->base.encoder = NULL;
15424                 }
15425                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15426                               connector->base.base.id,
15427                               connector->base.name,
15428                               connector->base.encoder ? "enabled" : "disabled");
15429         }
15430 }
15431
15432 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15433  * and i915 state tracking structures. */
15434 void intel_modeset_setup_hw_state(struct drm_device *dev,
15435                                   bool force_restore)
15436 {
15437         struct drm_i915_private *dev_priv = dev->dev_private;
15438         enum pipe pipe;
15439         struct intel_crtc *crtc;
15440         struct intel_encoder *encoder;
15441         int i;
15442
15443         intel_modeset_readout_hw_state(dev);
15444
15445         /*
15446          * Now that we have the config, copy it to each CRTC struct
15447          * Note that this could go away if we move to using crtc_config
15448          * checking everywhere.
15449          */
15450         for_each_intel_crtc(dev, crtc) {
15451                 if (crtc->active && i915.fastboot) {
15452                         intel_mode_from_pipe_config(&crtc->base.mode,
15453                                                     crtc->config);
15454                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15455                                       crtc->base.base.id);
15456                         drm_mode_debug_printmodeline(&crtc->base.mode);
15457                 }
15458         }
15459
15460         /* HW state is read out, now we need to sanitize this mess. */
15461         for_each_intel_encoder(dev, encoder) {
15462                 intel_sanitize_encoder(encoder);
15463         }
15464
15465         for_each_pipe(dev_priv, pipe) {
15466                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15467                 intel_sanitize_crtc(crtc);
15468                 intel_dump_pipe_config(crtc, crtc->config,
15469                                        "[setup_hw_state]");
15470         }
15471
15472         intel_modeset_update_connector_atomic_state(dev);
15473
15474         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15475                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15476
15477                 if (!pll->on || pll->active)
15478                         continue;
15479
15480                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15481
15482                 pll->disable(dev_priv, pll);
15483                 pll->on = false;
15484         }
15485
15486         if (IS_VALLEYVIEW(dev))
15487                 vlv_wm_get_hw_state(dev);
15488         else if (IS_GEN9(dev))
15489                 skl_wm_get_hw_state(dev);
15490         else if (HAS_PCH_SPLIT(dev))
15491                 ilk_wm_get_hw_state(dev);
15492
15493         if (force_restore) {
15494                 i915_redisable_vga(dev);
15495
15496                 /*
15497                  * We need to use raw interfaces for restoring state to avoid
15498                  * checking (bogus) intermediate states.
15499                  */
15500                 for_each_pipe(dev_priv, pipe) {
15501                         struct drm_crtc *crtc =
15502                                 dev_priv->pipe_to_crtc_mapping[pipe];
15503
15504                         intel_crtc_restore_mode(crtc);
15505                 }
15506         } else {
15507                 intel_modeset_update_staged_output_state(dev);
15508         }
15509
15510         intel_modeset_check_state(dev);
15511 }
15512
15513 void intel_modeset_gem_init(struct drm_device *dev)
15514 {
15515         struct drm_i915_private *dev_priv = dev->dev_private;
15516         struct drm_crtc *c;
15517         struct drm_i915_gem_object *obj;
15518         int ret;
15519
15520         mutex_lock(&dev->struct_mutex);
15521         intel_init_gt_powersave(dev);
15522         mutex_unlock(&dev->struct_mutex);
15523
15524         /*
15525          * There may be no VBT; and if the BIOS enabled SSC we can
15526          * just keep using it to avoid unnecessary flicker.  Whereas if the
15527          * BIOS isn't using it, don't assume it will work even if the VBT
15528          * indicates as much.
15529          */
15530         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15531                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15532                                                 DREF_SSC1_ENABLE);
15533
15534         intel_modeset_init_hw(dev);
15535
15536         intel_setup_overlay(dev);
15537
15538         /*
15539          * Make sure any fbs we allocated at startup are properly
15540          * pinned & fenced.  When we do the allocation it's too early
15541          * for this.
15542          */
15543         for_each_crtc(dev, c) {
15544                 obj = intel_fb_obj(c->primary->fb);
15545                 if (obj == NULL)
15546                         continue;
15547
15548                 mutex_lock(&dev->struct_mutex);
15549                 ret = intel_pin_and_fence_fb_obj(c->primary,
15550                                                  c->primary->fb,
15551                                                  c->primary->state,
15552                                                  NULL, NULL);
15553                 mutex_unlock(&dev->struct_mutex);
15554                 if (ret) {
15555                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15556                                   to_intel_crtc(c)->pipe);
15557                         drm_framebuffer_unreference(c->primary->fb);
15558                         c->primary->fb = NULL;
15559                         c->primary->crtc = c->primary->state->crtc = NULL;
15560                         update_state_fb(c->primary);
15561                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15562                 }
15563         }
15564
15565         intel_backlight_register(dev);
15566 }
15567
15568 void intel_connector_unregister(struct intel_connector *intel_connector)
15569 {
15570         struct drm_connector *connector = &intel_connector->base;
15571
15572         intel_panel_destroy_backlight(connector);
15573         drm_connector_unregister(connector);
15574 }
15575
15576 void intel_modeset_cleanup(struct drm_device *dev)
15577 {
15578         struct drm_i915_private *dev_priv = dev->dev_private;
15579         struct drm_connector *connector;
15580
15581         intel_disable_gt_powersave(dev);
15582
15583         intel_backlight_unregister(dev);
15584
15585         /*
15586          * Interrupts and polling as the first thing to avoid creating havoc.
15587          * Too much stuff here (turning of connectors, ...) would
15588          * experience fancy races otherwise.
15589          */
15590         intel_irq_uninstall(dev_priv);
15591
15592         /*
15593          * Due to the hpd irq storm handling the hotplug work can re-arm the
15594          * poll handlers. Hence disable polling after hpd handling is shut down.
15595          */
15596         drm_kms_helper_poll_fini(dev);
15597
15598         mutex_lock(&dev->struct_mutex);
15599
15600         intel_unregister_dsm_handler();
15601
15602         intel_fbc_disable(dev);
15603
15604         mutex_unlock(&dev->struct_mutex);
15605
15606         /* flush any delayed tasks or pending work */
15607         flush_scheduled_work();
15608
15609         /* destroy the backlight and sysfs files before encoders/connectors */
15610         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15611                 struct intel_connector *intel_connector;
15612
15613                 intel_connector = to_intel_connector(connector);
15614                 intel_connector->unregister(intel_connector);
15615         }
15616
15617         drm_mode_config_cleanup(dev);
15618
15619         intel_cleanup_overlay(dev);
15620
15621         mutex_lock(&dev->struct_mutex);
15622         intel_cleanup_gt_powersave(dev);
15623         mutex_unlock(&dev->struct_mutex);
15624 }
15625
15626 /*
15627  * Return which encoder is currently attached for connector.
15628  */
15629 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15630 {
15631         return &intel_attached_encoder(connector)->base;
15632 }
15633
15634 void intel_connector_attach_encoder(struct intel_connector *connector,
15635                                     struct intel_encoder *encoder)
15636 {
15637         connector->encoder = encoder;
15638         drm_mode_connector_attach_encoder(&connector->base,
15639                                           &encoder->base);
15640 }
15641
15642 /*
15643  * set vga decode state - true == enable VGA decode
15644  */
15645 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15646 {
15647         struct drm_i915_private *dev_priv = dev->dev_private;
15648         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15649         u16 gmch_ctrl;
15650
15651         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15652                 DRM_ERROR("failed to read control word\n");
15653                 return -EIO;
15654         }
15655
15656         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15657                 return 0;
15658
15659         if (state)
15660                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15661         else
15662                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15663
15664         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15665                 DRM_ERROR("failed to write control word\n");
15666                 return -EIO;
15667         }
15668
15669         return 0;
15670 }
15671
15672 struct intel_display_error_state {
15673
15674         u32 power_well_driver;
15675
15676         int num_transcoders;
15677
15678         struct intel_cursor_error_state {
15679                 u32 control;
15680                 u32 position;
15681                 u32 base;
15682                 u32 size;
15683         } cursor[I915_MAX_PIPES];
15684
15685         struct intel_pipe_error_state {
15686                 bool power_domain_on;
15687                 u32 source;
15688                 u32 stat;
15689         } pipe[I915_MAX_PIPES];
15690
15691         struct intel_plane_error_state {
15692                 u32 control;
15693                 u32 stride;
15694                 u32 size;
15695                 u32 pos;
15696                 u32 addr;
15697                 u32 surface;
15698                 u32 tile_offset;
15699         } plane[I915_MAX_PIPES];
15700
15701         struct intel_transcoder_error_state {
15702                 bool power_domain_on;
15703                 enum transcoder cpu_transcoder;
15704
15705                 u32 conf;
15706
15707                 u32 htotal;
15708                 u32 hblank;
15709                 u32 hsync;
15710                 u32 vtotal;
15711                 u32 vblank;
15712                 u32 vsync;
15713         } transcoder[4];
15714 };
15715
15716 struct intel_display_error_state *
15717 intel_display_capture_error_state(struct drm_device *dev)
15718 {
15719         struct drm_i915_private *dev_priv = dev->dev_private;
15720         struct intel_display_error_state *error;
15721         int transcoders[] = {
15722                 TRANSCODER_A,
15723                 TRANSCODER_B,
15724                 TRANSCODER_C,
15725                 TRANSCODER_EDP,
15726         };
15727         int i;
15728
15729         if (INTEL_INFO(dev)->num_pipes == 0)
15730                 return NULL;
15731
15732         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15733         if (error == NULL)
15734                 return NULL;
15735
15736         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15737                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15738
15739         for_each_pipe(dev_priv, i) {
15740                 error->pipe[i].power_domain_on =
15741                         __intel_display_power_is_enabled(dev_priv,
15742                                                          POWER_DOMAIN_PIPE(i));
15743                 if (!error->pipe[i].power_domain_on)
15744                         continue;
15745
15746                 error->cursor[i].control = I915_READ(CURCNTR(i));
15747                 error->cursor[i].position = I915_READ(CURPOS(i));
15748                 error->cursor[i].base = I915_READ(CURBASE(i));
15749
15750                 error->plane[i].control = I915_READ(DSPCNTR(i));
15751                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15752                 if (INTEL_INFO(dev)->gen <= 3) {
15753                         error->plane[i].size = I915_READ(DSPSIZE(i));
15754                         error->plane[i].pos = I915_READ(DSPPOS(i));
15755                 }
15756                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15757                         error->plane[i].addr = I915_READ(DSPADDR(i));
15758                 if (INTEL_INFO(dev)->gen >= 4) {
15759                         error->plane[i].surface = I915_READ(DSPSURF(i));
15760                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15761                 }
15762
15763                 error->pipe[i].source = I915_READ(PIPESRC(i));
15764
15765                 if (HAS_GMCH_DISPLAY(dev))
15766                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15767         }
15768
15769         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15770         if (HAS_DDI(dev_priv->dev))
15771                 error->num_transcoders++; /* Account for eDP. */
15772
15773         for (i = 0; i < error->num_transcoders; i++) {
15774                 enum transcoder cpu_transcoder = transcoders[i];
15775
15776                 error->transcoder[i].power_domain_on =
15777                         __intel_display_power_is_enabled(dev_priv,
15778                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15779                 if (!error->transcoder[i].power_domain_on)
15780                         continue;
15781
15782                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15783
15784                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15785                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15786                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15787                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15788                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15789                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15790                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15791         }
15792
15793         return error;
15794 }
15795
15796 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15797
15798 void
15799 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15800                                 struct drm_device *dev,
15801                                 struct intel_display_error_state *error)
15802 {
15803         struct drm_i915_private *dev_priv = dev->dev_private;
15804         int i;
15805
15806         if (!error)
15807                 return;
15808
15809         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15810         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15811                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15812                            error->power_well_driver);
15813         for_each_pipe(dev_priv, i) {
15814                 err_printf(m, "Pipe [%d]:\n", i);
15815                 err_printf(m, "  Power: %s\n",
15816                            error->pipe[i].power_domain_on ? "on" : "off");
15817                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15818                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15819
15820                 err_printf(m, "Plane [%d]:\n", i);
15821                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15822                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15823                 if (INTEL_INFO(dev)->gen <= 3) {
15824                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15825                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15826                 }
15827                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15828                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15829                 if (INTEL_INFO(dev)->gen >= 4) {
15830                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15831                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15832                 }
15833
15834                 err_printf(m, "Cursor [%d]:\n", i);
15835                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15836                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15837                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15838         }
15839
15840         for (i = 0; i < error->num_transcoders; i++) {
15841                 err_printf(m, "CPU transcoder: %c\n",
15842                            transcoder_name(error->transcoder[i].cpu_transcoder));
15843                 err_printf(m, "  Power: %s\n",
15844                            error->transcoder[i].power_domain_on ? "on" : "off");
15845                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15846                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15847                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15848                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15849                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15850                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15851                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15852         }
15853 }
15854
15855 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15856 {
15857         struct intel_crtc *crtc;
15858
15859         for_each_intel_crtc(dev, crtc) {
15860                 struct intel_unpin_work *work;
15861
15862                 spin_lock_irq(&dev->event_lock);
15863
15864                 work = crtc->unpin_work;
15865
15866                 if (work && work->event &&
15867                     work->event->base.file_priv == file) {
15868                         kfree(work->event);
15869                         work->event = NULL;
15870                 }
15871
15872                 spin_unlock_irq(&dev->event_lock);
15873         }
15874 }