drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 /* Primary plane formats for gen <= 3 */
  53 static const uint32_t i8xx_primary_formats[] = {
  54         DRM_FORMAT_C8,
  55         DRM_FORMAT_RGB565,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_XRGB8888,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t i965_primary_formats[] = {
  62         DRM_FORMAT_C8,
  63         DRM_FORMAT_RGB565,
  64         DRM_FORMAT_XRGB8888,
  65         DRM_FORMAT_XBGR8888,
  66         DRM_FORMAT_XRGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68 };
  69
  70 static const uint64_t i9xx_format_modifiers[] = {
  71         I915_FORMAT_MOD_X_TILED,
  72         DRM_FORMAT_MOD_LINEAR,
  73         DRM_FORMAT_MOD_INVALID
  74 };
  75
  76 static const uint32_t skl_primary_formats[] = {
  77         DRM_FORMAT_C8,
  78         DRM_FORMAT_RGB565,
  79         DRM_FORMAT_XRGB8888,
  80         DRM_FORMAT_XBGR8888,
  81         DRM_FORMAT_ARGB8888,
  82         DRM_FORMAT_ABGR8888,
  83         DRM_FORMAT_XRGB2101010,
  84         DRM_FORMAT_XBGR2101010,
  85         DRM_FORMAT_YUYV,
  86         DRM_FORMAT_YVYU,
  87         DRM_FORMAT_UYVY,
  88         DRM_FORMAT_VYUY,
  89 };
  90
  91 static const uint64_t skl_format_modifiers_noccs[] = {
  92         I915_FORMAT_MOD_Yf_TILED,
  93         I915_FORMAT_MOD_Y_TILED,
  94         I915_FORMAT_MOD_X_TILED,
  95         DRM_FORMAT_MOD_LINEAR,
  96         DRM_FORMAT_MOD_INVALID
  97 };
  98
  99 static const uint64_t skl_format_modifiers_ccs[] = {
 100         I915_FORMAT_MOD_Yf_TILED_CCS,
 101         I915_FORMAT_MOD_Y_TILED_CCS,
 102         I915_FORMAT_MOD_Yf_TILED,
 103         I915_FORMAT_MOD_Y_TILED,
 104         I915_FORMAT_MOD_X_TILED,
 105         DRM_FORMAT_MOD_LINEAR,
 106         DRM_FORMAT_MOD_INVALID
 107 };
 108
 109 /* Cursor formats */
 110 static const uint32_t intel_cursor_formats[] = {
 111         DRM_FORMAT_ARGB8888,
 112 };
 113
 114 static const uint64_t cursor_format_modifiers[] = {
 115         DRM_FORMAT_MOD_LINEAR,
 116         DRM_FORMAT_MOD_INVALID
 117 };
 118
 119 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 120                                 struct intel_crtc_state *pipe_config);
 121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 122                                    struct intel_crtc_state *pipe_config);
 123
 124 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 125                                   struct drm_i915_gem_object *obj,
 126                                   struct drm_mode_fb_cmd2 *mode_cmd);
 127 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 128 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 129 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 130 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 131                                          struct intel_link_m_n *m_n,
 132                                          struct intel_link_m_n *m2_n2);
 133 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 134 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 135 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 136 static void vlv_prepare_pll(struct intel_crtc *crtc,
 137                             const struct intel_crtc_state *pipe_config);
 138 static void chv_prepare_pll(struct intel_crtc *crtc,
 139                             const struct intel_crtc_state *pipe_config);
 140 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 141 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 142 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 143                                     struct intel_crtc_state *crtc_state);
 144 static void skylake_pfit_enable(struct intel_crtc *crtc);
 145 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 146 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 147 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 148                                          struct drm_modeset_acquire_ctx *ctx);
 149 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 150
 151 struct intel_limit {
 152         struct {
 153                 int min, max;
 154         } dot, vco, n, m, m1, m2, p, p1;
 155
 156         struct {
 157                 int dot_limit;
 158                 int p2_slow, p2_fast;
 159         } p2;
 160 };
 161
 162 /* returns HPLL frequency in kHz */
 163 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 164 {
 165         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 166
 167         /* Obtain SKU information */
 168         mutex_lock(&dev_priv->sb_lock);
 169         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 170                 CCK_FUSE_HPLL_FREQ_MASK;
 171         mutex_unlock(&dev_priv->sb_lock);
 172
 173         return vco_freq[hpll_freq] * 1000;
 174 }
 175
 176 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 177                       const char *name, u32 reg, int ref_freq)
 178 {
 179         u32 val;
 180         int divider;
 181
 182         mutex_lock(&dev_priv->sb_lock);
 183         val = vlv_cck_read(dev_priv, reg);
 184         mutex_unlock(&dev_priv->sb_lock);
 185
 186         divider = val & CCK_FREQUENCY_VALUES;
 187
 188         WARN((val & CCK_FREQUENCY_STATUS) !=
 189              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 190              "%s change in progress\n", name);
 191
 192         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 193 }
 194
 195 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 196                            const char *name, u32 reg)
 197 {
 198         if (dev_priv->hpll_freq == 0)
 199                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 200
 201         return vlv_get_cck_clock(dev_priv, name, reg,
 202                                  dev_priv->hpll_freq);
 203 }
 204
 205 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 206 {
 207         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 208                 return;
 209
 210         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 211                                                       CCK_CZ_CLOCK_CONTROL);
 212
 213         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 214 }
 215
 216 static inline u32 /* units of 100MHz */
 217 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 218                     const struct intel_crtc_state *pipe_config)
 219 {
 220         if (HAS_DDI(dev_priv))
 221                 return pipe_config->port_clock; /* SPLL */
 222         else if (IS_GEN5(dev_priv))
 223                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 224         else
 225                 return 270000;
 226 }
 227
 228 static const struct intel_limit intel_limits_i8xx_dac = {
 229         .dot = { .min = 25000, .max = 350000 },
 230         .vco = { .min = 908000, .max = 1512000 },
 231         .n = { .min = 2, .max = 16 },
 232         .m = { .min = 96, .max = 140 },
 233         .m1 = { .min = 18, .max = 26 },
 234         .m2 = { .min = 6, .max = 16 },
 235         .p = { .min = 4, .max = 128 },
 236         .p1 = { .min = 2, .max = 33 },
 237         .p2 = { .dot_limit = 165000,
 238                 .p2_slow = 4, .p2_fast = 2 },
 239 };
 240
 241 static const struct intel_limit intel_limits_i8xx_dvo = {
 242         .dot = { .min = 25000, .max = 350000 },
 243         .vco = { .min = 908000, .max = 1512000 },
 244         .n = { .min = 2, .max = 16 },
 245         .m = { .min = 96, .max = 140 },
 246         .m1 = { .min = 18, .max = 26 },
 247         .m2 = { .min = 6, .max = 16 },
 248         .p = { .min = 4, .max = 128 },
 249         .p1 = { .min = 2, .max = 33 },
 250         .p2 = { .dot_limit = 165000,
 251                 .p2_slow = 4, .p2_fast = 4 },
 252 };
 253
 254 static const struct intel_limit intel_limits_i8xx_lvds = {
 255         .dot = { .min = 25000, .max = 350000 },
 256         .vco = { .min = 908000, .max = 1512000 },
 257         .n = { .min = 2, .max = 16 },
 258         .m = { .min = 96, .max = 140 },
 259         .m1 = { .min = 18, .max = 26 },
 260         .m2 = { .min = 6, .max = 16 },
 261         .p = { .min = 4, .max = 128 },
 262         .p1 = { .min = 1, .max = 6 },
 263         .p2 = { .dot_limit = 165000,
 264                 .p2_slow = 14, .p2_fast = 7 },
 265 };
 266
 267 static const struct intel_limit intel_limits_i9xx_sdvo = {
 268         .dot = { .min = 20000, .max = 400000 },
 269         .vco = { .min = 1400000, .max = 2800000 },
 270         .n = { .min = 1, .max = 6 },
 271         .m = { .min = 70, .max = 120 },
 272         .m1 = { .min = 8, .max = 18 },
 273         .m2 = { .min = 3, .max = 7 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const struct intel_limit intel_limits_i9xx_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1400000, .max = 2800000 },
 283         .n = { .min = 1, .max = 6 },
 284         .m = { .min = 70, .max = 120 },
 285         .m1 = { .min = 8, .max = 18 },
 286         .m2 = { .min = 3, .max = 7 },
 287         .p = { .min = 7, .max = 98 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 7 },
 291 };
 292
 293
 294 static const struct intel_limit intel_limits_g4x_sdvo = {
 295         .dot = { .min = 25000, .max = 270000 },
 296         .vco = { .min = 1750000, .max = 3500000},
 297         .n = { .min = 1, .max = 4 },
 298         .m = { .min = 104, .max = 138 },
 299         .m1 = { .min = 17, .max = 23 },
 300         .m2 = { .min = 5, .max = 11 },
 301         .p = { .min = 10, .max = 30 },
 302         .p1 = { .min = 1, .max = 3},
 303         .p2 = { .dot_limit = 270000,
 304                 .p2_slow = 10,
 305                 .p2_fast = 10
 306         },
 307 };
 308
 309 static const struct intel_limit intel_limits_g4x_hdmi = {
 310         .dot = { .min = 22000, .max = 400000 },
 311         .vco = { .min = 1750000, .max = 3500000},
 312         .n = { .min = 1, .max = 4 },
 313         .m = { .min = 104, .max = 138 },
 314         .m1 = { .min = 16, .max = 23 },
 315         .m2 = { .min = 5, .max = 11 },
 316         .p = { .min = 5, .max = 80 },
 317         .p1 = { .min = 1, .max = 8},
 318         .p2 = { .dot_limit = 165000,
 319                 .p2_slow = 10, .p2_fast = 5 },
 320 };
 321
 322 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 323         .dot = { .min = 20000, .max = 115000 },
 324         .vco = { .min = 1750000, .max = 3500000 },
 325         .n = { .min = 1, .max = 3 },
 326         .m = { .min = 104, .max = 138 },
 327         .m1 = { .min = 17, .max = 23 },
 328         .m2 = { .min = 5, .max = 11 },
 329         .p = { .min = 28, .max = 112 },
 330         .p1 = { .min = 2, .max = 8 },
 331         .p2 = { .dot_limit = 0,
 332                 .p2_slow = 14, .p2_fast = 14
 333         },
 334 };
 335
 336 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 337         .dot = { .min = 80000, .max = 224000 },
 338         .vco = { .min = 1750000, .max = 3500000 },
 339         .n = { .min = 1, .max = 3 },
 340         .m = { .min = 104, .max = 138 },
 341         .m1 = { .min = 17, .max = 23 },
 342         .m2 = { .min = 5, .max = 11 },
 343         .p = { .min = 14, .max = 42 },
 344         .p1 = { .min = 2, .max = 6 },
 345         .p2 = { .dot_limit = 0,
 346                 .p2_slow = 7, .p2_fast = 7
 347         },
 348 };
 349
 350 static const struct intel_limit intel_limits_pineview_sdvo = {
 351         .dot = { .min = 20000, .max = 400000},
 352         .vco = { .min = 1700000, .max = 3500000 },
 353         /* Pineview's Ncounter is a ring counter */
 354         .n = { .min = 3, .max = 6 },
 355         .m = { .min = 2, .max = 256 },
 356         /* Pineview only has one combined m divider, which we treat as m2. */
 357         .m1 = { .min = 0, .max = 0 },
 358         .m2 = { .min = 0, .max = 254 },
 359         .p = { .min = 5, .max = 80 },
 360         .p1 = { .min = 1, .max = 8 },
 361         .p2 = { .dot_limit = 200000,
 362                 .p2_slow = 10, .p2_fast = 5 },
 363 };
 364
 365 static const struct intel_limit intel_limits_pineview_lvds = {
 366         .dot = { .min = 20000, .max = 400000 },
 367         .vco = { .min = 1700000, .max = 3500000 },
 368         .n = { .min = 3, .max = 6 },
 369         .m = { .min = 2, .max = 256 },
 370         .m1 = { .min = 0, .max = 0 },
 371         .m2 = { .min = 0, .max = 254 },
 372         .p = { .min = 7, .max = 112 },
 373         .p1 = { .min = 1, .max = 8 },
 374         .p2 = { .dot_limit = 112000,
 375                 .p2_slow = 14, .p2_fast = 14 },
 376 };
 377
 378 /* Ironlake / Sandybridge
 379  *
 380  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 381  * the range value for them is (actual_value - 2).
 382  */
 383 static const struct intel_limit intel_limits_ironlake_dac = {
 384         .dot = { .min = 25000, .max = 350000 },
 385         .vco = { .min = 1760000, .max = 3510000 },
 386         .n = { .min = 1, .max = 5 },
 387         .m = { .min = 79, .max = 127 },
 388         .m1 = { .min = 12, .max = 22 },
 389         .m2 = { .min = 5, .max = 9 },
 390         .p = { .min = 5, .max = 80 },
 391         .p1 = { .min = 1, .max = 8 },
 392         .p2 = { .dot_limit = 225000,
 393                 .p2_slow = 10, .p2_fast = 5 },
 394 };
 395
 396 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 397         .dot = { .min = 25000, .max = 350000 },
 398         .vco = { .min = 1760000, .max = 3510000 },
 399         .n = { .min = 1, .max = 3 },
 400         .m = { .min = 79, .max = 118 },
 401         .m1 = { .min = 12, .max = 22 },
 402         .m2 = { .min = 5, .max = 9 },
 403         .p = { .min = 28, .max = 112 },
 404         .p1 = { .min = 2, .max = 8 },
 405         .p2 = { .dot_limit = 225000,
 406                 .p2_slow = 14, .p2_fast = 14 },
 407 };
 408
 409 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 410         .dot = { .min = 25000, .max = 350000 },
 411         .vco = { .min = 1760000, .max = 3510000 },
 412         .n = { .min = 1, .max = 3 },
 413         .m = { .min = 79, .max = 127 },
 414         .m1 = { .min = 12, .max = 22 },
 415         .m2 = { .min = 5, .max = 9 },
 416         .p = { .min = 14, .max = 56 },
 417         .p1 = { .min = 2, .max = 8 },
 418         .p2 = { .dot_limit = 225000,
 419                 .p2_slow = 7, .p2_fast = 7 },
 420 };
 421
 422 /* LVDS 100mhz refclk limits. */
 423 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 424         .dot = { .min = 25000, .max = 350000 },
 425         .vco = { .min = 1760000, .max = 3510000 },
 426         .n = { .min = 1, .max = 2 },
 427         .m = { .min = 79, .max = 126 },
 428         .m1 = { .min = 12, .max = 22 },
 429         .m2 = { .min = 5, .max = 9 },
 430         .p = { .min = 28, .max = 112 },
 431         .p1 = { .min = 2, .max = 8 },
 432         .p2 = { .dot_limit = 225000,
 433                 .p2_slow = 14, .p2_fast = 14 },
 434 };
 435
 436 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 437         .dot = { .min = 25000, .max = 350000 },
 438         .vco = { .min = 1760000, .max = 3510000 },
 439         .n = { .min = 1, .max = 3 },
 440         .m = { .min = 79, .max = 126 },
 441         .m1 = { .min = 12, .max = 22 },
 442         .m2 = { .min = 5, .max = 9 },
 443         .p = { .min = 14, .max = 42 },
 444         .p1 = { .min = 2, .max = 6 },
 445         .p2 = { .dot_limit = 225000,
 446                 .p2_slow = 7, .p2_fast = 7 },
 447 };
 448
 449 static const struct intel_limit intel_limits_vlv = {
 450          /*
 451           * These are the data rate limits (measured in fast clocks)
 452           * since those are the strictest limits we have. The fast
 453           * clock and actual rate limits are more relaxed, so checking
 454           * them would make no difference.
 455           */
 456         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 457         .vco = { .min = 4000000, .max = 6000000 },
 458         .n = { .min = 1, .max = 7 },
 459         .m1 = { .min = 2, .max = 3 },
 460         .m2 = { .min = 11, .max = 156 },
 461         .p1 = { .min = 2, .max = 3 },
 462         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 463 };
 464
 465 static const struct intel_limit intel_limits_chv = {
 466         /*
 467          * These are the data rate limits (measured in fast clocks)
 468          * since those are the strictest limits we have.  The fast
 469          * clock and actual rate limits are more relaxed, so checking
 470          * them would make no difference.
 471          */
 472         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 473         .vco = { .min = 4800000, .max = 6480000 },
 474         .n = { .min = 1, .max = 1 },
 475         .m1 = { .min = 2, .max = 2 },
 476         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 477         .p1 = { .min = 2, .max = 4 },
 478         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 479 };
 480
 481 static const struct intel_limit intel_limits_bxt = {
 482         /* FIXME: find real dot limits */
 483         .dot = { .min = 0, .max = INT_MAX },
 484         .vco = { .min = 4800000, .max = 6700000 },
 485         .n = { .min = 1, .max = 1 },
 486         .m1 = { .min = 2, .max = 2 },
 487         /* FIXME: find real m2 limits */
 488         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 489         .p1 = { .min = 2, .max = 4 },
 490         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 491 };
 492
 493 static bool
 494 needs_modeset(struct drm_crtc_state *state)
 495 {
 496         return drm_atomic_crtc_needs_modeset(state);
 497 }
 498
 499 /*
 500  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 501  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 502  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 503  * The helpers' return value is the rate of the clock that is fed to the
 504  * display engine's pipe which can be the above fast dot clock rate or a
 505  * divided-down version of it.
 506  */
 507 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 509 {
 510         clock->m = clock->m2 + 2;
 511         clock->p = clock->p1 * clock->p2;
 512         if (WARN_ON(clock->n == 0 || clock->p == 0))
 513                 return 0;
 514         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 515         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 516
 517         return clock->dot;
 518 }
 519
 520 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 521 {
 522         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 523 }
 524
 525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 526 {
 527         clock->m = i9xx_dpll_compute_m(clock);
 528         clock->p = clock->p1 * clock->p2;
 529         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 530                 return 0;
 531         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot;
 535 }
 536
 537 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 538 {
 539         clock->m = clock->m1 * clock->m2;
 540         clock->p = clock->p1 * clock->p2;
 541         if (WARN_ON(clock->n == 0 || clock->p == 0))
 542                 return 0;
 543         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 544         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 545
 546         return clock->dot / 5;
 547 }
 548
 549 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 550 {
 551         clock->m = clock->m1 * clock->m2;
 552         clock->p = clock->p1 * clock->p2;
 553         if (WARN_ON(clock->n == 0 || clock->p == 0))
 554                 return 0;
 555         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 556                         clock->n << 22);
 557         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 558
 559         return clock->dot / 5;
 560 }
 561
 562 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 563 /**
 564  * Returns whether the given set of divisors are valid for a given refclk with
 565  * the given connectors.
 566  */
 567
 568 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 569                                const struct intel_limit *limit,
 570                                const struct dpll *clock)
 571 {
 572         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 573                 INTELPllInvalid("n out of range\n");
 574         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 575                 INTELPllInvalid("p1 out of range\n");
 576         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 577                 INTELPllInvalid("m2 out of range\n");
 578         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 579                 INTELPllInvalid("m1 out of range\n");
 580
 581         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 582             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 583                 if (clock->m1 <= clock->m2)
 584                         INTELPllInvalid("m1 <= m2\n");
 585
 586         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 587             !IS_GEN9_LP(dev_priv)) {
 588                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 589                         INTELPllInvalid("p out of range\n");
 590                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 591                         INTELPllInvalid("m out of range\n");
 592         }
 593
 594         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 595                 INTELPllInvalid("vco out of range\n");
 596         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 597          * connector, etc., rather than just a single range.
 598          */
 599         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 600                 INTELPllInvalid("dot out of range\n");
 601
 602         return true;
 603 }
 604
 605 static int
 606 i9xx_select_p2_div(const struct intel_limit *limit,
 607                    const struct intel_crtc_state *crtc_state,
 608                    int target)
 609 {
 610         struct drm_device *dev = crtc_state->base.crtc->dev;
 611
 612         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 613                 /*
 614                  * For LVDS just rely on its current settings for dual-channel.
 615                  * We haven't figured out how to reliably set up different
 616                  * single/dual channel state, if we even can.
 617                  */
 618                 if (intel_is_dual_link_lvds(dev))
 619                         return limit->p2.p2_fast;
 620                 else
 621                         return limit->p2.p2_slow;
 622         } else {
 623                 if (target < limit->p2.dot_limit)
 624                         return limit->p2.p2_slow;
 625                 else
 626                         return limit->p2.p2_fast;
 627         }
 628 }
 629
 630 /*
 631  * Returns a set of divisors for the desired target clock with the given
 632  * refclk, or FALSE.  The returned values represent the clock equation:
 633  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 634  *
 635  * Target and reference clocks are specified in kHz.
 636  *
 637  * If match_clock is provided, then best_clock P divider must match the P
 638  * divider from @match_clock used for LVDS downclocking.
 639  */
 640 static bool
 641 i9xx_find_best_dpll(const struct intel_limit *limit,
 642                     struct intel_crtc_state *crtc_state,
 643                     int target, int refclk, struct dpll *match_clock,
 644                     struct dpll *best_clock)
 645 {
 646         struct drm_device *dev = crtc_state->base.crtc->dev;
 647         struct dpll clock;
 648         int err = target;
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651
 652         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         if (clock.m2 >= clock.m1)
 659                                 break;
 660                         for (clock.n = limit->n.min;
 661                              clock.n <= limit->n.max; clock.n++) {
 662                                 for (clock.p1 = limit->p1.min;
 663                                         clock.p1 <= limit->p1.max; clock.p1++) {
 664                                         int this_err;
 665
 666                                         i9xx_calc_dpll_params(refclk, &clock);
 667                                         if (!intel_PLL_is_valid(to_i915(dev),
 668                                                                 limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 /*
 689  * Returns a set of divisors for the desired target clock with the given
 690  * refclk, or FALSE.  The returned values represent the clock equation:
 691  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 692  *
 693  * Target and reference clocks are specified in kHz.
 694  *
 695  * If match_clock is provided, then best_clock P divider must match the P
 696  * divider from @match_clock used for LVDS downclocking.
 697  */
 698 static bool
 699 pnv_find_best_dpll(const struct intel_limit *limit,
 700                    struct intel_crtc_state *crtc_state,
 701                    int target, int refclk, struct dpll *match_clock,
 702                    struct dpll *best_clock)
 703 {
 704         struct drm_device *dev = crtc_state->base.crtc->dev;
 705         struct dpll clock;
 706         int err = target;
 707
 708         memset(best_clock, 0, sizeof(*best_clock));
 709
 710         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 711
 712         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 713              clock.m1++) {
 714                 for (clock.m2 = limit->m2.min;
 715                      clock.m2 <= limit->m2.max; clock.m2++) {
 716                         for (clock.n = limit->n.min;
 717                              clock.n <= limit->n.max; clock.n++) {
 718                                 for (clock.p1 = limit->p1.min;
 719                                         clock.p1 <= limit->p1.max; clock.p1++) {
 720                                         int this_err;
 721
 722                                         pnv_calc_dpll_params(refclk, &clock);
 723                                         if (!intel_PLL_is_valid(to_i915(dev),
 724                                                                 limit,
 725                                                                 &clock))
 726                                                 continue;
 727                                         if (match_clock &&
 728                                             clock.p != match_clock->p)
 729                                                 continue;
 730
 731                                         this_err = abs(clock.dot - target);
 732                                         if (this_err < err) {
 733                                                 *best_clock = clock;
 734                                                 err = this_err;
 735                                         }
 736                                 }
 737                         }
 738                 }
 739         }
 740
 741         return (err != target);
 742 }
 743
 744 /*
 745  * Returns a set of divisors for the desired target clock with the given
 746  * refclk, or FALSE.  The returned values represent the clock equation:
 747  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 748  *
 749  * Target and reference clocks are specified in kHz.
 750  *
 751  * If match_clock is provided, then best_clock P divider must match the P
 752  * divider from @match_clock used for LVDS downclocking.
 753  */
 754 static bool
 755 g4x_find_best_dpll(const struct intel_limit *limit,
 756                    struct intel_crtc_state *crtc_state,
 757                    int target, int refclk, struct dpll *match_clock,
 758                    struct dpll *best_clock)
 759 {
 760         struct drm_device *dev = crtc_state->base.crtc->dev;
 761         struct dpll clock;
 762         int max_n;
 763         bool found = false;
 764         /* approximately equals target * 0.00585 */
 765         int err_most = (target >> 8) + (target >> 9);
 766
 767         memset(best_clock, 0, sizeof(*best_clock));
 768
 769         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 770
 771         max_n = limit->n.max;
 772         /* based on hardware requirement, prefer smaller n to precision */
 773         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 774                 /* based on hardware requirement, prefere larger m1,m2 */
 775                 for (clock.m1 = limit->m1.max;
 776                      clock.m1 >= limit->m1.min; clock.m1--) {
 777                         for (clock.m2 = limit->m2.max;
 778                              clock.m2 >= limit->m2.min; clock.m2--) {
 779                                 for (clock.p1 = limit->p1.max;
 780                                      clock.p1 >= limit->p1.min; clock.p1--) {
 781                                         int this_err;
 782
 783                                         i9xx_calc_dpll_params(refclk, &clock);
 784                                         if (!intel_PLL_is_valid(to_i915(dev),
 785                                                                 limit,
 786                                                                 &clock))
 787                                                 continue;
 788
 789                                         this_err = abs(clock.dot - target);
 790                                         if (this_err < err_most) {
 791                                                 *best_clock = clock;
 792                                                 err_most = this_err;
 793                                                 max_n = clock.n;
 794                                                 found = true;
 795                                         }
 796                                 }
 797                         }
 798                 }
 799         }
 800         return found;
 801 }
 802
 803 /*
 804  * Check if the calculated PLL configuration is more optimal compared to the
 805  * best configuration and error found so far. Return the calculated error.
 806  */
 807 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 808                                const struct dpll *calculated_clock,
 809                                const struct dpll *best_clock,
 810                                unsigned int best_error_ppm,
 811                                unsigned int *error_ppm)
 812 {
 813         /*
 814          * For CHV ignore the error and consider only the P value.
 815          * Prefer a bigger P value based on HW requirements.
 816          */
 817         if (IS_CHERRYVIEW(to_i915(dev))) {
 818                 *error_ppm = 0;
 819
 820                 return calculated_clock->p > best_clock->p;
 821         }
 822
 823         if (WARN_ON_ONCE(!target_freq))
 824                 return false;
 825
 826         *error_ppm = div_u64(1000000ULL *
 827                                 abs(target_freq - calculated_clock->dot),
 828                              target_freq);
 829         /*
 830          * Prefer a better P value over a better (smaller) error if the error
 831          * is small. Ensure this preference for future configurations too by
 832          * setting the error to 0.
 833          */
 834         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 835                 *error_ppm = 0;
 836
 837                 return true;
 838         }
 839
 840         return *error_ppm + 10 < best_error_ppm;
 841 }
 842
 843 /*
 844  * Returns a set of divisors for the desired target clock with the given
 845  * refclk, or FALSE.  The returned values represent the clock equation:
 846  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 847  */
 848 static bool
 849 vlv_find_best_dpll(const struct intel_limit *limit,
 850                    struct intel_crtc_state *crtc_state,
 851                    int target, int refclk, struct dpll *match_clock,
 852                    struct dpll *best_clock)
 853 {
 854         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 855         struct drm_device *dev = crtc->base.dev;
 856         struct dpll clock;
 857         unsigned int bestppm = 1000000;
 858         /* min update 19.2 MHz */
 859         int max_n = min(limit->n.max, refclk / 19200);
 860         bool found = false;
 861
 862         target *= 5; /* fast clock */
 863
 864         memset(best_clock, 0, sizeof(*best_clock));
 865
 866         /* based on hardware requirement, prefer smaller n to precision */
 867         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 868                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 869                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 870                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 871                                 clock.p = clock.p1 * clock.p2;
 872                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 873                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 874                                         unsigned int ppm;
 875
 876                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 877                                                                      refclk * clock.m1);
 878
 879                                         vlv_calc_dpll_params(refclk, &clock);
 880
 881                                         if (!intel_PLL_is_valid(to_i915(dev),
 882                                                                 limit,
 883                                                                 &clock))
 884                                                 continue;
 885
 886                                         if (!vlv_PLL_is_optimal(dev, target,
 887                                                                 &clock,
 888                                                                 best_clock,
 889                                                                 bestppm, &ppm))
 890                                                 continue;
 891
 892                                         *best_clock = clock;
 893                                         bestppm = ppm;
 894                                         found = true;
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         return found;
 901 }
 902
 903 /*
 904  * Returns a set of divisors for the desired target clock with the given
 905  * refclk, or FALSE.  The returned values represent the clock equation:
 906  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 907  */
 908 static bool
 909 chv_find_best_dpll(const struct intel_limit *limit,
 910                    struct intel_crtc_state *crtc_state,
 911                    int target, int refclk, struct dpll *match_clock,
 912                    struct dpll *best_clock)
 913 {
 914         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 915         struct drm_device *dev = crtc->base.dev;
 916         unsigned int best_error_ppm;
 917         struct dpll clock;
 918         uint64_t m2;
 919         int found = false;
 920
 921         memset(best_clock, 0, sizeof(*best_clock));
 922         best_error_ppm = 1000000;
 923
 924         /*
 925          * Based on hardware doc, the n always set to 1, and m1 always
 926          * set to 2.  If requires to support 200Mhz refclk, we need to
 927          * revisit this because n may not 1 anymore.
 928          */
 929         clock.n = 1, clock.m1 = 2;
 930         target *= 5;    /* fast clock */
 931
 932         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 933                 for (clock.p2 = limit->p2.p2_fast;
 934                                 clock.p2 >= limit->p2.p2_slow;
 935                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 936                         unsigned int error_ppm;
 937
 938                         clock.p = clock.p1 * clock.p2;
 939
 940                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 941                                         clock.n) << 22, refclk * clock.m1);
 942
 943                         if (m2 > INT_MAX/clock.m1)
 944                                 continue;
 945
 946                         clock.m2 = m2;
 947
 948                         chv_calc_dpll_params(refclk, &clock);
 949
 950                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 951                                 continue;
 952
 953                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 954                                                 best_error_ppm, &error_ppm))
 955                                 continue;
 956
 957                         *best_clock = clock;
 958                         best_error_ppm = error_ppm;
 959                         found = true;
 960                 }
 961         }
 962
 963         return found;
 964 }
 965
 966 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 967                         struct dpll *best_clock)
 968 {
 969         int refclk = 100000;
 970         const struct intel_limit *limit = &intel_limits_bxt;
 971
 972         return chv_find_best_dpll(limit, crtc_state,
 973                                   target_clock, refclk, NULL, best_clock);
 974 }
 975
 976 bool intel_crtc_active(struct intel_crtc *crtc)
 977 {
 978         /* Be paranoid as we can arrive here with only partial
 979          * state retrieved from the hardware during setup.
 980          *
 981          * We can ditch the adjusted_mode.crtc_clock check as soon
 982          * as Haswell has gained clock readout/fastboot support.
 983          *
 984          * We can ditch the crtc->primary->fb check as soon as we can
 985          * properly reconstruct framebuffers.
 986          *
 987          * FIXME: The intel_crtc->active here should be switched to
 988          * crtc->state->active once we have proper CRTC states wired up
 989          * for atomic.
 990          */
 991         return crtc->active && crtc->base.primary->state->fb &&
 992                 crtc->config->base.adjusted_mode.crtc_clock;
 993 }
 994
 995 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 996                                              enum pipe pipe)
 997 {
 998         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 999
1000         return crtc->config->cpu_transcoder;
1001 }
1002
1003 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
1004 {
1005         i915_reg_t reg = PIPEDSL(pipe);
1006         u32 line1, line2;
1007         u32 line_mask;
1008
1009         if (IS_GEN2(dev_priv))
1010                 line_mask = DSL_LINEMASK_GEN2;
1011         else
1012                 line_mask = DSL_LINEMASK_GEN3;
1013
1014         line1 = I915_READ(reg) & line_mask;
1015         msleep(5);
1016         line2 = I915_READ(reg) & line_mask;
1017
1018         return line1 == line2;
1019 }
1020
1021 /*
1022  * intel_wait_for_pipe_off - wait for pipe to turn off
1023  * @crtc: crtc whose pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * On Gen4 and above:
1030  *   wait for the pipe register state bit to turn off
1031  *
1032  * Otherwise:
1033  *   wait for the display line value to settle (it usually
1034  *   ends up stopping at the start of the next frame).
1035  *
1036  */
1037 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1040         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1041         enum pipe pipe = crtc->pipe;
1042
1043         if (INTEL_GEN(dev_priv) >= 4) {
1044                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1045
1046                 /* Wait for the Pipe State to go off */
1047                 if (intel_wait_for_register(dev_priv,
1048                                             reg, I965_PIPECONF_ACTIVE, 0,
1049                                             100))
1050                         WARN(1, "pipe_off wait timed out\n");
1051         } else {
1052                 /* Wait for the display line to settle */
1053                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1054                         WARN(1, "pipe_off wait timed out\n");
1055         }
1056 }
1057
1058 /* Only for pre-ILK configs */
1059 void assert_pll(struct drm_i915_private *dev_priv,
1060                 enum pipe pipe, bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         val = I915_READ(DPLL(pipe));
1066         cur_state = !!(val & DPLL_VCO_ENABLE);
1067         I915_STATE_WARN(cur_state != state,
1068              "PLL state assertion failure (expected %s, current %s)\n",
1069                         onoff(state), onoff(cur_state));
1070 }
1071
1072 /* XXX: the dsi pll is shared between MIPI DSI ports */
1073 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1074 {
1075         u32 val;
1076         bool cur_state;
1077
1078         mutex_lock(&dev_priv->sb_lock);
1079         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1080         mutex_unlock(&dev_priv->sb_lock);
1081
1082         cur_state = val & DSI_PLL_VCO_EN;
1083         I915_STATE_WARN(cur_state != state,
1084              "DSI PLL state assertion failure (expected %s, current %s)\n",
1085                         onoff(state), onoff(cur_state));
1086 }
1087
1088 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1089                           enum pipe pipe, bool state)
1090 {
1091         bool cur_state;
1092         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093                                                                       pipe);
1094
1095         if (HAS_DDI(dev_priv)) {
1096                 /* DDI does not have a specific FDI_TX register */
1097                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1098                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1099         } else {
1100                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1101                 cur_state = !!(val & FDI_TX_ENABLE);
1102         }
1103         I915_STATE_WARN(cur_state != state,
1104              "FDI TX state assertion failure (expected %s, current %s)\n",
1105                         onoff(state), onoff(cur_state));
1106 }
1107 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1108 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1109
1110 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         u32 val;
1114         bool cur_state;
1115
1116         val = I915_READ(FDI_RX_CTL(pipe));
1117         cur_state = !!(val & FDI_RX_ENABLE);
1118         I915_STATE_WARN(cur_state != state,
1119              "FDI RX state assertion failure (expected %s, current %s)\n",
1120                         onoff(state), onoff(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126                                       enum pipe pipe)
1127 {
1128         u32 val;
1129
1130         /* ILK FDI PLL is always enabled */
1131         if (IS_GEN5(dev_priv))
1132                 return;
1133
1134         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135         if (HAS_DDI(dev_priv))
1136                 return;
1137
1138         val = I915_READ(FDI_TX_CTL(pipe));
1139         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1140 }
1141
1142 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1143                        enum pipe pipe, bool state)
1144 {
1145         u32 val;
1146         bool cur_state;
1147
1148         val = I915_READ(FDI_RX_CTL(pipe));
1149         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1150         I915_STATE_WARN(cur_state != state,
1151              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1152                         onoff(state), onoff(cur_state));
1153 }
1154
1155 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1156 {
1157         i915_reg_t pp_reg;
1158         u32 val;
1159         enum pipe panel_pipe = PIPE_A;
1160         bool locked = true;
1161
1162         if (WARN_ON(HAS_DDI(dev_priv)))
1163                 return;
1164
1165         if (HAS_PCH_SPLIT(dev_priv)) {
1166                 u32 port_sel;
1167
1168                 pp_reg = PP_CONTROL(0);
1169                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1170
1171                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1172                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1173                         panel_pipe = PIPE_B;
1174                 /* XXX: else fix for eDP */
1175         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1176                 /* presumably write lock depends on pipe, not port select */
1177                 pp_reg = PP_CONTROL(pipe);
1178                 panel_pipe = pipe;
1179         } else {
1180                 pp_reg = PP_CONTROL(0);
1181                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1182                         panel_pipe = PIPE_B;
1183         }
1184
1185         val = I915_READ(pp_reg);
1186         if (!(val & PANEL_POWER_ON) ||
1187             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1188                 locked = false;
1189
1190         I915_STATE_WARN(panel_pipe == pipe && locked,
1191              "panel assertion failure, pipe %c regs locked\n",
1192              pipe_name(pipe));
1193 }
1194
1195 static void assert_cursor(struct drm_i915_private *dev_priv,
1196                           enum pipe pipe, bool state)
1197 {
1198         bool cur_state;
1199
1200         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1201                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1202         else
1203                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1204
1205         I915_STATE_WARN(cur_state != state,
1206              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1207                         pipe_name(pipe), onoff(state), onoff(cur_state));
1208 }
1209 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1210 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1211
1212 void assert_pipe(struct drm_i915_private *dev_priv,
1213                  enum pipe pipe, bool state)
1214 {
1215         bool cur_state;
1216         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1217                                                                       pipe);
1218         enum intel_display_power_domain power_domain;
1219
1220         /* we keep both pipes enabled on 830 */
1221         if (IS_I830(dev_priv))
1222                 state = true;
1223
1224         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1225         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1226                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1227                 cur_state = !!(val & PIPECONF_ENABLE);
1228
1229                 intel_display_power_put(dev_priv, power_domain);
1230         } else {
1231                 cur_state = false;
1232         }
1233
1234         I915_STATE_WARN(cur_state != state,
1235              "pipe %c assertion failure (expected %s, current %s)\n",
1236                         pipe_name(pipe), onoff(state), onoff(cur_state));
1237 }
1238
1239 static void assert_plane(struct drm_i915_private *dev_priv,
1240                          enum plane plane, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(DSPCNTR(plane));
1246         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "plane %c assertion failure (expected %s, current %s)\n",
1249                         plane_name(plane), onoff(state), onoff(cur_state));
1250 }
1251
1252 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1253 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1254
1255 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1256                                    enum pipe pipe)
1257 {
1258         int i;
1259
1260         /* Primary planes are fixed to pipes on gen4+ */
1261         if (INTEL_GEN(dev_priv) >= 4) {
1262                 u32 val = I915_READ(DSPCNTR(pipe));
1263                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1264                      "plane %c assertion failure, should be disabled but not\n",
1265                      plane_name(pipe));
1266                 return;
1267         }
1268
1269         /* Need to check both planes against the pipe */
1270         for_each_pipe(dev_priv, i) {
1271                 u32 val = I915_READ(DSPCNTR(i));
1272                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1273                         DISPPLANE_SEL_PIPE_SHIFT;
1274                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1275                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1276                      plane_name(i), pipe_name(pipe));
1277         }
1278 }
1279
1280 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1281                                     enum pipe pipe)
1282 {
1283         int sprite;
1284
1285         if (INTEL_GEN(dev_priv) >= 9) {
1286                 for_each_sprite(dev_priv, pipe, sprite) {
1287                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1288                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1289                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1290                              sprite, pipe_name(pipe));
1291                 }
1292         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1293                 for_each_sprite(dev_priv, pipe, sprite) {
1294                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1295                         I915_STATE_WARN(val & SP_ENABLE,
1296                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                              sprite_name(pipe, sprite), pipe_name(pipe));
1298                 }
1299         } else if (INTEL_GEN(dev_priv) >= 7) {
1300                 u32 val = I915_READ(SPRCTL(pipe));
1301                 I915_STATE_WARN(val & SPRITE_ENABLE,
1302                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1303                      plane_name(pipe), pipe_name(pipe));
1304         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
1305                 u32 val = I915_READ(DVSCNTR(pipe));
1306                 I915_STATE_WARN(val & DVS_ENABLE,
1307                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1308                      plane_name(pipe), pipe_name(pipe));
1309         }
1310 }
1311
1312 static void assert_vblank_disabled(struct drm_crtc *crtc)
1313 {
1314         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1315                 drm_crtc_vblank_put(crtc);
1316 }
1317
1318 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1319                                     enum pipe pipe)
1320 {
1321         u32 val;
1322         bool enabled;
1323
1324         val = I915_READ(PCH_TRANSCONF(pipe));
1325         enabled = !!(val & TRANS_ENABLE);
1326         I915_STATE_WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv)) {
1338                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1339                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1340                         return false;
1341         } else if (IS_CHERRYVIEW(dev_priv)) {
1342                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1343                         return false;
1344         } else {
1345                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1346                         return false;
1347         }
1348         return true;
1349 }
1350
1351 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1352                               enum pipe pipe, u32 val)
1353 {
1354         if ((val & SDVO_ENABLE) == 0)
1355                 return false;
1356
1357         if (HAS_PCH_CPT(dev_priv)) {
1358                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1359                         return false;
1360         } else if (IS_CHERRYVIEW(dev_priv)) {
1361                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & LVDS_PORT_EN) == 0)
1374                 return false;
1375
1376         if (HAS_PCH_CPT(dev_priv)) {
1377                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1378                         return false;
1379         } else {
1380                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381                         return false;
1382         }
1383         return true;
1384 }
1385
1386 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1387                               enum pipe pipe, u32 val)
1388 {
1389         if ((val & ADPA_DAC_ENABLE) == 0)
1390                 return false;
1391         if (HAS_PCH_CPT(dev_priv)) {
1392                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393                         return false;
1394         } else {
1395                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396                         return false;
1397         }
1398         return true;
1399 }
1400
1401 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1402                                    enum pipe pipe, i915_reg_t reg,
1403                                    u32 port_sel)
1404 {
1405         u32 val = I915_READ(reg);
1406         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1407              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1408              i915_mmio_reg_offset(reg), pipe_name(pipe));
1409
1410         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1411              && (val & DP_PIPEB_SELECT),
1412              "IBX PCH dp port still using transcoder B\n");
1413 }
1414
1415 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1416                                      enum pipe pipe, i915_reg_t reg)
1417 {
1418         u32 val = I915_READ(reg);
1419         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1420              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1421              i915_mmio_reg_offset(reg), pipe_name(pipe));
1422
1423         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1424              && (val & SDVO_PIPE_B_SELECT),
1425              "IBX PCH hdmi port still using transcoder B\n");
1426 }
1427
1428 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1429                                       enum pipe pipe)
1430 {
1431         u32 val;
1432
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1435         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1436
1437         val = I915_READ(PCH_ADPA);
1438         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         val = I915_READ(PCH_LVDS);
1443         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1444              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1445              pipe_name(pipe));
1446
1447         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1450 }
1451
1452 static void _vlv_enable_pll(struct intel_crtc *crtc,
1453                             const struct intel_crtc_state *pipe_config)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1456         enum pipe pipe = crtc->pipe;
1457
1458         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1459         POSTING_READ(DPLL(pipe));
1460         udelay(150);
1461
1462         if (intel_wait_for_register(dev_priv,
1463                                     DPLL(pipe),
1464                                     DPLL_LOCK_VLV,
1465                                     DPLL_LOCK_VLV,
1466                                     1))
1467                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1468 }
1469
1470 static void vlv_enable_pll(struct intel_crtc *crtc,
1471                            const struct intel_crtc_state *pipe_config)
1472 {
1473         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1474         enum pipe pipe = crtc->pipe;
1475
1476         assert_pipe_disabled(dev_priv, pipe);
1477
1478         /* PLL is protected by panel, make sure we can write it */
1479         assert_panel_unlocked(dev_priv, pipe);
1480
1481         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1482                 _vlv_enable_pll(crtc, pipe_config);
1483
1484         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1485         POSTING_READ(DPLL_MD(pipe));
1486 }
1487
1488
1489 static void _chv_enable_pll(struct intel_crtc *crtc,
1490                             const struct intel_crtc_state *pipe_config)
1491 {
1492         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1493         enum pipe pipe = crtc->pipe;
1494         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1495         u32 tmp;
1496
1497         mutex_lock(&dev_priv->sb_lock);
1498
1499         /* Enable back the 10bit clock to display controller */
1500         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1501         tmp |= DPIO_DCLKP_EN;
1502         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1503
1504         mutex_unlock(&dev_priv->sb_lock);
1505
1506         /*
1507          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1508          */
1509         udelay(1);
1510
1511         /* Enable PLL */
1512         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1513
1514         /* Check PLL is locked */
1515         if (intel_wait_for_register(dev_priv,
1516                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1517                                     1))
1518                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1519 }
1520
1521 static void chv_enable_pll(struct intel_crtc *crtc,
1522                            const struct intel_crtc_state *pipe_config)
1523 {
1524         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1525         enum pipe pipe = crtc->pipe;
1526
1527         assert_pipe_disabled(dev_priv, pipe);
1528
1529         /* PLL is protected by panel, make sure we can write it */
1530         assert_panel_unlocked(dev_priv, pipe);
1531
1532         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1533                 _chv_enable_pll(crtc, pipe_config);
1534
1535         if (pipe != PIPE_A) {
1536                 /*
1537                  * WaPixelRepeatModeFixForC0:chv
1538                  *
1539                  * DPLLCMD is AWOL. Use chicken bits to propagate
1540                  * the value from DPLLBMD to either pipe B or C.
1541                  */
1542                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1543                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1544                 I915_WRITE(CBR4_VLV, 0);
1545                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1546
1547                 /*
1548                  * DPLLB VGA mode also seems to cause problems.
1549                  * We should always have it disabled.
1550                  */
1551                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1552         } else {
1553                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1554                 POSTING_READ(DPLL_MD(pipe));
1555         }
1556 }
1557
1558 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1559 {
1560         struct intel_crtc *crtc;
1561         int count = 0;
1562
1563         for_each_intel_crtc(&dev_priv->drm, crtc) {
1564                 count += crtc->base.state->active &&
1565                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1566         }
1567
1568         return count;
1569 }
1570
1571 static void i9xx_enable_pll(struct intel_crtc *crtc)
1572 {
1573         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1574         i915_reg_t reg = DPLL(crtc->pipe);
1575         u32 dpll = crtc->config->dpll_hw_state.dpll;
1576         int i;
1577
1578         assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580         /* PLL is protected by panel, make sure we can write it */
1581         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1582                 assert_panel_unlocked(dev_priv, crtc->pipe);
1583
1584         /* Enable DVO 2x clock on both PLLs if necessary */
1585         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1586                 /*
1587                  * It appears to be important that we don't enable this
1588                  * for the current pipe before otherwise configuring the
1589                  * PLL. No idea how this should be handled if multiple
1590                  * DVO outputs are enabled simultaneosly.
1591                  */
1592                 dpll |= DPLL_DVO_2X_MODE;
1593                 I915_WRITE(DPLL(!crtc->pipe),
1594                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1595         }
1596
1597         /*
1598          * Apparently we need to have VGA mode enabled prior to changing
1599          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1600          * dividers, even though the register value does change.
1601          */
1602         I915_WRITE(reg, 0);
1603
1604         I915_WRITE(reg, dpll);
1605
1606         /* Wait for the clocks to stabilize. */
1607         POSTING_READ(reg);
1608         udelay(150);
1609
1610         if (INTEL_GEN(dev_priv) >= 4) {
1611                 I915_WRITE(DPLL_MD(crtc->pipe),
1612                            crtc->config->dpll_hw_state.dpll_md);
1613         } else {
1614                 /* The pixel multiplier can only be updated once the
1615                  * DPLL is enabled and the clocks are stable.
1616                  *
1617                  * So write it again.
1618                  */
1619                 I915_WRITE(reg, dpll);
1620         }
1621
1622         /* We do this three times for luck */
1623         for (i = 0; i < 3; i++) {
1624                 I915_WRITE(reg, dpll);
1625                 POSTING_READ(reg);
1626                 udelay(150); /* wait for warmup */
1627         }
1628 }
1629
1630 /**
1631  * i9xx_disable_pll - disable a PLL
1632  * @dev_priv: i915 private structure
1633  * @pipe: pipe PLL to disable
1634  *
1635  * Disable the PLL for @pipe, making sure the pipe is off first.
1636  *
1637  * Note!  This is for pre-ILK only.
1638  */
1639 static void i9xx_disable_pll(struct intel_crtc *crtc)
1640 {
1641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1642         enum pipe pipe = crtc->pipe;
1643
1644         /* Disable DVO 2x clock on both PLLs if necessary */
1645         if (IS_I830(dev_priv) &&
1646             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1647             !intel_num_dvo_pipes(dev_priv)) {
1648                 I915_WRITE(DPLL(PIPE_B),
1649                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1650                 I915_WRITE(DPLL(PIPE_A),
1651                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1652         }
1653
1654         /* Don't disable pipe or pipe PLLs if needed */
1655         if (IS_I830(dev_priv))
1656                 return;
1657
1658         /* Make sure the pipe isn't still relying on us */
1659         assert_pipe_disabled(dev_priv, pipe);
1660
1661         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1662         POSTING_READ(DPLL(pipe));
1663 }
1664
1665 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1666 {
1667         u32 val;
1668
1669         /* Make sure the pipe isn't still relying on us */
1670         assert_pipe_disabled(dev_priv, pipe);
1671
1672         val = DPLL_INTEGRATED_REF_CLK_VLV |
1673                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1674         if (pipe != PIPE_A)
1675                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1676
1677         I915_WRITE(DPLL(pipe), val);
1678         POSTING_READ(DPLL(pipe));
1679 }
1680
1681 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1682 {
1683         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1684         u32 val;
1685
1686         /* Make sure the pipe isn't still relying on us */
1687         assert_pipe_disabled(dev_priv, pipe);
1688
1689         val = DPLL_SSC_REF_CLK_CHV |
1690                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1691         if (pipe != PIPE_A)
1692                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1693
1694         I915_WRITE(DPLL(pipe), val);
1695         POSTING_READ(DPLL(pipe));
1696
1697         mutex_lock(&dev_priv->sb_lock);
1698
1699         /* Disable 10bit clock to display controller */
1700         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1701         val &= ~DPIO_DCLKP_EN;
1702         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1703
1704         mutex_unlock(&dev_priv->sb_lock);
1705 }
1706
1707 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1708                          struct intel_digital_port *dport,
1709                          unsigned int expected_mask)
1710 {
1711         u32 port_mask;
1712         i915_reg_t dpll_reg;
1713
1714         switch (dport->port) {
1715         case PORT_B:
1716                 port_mask = DPLL_PORTB_READY_MASK;
1717                 dpll_reg = DPLL(0);
1718                 break;
1719         case PORT_C:
1720                 port_mask = DPLL_PORTC_READY_MASK;
1721                 dpll_reg = DPLL(0);
1722                 expected_mask <<= 4;
1723                 break;
1724         case PORT_D:
1725                 port_mask = DPLL_PORTD_READY_MASK;
1726                 dpll_reg = DPIO_PHY_STATUS;
1727                 break;
1728         default:
1729                 BUG();
1730         }
1731
1732         if (intel_wait_for_register(dev_priv,
1733                                     dpll_reg, port_mask, expected_mask,
1734                                     1000))
1735                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1736                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1737 }
1738
1739 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740                                            enum pipe pipe)
1741 {
1742         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1743                                                                 pipe);
1744         i915_reg_t reg;
1745         uint32_t val, pipeconf_val;
1746
1747         /* Make sure PCH DPLL is enabled */
1748         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1749
1750         /* FDI must be feeding us bits for PCH ports */
1751         assert_fdi_tx_enabled(dev_priv, pipe);
1752         assert_fdi_rx_enabled(dev_priv, pipe);
1753
1754         if (HAS_PCH_CPT(dev_priv)) {
1755                 /* Workaround: Set the timing override bit before enabling the
1756                  * pch transcoder. */
1757                 reg = TRANS_CHICKEN2(pipe);
1758                 val = I915_READ(reg);
1759                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1760                 I915_WRITE(reg, val);
1761         }
1762
1763         reg = PCH_TRANSCONF(pipe);
1764         val = I915_READ(reg);
1765         pipeconf_val = I915_READ(PIPECONF(pipe));
1766
1767         if (HAS_PCH_IBX(dev_priv)) {
1768                 /*
1769                  * Make the BPC in transcoder be consistent with
1770                  * that in pipeconf reg. For HDMI we must use 8bpc
1771                  * here for both 8bpc and 12bpc.
1772                  */
1773                 val &= ~PIPECONF_BPC_MASK;
1774                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1775                         val |= PIPECONF_8BPC;
1776                 else
1777                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1778         }
1779
1780         val &= ~TRANS_INTERLACE_MASK;
1781         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1782                 if (HAS_PCH_IBX(dev_priv) &&
1783                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1784                         val |= TRANS_LEGACY_INTERLACED_ILK;
1785                 else
1786                         val |= TRANS_INTERLACED;
1787         else
1788                 val |= TRANS_PROGRESSIVE;
1789
1790         I915_WRITE(reg, val | TRANS_ENABLE);
1791         if (intel_wait_for_register(dev_priv,
1792                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1793                                     100))
1794                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1795 }
1796
1797 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1798                                       enum transcoder cpu_transcoder)
1799 {
1800         u32 val, pipeconf_val;
1801
1802         /* FDI must be feeding us bits for PCH ports */
1803         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1804         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1805
1806         /* Workaround: set timing override bit. */
1807         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1808         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1809         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1810
1811         val = TRANS_ENABLE;
1812         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1813
1814         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1815             PIPECONF_INTERLACED_ILK)
1816                 val |= TRANS_INTERLACED;
1817         else
1818                 val |= TRANS_PROGRESSIVE;
1819
1820         I915_WRITE(LPT_TRANSCONF, val);
1821         if (intel_wait_for_register(dev_priv,
1822                                     LPT_TRANSCONF,
1823                                     TRANS_STATE_ENABLE,
1824                                     TRANS_STATE_ENABLE,
1825                                     100))
1826                 DRM_ERROR("Failed to enable PCH transcoder\n");
1827 }
1828
1829 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1830                                             enum pipe pipe)
1831 {
1832         i915_reg_t reg;
1833         uint32_t val;
1834
1835         /* FDI relies on the transcoder */
1836         assert_fdi_tx_disabled(dev_priv, pipe);
1837         assert_fdi_rx_disabled(dev_priv, pipe);
1838
1839         /* Ports must be off as well */
1840         assert_pch_ports_disabled(dev_priv, pipe);
1841
1842         reg = PCH_TRANSCONF(pipe);
1843         val = I915_READ(reg);
1844         val &= ~TRANS_ENABLE;
1845         I915_WRITE(reg, val);
1846         /* wait for PCH transcoder off, transcoder state */
1847         if (intel_wait_for_register(dev_priv,
1848                                     reg, TRANS_STATE_ENABLE, 0,
1849                                     50))
1850                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1851
1852         if (HAS_PCH_CPT(dev_priv)) {
1853                 /* Workaround: Clear the timing override chicken bit again. */
1854                 reg = TRANS_CHICKEN2(pipe);
1855                 val = I915_READ(reg);
1856                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857                 I915_WRITE(reg, val);
1858         }
1859 }
1860
1861 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1862 {
1863         u32 val;
1864
1865         val = I915_READ(LPT_TRANSCONF);
1866         val &= ~TRANS_ENABLE;
1867         I915_WRITE(LPT_TRANSCONF, val);
1868         /* wait for PCH transcoder off, transcoder state */
1869         if (intel_wait_for_register(dev_priv,
1870                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1871                                     50))
1872                 DRM_ERROR("Failed to disable PCH transcoder\n");
1873
1874         /* Workaround: clear timing override bit. */
1875         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1876         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1877         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1878 }
1879
1880 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1881 {
1882         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1883
1884         WARN_ON(!crtc->config->has_pch_encoder);
1885
1886         if (HAS_PCH_LPT(dev_priv))
1887                 return PIPE_A;
1888         else
1889                 return crtc->pipe;
1890 }
1891
1892 /**
1893  * intel_enable_pipe - enable a pipe, asserting requirements
1894  * @crtc: crtc responsible for the pipe
1895  *
1896  * Enable @crtc's pipe, making sure that various hardware specific requirements
1897  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1898  */
1899 static void intel_enable_pipe(struct intel_crtc *crtc)
1900 {
1901         struct drm_device *dev = crtc->base.dev;
1902         struct drm_i915_private *dev_priv = to_i915(dev);
1903         enum pipe pipe = crtc->pipe;
1904         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1905         i915_reg_t reg;
1906         u32 val;
1907
1908         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1909
1910         assert_planes_disabled(dev_priv, pipe);
1911         assert_cursor_disabled(dev_priv, pipe);
1912         assert_sprites_disabled(dev_priv, pipe);
1913
1914         /*
1915          * A pipe without a PLL won't actually be able to drive bits from
1916          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1917          * need the check.
1918          */
1919         if (HAS_GMCH_DISPLAY(dev_priv)) {
1920                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1921                         assert_dsi_pll_enabled(dev_priv);
1922                 else
1923                         assert_pll_enabled(dev_priv, pipe);
1924         } else {
1925                 if (crtc->config->has_pch_encoder) {
1926                         /* if driving the PCH, we need FDI enabled */
1927                         assert_fdi_rx_pll_enabled(dev_priv,
1928                                                   intel_crtc_pch_transcoder(crtc));
1929                         assert_fdi_tx_pll_enabled(dev_priv,
1930                                                   (enum pipe) cpu_transcoder);
1931                 }
1932                 /* FIXME: assert CPU port conditions for SNB+ */
1933         }
1934
1935         reg = PIPECONF(cpu_transcoder);
1936         val = I915_READ(reg);
1937         if (val & PIPECONF_ENABLE) {
1938                 /* we keep both pipes enabled on 830 */
1939                 WARN_ON(!IS_I830(dev_priv));
1940                 return;
1941         }
1942
1943         I915_WRITE(reg, val | PIPECONF_ENABLE);
1944         POSTING_READ(reg);
1945
1946         /*
1947          * Until the pipe starts DSL will read as 0, which would cause
1948          * an apparent vblank timestamp jump, which messes up also the
1949          * frame count when it's derived from the timestamps. So let's
1950          * wait for the pipe to start properly before we call
1951          * drm_crtc_vblank_on()
1952          */
1953         if (dev->max_vblank_count == 0 &&
1954             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1955                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1956 }
1957
1958 /**
1959  * intel_disable_pipe - disable a pipe, asserting requirements
1960  * @crtc: crtc whose pipes is to be disabled
1961  *
1962  * Disable the pipe of @crtc, making sure that various hardware
1963  * specific requirements are met, if applicable, e.g. plane
1964  * disabled, panel fitter off, etc.
1965  *
1966  * Will wait until the pipe has shut down before returning.
1967  */
1968 static void intel_disable_pipe(struct intel_crtc *crtc)
1969 {
1970         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1971         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1972         enum pipe pipe = crtc->pipe;
1973         i915_reg_t reg;
1974         u32 val;
1975
1976         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1977
1978         /*
1979          * Make sure planes won't keep trying to pump pixels to us,
1980          * or we might hang the display.
1981          */
1982         assert_planes_disabled(dev_priv, pipe);
1983         assert_cursor_disabled(dev_priv, pipe);
1984         assert_sprites_disabled(dev_priv, pipe);
1985
1986         reg = PIPECONF(cpu_transcoder);
1987         val = I915_READ(reg);
1988         if ((val & PIPECONF_ENABLE) == 0)
1989                 return;
1990
1991         /*
1992          * Double wide has implications for planes
1993          * so best keep it disabled when not needed.
1994          */
1995         if (crtc->config->double_wide)
1996                 val &= ~PIPECONF_DOUBLE_WIDE;
1997
1998         /* Don't disable pipe or pipe PLLs if needed */
1999         if (!IS_I830(dev_priv))
2000                 val &= ~PIPECONF_ENABLE;
2001
2002         I915_WRITE(reg, val);
2003         if ((val & PIPECONF_ENABLE) == 0)
2004                 intel_wait_for_pipe_off(crtc);
2005 }
2006
2007 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2008 {
2009         return IS_GEN2(dev_priv) ? 2048 : 4096;
2010 }
2011
2012 static unsigned int
2013 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
2014 {
2015         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2016         unsigned int cpp = fb->format->cpp[plane];
2017
2018         switch (fb->modifier) {
2019         case DRM_FORMAT_MOD_LINEAR:
2020                 return cpp;
2021         case I915_FORMAT_MOD_X_TILED:
2022                 if (IS_GEN2(dev_priv))
2023                         return 128;
2024                 else
2025                         return 512;
2026         case I915_FORMAT_MOD_Y_TILED_CCS:
2027                 if (plane == 1)
2028                         return 128;
2029                 /* fall through */
2030         case I915_FORMAT_MOD_Y_TILED:
2031                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2032                         return 128;
2033                 else
2034                         return 512;
2035         case I915_FORMAT_MOD_Yf_TILED_CCS:
2036                 if (plane == 1)
2037                         return 128;
2038                 /* fall through */
2039         case I915_FORMAT_MOD_Yf_TILED:
2040                 switch (cpp) {
2041                 case 1:
2042                         return 64;
2043                 case 2:
2044                 case 4:
2045                         return 128;
2046                 case 8:
2047                 case 16:
2048                         return 256;
2049                 default:
2050                         MISSING_CASE(cpp);
2051                         return cpp;
2052                 }
2053                 break;
2054         default:
2055                 MISSING_CASE(fb->modifier);
2056                 return cpp;
2057         }
2058 }
2059
2060 static unsigned int
2061 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2062 {
2063         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
2064                 return 1;
2065         else
2066                 return intel_tile_size(to_i915(fb->dev)) /
2067                         intel_tile_width_bytes(fb, plane);
2068 }
2069
2070 /* Return the tile dimensions in pixel units */
2071 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2072                             unsigned int *tile_width,
2073                             unsigned int *tile_height)
2074 {
2075         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2076         unsigned int cpp = fb->format->cpp[plane];
2077
2078         *tile_width = tile_width_bytes / cpp;
2079         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2080 }
2081
2082 unsigned int
2083 intel_fb_align_height(const struct drm_framebuffer *fb,
2084                       int plane, unsigned int height)
2085 {
2086         unsigned int tile_height = intel_tile_height(fb, plane);
2087
2088         return ALIGN(height, tile_height);
2089 }
2090
2091 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2092 {
2093         unsigned int size = 0;
2094         int i;
2095
2096         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2097                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2098
2099         return size;
2100 }
2101
2102 static void
2103 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2104                         const struct drm_framebuffer *fb,
2105                         unsigned int rotation)
2106 {
2107         view->type = I915_GGTT_VIEW_NORMAL;
2108         if (drm_rotation_90_or_270(rotation)) {
2109                 view->type = I915_GGTT_VIEW_ROTATED;
2110                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2111         }
2112 }
2113
2114 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2115 {
2116         if (IS_I830(dev_priv))
2117                 return 16 * 1024;
2118         else if (IS_I85X(dev_priv))
2119                 return 256;
2120         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2121                 return 32;
2122         else
2123                 return 4 * 1024;
2124 }
2125
2126 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2127 {
2128         if (INTEL_INFO(dev_priv)->gen >= 9)
2129                 return 256 * 1024;
2130         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2131                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2132                 return 128 * 1024;
2133         else if (INTEL_INFO(dev_priv)->gen >= 4)
2134                 return 4 * 1024;
2135         else
2136                 return 0;
2137 }
2138
2139 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2140                                          int plane)
2141 {
2142         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2143
2144         /* AUX_DIST needs only 4K alignment */
2145         if (plane == 1)
2146                 return 4096;
2147
2148         switch (fb->modifier) {
2149         case DRM_FORMAT_MOD_LINEAR:
2150                 return intel_linear_alignment(dev_priv);
2151         case I915_FORMAT_MOD_X_TILED:
2152                 if (INTEL_GEN(dev_priv) >= 9)
2153                         return 256 * 1024;
2154                 return 0;
2155         case I915_FORMAT_MOD_Y_TILED_CCS:
2156         case I915_FORMAT_MOD_Yf_TILED_CCS:
2157         case I915_FORMAT_MOD_Y_TILED:
2158         case I915_FORMAT_MOD_Yf_TILED:
2159                 return 1 * 1024 * 1024;
2160         default:
2161                 MISSING_CASE(fb->modifier);
2162                 return 0;
2163         }
2164 }
2165
2166 struct i915_vma *
2167 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2168 {
2169         struct drm_device *dev = fb->dev;
2170         struct drm_i915_private *dev_priv = to_i915(dev);
2171         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2172         struct i915_ggtt_view view;
2173         struct i915_vma *vma;
2174         u32 alignment;
2175
2176         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2177
2178         alignment = intel_surf_alignment(fb, 0);
2179
2180         intel_fill_fb_ggtt_view(&view, fb, rotation);
2181
2182         /* Note that the w/a also requires 64 PTE of padding following the
2183          * bo. We currently fill all unused PTE with the shadow page and so
2184          * we should always have valid PTE following the scanout preventing
2185          * the VT-d warning.
2186          */
2187         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2188                 alignment = 256 * 1024;
2189
2190         /*
2191          * Global gtt pte registers are special registers which actually forward
2192          * writes to a chunk of system memory. Which means that there is no risk
2193          * that the register values disappear as soon as we call
2194          * intel_runtime_pm_put(), so it is correct to wrap only the
2195          * pin/unpin/fence and not more.
2196          */
2197         intel_runtime_pm_get(dev_priv);
2198
2199         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2200
2201         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2202         if (IS_ERR(vma))
2203                 goto err;
2204
2205         if (i915_vma_is_map_and_fenceable(vma)) {
2206                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2207                  * fence, whereas 965+ only requires a fence if using
2208                  * framebuffer compression.  For simplicity, we always, when
2209                  * possible, install a fence as the cost is not that onerous.
2210                  *
2211                  * If we fail to fence the tiled scanout, then either the
2212                  * modeset will reject the change (which is highly unlikely as
2213                  * the affected systems, all but one, do not have unmappable
2214                  * space) or we will not be able to enable full powersaving
2215                  * techniques (also likely not to apply due to various limits
2216                  * FBC and the like impose on the size of the buffer, which
2217                  * presumably we violated anyway with this unmappable buffer).
2218                  * Anyway, it is presumably better to stumble onwards with
2219                  * something and try to run the system in a "less than optimal"
2220                  * mode that matches the user configuration.
2221                  */
2222                 if (i915_vma_get_fence(vma) == 0)
2223                         i915_vma_pin_fence(vma);
2224         }
2225
2226         i915_vma_get(vma);
2227 err:
2228         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2229
2230         intel_runtime_pm_put(dev_priv);
2231         return vma;
2232 }
2233
2234 void intel_unpin_fb_vma(struct i915_vma *vma)
2235 {
2236         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2237
2238         i915_vma_unpin_fence(vma);
2239         i915_gem_object_unpin_from_display_plane(vma);
2240         i915_vma_put(vma);
2241 }
2242
2243 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2244                           unsigned int rotation)
2245 {
2246         if (drm_rotation_90_or_270(rotation))
2247                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2248         else
2249                 return fb->pitches[plane];
2250 }
2251
2252 /*
2253  * Convert the x/y offsets into a linear offset.
2254  * Only valid with 0/180 degree rotation, which is fine since linear
2255  * offset is only used with linear buffers on pre-hsw and tiled buffers
2256  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2257  */
2258 u32 intel_fb_xy_to_linear(int x, int y,
2259                           const struct intel_plane_state *state,
2260                           int plane)
2261 {
2262         const struct drm_framebuffer *fb = state->base.fb;
2263         unsigned int cpp = fb->format->cpp[plane];
2264         unsigned int pitch = fb->pitches[plane];
2265
2266         return y * pitch + x * cpp;
2267 }
2268
2269 /*
2270  * Add the x/y offsets derived from fb->offsets[] to the user
2271  * specified plane src x/y offsets. The resulting x/y offsets
2272  * specify the start of scanout from the beginning of the gtt mapping.
2273  */
2274 void intel_add_fb_offsets(int *x, int *y,
2275                           const struct intel_plane_state *state,
2276                           int plane)
2277
2278 {
2279         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2280         unsigned int rotation = state->base.rotation;
2281
2282         if (drm_rotation_90_or_270(rotation)) {
2283                 *x += intel_fb->rotated[plane].x;
2284                 *y += intel_fb->rotated[plane].y;
2285         } else {
2286                 *x += intel_fb->normal[plane].x;
2287                 *y += intel_fb->normal[plane].y;
2288         }
2289 }
2290
2291 static u32 __intel_adjust_tile_offset(int *x, int *y,
2292                                       unsigned int tile_width,
2293                                       unsigned int tile_height,
2294                                       unsigned int tile_size,
2295                                       unsigned int pitch_tiles,
2296                                       u32 old_offset,
2297                                       u32 new_offset)
2298 {
2299         unsigned int pitch_pixels = pitch_tiles * tile_width;
2300         unsigned int tiles;
2301
2302         WARN_ON(old_offset & (tile_size - 1));
2303         WARN_ON(new_offset & (tile_size - 1));
2304         WARN_ON(new_offset > old_offset);
2305
2306         tiles = (old_offset - new_offset) / tile_size;
2307
2308         *y += tiles / pitch_tiles * tile_height;
2309         *x += tiles % pitch_tiles * tile_width;
2310
2311         /* minimize x in case it got needlessly big */
2312         *y += *x / pitch_pixels * tile_height;
2313         *x %= pitch_pixels;
2314
2315         return new_offset;
2316 }
2317
2318 static u32 _intel_adjust_tile_offset(int *x, int *y,
2319                                      const struct drm_framebuffer *fb, int plane,
2320                                      unsigned int rotation,
2321                                      u32 old_offset, u32 new_offset)
2322 {
2323         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2324         unsigned int cpp = fb->format->cpp[plane];
2325         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2326
2327         WARN_ON(new_offset > old_offset);
2328
2329         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2330                 unsigned int tile_size, tile_width, tile_height;
2331                 unsigned int pitch_tiles;
2332
2333                 tile_size = intel_tile_size(dev_priv);
2334                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2335
2336                 if (drm_rotation_90_or_270(rotation)) {
2337                         pitch_tiles = pitch / tile_height;
2338                         swap(tile_width, tile_height);
2339                 } else {
2340                         pitch_tiles = pitch / (tile_width * cpp);
2341                 }
2342
2343                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2344                                            tile_size, pitch_tiles,
2345                                            old_offset, new_offset);
2346         } else {
2347                 old_offset += *y * pitch + *x * cpp;
2348
2349                 *y = (old_offset - new_offset) / pitch;
2350                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2351         }
2352
2353         return new_offset;
2354 }
2355
2356 /*
2357  * Adjust the tile offset by moving the difference into
2358  * the x/y offsets.
2359  */
2360 static u32 intel_adjust_tile_offset(int *x, int *y,
2361                                     const struct intel_plane_state *state, int plane,
2362                                     u32 old_offset, u32 new_offset)
2363 {
2364         return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
2365                                          state->base.rotation,
2366                                          old_offset, new_offset);
2367 }
2368
2369 /*
2370  * Computes the linear offset to the base tile and adjusts
2371  * x, y. bytes per pixel is assumed to be a power-of-two.
2372  *
2373  * In the 90/270 rotated case, x and y are assumed
2374  * to be already rotated to match the rotated GTT view, and
2375  * pitch is the tile_height aligned framebuffer height.
2376  *
2377  * This function is used when computing the derived information
2378  * under intel_framebuffer, so using any of that information
2379  * here is not allowed. Anything under drm_framebuffer can be
2380  * used. This is why the user has to pass in the pitch since it
2381  * is specified in the rotated orientation.
2382  */
2383 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2384                                       int *x, int *y,
2385                                       const struct drm_framebuffer *fb, int plane,
2386                                       unsigned int pitch,
2387                                       unsigned int rotation,
2388                                       u32 alignment)
2389 {
2390         uint64_t fb_modifier = fb->modifier;
2391         unsigned int cpp = fb->format->cpp[plane];
2392         u32 offset, offset_aligned;
2393
2394         if (alignment)
2395                 alignment--;
2396
2397         if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
2398                 unsigned int tile_size, tile_width, tile_height;
2399                 unsigned int tile_rows, tiles, pitch_tiles;
2400
2401                 tile_size = intel_tile_size(dev_priv);
2402                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2403
2404                 if (drm_rotation_90_or_270(rotation)) {
2405                         pitch_tiles = pitch / tile_height;
2406                         swap(tile_width, tile_height);
2407                 } else {
2408                         pitch_tiles = pitch / (tile_width * cpp);
2409                 }
2410
2411                 tile_rows = *y / tile_height;
2412                 *y %= tile_height;
2413
2414                 tiles = *x / tile_width;
2415                 *x %= tile_width;
2416
2417                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2418                 offset_aligned = offset & ~alignment;
2419
2420                 __intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421                                            tile_size, pitch_tiles,
2422                                            offset, offset_aligned);
2423         } else {
2424                 offset = *y * pitch + *x * cpp;
2425                 offset_aligned = offset & ~alignment;
2426
2427                 *y = (offset & alignment) / pitch;
2428                 *x = ((offset & alignment) - *y * pitch) / cpp;
2429         }
2430
2431         return offset_aligned;
2432 }
2433
2434 u32 intel_compute_tile_offset(int *x, int *y,
2435                               const struct intel_plane_state *state,
2436                               int plane)
2437 {
2438         struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
2439         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2440         const struct drm_framebuffer *fb = state->base.fb;
2441         unsigned int rotation = state->base.rotation;
2442         int pitch = intel_fb_pitch(fb, plane, rotation);
2443         u32 alignment;
2444
2445         if (intel_plane->id == PLANE_CURSOR)
2446                 alignment = intel_cursor_alignment(dev_priv);
2447         else
2448                 alignment = intel_surf_alignment(fb, plane);
2449
2450         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2451                                           rotation, alignment);
2452 }
2453
2454 /* Convert the fb->offset[] into x/y offsets */
2455 static int intel_fb_offset_to_xy(int *x, int *y,
2456                                  const struct drm_framebuffer *fb, int plane)
2457 {
2458         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2459
2460         if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
2461             fb->offsets[plane] % intel_tile_size(dev_priv))
2462                 return -EINVAL;
2463
2464         *x = 0;
2465         *y = 0;
2466
2467         _intel_adjust_tile_offset(x, y,
2468                                   fb, plane, DRM_MODE_ROTATE_0,
2469                                   fb->offsets[plane], 0);
2470
2471         return 0;
2472 }
2473
2474 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2475 {
2476         switch (fb_modifier) {
2477         case I915_FORMAT_MOD_X_TILED:
2478                 return I915_TILING_X;
2479         case I915_FORMAT_MOD_Y_TILED:
2480         case I915_FORMAT_MOD_Y_TILED_CCS:
2481                 return I915_TILING_Y;
2482         default:
2483                 return I915_TILING_NONE;
2484         }
2485 }
2486
2487 static const struct drm_format_info ccs_formats[] = {
2488         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2489         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2490         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2491         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2492 };
2493
2494 static const struct drm_format_info *
2495 lookup_format_info(const struct drm_format_info formats[],
2496                    int num_formats, u32 format)
2497 {
2498         int i;
2499
2500         for (i = 0; i < num_formats; i++) {
2501                 if (formats[i].format == format)
2502                         return &formats[i];
2503         }
2504
2505         return NULL;
2506 }
2507
2508 static const struct drm_format_info *
2509 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2510 {
2511         switch (cmd->modifier[0]) {
2512         case I915_FORMAT_MOD_Y_TILED_CCS:
2513         case I915_FORMAT_MOD_Yf_TILED_CCS:
2514                 return lookup_format_info(ccs_formats,
2515                                           ARRAY_SIZE(ccs_formats),
2516                                           cmd->pixel_format);
2517         default:
2518                 return NULL;
2519         }
2520 }
2521
2522 static int
2523 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2524                    struct drm_framebuffer *fb)
2525 {
2526         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2527         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2528         u32 gtt_offset_rotated = 0;
2529         unsigned int max_size = 0;
2530         int i, num_planes = fb->format->num_planes;
2531         unsigned int tile_size = intel_tile_size(dev_priv);
2532
2533         for (i = 0; i < num_planes; i++) {
2534                 unsigned int width, height;
2535                 unsigned int cpp, size;
2536                 u32 offset;
2537                 int x, y;
2538                 int ret;
2539
2540                 cpp = fb->format->cpp[i];
2541                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2542                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2543
2544                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
2545                 if (ret) {
2546                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2547                                       i, fb->offsets[i]);
2548                         return ret;
2549                 }
2550
2551                 if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2552                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) {
2553                         int hsub = fb->format->hsub;
2554                         int vsub = fb->format->vsub;
2555                         int tile_width, tile_height;
2556                         int main_x, main_y;
2557                         int ccs_x, ccs_y;
2558
2559                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2560                         tile_width *= hsub;
2561                         tile_height *= vsub;
2562
2563                         ccs_x = (x * hsub) % tile_width;
2564                         ccs_y = (y * vsub) % tile_height;
2565                         main_x = intel_fb->normal[0].x % tile_width;
2566                         main_y = intel_fb->normal[0].y % tile_height;
2567
2568                         /*
2569                          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2570                          * x/y offsets must match between CCS and the main surface.
2571                          */
2572                         if (main_x != ccs_x || main_y != ccs_y) {
2573                                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2574                                               main_x, main_y,
2575                                               ccs_x, ccs_y,
2576                                               intel_fb->normal[0].x,
2577                                               intel_fb->normal[0].y,
2578                                               x, y);
2579                                 return -EINVAL;
2580                         }
2581                 }
2582
2583                 /*
2584                  * The fence (if used) is aligned to the start of the object
2585                  * so having the framebuffer wrap around across the edge of the
2586                  * fenced region doesn't really work. We have no API to configure
2587                  * the fence start offset within the object (nor could we probably
2588                  * on gen2/3). So it's just easier if we just require that the
2589                  * fb layout agrees with the fence layout. We already check that the
2590                  * fb stride matches the fence stride elsewhere.
2591                  */
2592                 if (i == 0 && i915_gem_object_is_tiled(intel_fb->obj) &&
2593                     (x + width) * cpp > fb->pitches[i]) {
2594                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2595                                       i, fb->offsets[i]);
2596                         return -EINVAL;
2597                 }
2598
2599                 /*
2600                  * First pixel of the framebuffer from
2601                  * the start of the normal gtt mapping.
2602                  */
2603                 intel_fb->normal[i].x = x;
2604                 intel_fb->normal[i].y = y;
2605
2606                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2607                                                     fb, i, fb->pitches[i],
2608                                                     DRM_MODE_ROTATE_0, tile_size);
2609                 offset /= tile_size;
2610
2611                 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
2612                         unsigned int tile_width, tile_height;
2613                         unsigned int pitch_tiles;
2614                         struct drm_rect r;
2615
2616                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2617
2618                         rot_info->plane[i].offset = offset;
2619                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2620                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2621                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2622
2623                         intel_fb->rotated[i].pitch =
2624                                 rot_info->plane[i].height * tile_height;
2625
2626                         /* how many tiles does this plane need */
2627                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2628                         /*
2629                          * If the plane isn't horizontally tile aligned,
2630                          * we need one more tile.
2631                          */
2632                         if (x != 0)
2633                                 size++;
2634
2635                         /* rotate the x/y offsets to match the GTT view */
2636                         r.x1 = x;
2637                         r.y1 = y;
2638                         r.x2 = x + width;
2639                         r.y2 = y + height;
2640                         drm_rect_rotate(&r,
2641                                         rot_info->plane[i].width * tile_width,
2642                                         rot_info->plane[i].height * tile_height,
2643                                         DRM_MODE_ROTATE_270);
2644                         x = r.x1;
2645                         y = r.y1;
2646
2647                         /* rotate the tile dimensions to match the GTT view */
2648                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2649                         swap(tile_width, tile_height);
2650
2651                         /*
2652                          * We only keep the x/y offsets, so push all of the
2653                          * gtt offset into the x/y offsets.
2654                          */
2655                         __intel_adjust_tile_offset(&x, &y,
2656                                                    tile_width, tile_height,
2657                                                    tile_size, pitch_tiles,
2658                                                    gtt_offset_rotated * tile_size, 0);
2659
2660                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2661
2662                         /*
2663                          * First pixel of the framebuffer from
2664                          * the start of the rotated gtt mapping.
2665                          */
2666                         intel_fb->rotated[i].x = x;
2667                         intel_fb->rotated[i].y = y;
2668                 } else {
2669                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2670                                             x * cpp, tile_size);
2671                 }
2672
2673                 /* how many tiles in total needed in the bo */
2674                 max_size = max(max_size, offset + size);
2675         }
2676
2677         if (max_size * tile_size > intel_fb->obj->base.size) {
2678                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2679                               max_size * tile_size, intel_fb->obj->base.size);
2680                 return -EINVAL;
2681         }
2682
2683         return 0;
2684 }
2685
2686 static int i9xx_format_to_fourcc(int format)
2687 {
2688         switch (format) {
2689         case DISPPLANE_8BPP:
2690                 return DRM_FORMAT_C8;
2691         case DISPPLANE_BGRX555:
2692                 return DRM_FORMAT_XRGB1555;
2693         case DISPPLANE_BGRX565:
2694                 return DRM_FORMAT_RGB565;
2695         default:
2696         case DISPPLANE_BGRX888:
2697                 return DRM_FORMAT_XRGB8888;
2698         case DISPPLANE_RGBX888:
2699                 return DRM_FORMAT_XBGR8888;
2700         case DISPPLANE_BGRX101010:
2701                 return DRM_FORMAT_XRGB2101010;
2702         case DISPPLANE_RGBX101010:
2703                 return DRM_FORMAT_XBGR2101010;
2704         }
2705 }
2706
2707 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2708 {
2709         switch (format) {
2710         case PLANE_CTL_FORMAT_RGB_565:
2711                 return DRM_FORMAT_RGB565;
2712         default:
2713         case PLANE_CTL_FORMAT_XRGB_8888:
2714                 if (rgb_order) {
2715                         if (alpha)
2716                                 return DRM_FORMAT_ABGR8888;
2717                         else
2718                                 return DRM_FORMAT_XBGR8888;
2719                 } else {
2720                         if (alpha)
2721                                 return DRM_FORMAT_ARGB8888;
2722                         else
2723                                 return DRM_FORMAT_XRGB8888;
2724                 }
2725         case PLANE_CTL_FORMAT_XRGB_2101010:
2726                 if (rgb_order)
2727                         return DRM_FORMAT_XBGR2101010;
2728                 else
2729                         return DRM_FORMAT_XRGB2101010;
2730         }
2731 }
2732
2733 static bool
2734 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2735                               struct intel_initial_plane_config *plane_config)
2736 {
2737         struct drm_device *dev = crtc->base.dev;
2738         struct drm_i915_private *dev_priv = to_i915(dev);
2739         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2740         struct drm_i915_gem_object *obj = NULL;
2741         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2742         struct drm_framebuffer *fb = &plane_config->fb->base;
2743         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2744         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2745                                     PAGE_SIZE);
2746
2747         size_aligned -= base_aligned;
2748
2749         if (plane_config->size == 0)
2750                 return false;
2751
2752         /* If the FB is too big, just don't use it since fbdev is not very
2753          * important and we should probably use that space with FBC or other
2754          * features. */
2755         if (size_aligned * 2 > ggtt->stolen_usable_size)
2756                 return false;
2757
2758         mutex_lock(&dev->struct_mutex);
2759         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2760                                                              base_aligned,
2761                                                              base_aligned,
2762                                                              size_aligned);
2763         mutex_unlock(&dev->struct_mutex);
2764         if (!obj)
2765                 return false;
2766
2767         if (plane_config->tiling == I915_TILING_X)
2768                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2769
2770         mode_cmd.pixel_format = fb->format->format;
2771         mode_cmd.width = fb->width;
2772         mode_cmd.height = fb->height;
2773         mode_cmd.pitches[0] = fb->pitches[0];
2774         mode_cmd.modifier[0] = fb->modifier;
2775         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2776
2777         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2778                 DRM_DEBUG_KMS("intel fb init failed\n");
2779                 goto out_unref_obj;
2780         }
2781
2782
2783         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2784         return true;
2785
2786 out_unref_obj:
2787         i915_gem_object_put(obj);
2788         return false;
2789 }
2790
2791 static void
2792 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2793                         struct intel_plane_state *plane_state,
2794                         bool visible)
2795 {
2796         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2797
2798         plane_state->base.visible = visible;
2799
2800         /* FIXME pre-g4x don't work like this */
2801         if (visible) {
2802                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2803                 crtc_state->active_planes |= BIT(plane->id);
2804         } else {
2805                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2806                 crtc_state->active_planes &= ~BIT(plane->id);
2807         }
2808
2809         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2810                       crtc_state->base.crtc->name,
2811                       crtc_state->active_planes);
2812 }
2813
2814 static void
2815 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2816                              struct intel_initial_plane_config *plane_config)
2817 {
2818         struct drm_device *dev = intel_crtc->base.dev;
2819         struct drm_i915_private *dev_priv = to_i915(dev);
2820         struct drm_crtc *c;
2821         struct drm_i915_gem_object *obj;
2822         struct drm_plane *primary = intel_crtc->base.primary;
2823         struct drm_plane_state *plane_state = primary->state;
2824         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2825         struct intel_plane *intel_plane = to_intel_plane(primary);
2826         struct intel_plane_state *intel_state =
2827                 to_intel_plane_state(plane_state);
2828         struct drm_framebuffer *fb;
2829
2830         if (!plane_config->fb)
2831                 return;
2832
2833         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2834                 fb = &plane_config->fb->base;
2835                 goto valid_fb;
2836         }
2837
2838         kfree(plane_config->fb);
2839
2840         /*
2841          * Failed to alloc the obj, check to see if we should share
2842          * an fb with another CRTC instead
2843          */
2844         for_each_crtc(dev, c) {
2845                 struct intel_plane_state *state;
2846
2847                 if (c == &intel_crtc->base)
2848                         continue;
2849
2850                 if (!to_intel_crtc(c)->active)
2851                         continue;
2852
2853                 state = to_intel_plane_state(c->primary->state);
2854                 if (!state->vma)
2855                         continue;
2856
2857                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2858                         fb = c->primary->fb;
2859                         drm_framebuffer_reference(fb);
2860                         goto valid_fb;
2861                 }
2862         }
2863
2864         /*
2865          * We've failed to reconstruct the BIOS FB.  Current display state
2866          * indicates that the primary plane is visible, but has a NULL FB,
2867          * which will lead to problems later if we don't fix it up.  The
2868          * simplest solution is to just disable the primary plane now and
2869          * pretend the BIOS never had it enabled.
2870          */
2871         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2872                                 to_intel_plane_state(plane_state),
2873                                 false);
2874         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2875         trace_intel_disable_plane(primary, intel_crtc);
2876         intel_plane->disable_plane(intel_plane, intel_crtc);
2877
2878         return;
2879
2880 valid_fb:
2881         mutex_lock(&dev->struct_mutex);
2882         intel_state->vma =
2883                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2884         mutex_unlock(&dev->struct_mutex);
2885         if (IS_ERR(intel_state->vma)) {
2886                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2887                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2888
2889                 intel_state->vma = NULL;
2890                 drm_framebuffer_unreference(fb);
2891                 return;
2892         }
2893
2894         plane_state->src_x = 0;
2895         plane_state->src_y = 0;
2896         plane_state->src_w = fb->width << 16;
2897         plane_state->src_h = fb->height << 16;
2898
2899         plane_state->crtc_x = 0;
2900         plane_state->crtc_y = 0;
2901         plane_state->crtc_w = fb->width;
2902         plane_state->crtc_h = fb->height;
2903
2904         intel_state->base.src = drm_plane_state_src(plane_state);
2905         intel_state->base.dst = drm_plane_state_dest(plane_state);
2906
2907         obj = intel_fb_obj(fb);
2908         if (i915_gem_object_is_tiled(obj))
2909                 dev_priv->preserve_bios_swizzle = true;
2910
2911         drm_framebuffer_reference(fb);
2912         primary->fb = primary->state->fb = fb;
2913         primary->crtc = primary->state->crtc = &intel_crtc->base;
2914
2915         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2916                                 to_intel_plane_state(plane_state),
2917                                 true);
2918
2919         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2920                   &obj->frontbuffer_bits);
2921 }
2922
2923 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2924                                unsigned int rotation)
2925 {
2926         int cpp = fb->format->cpp[plane];
2927
2928         switch (fb->modifier) {
2929         case DRM_FORMAT_MOD_LINEAR:
2930         case I915_FORMAT_MOD_X_TILED:
2931                 switch (cpp) {
2932                 case 8:
2933                         return 4096;
2934                 case 4:
2935                 case 2:
2936                 case 1:
2937                         return 8192;
2938                 default:
2939                         MISSING_CASE(cpp);
2940                         break;
2941                 }
2942                 break;
2943         case I915_FORMAT_MOD_Y_TILED_CCS:
2944         case I915_FORMAT_MOD_Yf_TILED_CCS:
2945                 /* FIXME AUX plane? */
2946         case I915_FORMAT_MOD_Y_TILED:
2947         case I915_FORMAT_MOD_Yf_TILED:
2948                 switch (cpp) {
2949                 case 8:
2950                         return 2048;
2951                 case 4:
2952                         return 4096;
2953                 case 2:
2954                 case 1:
2955                         return 8192;
2956                 default:
2957                         MISSING_CASE(cpp);
2958                         break;
2959                 }
2960                 break;
2961         default:
2962                 MISSING_CASE(fb->modifier);
2963         }
2964
2965         return 2048;
2966 }
2967
2968 static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
2969                                            int main_x, int main_y, u32 main_offset)
2970 {
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         int hsub = fb->format->hsub;
2973         int vsub = fb->format->vsub;
2974         int aux_x = plane_state->aux.x;
2975         int aux_y = plane_state->aux.y;
2976         u32 aux_offset = plane_state->aux.offset;
2977         u32 alignment = intel_surf_alignment(fb, 1);
2978
2979         while (aux_offset >= main_offset && aux_y <= main_y) {
2980                 int x, y;
2981
2982                 if (aux_x == main_x && aux_y == main_y)
2983                         break;
2984
2985                 if (aux_offset == 0)
2986                         break;
2987
2988                 x = aux_x / hsub;
2989                 y = aux_y / vsub;
2990                 aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
2991                                                       aux_offset, aux_offset - alignment);
2992                 aux_x = x * hsub + aux_x % hsub;
2993                 aux_y = y * vsub + aux_y % vsub;
2994         }
2995
2996         if (aux_x != main_x || aux_y != main_y)
2997                 return false;
2998
2999         plane_state->aux.offset = aux_offset;
3000         plane_state->aux.x = aux_x;
3001         plane_state->aux.y = aux_y;
3002
3003         return true;
3004 }
3005
3006 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3007 {
3008         const struct drm_framebuffer *fb = plane_state->base.fb;
3009         unsigned int rotation = plane_state->base.rotation;
3010         int x = plane_state->base.src.x1 >> 16;
3011         int y = plane_state->base.src.y1 >> 16;
3012         int w = drm_rect_width(&plane_state->base.src) >> 16;
3013         int h = drm_rect_height(&plane_state->base.src) >> 16;
3014         int max_width = skl_max_plane_width(fb, 0, rotation);
3015         int max_height = 4096;
3016         u32 alignment, offset, aux_offset = plane_state->aux.offset;
3017
3018         if (w > max_width || h > max_height) {
3019                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3020                               w, h, max_width, max_height);
3021                 return -EINVAL;
3022         }
3023
3024         intel_add_fb_offsets(&x, &y, plane_state, 0);
3025         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
3026         alignment = intel_surf_alignment(fb, 0);
3027
3028         /*
3029          * AUX surface offset is specified as the distance from the
3030          * main surface offset, and it must be non-negative. Make
3031          * sure that is what we will get.
3032          */
3033         if (offset > aux_offset)
3034                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3035                                                   offset, aux_offset & ~(alignment - 1));
3036
3037         /*
3038          * When using an X-tiled surface, the plane blows up
3039          * if the x offset + width exceed the stride.
3040          *
3041          * TODO: linear and Y-tiled seem fine, Yf untested,
3042          */
3043         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3044                 int cpp = fb->format->cpp[0];
3045
3046                 while ((x + w) * cpp > fb->pitches[0]) {
3047                         if (offset == 0) {
3048                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n");
3049                                 return -EINVAL;
3050                         }
3051
3052                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3053                                                           offset, offset - alignment);
3054                 }
3055         }
3056
3057         /*
3058          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3059          * they match with the main surface x/y offsets.
3060          */
3061         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3062             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3063                 while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
3064                         if (offset == 0)
3065                                 break;
3066
3067                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
3068                                                           offset, offset - alignment);
3069                 }
3070
3071                 if (x != plane_state->aux.x || y != plane_state->aux.y) {
3072                         DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
3073                         return -EINVAL;
3074                 }
3075         }
3076
3077         plane_state->main.offset = offset;
3078         plane_state->main.x = x;
3079         plane_state->main.y = y;
3080
3081         return 0;
3082 }
3083
3084 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3085 {
3086         const struct drm_framebuffer *fb = plane_state->base.fb;
3087         unsigned int rotation = plane_state->base.rotation;
3088         int max_width = skl_max_plane_width(fb, 1, rotation);
3089         int max_height = 4096;
3090         int x = plane_state->base.src.x1 >> 17;
3091         int y = plane_state->base.src.y1 >> 17;
3092         int w = drm_rect_width(&plane_state->base.src) >> 17;
3093         int h = drm_rect_height(&plane_state->base.src) >> 17;
3094         u32 offset;
3095
3096         intel_add_fb_offsets(&x, &y, plane_state, 1);
3097         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3098
3099         /* FIXME not quite sure how/if these apply to the chroma plane */
3100         if (w > max_width || h > max_height) {
3101                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
3102                               w, h, max_width, max_height);
3103                 return -EINVAL;
3104         }
3105
3106         plane_state->aux.offset = offset;
3107         plane_state->aux.x = x;
3108         plane_state->aux.y = y;
3109
3110         return 0;
3111 }
3112
3113 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3114 {
3115         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3116         struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
3117         const struct drm_framebuffer *fb = plane_state->base.fb;
3118         int src_x = plane_state->base.src.x1 >> 16;
3119         int src_y = plane_state->base.src.y1 >> 16;
3120         int hsub = fb->format->hsub;
3121         int vsub = fb->format->vsub;
3122         int x = src_x / hsub;
3123         int y = src_y / vsub;
3124         u32 offset;
3125
3126         switch (plane->id) {
3127         case PLANE_PRIMARY:
3128         case PLANE_SPRITE0:
3129                 break;
3130         default:
3131                 DRM_DEBUG_KMS("RC support only on plane 1 and 2\n");
3132                 return -EINVAL;
3133         }
3134
3135         if (crtc->pipe == PIPE_C) {
3136                 DRM_DEBUG_KMS("No RC support on pipe C\n");
3137                 return -EINVAL;
3138         }
3139
3140         if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
3141                 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
3142                               plane_state->base.rotation);
3143                 return -EINVAL;
3144         }
3145
3146         intel_add_fb_offsets(&x, &y, plane_state, 1);
3147         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
3148
3149         plane_state->aux.offset = offset;
3150         plane_state->aux.x = x * hsub + src_x % hsub;
3151         plane_state->aux.y = y * vsub + src_y % vsub;
3152
3153         return 0;
3154 }
3155
3156 int skl_check_plane_surface(struct intel_plane_state *plane_state)
3157 {
3158         const struct drm_framebuffer *fb = plane_state->base.fb;
3159         unsigned int rotation = plane_state->base.rotation;
3160         int ret;
3161
3162         if (!plane_state->base.visible)
3163                 return 0;
3164
3165         /* Rotate src coordinates to match rotated GTT view */
3166         if (drm_rotation_90_or_270(rotation))
3167                 drm_rect_rotate(&plane_state->base.src,
3168                                 fb->width << 16, fb->height << 16,
3169                                 DRM_MODE_ROTATE_270);
3170
3171         /*
3172          * Handle the AUX surface first since
3173          * the main surface setup depends on it.
3174          */
3175         if (fb->format->format == DRM_FORMAT_NV12) {
3176                 ret = skl_check_nv12_aux_surface(plane_state);
3177                 if (ret)
3178                         return ret;
3179         } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
3180                    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) {
3181                 ret = skl_check_ccs_aux_surface(plane_state);
3182                 if (ret)
3183                         return ret;
3184         } else {
3185                 plane_state->aux.offset = ~0xfff;
3186                 plane_state->aux.x = 0;
3187                 plane_state->aux.y = 0;
3188         }
3189
3190         ret = skl_check_main_surface(plane_state);
3191         if (ret)
3192                 return ret;
3193
3194         return 0;
3195 }
3196
3197 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
3198                           const struct intel_plane_state *plane_state)
3199 {
3200         struct drm_i915_private *dev_priv =
3201                 to_i915(plane_state->base.plane->dev);
3202         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3203         const struct drm_framebuffer *fb = plane_state->base.fb;
3204         unsigned int rotation = plane_state->base.rotation;
3205         u32 dspcntr;
3206
3207         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
3208
3209         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
3210             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
3211                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3212
3213         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3214                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3215
3216         if (INTEL_GEN(dev_priv) < 4)
3217                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
3218
3219         switch (fb->format->format) {
3220         case DRM_FORMAT_C8:
3221                 dspcntr |= DISPPLANE_8BPP;
3222                 break;
3223         case DRM_FORMAT_XRGB1555:
3224                 dspcntr |= DISPPLANE_BGRX555;
3225                 break;
3226         case DRM_FORMAT_RGB565:
3227                 dspcntr |= DISPPLANE_BGRX565;
3228                 break;
3229         case DRM_FORMAT_XRGB8888:
3230                 dspcntr |= DISPPLANE_BGRX888;
3231                 break;
3232         case DRM_FORMAT_XBGR8888:
3233                 dspcntr |= DISPPLANE_RGBX888;
3234                 break;
3235         case DRM_FORMAT_XRGB2101010:
3236                 dspcntr |= DISPPLANE_BGRX101010;
3237                 break;
3238         case DRM_FORMAT_XBGR2101010:
3239                 dspcntr |= DISPPLANE_RGBX101010;
3240                 break;
3241         default:
3242                 MISSING_CASE(fb->format->format);
3243                 return 0;
3244         }
3245
3246         if (INTEL_GEN(dev_priv) >= 4 &&
3247             fb->modifier == I915_FORMAT_MOD_X_TILED)
3248                 dspcntr |= DISPPLANE_TILED;
3249
3250         if (rotation & DRM_MODE_ROTATE_180)
3251                 dspcntr |= DISPPLANE_ROTATE_180;
3252
3253         if (rotation & DRM_MODE_REFLECT_X)
3254                 dspcntr |= DISPPLANE_MIRROR;
3255
3256         return dspcntr;
3257 }
3258
3259 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3260 {
3261         struct drm_i915_private *dev_priv =
3262                 to_i915(plane_state->base.plane->dev);
3263         int src_x = plane_state->base.src.x1 >> 16;
3264         int src_y = plane_state->base.src.y1 >> 16;
3265         u32 offset;
3266
3267         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3268
3269         if (INTEL_GEN(dev_priv) >= 4)
3270                 offset = intel_compute_tile_offset(&src_x, &src_y,
3271                                                    plane_state, 0);
3272         else
3273                 offset = 0;
3274
3275         /* HSW/BDW do this automagically in hardware */
3276         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3277                 unsigned int rotation = plane_state->base.rotation;
3278                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3279                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3280
3281                 if (rotation & DRM_MODE_ROTATE_180) {
3282                         src_x += src_w - 1;
3283                         src_y += src_h - 1;
3284                 } else if (rotation & DRM_MODE_REFLECT_X) {
3285                         src_x += src_w - 1;
3286                 }
3287         }
3288
3289         plane_state->main.offset = offset;
3290         plane_state->main.x = src_x;
3291         plane_state->main.y = src_y;
3292
3293         return 0;
3294 }
3295
3296 static void i9xx_update_primary_plane(struct intel_plane *primary,
3297                                       const struct intel_crtc_state *crtc_state,
3298                                       const struct intel_plane_state *plane_state)
3299 {
3300         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3301         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3302         const struct drm_framebuffer *fb = plane_state->base.fb;
3303         enum plane plane = primary->plane;
3304         u32 linear_offset;
3305         u32 dspcntr = plane_state->ctl;
3306         i915_reg_t reg = DSPCNTR(plane);
3307         int x = plane_state->main.x;
3308         int y = plane_state->main.y;
3309         unsigned long irqflags;
3310
3311         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3312
3313         if (INTEL_GEN(dev_priv) >= 4)
3314                 crtc->dspaddr_offset = plane_state->main.offset;
3315         else
3316                 crtc->dspaddr_offset = linear_offset;
3317
3318         crtc->adjusted_x = x;
3319         crtc->adjusted_y = y;
3320
3321         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3322
3323         if (INTEL_GEN(dev_priv) < 4) {
3324                 /* pipesrc and dspsize control the size that is scaled from,
3325                  * which should always be the user's requested size.
3326                  */
3327                 I915_WRITE_FW(DSPSIZE(plane),
3328                               ((crtc_state->pipe_src_h - 1) << 16) |
3329                               (crtc_state->pipe_src_w - 1));
3330                 I915_WRITE_FW(DSPPOS(plane), 0);
3331         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3332                 I915_WRITE_FW(PRIMSIZE(plane),
3333                               ((crtc_state->pipe_src_h - 1) << 16) |
3334                               (crtc_state->pipe_src_w - 1));
3335                 I915_WRITE_FW(PRIMPOS(plane), 0);
3336                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3337         }
3338
3339         I915_WRITE_FW(reg, dspcntr);
3340
3341         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3342         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3343                 I915_WRITE_FW(DSPSURF(plane),
3344                               intel_plane_ggtt_offset(plane_state) +
3345                               crtc->dspaddr_offset);
3346                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3347         } else if (INTEL_GEN(dev_priv) >= 4) {
3348                 I915_WRITE_FW(DSPSURF(plane),
3349                               intel_plane_ggtt_offset(plane_state) +
3350                               crtc->dspaddr_offset);
3351                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3352                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3353         } else {
3354                 I915_WRITE_FW(DSPADDR(plane),
3355                               intel_plane_ggtt_offset(plane_state) +
3356                               crtc->dspaddr_offset);
3357         }
3358         POSTING_READ_FW(reg);
3359
3360         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3361 }
3362
3363 static void i9xx_disable_primary_plane(struct intel_plane *primary,
3364                                        struct intel_crtc *crtc)
3365 {
3366         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3367         enum plane plane = primary->plane;
3368         unsigned long irqflags;
3369
3370         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3371
3372         I915_WRITE_FW(DSPCNTR(plane), 0);
3373         if (INTEL_INFO(dev_priv)->gen >= 4)
3374                 I915_WRITE_FW(DSPSURF(plane), 0);
3375         else
3376                 I915_WRITE_FW(DSPADDR(plane), 0);
3377         POSTING_READ_FW(DSPCNTR(plane));
3378
3379         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3380 }
3381
3382 static u32
3383 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3384 {
3385         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
3386                 return 64;
3387         else
3388                 return intel_tile_width_bytes(fb, plane);
3389 }
3390
3391 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3392 {
3393         struct drm_device *dev = intel_crtc->base.dev;
3394         struct drm_i915_private *dev_priv = to_i915(dev);
3395
3396         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3397         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3398         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3399 }
3400
3401 /*
3402  * This function detaches (aka. unbinds) unused scalers in hardware
3403  */
3404 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3405 {
3406         struct intel_crtc_scaler_state *scaler_state;
3407         int i;
3408
3409         scaler_state = &intel_crtc->config->scaler_state;
3410
3411         /* loop through and disable scalers that aren't in use */
3412         for (i = 0; i < intel_crtc->num_scalers; i++) {
3413                 if (!scaler_state->scalers[i].in_use)
3414                         skl_detach_scaler(intel_crtc, i);
3415         }
3416 }
3417
3418 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3419                      unsigned int rotation)
3420 {
3421         u32 stride;
3422
3423         if (plane >= fb->format->num_planes)
3424                 return 0;
3425
3426         stride = intel_fb_pitch(fb, plane, rotation);
3427
3428         /*
3429          * The stride is either expressed as a multiple of 64 bytes chunks for
3430          * linear buffers or in number of tiles for tiled buffers.
3431          */
3432         if (drm_rotation_90_or_270(rotation))
3433                 stride /= intel_tile_height(fb, plane);
3434         else
3435                 stride /= intel_fb_stride_alignment(fb, plane);
3436
3437         return stride;
3438 }
3439
3440 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3441 {
3442         switch (pixel_format) {
3443         case DRM_FORMAT_C8:
3444                 return PLANE_CTL_FORMAT_INDEXED;
3445         case DRM_FORMAT_RGB565:
3446                 return PLANE_CTL_FORMAT_RGB_565;
3447         case DRM_FORMAT_XBGR8888:
3448                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3449         case DRM_FORMAT_XRGB8888:
3450                 return PLANE_CTL_FORMAT_XRGB_8888;
3451         /*
3452          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3453          * to be already pre-multiplied. We need to add a knob (or a different
3454          * DRM_FORMAT) for user-space to configure that.
3455          */
3456         case DRM_FORMAT_ABGR8888:
3457                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3458                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3459         case DRM_FORMAT_ARGB8888:
3460                 return PLANE_CTL_FORMAT_XRGB_8888 |
3461                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3462         case DRM_FORMAT_XRGB2101010:
3463                 return PLANE_CTL_FORMAT_XRGB_2101010;
3464         case DRM_FORMAT_XBGR2101010:
3465                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3466         case DRM_FORMAT_YUYV:
3467                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3468         case DRM_FORMAT_YVYU:
3469                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3470         case DRM_FORMAT_UYVY:
3471                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3472         case DRM_FORMAT_VYUY:
3473                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3474         default:
3475                 MISSING_CASE(pixel_format);
3476         }
3477
3478         return 0;
3479 }
3480
3481 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3482 {
3483         switch (fb_modifier) {
3484         case DRM_FORMAT_MOD_LINEAR:
3485                 break;
3486         case I915_FORMAT_MOD_X_TILED:
3487                 return PLANE_CTL_TILED_X;
3488         case I915_FORMAT_MOD_Y_TILED:
3489                 return PLANE_CTL_TILED_Y;
3490         case I915_FORMAT_MOD_Y_TILED_CCS:
3491                 return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE;
3492         case I915_FORMAT_MOD_Yf_TILED:
3493                 return PLANE_CTL_TILED_YF;
3494         case I915_FORMAT_MOD_Yf_TILED_CCS:
3495                 return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE;
3496         default:
3497                 MISSING_CASE(fb_modifier);
3498         }
3499
3500         return 0;
3501 }
3502
3503 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3504 {
3505         switch (rotation) {
3506         case DRM_MODE_ROTATE_0:
3507                 break;
3508         /*
3509          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
3510          * while i915 HW rotation is clockwise, thats why this swapping.
3511          */
3512         case DRM_MODE_ROTATE_90:
3513                 return PLANE_CTL_ROTATE_270;
3514         case DRM_MODE_ROTATE_180:
3515                 return PLANE_CTL_ROTATE_180;
3516         case DRM_MODE_ROTATE_270:
3517                 return PLANE_CTL_ROTATE_90;
3518         default:
3519                 MISSING_CASE(rotation);
3520         }
3521
3522         return 0;
3523 }
3524
3525 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3526                   const struct intel_plane_state *plane_state)
3527 {
3528         struct drm_i915_private *dev_priv =
3529                 to_i915(plane_state->base.plane->dev);
3530         const struct drm_framebuffer *fb = plane_state->base.fb;
3531         unsigned int rotation = plane_state->base.rotation;
3532         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3533         u32 plane_ctl;
3534
3535         plane_ctl = PLANE_CTL_ENABLE;
3536
3537         if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
3538                 plane_ctl |=
3539                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3540                         PLANE_CTL_PIPE_CSC_ENABLE |
3541                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3542         }
3543
3544         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3545         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3546         plane_ctl |= skl_plane_ctl_rotation(rotation);
3547
3548         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3549                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3550         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3551                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3552
3553         return plane_ctl;
3554 }
3555
3556 static void skylake_update_primary_plane(struct intel_plane *plane,
3557                                          const struct intel_crtc_state *crtc_state,
3558                                          const struct intel_plane_state *plane_state)
3559 {
3560         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3561         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3562         const struct drm_framebuffer *fb = plane_state->base.fb;
3563         enum plane_id plane_id = plane->id;
3564         enum pipe pipe = plane->pipe;
3565         u32 plane_ctl = plane_state->ctl;
3566         unsigned int rotation = plane_state->base.rotation;
3567         u32 stride = skl_plane_stride(fb, 0, rotation);
3568         u32 aux_stride = skl_plane_stride(fb, 1, rotation);
3569         u32 surf_addr = plane_state->main.offset;
3570         int scaler_id = plane_state->scaler_id;
3571         int src_x = plane_state->main.x;
3572         int src_y = plane_state->main.y;
3573         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3574         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3575         int dst_x = plane_state->base.dst.x1;
3576         int dst_y = plane_state->base.dst.y1;
3577         int dst_w = drm_rect_width(&plane_state->base.dst);
3578         int dst_h = drm_rect_height(&plane_state->base.dst);
3579         unsigned long irqflags;
3580
3581         /* Sizes are 0 based */
3582         src_w--;
3583         src_h--;
3584         dst_w--;
3585         dst_h--;
3586
3587         crtc->dspaddr_offset = surf_addr;
3588
3589         crtc->adjusted_x = src_x;
3590         crtc->adjusted_y = src_y;
3591
3592         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3593
3594         if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3595                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3596                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3597                               PLANE_COLOR_PIPE_CSC_ENABLE |
3598                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3599         }
3600
3601         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3602         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3603         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3604         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3605         I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
3606                       (plane_state->aux.offset - surf_addr) | aux_stride);
3607         I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
3608                       (plane_state->aux.y << 16) | plane_state->aux.x);
3609
3610         if (scaler_id >= 0) {
3611                 uint32_t ps_ctrl = 0;
3612
3613                 WARN_ON(!dst_w || !dst_h);
3614                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3615                         crtc_state->scaler_state.scalers[scaler_id].mode;
3616                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3617                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3618                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3619                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3620                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3621         } else {
3622                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3623         }
3624
3625         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3626                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3627
3628         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3629
3630         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3631 }
3632
3633 static void skylake_disable_primary_plane(struct intel_plane *primary,
3634                                           struct intel_crtc *crtc)
3635 {
3636         struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
3637         enum plane_id plane_id = primary->id;
3638         enum pipe pipe = primary->pipe;
3639         unsigned long irqflags;
3640
3641         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3642
3643         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3644         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3645         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3646
3647         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3648 }
3649
3650 static int
3651 __intel_display_resume(struct drm_device *dev,
3652                        struct drm_atomic_state *state,
3653                        struct drm_modeset_acquire_ctx *ctx)
3654 {
3655         struct drm_crtc_state *crtc_state;
3656         struct drm_crtc *crtc;
3657         int i, ret;
3658
3659         intel_modeset_setup_hw_state(dev, ctx);
3660         i915_redisable_vga(to_i915(dev));
3661
3662         if (!state)
3663                 return 0;
3664
3665         /*
3666          * We've duplicated the state, pointers to the old state are invalid.
3667          *
3668          * Don't attempt to use the old state until we commit the duplicated state.
3669          */
3670         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3671                 /*
3672                  * Force recalculation even if we restore
3673                  * current state. With fast modeset this may not result
3674                  * in a modeset when the state is compatible.
3675                  */
3676                 crtc_state->mode_changed = true;
3677         }
3678
3679         /* ignore any reset values/BIOS leftovers in the WM registers */
3680         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3681                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3682
3683         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3684
3685         WARN_ON(ret == -EDEADLK);
3686         return ret;
3687 }
3688
3689 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3690 {
3691         return intel_has_gpu_reset(dev_priv) &&
3692                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3693 }
3694
3695 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3696 {
3697         struct drm_device *dev = &dev_priv->drm;
3698         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3699         struct drm_atomic_state *state;
3700         int ret;
3701
3702
3703         /* reset doesn't touch the display */
3704         if (!i915.force_reset_modeset_test &&
3705             !gpu_reset_clobbers_display(dev_priv))
3706                 return;
3707
3708         /* We have a modeset vs reset deadlock, defensively unbreak it. */
3709         set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3710         wake_up_all(&dev_priv->gpu_error.wait_queue);
3711
3712         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
3713                 DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
3714                 i915_gem_set_wedged(dev_priv);
3715         }
3716
3717         /*
3718          * Need mode_config.mutex so that we don't
3719          * trample ongoing ->detect() and whatnot.
3720          */
3721         mutex_lock(&dev->mode_config.mutex);
3722         drm_modeset_acquire_init(ctx, 0);
3723         while (1) {
3724                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3725                 if (ret != -EDEADLK)
3726                         break;
3727
3728                 drm_modeset_backoff(ctx);
3729         }
3730         /*
3731          * Disabling the crtcs gracefully seems nicer. Also the
3732          * g33 docs say we should at least disable all the planes.
3733          */
3734         state = drm_atomic_helper_duplicate_state(dev, ctx);
3735         if (IS_ERR(state)) {
3736                 ret = PTR_ERR(state);
3737                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3738                 return;
3739         }
3740
3741         ret = drm_atomic_helper_disable_all(dev, ctx);
3742         if (ret) {
3743                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3744                 drm_atomic_state_put(state);
3745                 return;
3746         }
3747
3748         dev_priv->modeset_restore_state = state;
3749         state->acquire_ctx = ctx;
3750 }
3751
3752 void intel_finish_reset(struct drm_i915_private *dev_priv)
3753 {
3754         struct drm_device *dev = &dev_priv->drm;
3755         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3756         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3757         int ret;
3758
3759         /* reset doesn't touch the display */
3760         if (!i915.force_reset_modeset_test &&
3761             !gpu_reset_clobbers_display(dev_priv))
3762                 return;
3763
3764         if (!state)
3765                 goto unlock;
3766
3767         dev_priv->modeset_restore_state = NULL;
3768
3769         /* reset doesn't touch the display */
3770         if (!gpu_reset_clobbers_display(dev_priv)) {
3771                 /* for testing only restore the display */
3772                 ret = __intel_display_resume(dev, state, ctx);
3773                 if (ret)
3774                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3775         } else {
3776                 /*
3777                  * The display has been reset as well,
3778                  * so need a full re-initialization.
3779                  */
3780                 intel_runtime_pm_disable_interrupts(dev_priv);
3781                 intel_runtime_pm_enable_interrupts(dev_priv);
3782
3783                 intel_pps_unlock_regs_wa(dev_priv);
3784                 intel_modeset_init_hw(dev);
3785
3786                 spin_lock_irq(&dev_priv->irq_lock);
3787                 if (dev_priv->display.hpd_irq_setup)
3788                         dev_priv->display.hpd_irq_setup(dev_priv);
3789                 spin_unlock_irq(&dev_priv->irq_lock);
3790
3791                 ret = __intel_display_resume(dev, state, ctx);
3792                 if (ret)
3793                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3794
3795                 intel_hpd_init(dev_priv);
3796         }
3797
3798         drm_atomic_state_put(state);
3799 unlock:
3800         drm_modeset_drop_locks(ctx);
3801         drm_modeset_acquire_fini(ctx);
3802         mutex_unlock(&dev->mode_config.mutex);
3803
3804         clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
3805 }
3806
3807 static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
3808                                      const struct intel_crtc_state *new_crtc_state)
3809 {
3810         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
3811         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3812
3813         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3814         crtc->base.mode = new_crtc_state->base.mode;
3815
3816         /*
3817          * Update pipe size and adjust fitter if needed: the reason for this is
3818          * that in compute_mode_changes we check the native mode (not the pfit
3819          * mode) to see if we can flip rather than do a full mode set. In the
3820          * fastboot case, we'll flip, but if we don't update the pipesrc and
3821          * pfit state, we'll end up with a big fb scanned out into the wrong
3822          * sized surface.
3823          */
3824
3825         I915_WRITE(PIPESRC(crtc->pipe),
3826                    ((new_crtc_state->pipe_src_w - 1) << 16) |
3827                    (new_crtc_state->pipe_src_h - 1));
3828
3829         /* on skylake this is done by detaching scalers */
3830         if (INTEL_GEN(dev_priv) >= 9) {
3831                 skl_detach_scalers(crtc);
3832
3833                 if (new_crtc_state->pch_pfit.enabled)
3834                         skylake_pfit_enable(crtc);
3835         } else if (HAS_PCH_SPLIT(dev_priv)) {
3836                 if (new_crtc_state->pch_pfit.enabled)
3837                         ironlake_pfit_enable(crtc);
3838                 else if (old_crtc_state->pch_pfit.enabled)
3839                         ironlake_pfit_disable(crtc, true);
3840         }
3841 }
3842
3843 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3844 {
3845         struct drm_device *dev = crtc->base.dev;
3846         struct drm_i915_private *dev_priv = to_i915(dev);
3847         int pipe = crtc->pipe;
3848         i915_reg_t reg;
3849         u32 temp;
3850
3851         /* enable normal train */
3852         reg = FDI_TX_CTL(pipe);
3853         temp = I915_READ(reg);
3854         if (IS_IVYBRIDGE(dev_priv)) {
3855                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3856                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3857         } else {
3858                 temp &= ~FDI_LINK_TRAIN_NONE;
3859                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3860         }
3861         I915_WRITE(reg, temp);
3862
3863         reg = FDI_RX_CTL(pipe);
3864         temp = I915_READ(reg);
3865         if (HAS_PCH_CPT(dev_priv)) {
3866                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3867                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3868         } else {
3869                 temp &= ~FDI_LINK_TRAIN_NONE;
3870                 temp |= FDI_LINK_TRAIN_NONE;
3871         }
3872         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3873
3874         /* wait one idle pattern time */
3875         POSTING_READ(reg);
3876         udelay(1000);
3877
3878         /* IVB wants error correction enabled */
3879         if (IS_IVYBRIDGE(dev_priv))
3880                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3881                            FDI_FE_ERRC_ENABLE);
3882 }
3883
3884 /* The FDI link training functions for ILK/Ibexpeak. */
3885 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3886                                     const struct intel_crtc_state *crtc_state)
3887 {
3888         struct drm_device *dev = crtc->base.dev;
3889         struct drm_i915_private *dev_priv = to_i915(dev);
3890         int pipe = crtc->pipe;
3891         i915_reg_t reg;
3892         u32 temp, tries;
3893
3894         /* FDI needs bits from pipe first */
3895         assert_pipe_enabled(dev_priv, pipe);
3896
3897         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3898            for train result */
3899         reg = FDI_RX_IMR(pipe);
3900         temp = I915_READ(reg);
3901         temp &= ~FDI_RX_SYMBOL_LOCK;
3902         temp &= ~FDI_RX_BIT_LOCK;
3903         I915_WRITE(reg, temp);
3904         I915_READ(reg);
3905         udelay(150);
3906
3907         /* enable CPU FDI TX and PCH FDI RX */
3908         reg = FDI_TX_CTL(pipe);
3909         temp = I915_READ(reg);
3910         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3911         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3912         temp &= ~FDI_LINK_TRAIN_NONE;
3913         temp |= FDI_LINK_TRAIN_PATTERN_1;
3914         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3915
3916         reg = FDI_RX_CTL(pipe);
3917         temp = I915_READ(reg);
3918         temp &= ~FDI_LINK_TRAIN_NONE;
3919         temp |= FDI_LINK_TRAIN_PATTERN_1;
3920         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3921
3922         POSTING_READ(reg);
3923         udelay(150);
3924
3925         /* Ironlake workaround, enable clock pointer after FDI enable*/
3926         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3927         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3928                    FDI_RX_PHASE_SYNC_POINTER_EN);
3929
3930         reg = FDI_RX_IIR(pipe);
3931         for (tries = 0; tries < 5; tries++) {
3932                 temp = I915_READ(reg);
3933                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3934
3935                 if ((temp & FDI_RX_BIT_LOCK)) {
3936                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3937                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3938                         break;
3939                 }
3940         }
3941         if (tries == 5)
3942                 DRM_ERROR("FDI train 1 fail!\n");
3943
3944         /* Train 2 */
3945         reg = FDI_TX_CTL(pipe);
3946         temp = I915_READ(reg);
3947         temp &= ~FDI_LINK_TRAIN_NONE;
3948         temp |= FDI_LINK_TRAIN_PATTERN_2;
3949         I915_WRITE(reg, temp);
3950
3951         reg = FDI_RX_CTL(pipe);
3952         temp = I915_READ(reg);
3953         temp &= ~FDI_LINK_TRAIN_NONE;
3954         temp |= FDI_LINK_TRAIN_PATTERN_2;
3955         I915_WRITE(reg, temp);
3956
3957         POSTING_READ(reg);
3958         udelay(150);
3959
3960         reg = FDI_RX_IIR(pipe);
3961         for (tries = 0; tries < 5; tries++) {
3962                 temp = I915_READ(reg);
3963                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3964
3965                 if (temp & FDI_RX_SYMBOL_LOCK) {
3966                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3967                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3968                         break;
3969                 }
3970         }
3971         if (tries == 5)
3972                 DRM_ERROR("FDI train 2 fail!\n");
3973
3974         DRM_DEBUG_KMS("FDI train done\n");
3975
3976 }
3977
3978 static const int snb_b_fdi_train_param[] = {
3979         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3980         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3981         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3982         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3983 };
3984
3985 /* The FDI link training functions for SNB/Cougarpoint. */
3986 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3987                                 const struct intel_crtc_state *crtc_state)
3988 {
3989         struct drm_device *dev = crtc->base.dev;
3990         struct drm_i915_private *dev_priv = to_i915(dev);
3991         int pipe = crtc->pipe;
3992         i915_reg_t reg;
3993         u32 temp, i, retry;
3994
3995         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3996            for train result */
3997         reg = FDI_RX_IMR(pipe);
3998         temp = I915_READ(reg);
3999         temp &= ~FDI_RX_SYMBOL_LOCK;
4000         temp &= ~FDI_RX_BIT_LOCK;
4001         I915_WRITE(reg, temp);
4002
4003         POSTING_READ(reg);
4004         udelay(150);
4005
4006         /* enable CPU FDI TX and PCH FDI RX */
4007         reg = FDI_TX_CTL(pipe);
4008         temp = I915_READ(reg);
4009         temp &= ~FDI_DP_PORT_WIDTH_MASK;
4010         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4011         temp &= ~FDI_LINK_TRAIN_NONE;
4012         temp |= FDI_LINK_TRAIN_PATTERN_1;
4013         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4014         /* SNB-B */
4015         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4016         I915_WRITE(reg, temp | FDI_TX_ENABLE);
4017
4018         I915_WRITE(FDI_RX_MISC(pipe),
4019                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4020
4021         reg = FDI_RX_CTL(pipe);
4022         temp = I915_READ(reg);
4023         if (HAS_PCH_CPT(dev_priv)) {
4024                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4025                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4026         } else {
4027                 temp &= ~FDI_LINK_TRAIN_NONE;
4028                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4029         }
4030         I915_WRITE(reg, temp | FDI_RX_ENABLE);
4031
4032         POSTING_READ(reg);
4033         udelay(150);
4034
4035         for (i = 0; i < 4; i++) {
4036                 reg = FDI_TX_CTL(pipe);
4037                 temp = I915_READ(reg);
4038                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4039                 temp |= snb_b_fdi_train_param[i];
4040                 I915_WRITE(reg, temp);
4041
4042                 POSTING_READ(reg);
4043                 udelay(500);
4044
4045                 for (retry = 0; retry < 5; retry++) {
4046                         reg = FDI_RX_IIR(pipe);
4047                         temp = I915_READ(reg);
4048                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4049                         if (temp & FDI_RX_BIT_LOCK) {
4050                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4051                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
4052                                 break;
4053                         }
4054                         udelay(50);
4055                 }
4056                 if (retry < 5)
4057                         break;
4058         }
4059         if (i == 4)
4060                 DRM_ERROR("FDI train 1 fail!\n");
4061
4062         /* Train 2 */
4063         reg = FDI_TX_CTL(pipe);
4064         temp = I915_READ(reg);
4065         temp &= ~FDI_LINK_TRAIN_NONE;
4066         temp |= FDI_LINK_TRAIN_PATTERN_2;
4067         if (IS_GEN6(dev_priv)) {
4068                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4069                 /* SNB-B */
4070                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
4071         }
4072         I915_WRITE(reg, temp);
4073
4074         reg = FDI_RX_CTL(pipe);
4075         temp = I915_READ(reg);
4076         if (HAS_PCH_CPT(dev_priv)) {
4077                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4078                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4079         } else {
4080                 temp &= ~FDI_LINK_TRAIN_NONE;
4081                 temp |= FDI_LINK_TRAIN_PATTERN_2;
4082         }
4083         I915_WRITE(reg, temp);
4084
4085         POSTING_READ(reg);
4086         udelay(150);
4087
4088         for (i = 0; i < 4; i++) {
4089                 reg = FDI_TX_CTL(pipe);
4090                 temp = I915_READ(reg);
4091                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4092                 temp |= snb_b_fdi_train_param[i];
4093                 I915_WRITE(reg, temp);
4094
4095                 POSTING_READ(reg);
4096                 udelay(500);
4097
4098                 for (retry = 0; retry < 5; retry++) {
4099                         reg = FDI_RX_IIR(pipe);
4100                         temp = I915_READ(reg);
4101                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4102                         if (temp & FDI_RX_SYMBOL_LOCK) {
4103                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4104                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
4105                                 break;
4106                         }
4107                         udelay(50);
4108                 }
4109                 if (retry < 5)
4110                         break;
4111         }
4112         if (i == 4)
4113                 DRM_ERROR("FDI train 2 fail!\n");
4114
4115         DRM_DEBUG_KMS("FDI train done.\n");
4116 }
4117
4118 /* Manual link training for Ivy Bridge A0 parts */
4119 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
4120                                       const struct intel_crtc_state *crtc_state)
4121 {
4122         struct drm_device *dev = crtc->base.dev;
4123         struct drm_i915_private *dev_priv = to_i915(dev);
4124         int pipe = crtc->pipe;
4125         i915_reg_t reg;
4126         u32 temp, i, j;
4127
4128         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4129            for train result */
4130         reg = FDI_RX_IMR(pipe);
4131         temp = I915_READ(reg);
4132         temp &= ~FDI_RX_SYMBOL_LOCK;
4133         temp &= ~FDI_RX_BIT_LOCK;
4134         I915_WRITE(reg, temp);
4135
4136         POSTING_READ(reg);
4137         udelay(150);
4138
4139         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4140                       I915_READ(FDI_RX_IIR(pipe)));
4141
4142         /* Try each vswing and preemphasis setting twice before moving on */
4143         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4144                 /* disable first in case we need to retry */
4145                 reg = FDI_TX_CTL(pipe);
4146                 temp = I915_READ(reg);
4147                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4148                 temp &= ~FDI_TX_ENABLE;
4149                 I915_WRITE(reg, temp);
4150
4151                 reg = FDI_RX_CTL(pipe);
4152                 temp = I915_READ(reg);
4153                 temp &= ~FDI_LINK_TRAIN_AUTO;
4154                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4155                 temp &= ~FDI_RX_ENABLE;
4156                 I915_WRITE(reg, temp);
4157
4158                 /* enable CPU FDI TX and PCH FDI RX */
4159                 reg = FDI_TX_CTL(pipe);
4160                 temp = I915_READ(reg);
4161                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4162                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4163                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4164                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4165                 temp |= snb_b_fdi_train_param[j/2];
4166                 temp |= FDI_COMPOSITE_SYNC;
4167                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4168
4169                 I915_WRITE(FDI_RX_MISC(pipe),
4170                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4171
4172                 reg = FDI_RX_CTL(pipe);
4173                 temp = I915_READ(reg);
4174                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4175                 temp |= FDI_COMPOSITE_SYNC;
4176                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4177
4178                 POSTING_READ(reg);
4179                 udelay(1); /* should be 0.5us */
4180
4181                 for (i = 0; i < 4; i++) {
4182                         reg = FDI_RX_IIR(pipe);
4183                         temp = I915_READ(reg);
4184                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4185
4186                         if (temp & FDI_RX_BIT_LOCK ||
4187                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4188                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4189                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4190                                               i);
4191                                 break;
4192                         }
4193                         udelay(1); /* should be 0.5us */
4194                 }
4195                 if (i == 4) {
4196                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4197                         continue;
4198                 }
4199
4200                 /* Train 2 */
4201                 reg = FDI_TX_CTL(pipe);
4202                 temp = I915_READ(reg);
4203                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4204                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4205                 I915_WRITE(reg, temp);
4206
4207                 reg = FDI_RX_CTL(pipe);
4208                 temp = I915_READ(reg);
4209                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4210                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4211                 I915_WRITE(reg, temp);
4212
4213                 POSTING_READ(reg);
4214                 udelay(2); /* should be 1.5us */
4215
4216                 for (i = 0; i < 4; i++) {
4217                         reg = FDI_RX_IIR(pipe);
4218                         temp = I915_READ(reg);
4219                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4220
4221                         if (temp & FDI_RX_SYMBOL_LOCK ||
4222                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4223                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4224                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4225                                               i);
4226                                 goto train_done;
4227                         }
4228                         udelay(2); /* should be 1.5us */
4229                 }
4230                 if (i == 4)
4231                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4232         }
4233
4234 train_done:
4235         DRM_DEBUG_KMS("FDI train done.\n");
4236 }
4237
4238 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4239 {
4240         struct drm_device *dev = intel_crtc->base.dev;
4241         struct drm_i915_private *dev_priv = to_i915(dev);
4242         int pipe = intel_crtc->pipe;
4243         i915_reg_t reg;
4244         u32 temp;
4245
4246         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4247         reg = FDI_RX_CTL(pipe);
4248         temp = I915_READ(reg);
4249         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4250         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4251         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4252         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4253
4254         POSTING_READ(reg);
4255         udelay(200);
4256
4257         /* Switch from Rawclk to PCDclk */
4258         temp = I915_READ(reg);
4259         I915_WRITE(reg, temp | FDI_PCDCLK);
4260
4261         POSTING_READ(reg);
4262         udelay(200);
4263
4264         /* Enable CPU FDI TX PLL, always on for Ironlake */
4265         reg = FDI_TX_CTL(pipe);
4266         temp = I915_READ(reg);
4267         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4268                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4269
4270                 POSTING_READ(reg);
4271                 udelay(100);
4272         }
4273 }
4274
4275 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4276 {
4277         struct drm_device *dev = intel_crtc->base.dev;
4278         struct drm_i915_private *dev_priv = to_i915(dev);
4279         int pipe = intel_crtc->pipe;
4280         i915_reg_t reg;
4281         u32 temp;
4282
4283         /* Switch from PCDclk to Rawclk */
4284         reg = FDI_RX_CTL(pipe);
4285         temp = I915_READ(reg);
4286         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4287
4288         /* Disable CPU FDI TX PLL */
4289         reg = FDI_TX_CTL(pipe);
4290         temp = I915_READ(reg);
4291         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4292
4293         POSTING_READ(reg);
4294         udelay(100);
4295
4296         reg = FDI_RX_CTL(pipe);
4297         temp = I915_READ(reg);
4298         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4299
4300         /* Wait for the clocks to turn off. */
4301         POSTING_READ(reg);
4302         udelay(100);
4303 }
4304
4305 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4306 {
4307         struct drm_device *dev = crtc->dev;
4308         struct drm_i915_private *dev_priv = to_i915(dev);
4309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4310         int pipe = intel_crtc->pipe;
4311         i915_reg_t reg;
4312         u32 temp;
4313
4314         /* disable CPU FDI tx and PCH FDI rx */
4315         reg = FDI_TX_CTL(pipe);
4316         temp = I915_READ(reg);
4317         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4318         POSTING_READ(reg);
4319
4320         reg = FDI_RX_CTL(pipe);
4321         temp = I915_READ(reg);
4322         temp &= ~(0x7 << 16);
4323         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4324         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4325
4326         POSTING_READ(reg);
4327         udelay(100);
4328
4329         /* Ironlake workaround, disable clock pointer after downing FDI */
4330         if (HAS_PCH_IBX(dev_priv))
4331                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4332
4333         /* still set train pattern 1 */
4334         reg = FDI_TX_CTL(pipe);
4335         temp = I915_READ(reg);
4336         temp &= ~FDI_LINK_TRAIN_NONE;
4337         temp |= FDI_LINK_TRAIN_PATTERN_1;
4338         I915_WRITE(reg, temp);
4339
4340         reg = FDI_RX_CTL(pipe);
4341         temp = I915_READ(reg);
4342         if (HAS_PCH_CPT(dev_priv)) {
4343                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4344                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4345         } else {
4346                 temp &= ~FDI_LINK_TRAIN_NONE;
4347                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4348         }
4349         /* BPC in FDI rx is consistent with that in PIPECONF */
4350         temp &= ~(0x07 << 16);
4351         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4352         I915_WRITE(reg, temp);
4353
4354         POSTING_READ(reg);
4355         udelay(100);
4356 }
4357
4358 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4359 {
4360         struct drm_crtc *crtc;
4361         bool cleanup_done;
4362
4363         drm_for_each_crtc(crtc, &dev_priv->drm) {
4364                 struct drm_crtc_commit *commit;
4365                 spin_lock(&crtc->commit_lock);
4366                 commit = list_first_entry_or_null(&crtc->commit_list,
4367                                                   struct drm_crtc_commit, commit_entry);
4368                 cleanup_done = commit ?
4369                         try_wait_for_completion(&commit->cleanup_done) : true;
4370                 spin_unlock(&crtc->commit_lock);
4371
4372                 if (cleanup_done)
4373                         continue;
4374
4375                 drm_crtc_wait_one_vblank(crtc);
4376
4377                 return true;
4378         }
4379
4380         return false;
4381 }
4382
4383 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4384 {
4385         u32 temp;
4386
4387         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4388
4389         mutex_lock(&dev_priv->sb_lock);
4390
4391         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4392         temp |= SBI_SSCCTL_DISABLE;
4393         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4394
4395         mutex_unlock(&dev_priv->sb_lock);
4396 }
4397
4398 /* Program iCLKIP clock to the desired frequency */
4399 static void lpt_program_iclkip(struct intel_crtc *crtc)
4400 {
4401         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4402         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4403         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4404         u32 temp;
4405
4406         lpt_disable_iclkip(dev_priv);
4407
4408         /* The iCLK virtual clock root frequency is in MHz,
4409          * but the adjusted_mode->crtc_clock in in KHz. To get the
4410          * divisors, it is necessary to divide one by another, so we
4411          * convert the virtual clock precision to KHz here for higher
4412          * precision.
4413          */
4414         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4415                 u32 iclk_virtual_root_freq = 172800 * 1000;
4416                 u32 iclk_pi_range = 64;
4417                 u32 desired_divisor;
4418
4419                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4420                                                     clock << auxdiv);
4421                 divsel = (desired_divisor / iclk_pi_range) - 2;
4422                 phaseinc = desired_divisor % iclk_pi_range;
4423
4424                 /*
4425                  * Near 20MHz is a corner case which is
4426                  * out of range for the 7-bit divisor
4427                  */
4428                 if (divsel <= 0x7f)
4429                         break;
4430         }
4431
4432         /* This should not happen with any sane values */
4433         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4434                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4435         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4436                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4437
4438         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4439                         clock,
4440                         auxdiv,
4441                         divsel,
4442                         phasedir,
4443                         phaseinc);
4444
4445         mutex_lock(&dev_priv->sb_lock);
4446
4447         /* Program SSCDIVINTPHASE6 */
4448         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4449         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4450         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4451         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4452         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4453         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4454         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4455         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4456
4457         /* Program SSCAUXDIV */
4458         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4459         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4460         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4461         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4462
4463         /* Enable modulator and associated divider */
4464         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4465         temp &= ~SBI_SSCCTL_DISABLE;
4466         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4467
4468         mutex_unlock(&dev_priv->sb_lock);
4469
4470         /* Wait for initialization time */
4471         udelay(24);
4472
4473         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4474 }
4475
4476 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4477 {
4478         u32 divsel, phaseinc, auxdiv;
4479         u32 iclk_virtual_root_freq = 172800 * 1000;
4480         u32 iclk_pi_range = 64;
4481         u32 desired_divisor;
4482         u32 temp;
4483
4484         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4485                 return 0;
4486
4487         mutex_lock(&dev_priv->sb_lock);
4488
4489         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4490         if (temp & SBI_SSCCTL_DISABLE) {
4491                 mutex_unlock(&dev_priv->sb_lock);
4492                 return 0;
4493         }
4494
4495         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4496         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4497                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4498         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4499                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4500
4501         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4502         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4503                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4504
4505         mutex_unlock(&dev_priv->sb_lock);
4506
4507         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4508
4509         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4510                                  desired_divisor << auxdiv);
4511 }
4512
4513 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4514                                                 enum pipe pch_transcoder)
4515 {
4516         struct drm_device *dev = crtc->base.dev;
4517         struct drm_i915_private *dev_priv = to_i915(dev);
4518         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4519
4520         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4521                    I915_READ(HTOTAL(cpu_transcoder)));
4522         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4523                    I915_READ(HBLANK(cpu_transcoder)));
4524         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4525                    I915_READ(HSYNC(cpu_transcoder)));
4526
4527         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4528                    I915_READ(VTOTAL(cpu_transcoder)));
4529         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4530                    I915_READ(VBLANK(cpu_transcoder)));
4531         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4532                    I915_READ(VSYNC(cpu_transcoder)));
4533         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4534                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4535 }
4536
4537 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4538 {
4539         struct drm_i915_private *dev_priv = to_i915(dev);
4540         uint32_t temp;
4541
4542         temp = I915_READ(SOUTH_CHICKEN1);
4543         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4544                 return;
4545
4546         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4547         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4548
4549         temp &= ~FDI_BC_BIFURCATION_SELECT;
4550         if (enable)
4551                 temp |= FDI_BC_BIFURCATION_SELECT;
4552
4553         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4554         I915_WRITE(SOUTH_CHICKEN1, temp);
4555         POSTING_READ(SOUTH_CHICKEN1);
4556 }
4557
4558 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4559 {
4560         struct drm_device *dev = intel_crtc->base.dev;
4561
4562         switch (intel_crtc->pipe) {
4563         case PIPE_A:
4564                 break;
4565         case PIPE_B:
4566                 if (intel_crtc->config->fdi_lanes > 2)
4567                         cpt_set_fdi_bc_bifurcation(dev, false);
4568                 else
4569                         cpt_set_fdi_bc_bifurcation(dev, true);
4570
4571                 break;
4572         case PIPE_C:
4573                 cpt_set_fdi_bc_bifurcation(dev, true);
4574
4575                 break;
4576         default:
4577                 BUG();
4578         }
4579 }
4580
4581 /* Return which DP Port should be selected for Transcoder DP control */
4582 static enum port
4583 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4584 {
4585         struct drm_device *dev = crtc->base.dev;
4586         struct intel_encoder *encoder;
4587
4588         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4589                 if (encoder->type == INTEL_OUTPUT_DP ||
4590                     encoder->type == INTEL_OUTPUT_EDP)
4591                         return enc_to_dig_port(&encoder->base)->port;
4592         }
4593
4594         return -1;
4595 }
4596
4597 /*
4598  * Enable PCH resources required for PCH ports:
4599  *   - PCH PLLs
4600  *   - FDI training & RX/TX
4601  *   - update transcoder timings
4602  *   - DP transcoding bits
4603  *   - transcoder
4604  */
4605 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4606 {
4607         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4608         struct drm_device *dev = crtc->base.dev;
4609         struct drm_i915_private *dev_priv = to_i915(dev);
4610         int pipe = crtc->pipe;
4611         u32 temp;
4612
4613         assert_pch_transcoder_disabled(dev_priv, pipe);
4614
4615         if (IS_IVYBRIDGE(dev_priv))
4616                 ivybridge_update_fdi_bc_bifurcation(crtc);
4617
4618         /* Write the TU size bits before fdi link training, so that error
4619          * detection works. */
4620         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4621                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4622
4623         /* For PCH output, training FDI link */
4624         dev_priv->display.fdi_link_train(crtc, crtc_state);
4625
4626         /* We need to program the right clock selection before writing the pixel
4627          * mutliplier into the DPLL. */
4628         if (HAS_PCH_CPT(dev_priv)) {
4629                 u32 sel;
4630
4631                 temp = I915_READ(PCH_DPLL_SEL);
4632                 temp |= TRANS_DPLL_ENABLE(pipe);
4633                 sel = TRANS_DPLLB_SEL(pipe);
4634                 if (crtc_state->shared_dpll ==
4635                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4636                         temp |= sel;
4637                 else
4638                         temp &= ~sel;
4639                 I915_WRITE(PCH_DPLL_SEL, temp);
4640         }
4641
4642         /* XXX: pch pll's can be enabled any time before we enable the PCH
4643          * transcoder, and we actually should do this to not upset any PCH
4644          * transcoder that already use the clock when we share it.
4645          *
4646          * Note that enable_shared_dpll tries to do the right thing, but
4647          * get_shared_dpll unconditionally resets the pll - we need that to have
4648          * the right LVDS enable sequence. */
4649         intel_enable_shared_dpll(crtc);
4650
4651         /* set transcoder timing, panel must allow it */
4652         assert_panel_unlocked(dev_priv, pipe);
4653         ironlake_pch_transcoder_set_timings(crtc, pipe);
4654
4655         intel_fdi_normal_train(crtc);
4656
4657         /* For PCH DP, enable TRANS_DP_CTL */
4658         if (HAS_PCH_CPT(dev_priv) &&
4659             intel_crtc_has_dp_encoder(crtc_state)) {
4660                 const struct drm_display_mode *adjusted_mode =
4661                         &crtc_state->base.adjusted_mode;
4662                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4663                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4664                 temp = I915_READ(reg);
4665                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4666                           TRANS_DP_SYNC_MASK |
4667                           TRANS_DP_BPC_MASK);
4668                 temp |= TRANS_DP_OUTPUT_ENABLE;
4669                 temp |= bpc << 9; /* same format but at 11:9 */
4670
4671                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4672                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4673                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4674                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4675
4676                 switch (intel_trans_dp_port_sel(crtc)) {
4677                 case PORT_B:
4678                         temp |= TRANS_DP_PORT_SEL_B;
4679                         break;
4680                 case PORT_C:
4681                         temp |= TRANS_DP_PORT_SEL_C;
4682                         break;
4683                 case PORT_D:
4684                         temp |= TRANS_DP_PORT_SEL_D;
4685                         break;
4686                 default:
4687                         BUG();
4688                 }
4689
4690                 I915_WRITE(reg, temp);
4691         }
4692
4693         ironlake_enable_pch_transcoder(dev_priv, pipe);
4694 }
4695
4696 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4697 {
4698         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4699         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4700         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4701
4702         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4703
4704         lpt_program_iclkip(crtc);
4705
4706         /* Set transcoder timing. */
4707         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4708
4709         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4710 }
4711
4712 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4713 {
4714         struct drm_i915_private *dev_priv = to_i915(dev);
4715         i915_reg_t dslreg = PIPEDSL(pipe);
4716         u32 temp;
4717
4718         temp = I915_READ(dslreg);
4719         udelay(500);
4720         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4721                 if (wait_for(I915_READ(dslreg) != temp, 5))
4722                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4723         }
4724 }
4725
4726 static int
4727 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4728                   unsigned int scaler_user, int *scaler_id,
4729                   int src_w, int src_h, int dst_w, int dst_h)
4730 {
4731         struct intel_crtc_scaler_state *scaler_state =
4732                 &crtc_state->scaler_state;
4733         struct intel_crtc *intel_crtc =
4734                 to_intel_crtc(crtc_state->base.crtc);
4735         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4736         const struct drm_display_mode *adjusted_mode =
4737                 &crtc_state->base.adjusted_mode;
4738         int need_scaling;
4739
4740         /*
4741          * Src coordinates are already rotated by 270 degrees for
4742          * the 90/270 degree plane rotation cases (to match the
4743          * GTT mapping), hence no need to account for rotation here.
4744          */
4745         need_scaling = src_w != dst_w || src_h != dst_h;
4746
4747         if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
4748                 need_scaling = true;
4749
4750         /*
4751          * Scaling/fitting not supported in IF-ID mode in GEN9+
4752          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
4753          * Once NV12 is enabled, handle it here while allocating scaler
4754          * for NV12.
4755          */
4756         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
4757             need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4758                 DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
4759                 return -EINVAL;
4760         }
4761
4762         /*
4763          * if plane is being disabled or scaler is no more required or force detach
4764          *  - free scaler binded to this plane/crtc
4765          *  - in order to do this, update crtc->scaler_usage
4766          *
4767          * Here scaler state in crtc_state is set free so that
4768          * scaler can be assigned to other user. Actual register
4769          * update to free the scaler is done in plane/panel-fit programming.
4770          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4771          */
4772         if (force_detach || !need_scaling) {
4773                 if (*scaler_id >= 0) {
4774                         scaler_state->scaler_users &= ~(1 << scaler_user);
4775                         scaler_state->scalers[*scaler_id].in_use = 0;
4776
4777                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4778                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4779                                 intel_crtc->pipe, scaler_user, *scaler_id,
4780                                 scaler_state->scaler_users);
4781                         *scaler_id = -1;
4782                 }
4783                 return 0;
4784         }
4785
4786         /* range checks */
4787         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4788                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4789
4790                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4791                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4792                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4793                         "size is out of scaler range\n",
4794                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4795                 return -EINVAL;
4796         }
4797
4798         /* mark this plane as a scaler user in crtc_state */
4799         scaler_state->scaler_users |= (1 << scaler_user);
4800         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4801                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4802                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4803                 scaler_state->scaler_users);
4804
4805         return 0;
4806 }
4807
4808 /**
4809  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4810  *
4811  * @state: crtc's scaler state
4812  *
4813  * Return
4814  *     0 - scaler_usage updated successfully
4815  *    error - requested scaling cannot be supported or other error condition
4816  */
4817 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4818 {
4819         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4820
4821         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4822                 &state->scaler_state.scaler_id,
4823                 state->pipe_src_w, state->pipe_src_h,
4824                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4825 }
4826
4827 /**
4828  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4829  *
4830  * @state: crtc's scaler state
4831  * @plane_state: atomic plane state to update
4832  *
4833  * Return
4834  *     0 - scaler_usage updated successfully
4835  *    error - requested scaling cannot be supported or other error condition
4836  */
4837 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4838                                    struct intel_plane_state *plane_state)
4839 {
4840
4841         struct intel_plane *intel_plane =
4842                 to_intel_plane(plane_state->base.plane);
4843         struct drm_framebuffer *fb = plane_state->base.fb;
4844         int ret;
4845
4846         bool force_detach = !fb || !plane_state->base.visible;
4847
4848         ret = skl_update_scaler(crtc_state, force_detach,
4849                                 drm_plane_index(&intel_plane->base),
4850                                 &plane_state->scaler_id,
4851                                 drm_rect_width(&plane_state->base.src) >> 16,
4852                                 drm_rect_height(&plane_state->base.src) >> 16,
4853                                 drm_rect_width(&plane_state->base.dst),
4854                                 drm_rect_height(&plane_state->base.dst));
4855
4856         if (ret || plane_state->scaler_id < 0)
4857                 return ret;
4858
4859         /* check colorkey */
4860         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4861                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4862                               intel_plane->base.base.id,
4863                               intel_plane->base.name);
4864                 return -EINVAL;
4865         }
4866
4867         /* Check src format */
4868         switch (fb->format->format) {
4869         case DRM_FORMAT_RGB565:
4870         case DRM_FORMAT_XBGR8888:
4871         case DRM_FORMAT_XRGB8888:
4872         case DRM_FORMAT_ABGR8888:
4873         case DRM_FORMAT_ARGB8888:
4874         case DRM_FORMAT_XRGB2101010:
4875         case DRM_FORMAT_XBGR2101010:
4876         case DRM_FORMAT_YUYV:
4877         case DRM_FORMAT_YVYU:
4878         case DRM_FORMAT_UYVY:
4879         case DRM_FORMAT_VYUY:
4880                 break;
4881         default:
4882                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4883                               intel_plane->base.base.id, intel_plane->base.name,
4884                               fb->base.id, fb->format->format);
4885                 return -EINVAL;
4886         }
4887
4888         return 0;
4889 }
4890
4891 static void skylake_scaler_disable(struct intel_crtc *crtc)
4892 {
4893         int i;
4894
4895         for (i = 0; i < crtc->num_scalers; i++)
4896                 skl_detach_scaler(crtc, i);
4897 }
4898
4899 static void skylake_pfit_enable(struct intel_crtc *crtc)
4900 {
4901         struct drm_device *dev = crtc->base.dev;
4902         struct drm_i915_private *dev_priv = to_i915(dev);
4903         int pipe = crtc->pipe;
4904         struct intel_crtc_scaler_state *scaler_state =
4905                 &crtc->config->scaler_state;
4906
4907         if (crtc->config->pch_pfit.enabled) {
4908                 int id;
4909
4910                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4911                         return;
4912
4913                 id = scaler_state->scaler_id;
4914                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4915                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4916                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4917                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4918         }
4919 }
4920
4921 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4922 {
4923         struct drm_device *dev = crtc->base.dev;
4924         struct drm_i915_private *dev_priv = to_i915(dev);
4925         int pipe = crtc->pipe;
4926
4927         if (crtc->config->pch_pfit.enabled) {
4928                 /* Force use of hard-coded filter coefficients
4929                  * as some pre-programmed values are broken,
4930                  * e.g. x201.
4931                  */
4932                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4933                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4934                                                  PF_PIPE_SEL_IVB(pipe));
4935                 else
4936                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4937                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4938                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4939         }
4940 }
4941
4942 void hsw_enable_ips(struct intel_crtc *crtc)
4943 {
4944         struct drm_device *dev = crtc->base.dev;
4945         struct drm_i915_private *dev_priv = to_i915(dev);
4946
4947         if (!crtc->config->ips_enabled)
4948                 return;
4949
4950         /*
4951          * We can only enable IPS after we enable a plane and wait for a vblank
4952          * This function is called from post_plane_update, which is run after
4953          * a vblank wait.
4954          */
4955
4956         assert_plane_enabled(dev_priv, crtc->plane);
4957         if (IS_BROADWELL(dev_priv)) {
4958                 mutex_lock(&dev_priv->rps.hw_lock);
4959                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
4960                                                 IPS_ENABLE | IPS_PCODE_CONTROL));
4961                 mutex_unlock(&dev_priv->rps.hw_lock);
4962                 /* Quoting Art Runyan: "its not safe to expect any particular
4963                  * value in IPS_CTL bit 31 after enabling IPS through the
4964                  * mailbox." Moreover, the mailbox may return a bogus state,
4965                  * so we need to just enable it and continue on.
4966                  */
4967         } else {
4968                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4969                 /* The bit only becomes 1 in the next vblank, so this wait here
4970                  * is essentially intel_wait_for_vblank. If we don't have this
4971                  * and don't wait for vblanks until the end of crtc_enable, then
4972                  * the HW state readout code will complain that the expected
4973                  * IPS_CTL value is not the one we read. */
4974                 if (intel_wait_for_register(dev_priv,
4975                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4976                                             50))
4977                         DRM_ERROR("Timed out waiting for IPS enable\n");
4978         }
4979 }
4980
4981 void hsw_disable_ips(struct intel_crtc *crtc)
4982 {
4983         struct drm_device *dev = crtc->base.dev;
4984         struct drm_i915_private *dev_priv = to_i915(dev);
4985
4986         if (!crtc->config->ips_enabled)
4987                 return;
4988
4989         assert_plane_enabled(dev_priv, crtc->plane);
4990         if (IS_BROADWELL(dev_priv)) {
4991                 mutex_lock(&dev_priv->rps.hw_lock);
4992                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4993                 mutex_unlock(&dev_priv->rps.hw_lock);
4994                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4995                 if (intel_wait_for_register(dev_priv,
4996                                             IPS_CTL, IPS_ENABLE, 0,
4997                                             42))
4998                         DRM_ERROR("Timed out waiting for IPS disable\n");
4999         } else {
5000                 I915_WRITE(IPS_CTL, 0);
5001                 POSTING_READ(IPS_CTL);
5002         }
5003
5004         /* We need to wait for a vblank before we can disable the plane. */
5005         intel_wait_for_vblank(dev_priv, crtc->pipe);
5006 }
5007
5008 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
5009 {
5010         if (intel_crtc->overlay) {
5011                 struct drm_device *dev = intel_crtc->base.dev;
5012
5013                 mutex_lock(&dev->struct_mutex);
5014                 (void) intel_overlay_switch_off(intel_crtc->overlay);
5015                 mutex_unlock(&dev->struct_mutex);
5016         }
5017
5018         /* Let userspace switch the overlay on again. In most cases userspace
5019          * has to recompute where to put it anyway.
5020          */
5021 }
5022
5023 /**
5024  * intel_post_enable_primary - Perform operations after enabling primary plane
5025  * @crtc: the CRTC whose primary plane was just enabled
5026  *
5027  * Performs potentially sleeping operations that must be done after the primary
5028  * plane is enabled, such as updating FBC and IPS.  Note that this may be
5029  * called due to an explicit primary plane update, or due to an implicit
5030  * re-enable that is caused when a sprite plane is updated to no longer
5031  * completely hide the primary plane.
5032  */
5033 static void
5034 intel_post_enable_primary(struct drm_crtc *crtc)
5035 {
5036         struct drm_device *dev = crtc->dev;
5037         struct drm_i915_private *dev_priv = to_i915(dev);
5038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5039         int pipe = intel_crtc->pipe;
5040
5041         /*
5042          * FIXME IPS should be fine as long as one plane is
5043          * enabled, but in practice it seems to have problems
5044          * when going from primary only to sprite only and vice
5045          * versa.
5046          */
5047         hsw_enable_ips(intel_crtc);
5048
5049         /*
5050          * Gen2 reports pipe underruns whenever all planes are disabled.
5051          * So don't enable underrun reporting before at least some planes
5052          * are enabled.
5053          * FIXME: Need to fix the logic to work when we turn off all planes
5054          * but leave the pipe running.
5055          */
5056         if (IS_GEN2(dev_priv))
5057                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059         /* Underruns don't always raise interrupts, so check manually. */
5060         intel_check_cpu_fifo_underruns(dev_priv);
5061         intel_check_pch_fifo_underruns(dev_priv);
5062 }
5063
5064 /* FIXME move all this to pre_plane_update() with proper state tracking */
5065 static void
5066 intel_pre_disable_primary(struct drm_crtc *crtc)
5067 {
5068         struct drm_device *dev = crtc->dev;
5069         struct drm_i915_private *dev_priv = to_i915(dev);
5070         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071         int pipe = intel_crtc->pipe;
5072
5073         /*
5074          * Gen2 reports pipe underruns whenever all planes are disabled.
5075          * So diasble underrun reporting before all the planes get disabled.
5076          * FIXME: Need to fix the logic to work when we turn off all planes
5077          * but leave the pipe running.
5078          */
5079         if (IS_GEN2(dev_priv))
5080                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5081
5082         /*
5083          * FIXME IPS should be fine as long as one plane is
5084          * enabled, but in practice it seems to have problems
5085          * when going from primary only to sprite only and vice
5086          * versa.
5087          */
5088         hsw_disable_ips(intel_crtc);
5089 }
5090
5091 /* FIXME get rid of this and use pre_plane_update */
5092 static void
5093 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5094 {
5095         struct drm_device *dev = crtc->dev;
5096         struct drm_i915_private *dev_priv = to_i915(dev);
5097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5098         int pipe = intel_crtc->pipe;
5099
5100         intel_pre_disable_primary(crtc);
5101
5102         /*
5103          * Vblank time updates from the shadow to live plane control register
5104          * are blocked if the memory self-refresh mode is active at that
5105          * moment. So to make sure the plane gets truly disabled, disable
5106          * first the self-refresh mode. The self-refresh enable bit in turn
5107          * will be checked/applied by the HW only at the next frame start
5108          * event which is after the vblank start event, so we need to have a
5109          * wait-for-vblank between disabling the plane and the pipe.
5110          */
5111         if (HAS_GMCH_DISPLAY(dev_priv) &&
5112             intel_set_memory_cxsr(dev_priv, false))
5113                 intel_wait_for_vblank(dev_priv, pipe);
5114 }
5115
5116 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5117 {
5118         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5119         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5120         struct intel_crtc_state *pipe_config =
5121                 intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
5122                                                 crtc);
5123         struct drm_plane *primary = crtc->base.primary;
5124         struct drm_plane_state *old_pri_state =
5125                 drm_atomic_get_existing_plane_state(old_state, primary);
5126
5127         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5128
5129         if (pipe_config->update_wm_post && pipe_config->base.active)
5130                 intel_update_watermarks(crtc);
5131
5132         if (old_pri_state) {
5133                 struct intel_plane_state *primary_state =
5134                         intel_atomic_get_new_plane_state(to_intel_atomic_state(old_state),
5135                                                          to_intel_plane(primary));
5136                 struct intel_plane_state *old_primary_state =
5137                         to_intel_plane_state(old_pri_state);
5138
5139                 intel_fbc_post_update(crtc);
5140
5141                 if (primary_state->base.visible &&
5142                     (needs_modeset(&pipe_config->base) ||
5143                      !old_primary_state->base.visible))
5144                         intel_post_enable_primary(&crtc->base);
5145         }
5146 }
5147
5148 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5149                                    struct intel_crtc_state *pipe_config)
5150 {
5151         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5152         struct drm_device *dev = crtc->base.dev;
5153         struct drm_i915_private *dev_priv = to_i915(dev);
5154         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5155         struct drm_plane *primary = crtc->base.primary;
5156         struct drm_plane_state *old_pri_state =
5157                 drm_atomic_get_existing_plane_state(old_state, primary);
5158         bool modeset = needs_modeset(&pipe_config->base);
5159         struct intel_atomic_state *old_intel_state =
5160                 to_intel_atomic_state(old_state);
5161
5162         if (old_pri_state) {
5163                 struct intel_plane_state *primary_state =
5164                         intel_atomic_get_new_plane_state(old_intel_state,
5165                                                          to_intel_plane(primary));
5166                 struct intel_plane_state *old_primary_state =
5167                         to_intel_plane_state(old_pri_state);
5168
5169                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5170
5171                 if (old_primary_state->base.visible &&
5172                     (modeset || !primary_state->base.visible))
5173                         intel_pre_disable_primary(&crtc->base);
5174         }
5175
5176         /*
5177          * Vblank time updates from the shadow to live plane control register
5178          * are blocked if the memory self-refresh mode is active at that
5179          * moment. So to make sure the plane gets truly disabled, disable
5180          * first the self-refresh mode. The self-refresh enable bit in turn
5181          * will be checked/applied by the HW only at the next frame start
5182          * event which is after the vblank start event, so we need to have a
5183          * wait-for-vblank between disabling the plane and the pipe.
5184          */
5185         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5186             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5187                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5188
5189         /*
5190          * IVB workaround: must disable low power watermarks for at least
5191          * one frame before enabling scaling.  LP watermarks can be re-enabled
5192          * when scaling is disabled.
5193          *
5194          * WaCxSRDisabledForSpriteScaling:ivb
5195          */
5196         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5197                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5198
5199         /*
5200          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5201          * watermark programming here.
5202          */
5203         if (needs_modeset(&pipe_config->base))
5204                 return;
5205
5206         /*
5207          * For platforms that support atomic watermarks, program the
5208          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5209          * will be the intermediate values that are safe for both pre- and
5210          * post- vblank; when vblank happens, the 'active' values will be set
5211          * to the final 'target' values and we'll do this again to get the
5212          * optimal watermarks.  For gen9+ platforms, the values we program here
5213          * will be the final target values which will get automatically latched
5214          * at vblank time; no further programming will be necessary.
5215          *
5216          * If a platform hasn't been transitioned to atomic watermarks yet,
5217          * we'll continue to update watermarks the old way, if flags tell
5218          * us to.
5219          */
5220         if (dev_priv->display.initial_watermarks != NULL)
5221                 dev_priv->display.initial_watermarks(old_intel_state,
5222                                                      pipe_config);
5223         else if (pipe_config->update_wm_pre)
5224                 intel_update_watermarks(crtc);
5225 }
5226
5227 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5228 {
5229         struct drm_device *dev = crtc->dev;
5230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5231         struct drm_plane *p;
5232         int pipe = intel_crtc->pipe;
5233
5234         intel_crtc_dpms_overlay_disable(intel_crtc);
5235
5236         drm_for_each_plane_mask(p, dev, plane_mask)
5237                 to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc);
5238
5239         /*
5240          * FIXME: Once we grow proper nuclear flip support out of this we need
5241          * to compute the mask of flip planes precisely. For the time being
5242          * consider this a flip to a NULL plane.
5243          */
5244         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5245 }
5246
5247 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5248                                           struct intel_crtc_state *crtc_state,
5249                                           struct drm_atomic_state *old_state)
5250 {
5251         struct drm_connector_state *conn_state;
5252         struct drm_connector *conn;
5253         int i;
5254
5255         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5256                 struct intel_encoder *encoder =
5257                         to_intel_encoder(conn_state->best_encoder);
5258
5259                 if (conn_state->crtc != crtc)
5260                         continue;
5261
5262                 if (encoder->pre_pll_enable)
5263                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5264         }
5265 }
5266
5267 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5268                                       struct intel_crtc_state *crtc_state,
5269                                       struct drm_atomic_state *old_state)
5270 {
5271         struct drm_connector_state *conn_state;
5272         struct drm_connector *conn;
5273         int i;
5274
5275         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5276                 struct intel_encoder *encoder =
5277                         to_intel_encoder(conn_state->best_encoder);
5278
5279                 if (conn_state->crtc != crtc)
5280                         continue;
5281
5282                 if (encoder->pre_enable)
5283                         encoder->pre_enable(encoder, crtc_state, conn_state);
5284         }
5285 }
5286
5287 static void intel_encoders_enable(struct drm_crtc *crtc,
5288                                   struct intel_crtc_state *crtc_state,
5289                                   struct drm_atomic_state *old_state)
5290 {
5291         struct drm_connector_state *conn_state;
5292         struct drm_connector *conn;
5293         int i;
5294
5295         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5296                 struct intel_encoder *encoder =
5297                         to_intel_encoder(conn_state->best_encoder);
5298
5299                 if (conn_state->crtc != crtc)
5300                         continue;
5301
5302                 encoder->enable(encoder, crtc_state, conn_state);
5303                 intel_opregion_notify_encoder(encoder, true);
5304         }
5305 }
5306
5307 static void intel_encoders_disable(struct drm_crtc *crtc,
5308                                    struct intel_crtc_state *old_crtc_state,
5309                                    struct drm_atomic_state *old_state)
5310 {
5311         struct drm_connector_state *old_conn_state;
5312         struct drm_connector *conn;
5313         int i;
5314
5315         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5316                 struct intel_encoder *encoder =
5317                         to_intel_encoder(old_conn_state->best_encoder);
5318
5319                 if (old_conn_state->crtc != crtc)
5320                         continue;
5321
5322                 intel_opregion_notify_encoder(encoder, false);
5323                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5324         }
5325 }
5326
5327 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5328                                         struct intel_crtc_state *old_crtc_state,
5329                                         struct drm_atomic_state *old_state)
5330 {
5331         struct drm_connector_state *old_conn_state;
5332         struct drm_connector *conn;
5333         int i;
5334
5335         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5336                 struct intel_encoder *encoder =
5337                         to_intel_encoder(old_conn_state->best_encoder);
5338
5339                 if (old_conn_state->crtc != crtc)
5340                         continue;
5341
5342                 if (encoder->post_disable)
5343                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5344         }
5345 }
5346
5347 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5348                                             struct intel_crtc_state *old_crtc_state,
5349                                             struct drm_atomic_state *old_state)
5350 {
5351         struct drm_connector_state *old_conn_state;
5352         struct drm_connector *conn;
5353         int i;
5354
5355         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5356                 struct intel_encoder *encoder =
5357                         to_intel_encoder(old_conn_state->best_encoder);
5358
5359                 if (old_conn_state->crtc != crtc)
5360                         continue;
5361
5362                 if (encoder->post_pll_disable)
5363                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5364         }
5365 }
5366
5367 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5368                                  struct drm_atomic_state *old_state)
5369 {
5370         struct drm_crtc *crtc = pipe_config->base.crtc;
5371         struct drm_device *dev = crtc->dev;
5372         struct drm_i915_private *dev_priv = to_i915(dev);
5373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374         int pipe = intel_crtc->pipe;
5375         struct intel_atomic_state *old_intel_state =
5376                 to_intel_atomic_state(old_state);
5377
5378         if (WARN_ON(intel_crtc->active))
5379                 return;
5380
5381         /*
5382          * Sometimes spurious CPU pipe underruns happen during FDI
5383          * training, at least with VGA+HDMI cloning. Suppress them.
5384          *
5385          * On ILK we get an occasional spurious CPU pipe underruns
5386          * between eDP port A enable and vdd enable. Also PCH port
5387          * enable seems to result in the occasional CPU pipe underrun.
5388          *
5389          * Spurious PCH underruns also occur during PCH enabling.
5390          */
5391         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5392                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5393         if (intel_crtc->config->has_pch_encoder)
5394                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5395
5396         if (intel_crtc->config->has_pch_encoder)
5397                 intel_prepare_shared_dpll(intel_crtc);
5398
5399         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5400                 intel_dp_set_m_n(intel_crtc, M1_N1);
5401
5402         intel_set_pipe_timings(intel_crtc);
5403         intel_set_pipe_src_size(intel_crtc);
5404
5405         if (intel_crtc->config->has_pch_encoder) {
5406                 intel_cpu_transcoder_set_m_n(intel_crtc,
5407                                      &intel_crtc->config->fdi_m_n, NULL);
5408         }
5409
5410         ironlake_set_pipeconf(crtc);
5411
5412         intel_crtc->active = true;
5413
5414         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5415
5416         if (intel_crtc->config->has_pch_encoder) {
5417                 /* Note: FDI PLL enabling _must_ be done before we enable the
5418                  * cpu pipes, hence this is separate from all the other fdi/pch
5419                  * enabling. */
5420                 ironlake_fdi_pll_enable(intel_crtc);
5421         } else {
5422                 assert_fdi_tx_disabled(dev_priv, pipe);
5423                 assert_fdi_rx_disabled(dev_priv, pipe);
5424         }
5425
5426         ironlake_pfit_enable(intel_crtc);
5427
5428         /*
5429          * On ILK+ LUT must be loaded before the pipe is running but with
5430          * clocks enabled
5431          */
5432         intel_color_load_luts(&pipe_config->base);
5433
5434         if (dev_priv->display.initial_watermarks != NULL)
5435                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5436         intel_enable_pipe(intel_crtc);
5437
5438         if (intel_crtc->config->has_pch_encoder)
5439                 ironlake_pch_enable(pipe_config);
5440
5441         assert_vblank_disabled(crtc);
5442         drm_crtc_vblank_on(crtc);
5443
5444         intel_encoders_enable(crtc, pipe_config, old_state);
5445
5446         if (HAS_PCH_CPT(dev_priv))
5447                 cpt_verify_modeset(dev, intel_crtc->pipe);
5448
5449         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5450         if (intel_crtc->config->has_pch_encoder)
5451                 intel_wait_for_vblank(dev_priv, pipe);
5452         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5453         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5454 }
5455
5456 /* IPS only exists on ULT machines and is tied to pipe A. */
5457 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5458 {
5459         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5460 }
5461
5462 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5463                                 struct drm_atomic_state *old_state)
5464 {
5465         struct drm_crtc *crtc = pipe_config->base.crtc;
5466         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5468         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5469         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5470         struct intel_atomic_state *old_intel_state =
5471                 to_intel_atomic_state(old_state);
5472
5473         if (WARN_ON(intel_crtc->active))
5474                 return;
5475
5476         if (intel_crtc->config->has_pch_encoder)
5477                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5478
5479         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5480
5481         if (intel_crtc->config->shared_dpll)
5482                 intel_enable_shared_dpll(intel_crtc);
5483
5484         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5485                 intel_dp_set_m_n(intel_crtc, M1_N1);
5486
5487         if (!transcoder_is_dsi(cpu_transcoder))
5488                 intel_set_pipe_timings(intel_crtc);
5489
5490         intel_set_pipe_src_size(intel_crtc);
5491
5492         if (cpu_transcoder != TRANSCODER_EDP &&
5493             !transcoder_is_dsi(cpu_transcoder)) {
5494                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5495                            intel_crtc->config->pixel_multiplier - 1);
5496         }
5497
5498         if (intel_crtc->config->has_pch_encoder) {
5499                 intel_cpu_transcoder_set_m_n(intel_crtc,
5500                                      &intel_crtc->config->fdi_m_n, NULL);
5501         }
5502
5503         if (!transcoder_is_dsi(cpu_transcoder))
5504                 haswell_set_pipeconf(crtc);
5505
5506         haswell_set_pipemisc(crtc);
5507
5508         intel_color_set_csc(&pipe_config->base);
5509
5510         intel_crtc->active = true;
5511
5512         if (intel_crtc->config->has_pch_encoder)
5513                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5514         else
5515                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5516
5517         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5518
5519         if (intel_crtc->config->has_pch_encoder)
5520                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5521
5522         if (!transcoder_is_dsi(cpu_transcoder))
5523                 intel_ddi_enable_pipe_clock(pipe_config);
5524
5525         if (INTEL_GEN(dev_priv) >= 9)
5526                 skylake_pfit_enable(intel_crtc);
5527         else
5528                 ironlake_pfit_enable(intel_crtc);
5529
5530         /*
5531          * On ILK+ LUT must be loaded before the pipe is running but with
5532          * clocks enabled
5533          */
5534         intel_color_load_luts(&pipe_config->base);
5535
5536         intel_ddi_set_pipe_settings(pipe_config);
5537         if (!transcoder_is_dsi(cpu_transcoder))
5538                 intel_ddi_enable_transcoder_func(pipe_config);
5539
5540         if (dev_priv->display.initial_watermarks != NULL)
5541                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5542
5543         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5544         if (!transcoder_is_dsi(cpu_transcoder))
5545                 intel_enable_pipe(intel_crtc);
5546
5547         if (intel_crtc->config->has_pch_encoder)
5548                 lpt_pch_enable(pipe_config);
5549
5550         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5551                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5552
5553         assert_vblank_disabled(crtc);
5554         drm_crtc_vblank_on(crtc);
5555
5556         intel_encoders_enable(crtc, pipe_config, old_state);
5557
5558         if (intel_crtc->config->has_pch_encoder) {
5559                 intel_wait_for_vblank(dev_priv, pipe);
5560                 intel_wait_for_vblank(dev_priv, pipe);
5561                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5562                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5563         }
5564
5565         /* If we change the relative order between pipe/planes enabling, we need
5566          * to change the workaround. */
5567         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5568         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5569                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5570                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5571         }
5572 }
5573
5574 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5575 {
5576         struct drm_device *dev = crtc->base.dev;
5577         struct drm_i915_private *dev_priv = to_i915(dev);
5578         int pipe = crtc->pipe;
5579
5580         /* To avoid upsetting the power well on haswell only disable the pfit if
5581          * it's in use. The hw state code will make sure we get this right. */
5582         if (force || crtc->config->pch_pfit.enabled) {
5583                 I915_WRITE(PF_CTL(pipe), 0);
5584                 I915_WRITE(PF_WIN_POS(pipe), 0);
5585                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5586         }
5587 }
5588
5589 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5590                                   struct drm_atomic_state *old_state)
5591 {
5592         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5593         struct drm_device *dev = crtc->dev;
5594         struct drm_i915_private *dev_priv = to_i915(dev);
5595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596         int pipe = intel_crtc->pipe;
5597
5598         /*
5599          * Sometimes spurious CPU pipe underruns happen when the
5600          * pipe is already disabled, but FDI RX/TX is still enabled.
5601          * Happens at least with VGA+HDMI cloning. Suppress them.
5602          */
5603         if (intel_crtc->config->has_pch_encoder) {
5604                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5605                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5606         }
5607
5608         intel_encoders_disable(crtc, old_crtc_state, old_state);
5609
5610         drm_crtc_vblank_off(crtc);
5611         assert_vblank_disabled(crtc);
5612
5613         intel_disable_pipe(intel_crtc);
5614
5615         ironlake_pfit_disable(intel_crtc, false);
5616
5617         if (intel_crtc->config->has_pch_encoder)
5618                 ironlake_fdi_disable(crtc);
5619
5620         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5621
5622         if (intel_crtc->config->has_pch_encoder) {
5623                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5624
5625                 if (HAS_PCH_CPT(dev_priv)) {
5626                         i915_reg_t reg;
5627                         u32 temp;
5628
5629                         /* disable TRANS_DP_CTL */
5630                         reg = TRANS_DP_CTL(pipe);
5631                         temp = I915_READ(reg);
5632                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5633                                   TRANS_DP_PORT_SEL_MASK);
5634                         temp |= TRANS_DP_PORT_SEL_NONE;
5635                         I915_WRITE(reg, temp);
5636
5637                         /* disable DPLL_SEL */
5638                         temp = I915_READ(PCH_DPLL_SEL);
5639                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5640                         I915_WRITE(PCH_DPLL_SEL, temp);
5641                 }
5642
5643                 ironlake_fdi_pll_disable(intel_crtc);
5644         }
5645
5646         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5647         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5648 }
5649
5650 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5651                                  struct drm_atomic_state *old_state)
5652 {
5653         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5654         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5656         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5657
5658         if (intel_crtc->config->has_pch_encoder)
5659                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5660
5661         intel_encoders_disable(crtc, old_crtc_state, old_state);
5662
5663         drm_crtc_vblank_off(crtc);
5664         assert_vblank_disabled(crtc);
5665
5666         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5667         if (!transcoder_is_dsi(cpu_transcoder))
5668                 intel_disable_pipe(intel_crtc);
5669
5670         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5671                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5672
5673         if (!transcoder_is_dsi(cpu_transcoder))
5674                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5675
5676         if (INTEL_GEN(dev_priv) >= 9)
5677                 skylake_scaler_disable(intel_crtc);
5678         else
5679                 ironlake_pfit_disable(intel_crtc, false);
5680
5681         if (!transcoder_is_dsi(cpu_transcoder))
5682                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5683
5684         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5685
5686         if (old_crtc_state->has_pch_encoder)
5687                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5688 }
5689
5690 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5691 {
5692         struct drm_device *dev = crtc->base.dev;
5693         struct drm_i915_private *dev_priv = to_i915(dev);
5694         struct intel_crtc_state *pipe_config = crtc->config;
5695
5696         if (!pipe_config->gmch_pfit.control)
5697                 return;
5698
5699         /*
5700          * The panel fitter should only be adjusted whilst the pipe is disabled,
5701          * according to register description and PRM.
5702          */
5703         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5704         assert_pipe_disabled(dev_priv, crtc->pipe);
5705
5706         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5707         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5708
5709         /* Border color in case we don't scale up to the full screen. Black by
5710          * default, change to something else for debugging. */
5711         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5712 }
5713
5714 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5715 {
5716         switch (port) {
5717         case PORT_A:
5718                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5719         case PORT_B:
5720                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5721         case PORT_C:
5722                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5723         case PORT_D:
5724                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5725         case PORT_E:
5726                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5727         default:
5728                 MISSING_CASE(port);
5729                 return POWER_DOMAIN_PORT_OTHER;
5730         }
5731 }
5732
5733 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5734                                   struct intel_crtc_state *crtc_state)
5735 {
5736         struct drm_device *dev = crtc->dev;
5737         struct drm_i915_private *dev_priv = to_i915(dev);
5738         struct drm_encoder *encoder;
5739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5740         enum pipe pipe = intel_crtc->pipe;
5741         u64 mask;
5742         enum transcoder transcoder = crtc_state->cpu_transcoder;
5743
5744         if (!crtc_state->base.active)
5745                 return 0;
5746
5747         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5748         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5749         if (crtc_state->pch_pfit.enabled ||
5750             crtc_state->pch_pfit.force_thru)
5751                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5752
5753         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5754                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5755
5756                 mask |= BIT_ULL(intel_encoder->power_domain);
5757         }
5758
5759         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5760                 mask |= BIT(POWER_DOMAIN_AUDIO);
5761
5762         if (crtc_state->shared_dpll)
5763                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5764
5765         return mask;
5766 }
5767
5768 static u64
5769 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5770                                struct intel_crtc_state *crtc_state)
5771 {
5772         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5774         enum intel_display_power_domain domain;
5775         u64 domains, new_domains, old_domains;
5776
5777         old_domains = intel_crtc->enabled_power_domains;
5778         intel_crtc->enabled_power_domains = new_domains =
5779                 get_crtc_power_domains(crtc, crtc_state);
5780
5781         domains = new_domains & ~old_domains;
5782
5783         for_each_power_domain(domain, domains)
5784                 intel_display_power_get(dev_priv, domain);
5785
5786         return old_domains & ~new_domains;
5787 }
5788
5789 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5790                                       u64 domains)
5791 {
5792         enum intel_display_power_domain domain;
5793
5794         for_each_power_domain(domain, domains)
5795                 intel_display_power_put(dev_priv, domain);
5796 }
5797
5798 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5799                                    struct drm_atomic_state *old_state)
5800 {
5801         struct intel_atomic_state *old_intel_state =
5802                 to_intel_atomic_state(old_state);
5803         struct drm_crtc *crtc = pipe_config->base.crtc;
5804         struct drm_device *dev = crtc->dev;
5805         struct drm_i915_private *dev_priv = to_i915(dev);
5806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5807         int pipe = intel_crtc->pipe;
5808
5809         if (WARN_ON(intel_crtc->active))
5810                 return;
5811
5812         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5813                 intel_dp_set_m_n(intel_crtc, M1_N1);
5814
5815         intel_set_pipe_timings(intel_crtc);
5816         intel_set_pipe_src_size(intel_crtc);
5817
5818         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5819                 struct drm_i915_private *dev_priv = to_i915(dev);
5820
5821                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5822                 I915_WRITE(CHV_CANVAS(pipe), 0);
5823         }
5824
5825         i9xx_set_pipeconf(intel_crtc);
5826
5827         intel_crtc->active = true;
5828
5829         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5830
5831         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5832
5833         if (IS_CHERRYVIEW(dev_priv)) {
5834                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5835                 chv_enable_pll(intel_crtc, intel_crtc->config);
5836         } else {
5837                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5838                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5839         }
5840
5841         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5842
5843         i9xx_pfit_enable(intel_crtc);
5844
5845         intel_color_load_luts(&pipe_config->base);
5846
5847         dev_priv->display.initial_watermarks(old_intel_state,
5848                                              pipe_config);
5849         intel_enable_pipe(intel_crtc);
5850
5851         assert_vblank_disabled(crtc);
5852         drm_crtc_vblank_on(crtc);
5853
5854         intel_encoders_enable(crtc, pipe_config, old_state);
5855 }
5856
5857 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5858 {
5859         struct drm_device *dev = crtc->base.dev;
5860         struct drm_i915_private *dev_priv = to_i915(dev);
5861
5862         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5863         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5864 }
5865
5866 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5867                              struct drm_atomic_state *old_state)
5868 {
5869         struct intel_atomic_state *old_intel_state =
5870                 to_intel_atomic_state(old_state);
5871         struct drm_crtc *crtc = pipe_config->base.crtc;
5872         struct drm_device *dev = crtc->dev;
5873         struct drm_i915_private *dev_priv = to_i915(dev);
5874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5875         enum pipe pipe = intel_crtc->pipe;
5876
5877         if (WARN_ON(intel_crtc->active))
5878                 return;
5879
5880         i9xx_set_pll_dividers(intel_crtc);
5881
5882         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5883                 intel_dp_set_m_n(intel_crtc, M1_N1);
5884
5885         intel_set_pipe_timings(intel_crtc);
5886         intel_set_pipe_src_size(intel_crtc);
5887
5888         i9xx_set_pipeconf(intel_crtc);
5889
5890         intel_crtc->active = true;
5891
5892         if (!IS_GEN2(dev_priv))
5893                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5894
5895         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5896
5897         i9xx_enable_pll(intel_crtc);
5898
5899         i9xx_pfit_enable(intel_crtc);
5900
5901         intel_color_load_luts(&pipe_config->base);
5902
5903         if (dev_priv->display.initial_watermarks != NULL)
5904                 dev_priv->display.initial_watermarks(old_intel_state,
5905                                                      intel_crtc->config);
5906         else
5907                 intel_update_watermarks(intel_crtc);
5908         intel_enable_pipe(intel_crtc);
5909
5910         assert_vblank_disabled(crtc);
5911         drm_crtc_vblank_on(crtc);
5912
5913         intel_encoders_enable(crtc, pipe_config, old_state);
5914 }
5915
5916 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5917 {
5918         struct drm_device *dev = crtc->base.dev;
5919         struct drm_i915_private *dev_priv = to_i915(dev);
5920
5921         if (!crtc->config->gmch_pfit.control)
5922                 return;
5923
5924         assert_pipe_disabled(dev_priv, crtc->pipe);
5925
5926         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5927                          I915_READ(PFIT_CONTROL));
5928         I915_WRITE(PFIT_CONTROL, 0);
5929 }
5930
5931 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5932                               struct drm_atomic_state *old_state)
5933 {
5934         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5935         struct drm_device *dev = crtc->dev;
5936         struct drm_i915_private *dev_priv = to_i915(dev);
5937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5938         int pipe = intel_crtc->pipe;
5939
5940         /*
5941          * On gen2 planes are double buffered but the pipe isn't, so we must
5942          * wait for planes to fully turn off before disabling the pipe.
5943          */
5944         if (IS_GEN2(dev_priv))
5945                 intel_wait_for_vblank(dev_priv, pipe);
5946
5947         intel_encoders_disable(crtc, old_crtc_state, old_state);
5948
5949         drm_crtc_vblank_off(crtc);
5950         assert_vblank_disabled(crtc);
5951
5952         intel_disable_pipe(intel_crtc);
5953
5954         i9xx_pfit_disable(intel_crtc);
5955
5956         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5957
5958         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5959                 if (IS_CHERRYVIEW(dev_priv))
5960                         chv_disable_pll(dev_priv, pipe);
5961                 else if (IS_VALLEYVIEW(dev_priv))
5962                         vlv_disable_pll(dev_priv, pipe);
5963                 else
5964                         i9xx_disable_pll(intel_crtc);
5965         }
5966
5967         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5968
5969         if (!IS_GEN2(dev_priv))
5970                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5971
5972         if (!dev_priv->display.initial_watermarks)
5973                 intel_update_watermarks(intel_crtc);
5974
5975         /* clock the pipe down to 640x480@60 to potentially save power */
5976         if (IS_I830(dev_priv))
5977                 i830_enable_pipe(dev_priv, pipe);
5978 }
5979
5980 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
5981                                         struct drm_modeset_acquire_ctx *ctx)
5982 {
5983         struct intel_encoder *encoder;
5984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5985         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5986         enum intel_display_power_domain domain;
5987         u64 domains;
5988         struct drm_atomic_state *state;
5989         struct intel_crtc_state *crtc_state;
5990         int ret;
5991
5992         if (!intel_crtc->active)
5993                 return;
5994
5995         if (crtc->primary->state->visible) {
5996                 intel_pre_disable_primary_noatomic(crtc);
5997
5998                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5999                 crtc->primary->state->visible = false;
6000         }
6001
6002         state = drm_atomic_state_alloc(crtc->dev);
6003         if (!state) {
6004                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6005                               crtc->base.id, crtc->name);
6006                 return;
6007         }
6008
6009         state->acquire_ctx = ctx;
6010
6011         /* Everything's already locked, -EDEADLK can't happen. */
6012         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6013         ret = drm_atomic_add_affected_connectors(state, crtc);
6014
6015         WARN_ON(IS_ERR(crtc_state) || ret);
6016
6017         dev_priv->display.crtc_disable(crtc_state, state);
6018
6019         drm_atomic_state_put(state);
6020
6021         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6022                       crtc->base.id, crtc->name);
6023
6024         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6025         crtc->state->active = false;
6026         intel_crtc->active = false;
6027         crtc->enabled = false;
6028         crtc->state->connector_mask = 0;
6029         crtc->state->encoder_mask = 0;
6030
6031         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6032                 encoder->base.crtc = NULL;
6033
6034         intel_fbc_disable(intel_crtc);
6035         intel_update_watermarks(intel_crtc);
6036         intel_disable_shared_dpll(intel_crtc);
6037
6038         domains = intel_crtc->enabled_power_domains;
6039         for_each_power_domain(domain, domains)
6040                 intel_display_power_put(dev_priv, domain);
6041         intel_crtc->enabled_power_domains = 0;
6042
6043         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6044         dev_priv->min_cdclk[intel_crtc->pipe] = 0;
6045 }
6046
6047 /*
6048  * turn all crtc's off, but do not adjust state
6049  * This has to be paired with a call to intel_modeset_setup_hw_state.
6050  */
6051 int intel_display_suspend(struct drm_device *dev)
6052 {
6053         struct drm_i915_private *dev_priv = to_i915(dev);
6054         struct drm_atomic_state *state;
6055         int ret;
6056
6057         state = drm_atomic_helper_suspend(dev);
6058         ret = PTR_ERR_OR_ZERO(state);
6059         if (ret)
6060                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6061         else
6062                 dev_priv->modeset_restore_state = state;
6063         return ret;
6064 }
6065
6066 void intel_encoder_destroy(struct drm_encoder *encoder)
6067 {
6068         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6069
6070         drm_encoder_cleanup(encoder);
6071         kfree(intel_encoder);
6072 }
6073
6074 /* Cross check the actual hw state with our own modeset state tracking (and it's
6075  * internal consistency). */
6076 static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
6077                                          struct drm_connector_state *conn_state)
6078 {
6079         struct intel_connector *connector = to_intel_connector(conn_state->connector);
6080
6081         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6082                       connector->base.base.id,
6083                       connector->base.name);
6084
6085         if (connector->get_hw_state(connector)) {
6086                 struct intel_encoder *encoder = connector->encoder;
6087
6088                 I915_STATE_WARN(!crtc_state,
6089                          "connector enabled without attached crtc\n");
6090
6091                 if (!crtc_state)
6092                         return;
6093
6094                 I915_STATE_WARN(!crtc_state->active,
6095                       "connector is active, but attached crtc isn't\n");
6096
6097                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6098                         return;
6099
6100                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6101                         "atomic encoder doesn't match attached encoder\n");
6102
6103                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6104                         "attached encoder crtc differs from connector crtc\n");
6105         } else {
6106                 I915_STATE_WARN(crtc_state && crtc_state->active,
6107                         "attached crtc is active, but connector isn't\n");
6108                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
6109                         "best encoder set without crtc!\n");
6110         }
6111 }
6112
6113 int intel_connector_init(struct intel_connector *connector)
6114 {
6115         struct intel_digital_connector_state *conn_state;
6116
6117         /*
6118          * Allocate enough memory to hold intel_digital_connector_state,
6119          * This might be a few bytes too many, but for connectors that don't
6120          * need it we'll free the state and allocate a smaller one on the first
6121          * succesful commit anyway.
6122          */
6123         conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
6124         if (!conn_state)
6125                 return -ENOMEM;
6126
6127         __drm_atomic_helper_connector_reset(&connector->base,
6128                                             &conn_state->base);
6129
6130         return 0;
6131 }
6132
6133 struct intel_connector *intel_connector_alloc(void)
6134 {
6135         struct intel_connector *connector;
6136
6137         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6138         if (!connector)
6139                 return NULL;
6140
6141         if (intel_connector_init(connector) < 0) {
6142                 kfree(connector);
6143                 return NULL;
6144         }
6145
6146         return connector;
6147 }
6148
6149 /* Simple connector->get_hw_state implementation for encoders that support only
6150  * one connector and no cloning and hence the encoder state determines the state
6151  * of the connector. */
6152 bool intel_connector_get_hw_state(struct intel_connector *connector)
6153 {
6154         enum pipe pipe = 0;
6155         struct intel_encoder *encoder = connector->encoder;
6156
6157         return encoder->get_hw_state(encoder, &pipe);
6158 }
6159
6160 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6161 {
6162         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6163                 return crtc_state->fdi_lanes;
6164
6165         return 0;
6166 }
6167
6168 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6169                                      struct intel_crtc_state *pipe_config)
6170 {
6171         struct drm_i915_private *dev_priv = to_i915(dev);
6172         struct drm_atomic_state *state = pipe_config->base.state;
6173         struct intel_crtc *other_crtc;
6174         struct intel_crtc_state *other_crtc_state;
6175
6176         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6177                       pipe_name(pipe), pipe_config->fdi_lanes);
6178         if (pipe_config->fdi_lanes > 4) {
6179                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6180                               pipe_name(pipe), pipe_config->fdi_lanes);
6181                 return -EINVAL;
6182         }
6183
6184         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6185                 if (pipe_config->fdi_lanes > 2) {
6186                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6187                                       pipe_config->fdi_lanes);
6188                         return -EINVAL;
6189                 } else {
6190                         return 0;
6191                 }
6192         }
6193
6194         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6195                 return 0;
6196
6197         /* Ivybridge 3 pipe is really complicated */
6198         switch (pipe) {
6199         case PIPE_A:
6200                 return 0;
6201         case PIPE_B:
6202                 if (pipe_config->fdi_lanes <= 2)
6203                         return 0;
6204
6205                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6206                 other_crtc_state =
6207                         intel_atomic_get_crtc_state(state, other_crtc);
6208                 if (IS_ERR(other_crtc_state))
6209                         return PTR_ERR(other_crtc_state);
6210
6211                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6212                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6213                                       pipe_name(pipe), pipe_config->fdi_lanes);
6214                         return -EINVAL;
6215                 }
6216                 return 0;
6217         case PIPE_C:
6218                 if (pipe_config->fdi_lanes > 2) {
6219                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6220                                       pipe_name(pipe), pipe_config->fdi_lanes);
6221                         return -EINVAL;
6222                 }
6223
6224                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6225                 other_crtc_state =
6226                         intel_atomic_get_crtc_state(state, other_crtc);
6227                 if (IS_ERR(other_crtc_state))
6228                         return PTR_ERR(other_crtc_state);
6229
6230                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6231                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6232                         return -EINVAL;
6233                 }
6234                 return 0;
6235         default:
6236                 BUG();
6237         }
6238 }
6239
6240 #define RETRY 1
6241 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6242                                        struct intel_crtc_state *pipe_config)
6243 {
6244         struct drm_device *dev = intel_crtc->base.dev;
6245         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6246         int lane, link_bw, fdi_dotclock, ret;
6247         bool needs_recompute = false;
6248
6249 retry:
6250         /* FDI is a binary signal running at ~2.7GHz, encoding
6251          * each output octet as 10 bits. The actual frequency
6252          * is stored as a divider into a 100MHz clock, and the
6253          * mode pixel clock is stored in units of 1KHz.
6254          * Hence the bw of each lane in terms of the mode signal
6255          * is:
6256          */
6257         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6258
6259         fdi_dotclock = adjusted_mode->crtc_clock;
6260
6261         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6262                                            pipe_config->pipe_bpp);
6263
6264         pipe_config->fdi_lanes = lane;
6265
6266         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6267                                link_bw, &pipe_config->fdi_m_n, false);
6268
6269         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6270         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6271                 pipe_config->pipe_bpp -= 2*3;
6272                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6273                               pipe_config->pipe_bpp);
6274                 needs_recompute = true;
6275                 pipe_config->bw_constrained = true;
6276
6277                 goto retry;
6278         }
6279
6280         if (needs_recompute)
6281                 return RETRY;
6282
6283         return ret;
6284 }
6285
6286 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6287                                      struct intel_crtc_state *pipe_config)
6288 {
6289         if (pipe_config->ips_force_disable)
6290                 return false;
6291
6292         if (pipe_config->pipe_bpp > 24)
6293                 return false;
6294
6295         /* HSW can handle pixel rate up to cdclk? */
6296         if (IS_HASWELL(dev_priv))
6297                 return true;
6298
6299         /*
6300          * We compare against max which means we must take
6301          * the increased cdclk requirement into account when
6302          * calculating the new cdclk.
6303          *
6304          * Should measure whether using a lower cdclk w/o IPS
6305          */
6306         return pipe_config->pixel_rate <=
6307                 dev_priv->max_cdclk_freq * 95 / 100;
6308 }
6309
6310 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6311                                    struct intel_crtc_state *pipe_config)
6312 {
6313         struct drm_device *dev = crtc->base.dev;
6314         struct drm_i915_private *dev_priv = to_i915(dev);
6315
6316         pipe_config->ips_enabled = i915.enable_ips &&
6317                 hsw_crtc_supports_ips(crtc) &&
6318                 pipe_config_supports_ips(dev_priv, pipe_config);
6319 }
6320
6321 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6322 {
6323         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6324
6325         /* GDG double wide on either pipe, otherwise pipe A only */
6326         return INTEL_INFO(dev_priv)->gen < 4 &&
6327                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6328 }
6329
6330 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6331 {
6332         uint32_t pixel_rate;
6333
6334         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6335
6336         /*
6337          * We only use IF-ID interlacing. If we ever use
6338          * PF-ID we'll need to adjust the pixel_rate here.
6339          */
6340
6341         if (pipe_config->pch_pfit.enabled) {
6342                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6343                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6344
6345                 pipe_w = pipe_config->pipe_src_w;
6346                 pipe_h = pipe_config->pipe_src_h;
6347
6348                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6349                 pfit_h = pfit_size & 0xFFFF;
6350                 if (pipe_w < pfit_w)
6351                         pipe_w = pfit_w;
6352                 if (pipe_h < pfit_h)
6353                         pipe_h = pfit_h;
6354
6355                 if (WARN_ON(!pfit_w || !pfit_h))
6356                         return pixel_rate;
6357
6358                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6359                                      pfit_w * pfit_h);
6360         }
6361
6362         return pixel_rate;
6363 }
6364
6365 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6366 {
6367         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6368
6369         if (HAS_GMCH_DISPLAY(dev_priv))
6370                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6371                 crtc_state->pixel_rate =
6372                         crtc_state->base.adjusted_mode.crtc_clock;
6373         else
6374                 crtc_state->pixel_rate =
6375                         ilk_pipe_pixel_rate(crtc_state);
6376 }
6377
6378 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6379                                      struct intel_crtc_state *pipe_config)
6380 {
6381         struct drm_device *dev = crtc->base.dev;
6382         struct drm_i915_private *dev_priv = to_i915(dev);
6383         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6384         int clock_limit = dev_priv->max_dotclk_freq;
6385
6386         if (INTEL_GEN(dev_priv) < 4) {
6387                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6388
6389                 /*
6390                  * Enable double wide mode when the dot clock
6391                  * is > 90% of the (display) core speed.
6392                  */
6393                 if (intel_crtc_supports_double_wide(crtc) &&
6394                     adjusted_mode->crtc_clock > clock_limit) {
6395                         clock_limit = dev_priv->max_dotclk_freq;
6396                         pipe_config->double_wide = true;
6397                 }
6398         }
6399
6400         if (adjusted_mode->crtc_clock > clock_limit) {
6401                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6402                               adjusted_mode->crtc_clock, clock_limit,
6403                               yesno(pipe_config->double_wide));
6404                 return -EINVAL;
6405         }
6406
6407         if (pipe_config->ycbcr420 && pipe_config->base.ctm) {
6408                 /*
6409                  * There is only one pipe CSC unit per pipe, and we need that
6410                  * for output conversion from RGB->YCBCR. So if CTM is already
6411                  * applied we can't support YCBCR420 output.
6412                  */
6413                 DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n");
6414                 return -EINVAL;
6415         }
6416
6417         /*
6418          * Pipe horizontal size must be even in:
6419          * - DVO ganged mode
6420          * - LVDS dual channel mode
6421          * - Double wide pipe
6422          */
6423         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6424              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6425                 pipe_config->pipe_src_w &= ~1;
6426
6427         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6428          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6429          */
6430         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6431                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6432                 return -EINVAL;
6433
6434         intel_crtc_compute_pixel_rate(pipe_config);
6435
6436         if (HAS_IPS(dev_priv))
6437                 hsw_compute_ips_config(crtc, pipe_config);
6438
6439         if (pipe_config->has_pch_encoder)
6440                 return ironlake_fdi_compute_config(crtc, pipe_config);
6441
6442         return 0;
6443 }
6444
6445 static void
6446 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6447 {
6448         while (*num > DATA_LINK_M_N_MASK ||
6449                *den > DATA_LINK_M_N_MASK) {
6450                 *num >>= 1;
6451                 *den >>= 1;
6452         }
6453 }
6454
6455 static void compute_m_n(unsigned int m, unsigned int n,
6456                         uint32_t *ret_m, uint32_t *ret_n,
6457                         bool reduce_m_n)
6458 {
6459         /*
6460          * Reduce M/N as much as possible without loss in precision. Several DP
6461          * dongles in particular seem to be fussy about too large *link* M/N
6462          * values. The passed in values are more likely to have the least
6463          * significant bits zero than M after rounding below, so do this first.
6464          */
6465         if (reduce_m_n) {
6466                 while ((m & 1) == 0 && (n & 1) == 0) {
6467                         m >>= 1;
6468                         n >>= 1;
6469                 }
6470         }
6471
6472         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6473         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6474         intel_reduce_m_n_ratio(ret_m, ret_n);
6475 }
6476
6477 void
6478 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6479                        int pixel_clock, int link_clock,
6480                        struct intel_link_m_n *m_n,
6481                        bool reduce_m_n)
6482 {
6483         m_n->tu = 64;
6484
6485         compute_m_n(bits_per_pixel * pixel_clock,
6486                     link_clock * nlanes * 8,
6487                     &m_n->gmch_m, &m_n->gmch_n,
6488                     reduce_m_n);
6489
6490         compute_m_n(pixel_clock, link_clock,
6491                     &m_n->link_m, &m_n->link_n,
6492                     reduce_m_n);
6493 }
6494
6495 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6496 {
6497         if (i915.panel_use_ssc >= 0)
6498                 return i915.panel_use_ssc != 0;
6499         return dev_priv->vbt.lvds_use_ssc
6500                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6501 }
6502
6503 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6504 {
6505         return (1 << dpll->n) << 16 | dpll->m2;
6506 }
6507
6508 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6509 {
6510         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6511 }
6512
6513 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6514                                      struct intel_crtc_state *crtc_state,
6515                                      struct dpll *reduced_clock)
6516 {
6517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6518         u32 fp, fp2 = 0;
6519
6520         if (IS_PINEVIEW(dev_priv)) {
6521                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6522                 if (reduced_clock)
6523                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6524         } else {
6525                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6526                 if (reduced_clock)
6527                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6528         }
6529
6530         crtc_state->dpll_hw_state.fp0 = fp;
6531
6532         crtc->lowfreq_avail = false;
6533         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6534             reduced_clock) {
6535                 crtc_state->dpll_hw_state.fp1 = fp2;
6536                 crtc->lowfreq_avail = true;
6537         } else {
6538                 crtc_state->dpll_hw_state.fp1 = fp;
6539         }
6540 }
6541
6542 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6543                 pipe)
6544 {
6545         u32 reg_val;
6546
6547         /*
6548          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6549          * and set it to a reasonable value instead.
6550          */
6551         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6552         reg_val &= 0xffffff00;
6553         reg_val |= 0x00000030;
6554         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6555
6556         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6557         reg_val &= 0x00ffffff;
6558         reg_val |= 0x8c000000;
6559         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6560
6561         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6562         reg_val &= 0xffffff00;
6563         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6564
6565         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6566         reg_val &= 0x00ffffff;
6567         reg_val |= 0xb0000000;
6568         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6569 }
6570
6571 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6572                                          struct intel_link_m_n *m_n)
6573 {
6574         struct drm_device *dev = crtc->base.dev;
6575         struct drm_i915_private *dev_priv = to_i915(dev);
6576         int pipe = crtc->pipe;
6577
6578         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6579         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6580         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6581         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6582 }
6583
6584 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6585                                          struct intel_link_m_n *m_n,
6586                                          struct intel_link_m_n *m2_n2)
6587 {
6588         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6589         int pipe = crtc->pipe;
6590         enum transcoder transcoder = crtc->config->cpu_transcoder;
6591
6592         if (INTEL_GEN(dev_priv) >= 5) {
6593                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6594                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6595                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6596                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6597                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6598                  * for gen < 8) and if DRRS is supported (to make sure the
6599                  * registers are not unnecessarily accessed).
6600                  */
6601                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6602                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6603                         I915_WRITE(PIPE_DATA_M2(transcoder),
6604                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6605                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6606                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6607                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6608                 }
6609         } else {
6610                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6611                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6612                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6613                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6614         }
6615 }
6616
6617 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6618 {
6619         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6620
6621         if (m_n == M1_N1) {
6622                 dp_m_n = &crtc->config->dp_m_n;
6623                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6624         } else if (m_n == M2_N2) {
6625
6626                 /*
6627                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6628                  * needs to be programmed into M1_N1.
6629                  */
6630                 dp_m_n = &crtc->config->dp_m2_n2;
6631         } else {
6632                 DRM_ERROR("Unsupported divider value\n");
6633                 return;
6634         }
6635
6636         if (crtc->config->has_pch_encoder)
6637                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6638         else
6639                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6640 }
6641
6642 static void vlv_compute_dpll(struct intel_crtc *crtc,
6643                              struct intel_crtc_state *pipe_config)
6644 {
6645         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6646                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6647         if (crtc->pipe != PIPE_A)
6648                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6649
6650         /* DPLL not used with DSI, but still need the rest set up */
6651         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6652                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6653                         DPLL_EXT_BUFFER_ENABLE_VLV;
6654
6655         pipe_config->dpll_hw_state.dpll_md =
6656                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6657 }
6658
6659 static void chv_compute_dpll(struct intel_crtc *crtc,
6660                              struct intel_crtc_state *pipe_config)
6661 {
6662         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6663                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6664         if (crtc->pipe != PIPE_A)
6665                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6666
6667         /* DPLL not used with DSI, but still need the rest set up */
6668         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6669                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6670
6671         pipe_config->dpll_hw_state.dpll_md =
6672                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6673 }
6674
6675 static void vlv_prepare_pll(struct intel_crtc *crtc,
6676                             const struct intel_crtc_state *pipe_config)
6677 {
6678         struct drm_device *dev = crtc->base.dev;
6679         struct drm_i915_private *dev_priv = to_i915(dev);
6680         enum pipe pipe = crtc->pipe;
6681         u32 mdiv;
6682         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6683         u32 coreclk, reg_val;
6684
6685         /* Enable Refclk */
6686         I915_WRITE(DPLL(pipe),
6687                    pipe_config->dpll_hw_state.dpll &
6688                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6689
6690         /* No need to actually set up the DPLL with DSI */
6691         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6692                 return;
6693
6694         mutex_lock(&dev_priv->sb_lock);
6695
6696         bestn = pipe_config->dpll.n;
6697         bestm1 = pipe_config->dpll.m1;
6698         bestm2 = pipe_config->dpll.m2;
6699         bestp1 = pipe_config->dpll.p1;
6700         bestp2 = pipe_config->dpll.p2;
6701
6702         /* See eDP HDMI DPIO driver vbios notes doc */
6703
6704         /* PLL B needs special handling */
6705         if (pipe == PIPE_B)
6706                 vlv_pllb_recal_opamp(dev_priv, pipe);
6707
6708         /* Set up Tx target for periodic Rcomp update */
6709         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6710
6711         /* Disable target IRef on PLL */
6712         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6713         reg_val &= 0x00ffffff;
6714         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6715
6716         /* Disable fast lock */
6717         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6718
6719         /* Set idtafcrecal before PLL is enabled */
6720         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6721         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6722         mdiv |= ((bestn << DPIO_N_SHIFT));
6723         mdiv |= (1 << DPIO_K_SHIFT);
6724
6725         /*
6726          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6727          * but we don't support that).
6728          * Note: don't use the DAC post divider as it seems unstable.
6729          */
6730         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6731         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6732
6733         mdiv |= DPIO_ENABLE_CALIBRATION;
6734         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6735
6736         /* Set HBR and RBR LPF coefficients */
6737         if (pipe_config->port_clock == 162000 ||
6738             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6739             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6740                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6741                                  0x009f0003);
6742         else
6743                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6744                                  0x00d0000f);
6745
6746         if (intel_crtc_has_dp_encoder(pipe_config)) {
6747                 /* Use SSC source */
6748                 if (pipe == PIPE_A)
6749                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6750                                          0x0df40000);
6751                 else
6752                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6753                                          0x0df70000);
6754         } else { /* HDMI or VGA */
6755                 /* Use bend source */
6756                 if (pipe == PIPE_A)
6757                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6758                                          0x0df70000);
6759                 else
6760                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6761                                          0x0df40000);
6762         }
6763
6764         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6765         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6766         if (intel_crtc_has_dp_encoder(crtc->config))
6767                 coreclk |= 0x01000000;
6768         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6769
6770         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6771         mutex_unlock(&dev_priv->sb_lock);
6772 }
6773
6774 static void chv_prepare_pll(struct intel_crtc *crtc,
6775                             const struct intel_crtc_state *pipe_config)
6776 {
6777         struct drm_device *dev = crtc->base.dev;
6778         struct drm_i915_private *dev_priv = to_i915(dev);
6779         enum pipe pipe = crtc->pipe;
6780         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6781         u32 loopfilter, tribuf_calcntr;
6782         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6783         u32 dpio_val;
6784         int vco;
6785
6786         /* Enable Refclk and SSC */
6787         I915_WRITE(DPLL(pipe),
6788                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6789
6790         /* No need to actually set up the DPLL with DSI */
6791         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6792                 return;
6793
6794         bestn = pipe_config->dpll.n;
6795         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6796         bestm1 = pipe_config->dpll.m1;
6797         bestm2 = pipe_config->dpll.m2 >> 22;
6798         bestp1 = pipe_config->dpll.p1;
6799         bestp2 = pipe_config->dpll.p2;
6800         vco = pipe_config->dpll.vco;
6801         dpio_val = 0;
6802         loopfilter = 0;
6803
6804         mutex_lock(&dev_priv->sb_lock);
6805
6806         /* p1 and p2 divider */
6807         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6808                         5 << DPIO_CHV_S1_DIV_SHIFT |
6809                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6810                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6811                         1 << DPIO_CHV_K_DIV_SHIFT);
6812
6813         /* Feedback post-divider - m2 */
6814         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6815
6816         /* Feedback refclk divider - n and m1 */
6817         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6818                         DPIO_CHV_M1_DIV_BY_2 |
6819                         1 << DPIO_CHV_N_DIV_SHIFT);
6820
6821         /* M2 fraction division */
6822         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6823
6824         /* M2 fraction division enable */
6825         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6826         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6827         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6828         if (bestm2_frac)
6829                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6830         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6831
6832         /* Program digital lock detect threshold */
6833         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6834         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6835                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6836         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6837         if (!bestm2_frac)
6838                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6839         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6840
6841         /* Loop filter */
6842         if (vco == 5400000) {
6843                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6844                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6845                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6846                 tribuf_calcntr = 0x9;
6847         } else if (vco <= 6200000) {
6848                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6849                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6850                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6851                 tribuf_calcntr = 0x9;
6852         } else if (vco <= 6480000) {
6853                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6854                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6855                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6856                 tribuf_calcntr = 0x8;
6857         } else {
6858                 /* Not supported. Apply the same limits as in the max case */
6859                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6860                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6861                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6862                 tribuf_calcntr = 0;
6863         }
6864         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6865
6866         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6867         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6868         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6869         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6870
6871         /* AFC Recal */
6872         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6873                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6874                         DPIO_AFC_RECAL);
6875
6876         mutex_unlock(&dev_priv->sb_lock);
6877 }
6878
6879 /**
6880  * vlv_force_pll_on - forcibly enable just the PLL
6881  * @dev_priv: i915 private structure
6882  * @pipe: pipe PLL to enable
6883  * @dpll: PLL configuration
6884  *
6885  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6886  * in cases where we need the PLL enabled even when @pipe is not going to
6887  * be enabled.
6888  */
6889 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6890                      const struct dpll *dpll)
6891 {
6892         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6893         struct intel_crtc_state *pipe_config;
6894
6895         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6896         if (!pipe_config)
6897                 return -ENOMEM;
6898
6899         pipe_config->base.crtc = &crtc->base;
6900         pipe_config->pixel_multiplier = 1;
6901         pipe_config->dpll = *dpll;
6902
6903         if (IS_CHERRYVIEW(dev_priv)) {
6904                 chv_compute_dpll(crtc, pipe_config);
6905                 chv_prepare_pll(crtc, pipe_config);
6906                 chv_enable_pll(crtc, pipe_config);
6907         } else {
6908                 vlv_compute_dpll(crtc, pipe_config);
6909                 vlv_prepare_pll(crtc, pipe_config);
6910                 vlv_enable_pll(crtc, pipe_config);
6911         }
6912
6913         kfree(pipe_config);
6914
6915         return 0;
6916 }
6917
6918 /**
6919  * vlv_force_pll_off - forcibly disable just the PLL
6920  * @dev_priv: i915 private structure
6921  * @pipe: pipe PLL to disable
6922  *
6923  * Disable the PLL for @pipe. To be used in cases where we need
6924  * the PLL enabled even when @pipe is not going to be enabled.
6925  */
6926 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6927 {
6928         if (IS_CHERRYVIEW(dev_priv))
6929                 chv_disable_pll(dev_priv, pipe);
6930         else
6931                 vlv_disable_pll(dev_priv, pipe);
6932 }
6933
6934 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6935                               struct intel_crtc_state *crtc_state,
6936                               struct dpll *reduced_clock)
6937 {
6938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6939         u32 dpll;
6940         struct dpll *clock = &crtc_state->dpll;
6941
6942         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6943
6944         dpll = DPLL_VGA_MODE_DIS;
6945
6946         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6947                 dpll |= DPLLB_MODE_LVDS;
6948         else
6949                 dpll |= DPLLB_MODE_DAC_SERIAL;
6950
6951         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6952             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6953                 dpll |= (crtc_state->pixel_multiplier - 1)
6954                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6955         }
6956
6957         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6958             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6959                 dpll |= DPLL_SDVO_HIGH_SPEED;
6960
6961         if (intel_crtc_has_dp_encoder(crtc_state))
6962                 dpll |= DPLL_SDVO_HIGH_SPEED;
6963
6964         /* compute bitmask from p1 value */
6965         if (IS_PINEVIEW(dev_priv))
6966                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6967         else {
6968                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6969                 if (IS_G4X(dev_priv) && reduced_clock)
6970                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6971         }
6972         switch (clock->p2) {
6973         case 5:
6974                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6975                 break;
6976         case 7:
6977                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6978                 break;
6979         case 10:
6980                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6981                 break;
6982         case 14:
6983                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6984                 break;
6985         }
6986         if (INTEL_GEN(dev_priv) >= 4)
6987                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6988
6989         if (crtc_state->sdvo_tv_clock)
6990                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6991         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6992                  intel_panel_use_ssc(dev_priv))
6993                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6994         else
6995                 dpll |= PLL_REF_INPUT_DREFCLK;
6996
6997         dpll |= DPLL_VCO_ENABLE;
6998         crtc_state->dpll_hw_state.dpll = dpll;
6999
7000         if (INTEL_GEN(dev_priv) >= 4) {
7001                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7002                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7003                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7004         }
7005 }
7006
7007 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7008                               struct intel_crtc_state *crtc_state,
7009                               struct dpll *reduced_clock)
7010 {
7011         struct drm_device *dev = crtc->base.dev;
7012         struct drm_i915_private *dev_priv = to_i915(dev);
7013         u32 dpll;
7014         struct dpll *clock = &crtc_state->dpll;
7015
7016         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7017
7018         dpll = DPLL_VGA_MODE_DIS;
7019
7020         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7021                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7022         } else {
7023                 if (clock->p1 == 2)
7024                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7025                 else
7026                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7027                 if (clock->p2 == 4)
7028                         dpll |= PLL_P2_DIVIDE_BY_4;
7029         }
7030
7031         if (!IS_I830(dev_priv) &&
7032             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
7033                 dpll |= DPLL_DVO_2X_MODE;
7034
7035         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7036             intel_panel_use_ssc(dev_priv))
7037                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7038         else
7039                 dpll |= PLL_REF_INPUT_DREFCLK;
7040
7041         dpll |= DPLL_VCO_ENABLE;
7042         crtc_state->dpll_hw_state.dpll = dpll;
7043 }
7044
7045 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7046 {
7047         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7048         enum pipe pipe = intel_crtc->pipe;
7049         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7050         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7051         uint32_t crtc_vtotal, crtc_vblank_end;
7052         int vsyncshift = 0;
7053
7054         /* We need to be careful not to changed the adjusted mode, for otherwise
7055          * the hw state checker will get angry at the mismatch. */
7056         crtc_vtotal = adjusted_mode->crtc_vtotal;
7057         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7058
7059         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7060                 /* the chip adds 2 halflines automatically */
7061                 crtc_vtotal -= 1;
7062                 crtc_vblank_end -= 1;
7063
7064                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7065                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7066                 else
7067                         vsyncshift = adjusted_mode->crtc_hsync_start -
7068                                 adjusted_mode->crtc_htotal / 2;
7069                 if (vsyncshift < 0)
7070                         vsyncshift += adjusted_mode->crtc_htotal;
7071         }
7072
7073         if (INTEL_GEN(dev_priv) > 3)
7074                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7075
7076         I915_WRITE(HTOTAL(cpu_transcoder),
7077                    (adjusted_mode->crtc_hdisplay - 1) |
7078                    ((adjusted_mode->crtc_htotal - 1) << 16));
7079         I915_WRITE(HBLANK(cpu_transcoder),
7080                    (adjusted_mode->crtc_hblank_start - 1) |
7081                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7082         I915_WRITE(HSYNC(cpu_transcoder),
7083                    (adjusted_mode->crtc_hsync_start - 1) |
7084                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7085
7086         I915_WRITE(VTOTAL(cpu_transcoder),
7087                    (adjusted_mode->crtc_vdisplay - 1) |
7088                    ((crtc_vtotal - 1) << 16));
7089         I915_WRITE(VBLANK(cpu_transcoder),
7090                    (adjusted_mode->crtc_vblank_start - 1) |
7091                    ((crtc_vblank_end - 1) << 16));
7092         I915_WRITE(VSYNC(cpu_transcoder),
7093                    (adjusted_mode->crtc_vsync_start - 1) |
7094                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7095
7096         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7097          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7098          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7099          * bits. */
7100         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
7101             (pipe == PIPE_B || pipe == PIPE_C))
7102                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7103
7104 }
7105
7106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7107 {
7108         struct drm_device *dev = intel_crtc->base.dev;
7109         struct drm_i915_private *dev_priv = to_i915(dev);
7110         enum pipe pipe = intel_crtc->pipe;
7111
7112         /* pipesrc controls the size that is scaled from, which should
7113          * always be the user's requested size.
7114          */
7115         I915_WRITE(PIPESRC(pipe),
7116                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7117                    (intel_crtc->config->pipe_src_h - 1));
7118 }
7119
7120 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7121                                    struct intel_crtc_state *pipe_config)
7122 {
7123         struct drm_device *dev = crtc->base.dev;
7124         struct drm_i915_private *dev_priv = to_i915(dev);
7125         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7126         uint32_t tmp;
7127
7128         tmp = I915_READ(HTOTAL(cpu_transcoder));
7129         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7130         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7131         tmp = I915_READ(HBLANK(cpu_transcoder));
7132         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7133         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7134         tmp = I915_READ(HSYNC(cpu_transcoder));
7135         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7136         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7137
7138         tmp = I915_READ(VTOTAL(cpu_transcoder));
7139         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7140         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7141         tmp = I915_READ(VBLANK(cpu_transcoder));
7142         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7143         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7144         tmp = I915_READ(VSYNC(cpu_transcoder));
7145         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7146         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7147
7148         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7149                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7150                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7151                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7152         }
7153 }
7154
7155 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7156                                     struct intel_crtc_state *pipe_config)
7157 {
7158         struct drm_device *dev = crtc->base.dev;
7159         struct drm_i915_private *dev_priv = to_i915(dev);
7160         u32 tmp;
7161
7162         tmp = I915_READ(PIPESRC(crtc->pipe));
7163         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7164         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7165
7166         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7167         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7168 }
7169
7170 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7171                                  struct intel_crtc_state *pipe_config)
7172 {
7173         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7174         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7175         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7176         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7177
7178         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7179         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7180         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7181         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7182
7183         mode->flags = pipe_config->base.adjusted_mode.flags;
7184         mode->type = DRM_MODE_TYPE_DRIVER;
7185
7186         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7187
7188         mode->hsync = drm_mode_hsync(mode);
7189         mode->vrefresh = drm_mode_vrefresh(mode);
7190         drm_mode_set_name(mode);
7191 }
7192
7193 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7194 {
7195         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7196         uint32_t pipeconf;
7197
7198         pipeconf = 0;
7199
7200         /* we keep both pipes enabled on 830 */
7201         if (IS_I830(dev_priv))
7202                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7203
7204         if (intel_crtc->config->double_wide)
7205                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7206
7207         /* only g4x and later have fancy bpc/dither controls */
7208         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7209             IS_CHERRYVIEW(dev_priv)) {
7210                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7211                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7212                         pipeconf |= PIPECONF_DITHER_EN |
7213                                     PIPECONF_DITHER_TYPE_SP;
7214
7215                 switch (intel_crtc->config->pipe_bpp) {
7216                 case 18:
7217                         pipeconf |= PIPECONF_6BPC;
7218                         break;
7219                 case 24:
7220                         pipeconf |= PIPECONF_8BPC;
7221                         break;
7222                 case 30:
7223                         pipeconf |= PIPECONF_10BPC;
7224                         break;
7225                 default:
7226                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7227                         BUG();
7228                 }
7229         }
7230
7231         if (HAS_PIPE_CXSR(dev_priv)) {
7232                 if (intel_crtc->lowfreq_avail) {
7233                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7234                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7235                 } else {
7236                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7237                 }
7238         }
7239
7240         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7241                 if (INTEL_GEN(dev_priv) < 4 ||
7242                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7243                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7244                 else
7245                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7246         } else
7247                 pipeconf |= PIPECONF_PROGRESSIVE;
7248
7249         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7250              intel_crtc->config->limited_color_range)
7251                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7252
7253         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7254         POSTING_READ(PIPECONF(intel_crtc->pipe));
7255 }
7256
7257 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7258                                    struct intel_crtc_state *crtc_state)
7259 {
7260         struct drm_device *dev = crtc->base.dev;
7261         struct drm_i915_private *dev_priv = to_i915(dev);
7262         const struct intel_limit *limit;
7263         int refclk = 48000;
7264
7265         memset(&crtc_state->dpll_hw_state, 0,
7266                sizeof(crtc_state->dpll_hw_state));
7267
7268         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7269                 if (intel_panel_use_ssc(dev_priv)) {
7270                         refclk = dev_priv->vbt.lvds_ssc_freq;
7271                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7272                 }
7273
7274                 limit = &intel_limits_i8xx_lvds;
7275         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7276                 limit = &intel_limits_i8xx_dvo;
7277         } else {
7278                 limit = &intel_limits_i8xx_dac;
7279         }
7280
7281         if (!crtc_state->clock_set &&
7282             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7283                                  refclk, NULL, &crtc_state->dpll)) {
7284                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7285                 return -EINVAL;
7286         }
7287
7288         i8xx_compute_dpll(crtc, crtc_state, NULL);
7289
7290         return 0;
7291 }
7292
7293 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7294                                   struct intel_crtc_state *crtc_state)
7295 {
7296         struct drm_device *dev = crtc->base.dev;
7297         struct drm_i915_private *dev_priv = to_i915(dev);
7298         const struct intel_limit *limit;
7299         int refclk = 96000;
7300
7301         memset(&crtc_state->dpll_hw_state, 0,
7302                sizeof(crtc_state->dpll_hw_state));
7303
7304         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7305                 if (intel_panel_use_ssc(dev_priv)) {
7306                         refclk = dev_priv->vbt.lvds_ssc_freq;
7307                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7308                 }
7309
7310                 if (intel_is_dual_link_lvds(dev))
7311                         limit = &intel_limits_g4x_dual_channel_lvds;
7312                 else
7313                         limit = &intel_limits_g4x_single_channel_lvds;
7314         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7315                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7316                 limit = &intel_limits_g4x_hdmi;
7317         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7318                 limit = &intel_limits_g4x_sdvo;
7319         } else {
7320                 /* The option is for other outputs */
7321                 limit = &intel_limits_i9xx_sdvo;
7322         }
7323
7324         if (!crtc_state->clock_set &&
7325             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7326                                 refclk, NULL, &crtc_state->dpll)) {
7327                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7328                 return -EINVAL;
7329         }
7330
7331         i9xx_compute_dpll(crtc, crtc_state, NULL);
7332
7333         return 0;
7334 }
7335
7336 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7337                                   struct intel_crtc_state *crtc_state)
7338 {
7339         struct drm_device *dev = crtc->base.dev;
7340         struct drm_i915_private *dev_priv = to_i915(dev);
7341         const struct intel_limit *limit;
7342         int refclk = 96000;
7343
7344         memset(&crtc_state->dpll_hw_state, 0,
7345                sizeof(crtc_state->dpll_hw_state));
7346
7347         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7348                 if (intel_panel_use_ssc(dev_priv)) {
7349                         refclk = dev_priv->vbt.lvds_ssc_freq;
7350                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7351                 }
7352
7353                 limit = &intel_limits_pineview_lvds;
7354         } else {
7355                 limit = &intel_limits_pineview_sdvo;
7356         }
7357
7358         if (!crtc_state->clock_set &&
7359             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7360                                 refclk, NULL, &crtc_state->dpll)) {
7361                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7362                 return -EINVAL;
7363         }
7364
7365         i9xx_compute_dpll(crtc, crtc_state, NULL);
7366
7367         return 0;
7368 }
7369
7370 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7371                                    struct intel_crtc_state *crtc_state)
7372 {
7373         struct drm_device *dev = crtc->base.dev;
7374         struct drm_i915_private *dev_priv = to_i915(dev);
7375         const struct intel_limit *limit;
7376         int refclk = 96000;
7377
7378         memset(&crtc_state->dpll_hw_state, 0,
7379                sizeof(crtc_state->dpll_hw_state));
7380
7381         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7382                 if (intel_panel_use_ssc(dev_priv)) {
7383                         refclk = dev_priv->vbt.lvds_ssc_freq;
7384                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7385                 }
7386
7387                 limit = &intel_limits_i9xx_lvds;
7388         } else {
7389                 limit = &intel_limits_i9xx_sdvo;
7390         }
7391
7392         if (!crtc_state->clock_set &&
7393             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7394                                  refclk, NULL, &crtc_state->dpll)) {
7395                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7396                 return -EINVAL;
7397         }
7398
7399         i9xx_compute_dpll(crtc, crtc_state, NULL);
7400
7401         return 0;
7402 }
7403
7404 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7405                                   struct intel_crtc_state *crtc_state)
7406 {
7407         int refclk = 100000;
7408         const struct intel_limit *limit = &intel_limits_chv;
7409
7410         memset(&crtc_state->dpll_hw_state, 0,
7411                sizeof(crtc_state->dpll_hw_state));
7412
7413         if (!crtc_state->clock_set &&
7414             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7415                                 refclk, NULL, &crtc_state->dpll)) {
7416                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7417                 return -EINVAL;
7418         }
7419
7420         chv_compute_dpll(crtc, crtc_state);
7421
7422         return 0;
7423 }
7424
7425 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7426                                   struct intel_crtc_state *crtc_state)
7427 {
7428         int refclk = 100000;
7429         const struct intel_limit *limit = &intel_limits_vlv;
7430
7431         memset(&crtc_state->dpll_hw_state, 0,
7432                sizeof(crtc_state->dpll_hw_state));
7433
7434         if (!crtc_state->clock_set &&
7435             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7436                                 refclk, NULL, &crtc_state->dpll)) {
7437                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7438                 return -EINVAL;
7439         }
7440
7441         vlv_compute_dpll(crtc, crtc_state);
7442
7443         return 0;
7444 }
7445
7446 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7447                                  struct intel_crtc_state *pipe_config)
7448 {
7449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7450         uint32_t tmp;
7451
7452         if (INTEL_GEN(dev_priv) <= 3 &&
7453             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7454                 return;
7455
7456         tmp = I915_READ(PFIT_CONTROL);
7457         if (!(tmp & PFIT_ENABLE))
7458                 return;
7459
7460         /* Check whether the pfit is attached to our pipe. */
7461         if (INTEL_GEN(dev_priv) < 4) {
7462                 if (crtc->pipe != PIPE_B)
7463                         return;
7464         } else {
7465                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7466                         return;
7467         }
7468
7469         pipe_config->gmch_pfit.control = tmp;
7470         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7471 }
7472
7473 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7474                                struct intel_crtc_state *pipe_config)
7475 {
7476         struct drm_device *dev = crtc->base.dev;
7477         struct drm_i915_private *dev_priv = to_i915(dev);
7478         int pipe = pipe_config->cpu_transcoder;
7479         struct dpll clock;
7480         u32 mdiv;
7481         int refclk = 100000;
7482
7483         /* In case of DSI, DPLL will not be used */
7484         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7485                 return;
7486
7487         mutex_lock(&dev_priv->sb_lock);
7488         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7489         mutex_unlock(&dev_priv->sb_lock);
7490
7491         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7492         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7493         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7494         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7495         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7496
7497         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7498 }
7499
7500 static void
7501 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7502                               struct intel_initial_plane_config *plane_config)
7503 {
7504         struct drm_device *dev = crtc->base.dev;
7505         struct drm_i915_private *dev_priv = to_i915(dev);
7506         u32 val, base, offset;
7507         int pipe = crtc->pipe, plane = crtc->plane;
7508         int fourcc, pixel_format;
7509         unsigned int aligned_height;
7510         struct drm_framebuffer *fb;
7511         struct intel_framebuffer *intel_fb;
7512
7513         val = I915_READ(DSPCNTR(plane));
7514         if (!(val & DISPLAY_PLANE_ENABLE))
7515                 return;
7516
7517         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7518         if (!intel_fb) {
7519                 DRM_DEBUG_KMS("failed to alloc fb\n");
7520                 return;
7521         }
7522
7523         fb = &intel_fb->base;
7524
7525         fb->dev = dev;
7526
7527         if (INTEL_GEN(dev_priv) >= 4) {
7528                 if (val & DISPPLANE_TILED) {
7529                         plane_config->tiling = I915_TILING_X;
7530                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7531                 }
7532         }
7533
7534         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7535         fourcc = i9xx_format_to_fourcc(pixel_format);
7536         fb->format = drm_format_info(fourcc);
7537
7538         if (INTEL_GEN(dev_priv) >= 4) {
7539                 if (plane_config->tiling)
7540                         offset = I915_READ(DSPTILEOFF(plane));
7541                 else
7542                         offset = I915_READ(DSPLINOFF(plane));
7543                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7544         } else {
7545                 base = I915_READ(DSPADDR(plane));
7546         }
7547         plane_config->base = base;
7548
7549         val = I915_READ(PIPESRC(pipe));
7550         fb->width = ((val >> 16) & 0xfff) + 1;
7551         fb->height = ((val >> 0) & 0xfff) + 1;
7552
7553         val = I915_READ(DSPSTRIDE(pipe));
7554         fb->pitches[0] = val & 0xffffffc0;
7555
7556         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7557
7558         plane_config->size = fb->pitches[0] * aligned_height;
7559
7560         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7561                       pipe_name(pipe), plane, fb->width, fb->height,
7562                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7563                       plane_config->size);
7564
7565         plane_config->fb = intel_fb;
7566 }
7567
7568 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7569                                struct intel_crtc_state *pipe_config)
7570 {
7571         struct drm_device *dev = crtc->base.dev;
7572         struct drm_i915_private *dev_priv = to_i915(dev);
7573         int pipe = pipe_config->cpu_transcoder;
7574         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7575         struct dpll clock;
7576         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7577         int refclk = 100000;
7578
7579         /* In case of DSI, DPLL will not be used */
7580         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7581                 return;
7582
7583         mutex_lock(&dev_priv->sb_lock);
7584         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7585         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7586         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7587         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7588         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7589         mutex_unlock(&dev_priv->sb_lock);
7590
7591         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7592         clock.m2 = (pll_dw0 & 0xff) << 22;
7593         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7594                 clock.m2 |= pll_dw2 & 0x3fffff;
7595         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7596         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7597         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7598
7599         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7600 }
7601
7602 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7603                                  struct intel_crtc_state *pipe_config)
7604 {
7605         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7606         enum intel_display_power_domain power_domain;
7607         uint32_t tmp;
7608         bool ret;
7609
7610         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7611         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7612                 return false;
7613
7614         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7615         pipe_config->shared_dpll = NULL;
7616
7617         ret = false;
7618
7619         tmp = I915_READ(PIPECONF(crtc->pipe));
7620         if (!(tmp & PIPECONF_ENABLE))
7621                 goto out;
7622
7623         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7624             IS_CHERRYVIEW(dev_priv)) {
7625                 switch (tmp & PIPECONF_BPC_MASK) {
7626                 case PIPECONF_6BPC:
7627                         pipe_config->pipe_bpp = 18;
7628                         break;
7629                 case PIPECONF_8BPC:
7630                         pipe_config->pipe_bpp = 24;
7631                         break;
7632                 case PIPECONF_10BPC:
7633                         pipe_config->pipe_bpp = 30;
7634                         break;
7635                 default:
7636                         break;
7637                 }
7638         }
7639
7640         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7641             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7642                 pipe_config->limited_color_range = true;
7643
7644         if (INTEL_GEN(dev_priv) < 4)
7645                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7646
7647         intel_get_pipe_timings(crtc, pipe_config);
7648         intel_get_pipe_src_size(crtc, pipe_config);
7649
7650         i9xx_get_pfit_config(crtc, pipe_config);
7651
7652         if (INTEL_GEN(dev_priv) >= 4) {
7653                 /* No way to read it out on pipes B and C */
7654                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7655                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7656                 else
7657                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7658                 pipe_config->pixel_multiplier =
7659                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7660                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7661                 pipe_config->dpll_hw_state.dpll_md = tmp;
7662         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7663                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7664                 tmp = I915_READ(DPLL(crtc->pipe));
7665                 pipe_config->pixel_multiplier =
7666                         ((tmp & SDVO_MULTIPLIER_MASK)
7667                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7668         } else {
7669                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7670                  * port and will be fixed up in the encoder->get_config
7671                  * function. */
7672                 pipe_config->pixel_multiplier = 1;
7673         }
7674         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7675         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7676                 /*
7677                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7678                  * on 830. Filter it out here so that we don't
7679                  * report errors due to that.
7680                  */
7681                 if (IS_I830(dev_priv))
7682                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7683
7684                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7685                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7686         } else {
7687                 /* Mask out read-only status bits. */
7688                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7689                                                      DPLL_PORTC_READY_MASK |
7690                                                      DPLL_PORTB_READY_MASK);
7691         }
7692
7693         if (IS_CHERRYVIEW(dev_priv))
7694                 chv_crtc_clock_get(crtc, pipe_config);
7695         else if (IS_VALLEYVIEW(dev_priv))
7696                 vlv_crtc_clock_get(crtc, pipe_config);
7697         else
7698                 i9xx_crtc_clock_get(crtc, pipe_config);
7699
7700         /*
7701          * Normally the dotclock is filled in by the encoder .get_config()
7702          * but in case the pipe is enabled w/o any ports we need a sane
7703          * default.
7704          */
7705         pipe_config->base.adjusted_mode.crtc_clock =
7706                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7707
7708         ret = true;
7709
7710 out:
7711         intel_display_power_put(dev_priv, power_domain);
7712
7713         return ret;
7714 }
7715
7716 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7717 {
7718         struct intel_encoder *encoder;
7719         int i;
7720         u32 val, final;
7721         bool has_lvds = false;
7722         bool has_cpu_edp = false;
7723         bool has_panel = false;
7724         bool has_ck505 = false;
7725         bool can_ssc = false;
7726         bool using_ssc_source = false;
7727
7728         /* We need to take the global config into account */
7729         for_each_intel_encoder(&dev_priv->drm, encoder) {
7730                 switch (encoder->type) {
7731                 case INTEL_OUTPUT_LVDS:
7732                         has_panel = true;
7733                         has_lvds = true;
7734                         break;
7735                 case INTEL_OUTPUT_EDP:
7736                         has_panel = true;
7737                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7738                                 has_cpu_edp = true;
7739                         break;
7740                 default:
7741                         break;
7742                 }
7743         }
7744
7745         if (HAS_PCH_IBX(dev_priv)) {
7746                 has_ck505 = dev_priv->vbt.display_clock_mode;
7747                 can_ssc = has_ck505;
7748         } else {
7749                 has_ck505 = false;
7750                 can_ssc = true;
7751         }
7752
7753         /* Check if any DPLLs are using the SSC source */
7754         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7755                 u32 temp = I915_READ(PCH_DPLL(i));
7756
7757                 if (!(temp & DPLL_VCO_ENABLE))
7758                         continue;
7759
7760                 if ((temp & PLL_REF_INPUT_MASK) ==
7761                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7762                         using_ssc_source = true;
7763                         break;
7764                 }
7765         }
7766
7767         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7768                       has_panel, has_lvds, has_ck505, using_ssc_source);
7769
7770         /* Ironlake: try to setup display ref clock before DPLL
7771          * enabling. This is only under driver's control after
7772          * PCH B stepping, previous chipset stepping should be
7773          * ignoring this setting.
7774          */
7775         val = I915_READ(PCH_DREF_CONTROL);
7776
7777         /* As we must carefully and slowly disable/enable each source in turn,
7778          * compute the final state we want first and check if we need to
7779          * make any changes at all.
7780          */
7781         final = val;
7782         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7783         if (has_ck505)
7784                 final |= DREF_NONSPREAD_CK505_ENABLE;
7785         else
7786                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7787
7788         final &= ~DREF_SSC_SOURCE_MASK;
7789         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7790         final &= ~DREF_SSC1_ENABLE;
7791
7792         if (has_panel) {
7793                 final |= DREF_SSC_SOURCE_ENABLE;
7794
7795                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7796                         final |= DREF_SSC1_ENABLE;
7797
7798                 if (has_cpu_edp) {
7799                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7800                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7801                         else
7802                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7803                 } else
7804                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7805         } else if (using_ssc_source) {
7806                 final |= DREF_SSC_SOURCE_ENABLE;
7807                 final |= DREF_SSC1_ENABLE;
7808         }
7809
7810         if (final == val)
7811                 return;
7812
7813         /* Always enable nonspread source */
7814         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7815
7816         if (has_ck505)
7817                 val |= DREF_NONSPREAD_CK505_ENABLE;
7818         else
7819                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7820
7821         if (has_panel) {
7822                 val &= ~DREF_SSC_SOURCE_MASK;
7823                 val |= DREF_SSC_SOURCE_ENABLE;
7824
7825                 /* SSC must be turned on before enabling the CPU output  */
7826                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7827                         DRM_DEBUG_KMS("Using SSC on panel\n");
7828                         val |= DREF_SSC1_ENABLE;
7829                 } else
7830                         val &= ~DREF_SSC1_ENABLE;
7831
7832                 /* Get SSC going before enabling the outputs */
7833                 I915_WRITE(PCH_DREF_CONTROL, val);
7834                 POSTING_READ(PCH_DREF_CONTROL);
7835                 udelay(200);
7836
7837                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7838
7839                 /* Enable CPU source on CPU attached eDP */
7840                 if (has_cpu_edp) {
7841                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7842                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7843                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7844                         } else
7845                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7846                 } else
7847                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7848
7849                 I915_WRITE(PCH_DREF_CONTROL, val);
7850                 POSTING_READ(PCH_DREF_CONTROL);
7851                 udelay(200);
7852         } else {
7853                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7854
7855                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7856
7857                 /* Turn off CPU output */
7858                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7859
7860                 I915_WRITE(PCH_DREF_CONTROL, val);
7861                 POSTING_READ(PCH_DREF_CONTROL);
7862                 udelay(200);
7863
7864                 if (!using_ssc_source) {
7865                         DRM_DEBUG_KMS("Disabling SSC source\n");
7866
7867                         /* Turn off the SSC source */
7868                         val &= ~DREF_SSC_SOURCE_MASK;
7869                         val |= DREF_SSC_SOURCE_DISABLE;
7870
7871                         /* Turn off SSC1 */
7872                         val &= ~DREF_SSC1_ENABLE;
7873
7874                         I915_WRITE(PCH_DREF_CONTROL, val);
7875                         POSTING_READ(PCH_DREF_CONTROL);
7876                         udelay(200);
7877                 }
7878         }
7879
7880         BUG_ON(val != final);
7881 }
7882
7883 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7884 {
7885         uint32_t tmp;
7886
7887         tmp = I915_READ(SOUTH_CHICKEN2);
7888         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7889         I915_WRITE(SOUTH_CHICKEN2, tmp);
7890
7891         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7892                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7893                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7894
7895         tmp = I915_READ(SOUTH_CHICKEN2);
7896         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7897         I915_WRITE(SOUTH_CHICKEN2, tmp);
7898
7899         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7900                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7901                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7902 }
7903
7904 /* WaMPhyProgramming:hsw */
7905 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7906 {
7907         uint32_t tmp;
7908
7909         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7910         tmp &= ~(0xFF << 24);
7911         tmp |= (0x12 << 24);
7912         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7913
7914         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7915         tmp |= (1 << 11);
7916         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7917
7918         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7919         tmp |= (1 << 11);
7920         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7921
7922         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7923         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7924         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7925
7926         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7927         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7928         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7929
7930         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7931         tmp &= ~(7 << 13);
7932         tmp |= (5 << 13);
7933         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7934
7935         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7936         tmp &= ~(7 << 13);
7937         tmp |= (5 << 13);
7938         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7939
7940         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7941         tmp &= ~0xFF;
7942         tmp |= 0x1C;
7943         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7944
7945         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7946         tmp &= ~0xFF;
7947         tmp |= 0x1C;
7948         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7949
7950         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7951         tmp &= ~(0xFF << 16);
7952         tmp |= (0x1C << 16);
7953         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7954
7955         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7956         tmp &= ~(0xFF << 16);
7957         tmp |= (0x1C << 16);
7958         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7959
7960         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7961         tmp |= (1 << 27);
7962         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7963
7964         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7965         tmp |= (1 << 27);
7966         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7967
7968         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7969         tmp &= ~(0xF << 28);
7970         tmp |= (4 << 28);
7971         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7972
7973         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7974         tmp &= ~(0xF << 28);
7975         tmp |= (4 << 28);
7976         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7977 }
7978
7979 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7980  * Programming" based on the parameters passed:
7981  * - Sequence to enable CLKOUT_DP
7982  * - Sequence to enable CLKOUT_DP without spread
7983  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7984  */
7985 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7986                                  bool with_spread, bool with_fdi)
7987 {
7988         uint32_t reg, tmp;
7989
7990         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7991                 with_spread = true;
7992         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7993             with_fdi, "LP PCH doesn't have FDI\n"))
7994                 with_fdi = false;
7995
7996         mutex_lock(&dev_priv->sb_lock);
7997
7998         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7999         tmp &= ~SBI_SSCCTL_DISABLE;
8000         tmp |= SBI_SSCCTL_PATHALT;
8001         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8002
8003         udelay(24);
8004
8005         if (with_spread) {
8006                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8007                 tmp &= ~SBI_SSCCTL_PATHALT;
8008                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8009
8010                 if (with_fdi) {
8011                         lpt_reset_fdi_mphy(dev_priv);
8012                         lpt_program_fdi_mphy(dev_priv);
8013                 }
8014         }
8015
8016         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8017         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8018         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8019         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8020
8021         mutex_unlock(&dev_priv->sb_lock);
8022 }
8023
8024 /* Sequence to disable CLKOUT_DP */
8025 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
8026 {
8027         uint32_t reg, tmp;
8028
8029         mutex_lock(&dev_priv->sb_lock);
8030
8031         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
8032         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8033         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8034         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8035
8036         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8037         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8038                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8039                         tmp |= SBI_SSCCTL_PATHALT;
8040                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8041                         udelay(32);
8042                 }
8043                 tmp |= SBI_SSCCTL_DISABLE;
8044                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8045         }
8046
8047         mutex_unlock(&dev_priv->sb_lock);
8048 }
8049
8050 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8051
8052 static const uint16_t sscdivintphase[] = {
8053         [BEND_IDX( 50)] = 0x3B23,
8054         [BEND_IDX( 45)] = 0x3B23,
8055         [BEND_IDX( 40)] = 0x3C23,
8056         [BEND_IDX( 35)] = 0x3C23,
8057         [BEND_IDX( 30)] = 0x3D23,
8058         [BEND_IDX( 25)] = 0x3D23,
8059         [BEND_IDX( 20)] = 0x3E23,
8060         [BEND_IDX( 15)] = 0x3E23,
8061         [BEND_IDX( 10)] = 0x3F23,
8062         [BEND_IDX(  5)] = 0x3F23,
8063         [BEND_IDX(  0)] = 0x0025,
8064         [BEND_IDX( -5)] = 0x0025,
8065         [BEND_IDX(-10)] = 0x0125,
8066         [BEND_IDX(-15)] = 0x0125,
8067         [BEND_IDX(-20)] = 0x0225,
8068         [BEND_IDX(-25)] = 0x0225,
8069         [BEND_IDX(-30)] = 0x0325,
8070         [BEND_IDX(-35)] = 0x0325,
8071         [BEND_IDX(-40)] = 0x0425,
8072         [BEND_IDX(-45)] = 0x0425,
8073         [BEND_IDX(-50)] = 0x0525,
8074 };
8075
8076 /*
8077  * Bend CLKOUT_DP
8078  * steps -50 to 50 inclusive, in steps of 5
8079  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8080  * change in clock period = -(steps / 10) * 5.787 ps
8081  */
8082 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8083 {
8084         uint32_t tmp;
8085         int idx = BEND_IDX(steps);
8086
8087         if (WARN_ON(steps % 5 != 0))
8088                 return;
8089
8090         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8091                 return;
8092
8093         mutex_lock(&dev_priv->sb_lock);
8094
8095         if (steps % 10 != 0)
8096                 tmp = 0xAAAAAAAB;
8097         else
8098                 tmp = 0x00000000;
8099         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8100
8101         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8102         tmp &= 0xffff0000;
8103         tmp |= sscdivintphase[idx];
8104         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8105
8106         mutex_unlock(&dev_priv->sb_lock);
8107 }
8108
8109 #undef BEND_IDX
8110
8111 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
8112 {
8113         struct intel_encoder *encoder;
8114         bool has_vga = false;
8115
8116         for_each_intel_encoder(&dev_priv->drm, encoder) {
8117                 switch (encoder->type) {
8118                 case INTEL_OUTPUT_ANALOG:
8119                         has_vga = true;
8120                         break;
8121                 default:
8122                         break;
8123                 }
8124         }
8125
8126         if (has_vga) {
8127                 lpt_bend_clkout_dp(dev_priv, 0);
8128                 lpt_enable_clkout_dp(dev_priv, true, true);
8129         } else {
8130                 lpt_disable_clkout_dp(dev_priv);
8131         }
8132 }
8133
8134 /*
8135  * Initialize reference clocks when the driver loads
8136  */
8137 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
8138 {
8139         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
8140                 ironlake_init_pch_refclk(dev_priv);
8141         else if (HAS_PCH_LPT(dev_priv))
8142                 lpt_init_pch_refclk(dev_priv);
8143 }
8144
8145 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8146 {
8147         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8149         int pipe = intel_crtc->pipe;
8150         uint32_t val;
8151
8152         val = 0;
8153
8154         switch (intel_crtc->config->pipe_bpp) {
8155         case 18:
8156                 val |= PIPECONF_6BPC;
8157                 break;
8158         case 24:
8159                 val |= PIPECONF_8BPC;
8160                 break;
8161         case 30:
8162                 val |= PIPECONF_10BPC;
8163                 break;
8164         case 36:
8165                 val |= PIPECONF_12BPC;
8166                 break;
8167         default:
8168                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8169                 BUG();
8170         }
8171
8172         if (intel_crtc->config->dither)
8173                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8174
8175         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8176                 val |= PIPECONF_INTERLACED_ILK;
8177         else
8178                 val |= PIPECONF_PROGRESSIVE;
8179
8180         if (intel_crtc->config->limited_color_range)
8181                 val |= PIPECONF_COLOR_RANGE_SELECT;
8182
8183         I915_WRITE(PIPECONF(pipe), val);
8184         POSTING_READ(PIPECONF(pipe));
8185 }
8186
8187 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8188 {
8189         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8191         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8192         u32 val = 0;
8193
8194         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8195                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8196
8197         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8198                 val |= PIPECONF_INTERLACED_ILK;
8199         else
8200                 val |= PIPECONF_PROGRESSIVE;
8201
8202         I915_WRITE(PIPECONF(cpu_transcoder), val);
8203         POSTING_READ(PIPECONF(cpu_transcoder));
8204 }
8205
8206 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8207 {
8208         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210         struct intel_crtc_state *config = intel_crtc->config;
8211
8212         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8213                 u32 val = 0;
8214
8215                 switch (intel_crtc->config->pipe_bpp) {
8216                 case 18:
8217                         val |= PIPEMISC_DITHER_6_BPC;
8218                         break;
8219                 case 24:
8220                         val |= PIPEMISC_DITHER_8_BPC;
8221                         break;
8222                 case 30:
8223                         val |= PIPEMISC_DITHER_10_BPC;
8224                         break;
8225                 case 36:
8226                         val |= PIPEMISC_DITHER_12_BPC;
8227                         break;
8228                 default:
8229                         /* Case prevented by pipe_config_set_bpp. */
8230                         BUG();
8231                 }
8232
8233                 if (intel_crtc->config->dither)
8234                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8235
8236                 if (config->ycbcr420) {
8237                         val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |
8238                                 PIPEMISC_YUV420_ENABLE |
8239                                 PIPEMISC_YUV420_MODE_FULL_BLEND;
8240                 }
8241
8242                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8243         }
8244 }
8245
8246 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8247 {
8248         /*
8249          * Account for spread spectrum to avoid
8250          * oversubscribing the link. Max center spread
8251          * is 2.5%; use 5% for safety's sake.
8252          */
8253         u32 bps = target_clock * bpp * 21 / 20;
8254         return DIV_ROUND_UP(bps, link_bw * 8);
8255 }
8256
8257 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8258 {
8259         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8260 }
8261
8262 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8263                                   struct intel_crtc_state *crtc_state,
8264                                   struct dpll *reduced_clock)
8265 {
8266         struct drm_crtc *crtc = &intel_crtc->base;
8267         struct drm_device *dev = crtc->dev;
8268         struct drm_i915_private *dev_priv = to_i915(dev);
8269         u32 dpll, fp, fp2;
8270         int factor;
8271
8272         /* Enable autotuning of the PLL clock (if permissible) */
8273         factor = 21;
8274         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8275                 if ((intel_panel_use_ssc(dev_priv) &&
8276                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8277                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8278                         factor = 25;
8279         } else if (crtc_state->sdvo_tv_clock)
8280                 factor = 20;
8281
8282         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8283
8284         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8285                 fp |= FP_CB_TUNE;
8286
8287         if (reduced_clock) {
8288                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8289
8290                 if (reduced_clock->m < factor * reduced_clock->n)
8291                         fp2 |= FP_CB_TUNE;
8292         } else {
8293                 fp2 = fp;
8294         }
8295
8296         dpll = 0;
8297
8298         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8299                 dpll |= DPLLB_MODE_LVDS;
8300         else
8301                 dpll |= DPLLB_MODE_DAC_SERIAL;
8302
8303         dpll |= (crtc_state->pixel_multiplier - 1)
8304                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8305
8306         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8307             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8308                 dpll |= DPLL_SDVO_HIGH_SPEED;
8309
8310         if (intel_crtc_has_dp_encoder(crtc_state))
8311                 dpll |= DPLL_SDVO_HIGH_SPEED;
8312
8313         /*
8314          * The high speed IO clock is only really required for
8315          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8316          * possible to share the DPLL between CRT and HDMI. Enabling
8317          * the clock needlessly does no real harm, except use up a
8318          * bit of power potentially.
8319          *
8320          * We'll limit this to IVB with 3 pipes, since it has only two
8321          * DPLLs and so DPLL sharing is the only way to get three pipes
8322          * driving PCH ports at the same time. On SNB we could do this,
8323          * and potentially avoid enabling the second DPLL, but it's not
8324          * clear if it''s a win or loss power wise. No point in doing
8325          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8326          */
8327         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8328             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8329                 dpll |= DPLL_SDVO_HIGH_SPEED;
8330
8331         /* compute bitmask from p1 value */
8332         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8333         /* also FPA1 */
8334         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8335
8336         switch (crtc_state->dpll.p2) {
8337         case 5:
8338                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8339                 break;
8340         case 7:
8341                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8342                 break;
8343         case 10:
8344                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8345                 break;
8346         case 14:
8347                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8348                 break;
8349         }
8350
8351         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8352             intel_panel_use_ssc(dev_priv))
8353                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8354         else
8355                 dpll |= PLL_REF_INPUT_DREFCLK;
8356
8357         dpll |= DPLL_VCO_ENABLE;
8358
8359         crtc_state->dpll_hw_state.dpll = dpll;
8360         crtc_state->dpll_hw_state.fp0 = fp;
8361         crtc_state->dpll_hw_state.fp1 = fp2;
8362 }
8363
8364 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8365                                        struct intel_crtc_state *crtc_state)
8366 {
8367         struct drm_device *dev = crtc->base.dev;
8368         struct drm_i915_private *dev_priv = to_i915(dev);
8369         const struct intel_limit *limit;
8370         int refclk = 120000;
8371
8372         memset(&crtc_state->dpll_hw_state, 0,
8373                sizeof(crtc_state->dpll_hw_state));
8374
8375         crtc->lowfreq_avail = false;
8376
8377         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8378         if (!crtc_state->has_pch_encoder)
8379                 return 0;
8380
8381         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8382                 if (intel_panel_use_ssc(dev_priv)) {
8383                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8384                                       dev_priv->vbt.lvds_ssc_freq);
8385                         refclk = dev_priv->vbt.lvds_ssc_freq;
8386                 }
8387
8388                 if (intel_is_dual_link_lvds(dev)) {
8389                         if (refclk == 100000)
8390                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8391                         else
8392                                 limit = &intel_limits_ironlake_dual_lvds;
8393                 } else {
8394                         if (refclk == 100000)
8395                                 limit = &intel_limits_ironlake_single_lvds_100m;
8396                         else
8397                                 limit = &intel_limits_ironlake_single_lvds;
8398                 }
8399         } else {
8400                 limit = &intel_limits_ironlake_dac;
8401         }
8402
8403         if (!crtc_state->clock_set &&
8404             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8405                                 refclk, NULL, &crtc_state->dpll)) {
8406                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8407                 return -EINVAL;
8408         }
8409
8410         ironlake_compute_dpll(crtc, crtc_state, NULL);
8411
8412         if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) {
8413                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8414                                  pipe_name(crtc->pipe));
8415                 return -EINVAL;
8416         }
8417
8418         return 0;
8419 }
8420
8421 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8422                                          struct intel_link_m_n *m_n)
8423 {
8424         struct drm_device *dev = crtc->base.dev;
8425         struct drm_i915_private *dev_priv = to_i915(dev);
8426         enum pipe pipe = crtc->pipe;
8427
8428         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8429         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8430         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8431                 & ~TU_SIZE_MASK;
8432         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8433         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8434                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8435 }
8436
8437 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8438                                          enum transcoder transcoder,
8439                                          struct intel_link_m_n *m_n,
8440                                          struct intel_link_m_n *m2_n2)
8441 {
8442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8443         enum pipe pipe = crtc->pipe;
8444
8445         if (INTEL_GEN(dev_priv) >= 5) {
8446                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8447                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8448                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8449                         & ~TU_SIZE_MASK;
8450                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8451                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8452                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8453                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8454                  * gen < 8) and if DRRS is supported (to make sure the
8455                  * registers are not unnecessarily read).
8456                  */
8457                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8458                         crtc->config->has_drrs) {
8459                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8460                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8461                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8462                                         & ~TU_SIZE_MASK;
8463                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8464                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8465                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8466                 }
8467         } else {
8468                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8469                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8470                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8471                         & ~TU_SIZE_MASK;
8472                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8473                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8474                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8475         }
8476 }
8477
8478 void intel_dp_get_m_n(struct intel_crtc *crtc,
8479                       struct intel_crtc_state *pipe_config)
8480 {
8481         if (pipe_config->has_pch_encoder)
8482                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8483         else
8484                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8485                                              &pipe_config->dp_m_n,
8486                                              &pipe_config->dp_m2_n2);
8487 }
8488
8489 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8490                                         struct intel_crtc_state *pipe_config)
8491 {
8492         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8493                                      &pipe_config->fdi_m_n, NULL);
8494 }
8495
8496 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8497                                     struct intel_crtc_state *pipe_config)
8498 {
8499         struct drm_device *dev = crtc->base.dev;
8500         struct drm_i915_private *dev_priv = to_i915(dev);
8501         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8502         uint32_t ps_ctrl = 0;
8503         int id = -1;
8504         int i;
8505
8506         /* find scaler attached to this pipe */
8507         for (i = 0; i < crtc->num_scalers; i++) {
8508                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8509                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8510                         id = i;
8511                         pipe_config->pch_pfit.enabled = true;
8512                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8513                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8514                         break;
8515                 }
8516         }
8517
8518         scaler_state->scaler_id = id;
8519         if (id >= 0) {
8520                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8521         } else {
8522                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8523         }
8524 }
8525
8526 static void
8527 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8528                                  struct intel_initial_plane_config *plane_config)
8529 {
8530         struct drm_device *dev = crtc->base.dev;
8531         struct drm_i915_private *dev_priv = to_i915(dev);
8532         u32 val, base, offset, stride_mult, tiling;
8533         int pipe = crtc->pipe;
8534         int fourcc, pixel_format;
8535         unsigned int aligned_height;
8536         struct drm_framebuffer *fb;
8537         struct intel_framebuffer *intel_fb;
8538
8539         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8540         if (!intel_fb) {
8541                 DRM_DEBUG_KMS("failed to alloc fb\n");
8542                 return;
8543         }
8544
8545         fb = &intel_fb->base;
8546
8547         fb->dev = dev;
8548
8549         val = I915_READ(PLANE_CTL(pipe, 0));
8550         if (!(val & PLANE_CTL_ENABLE))
8551                 goto error;
8552
8553         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8554         fourcc = skl_format_to_fourcc(pixel_format,
8555                                       val & PLANE_CTL_ORDER_RGBX,
8556                                       val & PLANE_CTL_ALPHA_MASK);
8557         fb->format = drm_format_info(fourcc);
8558
8559         tiling = val & PLANE_CTL_TILED_MASK;
8560         switch (tiling) {
8561         case PLANE_CTL_TILED_LINEAR:
8562                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
8563                 break;
8564         case PLANE_CTL_TILED_X:
8565                 plane_config->tiling = I915_TILING_X;
8566                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8567                 break;
8568         case PLANE_CTL_TILED_Y:
8569                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8570                         fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
8571                 else
8572                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
8573                 break;
8574         case PLANE_CTL_TILED_YF:
8575                 if (val & PLANE_CTL_DECOMPRESSION_ENABLE)
8576                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
8577                 else
8578                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8579                 break;
8580         default:
8581                 MISSING_CASE(tiling);
8582                 goto error;
8583         }
8584
8585         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8586         plane_config->base = base;
8587
8588         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8589
8590         val = I915_READ(PLANE_SIZE(pipe, 0));
8591         fb->height = ((val >> 16) & 0xfff) + 1;
8592         fb->width = ((val >> 0) & 0x1fff) + 1;
8593
8594         val = I915_READ(PLANE_STRIDE(pipe, 0));
8595         stride_mult = intel_fb_stride_alignment(fb, 0);
8596         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8597
8598         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8599
8600         plane_config->size = fb->pitches[0] * aligned_height;
8601
8602         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8603                       pipe_name(pipe), fb->width, fb->height,
8604                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8605                       plane_config->size);
8606
8607         plane_config->fb = intel_fb;
8608         return;
8609
8610 error:
8611         kfree(intel_fb);
8612 }
8613
8614 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8615                                      struct intel_crtc_state *pipe_config)
8616 {
8617         struct drm_device *dev = crtc->base.dev;
8618         struct drm_i915_private *dev_priv = to_i915(dev);
8619         uint32_t tmp;
8620
8621         tmp = I915_READ(PF_CTL(crtc->pipe));
8622
8623         if (tmp & PF_ENABLE) {
8624                 pipe_config->pch_pfit.enabled = true;
8625                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8626                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8627
8628                 /* We currently do not free assignements of panel fitters on
8629                  * ivb/hsw (since we don't use the higher upscaling modes which
8630                  * differentiates them) so just WARN about this case for now. */
8631                 if (IS_GEN7(dev_priv)) {
8632                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8633                                 PF_PIPE_SEL_IVB(crtc->pipe));
8634                 }
8635         }
8636 }
8637
8638 static void
8639 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8640                                   struct intel_initial_plane_config *plane_config)
8641 {
8642         struct drm_device *dev = crtc->base.dev;
8643         struct drm_i915_private *dev_priv = to_i915(dev);
8644         u32 val, base, offset;
8645         int pipe = crtc->pipe;
8646         int fourcc, pixel_format;
8647         unsigned int aligned_height;
8648         struct drm_framebuffer *fb;
8649         struct intel_framebuffer *intel_fb;
8650
8651         val = I915_READ(DSPCNTR(pipe));
8652         if (!(val & DISPLAY_PLANE_ENABLE))
8653                 return;
8654
8655         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8656         if (!intel_fb) {
8657                 DRM_DEBUG_KMS("failed to alloc fb\n");
8658                 return;
8659         }
8660
8661         fb = &intel_fb->base;
8662
8663         fb->dev = dev;
8664
8665         if (INTEL_GEN(dev_priv) >= 4) {
8666                 if (val & DISPPLANE_TILED) {
8667                         plane_config->tiling = I915_TILING_X;
8668                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8669                 }
8670         }
8671
8672         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8673         fourcc = i9xx_format_to_fourcc(pixel_format);
8674         fb->format = drm_format_info(fourcc);
8675
8676         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8677         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8678                 offset = I915_READ(DSPOFFSET(pipe));
8679         } else {
8680                 if (plane_config->tiling)
8681                         offset = I915_READ(DSPTILEOFF(pipe));
8682                 else
8683                         offset = I915_READ(DSPLINOFF(pipe));
8684         }
8685         plane_config->base = base;
8686
8687         val = I915_READ(PIPESRC(pipe));
8688         fb->width = ((val >> 16) & 0xfff) + 1;
8689         fb->height = ((val >> 0) & 0xfff) + 1;
8690
8691         val = I915_READ(DSPSTRIDE(pipe));
8692         fb->pitches[0] = val & 0xffffffc0;
8693
8694         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8695
8696         plane_config->size = fb->pitches[0] * aligned_height;
8697
8698         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8699                       pipe_name(pipe), fb->width, fb->height,
8700                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8701                       plane_config->size);
8702
8703         plane_config->fb = intel_fb;
8704 }
8705
8706 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8707                                      struct intel_crtc_state *pipe_config)
8708 {
8709         struct drm_device *dev = crtc->base.dev;
8710         struct drm_i915_private *dev_priv = to_i915(dev);
8711         enum intel_display_power_domain power_domain;
8712         uint32_t tmp;
8713         bool ret;
8714
8715         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8716         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8717                 return false;
8718
8719         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8720         pipe_config->shared_dpll = NULL;
8721
8722         ret = false;
8723         tmp = I915_READ(PIPECONF(crtc->pipe));
8724         if (!(tmp & PIPECONF_ENABLE))
8725                 goto out;
8726
8727         switch (tmp & PIPECONF_BPC_MASK) {
8728         case PIPECONF_6BPC:
8729                 pipe_config->pipe_bpp = 18;
8730                 break;
8731         case PIPECONF_8BPC:
8732                 pipe_config->pipe_bpp = 24;
8733                 break;
8734         case PIPECONF_10BPC:
8735                 pipe_config->pipe_bpp = 30;
8736                 break;
8737         case PIPECONF_12BPC:
8738                 pipe_config->pipe_bpp = 36;
8739                 break;
8740         default:
8741                 break;
8742         }
8743
8744         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8745                 pipe_config->limited_color_range = true;
8746
8747         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8748                 struct intel_shared_dpll *pll;
8749                 enum intel_dpll_id pll_id;
8750
8751                 pipe_config->has_pch_encoder = true;
8752
8753                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8754                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8755                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8756
8757                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8758
8759                 if (HAS_PCH_IBX(dev_priv)) {
8760                         /*
8761                          * The pipe->pch transcoder and pch transcoder->pll
8762                          * mapping is fixed.
8763                          */
8764                         pll_id = (enum intel_dpll_id) crtc->pipe;
8765                 } else {
8766                         tmp = I915_READ(PCH_DPLL_SEL);
8767                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8768                                 pll_id = DPLL_ID_PCH_PLL_B;
8769                         else
8770                                 pll_id= DPLL_ID_PCH_PLL_A;
8771                 }
8772
8773                 pipe_config->shared_dpll =
8774                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8775                 pll = pipe_config->shared_dpll;
8776
8777                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8778                                                  &pipe_config->dpll_hw_state));
8779
8780                 tmp = pipe_config->dpll_hw_state.dpll;
8781                 pipe_config->pixel_multiplier =
8782                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8783                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8784
8785                 ironlake_pch_clock_get(crtc, pipe_config);
8786         } else {
8787                 pipe_config->pixel_multiplier = 1;
8788         }
8789
8790         intel_get_pipe_timings(crtc, pipe_config);
8791         intel_get_pipe_src_size(crtc, pipe_config);
8792
8793         ironlake_get_pfit_config(crtc, pipe_config);
8794
8795         ret = true;
8796
8797 out:
8798         intel_display_power_put(dev_priv, power_domain);
8799
8800         return ret;
8801 }
8802
8803 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8804 {
8805         struct drm_device *dev = &dev_priv->drm;
8806         struct intel_crtc *crtc;
8807
8808         for_each_intel_crtc(dev, crtc)
8809                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8810                      pipe_name(crtc->pipe));
8811
8812         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)),
8813                         "Display power well on\n");
8814         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8815         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8816         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8817         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8818         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8819              "CPU PWM1 enabled\n");
8820         if (IS_HASWELL(dev_priv))
8821                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8822                      "CPU PWM2 enabled\n");
8823         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8824              "PCH PWM1 enabled\n");
8825         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8826              "Utility pin enabled\n");
8827         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8828
8829         /*
8830          * In theory we can still leave IRQs enabled, as long as only the HPD
8831          * interrupts remain enabled. We used to check for that, but since it's
8832          * gen-specific and since we only disable LCPLL after we fully disable
8833          * the interrupts, the check below should be enough.
8834          */
8835         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8836 }
8837
8838 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8839 {
8840         if (IS_HASWELL(dev_priv))
8841                 return I915_READ(D_COMP_HSW);
8842         else
8843                 return I915_READ(D_COMP_BDW);
8844 }
8845
8846 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8847 {
8848         if (IS_HASWELL(dev_priv)) {
8849                 mutex_lock(&dev_priv->rps.hw_lock);
8850                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8851                                             val))
8852                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8853                 mutex_unlock(&dev_priv->rps.hw_lock);
8854         } else {
8855                 I915_WRITE(D_COMP_BDW, val);
8856                 POSTING_READ(D_COMP_BDW);
8857         }
8858 }
8859
8860 /*
8861  * This function implements pieces of two sequences from BSpec:
8862  * - Sequence for display software to disable LCPLL
8863  * - Sequence for display software to allow package C8+
8864  * The steps implemented here are just the steps that actually touch the LCPLL
8865  * register. Callers should take care of disabling all the display engine
8866  * functions, doing the mode unset, fixing interrupts, etc.
8867  */
8868 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8869                               bool switch_to_fclk, bool allow_power_down)
8870 {
8871         uint32_t val;
8872
8873         assert_can_disable_lcpll(dev_priv);
8874
8875         val = I915_READ(LCPLL_CTL);
8876
8877         if (switch_to_fclk) {
8878                 val |= LCPLL_CD_SOURCE_FCLK;
8879                 I915_WRITE(LCPLL_CTL, val);
8880
8881                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8882                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8883                         DRM_ERROR("Switching to FCLK failed\n");
8884
8885                 val = I915_READ(LCPLL_CTL);
8886         }
8887
8888         val |= LCPLL_PLL_DISABLE;
8889         I915_WRITE(LCPLL_CTL, val);
8890         POSTING_READ(LCPLL_CTL);
8891
8892         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8893                 DRM_ERROR("LCPLL still locked\n");
8894
8895         val = hsw_read_dcomp(dev_priv);
8896         val |= D_COMP_COMP_DISABLE;
8897         hsw_write_dcomp(dev_priv, val);
8898         ndelay(100);
8899
8900         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8901                      1))
8902                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8903
8904         if (allow_power_down) {
8905                 val = I915_READ(LCPLL_CTL);
8906                 val |= LCPLL_POWER_DOWN_ALLOW;
8907                 I915_WRITE(LCPLL_CTL, val);
8908                 POSTING_READ(LCPLL_CTL);
8909         }
8910 }
8911
8912 /*
8913  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8914  * source.
8915  */
8916 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8917 {
8918         uint32_t val;
8919
8920         val = I915_READ(LCPLL_CTL);
8921
8922         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8923                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8924                 return;
8925
8926         /*
8927          * Make sure we're not on PC8 state before disabling PC8, otherwise
8928          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8929          */
8930         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8931
8932         if (val & LCPLL_POWER_DOWN_ALLOW) {
8933                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8934                 I915_WRITE(LCPLL_CTL, val);
8935                 POSTING_READ(LCPLL_CTL);
8936         }
8937
8938         val = hsw_read_dcomp(dev_priv);
8939         val |= D_COMP_COMP_FORCE;
8940         val &= ~D_COMP_COMP_DISABLE;
8941         hsw_write_dcomp(dev_priv, val);
8942
8943         val = I915_READ(LCPLL_CTL);
8944         val &= ~LCPLL_PLL_DISABLE;
8945         I915_WRITE(LCPLL_CTL, val);
8946
8947         if (intel_wait_for_register(dev_priv,
8948                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8949                                     5))
8950                 DRM_ERROR("LCPLL not locked yet\n");
8951
8952         if (val & LCPLL_CD_SOURCE_FCLK) {
8953                 val = I915_READ(LCPLL_CTL);
8954                 val &= ~LCPLL_CD_SOURCE_FCLK;
8955                 I915_WRITE(LCPLL_CTL, val);
8956
8957                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8958                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8959                         DRM_ERROR("Switching back to LCPLL failed\n");
8960         }
8961
8962         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8963         intel_update_cdclk(dev_priv);
8964 }
8965
8966 /*
8967  * Package states C8 and deeper are really deep PC states that can only be
8968  * reached when all the devices on the system allow it, so even if the graphics
8969  * device allows PC8+, it doesn't mean the system will actually get to these
8970  * states. Our driver only allows PC8+ when going into runtime PM.
8971  *
8972  * The requirements for PC8+ are that all the outputs are disabled, the power
8973  * well is disabled and most interrupts are disabled, and these are also
8974  * requirements for runtime PM. When these conditions are met, we manually do
8975  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8976  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8977  * hang the machine.
8978  *
8979  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8980  * the state of some registers, so when we come back from PC8+ we need to
8981  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8982  * need to take care of the registers kept by RC6. Notice that this happens even
8983  * if we don't put the device in PCI D3 state (which is what currently happens
8984  * because of the runtime PM support).
8985  *
8986  * For more, read "Display Sequences for Package C8" on the hardware
8987  * documentation.
8988  */
8989 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8990 {
8991         uint32_t val;
8992
8993         DRM_DEBUG_KMS("Enabling package C8+\n");
8994
8995         if (HAS_PCH_LPT_LP(dev_priv)) {
8996                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8997                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8998                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8999         }
9000
9001         lpt_disable_clkout_dp(dev_priv);
9002         hsw_disable_lcpll(dev_priv, true, true);
9003 }
9004
9005 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9006 {
9007         uint32_t val;
9008
9009         DRM_DEBUG_KMS("Disabling package C8+\n");
9010
9011         hsw_restore_lcpll(dev_priv);
9012         lpt_init_pch_refclk(dev_priv);
9013
9014         if (HAS_PCH_LPT_LP(dev_priv)) {
9015                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9016                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9017                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9018         }
9019 }
9020
9021 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9022                                       struct intel_crtc_state *crtc_state)
9023 {
9024         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
9025                 struct intel_encoder *encoder =
9026                         intel_ddi_get_crtc_new_encoder(crtc_state);
9027
9028                 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
9029                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9030                                          pipe_name(crtc->pipe));
9031                         return -EINVAL;
9032                 }
9033         }
9034
9035         crtc->lowfreq_avail = false;
9036
9037         return 0;
9038 }
9039
9040 static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
9041                                    enum port port,
9042                                    struct intel_crtc_state *pipe_config)
9043 {
9044         enum intel_dpll_id id;
9045         u32 temp;
9046
9047         temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
9048         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
9049
9050         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
9051                 return;
9052
9053         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9054 }
9055
9056 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9057                                 enum port port,
9058                                 struct intel_crtc_state *pipe_config)
9059 {
9060         enum intel_dpll_id id;
9061
9062         switch (port) {
9063         case PORT_A:
9064                 id = DPLL_ID_SKL_DPLL0;
9065                 break;
9066         case PORT_B:
9067                 id = DPLL_ID_SKL_DPLL1;
9068                 break;
9069         case PORT_C:
9070                 id = DPLL_ID_SKL_DPLL2;
9071                 break;
9072         default:
9073                 DRM_ERROR("Incorrect port type\n");
9074                 return;
9075         }
9076
9077         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9078 }
9079
9080 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9081                                 enum port port,
9082                                 struct intel_crtc_state *pipe_config)
9083 {
9084         enum intel_dpll_id id;
9085         u32 temp;
9086
9087         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9088         id = temp >> (port * 3 + 1);
9089
9090         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
9091                 return;
9092
9093         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9094 }
9095
9096 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9097                                 enum port port,
9098                                 struct intel_crtc_state *pipe_config)
9099 {
9100         enum intel_dpll_id id;
9101         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9102
9103         switch (ddi_pll_sel) {
9104         case PORT_CLK_SEL_WRPLL1:
9105                 id = DPLL_ID_WRPLL1;
9106                 break;
9107         case PORT_CLK_SEL_WRPLL2:
9108                 id = DPLL_ID_WRPLL2;
9109                 break;
9110         case PORT_CLK_SEL_SPLL:
9111                 id = DPLL_ID_SPLL;
9112                 break;
9113         case PORT_CLK_SEL_LCPLL_810:
9114                 id = DPLL_ID_LCPLL_810;
9115                 break;
9116         case PORT_CLK_SEL_LCPLL_1350:
9117                 id = DPLL_ID_LCPLL_1350;
9118                 break;
9119         case PORT_CLK_SEL_LCPLL_2700:
9120                 id = DPLL_ID_LCPLL_2700;
9121                 break;
9122         default:
9123                 MISSING_CASE(ddi_pll_sel);
9124                 /* fall through */
9125         case PORT_CLK_SEL_NONE:
9126                 return;
9127         }
9128
9129         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9130 }
9131
9132 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9133                                      struct intel_crtc_state *pipe_config,
9134                                      u64 *power_domain_mask)
9135 {
9136         struct drm_device *dev = crtc->base.dev;
9137         struct drm_i915_private *dev_priv = to_i915(dev);
9138         enum intel_display_power_domain power_domain;
9139         u32 tmp;
9140
9141         /*
9142          * The pipe->transcoder mapping is fixed with the exception of the eDP
9143          * transcoder handled below.
9144          */
9145         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9146
9147         /*
9148          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9149          * consistency and less surprising code; it's in always on power).
9150          */
9151         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9152         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9153                 enum pipe trans_edp_pipe;
9154                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9155                 default:
9156                         WARN(1, "unknown pipe linked to edp transcoder\n");
9157                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9158                 case TRANS_DDI_EDP_INPUT_A_ON:
9159                         trans_edp_pipe = PIPE_A;
9160                         break;
9161                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9162                         trans_edp_pipe = PIPE_B;
9163                         break;
9164                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9165                         trans_edp_pipe = PIPE_C;
9166                         break;
9167                 }
9168
9169                 if (trans_edp_pipe == crtc->pipe)
9170                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9171         }
9172
9173         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9174         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9175                 return false;
9176         *power_domain_mask |= BIT_ULL(power_domain);
9177
9178         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9179
9180         return tmp & PIPECONF_ENABLE;
9181 }
9182
9183 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9184                                          struct intel_crtc_state *pipe_config,
9185                                          u64 *power_domain_mask)
9186 {
9187         struct drm_device *dev = crtc->base.dev;
9188         struct drm_i915_private *dev_priv = to_i915(dev);
9189         enum intel_display_power_domain power_domain;
9190         enum port port;
9191         enum transcoder cpu_transcoder;
9192         u32 tmp;
9193
9194         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9195                 if (port == PORT_A)
9196                         cpu_transcoder = TRANSCODER_DSI_A;
9197                 else
9198                         cpu_transcoder = TRANSCODER_DSI_C;
9199
9200                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9201                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9202                         continue;
9203                 *power_domain_mask |= BIT_ULL(power_domain);
9204
9205                 /*
9206                  * The PLL needs to be enabled with a valid divider
9207                  * configuration, otherwise accessing DSI registers will hang
9208                  * the machine. See BSpec North Display Engine
9209                  * registers/MIPI[BXT]. We can break out here early, since we
9210                  * need the same DSI PLL to be enabled for both DSI ports.
9211                  */
9212                 if (!intel_dsi_pll_is_enabled(dev_priv))
9213                         break;
9214
9215                 /* XXX: this works for video mode only */
9216                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9217                 if (!(tmp & DPI_ENABLE))
9218                         continue;
9219
9220                 tmp = I915_READ(MIPI_CTRL(port));
9221                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9222                         continue;
9223
9224                 pipe_config->cpu_transcoder = cpu_transcoder;
9225                 break;
9226         }
9227
9228         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9229 }
9230
9231 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9232                                        struct intel_crtc_state *pipe_config)
9233 {
9234         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9235         struct intel_shared_dpll *pll;
9236         enum port port;
9237         uint32_t tmp;
9238
9239         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9240
9241         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9242
9243         if (IS_CANNONLAKE(dev_priv))
9244                 cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
9245         else if (IS_GEN9_BC(dev_priv))
9246                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9247         else if (IS_GEN9_LP(dev_priv))
9248                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9249         else
9250                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9251
9252         pll = pipe_config->shared_dpll;
9253         if (pll) {
9254                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9255                                                  &pipe_config->dpll_hw_state));
9256         }
9257
9258         /*
9259          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9260          * DDI E. So just check whether this pipe is wired to DDI E and whether
9261          * the PCH transcoder is on.
9262          */
9263         if (INTEL_GEN(dev_priv) < 9 &&
9264             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9265                 pipe_config->has_pch_encoder = true;
9266
9267                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9268                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9269                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9270
9271                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9272         }
9273 }
9274
9275 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9276                                     struct intel_crtc_state *pipe_config)
9277 {
9278         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9279         enum intel_display_power_domain power_domain;
9280         u64 power_domain_mask;
9281         bool active;
9282
9283         intel_crtc_init_scalers(crtc, pipe_config);
9284
9285         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9286         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9287                 return false;
9288         power_domain_mask = BIT_ULL(power_domain);
9289
9290         pipe_config->shared_dpll = NULL;
9291
9292         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9293
9294         if (IS_GEN9_LP(dev_priv) &&
9295             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9296                 WARN_ON(active);
9297                 active = true;
9298         }
9299
9300         if (!active)
9301                 goto out;
9302
9303         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9304                 haswell_get_ddi_port_state(crtc, pipe_config);
9305                 intel_get_pipe_timings(crtc, pipe_config);
9306         }
9307
9308         intel_get_pipe_src_size(crtc, pipe_config);
9309
9310         pipe_config->gamma_mode =
9311                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9312
9313         if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
9314                 u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
9315                 bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
9316
9317                 if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {
9318                         bool blend_mode_420 = tmp &
9319                                               PIPEMISC_YUV420_MODE_FULL_BLEND;
9320
9321                         pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;
9322                         if (pipe_config->ycbcr420 != clrspace_yuv ||
9323                             pipe_config->ycbcr420 != blend_mode_420)
9324                                 DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);
9325                 } else if (clrspace_yuv) {
9326                         DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");
9327                 }
9328         }
9329
9330         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9331         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9332                 power_domain_mask |= BIT_ULL(power_domain);
9333                 if (INTEL_GEN(dev_priv) >= 9)
9334                         skylake_get_pfit_config(crtc, pipe_config);
9335                 else
9336                         ironlake_get_pfit_config(crtc, pipe_config);
9337         }
9338
9339         if (IS_HASWELL(dev_priv))
9340                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9341                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9342
9343         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9344             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9345                 pipe_config->pixel_multiplier =
9346                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9347         } else {
9348                 pipe_config->pixel_multiplier = 1;
9349         }
9350
9351 out:
9352         for_each_power_domain(power_domain, power_domain_mask)
9353                 intel_display_power_put(dev_priv, power_domain);
9354
9355         return active;
9356 }
9357
9358 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
9359 {
9360         struct drm_i915_private *dev_priv =
9361                 to_i915(plane_state->base.plane->dev);
9362         const struct drm_framebuffer *fb = plane_state->base.fb;
9363         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9364         u32 base;
9365
9366         if (INTEL_INFO(dev_priv)->cursor_needs_physical)
9367                 base = obj->phys_handle->busaddr;
9368         else
9369                 base = intel_plane_ggtt_offset(plane_state);
9370
9371         base += plane_state->main.offset;
9372
9373         /* ILK+ do this automagically */
9374         if (HAS_GMCH_DISPLAY(dev_priv) &&
9375             plane_state->base.rotation & DRM_MODE_ROTATE_180)
9376                 base += (plane_state->base.crtc_h *
9377                          plane_state->base.crtc_w - 1) * fb->format->cpp[0];
9378
9379         return base;
9380 }
9381
9382 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
9383 {
9384         int x = plane_state->base.crtc_x;
9385         int y = plane_state->base.crtc_y;
9386         u32 pos = 0;
9387
9388         if (x < 0) {
9389                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9390                 x = -x;
9391         }
9392         pos |= x << CURSOR_X_SHIFT;
9393
9394         if (y < 0) {
9395                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9396                 y = -y;
9397         }
9398         pos |= y << CURSOR_Y_SHIFT;
9399
9400         return pos;
9401 }
9402
9403 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
9404 {
9405         const struct drm_mode_config *config =
9406                 &plane_state->base.plane->dev->mode_config;
9407         int width = plane_state->base.crtc_w;
9408         int height = plane_state->base.crtc_h;
9409
9410         return width > 0 && width <= config->cursor_width &&
9411                 height > 0 && height <= config->cursor_height;
9412 }
9413
9414 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
9415                               struct intel_plane_state *plane_state)
9416 {
9417         const struct drm_framebuffer *fb = plane_state->base.fb;
9418         int src_x, src_y;
9419         u32 offset;
9420         int ret;
9421
9422         ret = drm_plane_helper_check_state(&plane_state->base,
9423                                            &plane_state->clip,
9424                                            DRM_PLANE_HELPER_NO_SCALING,
9425                                            DRM_PLANE_HELPER_NO_SCALING,
9426                                            true, true);
9427         if (ret)
9428                 return ret;
9429
9430         if (!fb)
9431                 return 0;
9432
9433         if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
9434                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
9435                 return -EINVAL;
9436         }
9437
9438         src_x = plane_state->base.src_x >> 16;
9439         src_y = plane_state->base.src_y >> 16;
9440
9441         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
9442         offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
9443
9444         if (src_x != 0 || src_y != 0) {
9445                 DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
9446                 return -EINVAL;
9447         }
9448
9449         plane_state->main.offset = offset;
9450
9451         return 0;
9452 }
9453
9454 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9455                            const struct intel_plane_state *plane_state)
9456 {
9457         const struct drm_framebuffer *fb = plane_state->base.fb;
9458
9459         return CURSOR_ENABLE |
9460                 CURSOR_GAMMA_ENABLE |
9461                 CURSOR_FORMAT_ARGB |
9462                 CURSOR_STRIDE(fb->pitches[0]);
9463 }
9464
9465 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
9466 {
9467         int width = plane_state->base.crtc_w;
9468
9469         /*
9470          * 845g/865g are only limited by the width of their cursors,
9471          * the height is arbitrary up to the precision of the register.
9472          */
9473         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
9474 }
9475
9476 static int i845_check_cursor(struct intel_plane *plane,
9477                              struct intel_crtc_state *crtc_state,
9478                              struct intel_plane_state *plane_state)
9479 {
9480         const struct drm_framebuffer *fb = plane_state->base.fb;
9481         int ret;
9482
9483         ret = intel_check_cursor(crtc_state, plane_state);
9484         if (ret)
9485                 return ret;
9486
9487         /* if we want to turn off the cursor ignore width and height */
9488         if (!fb)
9489                 return 0;
9490
9491         /* Check for which cursor types we support */
9492         if (!i845_cursor_size_ok(plane_state)) {
9493                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9494                           plane_state->base.crtc_w,
9495                           plane_state->base.crtc_h);
9496                 return -EINVAL;
9497         }
9498
9499         switch (fb->pitches[0]) {
9500         case 256:
9501         case 512:
9502         case 1024:
9503         case 2048:
9504                 break;
9505         default:
9506                 DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
9507                               fb->pitches[0]);
9508                 return -EINVAL;
9509         }
9510
9511         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
9512
9513         return 0;
9514 }
9515
9516 static void i845_update_cursor(struct intel_plane *plane,
9517                                const struct intel_crtc_state *crtc_state,
9518                                const struct intel_plane_state *plane_state)
9519 {
9520         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9521         u32 cntl = 0, base = 0, pos = 0, size = 0;
9522         unsigned long irqflags;
9523
9524         if (plane_state && plane_state->base.visible) {
9525                 unsigned int width = plane_state->base.crtc_w;
9526                 unsigned int height = plane_state->base.crtc_h;
9527
9528                 cntl = plane_state->ctl;
9529                 size = (height << 12) | width;
9530
9531                 base = intel_cursor_base(plane_state);
9532                 pos = intel_cursor_position(plane_state);
9533         }
9534
9535         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9536
9537         /* On these chipsets we can only modify the base/size/stride
9538          * whilst the cursor is disabled.
9539          */
9540         if (plane->cursor.base != base ||
9541             plane->cursor.size != size ||
9542             plane->cursor.cntl != cntl) {
9543                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9544                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9545                 I915_WRITE_FW(CURSIZE, size);
9546                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9547                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9548
9549                 plane->cursor.base = base;
9550                 plane->cursor.size = size;
9551                 plane->cursor.cntl = cntl;
9552         } else {
9553                 I915_WRITE_FW(CURPOS(PIPE_A), pos);
9554         }
9555
9556         POSTING_READ_FW(CURCNTR(PIPE_A));
9557
9558         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9559 }
9560
9561 static void i845_disable_cursor(struct intel_plane *plane,
9562                                 struct intel_crtc *crtc)
9563 {
9564         i845_update_cursor(plane, NULL, NULL);
9565 }
9566
9567 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9568                            const struct intel_plane_state *plane_state)
9569 {
9570         struct drm_i915_private *dev_priv =
9571                 to_i915(plane_state->base.plane->dev);
9572         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9573         u32 cntl;
9574
9575         cntl = MCURSOR_GAMMA_ENABLE;
9576
9577         if (HAS_DDI(dev_priv))
9578                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9579
9580         cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
9581
9582         switch (plane_state->base.crtc_w) {
9583         case 64:
9584                 cntl |= CURSOR_MODE_64_ARGB_AX;
9585                 break;
9586         case 128:
9587                 cntl |= CURSOR_MODE_128_ARGB_AX;
9588                 break;
9589         case 256:
9590                 cntl |= CURSOR_MODE_256_ARGB_AX;
9591                 break;
9592         default:
9593                 MISSING_CASE(plane_state->base.crtc_w);
9594                 return 0;
9595         }
9596
9597         if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
9598                 cntl |= CURSOR_ROTATE_180;
9599
9600         return cntl;
9601 }
9602
9603 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
9604 {
9605         struct drm_i915_private *dev_priv =
9606                 to_i915(plane_state->base.plane->dev);
9607         int width = plane_state->base.crtc_w;
9608         int height = plane_state->base.crtc_h;
9609
9610         if (!intel_cursor_size_ok(plane_state))
9611                 return false;
9612
9613         /* Cursor width is limited to a few power-of-two sizes */
9614         switch (width) {
9615         case 256:
9616         case 128:
9617         case 64:
9618                 break;
9619         default:
9620                 return false;
9621         }
9622
9623         /*
9624          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
9625          * height from 8 lines up to the cursor width, when the
9626          * cursor is not rotated. Everything else requires square
9627          * cursors.
9628          */
9629         if (HAS_CUR_FBC(dev_priv) &&
9630             plane_state->base.rotation & DRM_MODE_ROTATE_0) {
9631                 if (height < 8 || height > width)
9632                         return false;
9633         } else {
9634                 if (height != width)
9635                         return false;
9636         }
9637
9638         return true;
9639 }
9640
9641 static int i9xx_check_cursor(struct intel_plane *plane,
9642                              struct intel_crtc_state *crtc_state,
9643                              struct intel_plane_state *plane_state)
9644 {
9645         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9646         const struct drm_framebuffer *fb = plane_state->base.fb;
9647         enum pipe pipe = plane->pipe;
9648         int ret;
9649
9650         ret = intel_check_cursor(crtc_state, plane_state);
9651         if (ret)
9652                 return ret;
9653
9654         /* if we want to turn off the cursor ignore width and height */
9655         if (!fb)
9656                 return 0;
9657
9658         /* Check for which cursor types we support */
9659         if (!i9xx_cursor_size_ok(plane_state)) {
9660                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
9661                           plane_state->base.crtc_w,
9662                           plane_state->base.crtc_h);
9663                 return -EINVAL;
9664         }
9665
9666         if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
9667                 DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
9668                               fb->pitches[0], plane_state->base.crtc_w);
9669                 return -EINVAL;
9670         }
9671
9672         /*
9673          * There's something wrong with the cursor on CHV pipe C.
9674          * If it straddles the left edge of the screen then
9675          * moving it away from the edge or disabling it often
9676          * results in a pipe underrun, and often that can lead to
9677          * dead pipe (constant underrun reported, and it scans
9678          * out just a solid color). To recover from that, the
9679          * display power well must be turned off and on again.
9680          * Refuse the put the cursor into that compromised position.
9681          */
9682         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
9683             plane_state->base.visible && plane_state->base.crtc_x < 0) {
9684                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
9685                 return -EINVAL;
9686         }
9687
9688         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
9689
9690         return 0;
9691 }
9692
9693 static void i9xx_update_cursor(struct intel_plane *plane,
9694                                const struct intel_crtc_state *crtc_state,
9695                                const struct intel_plane_state *plane_state)
9696 {
9697         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
9698         enum pipe pipe = plane->pipe;
9699         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
9700         unsigned long irqflags;
9701
9702         if (plane_state && plane_state->base.visible) {
9703                 cntl = plane_state->ctl;
9704
9705                 if (plane_state->base.crtc_h != plane_state->base.crtc_w)
9706                         fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
9707
9708                 base = intel_cursor_base(plane_state);
9709                 pos = intel_cursor_position(plane_state);
9710         }
9711
9712         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9713
9714         /*
9715          * On some platforms writing CURCNTR first will also
9716          * cause CURPOS to be armed by the CURBASE write.
9717          * Without the CURCNTR write the CURPOS write would
9718          * arm itself. Thus we always start the full update
9719          * with a CURCNTR write.
9720          *
9721          * On other platforms CURPOS always requires the
9722          * CURBASE write to arm the update. Additonally
9723          * a write to any of the cursor register will cancel
9724          * an already armed cursor update. Thus leaving out
9725          * the CURBASE write after CURPOS could lead to a
9726          * cursor that doesn't appear to move, or even change
9727          * shape. Thus we always write CURBASE.
9728          *
9729          * CURCNTR and CUR_FBC_CTL are always
9730          * armed by the CURBASE write only.
9731          */
9732         if (plane->cursor.base != base ||
9733             plane->cursor.size != fbc_ctl ||
9734             plane->cursor.cntl != cntl) {
9735                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9736                 if (HAS_CUR_FBC(dev_priv))
9737                         I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);
9738                 I915_WRITE_FW(CURPOS(pipe), pos);
9739                 I915_WRITE_FW(CURBASE(pipe), base);
9740
9741                 plane->cursor.base = base;
9742                 plane->cursor.size = fbc_ctl;
9743                 plane->cursor.cntl = cntl;
9744         } else {
9745                 I915_WRITE_FW(CURPOS(pipe), pos);
9746                 I915_WRITE_FW(CURBASE(pipe), base);
9747         }
9748
9749         POSTING_READ_FW(CURBASE(pipe));
9750
9751         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9752 }
9753
9754 static void i9xx_disable_cursor(struct intel_plane *plane,
9755                                 struct intel_crtc *crtc)
9756 {
9757         i9xx_update_cursor(plane, NULL, NULL);
9758 }
9759
9760
9761 /* VESA 640x480x72Hz mode to set on the pipe */
9762 static const struct drm_display_mode load_detect_mode = {
9763         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9764                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9765 };
9766
9767 struct drm_framebuffer *
9768 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9769                          struct drm_mode_fb_cmd2 *mode_cmd)
9770 {
9771         struct intel_framebuffer *intel_fb;
9772         int ret;
9773
9774         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9775         if (!intel_fb)
9776                 return ERR_PTR(-ENOMEM);
9777
9778         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9779         if (ret)
9780                 goto err;
9781
9782         return &intel_fb->base;
9783
9784 err:
9785         kfree(intel_fb);
9786         return ERR_PTR(ret);
9787 }
9788
9789 static u32
9790 intel_framebuffer_pitch_for_width(int width, int bpp)
9791 {
9792         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9793         return ALIGN(pitch, 64);
9794 }
9795
9796 static u32
9797 intel_framebuffer_size_for_mode(const struct drm_display_mode *mode, int bpp)
9798 {
9799         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9800         return PAGE_ALIGN(pitch * mode->vdisplay);
9801 }
9802
9803 static struct drm_framebuffer *
9804 intel_framebuffer_create_for_mode(struct drm_device *dev,
9805                                   const struct drm_display_mode *mode,
9806                                   int depth, int bpp)
9807 {
9808         struct drm_framebuffer *fb;
9809         struct drm_i915_gem_object *obj;
9810         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9811
9812         obj = i915_gem_object_create(to_i915(dev),
9813                                     intel_framebuffer_size_for_mode(mode, bpp));
9814         if (IS_ERR(obj))
9815                 return ERR_CAST(obj);
9816
9817         mode_cmd.width = mode->hdisplay;
9818         mode_cmd.height = mode->vdisplay;
9819         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9820                                                                 bpp);
9821         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9822
9823         fb = intel_framebuffer_create(obj, &mode_cmd);
9824         if (IS_ERR(fb))
9825                 i915_gem_object_put(obj);
9826
9827         return fb;
9828 }
9829
9830 static struct drm_framebuffer *
9831 mode_fits_in_fbdev(struct drm_device *dev,
9832                    const struct drm_display_mode *mode)
9833 {
9834 #ifdef CONFIG_DRM_FBDEV_EMULATION
9835         struct drm_i915_private *dev_priv = to_i915(dev);
9836         struct drm_i915_gem_object *obj;
9837         struct drm_framebuffer *fb;
9838
9839         if (!dev_priv->fbdev)
9840                 return NULL;
9841
9842         if (!dev_priv->fbdev->fb)
9843                 return NULL;
9844
9845         obj = dev_priv->fbdev->fb->obj;
9846         BUG_ON(!obj);
9847
9848         fb = &dev_priv->fbdev->fb->base;
9849         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9850                                                                fb->format->cpp[0] * 8))
9851                 return NULL;
9852
9853         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9854                 return NULL;
9855
9856         drm_framebuffer_reference(fb);
9857         return fb;
9858 #else
9859         return NULL;
9860 #endif
9861 }
9862
9863 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9864                                            struct drm_crtc *crtc,
9865                                            const struct drm_display_mode *mode,
9866                                            struct drm_framebuffer *fb,
9867                                            int x, int y)
9868 {
9869         struct drm_plane_state *plane_state;
9870         int hdisplay, vdisplay;
9871         int ret;
9872
9873         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9874         if (IS_ERR(plane_state))
9875                 return PTR_ERR(plane_state);
9876
9877         if (mode)
9878                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9879         else
9880                 hdisplay = vdisplay = 0;
9881
9882         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9883         if (ret)
9884                 return ret;
9885         drm_atomic_set_fb_for_plane(plane_state, fb);
9886         plane_state->crtc_x = 0;
9887         plane_state->crtc_y = 0;
9888         plane_state->crtc_w = hdisplay;
9889         plane_state->crtc_h = vdisplay;
9890         plane_state->src_x = x << 16;
9891         plane_state->src_y = y << 16;
9892         plane_state->src_w = hdisplay << 16;
9893         plane_state->src_h = vdisplay << 16;
9894
9895         return 0;
9896 }
9897
9898 int intel_get_load_detect_pipe(struct drm_connector *connector,
9899                                const struct drm_display_mode *mode,
9900                                struct intel_load_detect_pipe *old,
9901                                struct drm_modeset_acquire_ctx *ctx)
9902 {
9903         struct intel_crtc *intel_crtc;
9904         struct intel_encoder *intel_encoder =
9905                 intel_attached_encoder(connector);
9906         struct drm_crtc *possible_crtc;
9907         struct drm_encoder *encoder = &intel_encoder->base;
9908         struct drm_crtc *crtc = NULL;
9909         struct drm_device *dev = encoder->dev;
9910         struct drm_i915_private *dev_priv = to_i915(dev);
9911         struct drm_framebuffer *fb;
9912         struct drm_mode_config *config = &dev->mode_config;
9913         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9914         struct drm_connector_state *connector_state;
9915         struct intel_crtc_state *crtc_state;
9916         int ret, i = -1;
9917
9918         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9919                       connector->base.id, connector->name,
9920                       encoder->base.id, encoder->name);
9921
9922         old->restore_state = NULL;
9923
9924         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
9925
9926         /*
9927          * Algorithm gets a little messy:
9928          *
9929          *   - if the connector already has an assigned crtc, use it (but make
9930          *     sure it's on first)
9931          *
9932          *   - try to find the first unused crtc that can drive this connector,
9933          *     and use that if we find one
9934          */
9935
9936         /* See if we already have a CRTC for this connector */
9937         if (connector->state->crtc) {
9938                 crtc = connector->state->crtc;
9939
9940                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9941                 if (ret)
9942                         goto fail;
9943
9944                 /* Make sure the crtc and connector are running */
9945                 goto found;
9946         }
9947
9948         /* Find an unused one (if possible) */
9949         for_each_crtc(dev, possible_crtc) {
9950                 i++;
9951                 if (!(encoder->possible_crtcs & (1 << i)))
9952                         continue;
9953
9954                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9955                 if (ret)
9956                         goto fail;
9957
9958                 if (possible_crtc->state->enable) {
9959                         drm_modeset_unlock(&possible_crtc->mutex);
9960                         continue;
9961                 }
9962
9963                 crtc = possible_crtc;
9964                 break;
9965         }
9966
9967         /*
9968          * If we didn't find an unused CRTC, don't use any.
9969          */
9970         if (!crtc) {
9971                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9972                 ret = -ENODEV;
9973                 goto fail;
9974         }
9975
9976 found:
9977         intel_crtc = to_intel_crtc(crtc);
9978
9979         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9980         if (ret)
9981                 goto fail;
9982
9983         state = drm_atomic_state_alloc(dev);
9984         restore_state = drm_atomic_state_alloc(dev);
9985         if (!state || !restore_state) {
9986                 ret = -ENOMEM;
9987                 goto fail;
9988         }
9989
9990         state->acquire_ctx = ctx;
9991         restore_state->acquire_ctx = ctx;
9992
9993         connector_state = drm_atomic_get_connector_state(state, connector);
9994         if (IS_ERR(connector_state)) {
9995                 ret = PTR_ERR(connector_state);
9996                 goto fail;
9997         }
9998
9999         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10000         if (ret)
10001                 goto fail;
10002
10003         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10004         if (IS_ERR(crtc_state)) {
10005                 ret = PTR_ERR(crtc_state);
10006                 goto fail;
10007         }
10008
10009         crtc_state->base.active = crtc_state->base.enable = true;
10010
10011         if (!mode)
10012                 mode = &load_detect_mode;
10013
10014         /* We need a framebuffer large enough to accommodate all accesses
10015          * that the plane may generate whilst we perform load detection.
10016          * We can not rely on the fbcon either being present (we get called
10017          * during its initialisation to detect all boot displays, or it may
10018          * not even exist) or that it is large enough to satisfy the
10019          * requested mode.
10020          */
10021         fb = mode_fits_in_fbdev(dev, mode);
10022         if (fb == NULL) {
10023                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10024                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10025         } else
10026                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10027         if (IS_ERR(fb)) {
10028                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10029                 ret = PTR_ERR(fb);
10030                 goto fail;
10031         }
10032
10033         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10034         if (ret)
10035                 goto fail;
10036
10037         drm_framebuffer_unreference(fb);
10038
10039         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10040         if (ret)
10041                 goto fail;
10042
10043         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10044         if (!ret)
10045                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10046         if (!ret)
10047                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10048         if (ret) {
10049                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10050                 goto fail;
10051         }
10052
10053         ret = drm_atomic_commit(state);
10054         if (ret) {
10055                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10056                 goto fail;
10057         }
10058
10059         old->restore_state = restore_state;
10060         drm_atomic_state_put(state);
10061
10062         /* let the connector get through one full cycle before testing */
10063         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
10064         return true;
10065
10066 fail:
10067         if (state) {
10068                 drm_atomic_state_put(state);
10069                 state = NULL;
10070         }
10071         if (restore_state) {
10072                 drm_atomic_state_put(restore_state);
10073                 restore_state = NULL;
10074         }
10075
10076         if (ret == -EDEADLK)
10077                 return ret;
10078
10079         return false;
10080 }
10081
10082 void intel_release_load_detect_pipe(struct drm_connector *connector,
10083                                     struct intel_load_detect_pipe *old,
10084                                     struct drm_modeset_acquire_ctx *ctx)
10085 {
10086         struct intel_encoder *intel_encoder =
10087                 intel_attached_encoder(connector);
10088         struct drm_encoder *encoder = &intel_encoder->base;
10089         struct drm_atomic_state *state = old->restore_state;
10090         int ret;
10091
10092         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10093                       connector->base.id, connector->name,
10094                       encoder->base.id, encoder->name);
10095
10096         if (!state)
10097                 return;
10098
10099         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
10100         if (ret)
10101                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10102         drm_atomic_state_put(state);
10103 }
10104
10105 static int i9xx_pll_refclk(struct drm_device *dev,
10106                            const struct intel_crtc_state *pipe_config)
10107 {
10108         struct drm_i915_private *dev_priv = to_i915(dev);
10109         u32 dpll = pipe_config->dpll_hw_state.dpll;
10110
10111         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10112                 return dev_priv->vbt.lvds_ssc_freq;
10113         else if (HAS_PCH_SPLIT(dev_priv))
10114                 return 120000;
10115         else if (!IS_GEN2(dev_priv))
10116                 return 96000;
10117         else
10118                 return 48000;
10119 }
10120
10121 /* Returns the clock of the currently programmed mode of the given pipe. */
10122 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10123                                 struct intel_crtc_state *pipe_config)
10124 {
10125         struct drm_device *dev = crtc->base.dev;
10126         struct drm_i915_private *dev_priv = to_i915(dev);
10127         int pipe = pipe_config->cpu_transcoder;
10128         u32 dpll = pipe_config->dpll_hw_state.dpll;
10129         u32 fp;
10130         struct dpll clock;
10131         int port_clock;
10132         int refclk = i9xx_pll_refclk(dev, pipe_config);
10133
10134         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10135                 fp = pipe_config->dpll_hw_state.fp0;
10136         else
10137                 fp = pipe_config->dpll_hw_state.fp1;
10138
10139         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10140         if (IS_PINEVIEW(dev_priv)) {
10141                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10142                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10143         } else {
10144                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10145                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10146         }
10147
10148         if (!IS_GEN2(dev_priv)) {
10149                 if (IS_PINEVIEW(dev_priv))
10150                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10151                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10152                 else
10153                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10154                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10155
10156                 switch (dpll & DPLL_MODE_MASK) {
10157                 case DPLLB_MODE_DAC_SERIAL:
10158                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10159                                 5 : 10;
10160                         break;
10161                 case DPLLB_MODE_LVDS:
10162                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10163                                 7 : 14;
10164                         break;
10165                 default:
10166                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10167                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10168                         return;
10169                 }
10170
10171                 if (IS_PINEVIEW(dev_priv))
10172                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10173                 else
10174                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10175         } else {
10176                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
10177                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10178
10179                 if (is_lvds) {
10180                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10181                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10182
10183                         if (lvds & LVDS_CLKB_POWER_UP)
10184                                 clock.p2 = 7;
10185                         else
10186                                 clock.p2 = 14;
10187                 } else {
10188                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10189                                 clock.p1 = 2;
10190                         else {
10191                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10192                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10193                         }
10194                         if (dpll & PLL_P2_DIVIDE_BY_4)
10195                                 clock.p2 = 4;
10196                         else
10197                                 clock.p2 = 2;
10198                 }
10199
10200                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10201         }
10202
10203         /*
10204          * This value includes pixel_multiplier. We will use
10205          * port_clock to compute adjusted_mode.crtc_clock in the
10206          * encoder's get_config() function.
10207          */
10208         pipe_config->port_clock = port_clock;
10209 }
10210
10211 int intel_dotclock_calculate(int link_freq,
10212                              const struct intel_link_m_n *m_n)
10213 {
10214         /*
10215          * The calculation for the data clock is:
10216          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10217          * But we want to avoid losing precison if possible, so:
10218          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10219          *
10220          * and the link clock is simpler:
10221          * link_clock = (m * link_clock) / n
10222          */
10223
10224         if (!m_n->link_n)
10225                 return 0;
10226
10227         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10228 }
10229
10230 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10231                                    struct intel_crtc_state *pipe_config)
10232 {
10233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10234
10235         /* read out port_clock from the DPLL */
10236         i9xx_crtc_clock_get(crtc, pipe_config);
10237
10238         /*
10239          * In case there is an active pipe without active ports,
10240          * we may need some idea for the dotclock anyway.
10241          * Calculate one based on the FDI configuration.
10242          */
10243         pipe_config->base.adjusted_mode.crtc_clock =
10244                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10245                                          &pipe_config->fdi_m_n);
10246 }
10247
10248 /** Returns the currently programmed mode of the given pipe. */
10249 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10250                                              struct drm_crtc *crtc)
10251 {
10252         struct drm_i915_private *dev_priv = to_i915(dev);
10253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10254         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10255         struct drm_display_mode *mode;
10256         struct intel_crtc_state *pipe_config;
10257         int htot = I915_READ(HTOTAL(cpu_transcoder));
10258         int hsync = I915_READ(HSYNC(cpu_transcoder));
10259         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10260         int vsync = I915_READ(VSYNC(cpu_transcoder));
10261         enum pipe pipe = intel_crtc->pipe;
10262
10263         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10264         if (!mode)
10265                 return NULL;
10266
10267         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10268         if (!pipe_config) {
10269                 kfree(mode);
10270                 return NULL;
10271         }
10272
10273         /*
10274          * Construct a pipe_config sufficient for getting the clock info
10275          * back out of crtc_clock_get.
10276          *
10277          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10278          * to use a real value here instead.
10279          */
10280         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10281         pipe_config->pixel_multiplier = 1;
10282         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10283         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10284         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10285         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10286
10287         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10288         mode->hdisplay = (htot & 0xffff) + 1;
10289         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10290         mode->hsync_start = (hsync & 0xffff) + 1;
10291         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10292         mode->vdisplay = (vtot & 0xffff) + 1;
10293         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10294         mode->vsync_start = (vsync & 0xffff) + 1;
10295         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10296
10297         drm_mode_set_name(mode);
10298
10299         kfree(pipe_config);
10300
10301         return mode;
10302 }
10303
10304 static void intel_crtc_destroy(struct drm_crtc *crtc)
10305 {
10306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10307
10308         drm_crtc_cleanup(crtc);
10309         kfree(intel_crtc);
10310 }
10311
10312 /**
10313  * intel_wm_need_update - Check whether watermarks need updating
10314  * @plane: drm plane
10315  * @state: new plane state
10316  *
10317  * Check current plane state versus the new one to determine whether
10318  * watermarks need to be recalculated.
10319  *
10320  * Returns true or false.
10321  */
10322 static bool intel_wm_need_update(struct drm_plane *plane,
10323                                  struct drm_plane_state *state)
10324 {
10325         struct intel_plane_state *new = to_intel_plane_state(state);
10326         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10327
10328         /* Update watermarks on tiling or size changes. */
10329         if (new->base.visible != cur->base.visible)
10330                 return true;
10331
10332         if (!cur->base.fb || !new->base.fb)
10333                 return false;
10334
10335         if (cur->base.fb->modifier != new->base.fb->modifier ||
10336             cur->base.rotation != new->base.rotation ||
10337             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10338             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10339             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10340             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10341                 return true;
10342
10343         return false;
10344 }
10345
10346 static bool needs_scaling(const struct intel_plane_state *state)
10347 {
10348         int src_w = drm_rect_width(&state->base.src) >> 16;
10349         int src_h = drm_rect_height(&state->base.src) >> 16;
10350         int dst_w = drm_rect_width(&state->base.dst);
10351         int dst_h = drm_rect_height(&state->base.dst);
10352
10353         return (src_w != dst_w || src_h != dst_h);
10354 }
10355
10356 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
10357                                     struct drm_crtc_state *crtc_state,
10358                                     const struct intel_plane_state *old_plane_state,
10359                                     struct drm_plane_state *plane_state)
10360 {
10361         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10362         struct drm_crtc *crtc = crtc_state->crtc;
10363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10364         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10365         struct drm_device *dev = crtc->dev;
10366         struct drm_i915_private *dev_priv = to_i915(dev);
10367         bool mode_changed = needs_modeset(crtc_state);
10368         bool was_crtc_enabled = old_crtc_state->base.active;
10369         bool is_crtc_enabled = crtc_state->active;
10370         bool turn_off, turn_on, visible, was_visible;
10371         struct drm_framebuffer *fb = plane_state->fb;
10372         int ret;
10373
10374         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10375                 ret = skl_update_scaler_plane(
10376                         to_intel_crtc_state(crtc_state),
10377                         to_intel_plane_state(plane_state));
10378                 if (ret)
10379                         return ret;
10380         }
10381
10382         was_visible = old_plane_state->base.visible;
10383         visible = plane_state->visible;
10384
10385         if (!was_crtc_enabled && WARN_ON(was_visible))
10386                 was_visible = false;
10387
10388         /*
10389          * Visibility is calculated as if the crtc was on, but
10390          * after scaler setup everything depends on it being off
10391          * when the crtc isn't active.
10392          *
10393          * FIXME this is wrong for watermarks. Watermarks should also
10394          * be computed as if the pipe would be active. Perhaps move
10395          * per-plane wm computation to the .check_plane() hook, and
10396          * only combine the results from all planes in the current place?
10397          */
10398         if (!is_crtc_enabled) {
10399                 plane_state->visible = visible = false;
10400                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10401         }
10402
10403         if (!was_visible && !visible)
10404                 return 0;
10405
10406         if (fb != old_plane_state->base.fb)
10407                 pipe_config->fb_changed = true;
10408
10409         turn_off = was_visible && (!visible || mode_changed);
10410         turn_on = visible && (!was_visible || mode_changed);
10411
10412         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10413                          intel_crtc->base.base.id, intel_crtc->base.name,
10414                          plane->base.base.id, plane->base.name,
10415                          fb ? fb->base.id : -1);
10416
10417         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10418                          plane->base.base.id, plane->base.name,
10419                          was_visible, visible,
10420                          turn_off, turn_on, mode_changed);
10421
10422         if (turn_on) {
10423                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10424                         pipe_config->update_wm_pre = true;
10425
10426                 /* must disable cxsr around plane enable/disable */
10427                 if (plane->id != PLANE_CURSOR)
10428                         pipe_config->disable_cxsr = true;
10429         } else if (turn_off) {
10430                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10431                         pipe_config->update_wm_post = true;
10432
10433                 /* must disable cxsr around plane enable/disable */
10434                 if (plane->id != PLANE_CURSOR)
10435                         pipe_config->disable_cxsr = true;
10436         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10437                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
10438                         /* FIXME bollocks */
10439                         pipe_config->update_wm_pre = true;
10440                         pipe_config->update_wm_post = true;
10441                 }
10442         }
10443
10444         if (visible || was_visible)
10445                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10446
10447         /*
10448          * WaCxSRDisabledForSpriteScaling:ivb
10449          *
10450          * cstate->update_wm was already set above, so this flag will
10451          * take effect when we commit and program watermarks.
10452          */
10453         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10454             needs_scaling(to_intel_plane_state(plane_state)) &&
10455             !needs_scaling(old_plane_state))
10456                 pipe_config->disable_lp_wm = true;
10457
10458         return 0;
10459 }
10460
10461 static bool encoders_cloneable(const struct intel_encoder *a,
10462                                const struct intel_encoder *b)
10463 {
10464         /* masks could be asymmetric, so check both ways */
10465         return a == b || (a->cloneable & (1 << b->type) &&
10466                           b->cloneable & (1 << a->type));
10467 }
10468
10469 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10470                                          struct intel_crtc *crtc,
10471                                          struct intel_encoder *encoder)
10472 {
10473         struct intel_encoder *source_encoder;
10474         struct drm_connector *connector;
10475         struct drm_connector_state *connector_state;
10476         int i;
10477
10478         for_each_new_connector_in_state(state, connector, connector_state, i) {
10479                 if (connector_state->crtc != &crtc->base)
10480                         continue;
10481
10482                 source_encoder =
10483                         to_intel_encoder(connector_state->best_encoder);
10484                 if (!encoders_cloneable(encoder, source_encoder))
10485                         return false;
10486         }
10487
10488         return true;
10489 }
10490
10491 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10492                                    struct drm_crtc_state *crtc_state)
10493 {
10494         struct drm_device *dev = crtc->dev;
10495         struct drm_i915_private *dev_priv = to_i915(dev);
10496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10497         struct intel_crtc_state *pipe_config =
10498                 to_intel_crtc_state(crtc_state);
10499         struct drm_atomic_state *state = crtc_state->state;
10500         int ret;
10501         bool mode_changed = needs_modeset(crtc_state);
10502
10503         if (mode_changed && !crtc_state->active)
10504                 pipe_config->update_wm_post = true;
10505
10506         if (mode_changed && crtc_state->enable &&
10507             dev_priv->display.crtc_compute_clock &&
10508             !WARN_ON(pipe_config->shared_dpll)) {
10509                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10510                                                            pipe_config);
10511                 if (ret)
10512                         return ret;
10513         }
10514
10515         if (crtc_state->color_mgmt_changed) {
10516                 ret = intel_color_check(crtc, crtc_state);
10517                 if (ret)
10518                         return ret;
10519
10520                 /*
10521                  * Changing color management on Intel hardware is
10522                  * handled as part of planes update.
10523                  */
10524                 crtc_state->planes_changed = true;
10525         }
10526
10527         ret = 0;
10528         if (dev_priv->display.compute_pipe_wm) {
10529                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10530                 if (ret) {
10531                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10532                         return ret;
10533                 }
10534         }
10535
10536         if (dev_priv->display.compute_intermediate_wm &&
10537             !to_intel_atomic_state(state)->skip_intermediate_wm) {
10538                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10539                         return 0;
10540
10541                 /*
10542                  * Calculate 'intermediate' watermarks that satisfy both the
10543                  * old state and the new state.  We can program these
10544                  * immediately.
10545                  */
10546                 ret = dev_priv->display.compute_intermediate_wm(dev,
10547                                                                 intel_crtc,
10548                                                                 pipe_config);
10549                 if (ret) {
10550                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
10551                         return ret;
10552                 }
10553         } else if (dev_priv->display.compute_intermediate_wm) {
10554                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10555                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
10556         }
10557
10558         if (INTEL_GEN(dev_priv) >= 9) {
10559                 if (mode_changed)
10560                         ret = skl_update_scaler_crtc(pipe_config);
10561
10562                 if (!ret)
10563                         ret = skl_check_pipe_max_pixel_rate(intel_crtc,
10564                                                             pipe_config);
10565                 if (!ret)
10566                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
10567                                                          pipe_config);
10568         }
10569
10570         return ret;
10571 }
10572
10573 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
10574         .atomic_begin = intel_begin_crtc_commit,
10575         .atomic_flush = intel_finish_crtc_commit,
10576         .atomic_check = intel_crtc_atomic_check,
10577 };
10578
10579 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10580 {
10581         struct intel_connector *connector;
10582         struct drm_connector_list_iter conn_iter;
10583
10584         drm_connector_list_iter_begin(dev, &conn_iter);
10585         for_each_intel_connector_iter(connector, &conn_iter) {
10586                 if (connector->base.state->crtc)
10587                         drm_connector_unreference(&connector->base);
10588
10589                 if (connector->base.encoder) {
10590                         connector->base.state->best_encoder =
10591                                 connector->base.encoder;
10592                         connector->base.state->crtc =
10593                                 connector->base.encoder->crtc;
10594
10595                         drm_connector_reference(&connector->base);
10596                 } else {
10597                         connector->base.state->best_encoder = NULL;
10598                         connector->base.state->crtc = NULL;
10599                 }
10600         }
10601         drm_connector_list_iter_end(&conn_iter);
10602 }
10603
10604 static void
10605 connected_sink_compute_bpp(struct intel_connector *connector,
10606                            struct intel_crtc_state *pipe_config)
10607 {
10608         const struct drm_display_info *info = &connector->base.display_info;
10609         int bpp = pipe_config->pipe_bpp;
10610
10611         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10612                       connector->base.base.id,
10613                       connector->base.name);
10614
10615         /* Don't use an invalid EDID bpc value */
10616         if (info->bpc != 0 && info->bpc * 3 < bpp) {
10617                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10618                               bpp, info->bpc * 3);
10619                 pipe_config->pipe_bpp = info->bpc * 3;
10620         }
10621
10622         /* Clamp bpp to 8 on screens without EDID 1.4 */
10623         if (info->bpc == 0 && bpp > 24) {
10624                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10625                               bpp);
10626                 pipe_config->pipe_bpp = 24;
10627         }
10628 }
10629
10630 static int
10631 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10632                           struct intel_crtc_state *pipe_config)
10633 {
10634         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10635         struct drm_atomic_state *state;
10636         struct drm_connector *connector;
10637         struct drm_connector_state *connector_state;
10638         int bpp, i;
10639
10640         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
10641             IS_CHERRYVIEW(dev_priv)))
10642                 bpp = 10*3;
10643         else if (INTEL_GEN(dev_priv) >= 5)
10644                 bpp = 12*3;
10645         else
10646                 bpp = 8*3;
10647
10648
10649         pipe_config->pipe_bpp = bpp;
10650
10651         state = pipe_config->base.state;
10652
10653         /* Clamp display bpp to EDID value */
10654         for_each_new_connector_in_state(state, connector, connector_state, i) {
10655                 if (connector_state->crtc != &crtc->base)
10656                         continue;
10657
10658                 connected_sink_compute_bpp(to_intel_connector(connector),
10659                                            pipe_config);
10660         }
10661
10662         return bpp;
10663 }
10664
10665 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10666 {
10667         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10668                         "type: 0x%x flags: 0x%x\n",
10669                 mode->crtc_clock,
10670                 mode->crtc_hdisplay, mode->crtc_hsync_start,
10671                 mode->crtc_hsync_end, mode->crtc_htotal,
10672                 mode->crtc_vdisplay, mode->crtc_vsync_start,
10673                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10674 }
10675
10676 static inline void
10677 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
10678                       unsigned int lane_count, struct intel_link_m_n *m_n)
10679 {
10680         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10681                       id, lane_count,
10682                       m_n->gmch_m, m_n->gmch_n,
10683                       m_n->link_m, m_n->link_n, m_n->tu);
10684 }
10685
10686 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10687                                    struct intel_crtc_state *pipe_config,
10688                                    const char *context)
10689 {
10690         struct drm_device *dev = crtc->base.dev;
10691         struct drm_i915_private *dev_priv = to_i915(dev);
10692         struct drm_plane *plane;
10693         struct intel_plane *intel_plane;
10694         struct intel_plane_state *state;
10695         struct drm_framebuffer *fb;
10696
10697         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
10698                       crtc->base.base.id, crtc->base.name, context);
10699
10700         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
10701                       transcoder_name(pipe_config->cpu_transcoder),
10702                       pipe_config->pipe_bpp, pipe_config->dither);
10703
10704         if (pipe_config->has_pch_encoder)
10705                 intel_dump_m_n_config(pipe_config, "fdi",
10706                                       pipe_config->fdi_lanes,
10707                                       &pipe_config->fdi_m_n);
10708
10709         if (pipe_config->ycbcr420)
10710                 DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");
10711
10712         if (intel_crtc_has_dp_encoder(pipe_config)) {
10713                 intel_dump_m_n_config(pipe_config, "dp m_n",
10714                                 pipe_config->lane_count, &pipe_config->dp_m_n);
10715                 if (pipe_config->has_drrs)
10716                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
10717                                               pipe_config->lane_count,
10718                                               &pipe_config->dp_m2_n2);
10719         }
10720
10721         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10722                       pipe_config->has_audio, pipe_config->has_infoframe);
10723
10724         DRM_DEBUG_KMS("requested mode:\n");
10725         drm_mode_debug_printmodeline(&pipe_config->base.mode);
10726         DRM_DEBUG_KMS("adjusted mode:\n");
10727         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10728         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10729         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
10730                       pipe_config->port_clock,
10731                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
10732                       pipe_config->pixel_rate);
10733
10734         if (INTEL_GEN(dev_priv) >= 9)
10735                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
10736                               crtc->num_scalers,
10737                               pipe_config->scaler_state.scaler_users,
10738                               pipe_config->scaler_state.scaler_id);
10739
10740         if (HAS_GMCH_DISPLAY(dev_priv))
10741                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10742                               pipe_config->gmch_pfit.control,
10743                               pipe_config->gmch_pfit.pgm_ratios,
10744                               pipe_config->gmch_pfit.lvds_border_bits);
10745         else
10746                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10747                               pipe_config->pch_pfit.pos,
10748                               pipe_config->pch_pfit.size,
10749                               enableddisabled(pipe_config->pch_pfit.enabled));
10750
10751         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
10752                       pipe_config->ips_enabled, pipe_config->double_wide);
10753
10754         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
10755
10756         DRM_DEBUG_KMS("planes on this crtc\n");
10757         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10758                 struct drm_format_name_buf format_name;
10759                 intel_plane = to_intel_plane(plane);
10760                 if (intel_plane->pipe != crtc->pipe)
10761                         continue;
10762
10763                 state = to_intel_plane_state(plane->state);
10764                 fb = state->base.fb;
10765                 if (!fb) {
10766                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
10767                                       plane->base.id, plane->name, state->scaler_id);
10768                         continue;
10769                 }
10770
10771                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
10772                               plane->base.id, plane->name,
10773                               fb->base.id, fb->width, fb->height,
10774                               drm_get_format_name(fb->format->format, &format_name));
10775                 if (INTEL_GEN(dev_priv) >= 9)
10776                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
10777                                       state->scaler_id,
10778                                       state->base.src.x1 >> 16,
10779                                       state->base.src.y1 >> 16,
10780                                       drm_rect_width(&state->base.src) >> 16,
10781                                       drm_rect_height(&state->base.src) >> 16,
10782                                       state->base.dst.x1, state->base.dst.y1,
10783                                       drm_rect_width(&state->base.dst),
10784                                       drm_rect_height(&state->base.dst));
10785         }
10786 }
10787
10788 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
10789 {
10790         struct drm_device *dev = state->dev;
10791         struct drm_connector *connector;
10792         struct drm_connector_list_iter conn_iter;
10793         unsigned int used_ports = 0;
10794         unsigned int used_mst_ports = 0;
10795
10796         /*
10797          * Walk the connector list instead of the encoder
10798          * list to detect the problem on ddi platforms
10799          * where there's just one encoder per digital port.
10800          */
10801         drm_connector_list_iter_begin(dev, &conn_iter);
10802         drm_for_each_connector_iter(connector, &conn_iter) {
10803                 struct drm_connector_state *connector_state;
10804                 struct intel_encoder *encoder;
10805
10806                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
10807                 if (!connector_state)
10808                         connector_state = connector->state;
10809
10810                 if (!connector_state->best_encoder)
10811                         continue;
10812
10813                 encoder = to_intel_encoder(connector_state->best_encoder);
10814
10815                 WARN_ON(!connector_state->crtc);
10816
10817                 switch (encoder->type) {
10818                         unsigned int port_mask;
10819                 case INTEL_OUTPUT_UNKNOWN:
10820                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
10821                                 break;
10822                 case INTEL_OUTPUT_DP:
10823                 case INTEL_OUTPUT_HDMI:
10824                 case INTEL_OUTPUT_EDP:
10825                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10826
10827                         /* the same port mustn't appear more than once */
10828                         if (used_ports & port_mask)
10829                                 return false;
10830
10831                         used_ports |= port_mask;
10832                         break;
10833                 case INTEL_OUTPUT_DP_MST:
10834                         used_mst_ports |=
10835                                 1 << enc_to_mst(&encoder->base)->primary->port;
10836                         break;
10837                 default:
10838                         break;
10839                 }
10840         }
10841         drm_connector_list_iter_end(&conn_iter);
10842
10843         /* can't mix MST and SST/HDMI on the same port */
10844         if (used_ports & used_mst_ports)
10845                 return false;
10846
10847         return true;
10848 }
10849
10850 static void
10851 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10852 {
10853         struct drm_i915_private *dev_priv =
10854                 to_i915(crtc_state->base.crtc->dev);
10855         struct intel_crtc_scaler_state scaler_state;
10856         struct intel_dpll_hw_state dpll_hw_state;
10857         struct intel_shared_dpll *shared_dpll;
10858         struct intel_crtc_wm_state wm_state;
10859         bool force_thru, ips_force_disable;
10860
10861         /* FIXME: before the switch to atomic started, a new pipe_config was
10862          * kzalloc'd. Code that depends on any field being zero should be
10863          * fixed, so that the crtc_state can be safely duplicated. For now,
10864          * only fields that are know to not cause problems are preserved. */
10865
10866         scaler_state = crtc_state->scaler_state;
10867         shared_dpll = crtc_state->shared_dpll;
10868         dpll_hw_state = crtc_state->dpll_hw_state;
10869         force_thru = crtc_state->pch_pfit.force_thru;
10870         ips_force_disable = crtc_state->ips_force_disable;
10871         if (IS_G4X(dev_priv) ||
10872             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10873                 wm_state = crtc_state->wm;
10874
10875         /* Keep base drm_crtc_state intact, only clear our extended struct */
10876         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
10877         memset(&crtc_state->base + 1, 0,
10878                sizeof(*crtc_state) - sizeof(crtc_state->base));
10879
10880         crtc_state->scaler_state = scaler_state;
10881         crtc_state->shared_dpll = shared_dpll;
10882         crtc_state->dpll_hw_state = dpll_hw_state;
10883         crtc_state->pch_pfit.force_thru = force_thru;
10884         crtc_state->ips_force_disable = ips_force_disable;
10885         if (IS_G4X(dev_priv) ||
10886             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10887                 crtc_state->wm = wm_state;
10888 }
10889
10890 static int
10891 intel_modeset_pipe_config(struct drm_crtc *crtc,
10892                           struct intel_crtc_state *pipe_config)
10893 {
10894         struct drm_atomic_state *state = pipe_config->base.state;
10895         struct intel_encoder *encoder;
10896         struct drm_connector *connector;
10897         struct drm_connector_state *connector_state;
10898         int base_bpp, ret = -EINVAL;
10899         int i;
10900         bool retry = true;
10901
10902         clear_intel_crtc_state(pipe_config);
10903
10904         pipe_config->cpu_transcoder =
10905                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10906
10907         /*
10908          * Sanitize sync polarity flags based on requested ones. If neither
10909          * positive or negative polarity is requested, treat this as meaning
10910          * negative polarity.
10911          */
10912         if (!(pipe_config->base.adjusted_mode.flags &
10913               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10914                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10915
10916         if (!(pipe_config->base.adjusted_mode.flags &
10917               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10918                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10919
10920         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10921                                              pipe_config);
10922         if (base_bpp < 0)
10923                 goto fail;
10924
10925         /*
10926          * Determine the real pipe dimensions. Note that stereo modes can
10927          * increase the actual pipe size due to the frame doubling and
10928          * insertion of additional space for blanks between the frame. This
10929          * is stored in the crtc timings. We use the requested mode to do this
10930          * computation to clearly distinguish it from the adjusted mode, which
10931          * can be changed by the connectors in the below retry loop.
10932          */
10933         drm_mode_get_hv_timing(&pipe_config->base.mode,
10934                                &pipe_config->pipe_src_w,
10935                                &pipe_config->pipe_src_h);
10936
10937         for_each_new_connector_in_state(state, connector, connector_state, i) {
10938                 if (connector_state->crtc != crtc)
10939                         continue;
10940
10941                 encoder = to_intel_encoder(connector_state->best_encoder);
10942
10943                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
10944                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10945                         goto fail;
10946                 }
10947
10948                 /*
10949                  * Determine output_types before calling the .compute_config()
10950                  * hooks so that the hooks can use this information safely.
10951                  */
10952                 pipe_config->output_types |= 1 << encoder->type;
10953         }
10954
10955 encoder_retry:
10956         /* Ensure the port clock defaults are reset when retrying. */
10957         pipe_config->port_clock = 0;
10958         pipe_config->pixel_multiplier = 1;
10959
10960         /* Fill in default crtc timings, allow encoders to overwrite them. */
10961         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10962                               CRTC_STEREO_DOUBLE);
10963
10964         /* Pass our mode to the connectors and the CRTC to give them a chance to
10965          * adjust it according to limitations or connector properties, and also
10966          * a chance to reject the mode entirely.
10967          */
10968         for_each_new_connector_in_state(state, connector, connector_state, i) {
10969                 if (connector_state->crtc != crtc)
10970                         continue;
10971
10972                 encoder = to_intel_encoder(connector_state->best_encoder);
10973
10974                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
10975                         DRM_DEBUG_KMS("Encoder config failure\n");
10976                         goto fail;
10977                 }
10978         }
10979
10980         /* Set default port clock if not overwritten by the encoder. Needs to be
10981          * done afterwards in case the encoder adjusts the mode. */
10982         if (!pipe_config->port_clock)
10983                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10984                         * pipe_config->pixel_multiplier;
10985
10986         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10987         if (ret < 0) {
10988                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10989                 goto fail;
10990         }
10991
10992         if (ret == RETRY) {
10993                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10994                         ret = -EINVAL;
10995                         goto fail;
10996                 }
10997
10998                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10999                 retry = false;
11000                 goto encoder_retry;
11001         }
11002
11003         /* Dithering seems to not pass-through bits correctly when it should, so
11004          * only enable it on 6bpc panels and when its not a compliance
11005          * test requesting 6bpc video pattern.
11006          */
11007         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11008                 !pipe_config->dither_force_disable;
11009         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11010                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11011
11012 fail:
11013         return ret;
11014 }
11015
11016 static void
11017 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11018 {
11019         struct drm_crtc *crtc;
11020         struct drm_crtc_state *new_crtc_state;
11021         int i;
11022
11023         /* Double check state. */
11024         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11025                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11026
11027                 /*
11028                  * Update legacy state to satisfy fbc code. This can
11029                  * be removed when fbc uses the atomic state.
11030                  */
11031                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11032                         struct drm_plane_state *plane_state = crtc->primary->state;
11033
11034                         crtc->primary->fb = plane_state->fb;
11035                         crtc->x = plane_state->src_x >> 16;
11036                         crtc->y = plane_state->src_y >> 16;
11037                 }
11038         }
11039 }
11040
11041 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11042 {
11043         int diff;
11044
11045         if (clock1 == clock2)
11046                 return true;
11047
11048         if (!clock1 || !clock2)
11049                 return false;
11050
11051         diff = abs(clock1 - clock2);
11052
11053         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11054                 return true;
11055
11056         return false;
11057 }
11058
11059 static bool
11060 intel_compare_m_n(unsigned int m, unsigned int n,
11061                   unsigned int m2, unsigned int n2,
11062                   bool exact)
11063 {
11064         if (m == m2 && n == n2)
11065                 return true;
11066
11067         if (exact || !m || !n || !m2 || !n2)
11068                 return false;
11069
11070         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11071
11072         if (n > n2) {
11073                 while (n > n2) {
11074                         m2 <<= 1;
11075                         n2 <<= 1;
11076                 }
11077         } else if (n < n2) {
11078                 while (n < n2) {
11079                         m <<= 1;
11080                         n <<= 1;
11081                 }
11082         }
11083
11084         if (n != n2)
11085                 return false;
11086
11087         return intel_fuzzy_clock_check(m, m2);
11088 }
11089
11090 static bool
11091 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11092                        struct intel_link_m_n *m2_n2,
11093                        bool adjust)
11094 {
11095         if (m_n->tu == m2_n2->tu &&
11096             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11097                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11098             intel_compare_m_n(m_n->link_m, m_n->link_n,
11099                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11100                 if (adjust)
11101                         *m2_n2 = *m_n;
11102
11103                 return true;
11104         }
11105
11106         return false;
11107 }
11108
11109 static void __printf(3, 4)
11110 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11111 {
11112         char *level;
11113         unsigned int category;
11114         struct va_format vaf;
11115         va_list args;
11116
11117         if (adjust) {
11118                 level = KERN_DEBUG;
11119                 category = DRM_UT_KMS;
11120         } else {
11121                 level = KERN_ERR;
11122                 category = DRM_UT_NONE;
11123         }
11124
11125         va_start(args, format);
11126         vaf.fmt = format;
11127         vaf.va = &args;
11128
11129         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11130
11131         va_end(args);
11132 }
11133
11134 static bool
11135 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11136                           struct intel_crtc_state *current_config,
11137                           struct intel_crtc_state *pipe_config,
11138                           bool adjust)
11139 {
11140         bool ret = true;
11141
11142 #define PIPE_CONF_CHECK_X(name) \
11143         if (current_config->name != pipe_config->name) { \
11144                 pipe_config_err(adjust, __stringify(name), \
11145                           "(expected 0x%08x, found 0x%08x)\n", \
11146                           current_config->name, \
11147                           pipe_config->name); \
11148                 ret = false; \
11149         }
11150
11151 #define PIPE_CONF_CHECK_I(name) \
11152         if (current_config->name != pipe_config->name) { \
11153                 pipe_config_err(adjust, __stringify(name), \
11154                           "(expected %i, found %i)\n", \
11155                           current_config->name, \
11156                           pipe_config->name); \
11157                 ret = false; \
11158         }
11159
11160 #define PIPE_CONF_CHECK_P(name) \
11161         if (current_config->name != pipe_config->name) { \
11162                 pipe_config_err(adjust, __stringify(name), \
11163                           "(expected %p, found %p)\n", \
11164                           current_config->name, \
11165                           pipe_config->name); \
11166                 ret = false; \
11167         }
11168
11169 #define PIPE_CONF_CHECK_M_N(name) \
11170         if (!intel_compare_link_m_n(&current_config->name, \
11171                                     &pipe_config->name,\
11172                                     adjust)) { \
11173                 pipe_config_err(adjust, __stringify(name), \
11174                           "(expected tu %i gmch %i/%i link %i/%i, " \
11175                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11176                           current_config->name.tu, \
11177                           current_config->name.gmch_m, \
11178                           current_config->name.gmch_n, \
11179                           current_config->name.link_m, \
11180                           current_config->name.link_n, \
11181                           pipe_config->name.tu, \
11182                           pipe_config->name.gmch_m, \
11183                           pipe_config->name.gmch_n, \
11184                           pipe_config->name.link_m, \
11185                           pipe_config->name.link_n); \
11186                 ret = false; \
11187         }
11188
11189 /* This is required for BDW+ where there is only one set of registers for
11190  * switching between high and low RR.
11191  * This macro can be used whenever a comparison has to be made between one
11192  * hw state and multiple sw state variables.
11193  */
11194 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11195         if (!intel_compare_link_m_n(&current_config->name, \
11196                                     &pipe_config->name, adjust) && \
11197             !intel_compare_link_m_n(&current_config->alt_name, \
11198                                     &pipe_config->name, adjust)) { \
11199                 pipe_config_err(adjust, __stringify(name), \
11200                           "(expected tu %i gmch %i/%i link %i/%i, " \
11201                           "or tu %i gmch %i/%i link %i/%i, " \
11202                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11203                           current_config->name.tu, \
11204                           current_config->name.gmch_m, \
11205                           current_config->name.gmch_n, \
11206                           current_config->name.link_m, \
11207                           current_config->name.link_n, \
11208                           current_config->alt_name.tu, \
11209                           current_config->alt_name.gmch_m, \
11210                           current_config->alt_name.gmch_n, \
11211                           current_config->alt_name.link_m, \
11212                           current_config->alt_name.link_n, \
11213                           pipe_config->name.tu, \
11214                           pipe_config->name.gmch_m, \
11215                           pipe_config->name.gmch_n, \
11216                           pipe_config->name.link_m, \
11217                           pipe_config->name.link_n); \
11218                 ret = false; \
11219         }
11220
11221 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11222         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11223                 pipe_config_err(adjust, __stringify(name), \
11224                           "(%x) (expected %i, found %i)\n", \
11225                           (mask), \
11226                           current_config->name & (mask), \
11227                           pipe_config->name & (mask)); \
11228                 ret = false; \
11229         }
11230
11231 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11232         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11233                 pipe_config_err(adjust, __stringify(name), \
11234                           "(expected %i, found %i)\n", \
11235                           current_config->name, \
11236                           pipe_config->name); \
11237                 ret = false; \
11238         }
11239
11240 #define PIPE_CONF_QUIRK(quirk)  \
11241         ((current_config->quirks | pipe_config->quirks) & (quirk))
11242
11243         PIPE_CONF_CHECK_I(cpu_transcoder);
11244
11245         PIPE_CONF_CHECK_I(has_pch_encoder);
11246         PIPE_CONF_CHECK_I(fdi_lanes);
11247         PIPE_CONF_CHECK_M_N(fdi_m_n);
11248
11249         PIPE_CONF_CHECK_I(lane_count);
11250         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11251
11252         if (INTEL_GEN(dev_priv) < 8) {
11253                 PIPE_CONF_CHECK_M_N(dp_m_n);
11254
11255                 if (current_config->has_drrs)
11256                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11257         } else
11258                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11259
11260         PIPE_CONF_CHECK_X(output_types);
11261
11262         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11263         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11264         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11265         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11266         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11267         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11268
11269         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11270         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11271         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11272         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11273         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11274         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11275
11276         PIPE_CONF_CHECK_I(pixel_multiplier);
11277         PIPE_CONF_CHECK_I(has_hdmi_sink);
11278         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11279             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11280                 PIPE_CONF_CHECK_I(limited_color_range);
11281
11282         PIPE_CONF_CHECK_I(hdmi_scrambling);
11283         PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
11284         PIPE_CONF_CHECK_I(has_infoframe);
11285         PIPE_CONF_CHECK_I(ycbcr420);
11286
11287         PIPE_CONF_CHECK_I(has_audio);
11288
11289         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11290                               DRM_MODE_FLAG_INTERLACE);
11291
11292         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11293                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11294                                       DRM_MODE_FLAG_PHSYNC);
11295                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11296                                       DRM_MODE_FLAG_NHSYNC);
11297                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11298                                       DRM_MODE_FLAG_PVSYNC);
11299                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11300                                       DRM_MODE_FLAG_NVSYNC);
11301         }
11302
11303         PIPE_CONF_CHECK_X(gmch_pfit.control);
11304         /* pfit ratios are autocomputed by the hw on gen4+ */
11305         if (INTEL_GEN(dev_priv) < 4)
11306                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11307         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11308
11309         if (!adjust) {
11310                 PIPE_CONF_CHECK_I(pipe_src_w);
11311                 PIPE_CONF_CHECK_I(pipe_src_h);
11312
11313                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11314                 if (current_config->pch_pfit.enabled) {
11315                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11316                         PIPE_CONF_CHECK_X(pch_pfit.size);
11317                 }
11318
11319                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11320                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11321         }
11322
11323         /* BDW+ don't expose a synchronous way to read the state */
11324         if (IS_HASWELL(dev_priv))
11325                 PIPE_CONF_CHECK_I(ips_enabled);
11326
11327         PIPE_CONF_CHECK_I(double_wide);
11328
11329         PIPE_CONF_CHECK_P(shared_dpll);
11330         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11331         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11332         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11333         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11334         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11335         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11336         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11337         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11338         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11339
11340         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11341         PIPE_CONF_CHECK_X(dsi_pll.div);
11342
11343         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11344                 PIPE_CONF_CHECK_I(pipe_bpp);
11345
11346         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11347         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11348
11349 #undef PIPE_CONF_CHECK_X
11350 #undef PIPE_CONF_CHECK_I
11351 #undef PIPE_CONF_CHECK_P
11352 #undef PIPE_CONF_CHECK_FLAGS
11353 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11354 #undef PIPE_CONF_QUIRK
11355
11356         return ret;
11357 }
11358
11359 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11360                                            const struct intel_crtc_state *pipe_config)
11361 {
11362         if (pipe_config->has_pch_encoder) {
11363                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11364                                                             &pipe_config->fdi_m_n);
11365                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11366
11367                 /*
11368                  * FDI already provided one idea for the dotclock.
11369                  * Yell if the encoder disagrees.
11370                  */
11371                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11372                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11373                      fdi_dotclock, dotclock);
11374         }
11375 }
11376
11377 static void verify_wm_state(struct drm_crtc *crtc,
11378                             struct drm_crtc_state *new_state)
11379 {
11380         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11381         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11382         struct skl_pipe_wm hw_wm, *sw_wm;
11383         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11384         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11386         const enum pipe pipe = intel_crtc->pipe;
11387         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11388
11389         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11390                 return;
11391
11392         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11393         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11394
11395         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11396         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11397
11398         /* planes */
11399         for_each_universal_plane(dev_priv, pipe, plane) {
11400                 hw_plane_wm = &hw_wm.planes[plane];
11401                 sw_plane_wm = &sw_wm->planes[plane];
11402
11403                 /* Watermarks */
11404                 for (level = 0; level <= max_level; level++) {
11405                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11406                                                 &sw_plane_wm->wm[level]))
11407                                 continue;
11408
11409                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11410                                   pipe_name(pipe), plane + 1, level,
11411                                   sw_plane_wm->wm[level].plane_en,
11412                                   sw_plane_wm->wm[level].plane_res_b,
11413                                   sw_plane_wm->wm[level].plane_res_l,
11414                                   hw_plane_wm->wm[level].plane_en,
11415                                   hw_plane_wm->wm[level].plane_res_b,
11416                                   hw_plane_wm->wm[level].plane_res_l);
11417                 }
11418
11419                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11420                                          &sw_plane_wm->trans_wm)) {
11421                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11422                                   pipe_name(pipe), plane + 1,
11423                                   sw_plane_wm->trans_wm.plane_en,
11424                                   sw_plane_wm->trans_wm.plane_res_b,
11425                                   sw_plane_wm->trans_wm.plane_res_l,
11426                                   hw_plane_wm->trans_wm.plane_en,
11427                                   hw_plane_wm->trans_wm.plane_res_b,
11428                                   hw_plane_wm->trans_wm.plane_res_l);
11429                 }
11430
11431                 /* DDB */
11432                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11433                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11434
11435                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11436                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11437                                   pipe_name(pipe), plane + 1,
11438                                   sw_ddb_entry->start, sw_ddb_entry->end,
11439                                   hw_ddb_entry->start, hw_ddb_entry->end);
11440                 }
11441         }
11442
11443         /*
11444          * cursor
11445          * If the cursor plane isn't active, we may not have updated it's ddb
11446          * allocation. In that case since the ddb allocation will be updated
11447          * once the plane becomes visible, we can skip this check
11448          */
11449         if (1) {
11450                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11451                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11452
11453                 /* Watermarks */
11454                 for (level = 0; level <= max_level; level++) {
11455                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11456                                                 &sw_plane_wm->wm[level]))
11457                                 continue;
11458
11459                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11460                                   pipe_name(pipe), level,
11461                                   sw_plane_wm->wm[level].plane_en,
11462                                   sw_plane_wm->wm[level].plane_res_b,
11463                                   sw_plane_wm->wm[level].plane_res_l,
11464                                   hw_plane_wm->wm[level].plane_en,
11465                                   hw_plane_wm->wm[level].plane_res_b,
11466                                   hw_plane_wm->wm[level].plane_res_l);
11467                 }
11468
11469                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11470                                          &sw_plane_wm->trans_wm)) {
11471                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11472                                   pipe_name(pipe),
11473                                   sw_plane_wm->trans_wm.plane_en,
11474                                   sw_plane_wm->trans_wm.plane_res_b,
11475                                   sw_plane_wm->trans_wm.plane_res_l,
11476                                   hw_plane_wm->trans_wm.plane_en,
11477                                   hw_plane_wm->trans_wm.plane_res_b,
11478                                   hw_plane_wm->trans_wm.plane_res_l);
11479                 }
11480
11481                 /* DDB */
11482                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11483                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11484
11485                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11486                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11487                                   pipe_name(pipe),
11488                                   sw_ddb_entry->start, sw_ddb_entry->end,
11489                                   hw_ddb_entry->start, hw_ddb_entry->end);
11490                 }
11491         }
11492 }
11493
11494 static void
11495 verify_connector_state(struct drm_device *dev,
11496                        struct drm_atomic_state *state,
11497                        struct drm_crtc *crtc)
11498 {
11499         struct drm_connector *connector;
11500         struct drm_connector_state *new_conn_state;
11501         int i;
11502
11503         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11504                 struct drm_encoder *encoder = connector->encoder;
11505                 struct drm_crtc_state *crtc_state = NULL;
11506
11507                 if (new_conn_state->crtc != crtc)
11508                         continue;
11509
11510                 if (crtc)
11511                         crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
11512
11513                 intel_connector_verify_state(crtc_state, new_conn_state);
11514
11515                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11516                      "connector's atomic encoder doesn't match legacy encoder\n");
11517         }
11518 }
11519
11520 static void
11521 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11522 {
11523         struct intel_encoder *encoder;
11524         struct drm_connector *connector;
11525         struct drm_connector_state *old_conn_state, *new_conn_state;
11526         int i;
11527
11528         for_each_intel_encoder(dev, encoder) {
11529                 bool enabled = false, found = false;
11530                 enum pipe pipe;
11531
11532                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11533                               encoder->base.base.id,
11534                               encoder->base.name);
11535
11536                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11537                                                    new_conn_state, i) {
11538                         if (old_conn_state->best_encoder == &encoder->base)
11539                                 found = true;
11540
11541                         if (new_conn_state->best_encoder != &encoder->base)
11542                                 continue;
11543                         found = enabled = true;
11544
11545                         I915_STATE_WARN(new_conn_state->crtc !=
11546                                         encoder->base.crtc,
11547                              "connector's crtc doesn't match encoder crtc\n");
11548                 }
11549
11550                 if (!found)
11551                         continue;
11552
11553                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11554                      "encoder's enabled state mismatch "
11555                      "(expected %i, found %i)\n",
11556                      !!encoder->base.crtc, enabled);
11557
11558                 if (!encoder->base.crtc) {
11559                         bool active;
11560
11561                         active = encoder->get_hw_state(encoder, &pipe);
11562                         I915_STATE_WARN(active,
11563                              "encoder detached but still enabled on pipe %c.\n",
11564                              pipe_name(pipe));
11565                 }
11566         }
11567 }
11568
11569 static void
11570 verify_crtc_state(struct drm_crtc *crtc,
11571                   struct drm_crtc_state *old_crtc_state,
11572                   struct drm_crtc_state *new_crtc_state)
11573 {
11574         struct drm_device *dev = crtc->dev;
11575         struct drm_i915_private *dev_priv = to_i915(dev);
11576         struct intel_encoder *encoder;
11577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11578         struct intel_crtc_state *pipe_config, *sw_config;
11579         struct drm_atomic_state *old_state;
11580         bool active;
11581
11582         old_state = old_crtc_state->state;
11583         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
11584         pipe_config = to_intel_crtc_state(old_crtc_state);
11585         memset(pipe_config, 0, sizeof(*pipe_config));
11586         pipe_config->base.crtc = crtc;
11587         pipe_config->base.state = old_state;
11588
11589         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
11590
11591         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
11592
11593         /* we keep both pipes enabled on 830 */
11594         if (IS_I830(dev_priv))
11595                 active = new_crtc_state->active;
11596
11597         I915_STATE_WARN(new_crtc_state->active != active,
11598              "crtc active state doesn't match with hw state "
11599              "(expected %i, found %i)\n", new_crtc_state->active, active);
11600
11601         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
11602              "transitional active state does not match atomic hw state "
11603              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
11604
11605         for_each_encoder_on_crtc(dev, crtc, encoder) {
11606                 enum pipe pipe;
11607
11608                 active = encoder->get_hw_state(encoder, &pipe);
11609                 I915_STATE_WARN(active != new_crtc_state->active,
11610                         "[ENCODER:%i] active %i with crtc active %i\n",
11611                         encoder->base.base.id, active, new_crtc_state->active);
11612
11613                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
11614                                 "Encoder connected to wrong pipe %c\n",
11615                                 pipe_name(pipe));
11616
11617                 if (active) {
11618                         pipe_config->output_types |= 1 << encoder->type;
11619                         encoder->get_config(encoder, pipe_config);
11620                 }
11621         }
11622
11623         intel_crtc_compute_pixel_rate(pipe_config);
11624
11625         if (!new_crtc_state->active)
11626                 return;
11627
11628         intel_pipe_config_sanity_check(dev_priv, pipe_config);
11629
11630         sw_config = to_intel_crtc_state(new_crtc_state);
11631         if (!intel_pipe_config_compare(dev_priv, sw_config,
11632                                        pipe_config, false)) {
11633                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11634                 intel_dump_pipe_config(intel_crtc, pipe_config,
11635                                        "[hw state]");
11636                 intel_dump_pipe_config(intel_crtc, sw_config,
11637                                        "[sw state]");
11638         }
11639 }
11640
11641 static void
11642 verify_single_dpll_state(struct drm_i915_private *dev_priv,
11643                          struct intel_shared_dpll *pll,
11644                          struct drm_crtc *crtc,
11645                          struct drm_crtc_state *new_state)
11646 {
11647         struct intel_dpll_hw_state dpll_hw_state;
11648         unsigned crtc_mask;
11649         bool active;
11650
11651         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11652
11653         DRM_DEBUG_KMS("%s\n", pll->name);
11654
11655         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
11656
11657         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
11658                 I915_STATE_WARN(!pll->on && pll->active_mask,
11659                      "pll in active use but not on in sw tracking\n");
11660                 I915_STATE_WARN(pll->on && !pll->active_mask,
11661                      "pll is on but not used by any active crtc\n");
11662                 I915_STATE_WARN(pll->on != active,
11663                      "pll on state mismatch (expected %i, found %i)\n",
11664                      pll->on, active);
11665         }
11666
11667         if (!crtc) {
11668                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
11669                                 "more active pll users than references: %x vs %x\n",
11670                                 pll->active_mask, pll->state.crtc_mask);
11671
11672                 return;
11673         }
11674
11675         crtc_mask = 1 << drm_crtc_index(crtc);
11676
11677         if (new_state->active)
11678                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
11679                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
11680                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11681         else
11682                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11683                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
11684                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
11685
11686         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
11687                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
11688                         crtc_mask, pll->state.crtc_mask);
11689
11690         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
11691                                           &dpll_hw_state,
11692                                           sizeof(dpll_hw_state)),
11693                         "pll hw state mismatch\n");
11694 }
11695
11696 static void
11697 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
11698                          struct drm_crtc_state *old_crtc_state,
11699                          struct drm_crtc_state *new_crtc_state)
11700 {
11701         struct drm_i915_private *dev_priv = to_i915(dev);
11702         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
11703         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
11704
11705         if (new_state->shared_dpll)
11706                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
11707
11708         if (old_state->shared_dpll &&
11709             old_state->shared_dpll != new_state->shared_dpll) {
11710                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
11711                 struct intel_shared_dpll *pll = old_state->shared_dpll;
11712
11713                 I915_STATE_WARN(pll->active_mask & crtc_mask,
11714                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
11715                                 pipe_name(drm_crtc_index(crtc)));
11716                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
11717                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
11718                                 pipe_name(drm_crtc_index(crtc)));
11719         }
11720 }
11721
11722 static void
11723 intel_modeset_verify_crtc(struct drm_crtc *crtc,
11724                           struct drm_atomic_state *state,
11725                           struct drm_crtc_state *old_state,
11726                           struct drm_crtc_state *new_state)
11727 {
11728         if (!needs_modeset(new_state) &&
11729             !to_intel_crtc_state(new_state)->update_pipe)
11730                 return;
11731
11732         verify_wm_state(crtc, new_state);
11733         verify_connector_state(crtc->dev, state, crtc);
11734         verify_crtc_state(crtc, old_state, new_state);
11735         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
11736 }
11737
11738 static void
11739 verify_disabled_dpll_state(struct drm_device *dev)
11740 {
11741         struct drm_i915_private *dev_priv = to_i915(dev);
11742         int i;
11743
11744         for (i = 0; i < dev_priv->num_shared_dpll; i++)
11745                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
11746 }
11747
11748 static void
11749 intel_modeset_verify_disabled(struct drm_device *dev,
11750                               struct drm_atomic_state *state)
11751 {
11752         verify_encoder_state(dev, state);
11753         verify_connector_state(dev, state, NULL);
11754         verify_disabled_dpll_state(dev);
11755 }
11756
11757 static void update_scanline_offset(struct intel_crtc *crtc)
11758 {
11759         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11760
11761         /*
11762          * The scanline counter increments at the leading edge of hsync.
11763          *
11764          * On most platforms it starts counting from vtotal-1 on the
11765          * first active line. That means the scanline counter value is
11766          * always one less than what we would expect. Ie. just after
11767          * start of vblank, which also occurs at start of hsync (on the
11768          * last active line), the scanline counter will read vblank_start-1.
11769          *
11770          * On gen2 the scanline counter starts counting from 1 instead
11771          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11772          * to keep the value positive), instead of adding one.
11773          *
11774          * On HSW+ the behaviour of the scanline counter depends on the output
11775          * type. For DP ports it behaves like most other platforms, but on HDMI
11776          * there's an extra 1 line difference. So we need to add two instead of
11777          * one to the value.
11778          *
11779          * On VLV/CHV DSI the scanline counter would appear to increment
11780          * approx. 1/3 of a scanline before start of vblank. Unfortunately
11781          * that means we can't tell whether we're in vblank or not while
11782          * we're on that particular line. We must still set scanline_offset
11783          * to 1 so that the vblank timestamps come out correct when we query
11784          * the scanline counter from within the vblank interrupt handler.
11785          * However if queried just before the start of vblank we'll get an
11786          * answer that's slightly in the future.
11787          */
11788         if (IS_GEN2(dev_priv)) {
11789                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
11790                 int vtotal;
11791
11792                 vtotal = adjusted_mode->crtc_vtotal;
11793                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
11794                         vtotal /= 2;
11795
11796                 crtc->scanline_offset = vtotal - 1;
11797         } else if (HAS_DDI(dev_priv) &&
11798                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
11799                 crtc->scanline_offset = 2;
11800         } else
11801                 crtc->scanline_offset = 1;
11802 }
11803
11804 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
11805 {
11806         struct drm_device *dev = state->dev;
11807         struct drm_i915_private *dev_priv = to_i915(dev);
11808         struct drm_crtc *crtc;
11809         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11810         int i;
11811
11812         if (!dev_priv->display.crtc_compute_clock)
11813                 return;
11814
11815         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11816                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11817                 struct intel_shared_dpll *old_dpll =
11818                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
11819
11820                 if (!needs_modeset(new_crtc_state))
11821                         continue;
11822
11823                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
11824
11825                 if (!old_dpll)
11826                         continue;
11827
11828                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
11829         }
11830 }
11831
11832 /*
11833  * This implements the workaround described in the "notes" section of the mode
11834  * set sequence documentation. When going from no pipes or single pipe to
11835  * multiple pipes, and planes are enabled after the pipe, we need to wait at
11836  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
11837  */
11838 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
11839 {
11840         struct drm_crtc_state *crtc_state;
11841         struct intel_crtc *intel_crtc;
11842         struct drm_crtc *crtc;
11843         struct intel_crtc_state *first_crtc_state = NULL;
11844         struct intel_crtc_state *other_crtc_state = NULL;
11845         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
11846         int i;
11847
11848         /* look at all crtc's that are going to be enabled in during modeset */
11849         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
11850                 intel_crtc = to_intel_crtc(crtc);
11851
11852                 if (!crtc_state->active || !needs_modeset(crtc_state))
11853                         continue;
11854
11855                 if (first_crtc_state) {
11856                         other_crtc_state = to_intel_crtc_state(crtc_state);
11857                         break;
11858                 } else {
11859                         first_crtc_state = to_intel_crtc_state(crtc_state);
11860                         first_pipe = intel_crtc->pipe;
11861                 }
11862         }
11863
11864         /* No workaround needed? */
11865         if (!first_crtc_state)
11866                 return 0;
11867
11868         /* w/a possibly needed, check how many crtc's are already enabled. */
11869         for_each_intel_crtc(state->dev, intel_crtc) {
11870                 struct intel_crtc_state *pipe_config;
11871
11872                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11873                 if (IS_ERR(pipe_config))
11874                         return PTR_ERR(pipe_config);
11875
11876                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
11877
11878                 if (!pipe_config->base.active ||
11879                     needs_modeset(&pipe_config->base))
11880                         continue;
11881
11882                 /* 2 or more enabled crtcs means no need for w/a */
11883                 if (enabled_pipe != INVALID_PIPE)
11884                         return 0;
11885
11886                 enabled_pipe = intel_crtc->pipe;
11887         }
11888
11889         if (enabled_pipe != INVALID_PIPE)
11890                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
11891         else if (other_crtc_state)
11892                 other_crtc_state->hsw_workaround_pipe = first_pipe;
11893
11894         return 0;
11895 }
11896
11897 static int intel_lock_all_pipes(struct drm_atomic_state *state)
11898 {
11899         struct drm_crtc *crtc;
11900
11901         /* Add all pipes to the state */
11902         for_each_crtc(state->dev, crtc) {
11903                 struct drm_crtc_state *crtc_state;
11904
11905                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11906                 if (IS_ERR(crtc_state))
11907                         return PTR_ERR(crtc_state);
11908         }
11909
11910         return 0;
11911 }
11912
11913 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
11914 {
11915         struct drm_crtc *crtc;
11916
11917         /*
11918          * Add all pipes to the state, and force
11919          * a modeset on all the active ones.
11920          */
11921         for_each_crtc(state->dev, crtc) {
11922                 struct drm_crtc_state *crtc_state;
11923                 int ret;
11924
11925                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
11926                 if (IS_ERR(crtc_state))
11927                         return PTR_ERR(crtc_state);
11928
11929                 if (!crtc_state->active || needs_modeset(crtc_state))
11930                         continue;
11931
11932                 crtc_state->mode_changed = true;
11933
11934                 ret = drm_atomic_add_affected_connectors(state, crtc);
11935                 if (ret)
11936                         return ret;
11937
11938                 ret = drm_atomic_add_affected_planes(state, crtc);
11939                 if (ret)
11940                         return ret;
11941         }
11942
11943         return 0;
11944 }
11945
11946 static int intel_modeset_checks(struct drm_atomic_state *state)
11947 {
11948         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
11949         struct drm_i915_private *dev_priv = to_i915(state->dev);
11950         struct drm_crtc *crtc;
11951         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
11952         int ret = 0, i;
11953
11954         if (!check_digital_port_conflicts(state)) {
11955                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11956                 return -EINVAL;
11957         }
11958
11959         intel_state->modeset = true;
11960         intel_state->active_crtcs = dev_priv->active_crtcs;
11961         intel_state->cdclk.logical = dev_priv->cdclk.logical;
11962         intel_state->cdclk.actual = dev_priv->cdclk.actual;
11963
11964         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
11965                 if (new_crtc_state->active)
11966                         intel_state->active_crtcs |= 1 << i;
11967                 else
11968                         intel_state->active_crtcs &= ~(1 << i);
11969
11970                 if (old_crtc_state->active != new_crtc_state->active)
11971                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
11972         }
11973
11974         /*
11975          * See if the config requires any additional preparation, e.g.
11976          * to adjust global state with pipes off.  We need to do this
11977          * here so we can get the modeset_pipe updated config for the new
11978          * mode set on this crtc.  For other crtcs we need to use the
11979          * adjusted_mode bits in the crtc directly.
11980          */
11981         if (dev_priv->display.modeset_calc_cdclk) {
11982                 ret = dev_priv->display.modeset_calc_cdclk(state);
11983                 if (ret < 0)
11984                         return ret;
11985
11986                 /*
11987                  * Writes to dev_priv->cdclk.logical must protected by
11988                  * holding all the crtc locks, even if we don't end up
11989                  * touching the hardware
11990                  */
11991                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
11992                                                &intel_state->cdclk.logical)) {
11993                         ret = intel_lock_all_pipes(state);
11994                         if (ret < 0)
11995                                 return ret;
11996                 }
11997
11998                 /* All pipes must be switched off while we change the cdclk. */
11999                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12000                                                &intel_state->cdclk.actual)) {
12001                         ret = intel_modeset_all_pipes(state);
12002                         if (ret < 0)
12003                                 return ret;
12004                 }
12005
12006                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12007                               intel_state->cdclk.logical.cdclk,
12008                               intel_state->cdclk.actual.cdclk);
12009         } else {
12010                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12011         }
12012
12013         intel_modeset_clear_plls(state);
12014
12015         if (IS_HASWELL(dev_priv))
12016                 return haswell_mode_set_planes_workaround(state);
12017
12018         return 0;
12019 }
12020
12021 /*
12022  * Handle calculation of various watermark data at the end of the atomic check
12023  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12024  * handlers to ensure that all derived state has been updated.
12025  */
12026 static int calc_watermark_data(struct drm_atomic_state *state)
12027 {
12028         struct drm_device *dev = state->dev;
12029         struct drm_i915_private *dev_priv = to_i915(dev);
12030
12031         /* Is there platform-specific watermark information to calculate? */
12032         if (dev_priv->display.compute_global_watermarks)
12033                 return dev_priv->display.compute_global_watermarks(state);
12034
12035         return 0;
12036 }
12037
12038 /**
12039  * intel_atomic_check - validate state object
12040  * @dev: drm device
12041  * @state: state to validate
12042  */
12043 static int intel_atomic_check(struct drm_device *dev,
12044                               struct drm_atomic_state *state)
12045 {
12046         struct drm_i915_private *dev_priv = to_i915(dev);
12047         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12048         struct drm_crtc *crtc;
12049         struct drm_crtc_state *old_crtc_state, *crtc_state;
12050         int ret, i;
12051         bool any_ms = false;
12052
12053         ret = drm_atomic_helper_check_modeset(dev, state);
12054         if (ret)
12055                 return ret;
12056
12057         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12058                 struct intel_crtc_state *pipe_config =
12059                         to_intel_crtc_state(crtc_state);
12060
12061                 /* Catch I915_MODE_FLAG_INHERITED */
12062                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12063                         crtc_state->mode_changed = true;
12064
12065                 if (!needs_modeset(crtc_state))
12066                         continue;
12067
12068                 if (!crtc_state->enable) {
12069                         any_ms = true;
12070                         continue;
12071                 }
12072
12073                 /* FIXME: For only active_changed we shouldn't need to do any
12074                  * state recomputation at all. */
12075
12076                 ret = drm_atomic_add_affected_connectors(state, crtc);
12077                 if (ret)
12078                         return ret;
12079
12080                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12081                 if (ret) {
12082                         intel_dump_pipe_config(to_intel_crtc(crtc),
12083                                                pipe_config, "[failed]");
12084                         return ret;
12085                 }
12086
12087                 if (i915.fastboot &&
12088                     intel_pipe_config_compare(dev_priv,
12089                                         to_intel_crtc_state(old_crtc_state),
12090                                         pipe_config, true)) {
12091                         crtc_state->mode_changed = false;
12092                         pipe_config->update_pipe = true;
12093                 }
12094
12095                 if (needs_modeset(crtc_state))
12096                         any_ms = true;
12097
12098                 ret = drm_atomic_add_affected_planes(state, crtc);
12099                 if (ret)
12100                         return ret;
12101
12102                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12103                                        needs_modeset(crtc_state) ?
12104                                        "[modeset]" : "[fastset]");
12105         }
12106
12107         if (any_ms) {
12108                 ret = intel_modeset_checks(state);
12109
12110                 if (ret)
12111                         return ret;
12112         } else {
12113                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12114         }
12115
12116         ret = drm_atomic_helper_check_planes(dev, state);
12117         if (ret)
12118                 return ret;
12119
12120         intel_fbc_choose_crtc(dev_priv, state);
12121         return calc_watermark_data(state);
12122 }
12123
12124 static int intel_atomic_prepare_commit(struct drm_device *dev,
12125                                        struct drm_atomic_state *state)
12126 {
12127         return drm_atomic_helper_prepare_planes(dev, state);
12128 }
12129
12130 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12131 {
12132         struct drm_device *dev = crtc->base.dev;
12133
12134         if (!dev->max_vblank_count)
12135                 return drm_crtc_accurate_vblank_count(&crtc->base);
12136
12137         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12138 }
12139
12140 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12141                                           struct drm_i915_private *dev_priv,
12142                                           unsigned crtc_mask)
12143 {
12144         unsigned last_vblank_count[I915_MAX_PIPES];
12145         enum pipe pipe;
12146         int ret;
12147
12148         if (!crtc_mask)
12149                 return;
12150
12151         for_each_pipe(dev_priv, pipe) {
12152                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12153                                                                   pipe);
12154
12155                 if (!((1 << pipe) & crtc_mask))
12156                         continue;
12157
12158                 ret = drm_crtc_vblank_get(&crtc->base);
12159                 if (WARN_ON(ret != 0)) {
12160                         crtc_mask &= ~(1 << pipe);
12161                         continue;
12162                 }
12163
12164                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12165         }
12166
12167         for_each_pipe(dev_priv, pipe) {
12168                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12169                                                                   pipe);
12170                 long lret;
12171
12172                 if (!((1 << pipe) & crtc_mask))
12173                         continue;
12174
12175                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12176                                 last_vblank_count[pipe] !=
12177                                         drm_crtc_vblank_count(&crtc->base),
12178                                 msecs_to_jiffies(50));
12179
12180                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12181
12182                 drm_crtc_vblank_put(&crtc->base);
12183         }
12184 }
12185
12186 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12187 {
12188         /* fb updated, need to unpin old fb */
12189         if (crtc_state->fb_changed)
12190                 return true;
12191
12192         /* wm changes, need vblank before final wm's */
12193         if (crtc_state->update_wm_post)
12194                 return true;
12195
12196         if (crtc_state->wm.need_postvbl_update)
12197                 return true;
12198
12199         return false;
12200 }
12201
12202 static void intel_update_crtc(struct drm_crtc *crtc,
12203                               struct drm_atomic_state *state,
12204                               struct drm_crtc_state *old_crtc_state,
12205                               struct drm_crtc_state *new_crtc_state,
12206                               unsigned int *crtc_vblank_mask)
12207 {
12208         struct drm_device *dev = crtc->dev;
12209         struct drm_i915_private *dev_priv = to_i915(dev);
12210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12211         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12212         bool modeset = needs_modeset(new_crtc_state);
12213
12214         if (modeset) {
12215                 update_scanline_offset(intel_crtc);
12216                 dev_priv->display.crtc_enable(pipe_config, state);
12217         } else {
12218                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12219                                        pipe_config);
12220         }
12221
12222         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12223                 intel_fbc_enable(
12224                     intel_crtc, pipe_config,
12225                     to_intel_plane_state(crtc->primary->state));
12226         }
12227
12228         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12229
12230         if (needs_vblank_wait(pipe_config))
12231                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12232 }
12233
12234 static void intel_update_crtcs(struct drm_atomic_state *state,
12235                                unsigned int *crtc_vblank_mask)
12236 {
12237         struct drm_crtc *crtc;
12238         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12239         int i;
12240
12241         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12242                 if (!new_crtc_state->active)
12243                         continue;
12244
12245                 intel_update_crtc(crtc, state, old_crtc_state,
12246                                   new_crtc_state, crtc_vblank_mask);
12247         }
12248 }
12249
12250 static void skl_update_crtcs(struct drm_atomic_state *state,
12251                              unsigned int *crtc_vblank_mask)
12252 {
12253         struct drm_i915_private *dev_priv = to_i915(state->dev);
12254         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12255         struct drm_crtc *crtc;
12256         struct intel_crtc *intel_crtc;
12257         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12258         struct intel_crtc_state *cstate;
12259         unsigned int updated = 0;
12260         bool progress;
12261         enum pipe pipe;
12262         int i;
12263
12264         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12265
12266         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12267                 /* ignore allocations for crtc's that have been turned off. */
12268                 if (new_crtc_state->active)
12269                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12270
12271         /*
12272          * Whenever the number of active pipes changes, we need to make sure we
12273          * update the pipes in the right order so that their ddb allocations
12274          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12275          * cause pipe underruns and other bad stuff.
12276          */
12277         do {
12278                 progress = false;
12279
12280                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12281                         bool vbl_wait = false;
12282                         unsigned int cmask = drm_crtc_mask(crtc);
12283
12284                         intel_crtc = to_intel_crtc(crtc);
12285                         cstate = to_intel_crtc_state(new_crtc_state);
12286                         pipe = intel_crtc->pipe;
12287
12288                         if (updated & cmask || !cstate->base.active)
12289                                 continue;
12290
12291                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12292                                 continue;
12293
12294                         updated |= cmask;
12295                         entries[i] = &cstate->wm.skl.ddb;
12296
12297                         /*
12298                          * If this is an already active pipe, it's DDB changed,
12299                          * and this isn't the last pipe that needs updating
12300                          * then we need to wait for a vblank to pass for the
12301                          * new ddb allocation to take effect.
12302                          */
12303                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12304                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12305                             !new_crtc_state->active_changed &&
12306                             intel_state->wm_results.dirty_pipes != updated)
12307                                 vbl_wait = true;
12308
12309                         intel_update_crtc(crtc, state, old_crtc_state,
12310                                           new_crtc_state, crtc_vblank_mask);
12311
12312                         if (vbl_wait)
12313                                 intel_wait_for_vblank(dev_priv, pipe);
12314
12315                         progress = true;
12316                 }
12317         } while (progress);
12318 }
12319
12320 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12321 {
12322         struct intel_atomic_state *state, *next;
12323         struct llist_node *freed;
12324
12325         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12326         llist_for_each_entry_safe(state, next, freed, freed)
12327                 drm_atomic_state_put(&state->base);
12328 }
12329
12330 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12331 {
12332         struct drm_i915_private *dev_priv =
12333                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12334
12335         intel_atomic_helper_free_state(dev_priv);
12336 }
12337
12338 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
12339 {
12340         struct wait_queue_entry wait_fence, wait_reset;
12341         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
12342
12343         init_wait_entry(&wait_fence, 0);
12344         init_wait_entry(&wait_reset, 0);
12345         for (;;) {
12346                 prepare_to_wait(&intel_state->commit_ready.wait,
12347                                 &wait_fence, TASK_UNINTERRUPTIBLE);
12348                 prepare_to_wait(&dev_priv->gpu_error.wait_queue,
12349                                 &wait_reset, TASK_UNINTERRUPTIBLE);
12350
12351
12352                 if (i915_sw_fence_done(&intel_state->commit_ready)
12353                     || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
12354                         break;
12355
12356                 schedule();
12357         }
12358         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
12359         finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
12360 }
12361
12362 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12363 {
12364         struct drm_device *dev = state->dev;
12365         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12366         struct drm_i915_private *dev_priv = to_i915(dev);
12367         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12368         struct drm_crtc *crtc;
12369         struct intel_crtc_state *intel_cstate;
12370         bool hw_check = intel_state->modeset;
12371         u64 put_domains[I915_MAX_PIPES] = {};
12372         unsigned crtc_vblank_mask = 0;
12373         int i;
12374
12375         intel_atomic_commit_fence_wait(intel_state);
12376
12377         drm_atomic_helper_wait_for_dependencies(state);
12378
12379         if (intel_state->modeset)
12380                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12381
12382         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12383                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12384
12385                 if (needs_modeset(new_crtc_state) ||
12386                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12387                         hw_check = true;
12388
12389                         put_domains[to_intel_crtc(crtc)->pipe] =
12390                                 modeset_get_crtc_power_domains(crtc,
12391                                         to_intel_crtc_state(new_crtc_state));
12392                 }
12393
12394                 if (!needs_modeset(new_crtc_state))
12395                         continue;
12396
12397                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12398                                        to_intel_crtc_state(new_crtc_state));
12399
12400                 if (old_crtc_state->active) {
12401                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12402                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12403                         intel_crtc->active = false;
12404                         intel_fbc_disable(intel_crtc);
12405                         intel_disable_shared_dpll(intel_crtc);
12406
12407                         /*
12408                          * Underruns don't always raise
12409                          * interrupts, so check manually.
12410                          */
12411                         intel_check_cpu_fifo_underruns(dev_priv);
12412                         intel_check_pch_fifo_underruns(dev_priv);
12413
12414                         if (!new_crtc_state->active) {
12415                                 /*
12416                                  * Make sure we don't call initial_watermarks
12417                                  * for ILK-style watermark updates.
12418                                  *
12419                                  * No clue what this is supposed to achieve.
12420                                  */
12421                                 if (INTEL_GEN(dev_priv) >= 9)
12422                                         dev_priv->display.initial_watermarks(intel_state,
12423                                                                              to_intel_crtc_state(new_crtc_state));
12424                         }
12425                 }
12426         }
12427
12428         /* Only after disabling all output pipelines that will be changed can we
12429          * update the the output configuration. */
12430         intel_modeset_update_crtc_state(state);
12431
12432         if (intel_state->modeset) {
12433                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12434
12435                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12436
12437                 /*
12438                  * SKL workaround: bspec recommends we disable the SAGV when we
12439                  * have more then one pipe enabled
12440                  */
12441                 if (!intel_can_enable_sagv(state))
12442                         intel_disable_sagv(dev_priv);
12443
12444                 intel_modeset_verify_disabled(dev, state);
12445         }
12446
12447         /* Complete the events for pipes that have now been disabled */
12448         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12449                 bool modeset = needs_modeset(new_crtc_state);
12450
12451                 /* Complete events for now disable pipes here. */
12452                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12453                         spin_lock_irq(&dev->event_lock);
12454                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12455                         spin_unlock_irq(&dev->event_lock);
12456
12457                         new_crtc_state->event = NULL;
12458                 }
12459         }
12460
12461         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12462         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12463
12464         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12465          * already, but still need the state for the delayed optimization. To
12466          * fix this:
12467          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12468          * - schedule that vblank worker _before_ calling hw_done
12469          * - at the start of commit_tail, cancel it _synchrously
12470          * - switch over to the vblank wait helper in the core after that since
12471          *   we don't need out special handling any more.
12472          */
12473         if (!state->legacy_cursor_update)
12474                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12475
12476         /*
12477          * Now that the vblank has passed, we can go ahead and program the
12478          * optimal watermarks on platforms that need two-step watermark
12479          * programming.
12480          *
12481          * TODO: Move this (and other cleanup) to an async worker eventually.
12482          */
12483         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12484                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12485
12486                 if (dev_priv->display.optimize_watermarks)
12487                         dev_priv->display.optimize_watermarks(intel_state,
12488                                                               intel_cstate);
12489         }
12490
12491         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12492                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12493
12494                 if (put_domains[i])
12495                         modeset_put_power_domains(dev_priv, put_domains[i]);
12496
12497                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12498         }
12499
12500         if (intel_state->modeset && intel_can_enable_sagv(state))
12501                 intel_enable_sagv(dev_priv);
12502
12503         drm_atomic_helper_commit_hw_done(state);
12504
12505         if (intel_state->modeset) {
12506                 /* As one of the primary mmio accessors, KMS has a high
12507                  * likelihood of triggering bugs in unclaimed access. After we
12508                  * finish modesetting, see if an error has been flagged, and if
12509                  * so enable debugging for the next modeset - and hope we catch
12510                  * the culprit.
12511                  */
12512                 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12513                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12514         }
12515
12516         drm_atomic_helper_cleanup_planes(dev, state);
12517
12518         drm_atomic_helper_commit_cleanup_done(state);
12519
12520         drm_atomic_state_put(state);
12521
12522         intel_atomic_helper_free_state(dev_priv);
12523 }
12524
12525 static void intel_atomic_commit_work(struct work_struct *work)
12526 {
12527         struct drm_atomic_state *state =
12528                 container_of(work, struct drm_atomic_state, commit_work);
12529
12530         intel_atomic_commit_tail(state);
12531 }
12532
12533 static int __i915_sw_fence_call
12534 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12535                           enum i915_sw_fence_notify notify)
12536 {
12537         struct intel_atomic_state *state =
12538                 container_of(fence, struct intel_atomic_state, commit_ready);
12539
12540         switch (notify) {
12541         case FENCE_COMPLETE:
12542                 /* we do blocking waits in the worker, nothing to do here */
12543                 break;
12544         case FENCE_FREE:
12545                 {
12546                         struct intel_atomic_helper *helper =
12547                                 &to_i915(state->base.dev)->atomic_helper;
12548
12549                         if (llist_add(&state->freed, &helper->free_list))
12550                                 schedule_work(&helper->free_work);
12551                         break;
12552                 }
12553         }
12554
12555         return NOTIFY_DONE;
12556 }
12557
12558 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12559 {
12560         struct drm_plane_state *old_plane_state, *new_plane_state;
12561         struct drm_plane *plane;
12562         int i;
12563
12564         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
12565                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
12566                                   intel_fb_obj(new_plane_state->fb),
12567                                   to_intel_plane(plane)->frontbuffer_bit);
12568 }
12569
12570 /**
12571  * intel_atomic_commit - commit validated state object
12572  * @dev: DRM device
12573  * @state: the top-level driver state object
12574  * @nonblock: nonblocking commit
12575  *
12576  * This function commits a top-level state object that has been validated
12577  * with drm_atomic_helper_check().
12578  *
12579  * RETURNS
12580  * Zero for success or -errno.
12581  */
12582 static int intel_atomic_commit(struct drm_device *dev,
12583                                struct drm_atomic_state *state,
12584                                bool nonblock)
12585 {
12586         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12587         struct drm_i915_private *dev_priv = to_i915(dev);
12588         int ret = 0;
12589
12590         ret = drm_atomic_helper_setup_commit(state, nonblock);
12591         if (ret)
12592                 return ret;
12593
12594         drm_atomic_state_get(state);
12595         i915_sw_fence_init(&intel_state->commit_ready,
12596                            intel_atomic_commit_ready);
12597
12598         ret = intel_atomic_prepare_commit(dev, state);
12599         if (ret) {
12600                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
12601                 i915_sw_fence_commit(&intel_state->commit_ready);
12602                 return ret;
12603         }
12604
12605         /*
12606          * The intel_legacy_cursor_update() fast path takes care
12607          * of avoiding the vblank waits for simple cursor
12608          * movement and flips. For cursor on/off and size changes,
12609          * we want to perform the vblank waits so that watermark
12610          * updates happen during the correct frames. Gen9+ have
12611          * double buffered watermarks and so shouldn't need this.
12612          *
12613          * Do this after drm_atomic_helper_setup_commit() and
12614          * intel_atomic_prepare_commit() because we still want
12615          * to skip the flip and fb cleanup waits. Although that
12616          * does risk yanking the mapping from under the display
12617          * engine.
12618          *
12619          * FIXME doing watermarks and fb cleanup from a vblank worker
12620          * (assuming we had any) would solve these problems.
12621          */
12622         if (INTEL_GEN(dev_priv) < 9)
12623                 state->legacy_cursor_update = false;
12624
12625         ret = drm_atomic_helper_swap_state(state, true);
12626         if (ret) {
12627                 i915_sw_fence_commit(&intel_state->commit_ready);
12628
12629                 drm_atomic_helper_cleanup_planes(dev, state);
12630                 return ret;
12631         }
12632         dev_priv->wm.distrust_bios_wm = false;
12633         intel_shared_dpll_swap_state(state);
12634         intel_atomic_track_fbs(state);
12635
12636         if (intel_state->modeset) {
12637                 memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
12638                        sizeof(intel_state->min_cdclk));
12639                 dev_priv->active_crtcs = intel_state->active_crtcs;
12640                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
12641                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
12642         }
12643
12644         drm_atomic_state_get(state);
12645         INIT_WORK(&state->commit_work, intel_atomic_commit_work);
12646
12647         i915_sw_fence_commit(&intel_state->commit_ready);
12648         if (nonblock)
12649                 queue_work(system_unbound_wq, &state->commit_work);
12650         else
12651                 intel_atomic_commit_tail(state);
12652
12653
12654         return 0;
12655 }
12656
12657 static const struct drm_crtc_funcs intel_crtc_funcs = {
12658         .gamma_set = drm_atomic_helper_legacy_gamma_set,
12659         .set_config = drm_atomic_helper_set_config,
12660         .destroy = intel_crtc_destroy,
12661         .page_flip = drm_atomic_helper_page_flip,
12662         .atomic_duplicate_state = intel_crtc_duplicate_state,
12663         .atomic_destroy_state = intel_crtc_destroy_state,
12664         .set_crc_source = intel_crtc_set_crc_source,
12665 };
12666
12667 struct wait_rps_boost {
12668         struct wait_queue_entry wait;
12669
12670         struct drm_crtc *crtc;
12671         struct drm_i915_gem_request *request;
12672 };
12673
12674 static int do_rps_boost(struct wait_queue_entry *_wait,
12675                         unsigned mode, int sync, void *key)
12676 {
12677         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
12678         struct drm_i915_gem_request *rq = wait->request;
12679
12680         gen6_rps_boost(rq, NULL);
12681         i915_gem_request_put(rq);
12682
12683         drm_crtc_vblank_put(wait->crtc);
12684
12685         list_del(&wait->wait.entry);
12686         kfree(wait);
12687         return 1;
12688 }
12689
12690 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
12691                                        struct dma_fence *fence)
12692 {
12693         struct wait_rps_boost *wait;
12694
12695         if (!dma_fence_is_i915(fence))
12696                 return;
12697
12698         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
12699                 return;
12700
12701         if (drm_crtc_vblank_get(crtc))
12702                 return;
12703
12704         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
12705         if (!wait) {
12706                 drm_crtc_vblank_put(crtc);
12707                 return;
12708         }
12709
12710         wait->request = to_request(dma_fence_get(fence));
12711         wait->crtc = crtc;
12712
12713         wait->wait.func = do_rps_boost;
12714         wait->wait.flags = 0;
12715
12716         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
12717 }
12718
12719 /**
12720  * intel_prepare_plane_fb - Prepare fb for usage on plane
12721  * @plane: drm plane to prepare for
12722  * @fb: framebuffer to prepare for presentation
12723  *
12724  * Prepares a framebuffer for usage on a display plane.  Generally this
12725  * involves pinning the underlying object and updating the frontbuffer tracking
12726  * bits.  Some older platforms need special physical address handling for
12727  * cursor planes.
12728  *
12729  * Must be called with struct_mutex held.
12730  *
12731  * Returns 0 on success, negative error code on failure.
12732  */
12733 int
12734 intel_prepare_plane_fb(struct drm_plane *plane,
12735                        struct drm_plane_state *new_state)
12736 {
12737         struct intel_atomic_state *intel_state =
12738                 to_intel_atomic_state(new_state->state);
12739         struct drm_i915_private *dev_priv = to_i915(plane->dev);
12740         struct drm_framebuffer *fb = new_state->fb;
12741         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12742         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
12743         int ret;
12744
12745         if (old_obj) {
12746                 struct drm_crtc_state *crtc_state =
12747                         drm_atomic_get_existing_crtc_state(new_state->state,
12748                                                            plane->state->crtc);
12749
12750                 /* Big Hammer, we also need to ensure that any pending
12751                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
12752                  * current scanout is retired before unpinning the old
12753                  * framebuffer. Note that we rely on userspace rendering
12754                  * into the buffer attached to the pipe they are waiting
12755                  * on. If not, userspace generates a GPU hang with IPEHR
12756                  * point to the MI_WAIT_FOR_EVENT.
12757                  *
12758                  * This should only fail upon a hung GPU, in which case we
12759                  * can safely continue.
12760                  */
12761                 if (needs_modeset(crtc_state)) {
12762                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12763                                                               old_obj->resv, NULL,
12764                                                               false, 0,
12765                                                               GFP_KERNEL);
12766                         if (ret < 0)
12767                                 return ret;
12768                 }
12769         }
12770
12771         if (new_state->fence) { /* explicit fencing */
12772                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
12773                                                     new_state->fence,
12774                                                     I915_FENCE_TIMEOUT,
12775                                                     GFP_KERNEL);
12776                 if (ret < 0)
12777                         return ret;
12778         }
12779
12780         if (!obj)
12781                 return 0;
12782
12783         ret = i915_gem_object_pin_pages(obj);
12784         if (ret)
12785                 return ret;
12786
12787         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
12788         if (ret) {
12789                 i915_gem_object_unpin_pages(obj);
12790                 return ret;
12791         }
12792
12793         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12794             INTEL_INFO(dev_priv)->cursor_needs_physical) {
12795                 const int align = intel_cursor_alignment(dev_priv);
12796
12797                 ret = i915_gem_object_attach_phys(obj, align);
12798         } else {
12799                 struct i915_vma *vma;
12800
12801                 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
12802                 if (!IS_ERR(vma))
12803                         to_intel_plane_state(new_state)->vma = vma;
12804                 else
12805                         ret =  PTR_ERR(vma);
12806         }
12807
12808         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
12809
12810         mutex_unlock(&dev_priv->drm.struct_mutex);
12811         i915_gem_object_unpin_pages(obj);
12812         if (ret)
12813                 return ret;
12814
12815         if (!new_state->fence) { /* implicit fencing */
12816                 struct dma_fence *fence;
12817
12818                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
12819                                                       obj->resv, NULL,
12820                                                       false, I915_FENCE_TIMEOUT,
12821                                                       GFP_KERNEL);
12822                 if (ret < 0)
12823                         return ret;
12824
12825                 fence = reservation_object_get_excl_rcu(obj->resv);
12826                 if (fence) {
12827                         add_rps_boost_after_vblank(new_state->crtc, fence);
12828                         dma_fence_put(fence);
12829                 }
12830         } else {
12831                 add_rps_boost_after_vblank(new_state->crtc, new_state->fence);
12832         }
12833
12834         return 0;
12835 }
12836
12837 /**
12838  * intel_cleanup_plane_fb - Cleans up an fb after plane use
12839  * @plane: drm plane to clean up for
12840  * @fb: old framebuffer that was on plane
12841  *
12842  * Cleans up a framebuffer that has just been removed from a plane.
12843  *
12844  * Must be called with struct_mutex held.
12845  */
12846 void
12847 intel_cleanup_plane_fb(struct drm_plane *plane,
12848                        struct drm_plane_state *old_state)
12849 {
12850         struct i915_vma *vma;
12851
12852         /* Should only be called after a successful intel_prepare_plane_fb()! */
12853         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
12854         if (vma) {
12855                 mutex_lock(&plane->dev->struct_mutex);
12856                 intel_unpin_fb_vma(vma);
12857                 mutex_unlock(&plane->dev->struct_mutex);
12858         }
12859 }
12860
12861 int
12862 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12863 {
12864         struct drm_i915_private *dev_priv;
12865         int max_scale;
12866         int crtc_clock, max_dotclk;
12867
12868         if (!intel_crtc || !crtc_state->base.enable)
12869                 return DRM_PLANE_HELPER_NO_SCALING;
12870
12871         dev_priv = to_i915(intel_crtc->base.dev);
12872
12873         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12874         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
12875
12876         if (IS_GEMINILAKE(dev_priv))
12877                 max_dotclk *= 2;
12878
12879         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
12880                 return DRM_PLANE_HELPER_NO_SCALING;
12881
12882         /*
12883          * skl max scale is lower of:
12884          *    close to 3 but not 3, -1 is for that purpose
12885          *            or
12886          *    cdclk/crtc_clock
12887          */
12888         max_scale = min((1 << 16) * 3 - 1,
12889                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
12890
12891         return max_scale;
12892 }
12893
12894 static int
12895 intel_check_primary_plane(struct intel_plane *plane,
12896                           struct intel_crtc_state *crtc_state,
12897                           struct intel_plane_state *state)
12898 {
12899         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
12900         struct drm_crtc *crtc = state->base.crtc;
12901         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
12902         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
12903         bool can_position = false;
12904         int ret;
12905
12906         if (INTEL_GEN(dev_priv) >= 9) {
12907                 /* use scaler when colorkey is not required */
12908                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
12909                         min_scale = 1;
12910                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
12911                 }
12912                 can_position = true;
12913         }
12914
12915         ret = drm_plane_helper_check_state(&state->base,
12916                                            &state->clip,
12917                                            min_scale, max_scale,
12918                                            can_position, true);
12919         if (ret)
12920                 return ret;
12921
12922         if (!state->base.fb)
12923                 return 0;
12924
12925         if (INTEL_GEN(dev_priv) >= 9) {
12926                 ret = skl_check_plane_surface(state);
12927                 if (ret)
12928                         return ret;
12929
12930                 state->ctl = skl_plane_ctl(crtc_state, state);
12931         } else {
12932                 ret = i9xx_check_plane_surface(state);
12933                 if (ret)
12934                         return ret;
12935
12936                 state->ctl = i9xx_plane_ctl(crtc_state, state);
12937         }
12938
12939         return 0;
12940 }
12941
12942 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
12943                                     struct drm_crtc_state *old_crtc_state)
12944 {
12945         struct drm_device *dev = crtc->dev;
12946         struct drm_i915_private *dev_priv = to_i915(dev);
12947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12948         struct intel_crtc_state *old_intel_cstate =
12949                 to_intel_crtc_state(old_crtc_state);
12950         struct intel_atomic_state *old_intel_state =
12951                 to_intel_atomic_state(old_crtc_state->state);
12952         struct intel_crtc_state *intel_cstate =
12953                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12954         bool modeset = needs_modeset(&intel_cstate->base);
12955
12956         if (!modeset &&
12957             (intel_cstate->base.color_mgmt_changed ||
12958              intel_cstate->update_pipe)) {
12959                 intel_color_set_csc(&intel_cstate->base);
12960                 intel_color_load_luts(&intel_cstate->base);
12961         }
12962
12963         /* Perform vblank evasion around commit operation */
12964         intel_pipe_update_start(intel_cstate);
12965
12966         if (modeset)
12967                 goto out;
12968
12969         if (intel_cstate->update_pipe)
12970                 intel_update_pipe_config(old_intel_cstate, intel_cstate);
12971         else if (INTEL_GEN(dev_priv) >= 9)
12972                 skl_detach_scalers(intel_crtc);
12973
12974 out:
12975         if (dev_priv->display.atomic_update_watermarks)
12976                 dev_priv->display.atomic_update_watermarks(old_intel_state,
12977                                                            intel_cstate);
12978 }
12979
12980 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
12981                                      struct drm_crtc_state *old_crtc_state)
12982 {
12983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12984         struct intel_atomic_state *old_intel_state =
12985                 to_intel_atomic_state(old_crtc_state->state);
12986         struct intel_crtc_state *new_crtc_state =
12987                 intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
12988
12989         intel_pipe_update_end(new_crtc_state);
12990 }
12991
12992 /**
12993  * intel_plane_destroy - destroy a plane
12994  * @plane: plane to destroy
12995  *
12996  * Common destruction function for all types of planes (primary, cursor,
12997  * sprite).
12998  */
12999 void intel_plane_destroy(struct drm_plane *plane)
13000 {
13001         drm_plane_cleanup(plane);
13002         kfree(to_intel_plane(plane));
13003 }
13004
13005 static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
13006 {
13007         switch (format) {
13008         case DRM_FORMAT_C8:
13009         case DRM_FORMAT_RGB565:
13010         case DRM_FORMAT_XRGB1555:
13011         case DRM_FORMAT_XRGB8888:
13012                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13013                         modifier == I915_FORMAT_MOD_X_TILED;
13014         default:
13015                 return false;
13016         }
13017 }
13018
13019 static bool i965_mod_supported(uint32_t format, uint64_t modifier)
13020 {
13021         switch (format) {
13022         case DRM_FORMAT_C8:
13023         case DRM_FORMAT_RGB565:
13024         case DRM_FORMAT_XRGB8888:
13025         case DRM_FORMAT_XBGR8888:
13026         case DRM_FORMAT_XRGB2101010:
13027         case DRM_FORMAT_XBGR2101010:
13028                 return modifier == DRM_FORMAT_MOD_LINEAR ||
13029                         modifier == I915_FORMAT_MOD_X_TILED;
13030         default:
13031                 return false;
13032         }
13033 }
13034
13035 static bool skl_mod_supported(uint32_t format, uint64_t modifier)
13036 {
13037         switch (format) {
13038         case DRM_FORMAT_XRGB8888:
13039         case DRM_FORMAT_XBGR8888:
13040         case DRM_FORMAT_ARGB8888:
13041         case DRM_FORMAT_ABGR8888:
13042                 if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
13043                     modifier == I915_FORMAT_MOD_Y_TILED_CCS)
13044                         return true;
13045                 /* fall through */
13046         case DRM_FORMAT_RGB565:
13047         case DRM_FORMAT_XRGB2101010:
13048         case DRM_FORMAT_XBGR2101010:
13049         case DRM_FORMAT_YUYV:
13050         case DRM_FORMAT_YVYU:
13051         case DRM_FORMAT_UYVY:
13052         case DRM_FORMAT_VYUY:
13053                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
13054                         return true;
13055                 /* fall through */
13056         case DRM_FORMAT_C8:
13057                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
13058                     modifier == I915_FORMAT_MOD_X_TILED ||
13059                     modifier == I915_FORMAT_MOD_Y_TILED)
13060                         return true;
13061                 /* fall through */
13062         default:
13063                 return false;
13064         }
13065 }
13066
13067 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
13068                                                      uint32_t format,
13069                                                      uint64_t modifier)
13070 {
13071         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13072
13073         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13074                 return false;
13075
13076         if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
13077             modifier != DRM_FORMAT_MOD_LINEAR)
13078                 return false;
13079
13080         if (INTEL_GEN(dev_priv) >= 9)
13081                 return skl_mod_supported(format, modifier);
13082         else if (INTEL_GEN(dev_priv) >= 4)
13083                 return i965_mod_supported(format, modifier);
13084         else
13085                 return i8xx_mod_supported(format, modifier);
13086
13087         unreachable();
13088 }
13089
13090 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
13091                                                     uint32_t format,
13092                                                     uint64_t modifier)
13093 {
13094         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
13095                 return false;
13096
13097         return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888;
13098 }
13099
13100 static struct drm_plane_funcs intel_plane_funcs = {
13101         .update_plane = drm_atomic_helper_update_plane,
13102         .disable_plane = drm_atomic_helper_disable_plane,
13103         .destroy = intel_plane_destroy,
13104         .atomic_get_property = intel_plane_atomic_get_property,
13105         .atomic_set_property = intel_plane_atomic_set_property,
13106         .atomic_duplicate_state = intel_plane_duplicate_state,
13107         .atomic_destroy_state = intel_plane_destroy_state,
13108         .format_mod_supported = intel_primary_plane_format_mod_supported,
13109 };
13110
13111 static int
13112 intel_legacy_cursor_update(struct drm_plane *plane,
13113                            struct drm_crtc *crtc,
13114                            struct drm_framebuffer *fb,
13115                            int crtc_x, int crtc_y,
13116                            unsigned int crtc_w, unsigned int crtc_h,
13117                            uint32_t src_x, uint32_t src_y,
13118                            uint32_t src_w, uint32_t src_h,
13119                            struct drm_modeset_acquire_ctx *ctx)
13120 {
13121         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13122         int ret;
13123         struct drm_plane_state *old_plane_state, *new_plane_state;
13124         struct intel_plane *intel_plane = to_intel_plane(plane);
13125         struct drm_framebuffer *old_fb;
13126         struct drm_crtc_state *crtc_state = crtc->state;
13127         struct i915_vma *old_vma, *vma;
13128
13129         /*
13130          * When crtc is inactive or there is a modeset pending,
13131          * wait for it to complete in the slowpath
13132          */
13133         if (!crtc_state->active || needs_modeset(crtc_state) ||
13134             to_intel_crtc_state(crtc_state)->update_pipe)
13135                 goto slow;
13136
13137         old_plane_state = plane->state;
13138
13139         /*
13140          * If any parameters change that may affect watermarks,
13141          * take the slowpath. Only changing fb or position should be
13142          * in the fastpath.
13143          */
13144         if (old_plane_state->crtc != crtc ||
13145             old_plane_state->src_w != src_w ||
13146             old_plane_state->src_h != src_h ||
13147             old_plane_state->crtc_w != crtc_w ||
13148             old_plane_state->crtc_h != crtc_h ||
13149             !old_plane_state->fb != !fb)
13150                 goto slow;
13151
13152         new_plane_state = intel_plane_duplicate_state(plane);
13153         if (!new_plane_state)
13154                 return -ENOMEM;
13155
13156         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13157
13158         new_plane_state->src_x = src_x;
13159         new_plane_state->src_y = src_y;
13160         new_plane_state->src_w = src_w;
13161         new_plane_state->src_h = src_h;
13162         new_plane_state->crtc_x = crtc_x;
13163         new_plane_state->crtc_y = crtc_y;
13164         new_plane_state->crtc_w = crtc_w;
13165         new_plane_state->crtc_h = crtc_h;
13166
13167         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13168                                                   to_intel_crtc_state(crtc->state), /* FIXME need a new crtc state? */
13169                                                   to_intel_plane_state(plane->state),
13170                                                   to_intel_plane_state(new_plane_state));
13171         if (ret)
13172                 goto out_free;
13173
13174         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13175         if (ret)
13176                 goto out_free;
13177
13178         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13179                 int align = intel_cursor_alignment(dev_priv);
13180
13181                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13182                 if (ret) {
13183                         DRM_DEBUG_KMS("failed to attach phys object\n");
13184                         goto out_unlock;
13185                 }
13186         } else {
13187                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13188                 if (IS_ERR(vma)) {
13189                         DRM_DEBUG_KMS("failed to pin object\n");
13190
13191                         ret = PTR_ERR(vma);
13192                         goto out_unlock;
13193                 }
13194
13195                 to_intel_plane_state(new_plane_state)->vma = vma;
13196         }
13197
13198         old_fb = old_plane_state->fb;
13199         old_vma = to_intel_plane_state(old_plane_state)->vma;
13200
13201         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13202                           intel_plane->frontbuffer_bit);
13203
13204         /* Swap plane state */
13205         new_plane_state->fence = old_plane_state->fence;
13206         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13207         new_plane_state->fence = NULL;
13208         new_plane_state->fb = old_fb;
13209         to_intel_plane_state(new_plane_state)->vma = NULL;
13210
13211         if (plane->state->visible) {
13212                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13213                 intel_plane->update_plane(intel_plane,
13214                                           to_intel_crtc_state(crtc->state),
13215                                           to_intel_plane_state(plane->state));
13216         } else {
13217                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13218                 intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc));
13219         }
13220
13221         if (old_vma)
13222                 intel_unpin_fb_vma(old_vma);
13223
13224 out_unlock:
13225         mutex_unlock(&dev_priv->drm.struct_mutex);
13226 out_free:
13227         intel_plane_destroy_state(plane, new_plane_state);
13228         return ret;
13229
13230 slow:
13231         return drm_atomic_helper_update_plane(plane, crtc, fb,
13232                                               crtc_x, crtc_y, crtc_w, crtc_h,
13233                                               src_x, src_y, src_w, src_h, ctx);
13234 }
13235
13236 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13237         .update_plane = intel_legacy_cursor_update,
13238         .disable_plane = drm_atomic_helper_disable_plane,
13239         .destroy = intel_plane_destroy,
13240         .atomic_get_property = intel_plane_atomic_get_property,
13241         .atomic_set_property = intel_plane_atomic_set_property,
13242         .atomic_duplicate_state = intel_plane_duplicate_state,
13243         .atomic_destroy_state = intel_plane_destroy_state,
13244         .format_mod_supported = intel_cursor_plane_format_mod_supported,
13245 };
13246
13247 static struct intel_plane *
13248 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13249 {
13250         struct intel_plane *primary = NULL;
13251         struct intel_plane_state *state = NULL;
13252         const uint32_t *intel_primary_formats;
13253         unsigned int supported_rotations;
13254         unsigned int num_formats;
13255         const uint64_t *modifiers;
13256         int ret;
13257
13258         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13259         if (!primary) {
13260                 ret = -ENOMEM;
13261                 goto fail;
13262         }
13263
13264         state = intel_create_plane_state(&primary->base);
13265         if (!state) {
13266                 ret = -ENOMEM;
13267                 goto fail;
13268         }
13269
13270         primary->base.state = &state->base;
13271
13272         primary->can_scale = false;
13273         primary->max_downscale = 1;
13274         if (INTEL_GEN(dev_priv) >= 9) {
13275                 primary->can_scale = true;
13276                 state->scaler_id = -1;
13277         }
13278         primary->pipe = pipe;
13279         /*
13280          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13281          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13282          */
13283         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13284                 primary->plane = (enum plane) !pipe;
13285         else
13286                 primary->plane = (enum plane) pipe;
13287         primary->id = PLANE_PRIMARY;
13288         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13289         primary->check_plane = intel_check_primary_plane;
13290
13291         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
13292                 intel_primary_formats = skl_primary_formats;
13293                 num_formats = ARRAY_SIZE(skl_primary_formats);
13294                 modifiers = skl_format_modifiers_ccs;
13295
13296                 primary->update_plane = skylake_update_primary_plane;
13297                 primary->disable_plane = skylake_disable_primary_plane;
13298         } else if (INTEL_GEN(dev_priv) >= 9) {
13299                 intel_primary_formats = skl_primary_formats;
13300                 num_formats = ARRAY_SIZE(skl_primary_formats);
13301                 if (pipe < PIPE_C)
13302                         modifiers = skl_format_modifiers_ccs;
13303                 else
13304                         modifiers = skl_format_modifiers_noccs;
13305
13306                 primary->update_plane = skylake_update_primary_plane;
13307                 primary->disable_plane = skylake_disable_primary_plane;
13308         } else if (INTEL_GEN(dev_priv) >= 4) {
13309                 intel_primary_formats = i965_primary_formats;
13310                 num_formats = ARRAY_SIZE(i965_primary_formats);
13311                 modifiers = i9xx_format_modifiers;
13312
13313                 primary->update_plane = i9xx_update_primary_plane;
13314                 primary->disable_plane = i9xx_disable_primary_plane;
13315         } else {
13316                 intel_primary_formats = i8xx_primary_formats;
13317                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13318                 modifiers = i9xx_format_modifiers;
13319
13320                 primary->update_plane = i9xx_update_primary_plane;
13321                 primary->disable_plane = i9xx_disable_primary_plane;
13322         }
13323
13324         if (INTEL_GEN(dev_priv) >= 9)
13325                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13326                                                0, &intel_plane_funcs,
13327                                                intel_primary_formats, num_formats,
13328                                                modifiers,
13329                                                DRM_PLANE_TYPE_PRIMARY,
13330                                                "plane 1%c", pipe_name(pipe));
13331         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13332                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13333                                                0, &intel_plane_funcs,
13334                                                intel_primary_formats, num_formats,
13335                                                modifiers,
13336                                                DRM_PLANE_TYPE_PRIMARY,
13337                                                "primary %c", pipe_name(pipe));
13338         else
13339                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13340                                                0, &intel_plane_funcs,
13341                                                intel_primary_formats, num_formats,
13342                                                modifiers,
13343                                                DRM_PLANE_TYPE_PRIMARY,
13344                                                "plane %c", plane_name(primary->plane));
13345         if (ret)
13346                 goto fail;
13347
13348         if (INTEL_GEN(dev_priv) >= 9) {
13349                 supported_rotations =
13350                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
13351                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
13352         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13353                 supported_rotations =
13354                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
13355                         DRM_MODE_REFLECT_X;
13356         } else if (INTEL_GEN(dev_priv) >= 4) {
13357                 supported_rotations =
13358                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
13359         } else {
13360                 supported_rotations = DRM_MODE_ROTATE_0;
13361         }
13362
13363         if (INTEL_GEN(dev_priv) >= 4)
13364                 drm_plane_create_rotation_property(&primary->base,
13365                                                    DRM_MODE_ROTATE_0,
13366                                                    supported_rotations);
13367
13368         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13369
13370         return primary;
13371
13372 fail:
13373         kfree(state);
13374         kfree(primary);
13375
13376         return ERR_PTR(ret);
13377 }
13378
13379 static struct intel_plane *
13380 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
13381                           enum pipe pipe)
13382 {
13383         struct intel_plane *cursor = NULL;
13384         struct intel_plane_state *state = NULL;
13385         int ret;
13386
13387         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13388         if (!cursor) {
13389                 ret = -ENOMEM;
13390                 goto fail;
13391         }
13392
13393         state = intel_create_plane_state(&cursor->base);
13394         if (!state) {
13395                 ret = -ENOMEM;
13396                 goto fail;
13397         }
13398
13399         cursor->base.state = &state->base;
13400
13401         cursor->can_scale = false;
13402         cursor->max_downscale = 1;
13403         cursor->pipe = pipe;
13404         cursor->plane = pipe;
13405         cursor->id = PLANE_CURSOR;
13406         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13407
13408         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
13409                 cursor->update_plane = i845_update_cursor;
13410                 cursor->disable_plane = i845_disable_cursor;
13411                 cursor->check_plane = i845_check_cursor;
13412         } else {
13413                 cursor->update_plane = i9xx_update_cursor;
13414                 cursor->disable_plane = i9xx_disable_cursor;
13415                 cursor->check_plane = i9xx_check_cursor;
13416         }
13417
13418         cursor->cursor.base = ~0;
13419         cursor->cursor.cntl = ~0;
13420
13421         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
13422                 cursor->cursor.size = ~0;
13423
13424         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13425                                        0, &intel_cursor_plane_funcs,
13426                                        intel_cursor_formats,
13427                                        ARRAY_SIZE(intel_cursor_formats),
13428                                        cursor_format_modifiers,
13429                                        DRM_PLANE_TYPE_CURSOR,
13430                                        "cursor %c", pipe_name(pipe));
13431         if (ret)
13432                 goto fail;
13433
13434         if (INTEL_GEN(dev_priv) >= 4)
13435                 drm_plane_create_rotation_property(&cursor->base,
13436                                                    DRM_MODE_ROTATE_0,
13437                                                    DRM_MODE_ROTATE_0 |
13438                                                    DRM_MODE_ROTATE_180);
13439
13440         if (INTEL_GEN(dev_priv) >= 9)
13441                 state->scaler_id = -1;
13442
13443         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13444
13445         return cursor;
13446
13447 fail:
13448         kfree(state);
13449         kfree(cursor);
13450
13451         return ERR_PTR(ret);
13452 }
13453
13454 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13455                                     struct intel_crtc_state *crtc_state)
13456 {
13457         struct intel_crtc_scaler_state *scaler_state =
13458                 &crtc_state->scaler_state;
13459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13460         int i;
13461
13462         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13463         if (!crtc->num_scalers)
13464                 return;
13465
13466         for (i = 0; i < crtc->num_scalers; i++) {
13467                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13468
13469                 scaler->in_use = 0;
13470                 scaler->mode = PS_SCALER_MODE_DYN;
13471         }
13472
13473         scaler_state->scaler_id = -1;
13474 }
13475
13476 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13477 {
13478         struct intel_crtc *intel_crtc;
13479         struct intel_crtc_state *crtc_state = NULL;
13480         struct intel_plane *primary = NULL;
13481         struct intel_plane *cursor = NULL;
13482         int sprite, ret;
13483
13484         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13485         if (!intel_crtc)
13486                 return -ENOMEM;
13487
13488         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13489         if (!crtc_state) {
13490                 ret = -ENOMEM;
13491                 goto fail;
13492         }
13493         intel_crtc->config = crtc_state;
13494         intel_crtc->base.state = &crtc_state->base;
13495         crtc_state->base.crtc = &intel_crtc->base;
13496
13497         primary = intel_primary_plane_create(dev_priv, pipe);
13498         if (IS_ERR(primary)) {
13499                 ret = PTR_ERR(primary);
13500                 goto fail;
13501         }
13502         intel_crtc->plane_ids_mask |= BIT(primary->id);
13503
13504         for_each_sprite(dev_priv, pipe, sprite) {
13505                 struct intel_plane *plane;
13506
13507                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13508                 if (IS_ERR(plane)) {
13509                         ret = PTR_ERR(plane);
13510                         goto fail;
13511                 }
13512                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13513         }
13514
13515         cursor = intel_cursor_plane_create(dev_priv, pipe);
13516         if (IS_ERR(cursor)) {
13517                 ret = PTR_ERR(cursor);
13518                 goto fail;
13519         }
13520         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13521
13522         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13523                                         &primary->base, &cursor->base,
13524                                         &intel_crtc_funcs,
13525                                         "pipe %c", pipe_name(pipe));
13526         if (ret)
13527                 goto fail;
13528
13529         intel_crtc->pipe = pipe;
13530         intel_crtc->plane = primary->plane;
13531
13532         /* initialize shared scalers */
13533         intel_crtc_init_scalers(intel_crtc, crtc_state);
13534
13535         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13536                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13537         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13538         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13539
13540         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13541
13542         intel_color_init(&intel_crtc->base);
13543
13544         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13545
13546         return 0;
13547
13548 fail:
13549         /*
13550          * drm_mode_config_cleanup() will free up any
13551          * crtcs/planes already initialized.
13552          */
13553         kfree(crtc_state);
13554         kfree(intel_crtc);
13555
13556         return ret;
13557 }
13558
13559 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13560 {
13561         struct drm_device *dev = connector->base.dev;
13562
13563         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13564
13565         if (!connector->base.state->crtc)
13566                 return INVALID_PIPE;
13567
13568         return to_intel_crtc(connector->base.state->crtc)->pipe;
13569 }
13570
13571 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13572                                 struct drm_file *file)
13573 {
13574         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13575         struct drm_crtc *drmmode_crtc;
13576         struct intel_crtc *crtc;
13577
13578         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13579         if (!drmmode_crtc)
13580                 return -ENOENT;
13581
13582         crtc = to_intel_crtc(drmmode_crtc);
13583         pipe_from_crtc_id->pipe = crtc->pipe;
13584
13585         return 0;
13586 }
13587
13588 static int intel_encoder_clones(struct intel_encoder *encoder)
13589 {
13590         struct drm_device *dev = encoder->base.dev;
13591         struct intel_encoder *source_encoder;
13592         int index_mask = 0;
13593         int entry = 0;
13594
13595         for_each_intel_encoder(dev, source_encoder) {
13596                 if (encoders_cloneable(encoder, source_encoder))
13597                         index_mask |= (1 << entry);
13598
13599                 entry++;
13600         }
13601
13602         return index_mask;
13603 }
13604
13605 static bool has_edp_a(struct drm_i915_private *dev_priv)
13606 {
13607         if (!IS_MOBILE(dev_priv))
13608                 return false;
13609
13610         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13611                 return false;
13612
13613         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13614                 return false;
13615
13616         return true;
13617 }
13618
13619 static bool intel_crt_present(struct drm_i915_private *dev_priv)
13620 {
13621         if (INTEL_GEN(dev_priv) >= 9)
13622                 return false;
13623
13624         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
13625                 return false;
13626
13627         if (IS_CHERRYVIEW(dev_priv))
13628                 return false;
13629
13630         if (HAS_PCH_LPT_H(dev_priv) &&
13631             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13632                 return false;
13633
13634         /* DDI E can't be used if DDI A requires 4 lanes */
13635         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13636                 return false;
13637
13638         if (!dev_priv->vbt.int_crt_support)
13639                 return false;
13640
13641         return true;
13642 }
13643
13644 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13645 {
13646         int pps_num;
13647         int pps_idx;
13648
13649         if (HAS_DDI(dev_priv))
13650                 return;
13651         /*
13652          * This w/a is needed at least on CPT/PPT, but to be sure apply it
13653          * everywhere where registers can be write protected.
13654          */
13655         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13656                 pps_num = 2;
13657         else
13658                 pps_num = 1;
13659
13660         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
13661                 u32 val = I915_READ(PP_CONTROL(pps_idx));
13662
13663                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
13664                 I915_WRITE(PP_CONTROL(pps_idx), val);
13665         }
13666 }
13667
13668 static void intel_pps_init(struct drm_i915_private *dev_priv)
13669 {
13670         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
13671                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
13672         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13673                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
13674         else
13675                 dev_priv->pps_mmio_base = PPS_BASE;
13676
13677         intel_pps_unlock_regs_wa(dev_priv);
13678 }
13679
13680 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
13681 {
13682         struct intel_encoder *encoder;
13683         bool dpd_is_edp = false;
13684
13685         intel_pps_init(dev_priv);
13686
13687         /*
13688          * intel_edp_init_connector() depends on this completing first, to
13689          * prevent the registeration of both eDP and LVDS and the incorrect
13690          * sharing of the PPS.
13691          */
13692         intel_lvds_init(dev_priv);
13693
13694         if (intel_crt_present(dev_priv))
13695                 intel_crt_init(dev_priv);
13696
13697         if (IS_GEN9_LP(dev_priv)) {
13698                 /*
13699                  * FIXME: Broxton doesn't support port detection via the
13700                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13701                  * detect the ports.
13702                  */
13703                 intel_ddi_init(dev_priv, PORT_A);
13704                 intel_ddi_init(dev_priv, PORT_B);
13705                 intel_ddi_init(dev_priv, PORT_C);
13706
13707                 intel_dsi_init(dev_priv);
13708         } else if (HAS_DDI(dev_priv)) {
13709                 int found;
13710
13711                 /*
13712                  * Haswell uses DDI functions to detect digital outputs.
13713                  * On SKL pre-D0 the strap isn't connected, so we assume
13714                  * it's there.
13715                  */
13716                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13717                 /* WaIgnoreDDIAStrap: skl */
13718                 if (found || IS_GEN9_BC(dev_priv))
13719                         intel_ddi_init(dev_priv, PORT_A);
13720
13721                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13722                  * register */
13723                 found = I915_READ(SFUSE_STRAP);
13724
13725                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13726                         intel_ddi_init(dev_priv, PORT_B);
13727                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13728                         intel_ddi_init(dev_priv, PORT_C);
13729                 if (found & SFUSE_STRAP_DDID_DETECTED)
13730                         intel_ddi_init(dev_priv, PORT_D);
13731                 /*
13732                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13733                  */
13734                 if (IS_GEN9_BC(dev_priv) &&
13735                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13736                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13737                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13738                         intel_ddi_init(dev_priv, PORT_E);
13739
13740         } else if (HAS_PCH_SPLIT(dev_priv)) {
13741                 int found;
13742                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
13743
13744                 if (has_edp_a(dev_priv))
13745                         intel_dp_init(dev_priv, DP_A, PORT_A);
13746
13747                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13748                         /* PCH SDVOB multiplex with HDMIB */
13749                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
13750                         if (!found)
13751                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
13752                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13753                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
13754                 }
13755
13756                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13757                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
13758
13759                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13760                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
13761
13762                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13763                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
13764
13765                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13766                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
13767         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13768                 bool has_edp, has_port;
13769
13770                 /*
13771                  * The DP_DETECTED bit is the latched state of the DDC
13772                  * SDA pin at boot. However since eDP doesn't require DDC
13773                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13774                  * eDP ports may have been muxed to an alternate function.
13775                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13776                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13777                  * detect eDP ports.
13778                  *
13779                  * Sadly the straps seem to be missing sometimes even for HDMI
13780                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
13781                  * and VBT for the presence of the port. Additionally we can't
13782                  * trust the port type the VBT declares as we've seen at least
13783                  * HDMI ports that the VBT claim are DP or eDP.
13784                  */
13785                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
13786                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
13787                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
13788                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
13789                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
13790                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
13791
13792                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
13793                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
13794                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
13795                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
13796                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
13797                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
13798
13799                 if (IS_CHERRYVIEW(dev_priv)) {
13800                         /*
13801                          * eDP not supported on port D,
13802                          * so no need to worry about it
13803                          */
13804                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
13805                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
13806                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
13807                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
13808                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
13809                 }
13810
13811                 intel_dsi_init(dev_priv);
13812         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
13813                 bool found = false;
13814
13815                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13816                         DRM_DEBUG_KMS("probing SDVOB\n");
13817                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
13818                         if (!found && IS_G4X(dev_priv)) {
13819                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13820                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
13821                         }
13822
13823                         if (!found && IS_G4X(dev_priv))
13824                                 intel_dp_init(dev_priv, DP_B, PORT_B);
13825                 }
13826
13827                 /* Before G4X SDVOC doesn't have its own detect register */
13828
13829                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13830                         DRM_DEBUG_KMS("probing SDVOC\n");
13831                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
13832                 }
13833
13834                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13835
13836                         if (IS_G4X(dev_priv)) {
13837                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13838                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
13839                         }
13840                         if (IS_G4X(dev_priv))
13841                                 intel_dp_init(dev_priv, DP_C, PORT_C);
13842                 }
13843
13844                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
13845                         intel_dp_init(dev_priv, DP_D, PORT_D);
13846         } else if (IS_GEN2(dev_priv))
13847                 intel_dvo_init(dev_priv);
13848
13849         if (SUPPORTS_TV(dev_priv))
13850                 intel_tv_init(dev_priv);
13851
13852         intel_psr_init(dev_priv);
13853
13854         for_each_intel_encoder(&dev_priv->drm, encoder) {
13855                 encoder->base.possible_crtcs = encoder->crtc_mask;
13856                 encoder->base.possible_clones =
13857                         intel_encoder_clones(encoder);
13858         }
13859
13860         intel_init_pch_refclk(dev_priv);
13861
13862         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
13863 }
13864
13865 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13866 {
13867         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13868
13869         drm_framebuffer_cleanup(fb);
13870
13871         i915_gem_object_lock(intel_fb->obj);
13872         WARN_ON(!intel_fb->obj->framebuffer_references--);
13873         i915_gem_object_unlock(intel_fb->obj);
13874
13875         i915_gem_object_put(intel_fb->obj);
13876
13877         kfree(intel_fb);
13878 }
13879
13880 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13881                                                 struct drm_file *file,
13882                                                 unsigned int *handle)
13883 {
13884         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13885         struct drm_i915_gem_object *obj = intel_fb->obj;
13886
13887         if (obj->userptr.mm) {
13888                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
13889                 return -EINVAL;
13890         }
13891
13892         return drm_gem_handle_create(file, &obj->base, handle);
13893 }
13894
13895 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
13896                                         struct drm_file *file,
13897                                         unsigned flags, unsigned color,
13898                                         struct drm_clip_rect *clips,
13899                                         unsigned num_clips)
13900 {
13901         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13902
13903         i915_gem_object_flush_if_display(obj);
13904         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
13905
13906         return 0;
13907 }
13908
13909 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13910         .destroy = intel_user_framebuffer_destroy,
13911         .create_handle = intel_user_framebuffer_create_handle,
13912         .dirty = intel_user_framebuffer_dirty,
13913 };
13914
13915 static
13916 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
13917                          uint64_t fb_modifier, uint32_t pixel_format)
13918 {
13919         u32 gen = INTEL_GEN(dev_priv);
13920
13921         if (gen >= 9) {
13922                 int cpp = drm_format_plane_cpp(pixel_format, 0);
13923
13924                 /* "The stride in bytes must not exceed the of the size of 8K
13925                  *  pixels and 32K bytes."
13926                  */
13927                 return min(8192 * cpp, 32768);
13928         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
13929                 return 32*1024;
13930         } else if (gen >= 4) {
13931                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13932                         return 16*1024;
13933                 else
13934                         return 32*1024;
13935         } else if (gen >= 3) {
13936                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13937                         return 8*1024;
13938                 else
13939                         return 16*1024;
13940         } else {
13941                 /* XXX DSPC is limited to 4k tiled */
13942                 return 8*1024;
13943         }
13944 }
13945
13946 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
13947                                   struct drm_i915_gem_object *obj,
13948                                   struct drm_mode_fb_cmd2 *mode_cmd)
13949 {
13950         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
13951         struct drm_framebuffer *fb = &intel_fb->base;
13952         struct drm_format_name_buf format_name;
13953         u32 pitch_limit;
13954         unsigned int tiling, stride;
13955         int ret = -EINVAL;
13956         int i;
13957
13958         i915_gem_object_lock(obj);
13959         obj->framebuffer_references++;
13960         tiling = i915_gem_object_get_tiling(obj);
13961         stride = i915_gem_object_get_stride(obj);
13962         i915_gem_object_unlock(obj);
13963
13964         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13965                 /*
13966                  * If there's a fence, enforce that
13967                  * the fb modifier and tiling mode match.
13968                  */
13969                 if (tiling != I915_TILING_NONE &&
13970                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
13971                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
13972                         goto err;
13973                 }
13974         } else {
13975                 if (tiling == I915_TILING_X) {
13976                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13977                 } else if (tiling == I915_TILING_Y) {
13978                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
13979                         goto err;
13980                 }
13981         }
13982
13983         /* Passed in modifier sanity checking. */
13984         switch (mode_cmd->modifier[0]) {
13985         case I915_FORMAT_MOD_Y_TILED_CCS:
13986         case I915_FORMAT_MOD_Yf_TILED_CCS:
13987                 switch (mode_cmd->pixel_format) {
13988                 case DRM_FORMAT_XBGR8888:
13989                 case DRM_FORMAT_ABGR8888:
13990                 case DRM_FORMAT_XRGB8888:
13991                 case DRM_FORMAT_ARGB8888:
13992                         break;
13993                 default:
13994                         DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n");
13995                         goto err;
13996                 }
13997                 /* fall through */
13998         case I915_FORMAT_MOD_Y_TILED:
13999         case I915_FORMAT_MOD_Yf_TILED:
14000                 if (INTEL_GEN(dev_priv) < 9) {
14001                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14002                                       mode_cmd->modifier[0]);
14003                         goto err;
14004                 }
14005         case DRM_FORMAT_MOD_LINEAR:
14006         case I915_FORMAT_MOD_X_TILED:
14007                 break;
14008         default:
14009                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14010                               mode_cmd->modifier[0]);
14011                 goto err;
14012         }
14013
14014         /*
14015          * gen2/3 display engine uses the fence if present,
14016          * so the tiling mode must match the fb modifier exactly.
14017          */
14018         if (INTEL_INFO(dev_priv)->gen < 4 &&
14019             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14020                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14021                 goto err;
14022         }
14023
14024         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14025                                            mode_cmd->pixel_format);
14026         if (mode_cmd->pitches[0] > pitch_limit) {
14027                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14028                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
14029                               "tiled" : "linear",
14030                               mode_cmd->pitches[0], pitch_limit);
14031                 goto err;
14032         }
14033
14034         /*
14035          * If there's a fence, enforce that
14036          * the fb pitch and fence stride match.
14037          */
14038         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14039                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14040                               mode_cmd->pitches[0], stride);
14041                 goto err;
14042         }
14043
14044         /* Reject formats not supported by any plane early. */
14045         switch (mode_cmd->pixel_format) {
14046         case DRM_FORMAT_C8:
14047         case DRM_FORMAT_RGB565:
14048         case DRM_FORMAT_XRGB8888:
14049         case DRM_FORMAT_ARGB8888:
14050                 break;
14051         case DRM_FORMAT_XRGB1555:
14052                 if (INTEL_GEN(dev_priv) > 3) {
14053                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14054                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14055                         goto err;
14056                 }
14057                 break;
14058         case DRM_FORMAT_ABGR8888:
14059                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14060                     INTEL_GEN(dev_priv) < 9) {
14061                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14062                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14063                         goto err;
14064                 }
14065                 break;
14066         case DRM_FORMAT_XBGR8888:
14067         case DRM_FORMAT_XRGB2101010:
14068         case DRM_FORMAT_XBGR2101010:
14069                 if (INTEL_GEN(dev_priv) < 4) {
14070                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14071                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14072                         goto err;
14073                 }
14074                 break;
14075         case DRM_FORMAT_ABGR2101010:
14076                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14077                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14078                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14079                         goto err;
14080                 }
14081                 break;
14082         case DRM_FORMAT_YUYV:
14083         case DRM_FORMAT_UYVY:
14084         case DRM_FORMAT_YVYU:
14085         case DRM_FORMAT_VYUY:
14086                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
14087                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14088                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14089                         goto err;
14090                 }
14091                 break;
14092         default:
14093                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14094                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14095                 goto err;
14096         }
14097
14098         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14099         if (mode_cmd->offsets[0] != 0)
14100                 goto err;
14101
14102         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
14103
14104         for (i = 0; i < fb->format->num_planes; i++) {
14105                 u32 stride_alignment;
14106
14107                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
14108                         DRM_DEBUG_KMS("bad plane %d handle\n", i);
14109                         goto err;
14110                 }
14111
14112                 stride_alignment = intel_fb_stride_alignment(fb, i);
14113
14114                 /*
14115                  * Display WA #0531: skl,bxt,kbl,glk
14116                  *
14117                  * Render decompression and plane width > 3840
14118                  * combined with horizontal panning requires the
14119                  * plane stride to be a multiple of 4. We'll just
14120                  * require the entire fb to accommodate that to avoid
14121                  * potential runtime errors at plane configuration time.
14122                  */
14123                 if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 &&
14124                     (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
14125                      fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
14126                         stride_alignment *= 4;
14127
14128                 if (fb->pitches[i] & (stride_alignment - 1)) {
14129                         DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
14130                                       i, fb->pitches[i], stride_alignment);
14131                         goto err;
14132                 }
14133         }
14134
14135         intel_fb->obj = obj;
14136
14137         ret = intel_fill_fb_info(dev_priv, fb);
14138         if (ret)
14139                 goto err;
14140
14141         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
14142         if (ret) {
14143                 DRM_ERROR("framebuffer init failed %d\n", ret);
14144                 goto err;
14145         }
14146
14147         return 0;
14148
14149 err:
14150         i915_gem_object_lock(obj);
14151         obj->framebuffer_references--;
14152         i915_gem_object_unlock(obj);
14153         return ret;
14154 }
14155
14156 static struct drm_framebuffer *
14157 intel_user_framebuffer_create(struct drm_device *dev,
14158                               struct drm_file *filp,
14159                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14160 {
14161         struct drm_framebuffer *fb;
14162         struct drm_i915_gem_object *obj;
14163         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14164
14165         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14166         if (!obj)
14167                 return ERR_PTR(-ENOENT);
14168
14169         fb = intel_framebuffer_create(obj, &mode_cmd);
14170         if (IS_ERR(fb))
14171                 i915_gem_object_put(obj);
14172
14173         return fb;
14174 }
14175
14176 static void intel_atomic_state_free(struct drm_atomic_state *state)
14177 {
14178         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14179
14180         drm_atomic_state_default_release(state);
14181
14182         i915_sw_fence_fini(&intel_state->commit_ready);
14183
14184         kfree(state);
14185 }
14186
14187 static const struct drm_mode_config_funcs intel_mode_funcs = {
14188         .fb_create = intel_user_framebuffer_create,
14189         .get_format_info = intel_get_format_info,
14190         .output_poll_changed = intel_fbdev_output_poll_changed,
14191         .atomic_check = intel_atomic_check,
14192         .atomic_commit = intel_atomic_commit,
14193         .atomic_state_alloc = intel_atomic_state_alloc,
14194         .atomic_state_clear = intel_atomic_state_clear,
14195         .atomic_state_free = intel_atomic_state_free,
14196 };
14197
14198 /**
14199  * intel_init_display_hooks - initialize the display modesetting hooks
14200  * @dev_priv: device private
14201  */
14202 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14203 {
14204         intel_init_cdclk_hooks(dev_priv);
14205
14206         if (INTEL_INFO(dev_priv)->gen >= 9) {
14207                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14208                 dev_priv->display.get_initial_plane_config =
14209                         skylake_get_initial_plane_config;
14210                 dev_priv->display.crtc_compute_clock =
14211                         haswell_crtc_compute_clock;
14212                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14213                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14214         } else if (HAS_DDI(dev_priv)) {
14215                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14216                 dev_priv->display.get_initial_plane_config =
14217                         ironlake_get_initial_plane_config;
14218                 dev_priv->display.crtc_compute_clock =
14219                         haswell_crtc_compute_clock;
14220                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14221                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14222         } else if (HAS_PCH_SPLIT(dev_priv)) {
14223                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14224                 dev_priv->display.get_initial_plane_config =
14225                         ironlake_get_initial_plane_config;
14226                 dev_priv->display.crtc_compute_clock =
14227                         ironlake_crtc_compute_clock;
14228                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14229                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14230         } else if (IS_CHERRYVIEW(dev_priv)) {
14231                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14232                 dev_priv->display.get_initial_plane_config =
14233                         i9xx_get_initial_plane_config;
14234                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14235                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14236                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14237         } else if (IS_VALLEYVIEW(dev_priv)) {
14238                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14239                 dev_priv->display.get_initial_plane_config =
14240                         i9xx_get_initial_plane_config;
14241                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14242                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14243                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14244         } else if (IS_G4X(dev_priv)) {
14245                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14246                 dev_priv->display.get_initial_plane_config =
14247                         i9xx_get_initial_plane_config;
14248                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14249                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14250                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14251         } else if (IS_PINEVIEW(dev_priv)) {
14252                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14253                 dev_priv->display.get_initial_plane_config =
14254                         i9xx_get_initial_plane_config;
14255                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14256                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14257                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14258         } else if (!IS_GEN2(dev_priv)) {
14259                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14260                 dev_priv->display.get_initial_plane_config =
14261                         i9xx_get_initial_plane_config;
14262                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14263                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14264                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14265         } else {
14266                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14267                 dev_priv->display.get_initial_plane_config =
14268                         i9xx_get_initial_plane_config;
14269                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14270                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14271                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14272         }
14273
14274         if (IS_GEN5(dev_priv)) {
14275                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14276         } else if (IS_GEN6(dev_priv)) {
14277                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14278         } else if (IS_IVYBRIDGE(dev_priv)) {
14279                 /* FIXME: detect B0+ stepping and use auto training */
14280                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14281         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14282                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14283         }
14284
14285         if (dev_priv->info.gen >= 9)
14286                 dev_priv->display.update_crtcs = skl_update_crtcs;
14287         else
14288                 dev_priv->display.update_crtcs = intel_update_crtcs;
14289 }
14290
14291 /*
14292  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14293  */
14294 static void quirk_ssc_force_disable(struct drm_device *dev)
14295 {
14296         struct drm_i915_private *dev_priv = to_i915(dev);
14297         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14298         DRM_INFO("applying lvds SSC disable quirk\n");
14299 }
14300
14301 /*
14302  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14303  * brightness value
14304  */
14305 static void quirk_invert_brightness(struct drm_device *dev)
14306 {
14307         struct drm_i915_private *dev_priv = to_i915(dev);
14308         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14309         DRM_INFO("applying inverted panel brightness quirk\n");
14310 }
14311
14312 /* Some VBT's incorrectly indicate no backlight is present */
14313 static void quirk_backlight_present(struct drm_device *dev)
14314 {
14315         struct drm_i915_private *dev_priv = to_i915(dev);
14316         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14317         DRM_INFO("applying backlight present quirk\n");
14318 }
14319
14320 /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms
14321  * which is 300 ms greater than eDP spec T12 min.
14322  */
14323 static void quirk_increase_t12_delay(struct drm_device *dev)
14324 {
14325         struct drm_i915_private *dev_priv = to_i915(dev);
14326
14327         dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY;
14328         DRM_INFO("Applying T12 delay quirk\n");
14329 }
14330
14331 struct intel_quirk {
14332         int device;
14333         int subsystem_vendor;
14334         int subsystem_device;
14335         void (*hook)(struct drm_device *dev);
14336 };
14337
14338 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14339 struct intel_dmi_quirk {
14340         void (*hook)(struct drm_device *dev);
14341         const struct dmi_system_id (*dmi_id_list)[];
14342 };
14343
14344 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14345 {
14346         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14347         return 1;
14348 }
14349
14350 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14351         {
14352                 .dmi_id_list = &(const struct dmi_system_id[]) {
14353                         {
14354                                 .callback = intel_dmi_reverse_brightness,
14355                                 .ident = "NCR Corporation",
14356                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14357                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14358                                 },
14359                         },
14360                         { }  /* terminating entry */
14361                 },
14362                 .hook = quirk_invert_brightness,
14363         },
14364 };
14365
14366 static struct intel_quirk intel_quirks[] = {
14367         /* Lenovo U160 cannot use SSC on LVDS */
14368         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14369
14370         /* Sony Vaio Y cannot use SSC on LVDS */
14371         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14372
14373         /* Acer Aspire 5734Z must invert backlight brightness */
14374         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14375
14376         /* Acer/eMachines G725 */
14377         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14378
14379         /* Acer/eMachines e725 */
14380         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14381
14382         /* Acer/Packard Bell NCL20 */
14383         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14384
14385         /* Acer Aspire 4736Z */
14386         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14387
14388         /* Acer Aspire 5336 */
14389         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14390
14391         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14392         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14393
14394         /* Acer C720 Chromebook (Core i3 4005U) */
14395         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14396
14397         /* Apple Macbook 2,1 (Core 2 T7400) */
14398         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14399
14400         /* Apple Macbook 4,1 */
14401         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14402
14403         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14404         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14405
14406         /* HP Chromebook 14 (Celeron 2955U) */
14407         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14408
14409         /* Dell Chromebook 11 */
14410         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14411
14412         /* Dell Chromebook 11 (2015 version) */
14413         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14414
14415         /* Toshiba Satellite P50-C-18C */
14416         { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay },
14417 };
14418
14419 static void intel_init_quirks(struct drm_device *dev)
14420 {
14421         struct pci_dev *d = dev->pdev;
14422         int i;
14423
14424         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14425                 struct intel_quirk *q = &intel_quirks[i];
14426
14427                 if (d->device == q->device &&
14428                     (d->subsystem_vendor == q->subsystem_vendor ||
14429                      q->subsystem_vendor == PCI_ANY_ID) &&
14430                     (d->subsystem_device == q->subsystem_device ||
14431                      q->subsystem_device == PCI_ANY_ID))
14432                         q->hook(dev);
14433         }
14434         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14435                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14436                         intel_dmi_quirks[i].hook(dev);
14437         }
14438 }
14439
14440 /* Disable the VGA plane that we never use */
14441 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14442 {
14443         struct pci_dev *pdev = dev_priv->drm.pdev;
14444         u8 sr1;
14445         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14446
14447         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14448         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14449         outb(SR01, VGA_SR_INDEX);
14450         sr1 = inb(VGA_SR_DATA);
14451         outb(sr1 | 1<<5, VGA_SR_DATA);
14452         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14453         udelay(300);
14454
14455         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14456         POSTING_READ(vga_reg);
14457 }
14458
14459 void intel_modeset_init_hw(struct drm_device *dev)
14460 {
14461         struct drm_i915_private *dev_priv = to_i915(dev);
14462
14463         intel_update_cdclk(dev_priv);
14464         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14465
14466         intel_init_clock_gating(dev_priv);
14467 }
14468
14469 /*
14470  * Calculate what we think the watermarks should be for the state we've read
14471  * out of the hardware and then immediately program those watermarks so that
14472  * we ensure the hardware settings match our internal state.
14473  *
14474  * We can calculate what we think WM's should be by creating a duplicate of the
14475  * current state (which was constructed during hardware readout) and running it
14476  * through the atomic check code to calculate new watermark values in the
14477  * state object.
14478  */
14479 static void sanitize_watermarks(struct drm_device *dev)
14480 {
14481         struct drm_i915_private *dev_priv = to_i915(dev);
14482         struct drm_atomic_state *state;
14483         struct intel_atomic_state *intel_state;
14484         struct drm_crtc *crtc;
14485         struct drm_crtc_state *cstate;
14486         struct drm_modeset_acquire_ctx ctx;
14487         int ret;
14488         int i;
14489
14490         /* Only supported on platforms that use atomic watermark design */
14491         if (!dev_priv->display.optimize_watermarks)
14492                 return;
14493
14494         /*
14495          * We need to hold connection_mutex before calling duplicate_state so
14496          * that the connector loop is protected.
14497          */
14498         drm_modeset_acquire_init(&ctx, 0);
14499 retry:
14500         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14501         if (ret == -EDEADLK) {
14502                 drm_modeset_backoff(&ctx);
14503                 goto retry;
14504         } else if (WARN_ON(ret)) {
14505                 goto fail;
14506         }
14507
14508         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14509         if (WARN_ON(IS_ERR(state)))
14510                 goto fail;
14511
14512         intel_state = to_intel_atomic_state(state);
14513
14514         /*
14515          * Hardware readout is the only time we don't want to calculate
14516          * intermediate watermarks (since we don't trust the current
14517          * watermarks).
14518          */
14519         if (!HAS_GMCH_DISPLAY(dev_priv))
14520                 intel_state->skip_intermediate_wm = true;
14521
14522         ret = intel_atomic_check(dev, state);
14523         if (ret) {
14524                 /*
14525                  * If we fail here, it means that the hardware appears to be
14526                  * programmed in a way that shouldn't be possible, given our
14527                  * understanding of watermark requirements.  This might mean a
14528                  * mistake in the hardware readout code or a mistake in the
14529                  * watermark calculations for a given platform.  Raise a WARN
14530                  * so that this is noticeable.
14531                  *
14532                  * If this actually happens, we'll have to just leave the
14533                  * BIOS-programmed watermarks untouched and hope for the best.
14534                  */
14535                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14536                 goto put_state;
14537         }
14538
14539         /* Write calculated watermark values back */
14540         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14541                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14542
14543                 cs->wm.need_postvbl_update = true;
14544                 dev_priv->display.optimize_watermarks(intel_state, cs);
14545         }
14546
14547 put_state:
14548         drm_atomic_state_put(state);
14549 fail:
14550         drm_modeset_drop_locks(&ctx);
14551         drm_modeset_acquire_fini(&ctx);
14552 }
14553
14554 int intel_modeset_init(struct drm_device *dev)
14555 {
14556         struct drm_i915_private *dev_priv = to_i915(dev);
14557         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14558         enum pipe pipe;
14559         struct intel_crtc *crtc;
14560
14561         drm_mode_config_init(dev);
14562
14563         dev->mode_config.min_width = 0;
14564         dev->mode_config.min_height = 0;
14565
14566         dev->mode_config.preferred_depth = 24;
14567         dev->mode_config.prefer_shadow = 1;
14568
14569         dev->mode_config.allow_fb_modifiers = true;
14570
14571         dev->mode_config.funcs = &intel_mode_funcs;
14572
14573         init_llist_head(&dev_priv->atomic_helper.free_list);
14574         INIT_WORK(&dev_priv->atomic_helper.free_work,
14575                   intel_atomic_helper_free_state_worker);
14576
14577         intel_init_quirks(dev);
14578
14579         intel_init_pm(dev_priv);
14580
14581         if (INTEL_INFO(dev_priv)->num_pipes == 0)
14582                 return 0;
14583
14584         /*
14585          * There may be no VBT; and if the BIOS enabled SSC we can
14586          * just keep using it to avoid unnecessary flicker.  Whereas if the
14587          * BIOS isn't using it, don't assume it will work even if the VBT
14588          * indicates as much.
14589          */
14590         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
14591                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14592                                             DREF_SSC1_ENABLE);
14593
14594                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14595                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14596                                      bios_lvds_use_ssc ? "en" : "dis",
14597                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14598                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14599                 }
14600         }
14601
14602         if (IS_GEN2(dev_priv)) {
14603                 dev->mode_config.max_width = 2048;
14604                 dev->mode_config.max_height = 2048;
14605         } else if (IS_GEN3(dev_priv)) {
14606                 dev->mode_config.max_width = 4096;
14607                 dev->mode_config.max_height = 4096;
14608         } else {
14609                 dev->mode_config.max_width = 8192;
14610                 dev->mode_config.max_height = 8192;
14611         }
14612
14613         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14614                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
14615                 dev->mode_config.cursor_height = 1023;
14616         } else if (IS_GEN2(dev_priv)) {
14617                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14618                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14619         } else {
14620                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14621                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14622         }
14623
14624         dev->mode_config.fb_base = ggtt->mappable_base;
14625
14626         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14627                       INTEL_INFO(dev_priv)->num_pipes,
14628                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
14629
14630         for_each_pipe(dev_priv, pipe) {
14631                 int ret;
14632
14633                 ret = intel_crtc_init(dev_priv, pipe);
14634                 if (ret) {
14635                         drm_mode_config_cleanup(dev);
14636                         return ret;
14637                 }
14638         }
14639
14640         intel_shared_dpll_init(dev);
14641
14642         intel_update_czclk(dev_priv);
14643         intel_modeset_init_hw(dev);
14644
14645         if (dev_priv->max_cdclk_freq == 0)
14646                 intel_update_max_cdclk(dev_priv);
14647
14648         /* Just disable it once at startup */
14649         i915_disable_vga(dev_priv);
14650         intel_setup_outputs(dev_priv);
14651
14652         drm_modeset_lock_all(dev);
14653         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
14654         drm_modeset_unlock_all(dev);
14655
14656         for_each_intel_crtc(dev, crtc) {
14657                 struct intel_initial_plane_config plane_config = {};
14658
14659                 if (!crtc->active)
14660                         continue;
14661
14662                 /*
14663                  * Note that reserving the BIOS fb up front prevents us
14664                  * from stuffing other stolen allocations like the ring
14665                  * on top.  This prevents some ugliness at boot time, and
14666                  * can even allow for smooth boot transitions if the BIOS
14667                  * fb is large enough for the active pipe configuration.
14668                  */
14669                 dev_priv->display.get_initial_plane_config(crtc,
14670                                                            &plane_config);
14671
14672                 /*
14673                  * If the fb is shared between multiple heads, we'll
14674                  * just get the first one.
14675                  */
14676                 intel_find_initial_plane_obj(crtc, &plane_config);
14677         }
14678
14679         /*
14680          * Make sure hardware watermarks really match the state we read out.
14681          * Note that we need to do this after reconstructing the BIOS fb's
14682          * since the watermark calculation done here will use pstate->fb.
14683          */
14684         if (!HAS_GMCH_DISPLAY(dev_priv))
14685                 sanitize_watermarks(dev);
14686
14687         return 0;
14688 }
14689
14690 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14691 {
14692         /* 640x480@60Hz, ~25175 kHz */
14693         struct dpll clock = {
14694                 .m1 = 18,
14695                 .m2 = 7,
14696                 .p1 = 13,
14697                 .p2 = 4,
14698                 .n = 2,
14699         };
14700         u32 dpll, fp;
14701         int i;
14702
14703         WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);
14704
14705         DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
14706                       pipe_name(pipe), clock.vco, clock.dot);
14707
14708         fp = i9xx_dpll_compute_fp(&clock);
14709         dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
14710                 DPLL_VGA_MODE_DIS |
14711                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
14712                 PLL_P2_DIVIDE_BY_4 |
14713                 PLL_REF_INPUT_DREFCLK |
14714                 DPLL_VCO_ENABLE;
14715
14716         I915_WRITE(FP0(pipe), fp);
14717         I915_WRITE(FP1(pipe), fp);
14718
14719         I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
14720         I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
14721         I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
14722         I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
14723         I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
14724         I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
14725         I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
14726
14727         /*
14728          * Apparently we need to have VGA mode enabled prior to changing
14729          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
14730          * dividers, even though the register value does change.
14731          */
14732         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
14733         I915_WRITE(DPLL(pipe), dpll);
14734
14735         /* Wait for the clocks to stabilize. */
14736         POSTING_READ(DPLL(pipe));
14737         udelay(150);
14738
14739         /* The pixel multiplier can only be updated once the
14740          * DPLL is enabled and the clocks are stable.
14741          *
14742          * So write it again.
14743          */
14744         I915_WRITE(DPLL(pipe), dpll);
14745
14746         /* We do this three times for luck */
14747         for (i = 0; i < 3 ; i++) {
14748                 I915_WRITE(DPLL(pipe), dpll);
14749                 POSTING_READ(DPLL(pipe));
14750                 udelay(150); /* wait for warmup */
14751         }
14752
14753         I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
14754         POSTING_READ(PIPECONF(pipe));
14755 }
14756
14757 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
14758 {
14759         DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
14760                       pipe_name(pipe));
14761
14762         assert_plane_disabled(dev_priv, PLANE_A);
14763         assert_plane_disabled(dev_priv, PLANE_B);
14764
14765         I915_WRITE(PIPECONF(pipe), 0);
14766         POSTING_READ(PIPECONF(pipe));
14767
14768         if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
14769                 DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe));
14770
14771         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
14772         POSTING_READ(DPLL(pipe));
14773 }
14774
14775 static bool
14776 intel_check_plane_mapping(struct intel_crtc *crtc)
14777 {
14778         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14779         u32 val;
14780
14781         if (INTEL_INFO(dev_priv)->num_pipes == 1)
14782                 return true;
14783
14784         val = I915_READ(DSPCNTR(!crtc->plane));
14785
14786         if ((val & DISPLAY_PLANE_ENABLE) &&
14787             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14788                 return false;
14789
14790         return true;
14791 }
14792
14793 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14794 {
14795         struct drm_device *dev = crtc->base.dev;
14796         struct intel_encoder *encoder;
14797
14798         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14799                 return true;
14800
14801         return false;
14802 }
14803
14804 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
14805 {
14806         struct drm_device *dev = encoder->base.dev;
14807         struct intel_connector *connector;
14808
14809         for_each_connector_on_encoder(dev, &encoder->base, connector)
14810                 return connector;
14811
14812         return NULL;
14813 }
14814
14815 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
14816                               enum transcoder pch_transcoder)
14817 {
14818         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
14819                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
14820 }
14821
14822 static void intel_sanitize_crtc(struct intel_crtc *crtc,
14823                                 struct drm_modeset_acquire_ctx *ctx)
14824 {
14825         struct drm_device *dev = crtc->base.dev;
14826         struct drm_i915_private *dev_priv = to_i915(dev);
14827         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
14828
14829         /* Clear any frame start delays used for debugging left by the BIOS */
14830         if (!transcoder_is_dsi(cpu_transcoder)) {
14831                 i915_reg_t reg = PIPECONF(cpu_transcoder);
14832
14833                 I915_WRITE(reg,
14834                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14835         }
14836
14837         /* restore vblank interrupts to correct state */
14838         drm_crtc_vblank_reset(&crtc->base);
14839         if (crtc->active) {
14840                 struct intel_plane *plane;
14841
14842                 drm_crtc_vblank_on(&crtc->base);
14843
14844                 /* Disable everything but the primary plane */
14845                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14846                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14847                                 continue;
14848
14849                         trace_intel_disable_plane(&plane->base, crtc);
14850                         plane->disable_plane(plane, crtc);
14851                 }
14852         }
14853
14854         /* We need to sanitize the plane -> pipe mapping first because this will
14855          * disable the crtc (and hence change the state) if it is wrong. Note
14856          * that gen4+ has a fixed plane -> pipe mapping.  */
14857         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
14858                 bool plane;
14859
14860                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
14861                               crtc->base.base.id, crtc->base.name);
14862
14863                 /* Pipe has the wrong plane attached and the plane is active.
14864                  * Temporarily change the plane mapping and disable everything
14865                  * ...  */
14866                 plane = crtc->plane;
14867                 crtc->base.primary->state->visible = true;
14868                 crtc->plane = !plane;
14869                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14870                 crtc->plane = plane;
14871         }
14872
14873         /* Adjust the state of the output pipe according to whether we
14874          * have active connectors/encoders. */
14875         if (crtc->active && !intel_crtc_has_encoders(crtc))
14876                 intel_crtc_disable_noatomic(&crtc->base, ctx);
14877
14878         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
14879                 /*
14880                  * We start out with underrun reporting disabled to avoid races.
14881                  * For correct bookkeeping mark this on active crtcs.
14882                  *
14883                  * Also on gmch platforms we dont have any hardware bits to
14884                  * disable the underrun reporting. Which means we need to start
14885                  * out with underrun reporting disabled also on inactive pipes,
14886                  * since otherwise we'll complain about the garbage we read when
14887                  * e.g. coming up after runtime pm.
14888                  *
14889                  * No protection against concurrent access is required - at
14890                  * worst a fifo underrun happens which also sets this to false.
14891                  */
14892                 crtc->cpu_fifo_underrun_disabled = true;
14893                 /*
14894                  * We track the PCH trancoder underrun reporting state
14895                  * within the crtc. With crtc for pipe A housing the underrun
14896                  * reporting state for PCH transcoder A, crtc for pipe B housing
14897                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
14898                  * and marking underrun reporting as disabled for the non-existing
14899                  * PCH transcoders B and C would prevent enabling the south
14900                  * error interrupt (see cpt_can_enable_serr_int()).
14901                  */
14902                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
14903                         crtc->pch_fifo_underrun_disabled = true;
14904         }
14905 }
14906
14907 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14908 {
14909         struct intel_connector *connector;
14910
14911         /* We need to check both for a crtc link (meaning that the
14912          * encoder is active and trying to read from a pipe) and the
14913          * pipe itself being active. */
14914         bool has_active_crtc = encoder->base.crtc &&
14915                 to_intel_crtc(encoder->base.crtc)->active;
14916
14917         connector = intel_encoder_find_connector(encoder);
14918         if (connector && !has_active_crtc) {
14919                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14920                               encoder->base.base.id,
14921                               encoder->base.name);
14922
14923                 /* Connector is active, but has no active pipe. This is
14924                  * fallout from our resume register restoring. Disable
14925                  * the encoder manually again. */
14926                 if (encoder->base.crtc) {
14927                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
14928
14929                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14930                                       encoder->base.base.id,
14931                                       encoder->base.name);
14932                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14933                         if (encoder->post_disable)
14934                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
14935                 }
14936                 encoder->base.crtc = NULL;
14937
14938                 /* Inconsistent output/port/pipe state happens presumably due to
14939                  * a bug in one of the get_hw_state functions. Or someplace else
14940                  * in our code, like the register restore mess on resume. Clamp
14941                  * things to off as a safer default. */
14942
14943                 connector->base.dpms = DRM_MODE_DPMS_OFF;
14944                 connector->base.encoder = NULL;
14945         }
14946         /* Enabled encoders without active connectors will be fixed in
14947          * the crtc fixup. */
14948 }
14949
14950 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
14951 {
14952         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14953
14954         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14955                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14956                 i915_disable_vga(dev_priv);
14957         }
14958 }
14959
14960 void i915_redisable_vga(struct drm_i915_private *dev_priv)
14961 {
14962         /* This function can be called both from intel_modeset_setup_hw_state or
14963          * at a very early point in our resume sequence, where the power well
14964          * structures are not yet restored. Since this function is at a very
14965          * paranoid "someone might have enabled VGA while we were not looking"
14966          * level, just check if the power well is enabled instead of trying to
14967          * follow the "don't touch the power well if we don't need it" policy
14968          * the rest of the driver uses. */
14969         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
14970                 return;
14971
14972         i915_redisable_vga_power_on(dev_priv);
14973
14974         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
14975 }
14976
14977 static bool primary_get_hw_state(struct intel_plane *plane)
14978 {
14979         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
14980
14981         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
14982 }
14983
14984 /* FIXME read out full plane state for all planes */
14985 static void readout_plane_state(struct intel_crtc *crtc)
14986 {
14987         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
14988         bool visible;
14989
14990         visible = crtc->active && primary_get_hw_state(primary);
14991
14992         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
14993                                 to_intel_plane_state(primary->base.state),
14994                                 visible);
14995 }
14996
14997 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14998 {
14999         struct drm_i915_private *dev_priv = to_i915(dev);
15000         enum pipe pipe;
15001         struct intel_crtc *crtc;
15002         struct intel_encoder *encoder;
15003         struct intel_connector *connector;
15004         struct drm_connector_list_iter conn_iter;
15005         int i;
15006
15007         dev_priv->active_crtcs = 0;
15008
15009         for_each_intel_crtc(dev, crtc) {
15010                 struct intel_crtc_state *crtc_state =
15011                         to_intel_crtc_state(crtc->base.state);
15012
15013                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15014                 memset(crtc_state, 0, sizeof(*crtc_state));
15015                 crtc_state->base.crtc = &crtc->base;
15016
15017                 crtc_state->base.active = crtc_state->base.enable =
15018                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15019
15020                 crtc->base.enabled = crtc_state->base.enable;
15021                 crtc->active = crtc_state->base.active;
15022
15023                 if (crtc_state->base.active)
15024                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15025
15026                 readout_plane_state(crtc);
15027
15028                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15029                               crtc->base.base.id, crtc->base.name,
15030                               enableddisabled(crtc_state->base.active));
15031         }
15032
15033         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15034                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15035
15036                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15037                                                   &pll->state.hw_state);
15038                 pll->state.crtc_mask = 0;
15039                 for_each_intel_crtc(dev, crtc) {
15040                         struct intel_crtc_state *crtc_state =
15041                                 to_intel_crtc_state(crtc->base.state);
15042
15043                         if (crtc_state->base.active &&
15044                             crtc_state->shared_dpll == pll)
15045                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15046                 }
15047                 pll->active_mask = pll->state.crtc_mask;
15048
15049                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15050                               pll->name, pll->state.crtc_mask, pll->on);
15051         }
15052
15053         for_each_intel_encoder(dev, encoder) {
15054                 pipe = 0;
15055
15056                 if (encoder->get_hw_state(encoder, &pipe)) {
15057                         struct intel_crtc_state *crtc_state;
15058
15059                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15060                         crtc_state = to_intel_crtc_state(crtc->base.state);
15061
15062                         encoder->base.crtc = &crtc->base;
15063                         crtc_state->output_types |= 1 << encoder->type;
15064                         encoder->get_config(encoder, crtc_state);
15065                 } else {
15066                         encoder->base.crtc = NULL;
15067                 }
15068
15069                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15070                               encoder->base.base.id, encoder->base.name,
15071                               enableddisabled(encoder->base.crtc),
15072                               pipe_name(pipe));
15073         }
15074
15075         drm_connector_list_iter_begin(dev, &conn_iter);
15076         for_each_intel_connector_iter(connector, &conn_iter) {
15077                 if (connector->get_hw_state(connector)) {
15078                         connector->base.dpms = DRM_MODE_DPMS_ON;
15079
15080                         encoder = connector->encoder;
15081                         connector->base.encoder = &encoder->base;
15082
15083                         if (encoder->base.crtc &&
15084                             encoder->base.crtc->state->active) {
15085                                 /*
15086                                  * This has to be done during hardware readout
15087                                  * because anything calling .crtc_disable may
15088                                  * rely on the connector_mask being accurate.
15089                                  */
15090                                 encoder->base.crtc->state->connector_mask |=
15091                                         1 << drm_connector_index(&connector->base);
15092                                 encoder->base.crtc->state->encoder_mask |=
15093                                         1 << drm_encoder_index(&encoder->base);
15094                         }
15095
15096                 } else {
15097                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15098                         connector->base.encoder = NULL;
15099                 }
15100                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15101                               connector->base.base.id, connector->base.name,
15102                               enableddisabled(connector->base.encoder));
15103         }
15104         drm_connector_list_iter_end(&conn_iter);
15105
15106         for_each_intel_crtc(dev, crtc) {
15107                 struct intel_crtc_state *crtc_state =
15108                         to_intel_crtc_state(crtc->base.state);
15109                 int min_cdclk = 0;
15110
15111                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15112                 if (crtc_state->base.active) {
15113                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15114                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15115                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15116
15117                         /*
15118                          * The initial mode needs to be set in order to keep
15119                          * the atomic core happy. It wants a valid mode if the
15120                          * crtc's enabled, so we do the above call.
15121                          *
15122                          * But we don't set all the derived state fully, hence
15123                          * set a flag to indicate that a full recalculation is
15124                          * needed on the next commit.
15125                          */
15126                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15127
15128                         intel_crtc_compute_pixel_rate(crtc_state);
15129
15130                         if (dev_priv->display.modeset_calc_cdclk) {
15131                                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
15132                                 if (WARN_ON(min_cdclk < 0))
15133                                         min_cdclk = 0;
15134                         }
15135
15136                         drm_calc_timestamping_constants(&crtc->base,
15137                                                         &crtc_state->base.adjusted_mode);
15138                         update_scanline_offset(crtc);
15139                 }
15140
15141                 dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
15142
15143                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15144         }
15145 }
15146
15147 static void
15148 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15149 {
15150         struct intel_encoder *encoder;
15151
15152         for_each_intel_encoder(&dev_priv->drm, encoder) {
15153                 u64 get_domains;
15154                 enum intel_display_power_domain domain;
15155
15156                 if (!encoder->get_power_domains)
15157                         continue;
15158
15159                 get_domains = encoder->get_power_domains(encoder);
15160                 for_each_power_domain(domain, get_domains)
15161                         intel_display_power_get(dev_priv, domain);
15162         }
15163 }
15164
15165 /* Scan out the current hw modeset state,
15166  * and sanitizes it to the current state
15167  */
15168 static void
15169 intel_modeset_setup_hw_state(struct drm_device *dev,
15170                              struct drm_modeset_acquire_ctx *ctx)
15171 {
15172         struct drm_i915_private *dev_priv = to_i915(dev);
15173         enum pipe pipe;
15174         struct intel_crtc *crtc;
15175         struct intel_encoder *encoder;
15176         int i;
15177
15178         intel_modeset_readout_hw_state(dev);
15179
15180         /* HW state is read out, now we need to sanitize this mess. */
15181         get_encoder_power_domains(dev_priv);
15182
15183         for_each_intel_encoder(dev, encoder) {
15184                 intel_sanitize_encoder(encoder);
15185         }
15186
15187         for_each_pipe(dev_priv, pipe) {
15188                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15189
15190                 intel_sanitize_crtc(crtc, ctx);
15191                 intel_dump_pipe_config(crtc, crtc->config,
15192                                        "[setup_hw_state]");
15193         }
15194
15195         intel_modeset_update_connector_atomic_state(dev);
15196
15197         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15198                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15199
15200                 if (!pll->on || pll->active_mask)
15201                         continue;
15202
15203                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15204
15205                 pll->funcs.disable(dev_priv, pll);
15206                 pll->on = false;
15207         }
15208
15209         if (IS_G4X(dev_priv)) {
15210                 g4x_wm_get_hw_state(dev);
15211                 g4x_wm_sanitize(dev_priv);
15212         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15213                 vlv_wm_get_hw_state(dev);
15214                 vlv_wm_sanitize(dev_priv);
15215         } else if (INTEL_GEN(dev_priv) >= 9) {
15216                 skl_wm_get_hw_state(dev);
15217         } else if (HAS_PCH_SPLIT(dev_priv)) {
15218                 ilk_wm_get_hw_state(dev);
15219         }
15220
15221         for_each_intel_crtc(dev, crtc) {
15222                 u64 put_domains;
15223
15224                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15225                 if (WARN_ON(put_domains))
15226                         modeset_put_power_domains(dev_priv, put_domains);
15227         }
15228         intel_display_set_init_power(dev_priv, false);
15229
15230         intel_power_domains_verify_state(dev_priv);
15231
15232         intel_fbc_init_pipe_state(dev_priv);
15233 }
15234
15235 void intel_display_resume(struct drm_device *dev)
15236 {
15237         struct drm_i915_private *dev_priv = to_i915(dev);
15238         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15239         struct drm_modeset_acquire_ctx ctx;
15240         int ret;
15241
15242         dev_priv->modeset_restore_state = NULL;
15243         if (state)
15244                 state->acquire_ctx = &ctx;
15245
15246         drm_modeset_acquire_init(&ctx, 0);
15247
15248         while (1) {
15249                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15250                 if (ret != -EDEADLK)
15251                         break;
15252
15253                 drm_modeset_backoff(&ctx);
15254         }
15255
15256         if (!ret)
15257                 ret = __intel_display_resume(dev, state, &ctx);
15258
15259         intel_enable_ipc(dev_priv);
15260         drm_modeset_drop_locks(&ctx);
15261         drm_modeset_acquire_fini(&ctx);
15262
15263         if (ret)
15264                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15265         if (state)
15266                 drm_atomic_state_put(state);
15267 }
15268
15269 void intel_modeset_gem_init(struct drm_device *dev)
15270 {
15271         struct drm_i915_private *dev_priv = to_i915(dev);
15272
15273         intel_init_gt_powersave(dev_priv);
15274
15275         intel_setup_overlay(dev_priv);
15276 }
15277
15278 int intel_connector_register(struct drm_connector *connector)
15279 {
15280         struct intel_connector *intel_connector = to_intel_connector(connector);
15281         int ret;
15282
15283         ret = intel_backlight_device_register(intel_connector);
15284         if (ret)
15285                 goto err;
15286
15287         return 0;
15288
15289 err:
15290         return ret;
15291 }
15292
15293 void intel_connector_unregister(struct drm_connector *connector)
15294 {
15295         struct intel_connector *intel_connector = to_intel_connector(connector);
15296
15297         intel_backlight_device_unregister(intel_connector);
15298         intel_panel_destroy_backlight(connector);
15299 }
15300
15301 void intel_modeset_cleanup(struct drm_device *dev)
15302 {
15303         struct drm_i915_private *dev_priv = to_i915(dev);
15304
15305         flush_work(&dev_priv->atomic_helper.free_work);
15306         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15307
15308         intel_disable_gt_powersave(dev_priv);
15309
15310         /*
15311          * Interrupts and polling as the first thing to avoid creating havoc.
15312          * Too much stuff here (turning of connectors, ...) would
15313          * experience fancy races otherwise.
15314          */
15315         intel_irq_uninstall(dev_priv);
15316
15317         /*
15318          * Due to the hpd irq storm handling the hotplug work can re-arm the
15319          * poll handlers. Hence disable polling after hpd handling is shut down.
15320          */
15321         drm_kms_helper_poll_fini(dev);
15322
15323         /* poll work can call into fbdev, hence clean that up afterwards */
15324         intel_fbdev_fini(dev_priv);
15325
15326         intel_unregister_dsm_handler();
15327
15328         intel_fbc_global_disable(dev_priv);
15329
15330         /* flush any delayed tasks or pending work */
15331         flush_scheduled_work();
15332
15333         drm_mode_config_cleanup(dev);
15334
15335         intel_cleanup_overlay(dev_priv);
15336
15337         intel_cleanup_gt_powersave(dev_priv);
15338
15339         intel_teardown_gmbus(dev_priv);
15340 }
15341
15342 void intel_connector_attach_encoder(struct intel_connector *connector,
15343                                     struct intel_encoder *encoder)
15344 {
15345         connector->encoder = encoder;
15346         drm_mode_connector_attach_encoder(&connector->base,
15347                                           &encoder->base);
15348 }
15349
15350 /*
15351  * set vga decode state - true == enable VGA decode
15352  */
15353 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15354 {
15355         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15356         u16 gmch_ctrl;
15357
15358         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15359                 DRM_ERROR("failed to read control word\n");
15360                 return -EIO;
15361         }
15362
15363         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15364                 return 0;
15365
15366         if (state)
15367                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15368         else
15369                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15370
15371         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15372                 DRM_ERROR("failed to write control word\n");
15373                 return -EIO;
15374         }
15375
15376         return 0;
15377 }
15378
15379 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15380
15381 struct intel_display_error_state {
15382
15383         u32 power_well_driver;
15384
15385         int num_transcoders;
15386
15387         struct intel_cursor_error_state {
15388                 u32 control;
15389                 u32 position;
15390                 u32 base;
15391                 u32 size;
15392         } cursor[I915_MAX_PIPES];
15393
15394         struct intel_pipe_error_state {
15395                 bool power_domain_on;
15396                 u32 source;
15397                 u32 stat;
15398         } pipe[I915_MAX_PIPES];
15399
15400         struct intel_plane_error_state {
15401                 u32 control;
15402                 u32 stride;
15403                 u32 size;
15404                 u32 pos;
15405                 u32 addr;
15406                 u32 surface;
15407                 u32 tile_offset;
15408         } plane[I915_MAX_PIPES];
15409
15410         struct intel_transcoder_error_state {
15411                 bool power_domain_on;
15412                 enum transcoder cpu_transcoder;
15413
15414                 u32 conf;
15415
15416                 u32 htotal;
15417                 u32 hblank;
15418                 u32 hsync;
15419                 u32 vtotal;
15420                 u32 vblank;
15421                 u32 vsync;
15422         } transcoder[4];
15423 };
15424
15425 struct intel_display_error_state *
15426 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15427 {
15428         struct intel_display_error_state *error;
15429         int transcoders[] = {
15430                 TRANSCODER_A,
15431                 TRANSCODER_B,
15432                 TRANSCODER_C,
15433                 TRANSCODER_EDP,
15434         };
15435         int i;
15436
15437         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15438                 return NULL;
15439
15440         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15441         if (error == NULL)
15442                 return NULL;
15443
15444         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15445                 error->power_well_driver =
15446                         I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL));
15447
15448         for_each_pipe(dev_priv, i) {
15449                 error->pipe[i].power_domain_on =
15450                         __intel_display_power_is_enabled(dev_priv,
15451                                                          POWER_DOMAIN_PIPE(i));
15452                 if (!error->pipe[i].power_domain_on)
15453                         continue;
15454
15455                 error->cursor[i].control = I915_READ(CURCNTR(i));
15456                 error->cursor[i].position = I915_READ(CURPOS(i));
15457                 error->cursor[i].base = I915_READ(CURBASE(i));
15458
15459                 error->plane[i].control = I915_READ(DSPCNTR(i));
15460                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15461                 if (INTEL_GEN(dev_priv) <= 3) {
15462                         error->plane[i].size = I915_READ(DSPSIZE(i));
15463                         error->plane[i].pos = I915_READ(DSPPOS(i));
15464                 }
15465                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15466                         error->plane[i].addr = I915_READ(DSPADDR(i));
15467                 if (INTEL_GEN(dev_priv) >= 4) {
15468                         error->plane[i].surface = I915_READ(DSPSURF(i));
15469                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15470                 }
15471
15472                 error->pipe[i].source = I915_READ(PIPESRC(i));
15473
15474                 if (HAS_GMCH_DISPLAY(dev_priv))
15475                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15476         }
15477
15478         /* Note: this does not include DSI transcoders. */
15479         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15480         if (HAS_DDI(dev_priv))
15481                 error->num_transcoders++; /* Account for eDP. */
15482
15483         for (i = 0; i < error->num_transcoders; i++) {
15484                 enum transcoder cpu_transcoder = transcoders[i];
15485
15486                 error->transcoder[i].power_domain_on =
15487                         __intel_display_power_is_enabled(dev_priv,
15488                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15489                 if (!error->transcoder[i].power_domain_on)
15490                         continue;
15491
15492                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15493
15494                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15495                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15496                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15497                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15498                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15499                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15500                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15501         }
15502
15503         return error;
15504 }
15505
15506 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15507
15508 void
15509 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15510                                 struct intel_display_error_state *error)
15511 {
15512         struct drm_i915_private *dev_priv = m->i915;
15513         int i;
15514
15515         if (!error)
15516                 return;
15517
15518         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15519         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15520                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15521                            error->power_well_driver);
15522         for_each_pipe(dev_priv, i) {
15523                 err_printf(m, "Pipe [%d]:\n", i);
15524                 err_printf(m, "  Power: %s\n",
15525                            onoff(error->pipe[i].power_domain_on));
15526                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15527                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15528
15529                 err_printf(m, "Plane [%d]:\n", i);
15530                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15531                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15532                 if (INTEL_GEN(dev_priv) <= 3) {
15533                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15534                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15535                 }
15536                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15537                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15538                 if (INTEL_GEN(dev_priv) >= 4) {
15539                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15540                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15541                 }
15542
15543                 err_printf(m, "Cursor [%d]:\n", i);
15544                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15545                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15546                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15547         }
15548
15549         for (i = 0; i < error->num_transcoders; i++) {
15550                 err_printf(m, "CPU transcoder: %s\n",
15551                            transcoder_name(error->transcoder[i].cpu_transcoder));
15552                 err_printf(m, "  Power: %s\n",
15553                            onoff(error->transcoder[i].power_domain_on));
15554                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15555                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15556                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15557                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15558                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15559                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15560                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15561         }
15562 }
15563
15564 #endif