drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 8, .max = 18 },
 172         .m2 = { .min = 3, .max = 7 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 420
 421         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 422                 DRM_ERROR("DPIO idle wait timed out\n");
 423                 return 0;
 424         }
 425
 426         I915_WRITE(DPIO_REG, reg);
 427         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 428                    DPIO_BYTE);
 429         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 430                 DRM_ERROR("DPIO read wait timed out\n");
 431                 return 0;
 432         }
 433
 434         return I915_READ(DPIO_DATA);
 435 }
 436
 437 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 438                              u32 val)
 439 {
 440         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 441
 442         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 443                 DRM_ERROR("DPIO idle wait timed out\n");
 444                 return;
 445         }
 446
 447         I915_WRITE(DPIO_DATA, val);
 448         I915_WRITE(DPIO_REG, reg);
 449         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 450                    DPIO_BYTE);
 451         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 452                 DRM_ERROR("DPIO write wait timed out\n");
 453 }
 454
 455 static void vlv_init_dpio(struct drm_device *dev)
 456 {
 457         struct drm_i915_private *dev_priv = dev->dev_private;
 458
 459         /* Reset the DPIO config */
 460         I915_WRITE(DPIO_CTL, 0);
 461         POSTING_READ(DPIO_CTL);
 462         I915_WRITE(DPIO_CTL, 1);
 463         POSTING_READ(DPIO_CTL);
 464 }
 465
 466 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 467                                                 int refclk)
 468 {
 469         struct drm_device *dev = crtc->dev;
 470         const intel_limit_t *limit;
 471
 472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 473                 if (intel_is_dual_link_lvds(dev)) {
 474                         /* LVDS dual channel */
 475                         if (refclk == 100000)
 476                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 477                         else
 478                                 limit = &intel_limits_ironlake_dual_lvds;
 479                 } else {
 480                         if (refclk == 100000)
 481                                 limit = &intel_limits_ironlake_single_lvds_100m;
 482                         else
 483                                 limit = &intel_limits_ironlake_single_lvds;
 484                 }
 485         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 486                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 487                 limit = &intel_limits_ironlake_display_port;
 488         else
 489                 limit = &intel_limits_ironlake_dac;
 490
 491         return limit;
 492 }
 493
 494 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         const intel_limit_t *limit;
 498
 499         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 500                 if (intel_is_dual_link_lvds(dev))
 501                         /* LVDS with dual channel */
 502                         limit = &intel_limits_g4x_dual_channel_lvds;
 503                 else
 504                         /* LVDS with dual channel */
 505                         limit = &intel_limits_g4x_single_channel_lvds;
 506         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 507                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 508                 limit = &intel_limits_g4x_hdmi;
 509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 510                 limit = &intel_limits_g4x_sdvo;
 511         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 512                 limit = &intel_limits_g4x_display_port;
 513         } else /* The option is for other outputs */
 514                 limit = &intel_limits_i9xx_sdvo;
 515
 516         return limit;
 517 }
 518
 519 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 520 {
 521         struct drm_device *dev = crtc->dev;
 522         const intel_limit_t *limit;
 523
 524         if (HAS_PCH_SPLIT(dev))
 525                 limit = intel_ironlake_limit(crtc, refclk);
 526         else if (IS_G4X(dev)) {
 527                 limit = intel_g4x_limit(crtc);
 528         } else if (IS_PINEVIEW(dev)) {
 529                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 530                         limit = &intel_limits_pineview_lvds;
 531                 else
 532                         limit = &intel_limits_pineview_sdvo;
 533         } else if (IS_VALLEYVIEW(dev)) {
 534                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 535                         limit = &intel_limits_vlv_dac;
 536                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 537                         limit = &intel_limits_vlv_hdmi;
 538                 else
 539                         limit = &intel_limits_vlv_dp;
 540         } else if (!IS_GEN2(dev)) {
 541                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 542                         limit = &intel_limits_i9xx_lvds;
 543                 else
 544                         limit = &intel_limits_i9xx_sdvo;
 545         } else {
 546                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 547                         limit = &intel_limits_i8xx_lvds;
 548                 else
 549                         limit = &intel_limits_i8xx_dvo;
 550         }
 551         return limit;
 552 }
 553
 554 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 555 static void pineview_clock(int refclk, intel_clock_t *clock)
 556 {
 557         clock->m = clock->m2 + 2;
 558         clock->p = clock->p1 * clock->p2;
 559         clock->vco = refclk * clock->m / clock->n;
 560         clock->dot = clock->vco / clock->p;
 561 }
 562
 563 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 564 {
 565         if (IS_PINEVIEW(dev)) {
 566                 pineview_clock(refclk, clock);
 567                 return;
 568         }
 569         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 570         clock->p = clock->p1 * clock->p2;
 571         clock->vco = refclk * clock->m / (clock->n + 2);
 572         clock->dot = clock->vco / clock->p;
 573 }
 574
 575 /**
 576  * Returns whether any output on the specified pipe is of the specified type
 577  */
 578 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         struct intel_encoder *encoder;
 582
 583         for_each_encoder_on_crtc(dev, crtc, encoder)
 584                 if (encoder->type == type)
 585                         return true;
 586
 587         return false;
 588 }
 589
 590 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 591 /**
 592  * Returns whether the given set of divisors are valid for a given refclk with
 593  * the given connectors.
 594  */
 595
 596 static bool intel_PLL_is_valid(struct drm_device *dev,
 597                                const intel_limit_t *limit,
 598                                const intel_clock_t *clock)
 599 {
 600         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 601                 INTELPllInvalid("p1 out of range\n");
 602         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 603                 INTELPllInvalid("p out of range\n");
 604         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 605                 INTELPllInvalid("m2 out of range\n");
 606         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 607                 INTELPllInvalid("m1 out of range\n");
 608         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 609                 INTELPllInvalid("m1 <= m2\n");
 610         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 611                 INTELPllInvalid("m out of range\n");
 612         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 613                 INTELPllInvalid("n out of range\n");
 614         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 615                 INTELPllInvalid("vco out of range\n");
 616         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 617          * connector, etc., rather than just a single range.
 618          */
 619         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 620                 INTELPllInvalid("dot out of range\n");
 621
 622         return true;
 623 }
 624
 625 static bool
 626 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                     int target, int refclk, intel_clock_t *match_clock,
 628                     intel_clock_t *best_clock)
 629
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int err = target;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 /*
 637                  * For LVDS just rely on its current settings for dual-channel.
 638                  * We haven't figured out how to reliably set up different
 639                  * single/dual channel state, if we even can.
 640                  */
 641                 if (intel_is_dual_link_lvds(dev))
 642                         clock.p2 = limit->p2.p2_fast;
 643                 else
 644                         clock.p2 = limit->p2.p2_slow;
 645         } else {
 646                 if (target < limit->p2.dot_limit)
 647                         clock.p2 = limit->p2.p2_slow;
 648                 else
 649                         clock.p2 = limit->p2.p2_fast;
 650         }
 651
 652         memset(best_clock, 0, sizeof(*best_clock));
 653
 654         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 655              clock.m1++) {
 656                 for (clock.m2 = limit->m2.min;
 657                      clock.m2 <= limit->m2.max; clock.m2++) {
 658                         /* m1 is always 0 in Pineview */
 659                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 660                                 break;
 661                         for (clock.n = limit->n.min;
 662                              clock.n <= limit->n.max; clock.n++) {
 663                                 for (clock.p1 = limit->p1.min;
 664                                         clock.p1 <= limit->p1.max; clock.p1++) {
 665                                         int this_err;
 666
 667                                         intel_clock(dev, refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671                                         if (match_clock &&
 672                                             clock.p != match_clock->p)
 673                                                 continue;
 674
 675                                         this_err = abs(clock.dot - target);
 676                                         if (this_err < err) {
 677                                                 *best_clock = clock;
 678                                                 err = this_err;
 679                                         }
 680                                 }
 681                         }
 682                 }
 683         }
 684
 685         return (err != target);
 686 }
 687
 688 static bool
 689 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 690                         int target, int refclk, intel_clock_t *match_clock,
 691                         intel_clock_t *best_clock)
 692 {
 693         struct drm_device *dev = crtc->dev;
 694         intel_clock_t clock;
 695         int max_n;
 696         bool found;
 697         /* approximately equals target * 0.00585 */
 698         int err_most = (target >> 8) + (target >> 9);
 699         found = false;
 700
 701         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 702                 int lvds_reg;
 703
 704                 if (HAS_PCH_SPLIT(dev))
 705                         lvds_reg = PCH_LVDS;
 706                 else
 707                         lvds_reg = LVDS;
 708                 if (intel_is_dual_link_lvds(dev))
 709                         clock.p2 = limit->p2.p2_fast;
 710                 else
 711                         clock.p2 = limit->p2.p2_slow;
 712         } else {
 713                 if (target < limit->p2.dot_limit)
 714                         clock.p2 = limit->p2.p2_slow;
 715                 else
 716                         clock.p2 = limit->p2.p2_fast;
 717         }
 718
 719         memset(best_clock, 0, sizeof(*best_clock));
 720         max_n = limit->n.max;
 721         /* based on hardware requirement, prefer smaller n to precision */
 722         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 723                 /* based on hardware requirement, prefere larger m1,m2 */
 724                 for (clock.m1 = limit->m1.max;
 725                      clock.m1 >= limit->m1.min; clock.m1--) {
 726                         for (clock.m2 = limit->m2.max;
 727                              clock.m2 >= limit->m2.min; clock.m2--) {
 728                                 for (clock.p1 = limit->p1.max;
 729                                      clock.p1 >= limit->p1.min; clock.p1--) {
 730                                         int this_err;
 731
 732                                         intel_clock(dev, refclk, &clock);
 733                                         if (!intel_PLL_is_valid(dev, limit,
 734                                                                 &clock))
 735                                                 continue;
 736                                         if (match_clock &&
 737                                             clock.p != match_clock->p)
 738                                                 continue;
 739
 740                                         this_err = abs(clock.dot - target);
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                            int target, int refclk, intel_clock_t *match_clock,
 757                            intel_clock_t *best_clock)
 758 {
 759         struct drm_device *dev = crtc->dev;
 760         intel_clock_t clock;
 761
 762         if (target < 200000) {
 763                 clock.n = 1;
 764                 clock.p1 = 2;
 765                 clock.p2 = 10;
 766                 clock.m1 = 12;
 767                 clock.m2 = 9;
 768         } else {
 769                 clock.n = 2;
 770                 clock.p1 = 1;
 771                 clock.p2 = 10;
 772                 clock.m1 = 14;
 773                 clock.m2 = 8;
 774         }
 775         intel_clock(dev, refclk, &clock);
 776         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 777         return true;
 778 }
 779
 780 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 781 static bool
 782 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 783                       int target, int refclk, intel_clock_t *match_clock,
 784                       intel_clock_t *best_clock)
 785 {
 786         intel_clock_t clock;
 787         if (target < 200000) {
 788                 clock.p1 = 2;
 789                 clock.p2 = 10;
 790                 clock.n = 2;
 791                 clock.m1 = 23;
 792                 clock.m2 = 8;
 793         } else {
 794                 clock.p1 = 1;
 795                 clock.p2 = 10;
 796                 clock.n = 1;
 797                 clock.m1 = 14;
 798                 clock.m2 = 2;
 799         }
 800         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 801         clock.p = (clock.p1 * clock.p2);
 802         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 803         clock.vco = 0;
 804         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 805         return true;
 806 }
 807 static bool
 808 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 809                         int target, int refclk, intel_clock_t *match_clock,
 810                         intel_clock_t *best_clock)
 811 {
 812         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 813         u32 m, n, fastclk;
 814         u32 updrate, minupdate, fracbits, p;
 815         unsigned long bestppm, ppm, absppm;
 816         int dotclk, flag;
 817
 818         flag = 0;
 819         dotclk = target * 1000;
 820         bestppm = 1000000;
 821         ppm = absppm = 0;
 822         fastclk = dotclk / (2*100);
 823         updrate = 0;
 824         minupdate = 19200;
 825         fracbits = 1;
 826         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 827         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 828
 829         /* based on hardware requirement, prefer smaller n to precision */
 830         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 831                 updrate = refclk / n;
 832                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 833                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 834                                 if (p2 > 10)
 835                                         p2 = p2 - 1;
 836                                 p = p1 * p2;
 837                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 838                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 839                                         m2 = (((2*(fastclk * p * n / m1 )) +
 840                                                refclk) / (2*refclk));
 841                                         m = m1 * m2;
 842                                         vco = updrate * m;
 843                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 844                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 845                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 846                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 847                                                         bestppm = 0;
 848                                                         flag = 1;
 849                                                 }
 850                                                 if (absppm < bestppm - 10) {
 851                                                         bestppm = absppm;
 852                                                         flag = 1;
 853                                                 }
 854                                                 if (flag) {
 855                                                         bestn = n;
 856                                                         bestm1 = m1;
 857                                                         bestm2 = m2;
 858                                                         bestp1 = p1;
 859                                                         bestp2 = p2;
 860                                                         flag = 0;
 861                                                 }
 862                                         }
 863                                 }
 864                         }
 865                 }
 866         }
 867         best_clock->n = bestn;
 868         best_clock->m1 = bestm1;
 869         best_clock->m2 = bestm2;
 870         best_clock->p1 = bestp1;
 871         best_clock->p2 = bestp2;
 872
 873         return true;
 874 }
 875
 876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 877                                              enum pipe pipe)
 878 {
 879         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 881
 882         return intel_crtc->cpu_transcoder;
 883 }
 884
 885 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 886 {
 887         struct drm_i915_private *dev_priv = dev->dev_private;
 888         u32 frame, frame_reg = PIPEFRAME(pipe);
 889
 890         frame = I915_READ(frame_reg);
 891
 892         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 /**
 897  * intel_wait_for_vblank - wait for vblank on a given pipe
 898  * @dev: drm device
 899  * @pipe: pipe to wait for
 900  *
 901  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 902  * mode setting code.
 903  */
 904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 905 {
 906         struct drm_i915_private *dev_priv = dev->dev_private;
 907         int pipestat_reg = PIPESTAT(pipe);
 908
 909         if (INTEL_INFO(dev)->gen >= 5) {
 910                 ironlake_wait_for_vblank(dev, pipe);
 911                 return;
 912         }
 913
 914         /* Clear existing vblank status. Note this will clear any other
 915          * sticky status fields as well.
 916          *
 917          * This races with i915_driver_irq_handler() with the result
 918          * that either function could miss a vblank event.  Here it is not
 919          * fatal, as we will either wait upon the next vblank interrupt or
 920          * timeout.  Generally speaking intel_wait_for_vblank() is only
 921          * called during modeset at which time the GPU should be idle and
 922          * should *not* be performing page flips and thus not waiting on
 923          * vblanks...
 924          * Currently, the result of us stealing a vblank from the irq
 925          * handler is that a single frame will be skipped during swapbuffers.
 926          */
 927         I915_WRITE(pipestat_reg,
 928                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 929
 930         /* Wait for vblank interrupt bit to set */
 931         if (wait_for(I915_READ(pipestat_reg) &
 932                      PIPE_VBLANK_INTERRUPT_STATUS,
 933                      50))
 934                 DRM_DEBUG_KMS("vblank wait timed out\n");
 935 }
 936
 937 /*
 938  * intel_wait_for_pipe_off - wait for pipe to turn off
 939  * @dev: drm device
 940  * @pipe: pipe to wait for
 941  *
 942  * After disabling a pipe, we can't wait for vblank in the usual way,
 943  * spinning on the vblank interrupt status bit, since we won't actually
 944  * see an interrupt when the pipe is disabled.
 945  *
 946  * On Gen4 and above:
 947  *   wait for the pipe register state bit to turn off
 948  *
 949  * Otherwise:
 950  *   wait for the display line value to settle (it usually
 951  *   ends up stopping at the start of the next frame).
 952  *
 953  */
 954 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 955 {
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 958                                                                       pipe);
 959
 960         if (INTEL_INFO(dev)->gen >= 4) {
 961                 int reg = PIPECONF(cpu_transcoder);
 962
 963                 /* Wait for the Pipe State to go off */
 964                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 965                              100))
 966                         WARN(1, "pipe_off wait timed out\n");
 967         } else {
 968                 u32 last_line, line_mask;
 969                 int reg = PIPEDSL(pipe);
 970                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 971
 972                 if (IS_GEN2(dev))
 973                         line_mask = DSL_LINEMASK_GEN2;
 974                 else
 975                         line_mask = DSL_LINEMASK_GEN3;
 976
 977                 /* Wait for the display line to settle */
 978                 do {
 979                         last_line = I915_READ(reg) & line_mask;
 980                         mdelay(5);
 981                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 982                          time_after(timeout, jiffies));
 983                 if (time_after(jiffies, timeout))
 984                         WARN(1, "pipe_off wait timed out\n");
 985         }
 986 }
 987
 988 /*
 989  * ibx_digital_port_connected - is the specified port connected?
 990  * @dev_priv: i915 private structure
 991  * @port: the port to test
 992  *
 993  * Returns true if @port is connected, false otherwise.
 994  */
 995 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 996                                 struct intel_digital_port *port)
 997 {
 998         u32 bit;
 999
1000         if (HAS_PCH_IBX(dev_priv->dev)) {
1001                 switch(port->port) {
1002                 case PORT_B:
1003                         bit = SDE_PORTB_HOTPLUG;
1004                         break;
1005                 case PORT_C:
1006                         bit = SDE_PORTC_HOTPLUG;
1007                         break;
1008                 case PORT_D:
1009                         bit = SDE_PORTD_HOTPLUG;
1010                         break;
1011                 default:
1012                         return true;
1013                 }
1014         } else {
1015                 switch(port->port) {
1016                 case PORT_B:
1017                         bit = SDE_PORTB_HOTPLUG_CPT;
1018                         break;
1019                 case PORT_C:
1020                         bit = SDE_PORTC_HOTPLUG_CPT;
1021                         break;
1022                 case PORT_D:
1023                         bit = SDE_PORTD_HOTPLUG_CPT;
1024                         break;
1025                 default:
1026                         return true;
1027                 }
1028         }
1029
1030         return I915_READ(SDEISR) & bit;
1031 }
1032
1033 static const char *state_string(bool enabled)
1034 {
1035         return enabled ? "on" : "off";
1036 }
1037
1038 /* Only for pre-ILK configs */
1039 static void assert_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = DPLL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & DPLL_VCO_ENABLE);
1049         WARN(cur_state != state,
1050              "PLL state assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
1056 /* For ILK+ */
1057 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1058                            struct intel_pch_pll *pll,
1059                            struct intel_crtc *crtc,
1060                            bool state)
1061 {
1062         u32 val;
1063         bool cur_state;
1064
1065         if (HAS_PCH_LPT(dev_priv->dev)) {
1066                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067                 return;
1068         }
1069
1070         if (WARN (!pll,
1071                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072                 return;
1073
1074         val = I915_READ(pll->pll_reg);
1075         cur_state = !!(val & DPLL_VCO_ENABLE);
1076         WARN(cur_state != state,
1077              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078              pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080         /* Make sure the selected PLL is correctly attached to the transcoder */
1081         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082                 u32 pch_dpll;
1083
1084                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1085                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1088                           cur_state, crtc->pipe, pch_dpll)) {
1089                         cur_state = !!(val >> (4*crtc->pipe + 3));
1090                         WARN(cur_state != state,
1091                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1092                              pll->pll_reg == _PCH_DPLL_B,
1093                              state_string(state),
1094                              crtc->pipe,
1095                              val);
1096                 }
1097         }
1098 }
1099 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1101
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103                           enum pipe pipe, bool state)
1104 {
1105         int reg;
1106         u32 val;
1107         bool cur_state;
1108         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109                                                                       pipe);
1110
1111         if (HAS_DDI(dev_priv->dev)) {
1112                 /* DDI does not have a specific FDI_TX register */
1113                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1116         } else {
1117                 reg = FDI_TX_CTL(pipe);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & FDI_TX_ENABLE);
1120         }
1121         WARN(cur_state != state,
1122              "FDI TX state assertion failure (expected %s, current %s)\n",
1123              state_string(state), state_string(cur_state));
1124 }
1125 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129                           enum pipe pipe, bool state)
1130 {
1131         int reg;
1132         u32 val;
1133         bool cur_state;
1134
1135         reg = FDI_RX_CTL(pipe);
1136         val = I915_READ(reg);
1137         cur_state = !!(val & FDI_RX_ENABLE);
1138         WARN(cur_state != state,
1139              "FDI RX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146                                       enum pipe pipe)
1147 {
1148         int reg;
1149         u32 val;
1150
1151         /* ILK FDI PLL is always enabled */
1152         if (dev_priv->info->gen == 5)
1153                 return;
1154
1155         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156         if (HAS_DDI(dev_priv->dev))
1157                 return;
1158
1159         reg = FDI_TX_CTL(pipe);
1160         val = I915_READ(reg);
1161         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162 }
1163
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165                                       enum pipe pipe)
1166 {
1167         int reg;
1168         u32 val;
1169
1170         reg = FDI_RX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176                                   enum pipe pipe)
1177 {
1178         int pp_reg, lvds_reg;
1179         u32 val;
1180         enum pipe panel_pipe = PIPE_A;
1181         bool locked = true;
1182
1183         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184                 pp_reg = PCH_PP_CONTROL;
1185                 lvds_reg = PCH_LVDS;
1186         } else {
1187                 pp_reg = PP_CONTROL;
1188                 lvds_reg = LVDS;
1189         }
1190
1191         val = I915_READ(pp_reg);
1192         if (!(val & PANEL_POWER_ON) ||
1193             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194                 locked = false;
1195
1196         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197                 panel_pipe = PIPE_B;
1198
1199         WARN(panel_pipe == pipe && locked,
1200              "panel assertion failure, pipe %c regs locked\n",
1201              pipe_name(pipe));
1202 }
1203
1204 void assert_pipe(struct drm_i915_private *dev_priv,
1205                  enum pipe pipe, bool state)
1206 {
1207         int reg;
1208         u32 val;
1209         bool cur_state;
1210         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211                                                                       pipe);
1212
1213         /* if we need the pipe A quirk it must be always on */
1214         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215                 state = true;
1216
1217         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219                 cur_state = false;
1220         } else {
1221                 reg = PIPECONF(cpu_transcoder);
1222                 val = I915_READ(reg);
1223                 cur_state = !!(val & PIPECONF_ENABLE);
1224         }
1225
1226         WARN(cur_state != state,
1227              "pipe %c assertion failure (expected %s, current %s)\n",
1228              pipe_name(pipe), state_string(state), state_string(cur_state));
1229 }
1230
1231 static void assert_plane(struct drm_i915_private *dev_priv,
1232                          enum plane plane, bool state)
1233 {
1234         int reg;
1235         u32 val;
1236         bool cur_state;
1237
1238         reg = DSPCNTR(plane);
1239         val = I915_READ(reg);
1240         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241         WARN(cur_state != state,
1242              "plane %c assertion failure (expected %s, current %s)\n",
1243              plane_name(plane), state_string(state), state_string(cur_state));
1244 }
1245
1246 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
1249 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe)
1251 {
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Planes are fixed to pipes on ILK+ */
1257         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN((val & DISPLAY_PLANE_ENABLE),
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for (i = 0; i < 2; i++) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279 {
1280         u32 val;
1281         bool enabled;
1282
1283         if (HAS_PCH_LPT(dev_priv->dev)) {
1284                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285                 return;
1286         }
1287
1288         val = I915_READ(PCH_DREF_CONTROL);
1289         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290                             DREF_SUPERSPREAD_SOURCE_MASK));
1291         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292 }
1293
1294 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                        enum pipe pipe)
1296 {
1297         int reg;
1298         u32 val;
1299         bool enabled;
1300
1301         reg = TRANSCONF(pipe);
1302         val = I915_READ(reg);
1303         enabled = !!(val & TRANS_ENABLE);
1304         WARN(enabled,
1305              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306              pipe_name(pipe));
1307 }
1308
1309 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310                             enum pipe pipe, u32 port_sel, u32 val)
1311 {
1312         if ((val & DP_PORT_EN) == 0)
1313                 return false;
1314
1315         if (HAS_PCH_CPT(dev_priv->dev)) {
1316                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & PORT_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv->dev)) {
1334                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335                         return false;
1336         } else {
1337                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & LVDS_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & ADPA_DAC_ENABLE) == 0)
1363                 return false;
1364         if (HAS_PCH_CPT(dev_priv->dev)) {
1365                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366                         return false;
1367         } else {
1368                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369                         return false;
1370         }
1371         return true;
1372 }
1373
1374 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1375                                    enum pipe pipe, int reg, u32 port_sel)
1376 {
1377         u32 val = I915_READ(reg);
1378         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1379              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1380              reg, pipe_name(pipe));
1381
1382         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383              && (val & DP_PIPEB_SELECT),
1384              "IBX PCH dp port still using transcoder B\n");
1385 }
1386
1387 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388                                      enum pipe pipe, int reg)
1389 {
1390         u32 val = I915_READ(reg);
1391         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1392              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1393              reg, pipe_name(pipe));
1394
1395         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396              && (val & SDVO_PIPE_B_SELECT),
1397              "IBX PCH hdmi port still using transcoder B\n");
1398 }
1399
1400 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401                                       enum pipe pipe)
1402 {
1403         int reg;
1404         u32 val;
1405
1406         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1409
1410         reg = PCH_ADPA;
1411         val = I915_READ(reg);
1412         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1413              "PCH VGA enabled on transcoder %c, should be disabled\n",
1414              pipe_name(pipe));
1415
1416         reg = PCH_LVDS;
1417         val = I915_READ(reg);
1418         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1419              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1420              pipe_name(pipe));
1421
1422         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425 }
1426
1427 /**
1428  * intel_enable_pll - enable a PLL
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe PLL to enable
1431  *
1432  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1433  * make sure the PLL reg is writable first though, since the panel write
1434  * protect mechanism may be enabled.
1435  *
1436  * Note!  This is for pre-ILK only.
1437  *
1438  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1439  */
1440 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441 {
1442         int reg;
1443         u32 val;
1444
1445         /* No really, not for ILK+ */
1446         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1447
1448         /* PLL is protected by panel, make sure we can write it */
1449         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450                 assert_panel_unlocked(dev_priv, pipe);
1451
1452         reg = DPLL(pipe);
1453         val = I915_READ(reg);
1454         val |= DPLL_VCO_ENABLE;
1455
1456         /* We do this three times for luck */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463         I915_WRITE(reg, val);
1464         POSTING_READ(reg);
1465         udelay(150); /* wait for warmup */
1466 }
1467
1468 /**
1469  * intel_disable_pll - disable a PLL
1470  * @dev_priv: i915 private structure
1471  * @pipe: pipe PLL to disable
1472  *
1473  * Disable the PLL for @pipe, making sure the pipe is off first.
1474  *
1475  * Note!  This is for pre-ILK only.
1476  */
1477 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478 {
1479         int reg;
1480         u32 val;
1481
1482         /* Don't disable pipe A or pipe A PLLs if needed */
1483         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484                 return;
1485
1486         /* Make sure the pipe isn't still relying on us */
1487         assert_pipe_disabled(dev_priv, pipe);
1488
1489         reg = DPLL(pipe);
1490         val = I915_READ(reg);
1491         val &= ~DPLL_VCO_ENABLE;
1492         I915_WRITE(reg, val);
1493         POSTING_READ(reg);
1494 }
1495
1496 /* SBI access */
1497 static void
1498 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499                 enum intel_sbi_destination destination)
1500 {
1501         u32 tmp;
1502
1503         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1504
1505         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1506                                 100)) {
1507                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1508                 return;
1509         }
1510
1511         I915_WRITE(SBI_ADDR, (reg << 16));
1512         I915_WRITE(SBI_DATA, value);
1513
1514         if (destination == SBI_ICLK)
1515                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516         else
1517                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1519
1520         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1521                                 100)) {
1522                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1523                 return;
1524         }
1525 }
1526
1527 static u32
1528 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529                enum intel_sbi_destination destination)
1530 {
1531         u32 value = 0;
1532         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1533
1534         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1535                                 100)) {
1536                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1537                 return 0;
1538         }
1539
1540         I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542         if (destination == SBI_ICLK)
1543                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544         else
1545                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1547
1548         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1549                                 100)) {
1550                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1551                 return 0;
1552         }
1553
1554         return I915_READ(SBI_DATA);
1555 }
1556
1557 /**
1558  * ironlake_enable_pch_pll - enable PCH PLL
1559  * @dev_priv: i915 private structure
1560  * @pipe: pipe PLL to enable
1561  *
1562  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563  * drives the transcoder clock.
1564  */
1565 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH PLLs only available on ILK, SNB and IVB */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         pll = intel_crtc->pch_pll;
1575         if (pll == NULL)
1576                 return;
1577
1578         if (WARN_ON(pll->refcount == 0))
1579                 return;
1580
1581         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582                       pll->pll_reg, pll->active, pll->on,
1583                       intel_crtc->base.base.id);
1584
1585         /* PCH refclock must be enabled first */
1586         assert_pch_refclk_enabled(dev_priv);
1587
1588         if (pll->active++ && pll->on) {
1589                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590                 return;
1591         }
1592
1593         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595         reg = pll->pll_reg;
1596         val = I915_READ(reg);
1597         val |= DPLL_VCO_ENABLE;
1598         I915_WRITE(reg, val);
1599         POSTING_READ(reg);
1600         udelay(200);
1601
1602         pll->on = true;
1603 }
1604
1605 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1606 {
1607         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609         int reg;
1610         u32 val;
1611
1612         /* PCH only available on ILK+ */
1613         BUG_ON(dev_priv->info->gen < 5);
1614         if (pll == NULL)
1615                return;
1616
1617         if (WARN_ON(pll->refcount == 0))
1618                 return;
1619
1620         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621                       pll->pll_reg, pll->active, pll->on,
1622                       intel_crtc->base.base.id);
1623
1624         if (WARN_ON(pll->active == 0)) {
1625                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         if (--pll->active) {
1630                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631                 return;
1632         }
1633
1634         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636         /* Make sure transcoder isn't still depending on us */
1637         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1638
1639         reg = pll->pll_reg;
1640         val = I915_READ(reg);
1641         val &= ~DPLL_VCO_ENABLE;
1642         I915_WRITE(reg, val);
1643         POSTING_READ(reg);
1644         udelay(200);
1645
1646         pll->on = false;
1647 }
1648
1649 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650                                            enum pipe pipe)
1651 {
1652         struct drm_device *dev = dev_priv->dev;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654         uint32_t reg, val, pipeconf_val;
1655
1656         /* PCH only available on ILK+ */
1657         BUG_ON(dev_priv->info->gen < 5);
1658
1659         /* Make sure PCH DPLL is enabled */
1660         assert_pch_pll_enabled(dev_priv,
1661                                to_intel_crtc(crtc)->pch_pll,
1662                                to_intel_crtc(crtc));
1663
1664         /* FDI must be feeding us bits for PCH ports */
1665         assert_fdi_tx_enabled(dev_priv, pipe);
1666         assert_fdi_rx_enabled(dev_priv, pipe);
1667
1668         if (HAS_PCH_CPT(dev)) {
1669                 /* Workaround: Set the timing override bit before enabling the
1670                  * pch transcoder. */
1671                 reg = TRANS_CHICKEN2(pipe);
1672                 val = I915_READ(reg);
1673                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674                 I915_WRITE(reg, val);
1675         }
1676
1677         reg = TRANSCONF(pipe);
1678         val = I915_READ(reg);
1679         pipeconf_val = I915_READ(PIPECONF(pipe));
1680
1681         if (HAS_PCH_IBX(dev_priv->dev)) {
1682                 /*
1683                  * make the BPC in transcoder be consistent with
1684                  * that in pipeconf reg.
1685                  */
1686                 val &= ~PIPECONF_BPC_MASK;
1687                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1688         }
1689
1690         val &= ~TRANS_INTERLACE_MASK;
1691         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1692                 if (HAS_PCH_IBX(dev_priv->dev) &&
1693                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694                         val |= TRANS_LEGACY_INTERLACED_ILK;
1695                 else
1696                         val |= TRANS_INTERLACED;
1697         else
1698                 val |= TRANS_PROGRESSIVE;
1699
1700         I915_WRITE(reg, val | TRANS_ENABLE);
1701         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703 }
1704
1705 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1706                                       enum transcoder cpu_transcoder)
1707 {
1708         u32 val, pipeconf_val;
1709
1710         /* PCH only available on ILK+ */
1711         BUG_ON(dev_priv->info->gen < 5);
1712
1713         /* FDI must be feeding us bits for PCH ports */
1714         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1715         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1716
1717         /* Workaround: set timing override bit. */
1718         val = I915_READ(_TRANSA_CHICKEN2);
1719         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1720         I915_WRITE(_TRANSA_CHICKEN2, val);
1721
1722         val = TRANS_ENABLE;
1723         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1724
1725         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726             PIPECONF_INTERLACED_ILK)
1727                 val |= TRANS_INTERLACED;
1728         else
1729                 val |= TRANS_PROGRESSIVE;
1730
1731         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1732         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733                 DRM_ERROR("Failed to enable PCH transcoder\n");
1734 }
1735
1736 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737                                             enum pipe pipe)
1738 {
1739         struct drm_device *dev = dev_priv->dev;
1740         uint32_t reg, val;
1741
1742         /* FDI relies on the transcoder */
1743         assert_fdi_tx_disabled(dev_priv, pipe);
1744         assert_fdi_rx_disabled(dev_priv, pipe);
1745
1746         /* Ports must be off as well */
1747         assert_pch_ports_disabled(dev_priv, pipe);
1748
1749         reg = TRANSCONF(pipe);
1750         val = I915_READ(reg);
1751         val &= ~TRANS_ENABLE;
1752         I915_WRITE(reg, val);
1753         /* wait for PCH transcoder off, transcoder state */
1754         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1755                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1756
1757         if (!HAS_PCH_IBX(dev)) {
1758                 /* Workaround: Clear the timing override chicken bit again. */
1759                 reg = TRANS_CHICKEN2(pipe);
1760                 val = I915_READ(reg);
1761                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762                 I915_WRITE(reg, val);
1763         }
1764 }
1765
1766 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1767 {
1768         u32 val;
1769
1770         val = I915_READ(_TRANSACONF);
1771         val &= ~TRANS_ENABLE;
1772         I915_WRITE(_TRANSACONF, val);
1773         /* wait for PCH transcoder off, transcoder state */
1774         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775                 DRM_ERROR("Failed to disable PCH transcoder\n");
1776
1777         /* Workaround: clear timing override bit. */
1778         val = I915_READ(_TRANSA_CHICKEN2);
1779         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1780         I915_WRITE(_TRANSA_CHICKEN2, val);
1781 }
1782
1783 /**
1784  * intel_enable_pipe - enable a pipe, asserting requirements
1785  * @dev_priv: i915 private structure
1786  * @pipe: pipe to enable
1787  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1788  *
1789  * Enable @pipe, making sure that various hardware specific requirements
1790  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791  *
1792  * @pipe should be %PIPE_A or %PIPE_B.
1793  *
1794  * Will wait until the pipe is actually running (i.e. first vblank) before
1795  * returning.
1796  */
1797 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798                               bool pch_port)
1799 {
1800         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801                                                                       pipe);
1802         enum pipe pch_transcoder;
1803         int reg;
1804         u32 val;
1805
1806         if (HAS_PCH_LPT(dev_priv->dev))
1807                 pch_transcoder = TRANSCODER_A;
1808         else
1809                 pch_transcoder = pipe;
1810
1811         /*
1812          * A pipe without a PLL won't actually be able to drive bits from
1813          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1814          * need the check.
1815          */
1816         if (!HAS_PCH_SPLIT(dev_priv->dev))
1817                 assert_pll_enabled(dev_priv, pipe);
1818         else {
1819                 if (pch_port) {
1820                         /* if driving the PCH, we need FDI enabled */
1821                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1822                         assert_fdi_tx_pll_enabled(dev_priv,
1823                                                   (enum pipe) cpu_transcoder);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005                                                unsigned int bpp,
2006                                                unsigned int pitch)
2007 {
2008         int tile_rows, tiles;
2009
2010         tile_rows = *y / 8;
2011         *y %= 8;
2012         tiles = *x / (512/bpp);
2013         *x %= 512/bpp;
2014
2015         return tile_rows * pitch * 8 + tiles * 4096;
2016 }
2017
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019                              int x, int y)
2020 {
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024         struct intel_framebuffer *intel_fb;
2025         struct drm_i915_gem_object *obj;
2026         int plane = intel_crtc->plane;
2027         unsigned long linear_offset;
2028         u32 dspcntr;
2029         u32 reg;
2030
2031         switch (plane) {
2032         case 0:
2033         case 1:
2034                 break;
2035         default:
2036                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037                 return -EINVAL;
2038         }
2039
2040         intel_fb = to_intel_framebuffer(fb);
2041         obj = intel_fb->obj;
2042
2043         reg = DSPCNTR(plane);
2044         dspcntr = I915_READ(reg);
2045         /* Mask out pixel format bits in case we change it */
2046         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047         switch (fb->pixel_format) {
2048         case DRM_FORMAT_C8:
2049                 dspcntr |= DISPPLANE_8BPP;
2050                 break;
2051         case DRM_FORMAT_XRGB1555:
2052         case DRM_FORMAT_ARGB1555:
2053                 dspcntr |= DISPPLANE_BGRX555;
2054                 break;
2055         case DRM_FORMAT_RGB565:
2056                 dspcntr |= DISPPLANE_BGRX565;
2057                 break;
2058         case DRM_FORMAT_XRGB8888:
2059         case DRM_FORMAT_ARGB8888:
2060                 dspcntr |= DISPPLANE_BGRX888;
2061                 break;
2062         case DRM_FORMAT_XBGR8888:
2063         case DRM_FORMAT_ABGR8888:
2064                 dspcntr |= DISPPLANE_RGBX888;
2065                 break;
2066         case DRM_FORMAT_XRGB2101010:
2067         case DRM_FORMAT_ARGB2101010:
2068                 dspcntr |= DISPPLANE_BGRX101010;
2069                 break;
2070         case DRM_FORMAT_XBGR2101010:
2071         case DRM_FORMAT_ABGR2101010:
2072                 dspcntr |= DISPPLANE_RGBX101010;
2073                 break;
2074         default:
2075                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2076                 return -EINVAL;
2077         }
2078
2079         if (INTEL_INFO(dev)->gen >= 4) {
2080                 if (obj->tiling_mode != I915_TILING_NONE)
2081                         dspcntr |= DISPPLANE_TILED;
2082                 else
2083                         dspcntr &= ~DISPPLANE_TILED;
2084         }
2085
2086         I915_WRITE(reg, dspcntr);
2087
2088         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 intel_crtc->dspaddr_offset =
2092                         intel_gen4_compute_offset_xtiled(&x, &y,
2093                                                          fb->bits_per_pixel / 8,
2094                                                          fb->pitches[0]);
2095                 linear_offset -= intel_crtc->dspaddr_offset;
2096         } else {
2097                 intel_crtc->dspaddr_offset = linear_offset;
2098         }
2099
2100         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103         if (INTEL_INFO(dev)->gen >= 4) {
2104                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2106                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108         } else
2109                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2110         POSTING_READ(reg);
2111
2112         return 0;
2113 }
2114
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116                                  struct drm_framebuffer *fb, int x, int y)
2117 {
2118         struct drm_device *dev = crtc->dev;
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121         struct intel_framebuffer *intel_fb;
2122         struct drm_i915_gem_object *obj;
2123         int plane = intel_crtc->plane;
2124         unsigned long linear_offset;
2125         u32 dspcntr;
2126         u32 reg;
2127
2128         switch (plane) {
2129         case 0:
2130         case 1:
2131         case 2:
2132                 break;
2133         default:
2134                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135                 return -EINVAL;
2136         }
2137
2138         intel_fb = to_intel_framebuffer(fb);
2139         obj = intel_fb->obj;
2140
2141         reg = DSPCNTR(plane);
2142         dspcntr = I915_READ(reg);
2143         /* Mask out pixel format bits in case we change it */
2144         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145         switch (fb->pixel_format) {
2146         case DRM_FORMAT_C8:
2147                 dspcntr |= DISPPLANE_8BPP;
2148                 break;
2149         case DRM_FORMAT_RGB565:
2150                 dspcntr |= DISPPLANE_BGRX565;
2151                 break;
2152         case DRM_FORMAT_XRGB8888:
2153         case DRM_FORMAT_ARGB8888:
2154                 dspcntr |= DISPPLANE_BGRX888;
2155                 break;
2156         case DRM_FORMAT_XBGR8888:
2157         case DRM_FORMAT_ABGR8888:
2158                 dspcntr |= DISPPLANE_RGBX888;
2159                 break;
2160         case DRM_FORMAT_XRGB2101010:
2161         case DRM_FORMAT_ARGB2101010:
2162                 dspcntr |= DISPPLANE_BGRX101010;
2163                 break;
2164         case DRM_FORMAT_XBGR2101010:
2165         case DRM_FORMAT_ABGR2101010:
2166                 dspcntr |= DISPPLANE_RGBX101010;
2167                 break;
2168         default:
2169                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2170                 return -EINVAL;
2171         }
2172
2173         if (obj->tiling_mode != I915_TILING_NONE)
2174                 dspcntr |= DISPPLANE_TILED;
2175         else
2176                 dspcntr &= ~DISPPLANE_TILED;
2177
2178         /* must disable */
2179         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181         I915_WRITE(reg, dspcntr);
2182
2183         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184         intel_crtc->dspaddr_offset =
2185                 intel_gen4_compute_offset_xtiled(&x, &y,
2186                                                  fb->bits_per_pixel / 8,
2187                                                  fb->pitches[0]);
2188         linear_offset -= intel_crtc->dspaddr_offset;
2189
2190         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193         I915_MODIFY_DISPBASE(DSPSURF(plane),
2194                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2195         if (IS_HASWELL(dev)) {
2196                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197         } else {
2198                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200         }
2201         POSTING_READ(reg);
2202
2203         return 0;
2204 }
2205
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2207 static int
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209                            int x, int y, enum mode_set_atomic state)
2210 {
2211         struct drm_device *dev = crtc->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213
2214         if (dev_priv->display.disable_fbc)
2215                 dev_priv->display.disable_fbc(dev);
2216         intel_increase_pllclock(crtc);
2217
2218         return dev_priv->display.update_plane(crtc, fb, x, y);
2219 }
2220
2221 static int
2222 intel_finish_fb(struct drm_framebuffer *old_fb)
2223 {
2224         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226         bool was_interruptible = dev_priv->mm.interruptible;
2227         int ret;
2228
2229         /* Big Hammer, we also need to ensure that any pending
2230          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231          * current scanout is retired before unpinning the old
2232          * framebuffer.
2233          *
2234          * This should only fail upon a hung GPU, in which case we
2235          * can safely continue.
2236          */
2237         dev_priv->mm.interruptible = false;
2238         ret = i915_gem_object_finish_gpu(obj);
2239         dev_priv->mm.interruptible = was_interruptible;
2240
2241         return ret;
2242 }
2243
2244 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245 {
2246         struct drm_device *dev = crtc->dev;
2247         struct drm_i915_master_private *master_priv;
2248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250         if (!dev->primary->master)
2251                 return;
2252
2253         master_priv = dev->primary->master->driver_priv;
2254         if (!master_priv->sarea_priv)
2255                 return;
2256
2257         switch (intel_crtc->pipe) {
2258         case 0:
2259                 master_priv->sarea_priv->pipeA_x = x;
2260                 master_priv->sarea_priv->pipeA_y = y;
2261                 break;
2262         case 1:
2263                 master_priv->sarea_priv->pipeB_x = x;
2264                 master_priv->sarea_priv->pipeB_y = y;
2265                 break;
2266         default:
2267                 break;
2268         }
2269 }
2270
2271 static int
2272 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2273                     struct drm_framebuffer *fb)
2274 {
2275         struct drm_device *dev = crtc->dev;
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2278         struct drm_framebuffer *old_fb;
2279         int ret;
2280
2281         /* no fb bound */
2282         if (!fb) {
2283                 DRM_ERROR("No FB bound\n");
2284                 return 0;
2285         }
2286
2287         if(intel_crtc->plane > dev_priv->num_pipe) {
2288                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289                                 intel_crtc->plane,
2290                                 dev_priv->num_pipe);
2291                 return -EINVAL;
2292         }
2293
2294         mutex_lock(&dev->struct_mutex);
2295         ret = intel_pin_and_fence_fb_obj(dev,
2296                                          to_intel_framebuffer(fb)->obj,
2297                                          NULL);
2298         if (ret != 0) {
2299                 mutex_unlock(&dev->struct_mutex);
2300                 DRM_ERROR("pin & fence failed\n");
2301                 return ret;
2302         }
2303
2304         if (crtc->fb)
2305                 intel_finish_fb(crtc->fb);
2306
2307         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2308         if (ret) {
2309                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2310                 mutex_unlock(&dev->struct_mutex);
2311                 DRM_ERROR("failed to update base address\n");
2312                 return ret;
2313         }
2314
2315         old_fb = crtc->fb;
2316         crtc->fb = fb;
2317         crtc->x = x;
2318         crtc->y = y;
2319
2320         if (old_fb) {
2321                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2322                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2323         }
2324
2325         intel_update_fbc(dev);
2326         mutex_unlock(&dev->struct_mutex);
2327
2328         intel_crtc_update_sarea_pos(crtc, x, y);
2329
2330         return 0;
2331 }
2332
2333 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334 {
2335         struct drm_device *dev = crtc->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338         int pipe = intel_crtc->pipe;
2339         u32 reg, temp;
2340
2341         /* enable normal train */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         if (IS_IVYBRIDGE(dev)) {
2345                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2347         } else {
2348                 temp &= ~FDI_LINK_TRAIN_NONE;
2349                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2350         }
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (HAS_PCH_CPT(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE;
2361         }
2362         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364         /* wait one idle pattern time */
2365         POSTING_READ(reg);
2366         udelay(1000);
2367
2368         /* IVB wants error correction enabled */
2369         if (IS_IVYBRIDGE(dev))
2370                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371                            FDI_FE_ERRC_ENABLE);
2372 }
2373
2374 static void ivb_modeset_global_resources(struct drm_device *dev)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         struct intel_crtc *pipe_B_crtc =
2378                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2379         struct intel_crtc *pipe_C_crtc =
2380                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381         uint32_t temp;
2382
2383         /* When everything is off disable fdi C so that we could enable fdi B
2384          * with all lanes. XXX: This misses the case where a pipe is not using
2385          * any pch resources and so doesn't need any fdi lanes. */
2386         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2387                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390                 temp = I915_READ(SOUTH_CHICKEN1);
2391                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393                 I915_WRITE(SOUTH_CHICKEN1, temp);
2394         }
2395 }
2396
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400         struct drm_device *dev = crtc->dev;
2401         struct drm_i915_private *dev_priv = dev->dev_private;
2402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403         int pipe = intel_crtc->pipe;
2404         int plane = intel_crtc->plane;
2405         u32 reg, temp, tries;
2406
2407         /* FDI needs bits from pipe & plane first */
2408         assert_pipe_enabled(dev_priv, pipe);
2409         assert_plane_enabled(dev_priv, plane);
2410
2411         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412            for train result */
2413         reg = FDI_RX_IMR(pipe);
2414         temp = I915_READ(reg);
2415         temp &= ~FDI_RX_SYMBOL_LOCK;
2416         temp &= ~FDI_RX_BIT_LOCK;
2417         I915_WRITE(reg, temp);
2418         I915_READ(reg);
2419         udelay(150);
2420
2421         /* enable CPU FDI TX and PCH FDI RX */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~(7 << 19);
2425         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_1;
2428         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2429
2430         reg = FDI_RX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436         POSTING_READ(reg);
2437         udelay(150);
2438
2439         /* Ironlake workaround, enable clock pointer after FDI enable*/
2440         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442                    FDI_RX_PHASE_SYNC_POINTER_EN);
2443
2444         reg = FDI_RX_IIR(pipe);
2445         for (tries = 0; tries < 5; tries++) {
2446                 temp = I915_READ(reg);
2447                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449                 if ((temp & FDI_RX_BIT_LOCK)) {
2450                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2451                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452                         break;
2453                 }
2454         }
2455         if (tries == 5)
2456                 DRM_ERROR("FDI train 1 fail!\n");
2457
2458         /* Train 2 */
2459         reg = FDI_TX_CTL(pipe);
2460         temp = I915_READ(reg);
2461         temp &= ~FDI_LINK_TRAIN_NONE;
2462         temp |= FDI_LINK_TRAIN_PATTERN_2;
2463         I915_WRITE(reg, temp);
2464
2465         reg = FDI_RX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         POSTING_READ(reg);
2472         udelay(150);
2473
2474         reg = FDI_RX_IIR(pipe);
2475         for (tries = 0; tries < 5; tries++) {
2476                 temp = I915_READ(reg);
2477                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479                 if (temp & FDI_RX_SYMBOL_LOCK) {
2480                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2482                         break;
2483                 }
2484         }
2485         if (tries == 5)
2486                 DRM_ERROR("FDI train 2 fail!\n");
2487
2488         DRM_DEBUG_KMS("FDI train done\n");
2489
2490 }
2491
2492 static const int snb_b_fdi_train_param[] = {
2493         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497 };
2498
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501 {
2502         struct drm_device *dev = crtc->dev;
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505         int pipe = intel_crtc->pipe;
2506         u32 reg, temp, i, retry;
2507
2508         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509            for train result */
2510         reg = FDI_RX_IMR(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_RX_SYMBOL_LOCK;
2513         temp &= ~FDI_RX_BIT_LOCK;
2514         I915_WRITE(reg, temp);
2515
2516         POSTING_READ(reg);
2517         udelay(150);
2518
2519         /* enable CPU FDI TX and PCH FDI RX */
2520         reg = FDI_TX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~(7 << 19);
2523         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2524         temp &= ~FDI_LINK_TRAIN_NONE;
2525         temp |= FDI_LINK_TRAIN_PATTERN_1;
2526         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527         /* SNB-B */
2528         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2530
2531         I915_WRITE(FDI_RX_MISC(pipe),
2532                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
2534         reg = FDI_RX_CTL(pipe);
2535         temp = I915_READ(reg);
2536         if (HAS_PCH_CPT(dev)) {
2537                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539         } else {
2540                 temp &= ~FDI_LINK_TRAIN_NONE;
2541                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542         }
2543         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545         POSTING_READ(reg);
2546         udelay(150);
2547
2548         for (i = 0; i < 4; i++) {
2549                 reg = FDI_TX_CTL(pipe);
2550                 temp = I915_READ(reg);
2551                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552                 temp |= snb_b_fdi_train_param[i];
2553                 I915_WRITE(reg, temp);
2554
2555                 POSTING_READ(reg);
2556                 udelay(500);
2557
2558                 for (retry = 0; retry < 5; retry++) {
2559                         reg = FDI_RX_IIR(pipe);
2560                         temp = I915_READ(reg);
2561                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562                         if (temp & FDI_RX_BIT_LOCK) {
2563                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565                                 break;
2566                         }
2567                         udelay(50);
2568                 }
2569                 if (retry < 5)
2570                         break;
2571         }
2572         if (i == 4)
2573                 DRM_ERROR("FDI train 1 fail!\n");
2574
2575         /* Train 2 */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_LINK_TRAIN_NONE;
2579         temp |= FDI_LINK_TRAIN_PATTERN_2;
2580         if (IS_GEN6(dev)) {
2581                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582                 /* SNB-B */
2583                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         }
2585         I915_WRITE(reg, temp);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595         }
2596         I915_WRITE(reg, temp);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         for (i = 0; i < 4; i++) {
2602                 reg = FDI_TX_CTL(pipe);
2603                 temp = I915_READ(reg);
2604                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605                 temp |= snb_b_fdi_train_param[i];
2606                 I915_WRITE(reg, temp);
2607
2608                 POSTING_READ(reg);
2609                 udelay(500);
2610
2611                 for (retry = 0; retry < 5; retry++) {
2612                         reg = FDI_RX_IIR(pipe);
2613                         temp = I915_READ(reg);
2614                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615                         if (temp & FDI_RX_SYMBOL_LOCK) {
2616                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618                                 break;
2619                         }
2620                         udelay(50);
2621                 }
2622                 if (retry < 5)
2623                         break;
2624         }
2625         if (i == 4)
2626                 DRM_ERROR("FDI train 2 fail!\n");
2627
2628         DRM_DEBUG_KMS("FDI train done.\n");
2629 }
2630
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633 {
2634         struct drm_device *dev = crtc->dev;
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637         int pipe = intel_crtc->pipe;
2638         u32 reg, temp, i;
2639
2640         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641            for train result */
2642         reg = FDI_RX_IMR(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_RX_SYMBOL_LOCK;
2645         temp &= ~FDI_RX_BIT_LOCK;
2646         I915_WRITE(reg, temp);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652                       I915_READ(FDI_RX_IIR(pipe)));
2653
2654         /* enable CPU FDI TX and PCH FDI RX */
2655         reg = FDI_TX_CTL(pipe);
2656         temp = I915_READ(reg);
2657         temp &= ~(7 << 19);
2658         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2659         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663         temp |= FDI_COMPOSITE_SYNC;
2664         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666         I915_WRITE(FDI_RX_MISC(pipe),
2667                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669         reg = FDI_RX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_AUTO;
2672         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674         temp |= FDI_COMPOSITE_SYNC;
2675         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677         POSTING_READ(reg);
2678         udelay(150);
2679
2680         for (i = 0; i < 4; i++) {
2681                 reg = FDI_TX_CTL(pipe);
2682                 temp = I915_READ(reg);
2683                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684                 temp |= snb_b_fdi_train_param[i];
2685                 I915_WRITE(reg, temp);
2686
2687                 POSTING_READ(reg);
2688                 udelay(500);
2689
2690                 reg = FDI_RX_IIR(pipe);
2691                 temp = I915_READ(reg);
2692                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694                 if (temp & FDI_RX_BIT_LOCK ||
2695                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 1 fail!\n");
2703
2704         /* Train 2 */
2705         reg = FDI_TX_CTL(pipe);
2706         temp = I915_READ(reg);
2707         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711         I915_WRITE(reg, temp);
2712
2713         reg = FDI_RX_CTL(pipe);
2714         temp = I915_READ(reg);
2715         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717         I915_WRITE(reg, temp);
2718
2719         POSTING_READ(reg);
2720         udelay(150);
2721
2722         for (i = 0; i < 4; i++) {
2723                 reg = FDI_TX_CTL(pipe);
2724                 temp = I915_READ(reg);
2725                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726                 temp |= snb_b_fdi_train_param[i];
2727                 I915_WRITE(reg, temp);
2728
2729                 POSTING_READ(reg);
2730                 udelay(500);
2731
2732                 reg = FDI_RX_IIR(pipe);
2733                 temp = I915_READ(reg);
2734                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736                 if (temp & FDI_RX_SYMBOL_LOCK) {
2737                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2739                         break;
2740                 }
2741         }
2742         if (i == 4)
2743                 DRM_ERROR("FDI train 2 fail!\n");
2744
2745         DRM_DEBUG_KMS("FDI train done.\n");
2746 }
2747
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2749 {
2750         struct drm_device *dev = intel_crtc->base.dev;
2751         struct drm_i915_private *dev_priv = dev->dev_private;
2752         int pipe = intel_crtc->pipe;
2753         u32 reg, temp;
2754
2755
2756         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757         reg = FDI_RX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         temp &= ~((0x7 << 19) | (0x7 << 16));
2760         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2761         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764         POSTING_READ(reg);
2765         udelay(200);
2766
2767         /* Switch from Rawclk to PCDclk */
2768         temp = I915_READ(reg);
2769         I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771         POSTING_READ(reg);
2772         udelay(200);
2773
2774         /* Enable CPU FDI TX PLL, always on for Ironlake */
2775         reg = FDI_TX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2779
2780                 POSTING_READ(reg);
2781                 udelay(100);
2782         }
2783 }
2784
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786 {
2787         struct drm_device *dev = intel_crtc->base.dev;
2788         struct drm_i915_private *dev_priv = dev->dev_private;
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp;
2791
2792         /* Switch from PCDclk to Rawclk */
2793         reg = FDI_RX_CTL(pipe);
2794         temp = I915_READ(reg);
2795         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797         /* Disable CPU FDI TX PLL */
2798         reg = FDI_TX_CTL(pipe);
2799         temp = I915_READ(reg);
2800         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802         POSTING_READ(reg);
2803         udelay(100);
2804
2805         reg = FDI_RX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809         /* Wait for the clocks to turn off. */
2810         POSTING_READ(reg);
2811         udelay(100);
2812 }
2813
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815 {
2816         struct drm_device *dev = crtc->dev;
2817         struct drm_i915_private *dev_priv = dev->dev_private;
2818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819         int pipe = intel_crtc->pipe;
2820         u32 reg, temp;
2821
2822         /* disable CPU FDI tx and PCH FDI rx */
2823         reg = FDI_TX_CTL(pipe);
2824         temp = I915_READ(reg);
2825         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826         POSTING_READ(reg);
2827
2828         reg = FDI_RX_CTL(pipe);
2829         temp = I915_READ(reg);
2830         temp &= ~(0x7 << 16);
2831         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834         POSTING_READ(reg);
2835         udelay(100);
2836
2837         /* Ironlake workaround, disable clock pointer after downing FDI */
2838         if (HAS_PCH_IBX(dev)) {
2839                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2840         }
2841
2842         /* still set train pattern 1 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_1;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         if (HAS_PCH_CPT(dev)) {
2852                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854         } else {
2855                 temp &= ~FDI_LINK_TRAIN_NONE;
2856                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857         }
2858         /* BPC in FDI rx is consistent with that in PIPECONF */
2859         temp &= ~(0x07 << 16);
2860         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861         I915_WRITE(reg, temp);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865 }
2866
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868 {
2869         struct drm_device *dev = crtc->dev;
2870         struct drm_i915_private *dev_priv = dev->dev_private;
2871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872         unsigned long flags;
2873         bool pending;
2874
2875         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2877                 return false;
2878
2879         spin_lock_irqsave(&dev->event_lock, flags);
2880         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881         spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883         return pending;
2884 }
2885
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887 {
2888         struct drm_device *dev = crtc->dev;
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890
2891         if (crtc->fb == NULL)
2892                 return;
2893
2894         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
2896         wait_event(dev_priv->pending_flip_queue,
2897                    !intel_crtc_has_pending_flip(crtc));
2898
2899         mutex_lock(&dev->struct_mutex);
2900         intel_finish_fb(crtc->fb);
2901         mutex_unlock(&dev->struct_mutex);
2902 }
2903
2904 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct intel_encoder *intel_encoder;
2908
2909         /*
2910          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2911          * must be driven by its own crtc; no sharing is possible.
2912          */
2913         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2914                 switch (intel_encoder->type) {
2915                 case INTEL_OUTPUT_EDP:
2916                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2917                                 return false;
2918                         continue;
2919                 }
2920         }
2921
2922         return true;
2923 }
2924
2925 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2926 {
2927         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2928 }
2929
2930 /* Program iCLKIP clock to the desired frequency */
2931 static void lpt_program_iclkip(struct drm_crtc *crtc)
2932 {
2933         struct drm_device *dev = crtc->dev;
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2936         u32 temp;
2937
2938         mutex_lock(&dev_priv->dpio_lock);
2939
2940         /* It is necessary to ungate the pixclk gate prior to programming
2941          * the divisors, and gate it back when it is done.
2942          */
2943         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2944
2945         /* Disable SSCCTL */
2946         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2947                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2948                                 SBI_SSCCTL_DISABLE,
2949                         SBI_ICLK);
2950
2951         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2952         if (crtc->mode.clock == 20000) {
2953                 auxdiv = 1;
2954                 divsel = 0x41;
2955                 phaseinc = 0x20;
2956         } else {
2957                 /* The iCLK virtual clock root frequency is in MHz,
2958                  * but the crtc->mode.clock in in KHz. To get the divisors,
2959                  * it is necessary to divide one by another, so we
2960                  * convert the virtual clock precision to KHz here for higher
2961                  * precision.
2962                  */
2963                 u32 iclk_virtual_root_freq = 172800 * 1000;
2964                 u32 iclk_pi_range = 64;
2965                 u32 desired_divisor, msb_divisor_value, pi_value;
2966
2967                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2968                 msb_divisor_value = desired_divisor / iclk_pi_range;
2969                 pi_value = desired_divisor % iclk_pi_range;
2970
2971                 auxdiv = 0;
2972                 divsel = msb_divisor_value - 2;
2973                 phaseinc = pi_value;
2974         }
2975
2976         /* This should not happen with any sane values */
2977         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2978                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2979         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2980                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2981
2982         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2983                         crtc->mode.clock,
2984                         auxdiv,
2985                         divsel,
2986                         phasedir,
2987                         phaseinc);
2988
2989         /* Program SSCDIVINTPHASE6 */
2990         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2991         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2992         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2993         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2994         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2995         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2996         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2997         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2998
2999         /* Program SSCAUXDIV */
3000         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3001         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3002         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3003         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3004
3005         /* Enable modulator and associated divider */
3006         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3007         temp &= ~SBI_SSCCTL_DISABLE;
3008         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3009
3010         /* Wait for initialization time */
3011         udelay(24);
3012
3013         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3014
3015         mutex_unlock(&dev_priv->dpio_lock);
3016 }
3017
3018 /*
3019  * Enable PCH resources required for PCH ports:
3020  *   - PCH PLLs
3021  *   - FDI training & RX/TX
3022  *   - update transcoder timings
3023  *   - DP transcoding bits
3024  *   - transcoder
3025  */
3026 static void ironlake_pch_enable(struct drm_crtc *crtc)
3027 {
3028         struct drm_device *dev = crtc->dev;
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031         int pipe = intel_crtc->pipe;
3032         u32 reg, temp;
3033
3034         assert_transcoder_disabled(dev_priv, pipe);
3035
3036         /* Write the TU size bits before fdi link training, so that error
3037          * detection works. */
3038         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3039                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3040
3041         /* For PCH output, training FDI link */
3042         dev_priv->display.fdi_link_train(crtc);
3043
3044         /* XXX: pch pll's can be enabled any time before we enable the PCH
3045          * transcoder, and we actually should do this to not upset any PCH
3046          * transcoder that already use the clock when we share it.
3047          *
3048          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3049          * unconditionally resets the pll - we need that to have the right LVDS
3050          * enable sequence. */
3051         ironlake_enable_pch_pll(intel_crtc);
3052
3053         if (HAS_PCH_CPT(dev)) {
3054                 u32 sel;
3055
3056                 temp = I915_READ(PCH_DPLL_SEL);
3057                 switch (pipe) {
3058                 default:
3059                 case 0:
3060                         temp |= TRANSA_DPLL_ENABLE;
3061                         sel = TRANSA_DPLLB_SEL;
3062                         break;
3063                 case 1:
3064                         temp |= TRANSB_DPLL_ENABLE;
3065                         sel = TRANSB_DPLLB_SEL;
3066                         break;
3067                 case 2:
3068                         temp |= TRANSC_DPLL_ENABLE;
3069                         sel = TRANSC_DPLLB_SEL;
3070                         break;
3071                 }
3072                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3073                         temp |= sel;
3074                 else
3075                         temp &= ~sel;
3076                 I915_WRITE(PCH_DPLL_SEL, temp);
3077         }
3078
3079         /* set transcoder timing, panel must allow it */
3080         assert_panel_unlocked(dev_priv, pipe);
3081         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3082         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3083         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3084
3085         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3086         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3087         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3088         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3089
3090         intel_fdi_normal_train(crtc);
3091
3092         /* For PCH DP, enable TRANS_DP_CTL */
3093         if (HAS_PCH_CPT(dev) &&
3094             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3095              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3096                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3097                 reg = TRANS_DP_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3100                           TRANS_DP_SYNC_MASK |
3101                           TRANS_DP_BPC_MASK);
3102                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3103                          TRANS_DP_ENH_FRAMING);
3104                 temp |= bpc << 9; /* same format but at 11:9 */
3105
3106                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3107                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3108                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3109                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3110
3111                 switch (intel_trans_dp_port_sel(crtc)) {
3112                 case PCH_DP_B:
3113                         temp |= TRANS_DP_PORT_SEL_B;
3114                         break;
3115                 case PCH_DP_C:
3116                         temp |= TRANS_DP_PORT_SEL_C;
3117                         break;
3118                 case PCH_DP_D:
3119                         temp |= TRANS_DP_PORT_SEL_D;
3120                         break;
3121                 default:
3122                         BUG();
3123                 }
3124
3125                 I915_WRITE(reg, temp);
3126         }
3127
3128         ironlake_enable_pch_transcoder(dev_priv, pipe);
3129 }
3130
3131 static void lpt_pch_enable(struct drm_crtc *crtc)
3132 {
3133         struct drm_device *dev = crtc->dev;
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3137
3138         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3139
3140         lpt_program_iclkip(crtc);
3141
3142         /* Set transcoder timing. */
3143         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3144         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3145         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3146
3147         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3148         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3149         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3150         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3151
3152         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3153 }
3154
3155 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3156 {
3157         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3158
3159         if (pll == NULL)
3160                 return;
3161
3162         if (pll->refcount == 0) {
3163                 WARN(1, "bad PCH PLL refcount\n");
3164                 return;
3165         }
3166
3167         --pll->refcount;
3168         intel_crtc->pch_pll = NULL;
3169 }
3170
3171 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3172 {
3173         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3174         struct intel_pch_pll *pll;
3175         int i;
3176
3177         pll = intel_crtc->pch_pll;
3178         if (pll) {
3179                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3180                               intel_crtc->base.base.id, pll->pll_reg);
3181                 goto prepare;
3182         }
3183
3184         if (HAS_PCH_IBX(dev_priv->dev)) {
3185                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3186                 i = intel_crtc->pipe;
3187                 pll = &dev_priv->pch_plls[i];
3188
3189                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3190                               intel_crtc->base.base.id, pll->pll_reg);
3191
3192                 goto found;
3193         }
3194
3195         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3196                 pll = &dev_priv->pch_plls[i];
3197
3198                 /* Only want to check enabled timings first */
3199                 if (pll->refcount == 0)
3200                         continue;
3201
3202                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3203                     fp == I915_READ(pll->fp0_reg)) {
3204                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3205                                       intel_crtc->base.base.id,
3206                                       pll->pll_reg, pll->refcount, pll->active);
3207
3208                         goto found;
3209                 }
3210         }
3211
3212         /* Ok no matching timings, maybe there's a free one? */
3213         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3214                 pll = &dev_priv->pch_plls[i];
3215                 if (pll->refcount == 0) {
3216                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3217                                       intel_crtc->base.base.id, pll->pll_reg);
3218                         goto found;
3219                 }
3220         }
3221
3222         return NULL;
3223
3224 found:
3225         intel_crtc->pch_pll = pll;
3226         pll->refcount++;
3227         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3228 prepare: /* separate function? */
3229         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3230
3231         /* Wait for the clocks to stabilize before rewriting the regs */
3232         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3233         POSTING_READ(pll->pll_reg);
3234         udelay(150);
3235
3236         I915_WRITE(pll->fp0_reg, fp);
3237         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3238         pll->on = false;
3239         return pll;
3240 }
3241
3242 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3243 {
3244         struct drm_i915_private *dev_priv = dev->dev_private;
3245         int dslreg = PIPEDSL(pipe);
3246         u32 temp;
3247
3248         temp = I915_READ(dslreg);
3249         udelay(500);
3250         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3251                 if (wait_for(I915_READ(dslreg) != temp, 5))
3252                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3253         }
3254 }
3255
3256 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3257 {
3258         struct drm_device *dev = crtc->dev;
3259         struct drm_i915_private *dev_priv = dev->dev_private;
3260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3261         struct intel_encoder *encoder;
3262         int pipe = intel_crtc->pipe;
3263         int plane = intel_crtc->plane;
3264         u32 temp;
3265         bool is_pch_port;
3266
3267         WARN_ON(!crtc->enabled);
3268
3269         if (intel_crtc->active)
3270                 return;
3271
3272         intel_crtc->active = true;
3273         intel_update_watermarks(dev);
3274
3275         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3276                 temp = I915_READ(PCH_LVDS);
3277                 if ((temp & LVDS_PORT_EN) == 0)
3278                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3279         }
3280
3281         is_pch_port = ironlake_crtc_driving_pch(crtc);
3282
3283         if (is_pch_port) {
3284                 /* Note: FDI PLL enabling _must_ be done before we enable the
3285                  * cpu pipes, hence this is separate from all the other fdi/pch
3286                  * enabling. */
3287                 ironlake_fdi_pll_enable(intel_crtc);
3288         } else {
3289                 assert_fdi_tx_disabled(dev_priv, pipe);
3290                 assert_fdi_rx_disabled(dev_priv, pipe);
3291         }
3292
3293         for_each_encoder_on_crtc(dev, crtc, encoder)
3294                 if (encoder->pre_enable)
3295                         encoder->pre_enable(encoder);
3296
3297         /* Enable panel fitting for LVDS */
3298         if (dev_priv->pch_pf_size &&
3299             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3300              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3301                 /* Force use of hard-coded filter coefficients
3302                  * as some pre-programmed values are broken,
3303                  * e.g. x201.
3304                  */
3305                 if (IS_IVYBRIDGE(dev))
3306                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3307                                                  PF_PIPE_SEL_IVB(pipe));
3308                 else
3309                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3310                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3311                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3312         }
3313
3314         /*
3315          * On ILK+ LUT must be loaded before the pipe is running but with
3316          * clocks enabled
3317          */
3318         intel_crtc_load_lut(crtc);
3319
3320         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3321         intel_enable_plane(dev_priv, plane, pipe);
3322
3323         if (is_pch_port)
3324                 ironlake_pch_enable(crtc);
3325
3326         mutex_lock(&dev->struct_mutex);
3327         intel_update_fbc(dev);
3328         mutex_unlock(&dev->struct_mutex);
3329
3330         intel_crtc_update_cursor(crtc, true);
3331
3332         for_each_encoder_on_crtc(dev, crtc, encoder)
3333                 encoder->enable(encoder);
3334
3335         if (HAS_PCH_CPT(dev))
3336                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3337
3338         /*
3339          * There seems to be a race in PCH platform hw (at least on some
3340          * outputs) where an enabled pipe still completes any pageflip right
3341          * away (as if the pipe is off) instead of waiting for vblank. As soon
3342          * as the first vblank happend, everything works as expected. Hence just
3343          * wait for one vblank before returning to avoid strange things
3344          * happening.
3345          */
3346         intel_wait_for_vblank(dev, intel_crtc->pipe);
3347 }
3348
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         struct intel_encoder *encoder;
3355         int pipe = intel_crtc->pipe;
3356         int plane = intel_crtc->plane;
3357         bool is_pch_port;
3358
3359         WARN_ON(!crtc->enabled);
3360
3361         if (intel_crtc->active)
3362                 return;
3363
3364         intel_crtc->active = true;
3365         intel_update_watermarks(dev);
3366
3367         is_pch_port = haswell_crtc_driving_pch(crtc);
3368
3369         if (is_pch_port)
3370                 dev_priv->display.fdi_link_train(crtc);
3371
3372         for_each_encoder_on_crtc(dev, crtc, encoder)
3373                 if (encoder->pre_enable)
3374                         encoder->pre_enable(encoder);
3375
3376         intel_ddi_enable_pipe_clock(intel_crtc);
3377
3378         /* Enable panel fitting for eDP */
3379         if (dev_priv->pch_pf_size &&
3380             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3381                 /* Force use of hard-coded filter coefficients
3382                  * as some pre-programmed values are broken,
3383                  * e.g. x201.
3384                  */
3385                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386                                          PF_PIPE_SEL_IVB(pipe));
3387                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3388                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3389         }
3390
3391         /*
3392          * On ILK+ LUT must be loaded before the pipe is running but with
3393          * clocks enabled
3394          */
3395         intel_crtc_load_lut(crtc);
3396
3397         intel_ddi_set_pipe_settings(crtc);
3398         intel_ddi_enable_pipe_func(crtc);
3399
3400         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3401         intel_enable_plane(dev_priv, plane, pipe);
3402
3403         if (is_pch_port)
3404                 lpt_pch_enable(crtc);
3405
3406         mutex_lock(&dev->struct_mutex);
3407         intel_update_fbc(dev);
3408         mutex_unlock(&dev->struct_mutex);
3409
3410         intel_crtc_update_cursor(crtc, true);
3411
3412         for_each_encoder_on_crtc(dev, crtc, encoder)
3413                 encoder->enable(encoder);
3414
3415         /*
3416          * There seems to be a race in PCH platform hw (at least on some
3417          * outputs) where an enabled pipe still completes any pageflip right
3418          * away (as if the pipe is off) instead of waiting for vblank. As soon
3419          * as the first vblank happend, everything works as expected. Hence just
3420          * wait for one vblank before returning to avoid strange things
3421          * happening.
3422          */
3423         intel_wait_for_vblank(dev, intel_crtc->pipe);
3424 }
3425
3426 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3427 {
3428         struct drm_device *dev = crtc->dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431         struct intel_encoder *encoder;
3432         int pipe = intel_crtc->pipe;
3433         int plane = intel_crtc->plane;
3434         u32 reg, temp;
3435
3436
3437         if (!intel_crtc->active)
3438                 return;
3439
3440         for_each_encoder_on_crtc(dev, crtc, encoder)
3441                 encoder->disable(encoder);
3442
3443         intel_crtc_wait_for_pending_flips(crtc);
3444         drm_vblank_off(dev, pipe);
3445         intel_crtc_update_cursor(crtc, false);
3446
3447         intel_disable_plane(dev_priv, plane, pipe);
3448
3449         if (dev_priv->cfb_plane == plane)
3450                 intel_disable_fbc(dev);
3451
3452         intel_disable_pipe(dev_priv, pipe);
3453
3454         /* Disable PF */
3455         I915_WRITE(PF_CTL(pipe), 0);
3456         I915_WRITE(PF_WIN_SZ(pipe), 0);
3457
3458         for_each_encoder_on_crtc(dev, crtc, encoder)
3459                 if (encoder->post_disable)
3460                         encoder->post_disable(encoder);
3461
3462         ironlake_fdi_disable(crtc);
3463
3464         ironlake_disable_pch_transcoder(dev_priv, pipe);
3465
3466         if (HAS_PCH_CPT(dev)) {
3467                 /* disable TRANS_DP_CTL */
3468                 reg = TRANS_DP_CTL(pipe);
3469                 temp = I915_READ(reg);
3470                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3471                 temp |= TRANS_DP_PORT_SEL_NONE;
3472                 I915_WRITE(reg, temp);
3473
3474                 /* disable DPLL_SEL */
3475                 temp = I915_READ(PCH_DPLL_SEL);
3476                 switch (pipe) {
3477                 case 0:
3478                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3479                         break;
3480                 case 1:
3481                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3482                         break;
3483                 case 2:
3484                         /* C shares PLL A or B */
3485                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3486                         break;
3487                 default:
3488                         BUG(); /* wtf */
3489                 }
3490                 I915_WRITE(PCH_DPLL_SEL, temp);
3491         }
3492
3493         /* disable PCH DPLL */
3494         intel_disable_pch_pll(intel_crtc);
3495
3496         ironlake_fdi_pll_disable(intel_crtc);
3497
3498         intel_crtc->active = false;
3499         intel_update_watermarks(dev);
3500
3501         mutex_lock(&dev->struct_mutex);
3502         intel_update_fbc(dev);
3503         mutex_unlock(&dev->struct_mutex);
3504 }
3505
3506 static void haswell_crtc_disable(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         struct intel_encoder *encoder;
3512         int pipe = intel_crtc->pipe;
3513         int plane = intel_crtc->plane;
3514         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3515         bool is_pch_port;
3516
3517         if (!intel_crtc->active)
3518                 return;
3519
3520         is_pch_port = haswell_crtc_driving_pch(crtc);
3521
3522         for_each_encoder_on_crtc(dev, crtc, encoder)
3523                 encoder->disable(encoder);
3524
3525         intel_crtc_wait_for_pending_flips(crtc);
3526         drm_vblank_off(dev, pipe);
3527         intel_crtc_update_cursor(crtc, false);
3528
3529         intel_disable_plane(dev_priv, plane, pipe);
3530
3531         if (dev_priv->cfb_plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         intel_disable_pipe(dev_priv, pipe);
3535
3536         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3537
3538         /* Disable PF */
3539         I915_WRITE(PF_CTL(pipe), 0);
3540         I915_WRITE(PF_WIN_SZ(pipe), 0);
3541
3542         intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         if (is_pch_port) {
3549                 lpt_disable_pch_transcoder(dev_priv);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_pch_pll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570
3571         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572          * start using it. */
3573         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3574
3575         intel_ddi_put_crtc_pll(crtc);
3576 }
3577
3578 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579 {
3580         if (!enable && intel_crtc->overlay) {
3581                 struct drm_device *dev = intel_crtc->base.dev;
3582                 struct drm_i915_private *dev_priv = dev->dev_private;
3583
3584                 mutex_lock(&dev->struct_mutex);
3585                 dev_priv->mm.interruptible = false;
3586                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587                 dev_priv->mm.interruptible = true;
3588                 mutex_unlock(&dev->struct_mutex);
3589         }
3590
3591         /* Let userspace switch the overlay on again. In most cases userspace
3592          * has to recompute where to put it anyway.
3593          */
3594 }
3595
3596 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3597 {
3598         struct drm_device *dev = crtc->dev;
3599         struct drm_i915_private *dev_priv = dev->dev_private;
3600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3601         struct intel_encoder *encoder;
3602         int pipe = intel_crtc->pipe;
3603         int plane = intel_crtc->plane;
3604
3605         WARN_ON(!crtc->enabled);
3606
3607         if (intel_crtc->active)
3608                 return;
3609
3610         intel_crtc->active = true;
3611         intel_update_watermarks(dev);
3612
3613         intel_enable_pll(dev_priv, pipe);
3614
3615         for_each_encoder_on_crtc(dev, crtc, encoder)
3616                 if (encoder->pre_enable)
3617                         encoder->pre_enable(encoder);
3618
3619         intel_enable_pipe(dev_priv, pipe, false);
3620         intel_enable_plane(dev_priv, plane, pipe);
3621
3622         intel_crtc_load_lut(crtc);
3623         intel_update_fbc(dev);
3624
3625         /* Give the overlay scaler a chance to enable if it's on this pipe */
3626         intel_crtc_dpms_overlay(intel_crtc, true);
3627         intel_crtc_update_cursor(crtc, true);
3628
3629         for_each_encoder_on_crtc(dev, crtc, encoder)
3630                 encoder->enable(encoder);
3631 }
3632
3633 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3634 {
3635         struct drm_device *dev = crtc->dev;
3636         struct drm_i915_private *dev_priv = dev->dev_private;
3637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638         struct intel_encoder *encoder;
3639         int pipe = intel_crtc->pipe;
3640         int plane = intel_crtc->plane;
3641         u32 pctl;
3642
3643
3644         if (!intel_crtc->active)
3645                 return;
3646
3647         for_each_encoder_on_crtc(dev, crtc, encoder)
3648                 encoder->disable(encoder);
3649
3650         /* Give the overlay scaler a chance to disable if it's on this pipe */
3651         intel_crtc_wait_for_pending_flips(crtc);
3652         drm_vblank_off(dev, pipe);
3653         intel_crtc_dpms_overlay(intel_crtc, false);
3654         intel_crtc_update_cursor(crtc, false);
3655
3656         if (dev_priv->cfb_plane == plane)
3657                 intel_disable_fbc(dev);
3658
3659         intel_disable_plane(dev_priv, plane, pipe);
3660         intel_disable_pipe(dev_priv, pipe);
3661
3662         /* Disable pannel fitter if it is on this pipe. */
3663         pctl = I915_READ(PFIT_CONTROL);
3664         if ((pctl & PFIT_ENABLE) &&
3665             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3666                 I915_WRITE(PFIT_CONTROL, 0);
3667
3668         intel_disable_pll(dev_priv, pipe);
3669
3670         intel_crtc->active = false;
3671         intel_update_fbc(dev);
3672         intel_update_watermarks(dev);
3673 }
3674
3675 static void i9xx_crtc_off(struct drm_crtc *crtc)
3676 {
3677 }
3678
3679 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3680                                     bool enabled)
3681 {
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_master_private *master_priv;
3684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685         int pipe = intel_crtc->pipe;
3686
3687         if (!dev->primary->master)
3688                 return;
3689
3690         master_priv = dev->primary->master->driver_priv;
3691         if (!master_priv->sarea_priv)
3692                 return;
3693
3694         switch (pipe) {
3695         case 0:
3696                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3697                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3698                 break;
3699         case 1:
3700                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3701                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3702                 break;
3703         default:
3704                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3705                 break;
3706         }
3707 }
3708
3709 /**
3710  * Sets the power management mode of the pipe and plane.
3711  */
3712 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         struct intel_encoder *intel_encoder;
3717         bool enable = false;
3718
3719         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3720                 enable |= intel_encoder->connectors_active;
3721
3722         if (enable)
3723                 dev_priv->display.crtc_enable(crtc);
3724         else
3725                 dev_priv->display.crtc_disable(crtc);
3726
3727         intel_crtc_update_sarea(crtc, enable);
3728 }
3729
3730 static void intel_crtc_noop(struct drm_crtc *crtc)
3731 {
3732 }
3733
3734 static void intel_crtc_disable(struct drm_crtc *crtc)
3735 {
3736         struct drm_device *dev = crtc->dev;
3737         struct drm_connector *connector;
3738         struct drm_i915_private *dev_priv = dev->dev_private;
3739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3740
3741         /* crtc should still be enabled when we disable it. */
3742         WARN_ON(!crtc->enabled);
3743
3744         intel_crtc->eld_vld = false;
3745         dev_priv->display.crtc_disable(crtc);
3746         intel_crtc_update_sarea(crtc, false);
3747         dev_priv->display.off(crtc);
3748
3749         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3750         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3751
3752         if (crtc->fb) {
3753                 mutex_lock(&dev->struct_mutex);
3754                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3755                 mutex_unlock(&dev->struct_mutex);
3756                 crtc->fb = NULL;
3757         }
3758
3759         /* Update computed state. */
3760         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3761                 if (!connector->encoder || !connector->encoder->crtc)
3762                         continue;
3763
3764                 if (connector->encoder->crtc != crtc)
3765                         continue;
3766
3767                 connector->dpms = DRM_MODE_DPMS_OFF;
3768                 to_intel_encoder(connector->encoder)->connectors_active = false;
3769         }
3770 }
3771
3772 void intel_modeset_disable(struct drm_device *dev)
3773 {
3774         struct drm_crtc *crtc;
3775
3776         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3777                 if (crtc->enabled)
3778                         intel_crtc_disable(crtc);
3779         }
3780 }
3781
3782 void intel_encoder_noop(struct drm_encoder *encoder)
3783 {
3784 }
3785
3786 void intel_encoder_destroy(struct drm_encoder *encoder)
3787 {
3788         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3789
3790         drm_encoder_cleanup(encoder);
3791         kfree(intel_encoder);
3792 }
3793
3794 /* Simple dpms helper for encodres with just one connector, no cloning and only
3795  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3796  * state of the entire output pipe. */
3797 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3798 {
3799         if (mode == DRM_MODE_DPMS_ON) {
3800                 encoder->connectors_active = true;
3801
3802                 intel_crtc_update_dpms(encoder->base.crtc);
3803         } else {
3804                 encoder->connectors_active = false;
3805
3806                 intel_crtc_update_dpms(encoder->base.crtc);
3807         }
3808 }
3809
3810 /* Cross check the actual hw state with our own modeset state tracking (and it's
3811  * internal consistency). */
3812 static void intel_connector_check_state(struct intel_connector *connector)
3813 {
3814         if (connector->get_hw_state(connector)) {
3815                 struct intel_encoder *encoder = connector->encoder;
3816                 struct drm_crtc *crtc;
3817                 bool encoder_enabled;
3818                 enum pipe pipe;
3819
3820                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3821                               connector->base.base.id,
3822                               drm_get_connector_name(&connector->base));
3823
3824                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3825                      "wrong connector dpms state\n");
3826                 WARN(connector->base.encoder != &encoder->base,
3827                      "active connector not linked to encoder\n");
3828                 WARN(!encoder->connectors_active,
3829                      "encoder->connectors_active not set\n");
3830
3831                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3832                 WARN(!encoder_enabled, "encoder not enabled\n");
3833                 if (WARN_ON(!encoder->base.crtc))
3834                         return;
3835
3836                 crtc = encoder->base.crtc;
3837
3838                 WARN(!crtc->enabled, "crtc not enabled\n");
3839                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3840                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3841                      "encoder active on the wrong pipe\n");
3842         }
3843 }
3844
3845 /* Even simpler default implementation, if there's really no special case to
3846  * consider. */
3847 void intel_connector_dpms(struct drm_connector *connector, int mode)
3848 {
3849         struct intel_encoder *encoder = intel_attached_encoder(connector);
3850
3851         /* All the simple cases only support two dpms states. */
3852         if (mode != DRM_MODE_DPMS_ON)
3853                 mode = DRM_MODE_DPMS_OFF;
3854
3855         if (mode == connector->dpms)
3856                 return;
3857
3858         connector->dpms = mode;
3859
3860         /* Only need to change hw state when actually enabled */
3861         if (encoder->base.crtc)
3862                 intel_encoder_dpms(encoder, mode);
3863         else
3864                 WARN_ON(encoder->connectors_active != false);
3865
3866         intel_modeset_check_state(connector->dev);
3867 }
3868
3869 /* Simple connector->get_hw_state implementation for encoders that support only
3870  * one connector and no cloning and hence the encoder state determines the state
3871  * of the connector. */
3872 bool intel_connector_get_hw_state(struct intel_connector *connector)
3873 {
3874         enum pipe pipe = 0;
3875         struct intel_encoder *encoder = connector->encoder;
3876
3877         return encoder->get_hw_state(encoder, &pipe);
3878 }
3879
3880 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3881                                   const struct drm_display_mode *mode,
3882                                   struct drm_display_mode *adjusted_mode)
3883 {
3884         struct drm_device *dev = crtc->dev;
3885
3886         if (HAS_PCH_SPLIT(dev)) {
3887                 /* FDI link clock is fixed at 2.7G */
3888                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3889                         return false;
3890         }
3891
3892         /* All interlaced capable intel hw wants timings in frames. Note though
3893          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3894          * timings, so we need to be careful not to clobber these.*/
3895         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3896                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3897
3898         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3899          * with a hsync front porch of 0.
3900          */
3901         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3902                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3903                 return false;
3904
3905         return true;
3906 }
3907
3908 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3909 {
3910         return 400000; /* FIXME */
3911 }
3912
3913 static int i945_get_display_clock_speed(struct drm_device *dev)
3914 {
3915         return 400000;
3916 }
3917
3918 static int i915_get_display_clock_speed(struct drm_device *dev)
3919 {
3920         return 333000;
3921 }
3922
3923 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3924 {
3925         return 200000;
3926 }
3927
3928 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3929 {
3930         u16 gcfgc = 0;
3931
3932         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3933
3934         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3935                 return 133000;
3936         else {
3937                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3938                 case GC_DISPLAY_CLOCK_333_MHZ:
3939                         return 333000;
3940                 default:
3941                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3942                         return 190000;
3943                 }
3944         }
3945 }
3946
3947 static int i865_get_display_clock_speed(struct drm_device *dev)
3948 {
3949         return 266000;
3950 }
3951
3952 static int i855_get_display_clock_speed(struct drm_device *dev)
3953 {
3954         u16 hpllcc = 0;
3955         /* Assume that the hardware is in the high speed state.  This
3956          * should be the default.
3957          */
3958         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3959         case GC_CLOCK_133_200:
3960         case GC_CLOCK_100_200:
3961                 return 200000;
3962         case GC_CLOCK_166_250:
3963                 return 250000;
3964         case GC_CLOCK_100_133:
3965                 return 133000;
3966         }
3967
3968         /* Shouldn't happen */
3969         return 0;
3970 }
3971
3972 static int i830_get_display_clock_speed(struct drm_device *dev)
3973 {
3974         return 133000;
3975 }
3976
3977 static void
3978 intel_reduce_ratio(uint32_t *num, uint32_t *den)
3979 {
3980         while (*num > 0xffffff || *den > 0xffffff) {
3981                 *num >>= 1;
3982                 *den >>= 1;
3983         }
3984 }
3985
3986 void
3987 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3988                        int pixel_clock, int link_clock,
3989                        struct intel_link_m_n *m_n)
3990 {
3991         m_n->tu = 64;
3992         m_n->gmch_m = bits_per_pixel * pixel_clock;
3993         m_n->gmch_n = link_clock * nlanes * 8;
3994         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3995         m_n->link_m = pixel_clock;
3996         m_n->link_n = link_clock;
3997         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
3998 }
3999
4000 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4001 {
4002         if (i915_panel_use_ssc >= 0)
4003                 return i915_panel_use_ssc != 0;
4004         return dev_priv->lvds_use_ssc
4005                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4006 }
4007
4008 /**
4009  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4010  * @crtc: CRTC structure
4011  * @mode: requested mode
4012  *
4013  * A pipe may be connected to one or more outputs.  Based on the depth of the
4014  * attached framebuffer, choose a good color depth to use on the pipe.
4015  *
4016  * If possible, match the pipe depth to the fb depth.  In some cases, this
4017  * isn't ideal, because the connected output supports a lesser or restricted
4018  * set of depths.  Resolve that here:
4019  *    LVDS typically supports only 6bpc, so clamp down in that case
4020  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4021  *    Displays may support a restricted set as well, check EDID and clamp as
4022  *      appropriate.
4023  *    DP may want to dither down to 6bpc to fit larger modes
4024  *
4025  * RETURNS:
4026  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4027  * true if they don't match).
4028  */
4029 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4030                                          struct drm_framebuffer *fb,
4031                                          unsigned int *pipe_bpp,
4032                                          struct drm_display_mode *mode)
4033 {
4034         struct drm_device *dev = crtc->dev;
4035         struct drm_i915_private *dev_priv = dev->dev_private;
4036         struct drm_connector *connector;
4037         struct intel_encoder *intel_encoder;
4038         unsigned int display_bpc = UINT_MAX, bpc;
4039
4040         /* Walk the encoders & connectors on this crtc, get min bpc */
4041         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4042
4043                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4044                         unsigned int lvds_bpc;
4045
4046                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4047                             LVDS_A3_POWER_UP)
4048                                 lvds_bpc = 8;
4049                         else
4050                                 lvds_bpc = 6;
4051
4052                         if (lvds_bpc < display_bpc) {
4053                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4054                                 display_bpc = lvds_bpc;
4055                         }
4056                         continue;
4057                 }
4058
4059                 /* Not one of the known troublemakers, check the EDID */
4060                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4061                                     head) {
4062                         if (connector->encoder != &intel_encoder->base)
4063                                 continue;
4064
4065                         /* Don't use an invalid EDID bpc value */
4066                         if (connector->display_info.bpc &&
4067                             connector->display_info.bpc < display_bpc) {
4068                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4069                                 display_bpc = connector->display_info.bpc;
4070                         }
4071                 }
4072
4073                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4074                         /* Use VBT settings if we have an eDP panel */
4075                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4076
4077                         if (edp_bpc && edp_bpc < display_bpc) {
4078                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4079                                 display_bpc = edp_bpc;
4080                         }
4081                         continue;
4082                 }
4083
4084                 /*
4085                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4086                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4087                  */
4088                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4089                         if (display_bpc > 8 && display_bpc < 12) {
4090                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4091                                 display_bpc = 12;
4092                         } else {
4093                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4094                                 display_bpc = 8;
4095                         }
4096                 }
4097         }
4098
4099         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4100                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4101                 display_bpc = 6;
4102         }
4103
4104         /*
4105          * We could just drive the pipe at the highest bpc all the time and
4106          * enable dithering as needed, but that costs bandwidth.  So choose
4107          * the minimum value that expresses the full color range of the fb but
4108          * also stays within the max display bpc discovered above.
4109          */
4110
4111         switch (fb->depth) {
4112         case 8:
4113                 bpc = 8; /* since we go through a colormap */
4114                 break;
4115         case 15:
4116         case 16:
4117                 bpc = 6; /* min is 18bpp */
4118                 break;
4119         case 24:
4120                 bpc = 8;
4121                 break;
4122         case 30:
4123                 bpc = 10;
4124                 break;
4125         case 48:
4126                 bpc = 12;
4127                 break;
4128         default:
4129                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4130                 bpc = min((unsigned int)8, display_bpc);
4131                 break;
4132         }
4133
4134         display_bpc = min(display_bpc, bpc);
4135
4136         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4137                       bpc, display_bpc);
4138
4139         *pipe_bpp = display_bpc * 3;
4140
4141         return display_bpc != bpc;
4142 }
4143
4144 static int vlv_get_refclk(struct drm_crtc *crtc)
4145 {
4146         struct drm_device *dev = crtc->dev;
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148         int refclk = 27000; /* for DP & HDMI */
4149
4150         return 100000; /* only one validated so far */
4151
4152         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4153                 refclk = 96000;
4154         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4155                 if (intel_panel_use_ssc(dev_priv))
4156                         refclk = 100000;
4157                 else
4158                         refclk = 96000;
4159         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4160                 refclk = 100000;
4161         }
4162
4163         return refclk;
4164 }
4165
4166 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4167 {
4168         struct drm_device *dev = crtc->dev;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         int refclk;
4171
4172         if (IS_VALLEYVIEW(dev)) {
4173                 refclk = vlv_get_refclk(crtc);
4174         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4175             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4176                 refclk = dev_priv->lvds_ssc_freq * 1000;
4177                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4178                               refclk / 1000);
4179         } else if (!IS_GEN2(dev)) {
4180                 refclk = 96000;
4181         } else {
4182                 refclk = 48000;
4183         }
4184
4185         return refclk;
4186 }
4187
4188 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4189                                       intel_clock_t *clock)
4190 {
4191         /* SDVO TV has fixed PLL values depend on its clock range,
4192            this mirrors vbios setting. */
4193         if (adjusted_mode->clock >= 100000
4194             && adjusted_mode->clock < 140500) {
4195                 clock->p1 = 2;
4196                 clock->p2 = 10;
4197                 clock->n = 3;
4198                 clock->m1 = 16;
4199                 clock->m2 = 8;
4200         } else if (adjusted_mode->clock >= 140500
4201                    && adjusted_mode->clock <= 200000) {
4202                 clock->p1 = 1;
4203                 clock->p2 = 10;
4204                 clock->n = 6;
4205                 clock->m1 = 12;
4206                 clock->m2 = 8;
4207         }
4208 }
4209
4210 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4211                                      intel_clock_t *clock,
4212                                      intel_clock_t *reduced_clock)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         int pipe = intel_crtc->pipe;
4218         u32 fp, fp2 = 0;
4219
4220         if (IS_PINEVIEW(dev)) {
4221                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4222                 if (reduced_clock)
4223                         fp2 = (1 << reduced_clock->n) << 16 |
4224                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4225         } else {
4226                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4227                 if (reduced_clock)
4228                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4229                                 reduced_clock->m2;
4230         }
4231
4232         I915_WRITE(FP0(pipe), fp);
4233
4234         intel_crtc->lowfreq_avail = false;
4235         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4236             reduced_clock && i915_powersave) {
4237                 I915_WRITE(FP1(pipe), fp2);
4238                 intel_crtc->lowfreq_avail = true;
4239         } else {
4240                 I915_WRITE(FP1(pipe), fp);
4241         }
4242 }
4243
4244 static void vlv_update_pll(struct drm_crtc *crtc,
4245                            struct drm_display_mode *mode,
4246                            struct drm_display_mode *adjusted_mode,
4247                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4248                            int num_connectors)
4249 {
4250         struct drm_device *dev = crtc->dev;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253         int pipe = intel_crtc->pipe;
4254         u32 dpll, mdiv, pdiv;
4255         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4256         bool is_sdvo;
4257         u32 temp;
4258
4259         mutex_lock(&dev_priv->dpio_lock);
4260
4261         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4262                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4263
4264         dpll = DPLL_VGA_MODE_DIS;
4265         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4266         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4267         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4268
4269         I915_WRITE(DPLL(pipe), dpll);
4270         POSTING_READ(DPLL(pipe));
4271
4272         bestn = clock->n;
4273         bestm1 = clock->m1;
4274         bestm2 = clock->m2;
4275         bestp1 = clock->p1;
4276         bestp2 = clock->p2;
4277
4278         /*
4279          * In Valleyview PLL and program lane counter registers are exposed
4280          * through DPIO interface
4281          */
4282         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4283         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4284         mdiv |= ((bestn << DPIO_N_SHIFT));
4285         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4286         mdiv |= (1 << DPIO_K_SHIFT);
4287         mdiv |= DPIO_ENABLE_CALIBRATION;
4288         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4289
4290         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4291
4292         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4293                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4294                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4295                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4296         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4297
4298         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4299
4300         dpll |= DPLL_VCO_ENABLE;
4301         I915_WRITE(DPLL(pipe), dpll);
4302         POSTING_READ(DPLL(pipe));
4303         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4304                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4305
4306         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4307
4308         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4309                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4310
4311         I915_WRITE(DPLL(pipe), dpll);
4312
4313         /* Wait for the clocks to stabilize. */
4314         POSTING_READ(DPLL(pipe));
4315         udelay(150);
4316
4317         temp = 0;
4318         if (is_sdvo) {
4319                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4320                 if (temp > 1)
4321                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4322                 else
4323                         temp = 0;
4324         }
4325         I915_WRITE(DPLL_MD(pipe), temp);
4326         POSTING_READ(DPLL_MD(pipe));
4327
4328         /* Now program lane control registers */
4329         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4330                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4331         {
4332                 temp = 0x1000C4;
4333                 if(pipe == 1)
4334                         temp |= (1 << 21);
4335                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4336         }
4337         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4338         {
4339                 temp = 0x1000C4;
4340                 if(pipe == 1)
4341                         temp |= (1 << 21);
4342                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4343         }
4344
4345         mutex_unlock(&dev_priv->dpio_lock);
4346 }
4347
4348 static void i9xx_update_pll(struct drm_crtc *crtc,
4349                             struct drm_display_mode *mode,
4350                             struct drm_display_mode *adjusted_mode,
4351                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4352                             int num_connectors)
4353 {
4354         struct drm_device *dev = crtc->dev;
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4357         struct intel_encoder *encoder;
4358         int pipe = intel_crtc->pipe;
4359         u32 dpll;
4360         bool is_sdvo;
4361
4362         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4363
4364         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4365                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4366
4367         dpll = DPLL_VGA_MODE_DIS;
4368
4369         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4370                 dpll |= DPLLB_MODE_LVDS;
4371         else
4372                 dpll |= DPLLB_MODE_DAC_SERIAL;
4373         if (is_sdvo) {
4374                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4375                 if (pixel_multiplier > 1) {
4376                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4377                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4378                 }
4379                 dpll |= DPLL_DVO_HIGH_SPEED;
4380         }
4381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4382                 dpll |= DPLL_DVO_HIGH_SPEED;
4383
4384         /* compute bitmask from p1 value */
4385         if (IS_PINEVIEW(dev))
4386                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4387         else {
4388                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4389                 if (IS_G4X(dev) && reduced_clock)
4390                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4391         }
4392         switch (clock->p2) {
4393         case 5:
4394                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4395                 break;
4396         case 7:
4397                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4398                 break;
4399         case 10:
4400                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4401                 break;
4402         case 14:
4403                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4404                 break;
4405         }
4406         if (INTEL_INFO(dev)->gen >= 4)
4407                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4408
4409         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4410                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4411         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4412                 /* XXX: just matching BIOS for now */
4413                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4414                 dpll |= 3;
4415         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4416                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4417                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4418         else
4419                 dpll |= PLL_REF_INPUT_DREFCLK;
4420
4421         dpll |= DPLL_VCO_ENABLE;
4422         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4423         POSTING_READ(DPLL(pipe));
4424         udelay(150);
4425
4426         for_each_encoder_on_crtc(dev, crtc, encoder)
4427                 if (encoder->pre_pll_enable)
4428                         encoder->pre_pll_enable(encoder);
4429
4430         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4431                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4432
4433         I915_WRITE(DPLL(pipe), dpll);
4434
4435         /* Wait for the clocks to stabilize. */
4436         POSTING_READ(DPLL(pipe));
4437         udelay(150);
4438
4439         if (INTEL_INFO(dev)->gen >= 4) {
4440                 u32 temp = 0;
4441                 if (is_sdvo) {
4442                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4443                         if (temp > 1)
4444                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4445                         else
4446                                 temp = 0;
4447                 }
4448                 I915_WRITE(DPLL_MD(pipe), temp);
4449         } else {
4450                 /* The pixel multiplier can only be updated once the
4451                  * DPLL is enabled and the clocks are stable.
4452                  *
4453                  * So write it again.
4454                  */
4455                 I915_WRITE(DPLL(pipe), dpll);
4456         }
4457 }
4458
4459 static void i8xx_update_pll(struct drm_crtc *crtc,
4460                             struct drm_display_mode *adjusted_mode,
4461                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4462                             int num_connectors)
4463 {
4464         struct drm_device *dev = crtc->dev;
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467         struct intel_encoder *encoder;
4468         int pipe = intel_crtc->pipe;
4469         u32 dpll;
4470
4471         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4472
4473         dpll = DPLL_VGA_MODE_DIS;
4474
4475         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4476                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4477         } else {
4478                 if (clock->p1 == 2)
4479                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4480                 else
4481                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4482                 if (clock->p2 == 4)
4483                         dpll |= PLL_P2_DIVIDE_BY_4;
4484         }
4485
4486         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487                 /* XXX: just matching BIOS for now */
4488                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4489                 dpll |= 3;
4490         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4491                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4492                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4493         else
4494                 dpll |= PLL_REF_INPUT_DREFCLK;
4495
4496         dpll |= DPLL_VCO_ENABLE;
4497         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4498         POSTING_READ(DPLL(pipe));
4499         udelay(150);
4500
4501         for_each_encoder_on_crtc(dev, crtc, encoder)
4502                 if (encoder->pre_pll_enable)
4503                         encoder->pre_pll_enable(encoder);
4504
4505         I915_WRITE(DPLL(pipe), dpll);
4506
4507         /* Wait for the clocks to stabilize. */
4508         POSTING_READ(DPLL(pipe));
4509         udelay(150);
4510
4511         /* The pixel multiplier can only be updated once the
4512          * DPLL is enabled and the clocks are stable.
4513          *
4514          * So write it again.
4515          */
4516         I915_WRITE(DPLL(pipe), dpll);
4517 }
4518
4519 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4520                                    struct drm_display_mode *mode,
4521                                    struct drm_display_mode *adjusted_mode)
4522 {
4523         struct drm_device *dev = intel_crtc->base.dev;
4524         struct drm_i915_private *dev_priv = dev->dev_private;
4525         enum pipe pipe = intel_crtc->pipe;
4526         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4527         uint32_t vsyncshift;
4528
4529         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4530                 /* the chip adds 2 halflines automatically */
4531                 adjusted_mode->crtc_vtotal -= 1;
4532                 adjusted_mode->crtc_vblank_end -= 1;
4533                 vsyncshift = adjusted_mode->crtc_hsync_start
4534                              - adjusted_mode->crtc_htotal / 2;
4535         } else {
4536                 vsyncshift = 0;
4537         }
4538
4539         if (INTEL_INFO(dev)->gen > 3)
4540                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4541
4542         I915_WRITE(HTOTAL(cpu_transcoder),
4543                    (adjusted_mode->crtc_hdisplay - 1) |
4544                    ((adjusted_mode->crtc_htotal - 1) << 16));
4545         I915_WRITE(HBLANK(cpu_transcoder),
4546                    (adjusted_mode->crtc_hblank_start - 1) |
4547                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4548         I915_WRITE(HSYNC(cpu_transcoder),
4549                    (adjusted_mode->crtc_hsync_start - 1) |
4550                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4551
4552         I915_WRITE(VTOTAL(cpu_transcoder),
4553                    (adjusted_mode->crtc_vdisplay - 1) |
4554                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4555         I915_WRITE(VBLANK(cpu_transcoder),
4556                    (adjusted_mode->crtc_vblank_start - 1) |
4557                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4558         I915_WRITE(VSYNC(cpu_transcoder),
4559                    (adjusted_mode->crtc_vsync_start - 1) |
4560                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4561
4562         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4563          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4564          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4565          * bits. */
4566         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4567             (pipe == PIPE_B || pipe == PIPE_C))
4568                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4569
4570         /* pipesrc controls the size that is scaled from, which should
4571          * always be the user's requested size.
4572          */
4573         I915_WRITE(PIPESRC(pipe),
4574                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4575 }
4576
4577 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4578                               struct drm_display_mode *mode,
4579                               struct drm_display_mode *adjusted_mode,
4580                               int x, int y,
4581                               struct drm_framebuffer *fb)
4582 {
4583         struct drm_device *dev = crtc->dev;
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586         int pipe = intel_crtc->pipe;
4587         int plane = intel_crtc->plane;
4588         int refclk, num_connectors = 0;
4589         intel_clock_t clock, reduced_clock;
4590         u32 dspcntr, pipeconf;
4591         bool ok, has_reduced_clock = false, is_sdvo = false;
4592         bool is_lvds = false, is_tv = false, is_dp = false;
4593         struct intel_encoder *encoder;
4594         const intel_limit_t *limit;
4595         int ret;
4596
4597         for_each_encoder_on_crtc(dev, crtc, encoder) {
4598                 switch (encoder->type) {
4599                 case INTEL_OUTPUT_LVDS:
4600                         is_lvds = true;
4601                         break;
4602                 case INTEL_OUTPUT_SDVO:
4603                 case INTEL_OUTPUT_HDMI:
4604                         is_sdvo = true;
4605                         if (encoder->needs_tv_clock)
4606                                 is_tv = true;
4607                         break;
4608                 case INTEL_OUTPUT_TVOUT:
4609                         is_tv = true;
4610                         break;
4611                 case INTEL_OUTPUT_DISPLAYPORT:
4612                         is_dp = true;
4613                         break;
4614                 }
4615
4616                 num_connectors++;
4617         }
4618
4619         refclk = i9xx_get_refclk(crtc, num_connectors);
4620
4621         /*
4622          * Returns a set of divisors for the desired target clock with the given
4623          * refclk, or FALSE.  The returned values represent the clock equation:
4624          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4625          */
4626         limit = intel_limit(crtc, refclk);
4627         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4628                              &clock);
4629         if (!ok) {
4630                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4631                 return -EINVAL;
4632         }
4633
4634         /* Ensure that the cursor is valid for the new mode before changing... */
4635         intel_crtc_update_cursor(crtc, true);
4636
4637         if (is_lvds && dev_priv->lvds_downclock_avail) {
4638                 /*
4639                  * Ensure we match the reduced clock's P to the target clock.
4640                  * If the clocks don't match, we can't switch the display clock
4641                  * by using the FP0/FP1. In such case we will disable the LVDS
4642                  * downclock feature.
4643                 */
4644                 has_reduced_clock = limit->find_pll(limit, crtc,
4645                                                     dev_priv->lvds_downclock,
4646                                                     refclk,
4647                                                     &clock,
4648                                                     &reduced_clock);
4649         }
4650
4651         if (is_sdvo && is_tv)
4652                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4653
4654         if (IS_GEN2(dev))
4655                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4656                                 has_reduced_clock ? &reduced_clock : NULL,
4657                                 num_connectors);
4658         else if (IS_VALLEYVIEW(dev))
4659                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4660                                 has_reduced_clock ? &reduced_clock : NULL,
4661                                 num_connectors);
4662         else
4663                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4664                                 has_reduced_clock ? &reduced_clock : NULL,
4665                                 num_connectors);
4666
4667         /* setup pipeconf */
4668         pipeconf = I915_READ(PIPECONF(pipe));
4669
4670         /* Set up the display plane register */
4671         dspcntr = DISPPLANE_GAMMA_ENABLE;
4672
4673         if (pipe == 0)
4674                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4675         else
4676                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4677
4678         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4679                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4680                  * core speed.
4681                  *
4682                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4683                  * pipe == 0 check?
4684                  */
4685                 if (mode->clock >
4686                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4687                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4688                 else
4689                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4690         }
4691
4692         /* default to 8bpc */
4693         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4694         if (is_dp) {
4695                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4696                         pipeconf |= PIPECONF_6BPC |
4697                                     PIPECONF_DITHER_EN |
4698                                     PIPECONF_DITHER_TYPE_SP;
4699                 }
4700         }
4701
4702         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4703                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4704                         pipeconf |= PIPECONF_6BPC |
4705                                         PIPECONF_ENABLE |
4706                                         I965_PIPECONF_ACTIVE;
4707                 }
4708         }
4709
4710         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4711         drm_mode_debug_printmodeline(mode);
4712
4713         if (HAS_PIPE_CXSR(dev)) {
4714                 if (intel_crtc->lowfreq_avail) {
4715                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4716                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4717                 } else {
4718                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4719                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4720                 }
4721         }
4722
4723         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4724         if (!IS_GEN2(dev) &&
4725             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4726                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4727         else
4728                 pipeconf |= PIPECONF_PROGRESSIVE;
4729
4730         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4731
4732         /* pipesrc and dspsize control the size that is scaled from,
4733          * which should always be the user's requested size.
4734          */
4735         I915_WRITE(DSPSIZE(plane),
4736                    ((mode->vdisplay - 1) << 16) |
4737                    (mode->hdisplay - 1));
4738         I915_WRITE(DSPPOS(plane), 0);
4739
4740         I915_WRITE(PIPECONF(pipe), pipeconf);
4741         POSTING_READ(PIPECONF(pipe));
4742         intel_enable_pipe(dev_priv, pipe, false);
4743
4744         intel_wait_for_vblank(dev, pipe);
4745
4746         I915_WRITE(DSPCNTR(plane), dspcntr);
4747         POSTING_READ(DSPCNTR(plane));
4748
4749         ret = intel_pipe_set_base(crtc, x, y, fb);
4750
4751         intel_update_watermarks(dev);
4752
4753         return ret;
4754 }
4755
4756 static void ironlake_init_pch_refclk(struct drm_device *dev)
4757 {
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759         struct drm_mode_config *mode_config = &dev->mode_config;
4760         struct intel_encoder *encoder;
4761         u32 temp;
4762         bool has_lvds = false;
4763         bool has_cpu_edp = false;
4764         bool has_pch_edp = false;
4765         bool has_panel = false;
4766         bool has_ck505 = false;
4767         bool can_ssc = false;
4768
4769         /* We need to take the global config into account */
4770         list_for_each_entry(encoder, &mode_config->encoder_list,
4771                             base.head) {
4772                 switch (encoder->type) {
4773                 case INTEL_OUTPUT_LVDS:
4774                         has_panel = true;
4775                         has_lvds = true;
4776                         break;
4777                 case INTEL_OUTPUT_EDP:
4778                         has_panel = true;
4779                         if (intel_encoder_is_pch_edp(&encoder->base))
4780                                 has_pch_edp = true;
4781                         else
4782                                 has_cpu_edp = true;
4783                         break;
4784                 }
4785         }
4786
4787         if (HAS_PCH_IBX(dev)) {
4788                 has_ck505 = dev_priv->display_clock_mode;
4789                 can_ssc = has_ck505;
4790         } else {
4791                 has_ck505 = false;
4792                 can_ssc = true;
4793         }
4794
4795         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4796                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4797                       has_ck505);
4798
4799         /* Ironlake: try to setup display ref clock before DPLL
4800          * enabling. This is only under driver's control after
4801          * PCH B stepping, previous chipset stepping should be
4802          * ignoring this setting.
4803          */
4804         temp = I915_READ(PCH_DREF_CONTROL);
4805         /* Always enable nonspread source */
4806         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4807
4808         if (has_ck505)
4809                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4810         else
4811                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4812
4813         if (has_panel) {
4814                 temp &= ~DREF_SSC_SOURCE_MASK;
4815                 temp |= DREF_SSC_SOURCE_ENABLE;
4816
4817                 /* SSC must be turned on before enabling the CPU output  */
4818                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4819                         DRM_DEBUG_KMS("Using SSC on panel\n");
4820                         temp |= DREF_SSC1_ENABLE;
4821                 } else
4822                         temp &= ~DREF_SSC1_ENABLE;
4823
4824                 /* Get SSC going before enabling the outputs */
4825                 I915_WRITE(PCH_DREF_CONTROL, temp);
4826                 POSTING_READ(PCH_DREF_CONTROL);
4827                 udelay(200);
4828
4829                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4830
4831                 /* Enable CPU source on CPU attached eDP */
4832                 if (has_cpu_edp) {
4833                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4834                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4835                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4836                         }
4837                         else
4838                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4839                 } else
4840                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4841
4842                 I915_WRITE(PCH_DREF_CONTROL, temp);
4843                 POSTING_READ(PCH_DREF_CONTROL);
4844                 udelay(200);
4845         } else {
4846                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4847
4848                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4849
4850                 /* Turn off CPU output */
4851                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4852
4853                 I915_WRITE(PCH_DREF_CONTROL, temp);
4854                 POSTING_READ(PCH_DREF_CONTROL);
4855                 udelay(200);
4856
4857                 /* Turn off the SSC source */
4858                 temp &= ~DREF_SSC_SOURCE_MASK;
4859                 temp |= DREF_SSC_SOURCE_DISABLE;
4860
4861                 /* Turn off SSC1 */
4862                 temp &= ~ DREF_SSC1_ENABLE;
4863
4864                 I915_WRITE(PCH_DREF_CONTROL, temp);
4865                 POSTING_READ(PCH_DREF_CONTROL);
4866                 udelay(200);
4867         }
4868 }
4869
4870 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4871 static void lpt_init_pch_refclk(struct drm_device *dev)
4872 {
4873         struct drm_i915_private *dev_priv = dev->dev_private;
4874         struct drm_mode_config *mode_config = &dev->mode_config;
4875         struct intel_encoder *encoder;
4876         bool has_vga = false;
4877         bool is_sdv = false;
4878         u32 tmp;
4879
4880         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4881                 switch (encoder->type) {
4882                 case INTEL_OUTPUT_ANALOG:
4883                         has_vga = true;
4884                         break;
4885                 }
4886         }
4887
4888         if (!has_vga)
4889                 return;
4890
4891         mutex_lock(&dev_priv->dpio_lock);
4892
4893         /* XXX: Rip out SDV support once Haswell ships for real. */
4894         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4895                 is_sdv = true;
4896
4897         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4898         tmp &= ~SBI_SSCCTL_DISABLE;
4899         tmp |= SBI_SSCCTL_PATHALT;
4900         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4901
4902         udelay(24);
4903
4904         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4905         tmp &= ~SBI_SSCCTL_PATHALT;
4906         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4907
4908         if (!is_sdv) {
4909                 tmp = I915_READ(SOUTH_CHICKEN2);
4910                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4911                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4912
4913                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4914                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4915                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4916
4917                 tmp = I915_READ(SOUTH_CHICKEN2);
4918                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4919                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4920
4921                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4922                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4923                                        100))
4924                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4925         }
4926
4927         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4928         tmp &= ~(0xFF << 24);
4929         tmp |= (0x12 << 24);
4930         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4931
4932         if (!is_sdv) {
4933                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4934                 tmp &= ~(0x3 << 6);
4935                 tmp |= (1 << 6) | (1 << 0);
4936                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4937         }
4938
4939         if (is_sdv) {
4940                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4941                 tmp |= 0x7FFF;
4942                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4943         }
4944
4945         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4946         tmp |= (1 << 11);
4947         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4948
4949         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4950         tmp |= (1 << 11);
4951         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4952
4953         if (is_sdv) {
4954                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4955                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4956                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4957
4958                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4959                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4960                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4961
4962                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4963                 tmp |= (0x3F << 8);
4964                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4965
4966                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4967                 tmp |= (0x3F << 8);
4968                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4969         }
4970
4971         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4972         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4973         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4974
4975         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4976         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4977         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4978
4979         if (!is_sdv) {
4980                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4981                 tmp &= ~(7 << 13);
4982                 tmp |= (5 << 13);
4983                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4984
4985                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4986                 tmp &= ~(7 << 13);
4987                 tmp |= (5 << 13);
4988                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4989         }
4990
4991         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4992         tmp &= ~0xFF;
4993         tmp |= 0x1C;
4994         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4995
4996         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4997         tmp &= ~0xFF;
4998         tmp |= 0x1C;
4999         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5000
5001         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5002         tmp &= ~(0xFF << 16);
5003         tmp |= (0x1C << 16);
5004         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5005
5006         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5007         tmp &= ~(0xFF << 16);
5008         tmp |= (0x1C << 16);
5009         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5010
5011         if (!is_sdv) {
5012                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5013                 tmp |= (1 << 27);
5014                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5015
5016                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5017                 tmp |= (1 << 27);
5018                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5019
5020                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5021                 tmp &= ~(0xF << 28);
5022                 tmp |= (4 << 28);
5023                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5024
5025                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5026                 tmp &= ~(0xF << 28);
5027                 tmp |= (4 << 28);
5028                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5029         }
5030
5031         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5032         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5033         tmp |= SBI_DBUFF0_ENABLE;
5034         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5035
5036         mutex_unlock(&dev_priv->dpio_lock);
5037 }
5038
5039 /*
5040  * Initialize reference clocks when the driver loads
5041  */
5042 void intel_init_pch_refclk(struct drm_device *dev)
5043 {
5044         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5045                 ironlake_init_pch_refclk(dev);
5046         else if (HAS_PCH_LPT(dev))
5047                 lpt_init_pch_refclk(dev);
5048 }
5049
5050 static int ironlake_get_refclk(struct drm_crtc *crtc)
5051 {
5052         struct drm_device *dev = crtc->dev;
5053         struct drm_i915_private *dev_priv = dev->dev_private;
5054         struct intel_encoder *encoder;
5055         struct intel_encoder *edp_encoder = NULL;
5056         int num_connectors = 0;
5057         bool is_lvds = false;
5058
5059         for_each_encoder_on_crtc(dev, crtc, encoder) {
5060                 switch (encoder->type) {
5061                 case INTEL_OUTPUT_LVDS:
5062                         is_lvds = true;
5063                         break;
5064                 case INTEL_OUTPUT_EDP:
5065                         edp_encoder = encoder;
5066                         break;
5067                 }
5068                 num_connectors++;
5069         }
5070
5071         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5072                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5073                               dev_priv->lvds_ssc_freq);
5074                 return dev_priv->lvds_ssc_freq * 1000;
5075         }
5076
5077         return 120000;
5078 }
5079
5080 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5081                                   struct drm_display_mode *adjusted_mode,
5082                                   bool dither)
5083 {
5084         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086         int pipe = intel_crtc->pipe;
5087         uint32_t val;
5088
5089         val = I915_READ(PIPECONF(pipe));
5090
5091         val &= ~PIPECONF_BPC_MASK;
5092         switch (intel_crtc->bpp) {
5093         case 18:
5094                 val |= PIPECONF_6BPC;
5095                 break;
5096         case 24:
5097                 val |= PIPECONF_8BPC;
5098                 break;
5099         case 30:
5100                 val |= PIPECONF_10BPC;
5101                 break;
5102         case 36:
5103                 val |= PIPECONF_12BPC;
5104                 break;
5105         default:
5106                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5107                 BUG();
5108         }
5109
5110         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5111         if (dither)
5112                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5113
5114         val &= ~PIPECONF_INTERLACE_MASK;
5115         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5116                 val |= PIPECONF_INTERLACED_ILK;
5117         else
5118                 val |= PIPECONF_PROGRESSIVE;
5119
5120         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5121                 val |= PIPECONF_COLOR_RANGE_SELECT;
5122         else
5123                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5124
5125         I915_WRITE(PIPECONF(pipe), val);
5126         POSTING_READ(PIPECONF(pipe));
5127 }
5128
5129 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5130                                  struct drm_display_mode *adjusted_mode,
5131                                  bool dither)
5132 {
5133         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5136         uint32_t val;
5137
5138         val = I915_READ(PIPECONF(cpu_transcoder));
5139
5140         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5141         if (dither)
5142                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5143
5144         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5145         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5146                 val |= PIPECONF_INTERLACED_ILK;
5147         else
5148                 val |= PIPECONF_PROGRESSIVE;
5149
5150         I915_WRITE(PIPECONF(cpu_transcoder), val);
5151         POSTING_READ(PIPECONF(cpu_transcoder));
5152 }
5153
5154 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5155                                     struct drm_display_mode *adjusted_mode,
5156                                     intel_clock_t *clock,
5157                                     bool *has_reduced_clock,
5158                                     intel_clock_t *reduced_clock)
5159 {
5160         struct drm_device *dev = crtc->dev;
5161         struct drm_i915_private *dev_priv = dev->dev_private;
5162         struct intel_encoder *intel_encoder;
5163         int refclk;
5164         const intel_limit_t *limit;
5165         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5166
5167         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5168                 switch (intel_encoder->type) {
5169                 case INTEL_OUTPUT_LVDS:
5170                         is_lvds = true;
5171                         break;
5172                 case INTEL_OUTPUT_SDVO:
5173                 case INTEL_OUTPUT_HDMI:
5174                         is_sdvo = true;
5175                         if (intel_encoder->needs_tv_clock)
5176                                 is_tv = true;
5177                         break;
5178                 case INTEL_OUTPUT_TVOUT:
5179                         is_tv = true;
5180                         break;
5181                 }
5182         }
5183
5184         refclk = ironlake_get_refclk(crtc);
5185
5186         /*
5187          * Returns a set of divisors for the desired target clock with the given
5188          * refclk, or FALSE.  The returned values represent the clock equation:
5189          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5190          */
5191         limit = intel_limit(crtc, refclk);
5192         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5193                               clock);
5194         if (!ret)
5195                 return false;
5196
5197         if (is_lvds && dev_priv->lvds_downclock_avail) {
5198                 /*
5199                  * Ensure we match the reduced clock's P to the target clock.
5200                  * If the clocks don't match, we can't switch the display clock
5201                  * by using the FP0/FP1. In such case we will disable the LVDS
5202                  * downclock feature.
5203                 */
5204                 *has_reduced_clock = limit->find_pll(limit, crtc,
5205                                                      dev_priv->lvds_downclock,
5206                                                      refclk,
5207                                                      clock,
5208                                                      reduced_clock);
5209         }
5210
5211         if (is_sdvo && is_tv)
5212                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5213
5214         return true;
5215 }
5216
5217 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5218 {
5219         struct drm_i915_private *dev_priv = dev->dev_private;
5220         uint32_t temp;
5221
5222         temp = I915_READ(SOUTH_CHICKEN1);
5223         if (temp & FDI_BC_BIFURCATION_SELECT)
5224                 return;
5225
5226         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5227         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5228
5229         temp |= FDI_BC_BIFURCATION_SELECT;
5230         DRM_DEBUG_KMS("enabling fdi C rx\n");
5231         I915_WRITE(SOUTH_CHICKEN1, temp);
5232         POSTING_READ(SOUTH_CHICKEN1);
5233 }
5234
5235 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5236 {
5237         struct drm_device *dev = intel_crtc->base.dev;
5238         struct drm_i915_private *dev_priv = dev->dev_private;
5239         struct intel_crtc *pipe_B_crtc =
5240                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5241
5242         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5243                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5244         if (intel_crtc->fdi_lanes > 4) {
5245                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5246                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5247                 /* Clamp lanes to avoid programming the hw with bogus values. */
5248                 intel_crtc->fdi_lanes = 4;
5249
5250                 return false;
5251         }
5252
5253         if (dev_priv->num_pipe == 2)
5254                 return true;
5255
5256         switch (intel_crtc->pipe) {
5257         case PIPE_A:
5258                 return true;
5259         case PIPE_B:
5260                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5261                     intel_crtc->fdi_lanes > 2) {
5262                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5263                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5264                         /* Clamp lanes to avoid programming the hw with bogus values. */
5265                         intel_crtc->fdi_lanes = 2;
5266
5267                         return false;
5268                 }
5269
5270                 if (intel_crtc->fdi_lanes > 2)
5271                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5272                 else
5273                         cpt_enable_fdi_bc_bifurcation(dev);
5274
5275                 return true;
5276         case PIPE_C:
5277                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5278                         if (intel_crtc->fdi_lanes > 2) {
5279                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5280                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5281                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5282                                 intel_crtc->fdi_lanes = 2;
5283
5284                                 return false;
5285                         }
5286                 } else {
5287                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5288                         return false;
5289                 }
5290
5291                 cpt_enable_fdi_bc_bifurcation(dev);
5292
5293                 return true;
5294         default:
5295                 BUG();
5296         }
5297 }
5298
5299 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5300 {
5301         /*
5302          * Account for spread spectrum to avoid
5303          * oversubscribing the link. Max center spread
5304          * is 2.5%; use 5% for safety's sake.
5305          */
5306         u32 bps = target_clock * bpp * 21 / 20;
5307         return bps / (link_bw * 8) + 1;
5308 }
5309
5310 static void ironlake_set_m_n(struct drm_crtc *crtc,
5311                              struct drm_display_mode *mode,
5312                              struct drm_display_mode *adjusted_mode)
5313 {
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5318         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5319         struct intel_link_m_n m_n = {0};
5320         int target_clock, pixel_multiplier, lane, link_bw;
5321         bool is_dp = false, is_cpu_edp = false;
5322
5323         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5324                 switch (intel_encoder->type) {
5325                 case INTEL_OUTPUT_DISPLAYPORT:
5326                         is_dp = true;
5327                         break;
5328                 case INTEL_OUTPUT_EDP:
5329                         is_dp = true;
5330                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5331                                 is_cpu_edp = true;
5332                         edp_encoder = intel_encoder;
5333                         break;
5334                 }
5335         }
5336
5337         /* FDI link */
5338         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5339         lane = 0;
5340         /* CPU eDP doesn't require FDI link, so just set DP M/N
5341            according to current link config */
5342         if (is_cpu_edp) {
5343                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5344         } else {
5345                 /* FDI is a binary signal running at ~2.7GHz, encoding
5346                  * each output octet as 10 bits. The actual frequency
5347                  * is stored as a divider into a 100MHz clock, and the
5348                  * mode pixel clock is stored in units of 1KHz.
5349                  * Hence the bw of each lane in terms of the mode signal
5350                  * is:
5351                  */
5352                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5353         }
5354
5355         /* [e]DP over FDI requires target mode clock instead of link clock. */
5356         if (edp_encoder)
5357                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5358         else if (is_dp)
5359                 target_clock = mode->clock;
5360         else
5361                 target_clock = adjusted_mode->clock;
5362
5363         if (!lane)
5364                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5365                                                    intel_crtc->bpp);
5366
5367         intel_crtc->fdi_lanes = lane;
5368
5369         if (pixel_multiplier > 1)
5370                 link_bw *= pixel_multiplier;
5371         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5372
5373         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5374         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5375         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5376         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5377 }
5378
5379 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5380                                       struct drm_display_mode *adjusted_mode,
5381                                       intel_clock_t *clock, u32 fp)
5382 {
5383         struct drm_crtc *crtc = &intel_crtc->base;
5384         struct drm_device *dev = crtc->dev;
5385         struct drm_i915_private *dev_priv = dev->dev_private;
5386         struct intel_encoder *intel_encoder;
5387         uint32_t dpll;
5388         int factor, pixel_multiplier, num_connectors = 0;
5389         bool is_lvds = false, is_sdvo = false, is_tv = false;
5390         bool is_dp = false, is_cpu_edp = false;
5391
5392         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5393                 switch (intel_encoder->type) {
5394                 case INTEL_OUTPUT_LVDS:
5395                         is_lvds = true;
5396                         break;
5397                 case INTEL_OUTPUT_SDVO:
5398                 case INTEL_OUTPUT_HDMI:
5399                         is_sdvo = true;
5400                         if (intel_encoder->needs_tv_clock)
5401                                 is_tv = true;
5402                         break;
5403                 case INTEL_OUTPUT_TVOUT:
5404                         is_tv = true;
5405                         break;
5406                 case INTEL_OUTPUT_DISPLAYPORT:
5407                         is_dp = true;
5408                         break;
5409                 case INTEL_OUTPUT_EDP:
5410                         is_dp = true;
5411                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5412                                 is_cpu_edp = true;
5413                         break;
5414                 }
5415
5416                 num_connectors++;
5417         }
5418
5419         /* Enable autotuning of the PLL clock (if permissible) */
5420         factor = 21;
5421         if (is_lvds) {
5422                 if ((intel_panel_use_ssc(dev_priv) &&
5423                      dev_priv->lvds_ssc_freq == 100) ||
5424                     intel_is_dual_link_lvds(dev))
5425                         factor = 25;
5426         } else if (is_sdvo && is_tv)
5427                 factor = 20;
5428
5429         if (clock->m < factor * clock->n)
5430                 fp |= FP_CB_TUNE;
5431
5432         dpll = 0;
5433
5434         if (is_lvds)
5435                 dpll |= DPLLB_MODE_LVDS;
5436         else
5437                 dpll |= DPLLB_MODE_DAC_SERIAL;
5438         if (is_sdvo) {
5439                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5440                 if (pixel_multiplier > 1) {
5441                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5442                 }
5443                 dpll |= DPLL_DVO_HIGH_SPEED;
5444         }
5445         if (is_dp && !is_cpu_edp)
5446                 dpll |= DPLL_DVO_HIGH_SPEED;
5447
5448         /* compute bitmask from p1 value */
5449         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5450         /* also FPA1 */
5451         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5452
5453         switch (clock->p2) {
5454         case 5:
5455                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5456                 break;
5457         case 7:
5458                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5459                 break;
5460         case 10:
5461                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5462                 break;
5463         case 14:
5464                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5465                 break;
5466         }
5467
5468         if (is_sdvo && is_tv)
5469                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5470         else if (is_tv)
5471                 /* XXX: just matching BIOS for now */
5472                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5473                 dpll |= 3;
5474         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5475                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5476         else
5477                 dpll |= PLL_REF_INPUT_DREFCLK;
5478
5479         return dpll;
5480 }
5481
5482 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5483                                   struct drm_display_mode *mode,
5484                                   struct drm_display_mode *adjusted_mode,
5485                                   int x, int y,
5486                                   struct drm_framebuffer *fb)
5487 {
5488         struct drm_device *dev = crtc->dev;
5489         struct drm_i915_private *dev_priv = dev->dev_private;
5490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5491         int pipe = intel_crtc->pipe;
5492         int plane = intel_crtc->plane;
5493         int num_connectors = 0;
5494         intel_clock_t clock, reduced_clock;
5495         u32 dpll, fp = 0, fp2 = 0;
5496         bool ok, has_reduced_clock = false;
5497         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5498         struct intel_encoder *encoder;
5499         int ret;
5500         bool dither, fdi_config_ok;
5501
5502         for_each_encoder_on_crtc(dev, crtc, encoder) {
5503                 switch (encoder->type) {
5504                 case INTEL_OUTPUT_LVDS:
5505                         is_lvds = true;
5506                         break;
5507                 case INTEL_OUTPUT_DISPLAYPORT:
5508                         is_dp = true;
5509                         break;
5510                 case INTEL_OUTPUT_EDP:
5511                         is_dp = true;
5512                         if (!intel_encoder_is_pch_edp(&encoder->base))
5513                                 is_cpu_edp = true;
5514                         break;
5515                 }
5516
5517                 num_connectors++;
5518         }
5519
5520         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5521              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5522
5523         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5524                                      &has_reduced_clock, &reduced_clock);
5525         if (!ok) {
5526                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5527                 return -EINVAL;
5528         }
5529
5530         /* Ensure that the cursor is valid for the new mode before changing... */
5531         intel_crtc_update_cursor(crtc, true);
5532
5533         /* determine panel color depth */
5534         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5535                                               adjusted_mode);
5536         if (is_lvds && dev_priv->lvds_dither)
5537                 dither = true;
5538
5539         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5540         if (has_reduced_clock)
5541                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5542                         reduced_clock.m2;
5543
5544         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5545
5546         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5547         drm_mode_debug_printmodeline(mode);
5548
5549         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5550         if (!is_cpu_edp) {
5551                 struct intel_pch_pll *pll;
5552
5553                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5554                 if (pll == NULL) {
5555                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5556                                          pipe);
5557                         return -EINVAL;
5558                 }
5559         } else
5560                 intel_put_pch_pll(intel_crtc);
5561
5562         if (is_dp && !is_cpu_edp)
5563                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5564
5565         for_each_encoder_on_crtc(dev, crtc, encoder)
5566                 if (encoder->pre_pll_enable)
5567                         encoder->pre_pll_enable(encoder);
5568
5569         if (intel_crtc->pch_pll) {
5570                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5571
5572                 /* Wait for the clocks to stabilize. */
5573                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5574                 udelay(150);
5575
5576                 /* The pixel multiplier can only be updated once the
5577                  * DPLL is enabled and the clocks are stable.
5578                  *
5579                  * So write it again.
5580                  */
5581                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5582         }
5583
5584         intel_crtc->lowfreq_avail = false;
5585         if (intel_crtc->pch_pll) {
5586                 if (is_lvds && has_reduced_clock && i915_powersave) {
5587                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5588                         intel_crtc->lowfreq_avail = true;
5589                 } else {
5590                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5591                 }
5592         }
5593
5594         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5595
5596         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5597          * ironlake_check_fdi_lanes. */
5598         ironlake_set_m_n(crtc, mode, adjusted_mode);
5599
5600         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5601
5602         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5603
5604         intel_wait_for_vblank(dev, pipe);
5605
5606         /* Set up the display plane register */
5607         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5608         POSTING_READ(DSPCNTR(plane));
5609
5610         ret = intel_pipe_set_base(crtc, x, y, fb);
5611
5612         intel_update_watermarks(dev);
5613
5614         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5615
5616         return fdi_config_ok ? ret : -EINVAL;
5617 }
5618
5619 static void haswell_modeset_global_resources(struct drm_device *dev)
5620 {
5621         struct drm_i915_private *dev_priv = dev->dev_private;
5622         bool enable = false;
5623         struct intel_crtc *crtc;
5624         struct intel_encoder *encoder;
5625
5626         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5627                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5628                         enable = true;
5629                 /* XXX: Should check for edp transcoder here, but thanks to init
5630                  * sequence that's not yet available. Just in case desktop eDP
5631                  * on PORT D is possible on haswell, too. */
5632         }
5633
5634         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5635                             base.head) {
5636                 if (encoder->type != INTEL_OUTPUT_EDP &&
5637                     encoder->connectors_active)
5638                         enable = true;
5639         }
5640
5641         /* Even the eDP panel fitter is outside the always-on well. */
5642         if (dev_priv->pch_pf_size)
5643                 enable = true;
5644
5645         intel_set_power_well(dev, enable);
5646 }
5647
5648 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5649                                  struct drm_display_mode *mode,
5650                                  struct drm_display_mode *adjusted_mode,
5651                                  int x, int y,
5652                                  struct drm_framebuffer *fb)
5653 {
5654         struct drm_device *dev = crtc->dev;
5655         struct drm_i915_private *dev_priv = dev->dev_private;
5656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5657         int pipe = intel_crtc->pipe;
5658         int plane = intel_crtc->plane;
5659         int num_connectors = 0;
5660         bool is_dp = false, is_cpu_edp = false;
5661         struct intel_encoder *encoder;
5662         int ret;
5663         bool dither;
5664
5665         for_each_encoder_on_crtc(dev, crtc, encoder) {
5666                 switch (encoder->type) {
5667                 case INTEL_OUTPUT_DISPLAYPORT:
5668                         is_dp = true;
5669                         break;
5670                 case INTEL_OUTPUT_EDP:
5671                         is_dp = true;
5672                         if (!intel_encoder_is_pch_edp(&encoder->base))
5673                                 is_cpu_edp = true;
5674                         break;
5675                 }
5676
5677                 num_connectors++;
5678         }
5679
5680         /* We are not sure yet this won't happen. */
5681         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5682              INTEL_PCH_TYPE(dev));
5683
5684         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5685              num_connectors, pipe_name(pipe));
5686
5687         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5688                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5689
5690         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5691
5692         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5693                 return -EINVAL;
5694
5695         /* Ensure that the cursor is valid for the new mode before changing... */
5696         intel_crtc_update_cursor(crtc, true);
5697
5698         /* determine panel color depth */
5699         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5700                                               adjusted_mode);
5701
5702         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5703         drm_mode_debug_printmodeline(mode);
5704
5705         if (is_dp && !is_cpu_edp)
5706                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5707
5708         intel_crtc->lowfreq_avail = false;
5709
5710         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5711
5712         if (!is_dp || is_cpu_edp)
5713                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5714
5715         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5716
5717         /* Set up the display plane register */
5718         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5719         POSTING_READ(DSPCNTR(plane));
5720
5721         ret = intel_pipe_set_base(crtc, x, y, fb);
5722
5723         intel_update_watermarks(dev);
5724
5725         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5726
5727         return ret;
5728 }
5729
5730 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5731                                struct drm_display_mode *mode,
5732                                struct drm_display_mode *adjusted_mode,
5733                                int x, int y,
5734                                struct drm_framebuffer *fb)
5735 {
5736         struct drm_device *dev = crtc->dev;
5737         struct drm_i915_private *dev_priv = dev->dev_private;
5738         struct drm_encoder_helper_funcs *encoder_funcs;
5739         struct intel_encoder *encoder;
5740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5741         int pipe = intel_crtc->pipe;
5742         int ret;
5743
5744         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5745                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5746         else
5747                 intel_crtc->cpu_transcoder = pipe;
5748
5749         drm_vblank_pre_modeset(dev, pipe);
5750
5751         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5752                                               x, y, fb);
5753         drm_vblank_post_modeset(dev, pipe);
5754
5755         if (ret != 0)
5756                 return ret;
5757
5758         for_each_encoder_on_crtc(dev, crtc, encoder) {
5759                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5760                         encoder->base.base.id,
5761                         drm_get_encoder_name(&encoder->base),
5762                         mode->base.id, mode->name);
5763                 encoder_funcs = encoder->base.helper_private;
5764                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5765         }
5766
5767         return 0;
5768 }
5769
5770 static bool intel_eld_uptodate(struct drm_connector *connector,
5771                                int reg_eldv, uint32_t bits_eldv,
5772                                int reg_elda, uint32_t bits_elda,
5773                                int reg_edid)
5774 {
5775         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5776         uint8_t *eld = connector->eld;
5777         uint32_t i;
5778
5779         i = I915_READ(reg_eldv);
5780         i &= bits_eldv;
5781
5782         if (!eld[0])
5783                 return !i;
5784
5785         if (!i)
5786                 return false;
5787
5788         i = I915_READ(reg_elda);
5789         i &= ~bits_elda;
5790         I915_WRITE(reg_elda, i);
5791
5792         for (i = 0; i < eld[2]; i++)
5793                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5794                         return false;
5795
5796         return true;
5797 }
5798
5799 static void g4x_write_eld(struct drm_connector *connector,
5800                           struct drm_crtc *crtc)
5801 {
5802         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5803         uint8_t *eld = connector->eld;
5804         uint32_t eldv;
5805         uint32_t len;
5806         uint32_t i;
5807
5808         i = I915_READ(G4X_AUD_VID_DID);
5809
5810         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5811                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5812         else
5813                 eldv = G4X_ELDV_DEVCTG;
5814
5815         if (intel_eld_uptodate(connector,
5816                                G4X_AUD_CNTL_ST, eldv,
5817                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5818                                G4X_HDMIW_HDMIEDID))
5819                 return;
5820
5821         i = I915_READ(G4X_AUD_CNTL_ST);
5822         i &= ~(eldv | G4X_ELD_ADDR);
5823         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5824         I915_WRITE(G4X_AUD_CNTL_ST, i);
5825
5826         if (!eld[0])
5827                 return;
5828
5829         len = min_t(uint8_t, eld[2], len);
5830         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5831         for (i = 0; i < len; i++)
5832                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5833
5834         i = I915_READ(G4X_AUD_CNTL_ST);
5835         i |= eldv;
5836         I915_WRITE(G4X_AUD_CNTL_ST, i);
5837 }
5838
5839 static void haswell_write_eld(struct drm_connector *connector,
5840                                      struct drm_crtc *crtc)
5841 {
5842         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843         uint8_t *eld = connector->eld;
5844         struct drm_device *dev = crtc->dev;
5845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5846         uint32_t eldv;
5847         uint32_t i;
5848         int len;
5849         int pipe = to_intel_crtc(crtc)->pipe;
5850         int tmp;
5851
5852         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5853         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5854         int aud_config = HSW_AUD_CFG(pipe);
5855         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5856
5857
5858         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5859
5860         /* Audio output enable */
5861         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5862         tmp = I915_READ(aud_cntrl_st2);
5863         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5864         I915_WRITE(aud_cntrl_st2, tmp);
5865
5866         /* Wait for 1 vertical blank */
5867         intel_wait_for_vblank(dev, pipe);
5868
5869         /* Set ELD valid state */
5870         tmp = I915_READ(aud_cntrl_st2);
5871         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5872         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5873         I915_WRITE(aud_cntrl_st2, tmp);
5874         tmp = I915_READ(aud_cntrl_st2);
5875         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5876
5877         /* Enable HDMI mode */
5878         tmp = I915_READ(aud_config);
5879         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5880         /* clear N_programing_enable and N_value_index */
5881         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5882         I915_WRITE(aud_config, tmp);
5883
5884         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5885
5886         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5887         intel_crtc->eld_vld = true;
5888
5889         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5890                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5891                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5892                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5893         } else
5894                 I915_WRITE(aud_config, 0);
5895
5896         if (intel_eld_uptodate(connector,
5897                                aud_cntrl_st2, eldv,
5898                                aud_cntl_st, IBX_ELD_ADDRESS,
5899                                hdmiw_hdmiedid))
5900                 return;
5901
5902         i = I915_READ(aud_cntrl_st2);
5903         i &= ~eldv;
5904         I915_WRITE(aud_cntrl_st2, i);
5905
5906         if (!eld[0])
5907                 return;
5908
5909         i = I915_READ(aud_cntl_st);
5910         i &= ~IBX_ELD_ADDRESS;
5911         I915_WRITE(aud_cntl_st, i);
5912         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5913         DRM_DEBUG_DRIVER("port num:%d\n", i);
5914
5915         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5916         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5917         for (i = 0; i < len; i++)
5918                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5919
5920         i = I915_READ(aud_cntrl_st2);
5921         i |= eldv;
5922         I915_WRITE(aud_cntrl_st2, i);
5923
5924 }
5925
5926 static void ironlake_write_eld(struct drm_connector *connector,
5927                                      struct drm_crtc *crtc)
5928 {
5929         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5930         uint8_t *eld = connector->eld;
5931         uint32_t eldv;
5932         uint32_t i;
5933         int len;
5934         int hdmiw_hdmiedid;
5935         int aud_config;
5936         int aud_cntl_st;
5937         int aud_cntrl_st2;
5938         int pipe = to_intel_crtc(crtc)->pipe;
5939
5940         if (HAS_PCH_IBX(connector->dev)) {
5941                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5942                 aud_config = IBX_AUD_CFG(pipe);
5943                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5944                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5945         } else {
5946                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5947                 aud_config = CPT_AUD_CFG(pipe);
5948                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5949                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5950         }
5951
5952         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5953
5954         i = I915_READ(aud_cntl_st);
5955         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5956         if (!i) {
5957                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5958                 /* operate blindly on all ports */
5959                 eldv = IBX_ELD_VALIDB;
5960                 eldv |= IBX_ELD_VALIDB << 4;
5961                 eldv |= IBX_ELD_VALIDB << 8;
5962         } else {
5963                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5964                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5965         }
5966
5967         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5968                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5969                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5970                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5971         } else
5972                 I915_WRITE(aud_config, 0);
5973
5974         if (intel_eld_uptodate(connector,
5975                                aud_cntrl_st2, eldv,
5976                                aud_cntl_st, IBX_ELD_ADDRESS,
5977                                hdmiw_hdmiedid))
5978                 return;
5979
5980         i = I915_READ(aud_cntrl_st2);
5981         i &= ~eldv;
5982         I915_WRITE(aud_cntrl_st2, i);
5983
5984         if (!eld[0])
5985                 return;
5986
5987         i = I915_READ(aud_cntl_st);
5988         i &= ~IBX_ELD_ADDRESS;
5989         I915_WRITE(aud_cntl_st, i);
5990
5991         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5992         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5993         for (i = 0; i < len; i++)
5994                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5995
5996         i = I915_READ(aud_cntrl_st2);
5997         i |= eldv;
5998         I915_WRITE(aud_cntrl_st2, i);
5999 }
6000
6001 void intel_write_eld(struct drm_encoder *encoder,
6002                      struct drm_display_mode *mode)
6003 {
6004         struct drm_crtc *crtc = encoder->crtc;
6005         struct drm_connector *connector;
6006         struct drm_device *dev = encoder->dev;
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008
6009         connector = drm_select_eld(encoder, mode);
6010         if (!connector)
6011                 return;
6012
6013         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6014                          connector->base.id,
6015                          drm_get_connector_name(connector),
6016                          connector->encoder->base.id,
6017                          drm_get_encoder_name(connector->encoder));
6018
6019         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6020
6021         if (dev_priv->display.write_eld)
6022                 dev_priv->display.write_eld(connector, crtc);
6023 }
6024
6025 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6026 void intel_crtc_load_lut(struct drm_crtc *crtc)
6027 {
6028         struct drm_device *dev = crtc->dev;
6029         struct drm_i915_private *dev_priv = dev->dev_private;
6030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031         int palreg = PALETTE(intel_crtc->pipe);
6032         int i;
6033
6034         /* The clocks have to be on to load the palette. */
6035         if (!crtc->enabled || !intel_crtc->active)
6036                 return;
6037
6038         /* use legacy palette for Ironlake */
6039         if (HAS_PCH_SPLIT(dev))
6040                 palreg = LGC_PALETTE(intel_crtc->pipe);
6041
6042         for (i = 0; i < 256; i++) {
6043                 I915_WRITE(palreg + 4 * i,
6044                            (intel_crtc->lut_r[i] << 16) |
6045                            (intel_crtc->lut_g[i] << 8) |
6046                            intel_crtc->lut_b[i]);
6047         }
6048 }
6049
6050 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6051 {
6052         struct drm_device *dev = crtc->dev;
6053         struct drm_i915_private *dev_priv = dev->dev_private;
6054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055         bool visible = base != 0;
6056         u32 cntl;
6057
6058         if (intel_crtc->cursor_visible == visible)
6059                 return;
6060
6061         cntl = I915_READ(_CURACNTR);
6062         if (visible) {
6063                 /* On these chipsets we can only modify the base whilst
6064                  * the cursor is disabled.
6065                  */
6066                 I915_WRITE(_CURABASE, base);
6067
6068                 cntl &= ~(CURSOR_FORMAT_MASK);
6069                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6070                 cntl |= CURSOR_ENABLE |
6071                         CURSOR_GAMMA_ENABLE |
6072                         CURSOR_FORMAT_ARGB;
6073         } else
6074                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6075         I915_WRITE(_CURACNTR, cntl);
6076
6077         intel_crtc->cursor_visible = visible;
6078 }
6079
6080 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6081 {
6082         struct drm_device *dev = crtc->dev;
6083         struct drm_i915_private *dev_priv = dev->dev_private;
6084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6085         int pipe = intel_crtc->pipe;
6086         bool visible = base != 0;
6087
6088         if (intel_crtc->cursor_visible != visible) {
6089                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6090                 if (base) {
6091                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6092                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6093                         cntl |= pipe << 28; /* Connect to correct pipe */
6094                 } else {
6095                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6096                         cntl |= CURSOR_MODE_DISABLE;
6097                 }
6098                 I915_WRITE(CURCNTR(pipe), cntl);
6099
6100                 intel_crtc->cursor_visible = visible;
6101         }
6102         /* and commit changes on next vblank */
6103         I915_WRITE(CURBASE(pipe), base);
6104 }
6105
6106 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6107 {
6108         struct drm_device *dev = crtc->dev;
6109         struct drm_i915_private *dev_priv = dev->dev_private;
6110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6111         int pipe = intel_crtc->pipe;
6112         bool visible = base != 0;
6113
6114         if (intel_crtc->cursor_visible != visible) {
6115                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6116                 if (base) {
6117                         cntl &= ~CURSOR_MODE;
6118                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6119                 } else {
6120                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6121                         cntl |= CURSOR_MODE_DISABLE;
6122                 }
6123                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6124
6125                 intel_crtc->cursor_visible = visible;
6126         }
6127         /* and commit changes on next vblank */
6128         I915_WRITE(CURBASE_IVB(pipe), base);
6129 }
6130
6131 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6132 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6133                                      bool on)
6134 {
6135         struct drm_device *dev = crtc->dev;
6136         struct drm_i915_private *dev_priv = dev->dev_private;
6137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138         int pipe = intel_crtc->pipe;
6139         int x = intel_crtc->cursor_x;
6140         int y = intel_crtc->cursor_y;
6141         u32 base, pos;
6142         bool visible;
6143
6144         pos = 0;
6145
6146         if (on && crtc->enabled && crtc->fb) {
6147                 base = intel_crtc->cursor_addr;
6148                 if (x > (int) crtc->fb->width)
6149                         base = 0;
6150
6151                 if (y > (int) crtc->fb->height)
6152                         base = 0;
6153         } else
6154                 base = 0;
6155
6156         if (x < 0) {
6157                 if (x + intel_crtc->cursor_width < 0)
6158                         base = 0;
6159
6160                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6161                 x = -x;
6162         }
6163         pos |= x << CURSOR_X_SHIFT;
6164
6165         if (y < 0) {
6166                 if (y + intel_crtc->cursor_height < 0)
6167                         base = 0;
6168
6169                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6170                 y = -y;
6171         }
6172         pos |= y << CURSOR_Y_SHIFT;
6173
6174         visible = base != 0;
6175         if (!visible && !intel_crtc->cursor_visible)
6176                 return;
6177
6178         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6179                 I915_WRITE(CURPOS_IVB(pipe), pos);
6180                 ivb_update_cursor(crtc, base);
6181         } else {
6182                 I915_WRITE(CURPOS(pipe), pos);
6183                 if (IS_845G(dev) || IS_I865G(dev))
6184                         i845_update_cursor(crtc, base);
6185                 else
6186                         i9xx_update_cursor(crtc, base);
6187         }
6188 }
6189
6190 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6191                                  struct drm_file *file,
6192                                  uint32_t handle,
6193                                  uint32_t width, uint32_t height)
6194 {
6195         struct drm_device *dev = crtc->dev;
6196         struct drm_i915_private *dev_priv = dev->dev_private;
6197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198         struct drm_i915_gem_object *obj;
6199         uint32_t addr;
6200         int ret;
6201
6202         /* if we want to turn off the cursor ignore width and height */
6203         if (!handle) {
6204                 DRM_DEBUG_KMS("cursor off\n");
6205                 addr = 0;
6206                 obj = NULL;
6207                 mutex_lock(&dev->struct_mutex);
6208                 goto finish;
6209         }
6210
6211         /* Currently we only support 64x64 cursors */
6212         if (width != 64 || height != 64) {
6213                 DRM_ERROR("we currently only support 64x64 cursors\n");
6214                 return -EINVAL;
6215         }
6216
6217         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6218         if (&obj->base == NULL)
6219                 return -ENOENT;
6220
6221         if (obj->base.size < width * height * 4) {
6222                 DRM_ERROR("buffer is to small\n");
6223                 ret = -ENOMEM;
6224                 goto fail;
6225         }
6226
6227         /* we only need to pin inside GTT if cursor is non-phy */
6228         mutex_lock(&dev->struct_mutex);
6229         if (!dev_priv->info->cursor_needs_physical) {
6230                 if (obj->tiling_mode) {
6231                         DRM_ERROR("cursor cannot be tiled\n");
6232                         ret = -EINVAL;
6233                         goto fail_locked;
6234                 }
6235
6236                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6237                 if (ret) {
6238                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6239                         goto fail_locked;
6240                 }
6241
6242                 ret = i915_gem_object_put_fence(obj);
6243                 if (ret) {
6244                         DRM_ERROR("failed to release fence for cursor");
6245                         goto fail_unpin;
6246                 }
6247
6248                 addr = obj->gtt_offset;
6249         } else {
6250                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6251                 ret = i915_gem_attach_phys_object(dev, obj,
6252                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6253                                                   align);
6254                 if (ret) {
6255                         DRM_ERROR("failed to attach phys object\n");
6256                         goto fail_locked;
6257                 }
6258                 addr = obj->phys_obj->handle->busaddr;
6259         }
6260
6261         if (IS_GEN2(dev))
6262                 I915_WRITE(CURSIZE, (height << 12) | width);
6263
6264  finish:
6265         if (intel_crtc->cursor_bo) {
6266                 if (dev_priv->info->cursor_needs_physical) {
6267                         if (intel_crtc->cursor_bo != obj)
6268                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6269                 } else
6270                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6271                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6272         }
6273
6274         mutex_unlock(&dev->struct_mutex);
6275
6276         intel_crtc->cursor_addr = addr;
6277         intel_crtc->cursor_bo = obj;
6278         intel_crtc->cursor_width = width;
6279         intel_crtc->cursor_height = height;
6280
6281         intel_crtc_update_cursor(crtc, true);
6282
6283         return 0;
6284 fail_unpin:
6285         i915_gem_object_unpin(obj);
6286 fail_locked:
6287         mutex_unlock(&dev->struct_mutex);
6288 fail:
6289         drm_gem_object_unreference_unlocked(&obj->base);
6290         return ret;
6291 }
6292
6293 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6294 {
6295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6296
6297         intel_crtc->cursor_x = x;
6298         intel_crtc->cursor_y = y;
6299
6300         intel_crtc_update_cursor(crtc, true);
6301
6302         return 0;
6303 }
6304
6305 /** Sets the color ramps on behalf of RandR */
6306 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6307                                  u16 blue, int regno)
6308 {
6309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6310
6311         intel_crtc->lut_r[regno] = red >> 8;
6312         intel_crtc->lut_g[regno] = green >> 8;
6313         intel_crtc->lut_b[regno] = blue >> 8;
6314 }
6315
6316 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6317                              u16 *blue, int regno)
6318 {
6319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6320
6321         *red = intel_crtc->lut_r[regno] << 8;
6322         *green = intel_crtc->lut_g[regno] << 8;
6323         *blue = intel_crtc->lut_b[regno] << 8;
6324 }
6325
6326 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6327                                  u16 *blue, uint32_t start, uint32_t size)
6328 {
6329         int end = (start + size > 256) ? 256 : start + size, i;
6330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331
6332         for (i = start; i < end; i++) {
6333                 intel_crtc->lut_r[i] = red[i] >> 8;
6334                 intel_crtc->lut_g[i] = green[i] >> 8;
6335                 intel_crtc->lut_b[i] = blue[i] >> 8;
6336         }
6337
6338         intel_crtc_load_lut(crtc);
6339 }
6340
6341 /**
6342  * Get a pipe with a simple mode set on it for doing load-based monitor
6343  * detection.
6344  *
6345  * It will be up to the load-detect code to adjust the pipe as appropriate for
6346  * its requirements.  The pipe will be connected to no other encoders.
6347  *
6348  * Currently this code will only succeed if there is a pipe with no encoders
6349  * configured for it.  In the future, it could choose to temporarily disable
6350  * some outputs to free up a pipe for its use.
6351  *
6352  * \return crtc, or NULL if no pipes are available.
6353  */
6354
6355 /* VESA 640x480x72Hz mode to set on the pipe */
6356 static struct drm_display_mode load_detect_mode = {
6357         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6358                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6359 };
6360
6361 static struct drm_framebuffer *
6362 intel_framebuffer_create(struct drm_device *dev,
6363                          struct drm_mode_fb_cmd2 *mode_cmd,
6364                          struct drm_i915_gem_object *obj)
6365 {
6366         struct intel_framebuffer *intel_fb;
6367         int ret;
6368
6369         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6370         if (!intel_fb) {
6371                 drm_gem_object_unreference_unlocked(&obj->base);
6372                 return ERR_PTR(-ENOMEM);
6373         }
6374
6375         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6376         if (ret) {
6377                 drm_gem_object_unreference_unlocked(&obj->base);
6378                 kfree(intel_fb);
6379                 return ERR_PTR(ret);
6380         }
6381
6382         return &intel_fb->base;
6383 }
6384
6385 static u32
6386 intel_framebuffer_pitch_for_width(int width, int bpp)
6387 {
6388         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6389         return ALIGN(pitch, 64);
6390 }
6391
6392 static u32
6393 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6394 {
6395         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6396         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6397 }
6398
6399 static struct drm_framebuffer *
6400 intel_framebuffer_create_for_mode(struct drm_device *dev,
6401                                   struct drm_display_mode *mode,
6402                                   int depth, int bpp)
6403 {
6404         struct drm_i915_gem_object *obj;
6405         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6406
6407         obj = i915_gem_alloc_object(dev,
6408                                     intel_framebuffer_size_for_mode(mode, bpp));
6409         if (obj == NULL)
6410                 return ERR_PTR(-ENOMEM);
6411
6412         mode_cmd.width = mode->hdisplay;
6413         mode_cmd.height = mode->vdisplay;
6414         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6415                                                                 bpp);
6416         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6417
6418         return intel_framebuffer_create(dev, &mode_cmd, obj);
6419 }
6420
6421 static struct drm_framebuffer *
6422 mode_fits_in_fbdev(struct drm_device *dev,
6423                    struct drm_display_mode *mode)
6424 {
6425         struct drm_i915_private *dev_priv = dev->dev_private;
6426         struct drm_i915_gem_object *obj;
6427         struct drm_framebuffer *fb;
6428
6429         if (dev_priv->fbdev == NULL)
6430                 return NULL;
6431
6432         obj = dev_priv->fbdev->ifb.obj;
6433         if (obj == NULL)
6434                 return NULL;
6435
6436         fb = &dev_priv->fbdev->ifb.base;
6437         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6438                                                                fb->bits_per_pixel))
6439                 return NULL;
6440
6441         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6442                 return NULL;
6443
6444         return fb;
6445 }
6446
6447 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6448                                 struct drm_display_mode *mode,
6449                                 struct intel_load_detect_pipe *old)
6450 {
6451         struct intel_crtc *intel_crtc;
6452         struct intel_encoder *intel_encoder =
6453                 intel_attached_encoder(connector);
6454         struct drm_crtc *possible_crtc;
6455         struct drm_encoder *encoder = &intel_encoder->base;
6456         struct drm_crtc *crtc = NULL;
6457         struct drm_device *dev = encoder->dev;
6458         struct drm_framebuffer *fb;
6459         int i = -1;
6460
6461         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6462                       connector->base.id, drm_get_connector_name(connector),
6463                       encoder->base.id, drm_get_encoder_name(encoder));
6464
6465         /*
6466          * Algorithm gets a little messy:
6467          *
6468          *   - if the connector already has an assigned crtc, use it (but make
6469          *     sure it's on first)
6470          *
6471          *   - try to find the first unused crtc that can drive this connector,
6472          *     and use that if we find one
6473          */
6474
6475         /* See if we already have a CRTC for this connector */
6476         if (encoder->crtc) {
6477                 crtc = encoder->crtc;
6478
6479                 mutex_lock(&crtc->mutex);
6480
6481                 old->dpms_mode = connector->dpms;
6482                 old->load_detect_temp = false;
6483
6484                 /* Make sure the crtc and connector are running */
6485                 if (connector->dpms != DRM_MODE_DPMS_ON)
6486                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6487
6488                 return true;
6489         }
6490
6491         /* Find an unused one (if possible) */
6492         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6493                 i++;
6494                 if (!(encoder->possible_crtcs & (1 << i)))
6495                         continue;
6496                 if (!possible_crtc->enabled) {
6497                         crtc = possible_crtc;
6498                         break;
6499                 }
6500         }
6501
6502         /*
6503          * If we didn't find an unused CRTC, don't use any.
6504          */
6505         if (!crtc) {
6506                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6507                 return false;
6508         }
6509
6510         mutex_lock(&crtc->mutex);
6511         intel_encoder->new_crtc = to_intel_crtc(crtc);
6512         to_intel_connector(connector)->new_encoder = intel_encoder;
6513
6514         intel_crtc = to_intel_crtc(crtc);
6515         old->dpms_mode = connector->dpms;
6516         old->load_detect_temp = true;
6517         old->release_fb = NULL;
6518
6519         if (!mode)
6520                 mode = &load_detect_mode;
6521
6522         /* We need a framebuffer large enough to accommodate all accesses
6523          * that the plane may generate whilst we perform load detection.
6524          * We can not rely on the fbcon either being present (we get called
6525          * during its initialisation to detect all boot displays, or it may
6526          * not even exist) or that it is large enough to satisfy the
6527          * requested mode.
6528          */
6529         fb = mode_fits_in_fbdev(dev, mode);
6530         if (fb == NULL) {
6531                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6532                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6533                 old->release_fb = fb;
6534         } else
6535                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6536         if (IS_ERR(fb)) {
6537                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6538                 mutex_unlock(&crtc->mutex);
6539                 return false;
6540         }
6541
6542         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6543                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6544                 if (old->release_fb)
6545                         old->release_fb->funcs->destroy(old->release_fb);
6546                 mutex_unlock(&crtc->mutex);
6547                 return false;
6548         }
6549
6550         /* let the connector get through one full cycle before testing */
6551         intel_wait_for_vblank(dev, intel_crtc->pipe);
6552         return true;
6553 }
6554
6555 void intel_release_load_detect_pipe(struct drm_connector *connector,
6556                                     struct intel_load_detect_pipe *old)
6557 {
6558         struct intel_encoder *intel_encoder =
6559                 intel_attached_encoder(connector);
6560         struct drm_encoder *encoder = &intel_encoder->base;
6561         struct drm_crtc *crtc = encoder->crtc;
6562
6563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6564                       connector->base.id, drm_get_connector_name(connector),
6565                       encoder->base.id, drm_get_encoder_name(encoder));
6566
6567         if (old->load_detect_temp) {
6568                 to_intel_connector(connector)->new_encoder = NULL;
6569                 intel_encoder->new_crtc = NULL;
6570                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6571
6572                 if (old->release_fb) {
6573                         drm_framebuffer_unregister_private(old->release_fb);
6574                         drm_framebuffer_unreference(old->release_fb);
6575                 }
6576
6577                 mutex_unlock(&crtc->mutex);
6578                 return;
6579         }
6580
6581         /* Switch crtc and encoder back off if necessary */
6582         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6583                 connector->funcs->dpms(connector, old->dpms_mode);
6584
6585         mutex_unlock(&crtc->mutex);
6586 }
6587
6588 /* Returns the clock of the currently programmed mode of the given pipe. */
6589 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6590 {
6591         struct drm_i915_private *dev_priv = dev->dev_private;
6592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6593         int pipe = intel_crtc->pipe;
6594         u32 dpll = I915_READ(DPLL(pipe));
6595         u32 fp;
6596         intel_clock_t clock;
6597
6598         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6599                 fp = I915_READ(FP0(pipe));
6600         else
6601                 fp = I915_READ(FP1(pipe));
6602
6603         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6604         if (IS_PINEVIEW(dev)) {
6605                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6606                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6607         } else {
6608                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6609                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6610         }
6611
6612         if (!IS_GEN2(dev)) {
6613                 if (IS_PINEVIEW(dev))
6614                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6615                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6616                 else
6617                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6618                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6619
6620                 switch (dpll & DPLL_MODE_MASK) {
6621                 case DPLLB_MODE_DAC_SERIAL:
6622                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6623                                 5 : 10;
6624                         break;
6625                 case DPLLB_MODE_LVDS:
6626                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6627                                 7 : 14;
6628                         break;
6629                 default:
6630                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6631                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6632                         return 0;
6633                 }
6634
6635                 /* XXX: Handle the 100Mhz refclk */
6636                 intel_clock(dev, 96000, &clock);
6637         } else {
6638                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6639
6640                 if (is_lvds) {
6641                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6642                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6643                         clock.p2 = 14;
6644
6645                         if ((dpll & PLL_REF_INPUT_MASK) ==
6646                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6647                                 /* XXX: might not be 66MHz */
6648                                 intel_clock(dev, 66000, &clock);
6649                         } else
6650                                 intel_clock(dev, 48000, &clock);
6651                 } else {
6652                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6653                                 clock.p1 = 2;
6654                         else {
6655                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6656                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6657                         }
6658                         if (dpll & PLL_P2_DIVIDE_BY_4)
6659                                 clock.p2 = 4;
6660                         else
6661                                 clock.p2 = 2;
6662
6663                         intel_clock(dev, 48000, &clock);
6664                 }
6665         }
6666
6667         /* XXX: It would be nice to validate the clocks, but we can't reuse
6668          * i830PllIsValid() because it relies on the xf86_config connector
6669          * configuration being accurate, which it isn't necessarily.
6670          */
6671
6672         return clock.dot;
6673 }
6674
6675 /** Returns the currently programmed mode of the given pipe. */
6676 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6677                                              struct drm_crtc *crtc)
6678 {
6679         struct drm_i915_private *dev_priv = dev->dev_private;
6680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6681         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6682         struct drm_display_mode *mode;
6683         int htot = I915_READ(HTOTAL(cpu_transcoder));
6684         int hsync = I915_READ(HSYNC(cpu_transcoder));
6685         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6686         int vsync = I915_READ(VSYNC(cpu_transcoder));
6687
6688         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6689         if (!mode)
6690                 return NULL;
6691
6692         mode->clock = intel_crtc_clock_get(dev, crtc);
6693         mode->hdisplay = (htot & 0xffff) + 1;
6694         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6695         mode->hsync_start = (hsync & 0xffff) + 1;
6696         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6697         mode->vdisplay = (vtot & 0xffff) + 1;
6698         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6699         mode->vsync_start = (vsync & 0xffff) + 1;
6700         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6701
6702         drm_mode_set_name(mode);
6703
6704         return mode;
6705 }
6706
6707 static void intel_increase_pllclock(struct drm_crtc *crtc)
6708 {
6709         struct drm_device *dev = crtc->dev;
6710         drm_i915_private_t *dev_priv = dev->dev_private;
6711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6712         int pipe = intel_crtc->pipe;
6713         int dpll_reg = DPLL(pipe);
6714         int dpll;
6715
6716         if (HAS_PCH_SPLIT(dev))
6717                 return;
6718
6719         if (!dev_priv->lvds_downclock_avail)
6720                 return;
6721
6722         dpll = I915_READ(dpll_reg);
6723         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6724                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6725
6726                 assert_panel_unlocked(dev_priv, pipe);
6727
6728                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6729                 I915_WRITE(dpll_reg, dpll);
6730                 intel_wait_for_vblank(dev, pipe);
6731
6732                 dpll = I915_READ(dpll_reg);
6733                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6734                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6735         }
6736 }
6737
6738 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6739 {
6740         struct drm_device *dev = crtc->dev;
6741         drm_i915_private_t *dev_priv = dev->dev_private;
6742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6743
6744         if (HAS_PCH_SPLIT(dev))
6745                 return;
6746
6747         if (!dev_priv->lvds_downclock_avail)
6748                 return;
6749
6750         /*
6751          * Since this is called by a timer, we should never get here in
6752          * the manual case.
6753          */
6754         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6755                 int pipe = intel_crtc->pipe;
6756                 int dpll_reg = DPLL(pipe);
6757                 int dpll;
6758
6759                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6760
6761                 assert_panel_unlocked(dev_priv, pipe);
6762
6763                 dpll = I915_READ(dpll_reg);
6764                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6765                 I915_WRITE(dpll_reg, dpll);
6766                 intel_wait_for_vblank(dev, pipe);
6767                 dpll = I915_READ(dpll_reg);
6768                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6769                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6770         }
6771
6772 }
6773
6774 void intel_mark_busy(struct drm_device *dev)
6775 {
6776         i915_update_gfx_val(dev->dev_private);
6777 }
6778
6779 void intel_mark_idle(struct drm_device *dev)
6780 {
6781         struct drm_crtc *crtc;
6782
6783         if (!i915_powersave)
6784                 return;
6785
6786         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6787                 if (!crtc->fb)
6788                         continue;
6789
6790                 intel_decrease_pllclock(crtc);
6791         }
6792 }
6793
6794 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6795 {
6796         struct drm_device *dev = obj->base.dev;
6797         struct drm_crtc *crtc;
6798
6799         if (!i915_powersave)
6800                 return;
6801
6802         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6803                 if (!crtc->fb)
6804                         continue;
6805
6806                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6807                         intel_increase_pllclock(crtc);
6808         }
6809 }
6810
6811 static void intel_crtc_destroy(struct drm_crtc *crtc)
6812 {
6813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814         struct drm_device *dev = crtc->dev;
6815         struct intel_unpin_work *work;
6816         unsigned long flags;
6817
6818         spin_lock_irqsave(&dev->event_lock, flags);
6819         work = intel_crtc->unpin_work;
6820         intel_crtc->unpin_work = NULL;
6821         spin_unlock_irqrestore(&dev->event_lock, flags);
6822
6823         if (work) {
6824                 cancel_work_sync(&work->work);
6825                 kfree(work);
6826         }
6827
6828         drm_crtc_cleanup(crtc);
6829
6830         kfree(intel_crtc);
6831 }
6832
6833 static void intel_unpin_work_fn(struct work_struct *__work)
6834 {
6835         struct intel_unpin_work *work =
6836                 container_of(__work, struct intel_unpin_work, work);
6837         struct drm_device *dev = work->crtc->dev;
6838
6839         mutex_lock(&dev->struct_mutex);
6840         intel_unpin_fb_obj(work->old_fb_obj);
6841         drm_gem_object_unreference(&work->pending_flip_obj->base);
6842         drm_gem_object_unreference(&work->old_fb_obj->base);
6843
6844         intel_update_fbc(dev);
6845         mutex_unlock(&dev->struct_mutex);
6846
6847         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6848         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6849
6850         kfree(work);
6851 }
6852
6853 static void do_intel_finish_page_flip(struct drm_device *dev,
6854                                       struct drm_crtc *crtc)
6855 {
6856         drm_i915_private_t *dev_priv = dev->dev_private;
6857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6858         struct intel_unpin_work *work;
6859         struct drm_i915_gem_object *obj;
6860         unsigned long flags;
6861
6862         /* Ignore early vblank irqs */
6863         if (intel_crtc == NULL)
6864                 return;
6865
6866         spin_lock_irqsave(&dev->event_lock, flags);
6867         work = intel_crtc->unpin_work;
6868
6869         /* Ensure we don't miss a work->pending update ... */
6870         smp_rmb();
6871
6872         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6873                 spin_unlock_irqrestore(&dev->event_lock, flags);
6874                 return;
6875         }
6876
6877         /* and that the unpin work is consistent wrt ->pending. */
6878         smp_rmb();
6879
6880         intel_crtc->unpin_work = NULL;
6881
6882         if (work->event)
6883                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6884
6885         drm_vblank_put(dev, intel_crtc->pipe);
6886
6887         spin_unlock_irqrestore(&dev->event_lock, flags);
6888
6889         obj = work->old_fb_obj;
6890
6891         wake_up_all(&dev_priv->pending_flip_queue);
6892
6893         queue_work(dev_priv->wq, &work->work);
6894
6895         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6896 }
6897
6898 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6899 {
6900         drm_i915_private_t *dev_priv = dev->dev_private;
6901         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6902
6903         do_intel_finish_page_flip(dev, crtc);
6904 }
6905
6906 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6907 {
6908         drm_i915_private_t *dev_priv = dev->dev_private;
6909         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6910
6911         do_intel_finish_page_flip(dev, crtc);
6912 }
6913
6914 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6915 {
6916         drm_i915_private_t *dev_priv = dev->dev_private;
6917         struct intel_crtc *intel_crtc =
6918                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6919         unsigned long flags;
6920
6921         /* NB: An MMIO update of the plane base pointer will also
6922          * generate a page-flip completion irq, i.e. every modeset
6923          * is also accompanied by a spurious intel_prepare_page_flip().
6924          */
6925         spin_lock_irqsave(&dev->event_lock, flags);
6926         if (intel_crtc->unpin_work)
6927                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6928         spin_unlock_irqrestore(&dev->event_lock, flags);
6929 }
6930
6931 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6932 {
6933         /* Ensure that the work item is consistent when activating it ... */
6934         smp_wmb();
6935         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6936         /* and that it is marked active as soon as the irq could fire. */
6937         smp_wmb();
6938 }
6939
6940 static int intel_gen2_queue_flip(struct drm_device *dev,
6941                                  struct drm_crtc *crtc,
6942                                  struct drm_framebuffer *fb,
6943                                  struct drm_i915_gem_object *obj)
6944 {
6945         struct drm_i915_private *dev_priv = dev->dev_private;
6946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6947         u32 flip_mask;
6948         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6949         int ret;
6950
6951         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6952         if (ret)
6953                 goto err;
6954
6955         ret = intel_ring_begin(ring, 6);
6956         if (ret)
6957                 goto err_unpin;
6958
6959         /* Can't queue multiple flips, so wait for the previous
6960          * one to finish before executing the next.
6961          */
6962         if (intel_crtc->plane)
6963                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6964         else
6965                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6966         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6967         intel_ring_emit(ring, MI_NOOP);
6968         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6969                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6970         intel_ring_emit(ring, fb->pitches[0]);
6971         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6972         intel_ring_emit(ring, 0); /* aux display base address, unused */
6973
6974         intel_mark_page_flip_active(intel_crtc);
6975         intel_ring_advance(ring);
6976         return 0;
6977
6978 err_unpin:
6979         intel_unpin_fb_obj(obj);
6980 err:
6981         return ret;
6982 }
6983
6984 static int intel_gen3_queue_flip(struct drm_device *dev,
6985                                  struct drm_crtc *crtc,
6986                                  struct drm_framebuffer *fb,
6987                                  struct drm_i915_gem_object *obj)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6991         u32 flip_mask;
6992         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6993         int ret;
6994
6995         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6996         if (ret)
6997                 goto err;
6998
6999         ret = intel_ring_begin(ring, 6);
7000         if (ret)
7001                 goto err_unpin;
7002
7003         if (intel_crtc->plane)
7004                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7005         else
7006                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7007         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7008         intel_ring_emit(ring, MI_NOOP);
7009         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7010                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7011         intel_ring_emit(ring, fb->pitches[0]);
7012         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7013         intel_ring_emit(ring, MI_NOOP);
7014
7015         intel_mark_page_flip_active(intel_crtc);
7016         intel_ring_advance(ring);
7017         return 0;
7018
7019 err_unpin:
7020         intel_unpin_fb_obj(obj);
7021 err:
7022         return ret;
7023 }
7024
7025 static int intel_gen4_queue_flip(struct drm_device *dev,
7026                                  struct drm_crtc *crtc,
7027                                  struct drm_framebuffer *fb,
7028                                  struct drm_i915_gem_object *obj)
7029 {
7030         struct drm_i915_private *dev_priv = dev->dev_private;
7031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7032         uint32_t pf, pipesrc;
7033         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7034         int ret;
7035
7036         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7037         if (ret)
7038                 goto err;
7039
7040         ret = intel_ring_begin(ring, 4);
7041         if (ret)
7042                 goto err_unpin;
7043
7044         /* i965+ uses the linear or tiled offsets from the
7045          * Display Registers (which do not change across a page-flip)
7046          * so we need only reprogram the base address.
7047          */
7048         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7049                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7050         intel_ring_emit(ring, fb->pitches[0]);
7051         intel_ring_emit(ring,
7052                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7053                         obj->tiling_mode);
7054
7055         /* XXX Enabling the panel-fitter across page-flip is so far
7056          * untested on non-native modes, so ignore it for now.
7057          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7058          */
7059         pf = 0;
7060         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7061         intel_ring_emit(ring, pf | pipesrc);
7062
7063         intel_mark_page_flip_active(intel_crtc);
7064         intel_ring_advance(ring);
7065         return 0;
7066
7067 err_unpin:
7068         intel_unpin_fb_obj(obj);
7069 err:
7070         return ret;
7071 }
7072
7073 static int intel_gen6_queue_flip(struct drm_device *dev,
7074                                  struct drm_crtc *crtc,
7075                                  struct drm_framebuffer *fb,
7076                                  struct drm_i915_gem_object *obj)
7077 {
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7080         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7081         uint32_t pf, pipesrc;
7082         int ret;
7083
7084         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7085         if (ret)
7086                 goto err;
7087
7088         ret = intel_ring_begin(ring, 4);
7089         if (ret)
7090                 goto err_unpin;
7091
7092         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7093                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7094         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7095         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7096
7097         /* Contrary to the suggestions in the documentation,
7098          * "Enable Panel Fitter" does not seem to be required when page
7099          * flipping with a non-native mode, and worse causes a normal
7100          * modeset to fail.
7101          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7102          */
7103         pf = 0;
7104         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7105         intel_ring_emit(ring, pf | pipesrc);
7106
7107         intel_mark_page_flip_active(intel_crtc);
7108         intel_ring_advance(ring);
7109         return 0;
7110
7111 err_unpin:
7112         intel_unpin_fb_obj(obj);
7113 err:
7114         return ret;
7115 }
7116
7117 /*
7118  * On gen7 we currently use the blit ring because (in early silicon at least)
7119  * the render ring doesn't give us interrpts for page flip completion, which
7120  * means clients will hang after the first flip is queued.  Fortunately the
7121  * blit ring generates interrupts properly, so use it instead.
7122  */
7123 static int intel_gen7_queue_flip(struct drm_device *dev,
7124                                  struct drm_crtc *crtc,
7125                                  struct drm_framebuffer *fb,
7126                                  struct drm_i915_gem_object *obj)
7127 {
7128         struct drm_i915_private *dev_priv = dev->dev_private;
7129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7130         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7131         uint32_t plane_bit = 0;
7132         int ret;
7133
7134         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7135         if (ret)
7136                 goto err;
7137
7138         switch(intel_crtc->plane) {
7139         case PLANE_A:
7140                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7141                 break;
7142         case PLANE_B:
7143                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7144                 break;
7145         case PLANE_C:
7146                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7147                 break;
7148         default:
7149                 WARN_ONCE(1, "unknown plane in flip command\n");
7150                 ret = -ENODEV;
7151                 goto err_unpin;
7152         }
7153
7154         ret = intel_ring_begin(ring, 4);
7155         if (ret)
7156                 goto err_unpin;
7157
7158         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7159         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7160         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7161         intel_ring_emit(ring, (MI_NOOP));
7162
7163         intel_mark_page_flip_active(intel_crtc);
7164         intel_ring_advance(ring);
7165         return 0;
7166
7167 err_unpin:
7168         intel_unpin_fb_obj(obj);
7169 err:
7170         return ret;
7171 }
7172
7173 static int intel_default_queue_flip(struct drm_device *dev,
7174                                     struct drm_crtc *crtc,
7175                                     struct drm_framebuffer *fb,
7176                                     struct drm_i915_gem_object *obj)
7177 {
7178         return -ENODEV;
7179 }
7180
7181 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7182                                 struct drm_framebuffer *fb,
7183                                 struct drm_pending_vblank_event *event)
7184 {
7185         struct drm_device *dev = crtc->dev;
7186         struct drm_i915_private *dev_priv = dev->dev_private;
7187         struct intel_framebuffer *intel_fb;
7188         struct drm_i915_gem_object *obj;
7189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7190         struct intel_unpin_work *work;
7191         unsigned long flags;
7192         int ret;
7193
7194         /* Can't change pixel format via MI display flips. */
7195         if (fb->pixel_format != crtc->fb->pixel_format)
7196                 return -EINVAL;
7197
7198         /*
7199          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7200          * Note that pitch changes could also affect these register.
7201          */
7202         if (INTEL_INFO(dev)->gen > 3 &&
7203             (fb->offsets[0] != crtc->fb->offsets[0] ||
7204              fb->pitches[0] != crtc->fb->pitches[0]))
7205                 return -EINVAL;
7206
7207         work = kzalloc(sizeof *work, GFP_KERNEL);
7208         if (work == NULL)
7209                 return -ENOMEM;
7210
7211         work->event = event;
7212         work->crtc = crtc;
7213         intel_fb = to_intel_framebuffer(crtc->fb);
7214         work->old_fb_obj = intel_fb->obj;
7215         INIT_WORK(&work->work, intel_unpin_work_fn);
7216
7217         ret = drm_vblank_get(dev, intel_crtc->pipe);
7218         if (ret)
7219                 goto free_work;
7220
7221         /* We borrow the event spin lock for protecting unpin_work */
7222         spin_lock_irqsave(&dev->event_lock, flags);
7223         if (intel_crtc->unpin_work) {
7224                 spin_unlock_irqrestore(&dev->event_lock, flags);
7225                 kfree(work);
7226                 drm_vblank_put(dev, intel_crtc->pipe);
7227
7228                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7229                 return -EBUSY;
7230         }
7231         intel_crtc->unpin_work = work;
7232         spin_unlock_irqrestore(&dev->event_lock, flags);
7233
7234         intel_fb = to_intel_framebuffer(fb);
7235         obj = intel_fb->obj;
7236
7237         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7238                 flush_workqueue(dev_priv->wq);
7239
7240         ret = i915_mutex_lock_interruptible(dev);
7241         if (ret)
7242                 goto cleanup;
7243
7244         /* Reference the objects for the scheduled work. */
7245         drm_gem_object_reference(&work->old_fb_obj->base);
7246         drm_gem_object_reference(&obj->base);
7247
7248         crtc->fb = fb;
7249
7250         work->pending_flip_obj = obj;
7251
7252         work->enable_stall_check = true;
7253
7254         atomic_inc(&intel_crtc->unpin_work_count);
7255         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7256
7257         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7258         if (ret)
7259                 goto cleanup_pending;
7260
7261         intel_disable_fbc(dev);
7262         intel_mark_fb_busy(obj);
7263         mutex_unlock(&dev->struct_mutex);
7264
7265         trace_i915_flip_request(intel_crtc->plane, obj);
7266
7267         return 0;
7268
7269 cleanup_pending:
7270         atomic_dec(&intel_crtc->unpin_work_count);
7271         drm_gem_object_unreference(&work->old_fb_obj->base);
7272         drm_gem_object_unreference(&obj->base);
7273         mutex_unlock(&dev->struct_mutex);
7274
7275 cleanup:
7276         spin_lock_irqsave(&dev->event_lock, flags);
7277         intel_crtc->unpin_work = NULL;
7278         spin_unlock_irqrestore(&dev->event_lock, flags);
7279
7280         drm_vblank_put(dev, intel_crtc->pipe);
7281 free_work:
7282         kfree(work);
7283
7284         return ret;
7285 }
7286
7287 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7288         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7289         .load_lut = intel_crtc_load_lut,
7290         .disable = intel_crtc_noop,
7291 };
7292
7293 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7294 {
7295         struct intel_encoder *other_encoder;
7296         struct drm_crtc *crtc = &encoder->new_crtc->base;
7297
7298         if (WARN_ON(!crtc))
7299                 return false;
7300
7301         list_for_each_entry(other_encoder,
7302                             &crtc->dev->mode_config.encoder_list,
7303                             base.head) {
7304
7305                 if (&other_encoder->new_crtc->base != crtc ||
7306                     encoder == other_encoder)
7307                         continue;
7308                 else
7309                         return true;
7310         }
7311
7312         return false;
7313 }
7314
7315 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7316                                   struct drm_crtc *crtc)
7317 {
7318         struct drm_device *dev;
7319         struct drm_crtc *tmp;
7320         int crtc_mask = 1;
7321
7322         WARN(!crtc, "checking null crtc?\n");
7323
7324         dev = crtc->dev;
7325
7326         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7327                 if (tmp == crtc)
7328                         break;
7329                 crtc_mask <<= 1;
7330         }
7331
7332         if (encoder->possible_crtcs & crtc_mask)
7333                 return true;
7334         return false;
7335 }
7336
7337 /**
7338  * intel_modeset_update_staged_output_state
7339  *
7340  * Updates the staged output configuration state, e.g. after we've read out the
7341  * current hw state.
7342  */
7343 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7344 {
7345         struct intel_encoder *encoder;
7346         struct intel_connector *connector;
7347
7348         list_for_each_entry(connector, &dev->mode_config.connector_list,
7349                             base.head) {
7350                 connector->new_encoder =
7351                         to_intel_encoder(connector->base.encoder);
7352         }
7353
7354         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7355                             base.head) {
7356                 encoder->new_crtc =
7357                         to_intel_crtc(encoder->base.crtc);
7358         }
7359 }
7360
7361 /**
7362  * intel_modeset_commit_output_state
7363  *
7364  * This function copies the stage display pipe configuration to the real one.
7365  */
7366 static void intel_modeset_commit_output_state(struct drm_device *dev)
7367 {
7368         struct intel_encoder *encoder;
7369         struct intel_connector *connector;
7370
7371         list_for_each_entry(connector, &dev->mode_config.connector_list,
7372                             base.head) {
7373                 connector->base.encoder = &connector->new_encoder->base;
7374         }
7375
7376         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7377                             base.head) {
7378                 encoder->base.crtc = &encoder->new_crtc->base;
7379         }
7380 }
7381
7382 static struct drm_display_mode *
7383 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7384                             struct drm_display_mode *mode)
7385 {
7386         struct drm_device *dev = crtc->dev;
7387         struct drm_display_mode *adjusted_mode;
7388         struct drm_encoder_helper_funcs *encoder_funcs;
7389         struct intel_encoder *encoder;
7390
7391         adjusted_mode = drm_mode_duplicate(dev, mode);
7392         if (!adjusted_mode)
7393                 return ERR_PTR(-ENOMEM);
7394
7395         /* Pass our mode to the connectors and the CRTC to give them a chance to
7396          * adjust it according to limitations or connector properties, and also
7397          * a chance to reject the mode entirely.
7398          */
7399         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7400                             base.head) {
7401
7402                 if (&encoder->new_crtc->base != crtc)
7403                         continue;
7404                 encoder_funcs = encoder->base.helper_private;
7405                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7406                                                 adjusted_mode))) {
7407                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7408                         goto fail;
7409                 }
7410         }
7411
7412         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7413                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7414                 goto fail;
7415         }
7416         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7417
7418         return adjusted_mode;
7419 fail:
7420         drm_mode_destroy(dev, adjusted_mode);
7421         return ERR_PTR(-EINVAL);
7422 }
7423
7424 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7425  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7426 static void
7427 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7428                              unsigned *prepare_pipes, unsigned *disable_pipes)
7429 {
7430         struct intel_crtc *intel_crtc;
7431         struct drm_device *dev = crtc->dev;
7432         struct intel_encoder *encoder;
7433         struct intel_connector *connector;
7434         struct drm_crtc *tmp_crtc;
7435
7436         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7437
7438         /* Check which crtcs have changed outputs connected to them, these need
7439          * to be part of the prepare_pipes mask. We don't (yet) support global
7440          * modeset across multiple crtcs, so modeset_pipes will only have one
7441          * bit set at most. */
7442         list_for_each_entry(connector, &dev->mode_config.connector_list,
7443                             base.head) {
7444                 if (connector->base.encoder == &connector->new_encoder->base)
7445                         continue;
7446
7447                 if (connector->base.encoder) {
7448                         tmp_crtc = connector->base.encoder->crtc;
7449
7450                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7451                 }
7452
7453                 if (connector->new_encoder)
7454                         *prepare_pipes |=
7455                                 1 << connector->new_encoder->new_crtc->pipe;
7456         }
7457
7458         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7459                             base.head) {
7460                 if (encoder->base.crtc == &encoder->new_crtc->base)
7461                         continue;
7462
7463                 if (encoder->base.crtc) {
7464                         tmp_crtc = encoder->base.crtc;
7465
7466                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7467                 }
7468
7469                 if (encoder->new_crtc)
7470                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7471         }
7472
7473         /* Check for any pipes that will be fully disabled ... */
7474         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7475                             base.head) {
7476                 bool used = false;
7477
7478                 /* Don't try to disable disabled crtcs. */
7479                 if (!intel_crtc->base.enabled)
7480                         continue;
7481
7482                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7483                                     base.head) {
7484                         if (encoder->new_crtc == intel_crtc)
7485                                 used = true;
7486                 }
7487
7488                 if (!used)
7489                         *disable_pipes |= 1 << intel_crtc->pipe;
7490         }
7491
7492
7493         /* set_mode is also used to update properties on life display pipes. */
7494         intel_crtc = to_intel_crtc(crtc);
7495         if (crtc->enabled)
7496                 *prepare_pipes |= 1 << intel_crtc->pipe;
7497
7498         /* We only support modeset on one single crtc, hence we need to do that
7499          * only for the passed in crtc iff we change anything else than just
7500          * disable crtcs.
7501          *
7502          * This is actually not true, to be fully compatible with the old crtc
7503          * helper we automatically disable _any_ output (i.e. doesn't need to be
7504          * connected to the crtc we're modesetting on) if it's disconnected.
7505          * Which is a rather nutty api (since changed the output configuration
7506          * without userspace's explicit request can lead to confusion), but
7507          * alas. Hence we currently need to modeset on all pipes we prepare. */
7508         if (*prepare_pipes)
7509                 *modeset_pipes = *prepare_pipes;
7510
7511         /* ... and mask these out. */
7512         *modeset_pipes &= ~(*disable_pipes);
7513         *prepare_pipes &= ~(*disable_pipes);
7514 }
7515
7516 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7517 {
7518         struct drm_encoder *encoder;
7519         struct drm_device *dev = crtc->dev;
7520
7521         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7522                 if (encoder->crtc == crtc)
7523                         return true;
7524
7525         return false;
7526 }
7527
7528 static void
7529 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7530 {
7531         struct intel_encoder *intel_encoder;
7532         struct intel_crtc *intel_crtc;
7533         struct drm_connector *connector;
7534
7535         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7536                             base.head) {
7537                 if (!intel_encoder->base.crtc)
7538                         continue;
7539
7540                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7541
7542                 if (prepare_pipes & (1 << intel_crtc->pipe))
7543                         intel_encoder->connectors_active = false;
7544         }
7545
7546         intel_modeset_commit_output_state(dev);
7547
7548         /* Update computed state. */
7549         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7550                             base.head) {
7551                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7552         }
7553
7554         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7555                 if (!connector->encoder || !connector->encoder->crtc)
7556                         continue;
7557
7558                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7559
7560                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7561                         struct drm_property *dpms_property =
7562                                 dev->mode_config.dpms_property;
7563
7564                         connector->dpms = DRM_MODE_DPMS_ON;
7565                         drm_object_property_set_value(&connector->base,
7566                                                          dpms_property,
7567                                                          DRM_MODE_DPMS_ON);
7568
7569                         intel_encoder = to_intel_encoder(connector->encoder);
7570                         intel_encoder->connectors_active = true;
7571                 }
7572         }
7573
7574 }
7575
7576 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7577         list_for_each_entry((intel_crtc), \
7578                             &(dev)->mode_config.crtc_list, \
7579                             base.head) \
7580                 if (mask & (1 <<(intel_crtc)->pipe)) \
7581
7582 void
7583 intel_modeset_check_state(struct drm_device *dev)
7584 {
7585         struct intel_crtc *crtc;
7586         struct intel_encoder *encoder;
7587         struct intel_connector *connector;
7588
7589         list_for_each_entry(connector, &dev->mode_config.connector_list,
7590                             base.head) {
7591                 /* This also checks the encoder/connector hw state with the
7592                  * ->get_hw_state callbacks. */
7593                 intel_connector_check_state(connector);
7594
7595                 WARN(&connector->new_encoder->base != connector->base.encoder,
7596                      "connector's staged encoder doesn't match current encoder\n");
7597         }
7598
7599         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7600                             base.head) {
7601                 bool enabled = false;
7602                 bool active = false;
7603                 enum pipe pipe, tracked_pipe;
7604
7605                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7606                               encoder->base.base.id,
7607                               drm_get_encoder_name(&encoder->base));
7608
7609                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7610                      "encoder's stage crtc doesn't match current crtc\n");
7611                 WARN(encoder->connectors_active && !encoder->base.crtc,
7612                      "encoder's active_connectors set, but no crtc\n");
7613
7614                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7615                                     base.head) {
7616                         if (connector->base.encoder != &encoder->base)
7617                                 continue;
7618                         enabled = true;
7619                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7620                                 active = true;
7621                 }
7622                 WARN(!!encoder->base.crtc != enabled,
7623                      "encoder's enabled state mismatch "
7624                      "(expected %i, found %i)\n",
7625                      !!encoder->base.crtc, enabled);
7626                 WARN(active && !encoder->base.crtc,
7627                      "active encoder with no crtc\n");
7628
7629                 WARN(encoder->connectors_active != active,
7630                      "encoder's computed active state doesn't match tracked active state "
7631                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7632
7633                 active = encoder->get_hw_state(encoder, &pipe);
7634                 WARN(active != encoder->connectors_active,
7635                      "encoder's hw state doesn't match sw tracking "
7636                      "(expected %i, found %i)\n",
7637                      encoder->connectors_active, active);
7638
7639                 if (!encoder->base.crtc)
7640                         continue;
7641
7642                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7643                 WARN(active && pipe != tracked_pipe,
7644                      "active encoder's pipe doesn't match"
7645                      "(expected %i, found %i)\n",
7646                      tracked_pipe, pipe);
7647
7648         }
7649
7650         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7651                             base.head) {
7652                 bool enabled = false;
7653                 bool active = false;
7654
7655                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7656                               crtc->base.base.id);
7657
7658                 WARN(crtc->active && !crtc->base.enabled,
7659                      "active crtc, but not enabled in sw tracking\n");
7660
7661                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7662                                     base.head) {
7663                         if (encoder->base.crtc != &crtc->base)
7664                                 continue;
7665                         enabled = true;
7666                         if (encoder->connectors_active)
7667                                 active = true;
7668                 }
7669                 WARN(active != crtc->active,
7670                      "crtc's computed active state doesn't match tracked active state "
7671                      "(expected %i, found %i)\n", active, crtc->active);
7672                 WARN(enabled != crtc->base.enabled,
7673                      "crtc's computed enabled state doesn't match tracked enabled state "
7674                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7675
7676                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7677         }
7678 }
7679
7680 int intel_set_mode(struct drm_crtc *crtc,
7681                    struct drm_display_mode *mode,
7682                    int x, int y, struct drm_framebuffer *fb)
7683 {
7684         struct drm_device *dev = crtc->dev;
7685         drm_i915_private_t *dev_priv = dev->dev_private;
7686         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7687         struct intel_crtc *intel_crtc;
7688         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7689         int ret = 0;
7690
7691         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7692         if (!saved_mode)
7693                 return -ENOMEM;
7694         saved_hwmode = saved_mode + 1;
7695
7696         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7697                                      &prepare_pipes, &disable_pipes);
7698
7699         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7700                       modeset_pipes, prepare_pipes, disable_pipes);
7701
7702         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7703                 intel_crtc_disable(&intel_crtc->base);
7704
7705         *saved_hwmode = crtc->hwmode;
7706         *saved_mode = crtc->mode;
7707
7708         /* Hack: Because we don't (yet) support global modeset on multiple
7709          * crtcs, we don't keep track of the new mode for more than one crtc.
7710          * Hence simply check whether any bit is set in modeset_pipes in all the
7711          * pieces of code that are not yet converted to deal with mutliple crtcs
7712          * changing their mode at the same time. */
7713         adjusted_mode = NULL;
7714         if (modeset_pipes) {
7715                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7716                 if (IS_ERR(adjusted_mode)) {
7717                         ret = PTR_ERR(adjusted_mode);
7718                         goto out;
7719                 }
7720         }
7721
7722         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7723                 if (intel_crtc->base.enabled)
7724                         dev_priv->display.crtc_disable(&intel_crtc->base);
7725         }
7726
7727         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7728          * to set it here already despite that we pass it down the callchain.
7729          */
7730         if (modeset_pipes)
7731                 crtc->mode = *mode;
7732
7733         /* Only after disabling all output pipelines that will be changed can we
7734          * update the the output configuration. */
7735         intel_modeset_update_state(dev, prepare_pipes);
7736
7737         if (dev_priv->display.modeset_global_resources)
7738                 dev_priv->display.modeset_global_resources(dev);
7739
7740         /* Set up the DPLL and any encoders state that needs to adjust or depend
7741          * on the DPLL.
7742          */
7743         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7744                 ret = intel_crtc_mode_set(&intel_crtc->base,
7745                                           mode, adjusted_mode,
7746                                           x, y, fb);
7747                 if (ret)
7748                         goto done;
7749         }
7750
7751         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7752         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7753                 dev_priv->display.crtc_enable(&intel_crtc->base);
7754
7755         if (modeset_pipes) {
7756                 /* Store real post-adjustment hardware mode. */
7757                 crtc->hwmode = *adjusted_mode;
7758
7759                 /* Calculate and store various constants which
7760                  * are later needed by vblank and swap-completion
7761                  * timestamping. They are derived from true hwmode.
7762                  */
7763                 drm_calc_timestamping_constants(crtc);
7764         }
7765
7766         /* FIXME: add subpixel order */
7767 done:
7768         drm_mode_destroy(dev, adjusted_mode);
7769         if (ret && crtc->enabled) {
7770                 crtc->hwmode = *saved_hwmode;
7771                 crtc->mode = *saved_mode;
7772         } else {
7773                 intel_modeset_check_state(dev);
7774         }
7775
7776 out:
7777         kfree(saved_mode);
7778         return ret;
7779 }
7780
7781 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7782 {
7783         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7784 }
7785
7786 #undef for_each_intel_crtc_masked
7787
7788 static void intel_set_config_free(struct intel_set_config *config)
7789 {
7790         if (!config)
7791                 return;
7792
7793         kfree(config->save_connector_encoders);
7794         kfree(config->save_encoder_crtcs);
7795         kfree(config);
7796 }
7797
7798 static int intel_set_config_save_state(struct drm_device *dev,
7799                                        struct intel_set_config *config)
7800 {
7801         struct drm_encoder *encoder;
7802         struct drm_connector *connector;
7803         int count;
7804
7805         config->save_encoder_crtcs =
7806                 kcalloc(dev->mode_config.num_encoder,
7807                         sizeof(struct drm_crtc *), GFP_KERNEL);
7808         if (!config->save_encoder_crtcs)
7809                 return -ENOMEM;
7810
7811         config->save_connector_encoders =
7812                 kcalloc(dev->mode_config.num_connector,
7813                         sizeof(struct drm_encoder *), GFP_KERNEL);
7814         if (!config->save_connector_encoders)
7815                 return -ENOMEM;
7816
7817         /* Copy data. Note that driver private data is not affected.
7818          * Should anything bad happen only the expected state is
7819          * restored, not the drivers personal bookkeeping.
7820          */
7821         count = 0;
7822         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7823                 config->save_encoder_crtcs[count++] = encoder->crtc;
7824         }
7825
7826         count = 0;
7827         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7828                 config->save_connector_encoders[count++] = connector->encoder;
7829         }
7830
7831         return 0;
7832 }
7833
7834 static void intel_set_config_restore_state(struct drm_device *dev,
7835                                            struct intel_set_config *config)
7836 {
7837         struct intel_encoder *encoder;
7838         struct intel_connector *connector;
7839         int count;
7840
7841         count = 0;
7842         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7843                 encoder->new_crtc =
7844                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7845         }
7846
7847         count = 0;
7848         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7849                 connector->new_encoder =
7850                         to_intel_encoder(config->save_connector_encoders[count++]);
7851         }
7852 }
7853
7854 static void
7855 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7856                                       struct intel_set_config *config)
7857 {
7858
7859         /* We should be able to check here if the fb has the same properties
7860          * and then just flip_or_move it */
7861         if (set->crtc->fb != set->fb) {
7862                 /* If we have no fb then treat it as a full mode set */
7863                 if (set->crtc->fb == NULL) {
7864                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7865                         config->mode_changed = true;
7866                 } else if (set->fb == NULL) {
7867                         config->mode_changed = true;
7868                 } else if (set->fb->depth != set->crtc->fb->depth) {
7869                         config->mode_changed = true;
7870                 } else if (set->fb->bits_per_pixel !=
7871                            set->crtc->fb->bits_per_pixel) {
7872                         config->mode_changed = true;
7873                 } else
7874                         config->fb_changed = true;
7875         }
7876
7877         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7878                 config->fb_changed = true;
7879
7880         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7881                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7882                 drm_mode_debug_printmodeline(&set->crtc->mode);
7883                 drm_mode_debug_printmodeline(set->mode);
7884                 config->mode_changed = true;
7885         }
7886 }
7887
7888 static int
7889 intel_modeset_stage_output_state(struct drm_device *dev,
7890                                  struct drm_mode_set *set,
7891                                  struct intel_set_config *config)
7892 {
7893         struct drm_crtc *new_crtc;
7894         struct intel_connector *connector;
7895         struct intel_encoder *encoder;
7896         int count, ro;
7897
7898         /* The upper layers ensure that we either disable a crtc or have a list
7899          * of connectors. For paranoia, double-check this. */
7900         WARN_ON(!set->fb && (set->num_connectors != 0));
7901         WARN_ON(set->fb && (set->num_connectors == 0));
7902
7903         count = 0;
7904         list_for_each_entry(connector, &dev->mode_config.connector_list,
7905                             base.head) {
7906                 /* Otherwise traverse passed in connector list and get encoders
7907                  * for them. */
7908                 for (ro = 0; ro < set->num_connectors; ro++) {
7909                         if (set->connectors[ro] == &connector->base) {
7910                                 connector->new_encoder = connector->encoder;
7911                                 break;
7912                         }
7913                 }
7914
7915                 /* If we disable the crtc, disable all its connectors. Also, if
7916                  * the connector is on the changing crtc but not on the new
7917                  * connector list, disable it. */
7918                 if ((!set->fb || ro == set->num_connectors) &&
7919                     connector->base.encoder &&
7920                     connector->base.encoder->crtc == set->crtc) {
7921                         connector->new_encoder = NULL;
7922
7923                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7924                                 connector->base.base.id,
7925                                 drm_get_connector_name(&connector->base));
7926                 }
7927
7928
7929                 if (&connector->new_encoder->base != connector->base.encoder) {
7930                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7931                         config->mode_changed = true;
7932                 }
7933         }
7934         /* connector->new_encoder is now updated for all connectors. */
7935
7936         /* Update crtc of enabled connectors. */
7937         count = 0;
7938         list_for_each_entry(connector, &dev->mode_config.connector_list,
7939                             base.head) {
7940                 if (!connector->new_encoder)
7941                         continue;
7942
7943                 new_crtc = connector->new_encoder->base.crtc;
7944
7945                 for (ro = 0; ro < set->num_connectors; ro++) {
7946                         if (set->connectors[ro] == &connector->base)
7947                                 new_crtc = set->crtc;
7948                 }
7949
7950                 /* Make sure the new CRTC will work with the encoder */
7951                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7952                                            new_crtc)) {
7953                         return -EINVAL;
7954                 }
7955                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7956
7957                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7958                         connector->base.base.id,
7959                         drm_get_connector_name(&connector->base),
7960                         new_crtc->base.id);
7961         }
7962
7963         /* Check for any encoders that needs to be disabled. */
7964         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7965                             base.head) {
7966                 list_for_each_entry(connector,
7967                                     &dev->mode_config.connector_list,
7968                                     base.head) {
7969                         if (connector->new_encoder == encoder) {
7970                                 WARN_ON(!connector->new_encoder->new_crtc);
7971
7972                                 goto next_encoder;
7973                         }
7974                 }
7975                 encoder->new_crtc = NULL;
7976 next_encoder:
7977                 /* Only now check for crtc changes so we don't miss encoders
7978                  * that will be disabled. */
7979                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7980                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7981                         config->mode_changed = true;
7982                 }
7983         }
7984         /* Now we've also updated encoder->new_crtc for all encoders. */
7985
7986         return 0;
7987 }
7988
7989 static int intel_crtc_set_config(struct drm_mode_set *set)
7990 {
7991         struct drm_device *dev;
7992         struct drm_mode_set save_set;
7993         struct intel_set_config *config;
7994         int ret;
7995
7996         BUG_ON(!set);
7997         BUG_ON(!set->crtc);
7998         BUG_ON(!set->crtc->helper_private);
7999
8000         if (!set->mode)
8001                 set->fb = NULL;
8002
8003         /* The fb helper likes to play gross jokes with ->mode_set_config.
8004          * Unfortunately the crtc helper doesn't do much at all for this case,
8005          * so we have to cope with this madness until the fb helper is fixed up. */
8006         if (set->fb && set->num_connectors == 0)
8007                 return 0;
8008
8009         if (set->fb) {
8010                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8011                                 set->crtc->base.id, set->fb->base.id,
8012                                 (int)set->num_connectors, set->x, set->y);
8013         } else {
8014                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8015         }
8016
8017         dev = set->crtc->dev;
8018
8019         ret = -ENOMEM;
8020         config = kzalloc(sizeof(*config), GFP_KERNEL);
8021         if (!config)
8022                 goto out_config;
8023
8024         ret = intel_set_config_save_state(dev, config);
8025         if (ret)
8026                 goto out_config;
8027
8028         save_set.crtc = set->crtc;
8029         save_set.mode = &set->crtc->mode;
8030         save_set.x = set->crtc->x;
8031         save_set.y = set->crtc->y;
8032         save_set.fb = set->crtc->fb;
8033
8034         /* Compute whether we need a full modeset, only an fb base update or no
8035          * change at all. In the future we might also check whether only the
8036          * mode changed, e.g. for LVDS where we only change the panel fitter in
8037          * such cases. */
8038         intel_set_config_compute_mode_changes(set, config);
8039
8040         ret = intel_modeset_stage_output_state(dev, set, config);
8041         if (ret)
8042                 goto fail;
8043
8044         if (config->mode_changed) {
8045                 if (set->mode) {
8046                         DRM_DEBUG_KMS("attempting to set mode from"
8047                                         " userspace\n");
8048                         drm_mode_debug_printmodeline(set->mode);
8049                 }
8050
8051                 ret = intel_set_mode(set->crtc, set->mode,
8052                                      set->x, set->y, set->fb);
8053                 if (ret) {
8054                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8055                                   set->crtc->base.id, ret);
8056                         goto fail;
8057                 }
8058         } else if (config->fb_changed) {
8059                 ret = intel_pipe_set_base(set->crtc,
8060                                           set->x, set->y, set->fb);
8061         }
8062
8063         intel_set_config_free(config);
8064
8065         return 0;
8066
8067 fail:
8068         intel_set_config_restore_state(dev, config);
8069
8070         /* Try to restore the config */
8071         if (config->mode_changed &&
8072             intel_set_mode(save_set.crtc, save_set.mode,
8073                            save_set.x, save_set.y, save_set.fb))
8074                 DRM_ERROR("failed to restore config after modeset failure\n");
8075
8076 out_config:
8077         intel_set_config_free(config);
8078         return ret;
8079 }
8080
8081 static const struct drm_crtc_funcs intel_crtc_funcs = {
8082         .cursor_set = intel_crtc_cursor_set,
8083         .cursor_move = intel_crtc_cursor_move,
8084         .gamma_set = intel_crtc_gamma_set,
8085         .set_config = intel_crtc_set_config,
8086         .destroy = intel_crtc_destroy,
8087         .page_flip = intel_crtc_page_flip,
8088 };
8089
8090 static void intel_cpu_pll_init(struct drm_device *dev)
8091 {
8092         if (HAS_DDI(dev))
8093                 intel_ddi_pll_init(dev);
8094 }
8095
8096 static void intel_pch_pll_init(struct drm_device *dev)
8097 {
8098         drm_i915_private_t *dev_priv = dev->dev_private;
8099         int i;
8100
8101         if (dev_priv->num_pch_pll == 0) {
8102                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8103                 return;
8104         }
8105
8106         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8107                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8108                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8109                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8110         }
8111 }
8112
8113 static void intel_crtc_init(struct drm_device *dev, int pipe)
8114 {
8115         drm_i915_private_t *dev_priv = dev->dev_private;
8116         struct intel_crtc *intel_crtc;
8117         int i;
8118
8119         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8120         if (intel_crtc == NULL)
8121                 return;
8122
8123         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8124
8125         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8126         for (i = 0; i < 256; i++) {
8127                 intel_crtc->lut_r[i] = i;
8128                 intel_crtc->lut_g[i] = i;
8129                 intel_crtc->lut_b[i] = i;
8130         }
8131
8132         /* Swap pipes & planes for FBC on pre-965 */
8133         intel_crtc->pipe = pipe;
8134         intel_crtc->plane = pipe;
8135         intel_crtc->cpu_transcoder = pipe;
8136         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8137                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8138                 intel_crtc->plane = !pipe;
8139         }
8140
8141         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8142                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8143         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8144         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8145
8146         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8147
8148         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8149 }
8150
8151 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8152                                 struct drm_file *file)
8153 {
8154         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8155         struct drm_mode_object *drmmode_obj;
8156         struct intel_crtc *crtc;
8157
8158         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8159                 return -ENODEV;
8160
8161         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8162                         DRM_MODE_OBJECT_CRTC);
8163
8164         if (!drmmode_obj) {
8165                 DRM_ERROR("no such CRTC id\n");
8166                 return -EINVAL;
8167         }
8168
8169         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8170         pipe_from_crtc_id->pipe = crtc->pipe;
8171
8172         return 0;
8173 }
8174
8175 static int intel_encoder_clones(struct intel_encoder *encoder)
8176 {
8177         struct drm_device *dev = encoder->base.dev;
8178         struct intel_encoder *source_encoder;
8179         int index_mask = 0;
8180         int entry = 0;
8181
8182         list_for_each_entry(source_encoder,
8183                             &dev->mode_config.encoder_list, base.head) {
8184
8185                 if (encoder == source_encoder)
8186                         index_mask |= (1 << entry);
8187
8188                 /* Intel hw has only one MUX where enocoders could be cloned. */
8189                 if (encoder->cloneable && source_encoder->cloneable)
8190                         index_mask |= (1 << entry);
8191
8192                 entry++;
8193         }
8194
8195         return index_mask;
8196 }
8197
8198 static bool has_edp_a(struct drm_device *dev)
8199 {
8200         struct drm_i915_private *dev_priv = dev->dev_private;
8201
8202         if (!IS_MOBILE(dev))
8203                 return false;
8204
8205         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8206                 return false;
8207
8208         if (IS_GEN5(dev) &&
8209             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8210                 return false;
8211
8212         return true;
8213 }
8214
8215 static void intel_setup_outputs(struct drm_device *dev)
8216 {
8217         struct drm_i915_private *dev_priv = dev->dev_private;
8218         struct intel_encoder *encoder;
8219         bool dpd_is_edp = false;
8220         bool has_lvds;
8221
8222         has_lvds = intel_lvds_init(dev);
8223         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8224                 /* disable the panel fitter on everything but LVDS */
8225                 I915_WRITE(PFIT_CONTROL, 0);
8226         }
8227
8228         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8229                 intel_crt_init(dev);
8230
8231         if (HAS_DDI(dev)) {
8232                 int found;
8233
8234                 /* Haswell uses DDI functions to detect digital outputs */
8235                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8236                 /* DDI A only supports eDP */
8237                 if (found)
8238                         intel_ddi_init(dev, PORT_A);
8239
8240                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8241                  * register */
8242                 found = I915_READ(SFUSE_STRAP);
8243
8244                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8245                         intel_ddi_init(dev, PORT_B);
8246                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8247                         intel_ddi_init(dev, PORT_C);
8248                 if (found & SFUSE_STRAP_DDID_DETECTED)
8249                         intel_ddi_init(dev, PORT_D);
8250         } else if (HAS_PCH_SPLIT(dev)) {
8251                 int found;
8252                 dpd_is_edp = intel_dpd_is_edp(dev);
8253
8254                 if (has_edp_a(dev))
8255                         intel_dp_init(dev, DP_A, PORT_A);
8256
8257                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8258                         /* PCH SDVOB multiplex with HDMIB */
8259                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8260                         if (!found)
8261                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8262                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8263                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8264                 }
8265
8266                 if (I915_READ(HDMIC) & PORT_DETECTED)
8267                         intel_hdmi_init(dev, HDMIC, PORT_C);
8268
8269                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8270                         intel_hdmi_init(dev, HDMID, PORT_D);
8271
8272                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8273                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8274
8275                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8276                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8277         } else if (IS_VALLEYVIEW(dev)) {
8278                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8279                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8280                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8281
8282                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8283                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8284                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8285                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8286                 }
8287
8288                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8289                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8290
8291         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8292                 bool found = false;
8293
8294                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8295                         DRM_DEBUG_KMS("probing SDVOB\n");
8296                         found = intel_sdvo_init(dev, SDVOB, true);
8297                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8298                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8299                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8300                         }
8301
8302                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8303                                 DRM_DEBUG_KMS("probing DP_B\n");
8304                                 intel_dp_init(dev, DP_B, PORT_B);
8305                         }
8306                 }
8307
8308                 /* Before G4X SDVOC doesn't have its own detect register */
8309
8310                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8311                         DRM_DEBUG_KMS("probing SDVOC\n");
8312                         found = intel_sdvo_init(dev, SDVOC, false);
8313                 }
8314
8315                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8316
8317                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8318                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8319                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8320                         }
8321                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8322                                 DRM_DEBUG_KMS("probing DP_C\n");
8323                                 intel_dp_init(dev, DP_C, PORT_C);
8324                         }
8325                 }
8326
8327                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8328                     (I915_READ(DP_D) & DP_DETECTED)) {
8329                         DRM_DEBUG_KMS("probing DP_D\n");
8330                         intel_dp_init(dev, DP_D, PORT_D);
8331                 }
8332         } else if (IS_GEN2(dev))
8333                 intel_dvo_init(dev);
8334
8335         if (SUPPORTS_TV(dev))
8336                 intel_tv_init(dev);
8337
8338         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8339                 encoder->base.possible_crtcs = encoder->crtc_mask;
8340                 encoder->base.possible_clones =
8341                         intel_encoder_clones(encoder);
8342         }
8343
8344         intel_init_pch_refclk(dev);
8345
8346         drm_helper_move_panel_connectors_to_head(dev);
8347 }
8348
8349 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8350 {
8351         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8352
8353         drm_framebuffer_cleanup(fb);
8354         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8355
8356         kfree(intel_fb);
8357 }
8358
8359 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8360                                                 struct drm_file *file,
8361                                                 unsigned int *handle)
8362 {
8363         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8364         struct drm_i915_gem_object *obj = intel_fb->obj;
8365
8366         return drm_gem_handle_create(file, &obj->base, handle);
8367 }
8368
8369 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8370         .destroy = intel_user_framebuffer_destroy,
8371         .create_handle = intel_user_framebuffer_create_handle,
8372 };
8373
8374 int intel_framebuffer_init(struct drm_device *dev,
8375                            struct intel_framebuffer *intel_fb,
8376                            struct drm_mode_fb_cmd2 *mode_cmd,
8377                            struct drm_i915_gem_object *obj)
8378 {
8379         int ret;
8380
8381         if (obj->tiling_mode == I915_TILING_Y) {
8382                 DRM_DEBUG("hardware does not support tiling Y\n");
8383                 return -EINVAL;
8384         }
8385
8386         if (mode_cmd->pitches[0] & 63) {
8387                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8388                           mode_cmd->pitches[0]);
8389                 return -EINVAL;
8390         }
8391
8392         /* FIXME <= Gen4 stride limits are bit unclear */
8393         if (mode_cmd->pitches[0] > 32768) {
8394                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8395                           mode_cmd->pitches[0]);
8396                 return -EINVAL;
8397         }
8398
8399         if (obj->tiling_mode != I915_TILING_NONE &&
8400             mode_cmd->pitches[0] != obj->stride) {
8401                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8402                           mode_cmd->pitches[0], obj->stride);
8403                 return -EINVAL;
8404         }
8405
8406         /* Reject formats not supported by any plane early. */
8407         switch (mode_cmd->pixel_format) {
8408         case DRM_FORMAT_C8:
8409         case DRM_FORMAT_RGB565:
8410         case DRM_FORMAT_XRGB8888:
8411         case DRM_FORMAT_ARGB8888:
8412                 break;
8413         case DRM_FORMAT_XRGB1555:
8414         case DRM_FORMAT_ARGB1555:
8415                 if (INTEL_INFO(dev)->gen > 3) {
8416                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8417                         return -EINVAL;
8418                 }
8419                 break;
8420         case DRM_FORMAT_XBGR8888:
8421         case DRM_FORMAT_ABGR8888:
8422         case DRM_FORMAT_XRGB2101010:
8423         case DRM_FORMAT_ARGB2101010:
8424         case DRM_FORMAT_XBGR2101010:
8425         case DRM_FORMAT_ABGR2101010:
8426                 if (INTEL_INFO(dev)->gen < 4) {
8427                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8428                         return -EINVAL;
8429                 }
8430                 break;
8431         case DRM_FORMAT_YUYV:
8432         case DRM_FORMAT_UYVY:
8433         case DRM_FORMAT_YVYU:
8434         case DRM_FORMAT_VYUY:
8435                 if (INTEL_INFO(dev)->gen < 5) {
8436                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8437                         return -EINVAL;
8438                 }
8439                 break;
8440         default:
8441                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8442                 return -EINVAL;
8443         }
8444
8445         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8446         if (mode_cmd->offsets[0] != 0)
8447                 return -EINVAL;
8448
8449         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8450         intel_fb->obj = obj;
8451
8452         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8453         if (ret) {
8454                 DRM_ERROR("framebuffer init failed %d\n", ret);
8455                 return ret;
8456         }
8457
8458         return 0;
8459 }
8460
8461 static struct drm_framebuffer *
8462 intel_user_framebuffer_create(struct drm_device *dev,
8463                               struct drm_file *filp,
8464                               struct drm_mode_fb_cmd2 *mode_cmd)
8465 {
8466         struct drm_i915_gem_object *obj;
8467
8468         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8469                                                 mode_cmd->handles[0]));
8470         if (&obj->base == NULL)
8471                 return ERR_PTR(-ENOENT);
8472
8473         return intel_framebuffer_create(dev, mode_cmd, obj);
8474 }
8475
8476 static const struct drm_mode_config_funcs intel_mode_funcs = {
8477         .fb_create = intel_user_framebuffer_create,
8478         .output_poll_changed = intel_fb_output_poll_changed,
8479 };
8480
8481 /* Set up chip specific display functions */
8482 static void intel_init_display(struct drm_device *dev)
8483 {
8484         struct drm_i915_private *dev_priv = dev->dev_private;
8485
8486         /* We always want a DPMS function */
8487         if (HAS_DDI(dev)) {
8488                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8489                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8490                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8491                 dev_priv->display.off = haswell_crtc_off;
8492                 dev_priv->display.update_plane = ironlake_update_plane;
8493         } else if (HAS_PCH_SPLIT(dev)) {
8494                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8495                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8496                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8497                 dev_priv->display.off = ironlake_crtc_off;
8498                 dev_priv->display.update_plane = ironlake_update_plane;
8499         } else {
8500                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8501                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8502                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8503                 dev_priv->display.off = i9xx_crtc_off;
8504                 dev_priv->display.update_plane = i9xx_update_plane;
8505         }
8506
8507         /* Returns the core display clock speed */
8508         if (IS_VALLEYVIEW(dev))
8509                 dev_priv->display.get_display_clock_speed =
8510                         valleyview_get_display_clock_speed;
8511         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8512                 dev_priv->display.get_display_clock_speed =
8513                         i945_get_display_clock_speed;
8514         else if (IS_I915G(dev))
8515                 dev_priv->display.get_display_clock_speed =
8516                         i915_get_display_clock_speed;
8517         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8518                 dev_priv->display.get_display_clock_speed =
8519                         i9xx_misc_get_display_clock_speed;
8520         else if (IS_I915GM(dev))
8521                 dev_priv->display.get_display_clock_speed =
8522                         i915gm_get_display_clock_speed;
8523         else if (IS_I865G(dev))
8524                 dev_priv->display.get_display_clock_speed =
8525                         i865_get_display_clock_speed;
8526         else if (IS_I85X(dev))
8527                 dev_priv->display.get_display_clock_speed =
8528                         i855_get_display_clock_speed;
8529         else /* 852, 830 */
8530                 dev_priv->display.get_display_clock_speed =
8531                         i830_get_display_clock_speed;
8532
8533         if (HAS_PCH_SPLIT(dev)) {
8534                 if (IS_GEN5(dev)) {
8535                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8536                         dev_priv->display.write_eld = ironlake_write_eld;
8537                 } else if (IS_GEN6(dev)) {
8538                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8539                         dev_priv->display.write_eld = ironlake_write_eld;
8540                 } else if (IS_IVYBRIDGE(dev)) {
8541                         /* FIXME: detect B0+ stepping and use auto training */
8542                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8543                         dev_priv->display.write_eld = ironlake_write_eld;
8544                         dev_priv->display.modeset_global_resources =
8545                                 ivb_modeset_global_resources;
8546                 } else if (IS_HASWELL(dev)) {
8547                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8548                         dev_priv->display.write_eld = haswell_write_eld;
8549                         dev_priv->display.modeset_global_resources =
8550                                 haswell_modeset_global_resources;
8551                 }
8552         } else if (IS_G4X(dev)) {
8553                 dev_priv->display.write_eld = g4x_write_eld;
8554         }
8555
8556         /* Default just returns -ENODEV to indicate unsupported */
8557         dev_priv->display.queue_flip = intel_default_queue_flip;
8558
8559         switch (INTEL_INFO(dev)->gen) {
8560         case 2:
8561                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8562                 break;
8563
8564         case 3:
8565                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8566                 break;
8567
8568         case 4:
8569         case 5:
8570                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8571                 break;
8572
8573         case 6:
8574                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8575                 break;
8576         case 7:
8577                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8578                 break;
8579         }
8580 }
8581
8582 /*
8583  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8584  * resume, or other times.  This quirk makes sure that's the case for
8585  * affected systems.
8586  */
8587 static void quirk_pipea_force(struct drm_device *dev)
8588 {
8589         struct drm_i915_private *dev_priv = dev->dev_private;
8590
8591         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8592         DRM_INFO("applying pipe a force quirk\n");
8593 }
8594
8595 /*
8596  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8597  */
8598 static void quirk_ssc_force_disable(struct drm_device *dev)
8599 {
8600         struct drm_i915_private *dev_priv = dev->dev_private;
8601         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8602         DRM_INFO("applying lvds SSC disable quirk\n");
8603 }
8604
8605 /*
8606  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8607  * brightness value
8608  */
8609 static void quirk_invert_brightness(struct drm_device *dev)
8610 {
8611         struct drm_i915_private *dev_priv = dev->dev_private;
8612         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8613         DRM_INFO("applying inverted panel brightness quirk\n");
8614 }
8615
8616 struct intel_quirk {
8617         int device;
8618         int subsystem_vendor;
8619         int subsystem_device;
8620         void (*hook)(struct drm_device *dev);
8621 };
8622
8623 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8624 struct intel_dmi_quirk {
8625         void (*hook)(struct drm_device *dev);
8626         const struct dmi_system_id (*dmi_id_list)[];
8627 };
8628
8629 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8630 {
8631         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8632         return 1;
8633 }
8634
8635 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8636         {
8637                 .dmi_id_list = &(const struct dmi_system_id[]) {
8638                         {
8639                                 .callback = intel_dmi_reverse_brightness,
8640                                 .ident = "NCR Corporation",
8641                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8642                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8643                                 },
8644                         },
8645                         { }  /* terminating entry */
8646                 },
8647                 .hook = quirk_invert_brightness,
8648         },
8649 };
8650
8651 static struct intel_quirk intel_quirks[] = {
8652         /* HP Mini needs pipe A force quirk (LP: #322104) */
8653         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8654
8655         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8656         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8657
8658         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8659         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8660
8661         /* 830/845 need to leave pipe A & dpll A up */
8662         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8663         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8664
8665         /* Lenovo U160 cannot use SSC on LVDS */
8666         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8667
8668         /* Sony Vaio Y cannot use SSC on LVDS */
8669         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8670
8671         /* Acer Aspire 5734Z must invert backlight brightness */
8672         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8673
8674         /* Acer/eMachines G725 */
8675         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8676
8677         /* Acer/eMachines e725 */
8678         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8679
8680         /* Acer/Packard Bell NCL20 */
8681         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8682 };
8683
8684 static void intel_init_quirks(struct drm_device *dev)
8685 {
8686         struct pci_dev *d = dev->pdev;
8687         int i;
8688
8689         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8690                 struct intel_quirk *q = &intel_quirks[i];
8691
8692                 if (d->device == q->device &&
8693                     (d->subsystem_vendor == q->subsystem_vendor ||
8694                      q->subsystem_vendor == PCI_ANY_ID) &&
8695                     (d->subsystem_device == q->subsystem_device ||
8696                      q->subsystem_device == PCI_ANY_ID))
8697                         q->hook(dev);
8698         }
8699         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8700                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8701                         intel_dmi_quirks[i].hook(dev);
8702         }
8703 }
8704
8705 /* Disable the VGA plane that we never use */
8706 static void i915_disable_vga(struct drm_device *dev)
8707 {
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709         u8 sr1;
8710         u32 vga_reg = i915_vgacntrl_reg(dev);
8711
8712         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8713         outb(SR01, VGA_SR_INDEX);
8714         sr1 = inb(VGA_SR_DATA);
8715         outb(sr1 | 1<<5, VGA_SR_DATA);
8716         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8717         udelay(300);
8718
8719         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8720         POSTING_READ(vga_reg);
8721 }
8722
8723 void intel_modeset_init_hw(struct drm_device *dev)
8724 {
8725         intel_init_power_well(dev);
8726
8727         intel_prepare_ddi(dev);
8728
8729         intel_init_clock_gating(dev);
8730
8731         mutex_lock(&dev->struct_mutex);
8732         intel_enable_gt_powersave(dev);
8733         mutex_unlock(&dev->struct_mutex);
8734 }
8735
8736 void intel_modeset_init(struct drm_device *dev)
8737 {
8738         struct drm_i915_private *dev_priv = dev->dev_private;
8739         int i, ret;
8740
8741         drm_mode_config_init(dev);
8742
8743         dev->mode_config.min_width = 0;
8744         dev->mode_config.min_height = 0;
8745
8746         dev->mode_config.preferred_depth = 24;
8747         dev->mode_config.prefer_shadow = 1;
8748
8749         dev->mode_config.funcs = &intel_mode_funcs;
8750
8751         intel_init_quirks(dev);
8752
8753         intel_init_pm(dev);
8754
8755         intel_init_display(dev);
8756
8757         if (IS_GEN2(dev)) {
8758                 dev->mode_config.max_width = 2048;
8759                 dev->mode_config.max_height = 2048;
8760         } else if (IS_GEN3(dev)) {
8761                 dev->mode_config.max_width = 4096;
8762                 dev->mode_config.max_height = 4096;
8763         } else {
8764                 dev->mode_config.max_width = 8192;
8765                 dev->mode_config.max_height = 8192;
8766         }
8767         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8768
8769         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8770                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8771
8772         for (i = 0; i < dev_priv->num_pipe; i++) {
8773                 intel_crtc_init(dev, i);
8774                 ret = intel_plane_init(dev, i);
8775                 if (ret)
8776                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8777         }
8778
8779         intel_cpu_pll_init(dev);
8780         intel_pch_pll_init(dev);
8781
8782         /* Just disable it once at startup */
8783         i915_disable_vga(dev);
8784         intel_setup_outputs(dev);
8785
8786         /* Just in case the BIOS is doing something questionable. */
8787         intel_disable_fbc(dev);
8788 }
8789
8790 static void
8791 intel_connector_break_all_links(struct intel_connector *connector)
8792 {
8793         connector->base.dpms = DRM_MODE_DPMS_OFF;
8794         connector->base.encoder = NULL;
8795         connector->encoder->connectors_active = false;
8796         connector->encoder->base.crtc = NULL;
8797 }
8798
8799 static void intel_enable_pipe_a(struct drm_device *dev)
8800 {
8801         struct intel_connector *connector;
8802         struct drm_connector *crt = NULL;
8803         struct intel_load_detect_pipe load_detect_temp;
8804
8805         /* We can't just switch on the pipe A, we need to set things up with a
8806          * proper mode and output configuration. As a gross hack, enable pipe A
8807          * by enabling the load detect pipe once. */
8808         list_for_each_entry(connector,
8809                             &dev->mode_config.connector_list,
8810                             base.head) {
8811                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8812                         crt = &connector->base;
8813                         break;
8814                 }
8815         }
8816
8817         if (!crt)
8818                 return;
8819
8820         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8821                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8822
8823
8824 }
8825
8826 static bool
8827 intel_check_plane_mapping(struct intel_crtc *crtc)
8828 {
8829         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8830         u32 reg, val;
8831
8832         if (dev_priv->num_pipe == 1)
8833                 return true;
8834
8835         reg = DSPCNTR(!crtc->plane);
8836         val = I915_READ(reg);
8837
8838         if ((val & DISPLAY_PLANE_ENABLE) &&
8839             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8840                 return false;
8841
8842         return true;
8843 }
8844
8845 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8846 {
8847         struct drm_device *dev = crtc->base.dev;
8848         struct drm_i915_private *dev_priv = dev->dev_private;
8849         u32 reg;
8850
8851         /* Clear any frame start delays used for debugging left by the BIOS */
8852         reg = PIPECONF(crtc->cpu_transcoder);
8853         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8854
8855         /* We need to sanitize the plane -> pipe mapping first because this will
8856          * disable the crtc (and hence change the state) if it is wrong. Note
8857          * that gen4+ has a fixed plane -> pipe mapping.  */
8858         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8859                 struct intel_connector *connector;
8860                 bool plane;
8861
8862                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8863                               crtc->base.base.id);
8864
8865                 /* Pipe has the wrong plane attached and the plane is active.
8866                  * Temporarily change the plane mapping and disable everything
8867                  * ...  */
8868                 plane = crtc->plane;
8869                 crtc->plane = !plane;
8870                 dev_priv->display.crtc_disable(&crtc->base);
8871                 crtc->plane = plane;
8872
8873                 /* ... and break all links. */
8874                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8875                                     base.head) {
8876                         if (connector->encoder->base.crtc != &crtc->base)
8877                                 continue;
8878
8879                         intel_connector_break_all_links(connector);
8880                 }
8881
8882                 WARN_ON(crtc->active);
8883                 crtc->base.enabled = false;
8884         }
8885
8886         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8887             crtc->pipe == PIPE_A && !crtc->active) {
8888                 /* BIOS forgot to enable pipe A, this mostly happens after
8889                  * resume. Force-enable the pipe to fix this, the update_dpms
8890                  * call below we restore the pipe to the right state, but leave
8891                  * the required bits on. */
8892                 intel_enable_pipe_a(dev);
8893         }
8894
8895         /* Adjust the state of the output pipe according to whether we
8896          * have active connectors/encoders. */
8897         intel_crtc_update_dpms(&crtc->base);
8898
8899         if (crtc->active != crtc->base.enabled) {
8900                 struct intel_encoder *encoder;
8901
8902                 /* This can happen either due to bugs in the get_hw_state
8903                  * functions or because the pipe is force-enabled due to the
8904                  * pipe A quirk. */
8905                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8906                               crtc->base.base.id,
8907                               crtc->base.enabled ? "enabled" : "disabled",
8908                               crtc->active ? "enabled" : "disabled");
8909
8910                 crtc->base.enabled = crtc->active;
8911
8912                 /* Because we only establish the connector -> encoder ->
8913                  * crtc links if something is active, this means the
8914                  * crtc is now deactivated. Break the links. connector
8915                  * -> encoder links are only establish when things are
8916                  *  actually up, hence no need to break them. */
8917                 WARN_ON(crtc->active);
8918
8919                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8920                         WARN_ON(encoder->connectors_active);
8921                         encoder->base.crtc = NULL;
8922                 }
8923         }
8924 }
8925
8926 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8927 {
8928         struct intel_connector *connector;
8929         struct drm_device *dev = encoder->base.dev;
8930
8931         /* We need to check both for a crtc link (meaning that the
8932          * encoder is active and trying to read from a pipe) and the
8933          * pipe itself being active. */
8934         bool has_active_crtc = encoder->base.crtc &&
8935                 to_intel_crtc(encoder->base.crtc)->active;
8936
8937         if (encoder->connectors_active && !has_active_crtc) {
8938                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8939                               encoder->base.base.id,
8940                               drm_get_encoder_name(&encoder->base));
8941
8942                 /* Connector is active, but has no active pipe. This is
8943                  * fallout from our resume register restoring. Disable
8944                  * the encoder manually again. */
8945                 if (encoder->base.crtc) {
8946                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8947                                       encoder->base.base.id,
8948                                       drm_get_encoder_name(&encoder->base));
8949                         encoder->disable(encoder);
8950                 }
8951
8952                 /* Inconsistent output/port/pipe state happens presumably due to
8953                  * a bug in one of the get_hw_state functions. Or someplace else
8954                  * in our code, like the register restore mess on resume. Clamp
8955                  * things to off as a safer default. */
8956                 list_for_each_entry(connector,
8957                                     &dev->mode_config.connector_list,
8958                                     base.head) {
8959                         if (connector->encoder != encoder)
8960                                 continue;
8961
8962                         intel_connector_break_all_links(connector);
8963                 }
8964         }
8965         /* Enabled encoders without active connectors will be fixed in
8966          * the crtc fixup. */
8967 }
8968
8969 void i915_redisable_vga(struct drm_device *dev)
8970 {
8971         struct drm_i915_private *dev_priv = dev->dev_private;
8972         u32 vga_reg = i915_vgacntrl_reg(dev);
8973
8974         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8975                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8976                 i915_disable_vga(dev);
8977         }
8978 }
8979
8980 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8981  * and i915 state tracking structures. */
8982 void intel_modeset_setup_hw_state(struct drm_device *dev,
8983                                   bool force_restore)
8984 {
8985         struct drm_i915_private *dev_priv = dev->dev_private;
8986         enum pipe pipe;
8987         u32 tmp;
8988         struct intel_crtc *crtc;
8989         struct intel_encoder *encoder;
8990         struct intel_connector *connector;
8991
8992         if (HAS_DDI(dev)) {
8993                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8994
8995                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8996                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8997                         case TRANS_DDI_EDP_INPUT_A_ON:
8998                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8999                                 pipe = PIPE_A;
9000                                 break;
9001                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9002                                 pipe = PIPE_B;
9003                                 break;
9004                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9005                                 pipe = PIPE_C;
9006                                 break;
9007                         }
9008
9009                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9010                         crtc->cpu_transcoder = TRANSCODER_EDP;
9011
9012                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9013                                       pipe_name(pipe));
9014                 }
9015         }
9016
9017         for_each_pipe(pipe) {
9018                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9019
9020                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9021                 if (tmp & PIPECONF_ENABLE)
9022                         crtc->active = true;
9023                 else
9024                         crtc->active = false;
9025
9026                 crtc->base.enabled = crtc->active;
9027
9028                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9029                               crtc->base.base.id,
9030                               crtc->active ? "enabled" : "disabled");
9031         }
9032
9033         if (HAS_DDI(dev))
9034                 intel_ddi_setup_hw_pll_state(dev);
9035
9036         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9037                             base.head) {
9038                 pipe = 0;
9039
9040                 if (encoder->get_hw_state(encoder, &pipe)) {
9041                         encoder->base.crtc =
9042                                 dev_priv->pipe_to_crtc_mapping[pipe];
9043                 } else {
9044                         encoder->base.crtc = NULL;
9045                 }
9046
9047                 encoder->connectors_active = false;
9048                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9049                               encoder->base.base.id,
9050                               drm_get_encoder_name(&encoder->base),
9051                               encoder->base.crtc ? "enabled" : "disabled",
9052                               pipe);
9053         }
9054
9055         list_for_each_entry(connector, &dev->mode_config.connector_list,
9056                             base.head) {
9057                 if (connector->get_hw_state(connector)) {
9058                         connector->base.dpms = DRM_MODE_DPMS_ON;
9059                         connector->encoder->connectors_active = true;
9060                         connector->base.encoder = &connector->encoder->base;
9061                 } else {
9062                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9063                         connector->base.encoder = NULL;
9064                 }
9065                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9066                               connector->base.base.id,
9067                               drm_get_connector_name(&connector->base),
9068                               connector->base.encoder ? "enabled" : "disabled");
9069         }
9070
9071         /* HW state is read out, now we need to sanitize this mess. */
9072         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9073                             base.head) {
9074                 intel_sanitize_encoder(encoder);
9075         }
9076
9077         for_each_pipe(pipe) {
9078                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9079                 intel_sanitize_crtc(crtc);
9080         }
9081
9082         if (force_restore) {
9083                 for_each_pipe(pipe) {
9084                         intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9085                 }
9086
9087                 i915_redisable_vga(dev);
9088         } else {
9089                 intel_modeset_update_staged_output_state(dev);
9090         }
9091
9092         intel_modeset_check_state(dev);
9093
9094         drm_mode_config_reset(dev);
9095 }
9096
9097 void intel_modeset_gem_init(struct drm_device *dev)
9098 {
9099         intel_modeset_init_hw(dev);
9100
9101         intel_setup_overlay(dev);
9102
9103         intel_modeset_setup_hw_state(dev, false);
9104 }
9105
9106 void intel_modeset_cleanup(struct drm_device *dev)
9107 {
9108         struct drm_i915_private *dev_priv = dev->dev_private;
9109         struct drm_crtc *crtc;
9110         struct intel_crtc *intel_crtc;
9111
9112         drm_kms_helper_poll_fini(dev);
9113         mutex_lock(&dev->struct_mutex);
9114
9115         intel_unregister_dsm_handler();
9116
9117
9118         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9119                 /* Skip inactive CRTCs */
9120                 if (!crtc->fb)
9121                         continue;
9122
9123                 intel_crtc = to_intel_crtc(crtc);
9124                 intel_increase_pllclock(crtc);
9125         }
9126
9127         intel_disable_fbc(dev);
9128
9129         intel_disable_gt_powersave(dev);
9130
9131         ironlake_teardown_rc6(dev);
9132
9133         if (IS_VALLEYVIEW(dev))
9134                 vlv_init_dpio(dev);
9135
9136         mutex_unlock(&dev->struct_mutex);
9137
9138         /* Disable the irq before mode object teardown, for the irq might
9139          * enqueue unpin/hotplug work. */
9140         drm_irq_uninstall(dev);
9141         cancel_work_sync(&dev_priv->hotplug_work);
9142         cancel_work_sync(&dev_priv->rps.work);
9143
9144         /* flush any delayed tasks or pending work */
9145         flush_scheduled_work();
9146
9147         drm_mode_config_cleanup(dev);
9148
9149         intel_cleanup_overlay(dev);
9150 }
9151
9152 /*
9153  * Return which encoder is currently attached for connector.
9154  */
9155 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9156 {
9157         return &intel_attached_encoder(connector)->base;
9158 }
9159
9160 void intel_connector_attach_encoder(struct intel_connector *connector,
9161                                     struct intel_encoder *encoder)
9162 {
9163         connector->encoder = encoder;
9164         drm_mode_connector_attach_encoder(&connector->base,
9165                                           &encoder->base);
9166 }
9167
9168 /*
9169  * set vga decode state - true == enable VGA decode
9170  */
9171 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9172 {
9173         struct drm_i915_private *dev_priv = dev->dev_private;
9174         u16 gmch_ctrl;
9175
9176         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9177         if (state)
9178                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9179         else
9180                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9181         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9182         return 0;
9183 }
9184
9185 #ifdef CONFIG_DEBUG_FS
9186 #include <linux/seq_file.h>
9187
9188 struct intel_display_error_state {
9189         struct intel_cursor_error_state {
9190                 u32 control;
9191                 u32 position;
9192                 u32 base;
9193                 u32 size;
9194         } cursor[I915_MAX_PIPES];
9195
9196         struct intel_pipe_error_state {
9197                 u32 conf;
9198                 u32 source;
9199
9200                 u32 htotal;
9201                 u32 hblank;
9202                 u32 hsync;
9203                 u32 vtotal;
9204                 u32 vblank;
9205                 u32 vsync;
9206         } pipe[I915_MAX_PIPES];
9207
9208         struct intel_plane_error_state {
9209                 u32 control;
9210                 u32 stride;
9211                 u32 size;
9212                 u32 pos;
9213                 u32 addr;
9214                 u32 surface;
9215                 u32 tile_offset;
9216         } plane[I915_MAX_PIPES];
9217 };
9218
9219 struct intel_display_error_state *
9220 intel_display_capture_error_state(struct drm_device *dev)
9221 {
9222         drm_i915_private_t *dev_priv = dev->dev_private;
9223         struct intel_display_error_state *error;
9224         enum transcoder cpu_transcoder;
9225         int i;
9226
9227         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9228         if (error == NULL)
9229                 return NULL;
9230
9231         for_each_pipe(i) {
9232                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9233
9234                 error->cursor[i].control = I915_READ(CURCNTR(i));
9235                 error->cursor[i].position = I915_READ(CURPOS(i));
9236                 error->cursor[i].base = I915_READ(CURBASE(i));
9237
9238                 error->plane[i].control = I915_READ(DSPCNTR(i));
9239                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9240                 error->plane[i].size = I915_READ(DSPSIZE(i));
9241                 error->plane[i].pos = I915_READ(DSPPOS(i));
9242                 error->plane[i].addr = I915_READ(DSPADDR(i));
9243                 if (INTEL_INFO(dev)->gen >= 4) {
9244                         error->plane[i].surface = I915_READ(DSPSURF(i));
9245                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9246                 }
9247
9248                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9249                 error->pipe[i].source = I915_READ(PIPESRC(i));
9250                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9251                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9252                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9253                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9254                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9255                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9256         }
9257
9258         return error;
9259 }
9260
9261 void
9262 intel_display_print_error_state(struct seq_file *m,
9263                                 struct drm_device *dev,
9264                                 struct intel_display_error_state *error)
9265 {
9266         drm_i915_private_t *dev_priv = dev->dev_private;
9267         int i;
9268
9269         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9270         for_each_pipe(i) {
9271                 seq_printf(m, "Pipe [%d]:\n", i);
9272                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9273                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9274                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9275                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9276                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9277                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9278                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9279                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9280
9281                 seq_printf(m, "Plane [%d]:\n", i);
9282                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9283                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9284                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9285                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9286                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9287                 if (INTEL_INFO(dev)->gen >= 4) {
9288                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9289                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9290                 }
9291
9292                 seq_printf(m, "Cursor [%d]:\n", i);
9293                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9294                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9295                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9296         }
9297 }
9298 #endif