2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
82 static const uint32_t intel_cursor_formats[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
126 int p2_slow, p2_fast;
129 typedef struct intel_limit intel_limit_t;
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
146 return vco_freq[hpll_freq] * 1000;
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
162 divider = val & CCK_FREQUENCY_VALUES;
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
172 intel_pch_rawclk(struct drm_device *dev)
174 struct drm_i915_private *dev_priv = dev->dev_private;
176 WARN_ON(!HAS_PCH_SPLIT(dev));
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_1067:
203 case CLKCFG_FSB_1333:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 if (!IS_VALLEYVIEW(dev_priv))
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
385 /* Ironlake / Sandybridge
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
456 static const intel_limit_t intel_limits_vlv = {
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
472 static const intel_limit_t intel_limits_chv = {
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
501 needs_modeset(struct drm_crtc_state *state)
503 return drm_atomic_crtc_needs_modeset(state);
507 * Returns whether any output on the specified pipe is of the specified type
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
547 WARN_ON(num_connectors == 0);
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
563 limit = &intel_limits_ironlake_dual_lvds;
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
568 limit = &intel_limits_ironlake_single_lvds;
571 limit = &intel_limits_ironlake_dac;
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
623 limit = &intel_limits_i9xx_sdvo;
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
630 limit = &intel_limits_i8xx_dac;
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682 return clock->dot / 5;
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695 return clock->dot / 5;
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
744 struct drm_device *dev = crtc_state->base.crtc->dev;
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
755 return limit->p2.p2_slow;
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
760 return limit->p2.p2_fast;
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
770 struct drm_device *dev = crtc_state->base.crtc->dev;
774 memset(best_clock, 0, sizeof(*best_clock));
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
795 clock.p != match_clock->p)
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
808 return (err != target);
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
817 struct drm_device *dev = crtc_state->base.crtc->dev;
821 memset(best_clock, 0, sizeof(*best_clock));
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
840 clock.p != match_clock->p)
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
853 return (err != target);
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
862 struct drm_device *dev = crtc_state->base.crtc->dev;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
869 memset(best_clock, 0, sizeof(*best_clock));
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
918 if (IS_CHERRYVIEW(dev)) {
921 return calculated_clock->p > best_clock->p;
924 if (WARN_ON_ONCE(!target_freq))
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
941 return *error_ppm + 10 < best_error_ppm;
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
958 target *= 5; /* fast clock */
960 memset(best_clock, 0, sizeof(*best_clock));
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 vlv_calc_dpll_params(refclk, &clock);
977 if (!intel_PLL_is_valid(dev, limit,
981 if (!vlv_PLL_is_optimal(dev, target,
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1028 clock.p = clock.p1 * clock.p2;
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1033 if (m2 > INT_MAX/clock.m1)
1038 chv_calc_dpll_params(refclk, &clock);
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1092 return intel_crtc->config->cpu_transcoder;
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1103 line_mask = DSL_LINEMASK_GEN2;
1105 line_mask = DSL_LINEMASK_GEN3;
1107 line1 = I915_READ(reg) & line_mask;
1109 line2 = I915_READ(reg) & line_mask;
1111 return line1 == line2;
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1143 WARN(1, "pipe_off wait timed out\n");
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1151 static const char *state_string(bool enabled)
1153 return enabled ? "on" : "off";
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1165 val = I915_READ(reg);
1166 cur_state = !!(val & DPLL_VCO_ENABLE);
1167 I915_STATE_WARN(cur_state != state,
1168 "PLL state assertion failure (expected %s, current %s)\n",
1169 state_string(state), state_string(cur_state));
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1178 mutex_lock(&dev_priv->sb_lock);
1179 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180 mutex_unlock(&dev_priv->sb_lock);
1182 cur_state = val & DSI_PLL_VCO_EN;
1183 I915_STATE_WARN(cur_state != state,
1184 "DSI PLL state assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1195 if (crtc->config->shared_dpll < 0)
1198 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203 struct intel_shared_dpll *pll,
1207 struct intel_dpll_hw_state hw_state;
1210 "asserting DPLL %s with no DPLL\n", state_string(state)))
1213 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214 I915_STATE_WARN(cur_state != state,
1215 "%s assertion failure (expected %s, current %s)\n",
1216 pll->name, state_string(state), state_string(cur_state));
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
1230 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1231 val = I915_READ(reg);
1232 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & FDI_TX_ENABLE);
1238 I915_STATE_WARN(cur_state != state,
1239 "FDI TX state assertion failure (expected %s, current %s)\n",
1240 state_string(state), state_string(cur_state));
1242 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1245 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1252 reg = FDI_RX_CTL(pipe);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & FDI_RX_ENABLE);
1255 I915_STATE_WARN(cur_state != state,
1256 "FDI RX state assertion failure (expected %s, current %s)\n",
1257 state_string(state), state_string(cur_state));
1259 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1262 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1268 /* ILK FDI PLL is always enabled */
1269 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1272 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1273 if (HAS_DDI(dev_priv->dev))
1276 reg = FDI_TX_CTL(pipe);
1277 val = I915_READ(reg);
1278 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1281 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282 enum pipe pipe, bool state)
1288 reg = FDI_RX_CTL(pipe);
1289 val = I915_READ(reg);
1290 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1291 I915_STATE_WARN(cur_state != state,
1292 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293 state_string(state), state_string(cur_state));
1296 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1299 struct drm_device *dev = dev_priv->dev;
1302 enum pipe panel_pipe = PIPE_A;
1305 if (WARN_ON(HAS_DDI(dev)))
1308 if (HAS_PCH_SPLIT(dev)) {
1311 pp_reg = PCH_PP_CONTROL;
1312 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1314 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316 panel_pipe = PIPE_B;
1317 /* XXX: else fix for eDP */
1318 } else if (IS_VALLEYVIEW(dev)) {
1319 /* presumably write lock depends on pipe, not port select */
1320 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1323 pp_reg = PP_CONTROL;
1324 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325 panel_pipe = PIPE_B;
1328 val = I915_READ(pp_reg);
1329 if (!(val & PANEL_POWER_ON) ||
1330 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1333 I915_STATE_WARN(panel_pipe == pipe && locked,
1334 "panel assertion failure, pipe %c regs locked\n",
1338 static void assert_cursor(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, bool state)
1341 struct drm_device *dev = dev_priv->dev;
1344 if (IS_845G(dev) || IS_I865G(dev))
1345 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1347 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1349 I915_STATE_WARN(cur_state != state,
1350 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1353 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1356 void assert_pipe(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, bool state)
1362 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1365 /* if we need the pipe quirk it must be always on */
1366 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1370 if (!intel_display_power_is_enabled(dev_priv,
1371 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1374 reg = PIPECONF(cpu_transcoder);
1375 val = I915_READ(reg);
1376 cur_state = !!(val & PIPECONF_ENABLE);
1379 I915_STATE_WARN(cur_state != state,
1380 "pipe %c assertion failure (expected %s, current %s)\n",
1381 pipe_name(pipe), state_string(state), state_string(cur_state));
1384 static void assert_plane(struct drm_i915_private *dev_priv,
1385 enum plane plane, bool state)
1391 reg = DSPCNTR(plane);
1392 val = I915_READ(reg);
1393 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1394 I915_STATE_WARN(cur_state != state,
1395 "plane %c assertion failure (expected %s, current %s)\n",
1396 plane_name(plane), state_string(state), state_string(cur_state));
1399 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1402 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1405 struct drm_device *dev = dev_priv->dev;
1410 /* Primary planes are fixed to pipes on gen4+ */
1411 if (INTEL_INFO(dev)->gen >= 4) {
1412 reg = DSPCNTR(pipe);
1413 val = I915_READ(reg);
1414 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1415 "plane %c assertion failure, should be disabled but not\n",
1420 /* Need to check both planes against the pipe */
1421 for_each_pipe(dev_priv, i) {
1423 val = I915_READ(reg);
1424 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425 DISPPLANE_SEL_PIPE_SHIFT;
1426 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1427 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428 plane_name(i), pipe_name(pipe));
1432 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1435 struct drm_device *dev = dev_priv->dev;
1439 if (INTEL_INFO(dev)->gen >= 9) {
1440 for_each_sprite(dev_priv, pipe, sprite) {
1441 val = I915_READ(PLANE_CTL(pipe, sprite));
1442 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1443 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444 sprite, pipe_name(pipe));
1446 } else if (IS_VALLEYVIEW(dev)) {
1447 for_each_sprite(dev_priv, pipe, sprite) {
1448 reg = SPCNTR(pipe, sprite);
1449 val = I915_READ(reg);
1450 I915_STATE_WARN(val & SP_ENABLE,
1451 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1452 sprite_name(pipe, sprite), pipe_name(pipe));
1454 } else if (INTEL_INFO(dev)->gen >= 7) {
1456 val = I915_READ(reg);
1457 I915_STATE_WARN(val & SPRITE_ENABLE,
1458 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1459 plane_name(pipe), pipe_name(pipe));
1460 } else if (INTEL_INFO(dev)->gen >= 5) {
1461 reg = DVSCNTR(pipe);
1462 val = I915_READ(reg);
1463 I915_STATE_WARN(val & DVS_ENABLE,
1464 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1465 plane_name(pipe), pipe_name(pipe));
1469 static void assert_vblank_disabled(struct drm_crtc *crtc)
1471 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1472 drm_crtc_vblank_put(crtc);
1475 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1480 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1482 val = I915_READ(PCH_DREF_CONTROL);
1483 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484 DREF_SUPERSPREAD_SOURCE_MASK));
1485 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1488 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1495 reg = PCH_TRANSCONF(pipe);
1496 val = I915_READ(reg);
1497 enabled = !!(val & TRANS_ENABLE);
1498 I915_STATE_WARN(enabled,
1499 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1503 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 port_sel, u32 val)
1506 if ((val & DP_PORT_EN) == 0)
1509 if (HAS_PCH_CPT(dev_priv->dev)) {
1510 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1514 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1518 if ((val & DP_PIPE_MASK) != (pipe << 30))
1524 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1527 if ((val & SDVO_ENABLE) == 0)
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1533 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1537 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1543 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544 enum pipe pipe, u32 val)
1546 if ((val & LVDS_PORT_EN) == 0)
1549 if (HAS_PCH_CPT(dev_priv->dev)) {
1550 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1553 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1559 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560 enum pipe pipe, u32 val)
1562 if ((val & ADPA_DAC_ENABLE) == 0)
1564 if (HAS_PCH_CPT(dev_priv->dev)) {
1565 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1568 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1574 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1575 enum pipe pipe, int reg, u32 port_sel)
1577 u32 val = I915_READ(reg);
1578 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1579 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1580 reg, pipe_name(pipe));
1582 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1583 && (val & DP_PIPEB_SELECT),
1584 "IBX PCH dp port still using transcoder B\n");
1587 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588 enum pipe pipe, int reg)
1590 u32 val = I915_READ(reg);
1591 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1592 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1593 reg, pipe_name(pipe));
1595 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1596 && (val & SDVO_PIPE_B_SELECT),
1597 "IBX PCH hdmi port still using transcoder B\n");
1600 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1606 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1611 val = I915_READ(reg);
1612 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1613 "PCH VGA enabled on transcoder %c, should be disabled\n",
1617 val = I915_READ(reg);
1618 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1619 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1622 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1627 static void vlv_enable_pll(struct intel_crtc *crtc,
1628 const struct intel_crtc_state *pipe_config)
1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 int reg = DPLL(crtc->pipe);
1633 u32 dpll = pipe_config->dpll_hw_state.dpll;
1635 assert_pipe_disabled(dev_priv, crtc->pipe);
1637 /* No really, not for ILK+ */
1638 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1640 /* PLL is protected by panel, make sure we can write it */
1641 if (IS_MOBILE(dev_priv->dev))
1642 assert_panel_unlocked(dev_priv, crtc->pipe);
1644 I915_WRITE(reg, dpll);
1648 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1651 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1652 POSTING_READ(DPLL_MD(crtc->pipe));
1654 /* We do this three times for luck */
1655 I915_WRITE(reg, dpll);
1657 udelay(150); /* wait for warmup */
1658 I915_WRITE(reg, dpll);
1660 udelay(150); /* wait for warmup */
1661 I915_WRITE(reg, dpll);
1663 udelay(150); /* wait for warmup */
1666 static void chv_enable_pll(struct intel_crtc *crtc,
1667 const struct intel_crtc_state *pipe_config)
1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int pipe = crtc->pipe;
1672 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1675 assert_pipe_disabled(dev_priv, crtc->pipe);
1677 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1679 mutex_lock(&dev_priv->sb_lock);
1681 /* Enable back the 10bit clock to display controller */
1682 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683 tmp |= DPIO_DCLKP_EN;
1684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1686 mutex_unlock(&dev_priv->sb_lock);
1689 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1694 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1696 /* Check PLL is locked */
1697 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1698 DRM_ERROR("PLL %d failed to lock\n", pipe);
1700 /* not sure when this should be written */
1701 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1702 POSTING_READ(DPLL_MD(pipe));
1705 static int intel_num_dvo_pipes(struct drm_device *dev)
1707 struct intel_crtc *crtc;
1710 for_each_intel_crtc(dev, crtc)
1711 count += crtc->base.state->active &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1717 static void i9xx_enable_pll(struct intel_crtc *crtc)
1719 struct drm_device *dev = crtc->base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 int reg = DPLL(crtc->pipe);
1722 u32 dpll = crtc->config->dpll_hw_state.dpll;
1724 assert_pipe_disabled(dev_priv, crtc->pipe);
1726 /* No really, not for ILK+ */
1727 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1729 /* PLL is protected by panel, make sure we can write it */
1730 if (IS_MOBILE(dev) && !IS_I830(dev))
1731 assert_panel_unlocked(dev_priv, crtc->pipe);
1733 /* Enable DVO 2x clock on both PLLs if necessary */
1734 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1736 * It appears to be important that we don't enable this
1737 * for the current pipe before otherwise configuring the
1738 * PLL. No idea how this should be handled if multiple
1739 * DVO outputs are enabled simultaneosly.
1741 dpll |= DPLL_DVO_2X_MODE;
1742 I915_WRITE(DPLL(!crtc->pipe),
1743 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1746 /* Wait for the clocks to stabilize. */
1750 if (INTEL_INFO(dev)->gen >= 4) {
1751 I915_WRITE(DPLL_MD(crtc->pipe),
1752 crtc->config->dpll_hw_state.dpll_md);
1754 /* The pixel multiplier can only be updated once the
1755 * DPLL is enabled and the clocks are stable.
1757 * So write it again.
1759 I915_WRITE(reg, dpll);
1762 /* We do this three times for luck */
1763 I915_WRITE(reg, dpll);
1765 udelay(150); /* wait for warmup */
1766 I915_WRITE(reg, dpll);
1768 udelay(150); /* wait for warmup */
1769 I915_WRITE(reg, dpll);
1771 udelay(150); /* wait for warmup */
1775 * i9xx_disable_pll - disable a PLL
1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe PLL to disable
1779 * Disable the PLL for @pipe, making sure the pipe is off first.
1781 * Note! This is for pre-ILK only.
1783 static void i9xx_disable_pll(struct intel_crtc *crtc)
1785 struct drm_device *dev = crtc->base.dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 enum pipe pipe = crtc->pipe;
1789 /* Disable DVO 2x clock on both PLLs if necessary */
1791 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1792 !intel_num_dvo_pipes(dev)) {
1793 I915_WRITE(DPLL(PIPE_B),
1794 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795 I915_WRITE(DPLL(PIPE_A),
1796 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1799 /* Don't disable pipe or pipe PLLs if needed */
1800 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1807 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1808 POSTING_READ(DPLL(pipe));
1811 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1819 * Leave integrated clock source and reference clock enabled for pipe B.
1820 * The latter is needed for VGA hotplug / manual detection.
1822 val = DPLL_VGA_MODE_DIS;
1824 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1825 I915_WRITE(DPLL(pipe), val);
1826 POSTING_READ(DPLL(pipe));
1830 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1832 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1835 /* Make sure the pipe isn't still relying on us */
1836 assert_pipe_disabled(dev_priv, pipe);
1838 /* Set PLL en = 0 */
1839 val = DPLL_SSC_REF_CLK_CHV |
1840 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1842 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843 I915_WRITE(DPLL(pipe), val);
1844 POSTING_READ(DPLL(pipe));
1846 mutex_lock(&dev_priv->sb_lock);
1848 /* Disable 10bit clock to display controller */
1849 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850 val &= ~DPIO_DCLKP_EN;
1851 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1853 mutex_unlock(&dev_priv->sb_lock);
1856 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
1863 switch (dport->port) {
1865 port_mask = DPLL_PORTB_READY_MASK;
1869 port_mask = DPLL_PORTC_READY_MASK;
1871 expected_mask <<= 4;
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1886 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1892 if (WARN_ON(pll == NULL))
1895 WARN_ON(!pll->config.crtc_mask);
1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1901 pll->mode_set(dev_priv, pll);
1906 * intel_enable_shared_dpll - enable PCH PLL
1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1913 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1919 if (WARN_ON(pll == NULL))
1922 if (WARN_ON(pll->config.crtc_mask == 0))
1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1926 pll->name, pll->active, pll->on,
1927 crtc->base.base.id);
1929 if (pll->active++) {
1931 assert_shared_dpll_enabled(dev_priv, pll);
1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1939 pll->enable(dev_priv, pll);
1943 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1949 /* PCH only available on ILK+ */
1950 if (INTEL_INFO(dev)->gen < 5)
1956 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1959 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960 pll->name, pll->active, pll->on,
1961 crtc->base.base.id);
1963 if (WARN_ON(pll->active == 0)) {
1964 assert_shared_dpll_disabled(dev_priv, pll);
1968 assert_shared_dpll_enabled(dev_priv, pll);
1973 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1974 pll->disable(dev_priv, pll);
1977 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1980 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1983 struct drm_device *dev = dev_priv->dev;
1984 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1986 uint32_t reg, val, pipeconf_val;
1988 /* PCH only available on ILK+ */
1989 BUG_ON(!HAS_PCH_SPLIT(dev));
1991 /* Make sure PCH DPLL is enabled */
1992 assert_shared_dpll_enabled(dev_priv,
1993 intel_crtc_to_shared_dpll(intel_crtc));
1995 /* FDI must be feeding us bits for PCH ports */
1996 assert_fdi_tx_enabled(dev_priv, pipe);
1997 assert_fdi_rx_enabled(dev_priv, pipe);
1999 if (HAS_PCH_CPT(dev)) {
2000 /* Workaround: Set the timing override bit before enabling the
2001 * pch transcoder. */
2002 reg = TRANS_CHICKEN2(pipe);
2003 val = I915_READ(reg);
2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005 I915_WRITE(reg, val);
2008 reg = PCH_TRANSCONF(pipe);
2009 val = I915_READ(reg);
2010 pipeconf_val = I915_READ(PIPECONF(pipe));
2012 if (HAS_PCH_IBX(dev_priv->dev)) {
2014 * Make the BPC in transcoder be consistent with
2015 * that in pipeconf reg. For HDMI we must use 8bpc
2016 * here for both 8bpc and 12bpc.
2018 val &= ~PIPECONF_BPC_MASK;
2019 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020 val |= PIPECONF_8BPC;
2022 val |= pipeconf_val & PIPECONF_BPC_MASK;
2025 val &= ~TRANS_INTERLACE_MASK;
2026 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2027 if (HAS_PCH_IBX(dev_priv->dev) &&
2028 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2029 val |= TRANS_LEGACY_INTERLACED_ILK;
2031 val |= TRANS_INTERLACED;
2033 val |= TRANS_PROGRESSIVE;
2035 I915_WRITE(reg, val | TRANS_ENABLE);
2036 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2037 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2040 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2041 enum transcoder cpu_transcoder)
2043 u32 val, pipeconf_val;
2045 /* PCH only available on ILK+ */
2046 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2048 /* FDI must be feeding us bits for PCH ports */
2049 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2050 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2052 /* Workaround: set timing override bit. */
2053 val = I915_READ(_TRANSA_CHICKEN2);
2054 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2055 I915_WRITE(_TRANSA_CHICKEN2, val);
2058 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2060 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061 PIPECONF_INTERLACED_ILK)
2062 val |= TRANS_INTERLACED;
2064 val |= TRANS_PROGRESSIVE;
2066 I915_WRITE(LPT_TRANSCONF, val);
2067 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2068 DRM_ERROR("Failed to enable PCH transcoder\n");
2071 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2074 struct drm_device *dev = dev_priv->dev;
2077 /* FDI relies on the transcoder */
2078 assert_fdi_tx_disabled(dev_priv, pipe);
2079 assert_fdi_rx_disabled(dev_priv, pipe);
2081 /* Ports must be off as well */
2082 assert_pch_ports_disabled(dev_priv, pipe);
2084 reg = PCH_TRANSCONF(pipe);
2085 val = I915_READ(reg);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(reg, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2090 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2092 if (!HAS_PCH_IBX(dev)) {
2093 /* Workaround: Clear the timing override chicken bit again. */
2094 reg = TRANS_CHICKEN2(pipe);
2095 val = I915_READ(reg);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(reg, val);
2101 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2105 val = I915_READ(LPT_TRANSCONF);
2106 val &= ~TRANS_ENABLE;
2107 I915_WRITE(LPT_TRANSCONF, val);
2108 /* wait for PCH transcoder off, transcoder state */
2109 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2110 DRM_ERROR("Failed to disable PCH transcoder\n");
2112 /* Workaround: clear timing override bit. */
2113 val = I915_READ(_TRANSA_CHICKEN2);
2114 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2115 I915_WRITE(_TRANSA_CHICKEN2, val);
2119 * intel_enable_pipe - enable a pipe, asserting requirements
2120 * @crtc: crtc responsible for the pipe
2122 * Enable @crtc's pipe, making sure that various hardware specific requirements
2123 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2125 static void intel_enable_pipe(struct intel_crtc *crtc)
2127 struct drm_device *dev = crtc->base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 enum pipe pipe = crtc->pipe;
2130 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2132 enum pipe pch_transcoder;
2136 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2138 assert_planes_disabled(dev_priv, pipe);
2139 assert_cursor_disabled(dev_priv, pipe);
2140 assert_sprites_disabled(dev_priv, pipe);
2142 if (HAS_PCH_LPT(dev_priv->dev))
2143 pch_transcoder = TRANSCODER_A;
2145 pch_transcoder = pipe;
2148 * A pipe without a PLL won't actually be able to drive bits from
2149 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2152 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2154 assert_dsi_pll_enabled(dev_priv);
2156 assert_pll_enabled(dev_priv, pipe);
2158 if (crtc->config->has_pch_encoder) {
2159 /* if driving the PCH, we need FDI enabled */
2160 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2161 assert_fdi_tx_pll_enabled(dev_priv,
2162 (enum pipe) cpu_transcoder);
2164 /* FIXME: assert CPU port conditions for SNB+ */
2167 reg = PIPECONF(cpu_transcoder);
2168 val = I915_READ(reg);
2169 if (val & PIPECONF_ENABLE) {
2170 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2175 I915_WRITE(reg, val | PIPECONF_ENABLE);
2180 * intel_disable_pipe - disable a pipe, asserting requirements
2181 * @crtc: crtc whose pipes is to be disabled
2183 * Disable the pipe of @crtc, making sure that various hardware
2184 * specific requirements are met, if applicable, e.g. plane
2185 * disabled, panel fitter off, etc.
2187 * Will wait until the pipe has shut down before returning.
2189 static void intel_disable_pipe(struct intel_crtc *crtc)
2191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2192 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2193 enum pipe pipe = crtc->pipe;
2197 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2200 * Make sure planes won't keep trying to pump pixels to us,
2201 * or we might hang the display.
2203 assert_planes_disabled(dev_priv, pipe);
2204 assert_cursor_disabled(dev_priv, pipe);
2205 assert_sprites_disabled(dev_priv, pipe);
2207 reg = PIPECONF(cpu_transcoder);
2208 val = I915_READ(reg);
2209 if ((val & PIPECONF_ENABLE) == 0)
2213 * Double wide has implications for planes
2214 * so best keep it disabled when not needed.
2216 if (crtc->config->double_wide)
2217 val &= ~PIPECONF_DOUBLE_WIDE;
2219 /* Don't disable pipe or pipe PLLs if needed */
2220 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2222 val &= ~PIPECONF_ENABLE;
2224 I915_WRITE(reg, val);
2225 if ((val & PIPECONF_ENABLE) == 0)
2226 intel_wait_for_pipe_off(crtc);
2229 static bool need_vtd_wa(struct drm_device *dev)
2231 #ifdef CONFIG_INTEL_IOMMU
2232 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2240 uint64_t fb_format_modifier, unsigned int plane)
2242 unsigned int tile_height;
2243 uint32_t pixel_bytes;
2245 switch (fb_format_modifier) {
2246 case DRM_FORMAT_MOD_NONE:
2249 case I915_FORMAT_MOD_X_TILED:
2250 tile_height = IS_GEN2(dev) ? 16 : 8;
2252 case I915_FORMAT_MOD_Y_TILED:
2255 case I915_FORMAT_MOD_Yf_TILED:
2256 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2257 switch (pixel_bytes) {
2271 "128-bit pixels are not supported for display!");
2277 MISSING_CASE(fb_format_modifier);
2286 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287 uint32_t pixel_format, uint64_t fb_format_modifier)
2289 return ALIGN(height, intel_tile_height(dev, pixel_format,
2290 fb_format_modifier, 0));
2294 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295 const struct drm_plane_state *plane_state)
2297 struct intel_rotation_info *info = &view->rotation_info;
2298 unsigned int tile_height, tile_pitch;
2300 *view = i915_ggtt_view_normal;
2305 if (!intel_rotation_90_or_270(plane_state->rotation))
2308 *view = i915_ggtt_view_rotated;
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
2313 info->uv_offset = fb->offsets[1];
2314 info->fb_modifier = fb->modifier[0];
2316 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2317 fb->modifier[0], 0);
2318 tile_pitch = PAGE_SIZE / tile_height;
2319 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2323 if (info->pixel_format == DRM_FORMAT_NV12) {
2324 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325 fb->modifier[0], 1);
2326 tile_pitch = PAGE_SIZE / tile_height;
2327 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2330 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2337 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2339 if (INTEL_INFO(dev_priv)->gen >= 9)
2341 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342 IS_VALLEYVIEW(dev_priv))
2344 else if (INTEL_INFO(dev_priv)->gen >= 4)
2351 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352 struct drm_framebuffer *fb,
2353 const struct drm_plane_state *plane_state,
2354 struct intel_engine_cs *pipelined,
2355 struct drm_i915_gem_request **pipelined_request)
2357 struct drm_device *dev = fb->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360 struct i915_ggtt_view view;
2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
2368 alignment = intel_linear_alignment(dev_priv);
2370 case I915_FORMAT_MOD_X_TILED:
2371 if (INTEL_INFO(dev)->gen >= 9)
2372 alignment = 256 * 1024;
2374 /* pin() will align the object as required by fence */
2378 case I915_FORMAT_MOD_Y_TILED:
2379 case I915_FORMAT_MOD_Yf_TILED:
2380 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381 "Y tiling bo slipped through, driver bug!\n"))
2383 alignment = 1 * 1024 * 1024;
2386 MISSING_CASE(fb->modifier[0]);
2390 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2394 /* Note that the w/a also requires 64 PTE of padding following the
2395 * bo. We currently fill all unused PTE with the shadow page and so
2396 * we should always have valid PTE following the scanout preventing
2399 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400 alignment = 256 * 1024;
2403 * Global gtt pte registers are special registers which actually forward
2404 * writes to a chunk of system memory. Which means that there is no risk
2405 * that the register values disappear as soon as we call
2406 * intel_runtime_pm_put(), so it is correct to wrap only the
2407 * pin/unpin/fence and not more.
2409 intel_runtime_pm_get(dev_priv);
2411 dev_priv->mm.interruptible = false;
2412 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2413 pipelined_request, &view);
2415 goto err_interruptible;
2417 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418 * fence, whereas 965+ only requires a fence if using
2419 * framebuffer compression. For simplicity, we always install
2420 * a fence as the cost is not that onerous.
2422 ret = i915_gem_object_get_fence(obj);
2423 if (ret == -EDEADLK) {
2425 * -EDEADLK means there are no free fences
2428 * This is propagated to atomic, but it uses
2429 * -EDEADLK to force a locking recovery, so
2430 * change the returned error to -EBUSY.
2437 i915_gem_object_pin_fence(obj);
2439 dev_priv->mm.interruptible = true;
2440 intel_runtime_pm_put(dev_priv);
2444 i915_gem_object_unpin_from_display_plane(obj, &view);
2446 dev_priv->mm.interruptible = true;
2447 intel_runtime_pm_put(dev_priv);
2451 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452 const struct drm_plane_state *plane_state)
2454 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2455 struct i915_ggtt_view view;
2458 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2460 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461 WARN_ONCE(ret, "Couldn't get view from plane state!");
2463 i915_gem_object_unpin_fence(obj);
2464 i915_gem_object_unpin_from_display_plane(obj, &view);
2467 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468 * is assumed to be a power-of-two. */
2469 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2471 unsigned int tiling_mode,
2475 if (tiling_mode != I915_TILING_NONE) {
2476 unsigned int tile_rows, tiles;
2481 tiles = *x / (512/cpp);
2484 return tile_rows * pitch * 8 + tiles * 4096;
2486 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2487 unsigned int offset;
2489 offset = *y * pitch + *x * cpp;
2490 *y = (offset & alignment) / pitch;
2491 *x = ((offset & alignment) - *y * pitch) / cpp;
2492 return offset & ~alignment;
2496 static int i9xx_format_to_fourcc(int format)
2499 case DISPPLANE_8BPP:
2500 return DRM_FORMAT_C8;
2501 case DISPPLANE_BGRX555:
2502 return DRM_FORMAT_XRGB1555;
2503 case DISPPLANE_BGRX565:
2504 return DRM_FORMAT_RGB565;
2506 case DISPPLANE_BGRX888:
2507 return DRM_FORMAT_XRGB8888;
2508 case DISPPLANE_RGBX888:
2509 return DRM_FORMAT_XBGR8888;
2510 case DISPPLANE_BGRX101010:
2511 return DRM_FORMAT_XRGB2101010;
2512 case DISPPLANE_RGBX101010:
2513 return DRM_FORMAT_XBGR2101010;
2517 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2520 case PLANE_CTL_FORMAT_RGB_565:
2521 return DRM_FORMAT_RGB565;
2523 case PLANE_CTL_FORMAT_XRGB_8888:
2526 return DRM_FORMAT_ABGR8888;
2528 return DRM_FORMAT_XBGR8888;
2531 return DRM_FORMAT_ARGB8888;
2533 return DRM_FORMAT_XRGB8888;
2535 case PLANE_CTL_FORMAT_XRGB_2101010:
2537 return DRM_FORMAT_XBGR2101010;
2539 return DRM_FORMAT_XRGB2101010;
2544 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545 struct intel_initial_plane_config *plane_config)
2547 struct drm_device *dev = crtc->base.dev;
2548 struct drm_i915_gem_object *obj = NULL;
2549 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2550 struct drm_framebuffer *fb = &plane_config->fb->base;
2551 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2552 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2555 size_aligned -= base_aligned;
2557 if (plane_config->size == 0)
2560 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2567 obj->tiling_mode = plane_config->tiling;
2568 if (obj->tiling_mode == I915_TILING_X)
2569 obj->stride = fb->pitches[0];
2571 mode_cmd.pixel_format = fb->pixel_format;
2572 mode_cmd.width = fb->width;
2573 mode_cmd.height = fb->height;
2574 mode_cmd.pitches[0] = fb->pitches[0];
2575 mode_cmd.modifier[0] = fb->modifier[0];
2576 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2578 mutex_lock(&dev->struct_mutex);
2579 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2581 DRM_DEBUG_KMS("intel fb init failed\n");
2584 mutex_unlock(&dev->struct_mutex);
2586 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2590 drm_gem_object_unreference(&obj->base);
2591 mutex_unlock(&dev->struct_mutex);
2595 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2597 update_state_fb(struct drm_plane *plane)
2599 if (plane->fb == plane->state->fb)
2602 if (plane->state->fb)
2603 drm_framebuffer_unreference(plane->state->fb);
2604 plane->state->fb = plane->fb;
2605 if (plane->state->fb)
2606 drm_framebuffer_reference(plane->state->fb);
2610 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2611 struct intel_initial_plane_config *plane_config)
2613 struct drm_device *dev = intel_crtc->base.dev;
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_crtc *i;
2617 struct drm_i915_gem_object *obj;
2618 struct drm_plane *primary = intel_crtc->base.primary;
2619 struct drm_plane_state *plane_state = primary->state;
2620 struct drm_framebuffer *fb;
2622 if (!plane_config->fb)
2625 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2626 fb = &plane_config->fb->base;
2630 kfree(plane_config->fb);
2633 * Failed to alloc the obj, check to see if we should share
2634 * an fb with another CRTC instead
2636 for_each_crtc(dev, c) {
2637 i = to_intel_crtc(c);
2639 if (c == &intel_crtc->base)
2645 fb = c->primary->fb;
2649 obj = intel_fb_obj(fb);
2650 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2651 drm_framebuffer_reference(fb);
2659 plane_state->src_x = plane_state->src_y = 0;
2660 plane_state->src_w = fb->width << 16;
2661 plane_state->src_h = fb->height << 16;
2663 plane_state->crtc_x = plane_state->src_y = 0;
2664 plane_state->crtc_w = fb->width;
2665 plane_state->crtc_h = fb->height;
2667 obj = intel_fb_obj(fb);
2668 if (obj->tiling_mode != I915_TILING_NONE)
2669 dev_priv->preserve_bios_swizzle = true;
2671 drm_framebuffer_reference(fb);
2672 primary->fb = primary->state->fb = fb;
2673 primary->crtc = primary->state->crtc = &intel_crtc->base;
2674 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2675 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2678 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2679 struct drm_framebuffer *fb,
2682 struct drm_device *dev = crtc->dev;
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2685 struct drm_plane *primary = crtc->primary;
2686 bool visible = to_intel_plane_state(primary->state)->visible;
2687 struct drm_i915_gem_object *obj;
2688 int plane = intel_crtc->plane;
2689 unsigned long linear_offset;
2691 u32 reg = DSPCNTR(plane);
2694 if (!visible || !fb) {
2696 if (INTEL_INFO(dev)->gen >= 4)
2697 I915_WRITE(DSPSURF(plane), 0);
2699 I915_WRITE(DSPADDR(plane), 0);
2704 obj = intel_fb_obj(fb);
2705 if (WARN_ON(obj == NULL))
2708 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2710 dspcntr = DISPPLANE_GAMMA_ENABLE;
2712 dspcntr |= DISPLAY_PLANE_ENABLE;
2714 if (INTEL_INFO(dev)->gen < 4) {
2715 if (intel_crtc->pipe == PIPE_B)
2716 dspcntr |= DISPPLANE_SEL_PIPE_B;
2718 /* pipesrc and dspsize control the size that is scaled from,
2719 * which should always be the user's requested size.
2721 I915_WRITE(DSPSIZE(plane),
2722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
2724 I915_WRITE(DSPPOS(plane), 0);
2725 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2726 I915_WRITE(PRIMSIZE(plane),
2727 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2728 (intel_crtc->config->pipe_src_w - 1));
2729 I915_WRITE(PRIMPOS(plane), 0);
2730 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2733 switch (fb->pixel_format) {
2735 dspcntr |= DISPPLANE_8BPP;
2737 case DRM_FORMAT_XRGB1555:
2738 dspcntr |= DISPPLANE_BGRX555;
2740 case DRM_FORMAT_RGB565:
2741 dspcntr |= DISPPLANE_BGRX565;
2743 case DRM_FORMAT_XRGB8888:
2744 dspcntr |= DISPPLANE_BGRX888;
2746 case DRM_FORMAT_XBGR8888:
2747 dspcntr |= DISPPLANE_RGBX888;
2749 case DRM_FORMAT_XRGB2101010:
2750 dspcntr |= DISPPLANE_BGRX101010;
2752 case DRM_FORMAT_XBGR2101010:
2753 dspcntr |= DISPPLANE_RGBX101010;
2759 if (INTEL_INFO(dev)->gen >= 4 &&
2760 obj->tiling_mode != I915_TILING_NONE)
2761 dspcntr |= DISPPLANE_TILED;
2764 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2766 linear_offset = y * fb->pitches[0] + x * pixel_size;
2768 if (INTEL_INFO(dev)->gen >= 4) {
2769 intel_crtc->dspaddr_offset =
2770 intel_gen4_compute_page_offset(dev_priv,
2771 &x, &y, obj->tiling_mode,
2774 linear_offset -= intel_crtc->dspaddr_offset;
2776 intel_crtc->dspaddr_offset = linear_offset;
2779 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2780 dspcntr |= DISPPLANE_ROTATE_180;
2782 x += (intel_crtc->config->pipe_src_w - 1);
2783 y += (intel_crtc->config->pipe_src_h - 1);
2785 /* Finding the last pixel of the last line of the display
2786 data and adding to linear_offset*/
2788 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2792 intel_crtc->adjusted_x = x;
2793 intel_crtc->adjusted_y = y;
2795 I915_WRITE(reg, dspcntr);
2797 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2798 if (INTEL_INFO(dev)->gen >= 4) {
2799 I915_WRITE(DSPSURF(plane),
2800 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2801 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2802 I915_WRITE(DSPLINOFF(plane), linear_offset);
2804 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2808 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 struct drm_plane *primary = crtc->primary;
2816 bool visible = to_intel_plane_state(primary->state)->visible;
2817 struct drm_i915_gem_object *obj;
2818 int plane = intel_crtc->plane;
2819 unsigned long linear_offset;
2821 u32 reg = DSPCNTR(plane);
2824 if (!visible || !fb) {
2826 I915_WRITE(DSPSURF(plane), 0);
2831 obj = intel_fb_obj(fb);
2832 if (WARN_ON(obj == NULL))
2835 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2837 dspcntr = DISPPLANE_GAMMA_ENABLE;
2839 dspcntr |= DISPLAY_PLANE_ENABLE;
2841 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2844 switch (fb->pixel_format) {
2846 dspcntr |= DISPPLANE_8BPP;
2848 case DRM_FORMAT_RGB565:
2849 dspcntr |= DISPPLANE_BGRX565;
2851 case DRM_FORMAT_XRGB8888:
2852 dspcntr |= DISPPLANE_BGRX888;
2854 case DRM_FORMAT_XBGR8888:
2855 dspcntr |= DISPPLANE_RGBX888;
2857 case DRM_FORMAT_XRGB2101010:
2858 dspcntr |= DISPPLANE_BGRX101010;
2860 case DRM_FORMAT_XBGR2101010:
2861 dspcntr |= DISPPLANE_RGBX101010;
2867 if (obj->tiling_mode != I915_TILING_NONE)
2868 dspcntr |= DISPPLANE_TILED;
2870 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2871 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2873 linear_offset = y * fb->pitches[0] + x * pixel_size;
2874 intel_crtc->dspaddr_offset =
2875 intel_gen4_compute_page_offset(dev_priv,
2876 &x, &y, obj->tiling_mode,
2879 linear_offset -= intel_crtc->dspaddr_offset;
2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2881 dspcntr |= DISPPLANE_ROTATE_180;
2883 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2884 x += (intel_crtc->config->pipe_src_w - 1);
2885 y += (intel_crtc->config->pipe_src_h - 1);
2887 /* Finding the last pixel of the last line of the display
2888 data and adding to linear_offset*/
2890 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2891 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2895 intel_crtc->adjusted_x = x;
2896 intel_crtc->adjusted_y = y;
2898 I915_WRITE(reg, dspcntr);
2900 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2901 I915_WRITE(DSPSURF(plane),
2902 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2903 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2904 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2906 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2907 I915_WRITE(DSPLINOFF(plane), linear_offset);
2912 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2913 uint32_t pixel_format)
2915 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2918 * The stride is either expressed as a multiple of 64 bytes
2919 * chunks for linear buffers or in number of tiles for tiled
2922 switch (fb_modifier) {
2923 case DRM_FORMAT_MOD_NONE:
2925 case I915_FORMAT_MOD_X_TILED:
2926 if (INTEL_INFO(dev)->gen == 2)
2929 case I915_FORMAT_MOD_Y_TILED:
2930 /* No need to check for old gens and Y tiling since this is
2931 * about the display engine and those will be blocked before
2935 case I915_FORMAT_MOD_Yf_TILED:
2936 if (bits_per_pixel == 8)
2941 MISSING_CASE(fb_modifier);
2946 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2947 struct drm_i915_gem_object *obj,
2950 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2951 struct i915_vma *vma;
2952 unsigned char *offset;
2954 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2955 view = &i915_ggtt_view_rotated;
2957 vma = i915_gem_obj_to_ggtt_view(obj, view);
2958 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2962 offset = (unsigned char *)vma->node.start;
2965 offset += vma->ggtt_view.rotation_info.uv_start_page *
2969 return (unsigned long)offset;
2972 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2974 struct drm_device *dev = intel_crtc->base.dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2977 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2983 * This function detaches (aka. unbinds) unused scalers in hardware
2985 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2987 struct intel_crtc_scaler_state *scaler_state;
2990 scaler_state = &intel_crtc->config->scaler_state;
2992 /* loop through and disable scalers that aren't in use */
2993 for (i = 0; i < intel_crtc->num_scalers; i++) {
2994 if (!scaler_state->scalers[i].in_use)
2995 skl_detach_scaler(intel_crtc, i);
2999 u32 skl_plane_ctl_format(uint32_t pixel_format)
3001 switch (pixel_format) {
3003 return PLANE_CTL_FORMAT_INDEXED;
3004 case DRM_FORMAT_RGB565:
3005 return PLANE_CTL_FORMAT_RGB_565;
3006 case DRM_FORMAT_XBGR8888:
3007 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3008 case DRM_FORMAT_XRGB8888:
3009 return PLANE_CTL_FORMAT_XRGB_8888;
3011 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012 * to be already pre-multiplied. We need to add a knob (or a different
3013 * DRM_FORMAT) for user-space to configure that.
3015 case DRM_FORMAT_ABGR8888:
3016 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018 case DRM_FORMAT_ARGB8888:
3019 return PLANE_CTL_FORMAT_XRGB_8888 |
3020 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3021 case DRM_FORMAT_XRGB2101010:
3022 return PLANE_CTL_FORMAT_XRGB_2101010;
3023 case DRM_FORMAT_XBGR2101010:
3024 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3025 case DRM_FORMAT_YUYV:
3026 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3027 case DRM_FORMAT_YVYU:
3028 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3029 case DRM_FORMAT_UYVY:
3030 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3031 case DRM_FORMAT_VYUY:
3032 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3034 MISSING_CASE(pixel_format);
3040 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3042 switch (fb_modifier) {
3043 case DRM_FORMAT_MOD_NONE:
3045 case I915_FORMAT_MOD_X_TILED:
3046 return PLANE_CTL_TILED_X;
3047 case I915_FORMAT_MOD_Y_TILED:
3048 return PLANE_CTL_TILED_Y;
3049 case I915_FORMAT_MOD_Yf_TILED:
3050 return PLANE_CTL_TILED_YF;
3052 MISSING_CASE(fb_modifier);
3058 u32 skl_plane_ctl_rotation(unsigned int rotation)
3061 case BIT(DRM_ROTATE_0):
3064 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065 * while i915 HW rotation is clockwise, thats why this swapping.
3067 case BIT(DRM_ROTATE_90):
3068 return PLANE_CTL_ROTATE_270;
3069 case BIT(DRM_ROTATE_180):
3070 return PLANE_CTL_ROTATE_180;
3071 case BIT(DRM_ROTATE_270):
3072 return PLANE_CTL_ROTATE_90;
3074 MISSING_CASE(rotation);
3080 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081 struct drm_framebuffer *fb,
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087 struct drm_plane *plane = crtc->primary;
3088 bool visible = to_intel_plane_state(plane->state)->visible;
3089 struct drm_i915_gem_object *obj;
3090 int pipe = intel_crtc->pipe;
3091 u32 plane_ctl, stride_div, stride;
3092 u32 tile_height, plane_offset, plane_size;
3093 unsigned int rotation;
3094 int x_offset, y_offset;
3095 unsigned long surf_addr;
3096 struct intel_crtc_state *crtc_state = intel_crtc->config;
3097 struct intel_plane_state *plane_state;
3098 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3102 plane_state = to_intel_plane_state(plane->state);
3104 if (!visible || !fb) {
3105 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107 POSTING_READ(PLANE_CTL(pipe, 0));
3111 plane_ctl = PLANE_CTL_ENABLE |
3112 PLANE_CTL_PIPE_GAMMA_ENABLE |
3113 PLANE_CTL_PIPE_CSC_ENABLE;
3115 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3119 rotation = plane->state->rotation;
3120 plane_ctl |= skl_plane_ctl_rotation(rotation);
3122 obj = intel_fb_obj(fb);
3123 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3125 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3128 * FIXME: intel_plane_state->src, dst aren't set when transitional
3129 * update_plane helpers are called from legacy paths.
3130 * Once full atomic crtc is available, below check can be avoided.
3132 if (drm_rect_width(&plane_state->src)) {
3133 scaler_id = plane_state->scaler_id;
3134 src_x = plane_state->src.x1 >> 16;
3135 src_y = plane_state->src.y1 >> 16;
3136 src_w = drm_rect_width(&plane_state->src) >> 16;
3137 src_h = drm_rect_height(&plane_state->src) >> 16;
3138 dst_x = plane_state->dst.x1;
3139 dst_y = plane_state->dst.y1;
3140 dst_w = drm_rect_width(&plane_state->dst);
3141 dst_h = drm_rect_height(&plane_state->dst);
3143 WARN_ON(x != src_x || y != src_y);
3145 src_w = intel_crtc->config->pipe_src_w;
3146 src_h = intel_crtc->config->pipe_src_h;
3149 if (intel_rotation_90_or_270(rotation)) {
3150 /* stride = Surface height in tiles */
3151 tile_height = intel_tile_height(dev, fb->pixel_format,
3152 fb->modifier[0], 0);
3153 stride = DIV_ROUND_UP(fb->height, tile_height);
3154 x_offset = stride * tile_height - y - src_h;
3156 plane_size = (src_w - 1) << 16 | (src_h - 1);
3158 stride = fb->pitches[0] / stride_div;
3161 plane_size = (src_h - 1) << 16 | (src_w - 1);
3163 plane_offset = y_offset << 16 | x_offset;
3165 intel_crtc->adjusted_x = x_offset;
3166 intel_crtc->adjusted_y = y_offset;
3168 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3169 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3170 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3171 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3173 if (scaler_id >= 0) {
3174 uint32_t ps_ctrl = 0;
3176 WARN_ON(!dst_w || !dst_h);
3177 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3178 crtc_state->scaler_state.scalers[scaler_id].mode;
3179 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3180 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3181 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3182 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3183 I915_WRITE(PLANE_POS(pipe, 0), 0);
3185 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3188 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3190 POSTING_READ(PLANE_SURF(pipe, 0));
3193 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3195 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3196 int x, int y, enum mode_set_atomic state)
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3201 if (dev_priv->fbc.disable_fbc)
3202 dev_priv->fbc.disable_fbc(dev_priv);
3204 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3209 static void intel_complete_page_flips(struct drm_device *dev)
3211 struct drm_crtc *crtc;
3213 for_each_crtc(dev, crtc) {
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 enum plane plane = intel_crtc->plane;
3217 intel_prepare_page_flip(dev, plane);
3218 intel_finish_page_flip_plane(dev, plane);
3222 static void intel_update_primary_planes(struct drm_device *dev)
3224 struct drm_crtc *crtc;
3226 for_each_crtc(dev, crtc) {
3227 struct intel_plane *plane = to_intel_plane(crtc->primary);
3228 struct intel_plane_state *plane_state;
3230 drm_modeset_lock_crtc(crtc, &plane->base);
3232 plane_state = to_intel_plane_state(plane->base.state);
3234 if (plane_state->base.fb)
3235 plane->commit_plane(&plane->base, plane_state);
3237 drm_modeset_unlock_crtc(crtc);
3241 void intel_prepare_reset(struct drm_device *dev)
3243 /* no reset support for gen2 */
3247 /* reset doesn't touch the display */
3248 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3251 drm_modeset_lock_all(dev);
3253 * Disabling the crtcs gracefully seems nicer. Also the
3254 * g33 docs say we should at least disable all the planes.
3256 intel_display_suspend(dev);
3259 void intel_finish_reset(struct drm_device *dev)
3261 struct drm_i915_private *dev_priv = to_i915(dev);
3264 * Flips in the rings will be nuked by the reset,
3265 * so complete all pending flips so that user space
3266 * will get its events and not get stuck.
3268 intel_complete_page_flips(dev);
3270 /* no reset support for gen2 */
3274 /* reset doesn't touch the display */
3275 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3277 * Flips in the rings have been nuked by the reset,
3278 * so update the base address of all primary
3279 * planes to the the last fb to make sure we're
3280 * showing the correct fb after a reset.
3282 * FIXME: Atomic will make this obsolete since we won't schedule
3283 * CS-based flips (which might get lost in gpu resets) any more.
3285 intel_update_primary_planes(dev);
3290 * The display has been reset as well,
3291 * so need a full re-initialization.
3293 intel_runtime_pm_disable_interrupts(dev_priv);
3294 intel_runtime_pm_enable_interrupts(dev_priv);
3296 intel_modeset_init_hw(dev);
3298 spin_lock_irq(&dev_priv->irq_lock);
3299 if (dev_priv->display.hpd_irq_setup)
3300 dev_priv->display.hpd_irq_setup(dev);
3301 spin_unlock_irq(&dev_priv->irq_lock);
3303 intel_display_resume(dev);
3305 intel_hpd_init(dev_priv);
3307 drm_modeset_unlock_all(dev);
3311 intel_finish_fb(struct drm_framebuffer *old_fb)
3313 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3314 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3315 bool was_interruptible = dev_priv->mm.interruptible;
3318 /* Big Hammer, we also need to ensure that any pending
3319 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3320 * current scanout is retired before unpinning the old
3321 * framebuffer. Note that we rely on userspace rendering
3322 * into the buffer attached to the pipe they are waiting
3323 * on. If not, userspace generates a GPU hang with IPEHR
3324 * point to the MI_WAIT_FOR_EVENT.
3326 * This should only fail upon a hung GPU, in which case we
3327 * can safely continue.
3329 dev_priv->mm.interruptible = false;
3330 ret = i915_gem_object_wait_rendering(obj, true);
3331 dev_priv->mm.interruptible = was_interruptible;
3336 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3344 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3347 spin_lock_irq(&dev->event_lock);
3348 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3349 spin_unlock_irq(&dev->event_lock);
3354 static void intel_update_pipe_config(struct intel_crtc *crtc,
3355 struct intel_crtc_state *old_crtc_state)
3357 struct drm_device *dev = crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct intel_crtc_state *pipe_config =
3360 to_intel_crtc_state(crtc->base.state);
3362 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3363 crtc->base.mode = crtc->base.state->mode;
3365 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3366 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3367 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3370 intel_set_pipe_csc(&crtc->base);
3373 * Update pipe size and adjust fitter if needed: the reason for this is
3374 * that in compute_mode_changes we check the native mode (not the pfit
3375 * mode) to see if we can flip rather than do a full mode set. In the
3376 * fastboot case, we'll flip, but if we don't update the pipesrc and
3377 * pfit state, we'll end up with a big fb scanned out into the wrong
3381 I915_WRITE(PIPESRC(crtc->pipe),
3382 ((pipe_config->pipe_src_w - 1) << 16) |
3383 (pipe_config->pipe_src_h - 1));
3385 /* on skylake this is done by detaching scalers */
3386 if (INTEL_INFO(dev)->gen >= 9) {
3387 skl_detach_scalers(crtc);
3389 if (pipe_config->pch_pfit.enabled)
3390 skylake_pfit_enable(crtc);
3391 } else if (HAS_PCH_SPLIT(dev)) {
3392 if (pipe_config->pch_pfit.enabled)
3393 ironlake_pfit_enable(crtc);
3394 else if (old_crtc_state->pch_pfit.enabled)
3395 ironlake_pfit_disable(crtc, true);
3399 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3401 struct drm_device *dev = crtc->dev;
3402 struct drm_i915_private *dev_priv = dev->dev_private;
3403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404 int pipe = intel_crtc->pipe;
3407 /* enable normal train */
3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 if (IS_IVYBRIDGE(dev)) {
3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3417 I915_WRITE(reg, temp);
3419 reg = FDI_RX_CTL(pipe);
3420 temp = I915_READ(reg);
3421 if (HAS_PCH_CPT(dev)) {
3422 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3423 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_NONE;
3428 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3430 /* wait one idle pattern time */
3434 /* IVB wants error correction enabled */
3435 if (IS_IVYBRIDGE(dev))
3436 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437 FDI_FE_ERRC_ENABLE);
3440 /* The FDI link training functions for ILK/Ibexpeak. */
3441 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446 int pipe = intel_crtc->pipe;
3447 u32 reg, temp, tries;
3449 /* FDI needs bits from pipe first */
3450 assert_pipe_enabled(dev_priv, pipe);
3452 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3454 reg = FDI_RX_IMR(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~FDI_RX_SYMBOL_LOCK;
3457 temp &= ~FDI_RX_BIT_LOCK;
3458 I915_WRITE(reg, temp);
3462 /* enable CPU FDI TX and PCH FDI RX */
3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_1;
3469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_1;
3475 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3480 /* Ironlake workaround, enable clock pointer after FDI enable*/
3481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3482 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3483 FDI_RX_PHASE_SYNC_POINTER_EN);
3485 reg = FDI_RX_IIR(pipe);
3486 for (tries = 0; tries < 5; tries++) {
3487 temp = I915_READ(reg);
3488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3490 if ((temp & FDI_RX_BIT_LOCK)) {
3491 DRM_DEBUG_KMS("FDI train 1 done.\n");
3492 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3497 DRM_ERROR("FDI train 1 fail!\n");
3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_2;
3504 I915_WRITE(reg, temp);
3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
3508 temp &= ~FDI_LINK_TRAIN_NONE;
3509 temp |= FDI_LINK_TRAIN_PATTERN_2;
3510 I915_WRITE(reg, temp);
3515 reg = FDI_RX_IIR(pipe);
3516 for (tries = 0; tries < 5; tries++) {
3517 temp = I915_READ(reg);
3518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3520 if (temp & FDI_RX_SYMBOL_LOCK) {
3521 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3522 DRM_DEBUG_KMS("FDI train 2 done.\n");
3527 DRM_ERROR("FDI train 2 fail!\n");
3529 DRM_DEBUG_KMS("FDI train done\n");
3533 static const int snb_b_fdi_train_param[] = {
3534 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3535 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3536 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3537 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3540 /* The FDI link training functions for SNB/Cougarpoint. */
3541 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 int pipe = intel_crtc->pipe;
3547 u32 reg, temp, i, retry;
3549 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3551 reg = FDI_RX_IMR(pipe);
3552 temp = I915_READ(reg);
3553 temp &= ~FDI_RX_SYMBOL_LOCK;
3554 temp &= ~FDI_RX_BIT_LOCK;
3555 I915_WRITE(reg, temp);
3560 /* enable CPU FDI TX and PCH FDI RX */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3569 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3572 I915_WRITE(FDI_RX_MISC(pipe),
3573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_1;
3584 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3589 for (i = 0; i < 4; i++) {
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
3594 I915_WRITE(reg, temp);
3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_BIT_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done.\n");
3614 DRM_ERROR("FDI train 1 fail!\n");
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_LINK_TRAIN_NONE;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2;
3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3626 I915_WRITE(reg, temp);
3628 reg = FDI_RX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 if (HAS_PCH_CPT(dev)) {
3631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3632 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3634 temp &= ~FDI_LINK_TRAIN_NONE;
3635 temp |= FDI_LINK_TRAIN_PATTERN_2;
3637 I915_WRITE(reg, temp);
3642 for (i = 0; i < 4; i++) {
3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3646 temp |= snb_b_fdi_train_param[i];
3647 I915_WRITE(reg, temp);
3652 for (retry = 0; retry < 5; retry++) {
3653 reg = FDI_RX_IIR(pipe);
3654 temp = I915_READ(reg);
3655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3656 if (temp & FDI_RX_SYMBOL_LOCK) {
3657 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658 DRM_DEBUG_KMS("FDI train 2 done.\n");
3667 DRM_ERROR("FDI train 2 fail!\n");
3669 DRM_DEBUG_KMS("FDI train done.\n");
3672 /* Manual link training for Ivy Bridge A0 parts */
3673 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3675 struct drm_device *dev = crtc->dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678 int pipe = intel_crtc->pipe;
3679 u32 reg, temp, i, j;
3681 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3683 reg = FDI_RX_IMR(pipe);
3684 temp = I915_READ(reg);
3685 temp &= ~FDI_RX_SYMBOL_LOCK;
3686 temp &= ~FDI_RX_BIT_LOCK;
3687 I915_WRITE(reg, temp);
3692 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3693 I915_READ(FDI_RX_IIR(pipe)));
3695 /* Try each vswing and preemphasis setting twice before moving on */
3696 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3697 /* disable first in case we need to retry */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3701 temp &= ~FDI_TX_ENABLE;
3702 I915_WRITE(reg, temp);
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_AUTO;
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp &= ~FDI_RX_ENABLE;
3709 I915_WRITE(reg, temp);
3711 /* enable CPU FDI TX and PCH FDI RX */
3712 reg = FDI_TX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3715 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3716 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3717 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3718 temp |= snb_b_fdi_train_param[j/2];
3719 temp |= FDI_COMPOSITE_SYNC;
3720 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3722 I915_WRITE(FDI_RX_MISC(pipe),
3723 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728 temp |= FDI_COMPOSITE_SYNC;
3729 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3732 udelay(1); /* should be 0.5us */
3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3739 if (temp & FDI_RX_BIT_LOCK ||
3740 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3742 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3746 udelay(1); /* should be 0.5us */
3749 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3754 reg = FDI_TX_CTL(pipe);
3755 temp = I915_READ(reg);
3756 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3757 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3758 I915_WRITE(reg, temp);
3760 reg = FDI_RX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3763 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3764 I915_WRITE(reg, temp);
3767 udelay(2); /* should be 1.5us */
3769 for (i = 0; i < 4; i++) {
3770 reg = FDI_RX_IIR(pipe);
3771 temp = I915_READ(reg);
3772 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3774 if (temp & FDI_RX_SYMBOL_LOCK ||
3775 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3776 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3777 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3781 udelay(2); /* should be 1.5us */
3784 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3788 DRM_DEBUG_KMS("FDI train done.\n");
3791 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3793 struct drm_device *dev = intel_crtc->base.dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 int pipe = intel_crtc->pipe;
3799 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3803 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3804 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3805 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3810 /* Switch from Rawclk to PCDclk */
3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp | FDI_PCDCLK);
3817 /* Enable CPU FDI TX PLL, always on for Ironlake */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3821 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3828 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3830 struct drm_device *dev = intel_crtc->base.dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 int pipe = intel_crtc->pipe;
3835 /* Switch from PCDclk to Rawclk */
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3840 /* Disable CPU FDI TX PLL */
3841 reg = FDI_TX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3852 /* Wait for the clocks to turn off. */
3857 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 int pipe = intel_crtc->pipe;
3865 /* disable CPU FDI tx and PCH FDI rx */
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3871 reg = FDI_RX_CTL(pipe);
3872 temp = I915_READ(reg);
3873 temp &= ~(0x7 << 16);
3874 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3875 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3880 /* Ironlake workaround, disable clock pointer after downing FDI */
3881 if (HAS_PCH_IBX(dev))
3882 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3884 /* still set train pattern 1 */
3885 reg = FDI_TX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 temp &= ~FDI_LINK_TRAIN_NONE;
3888 temp |= FDI_LINK_TRAIN_PATTERN_1;
3889 I915_WRITE(reg, temp);
3891 reg = FDI_RX_CTL(pipe);
3892 temp = I915_READ(reg);
3893 if (HAS_PCH_CPT(dev)) {
3894 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3895 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3897 temp &= ~FDI_LINK_TRAIN_NONE;
3898 temp |= FDI_LINK_TRAIN_PATTERN_1;
3900 /* BPC in FDI rx is consistent with that in PIPECONF */
3901 temp &= ~(0x07 << 16);
3902 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3903 I915_WRITE(reg, temp);
3909 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3911 struct intel_crtc *crtc;
3913 /* Note that we don't need to be called with mode_config.lock here
3914 * as our list of CRTC objects is static for the lifetime of the
3915 * device and so cannot disappear as we iterate. Similarly, we can
3916 * happily treat the predicates as racy, atomic checks as userspace
3917 * cannot claim and pin a new fb without at least acquring the
3918 * struct_mutex and so serialising with us.
3920 for_each_intel_crtc(dev, crtc) {
3921 if (atomic_read(&crtc->unpin_work_count) == 0)
3924 if (crtc->unpin_work)
3925 intel_wait_for_vblank(dev, crtc->pipe);
3933 static void page_flip_completed(struct intel_crtc *intel_crtc)
3935 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3936 struct intel_unpin_work *work = intel_crtc->unpin_work;
3938 /* ensure that the unpin work is consistent wrt ->pending. */
3940 intel_crtc->unpin_work = NULL;
3943 drm_send_vblank_event(intel_crtc->base.dev,
3947 drm_crtc_vblank_put(&intel_crtc->base);
3949 wake_up_all(&dev_priv->pending_flip_queue);
3950 queue_work(dev_priv->wq, &work->work);
3952 trace_i915_flip_complete(intel_crtc->plane,
3953 work->pending_flip_obj);
3956 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3958 struct drm_device *dev = crtc->dev;
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3961 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3962 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3963 !intel_crtc_has_pending_flip(crtc),
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3967 spin_lock_irq(&dev->event_lock);
3968 if (intel_crtc->unpin_work) {
3969 WARN_ONCE(1, "Removing stuck page flip\n");
3970 page_flip_completed(intel_crtc);
3972 spin_unlock_irq(&dev->event_lock);
3975 if (crtc->primary->fb) {
3976 mutex_lock(&dev->struct_mutex);
3977 intel_finish_fb(crtc->primary->fb);
3978 mutex_unlock(&dev->struct_mutex);
3982 /* Program iCLKIP clock to the desired frequency */
3983 static void lpt_program_iclkip(struct drm_crtc *crtc)
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3991 mutex_lock(&dev_priv->sb_lock);
3993 /* It is necessary to ungate the pixclk gate prior to programming
3994 * the divisors, and gate it back when it is done.
3996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3998 /* Disable SSCCTL */
3999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
4000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4005 if (clock == 20000) {
4010 /* The iCLK virtual clock root frequency is in MHz,
4011 * but the adjusted_mode->crtc_clock in in KHz. To get the
4012 * divisors, it is necessary to divide one by another, so we
4013 * convert the virtual clock precision to KHz here for higher
4016 u32 iclk_virtual_root_freq = 172800 * 1000;
4017 u32 iclk_pi_range = 64;
4018 u32 desired_divisor, msb_divisor_value, pi_value;
4020 desired_divisor = (iclk_virtual_root_freq / clock);
4021 msb_divisor_value = desired_divisor / iclk_pi_range;
4022 pi_value = desired_divisor % iclk_pi_range;
4025 divsel = msb_divisor_value - 2;
4026 phaseinc = pi_value;
4029 /* This should not happen with any sane values */
4030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4042 /* Program SSCDIVINTPHASE6 */
4043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4052 /* Program SSCAUXDIV */
4053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4058 /* Enable modulator and associated divider */
4059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4060 temp &= ~SBI_SSCCTL_DISABLE;
4061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4063 /* Wait for initialization time */
4066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4068 mutex_unlock(&dev_priv->sb_lock);
4071 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072 enum pipe pch_transcoder)
4074 struct drm_device *dev = crtc->base.dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4078 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079 I915_READ(HTOTAL(cpu_transcoder)));
4080 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081 I915_READ(HBLANK(cpu_transcoder)));
4082 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083 I915_READ(HSYNC(cpu_transcoder)));
4085 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086 I915_READ(VTOTAL(cpu_transcoder)));
4087 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088 I915_READ(VBLANK(cpu_transcoder)));
4089 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090 I915_READ(VSYNC(cpu_transcoder)));
4091 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4095 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4100 temp = I915_READ(SOUTH_CHICKEN1);
4101 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4104 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4107 temp &= ~FDI_BC_BIFURCATION_SELECT;
4109 temp |= FDI_BC_BIFURCATION_SELECT;
4111 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4112 I915_WRITE(SOUTH_CHICKEN1, temp);
4113 POSTING_READ(SOUTH_CHICKEN1);
4116 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4118 struct drm_device *dev = intel_crtc->base.dev;
4120 switch (intel_crtc->pipe) {
4124 if (intel_crtc->config->fdi_lanes > 2)
4125 cpt_set_fdi_bc_bifurcation(dev, false);
4127 cpt_set_fdi_bc_bifurcation(dev, true);
4131 cpt_set_fdi_bc_bifurcation(dev, true);
4140 * Enable PCH resources required for PCH ports:
4142 * - FDI training & RX/TX
4143 * - update transcoder timings
4144 * - DP transcoding bits
4147 static void ironlake_pch_enable(struct drm_crtc *crtc)
4149 struct drm_device *dev = crtc->dev;
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152 int pipe = intel_crtc->pipe;
4155 assert_pch_transcoder_disabled(dev_priv, pipe);
4157 if (IS_IVYBRIDGE(dev))
4158 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4160 /* Write the TU size bits before fdi link training, so that error
4161 * detection works. */
4162 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4165 /* For PCH output, training FDI link */
4166 dev_priv->display.fdi_link_train(crtc);
4168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
4170 if (HAS_PCH_CPT(dev)) {
4173 temp = I915_READ(PCH_DPLL_SEL);
4174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
4176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4180 I915_WRITE(PCH_DPLL_SEL, temp);
4183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
4190 intel_enable_shared_dpll(intel_crtc);
4192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
4194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4196 intel_fdi_normal_train(crtc);
4198 /* For PCH DP, enable TRANS_DP_CTL */
4199 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4200 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4201 reg = TRANS_DP_CTL(pipe);
4202 temp = I915_READ(reg);
4203 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4204 TRANS_DP_SYNC_MASK |
4206 temp |= TRANS_DP_OUTPUT_ENABLE;
4207 temp |= bpc << 9; /* same format but at 11:9 */
4209 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4210 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4211 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4212 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4214 switch (intel_trans_dp_port_sel(crtc)) {
4216 temp |= TRANS_DP_PORT_SEL_B;
4219 temp |= TRANS_DP_PORT_SEL_C;
4222 temp |= TRANS_DP_PORT_SEL_D;
4228 I915_WRITE(reg, temp);
4231 ironlake_enable_pch_transcoder(dev_priv, pipe);
4234 static void lpt_pch_enable(struct drm_crtc *crtc)
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4241 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4243 lpt_program_iclkip(crtc);
4245 /* Set transcoder timing. */
4246 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4248 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4251 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252 struct intel_crtc_state *crtc_state)
4254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4255 struct intel_shared_dpll *pll;
4256 struct intel_shared_dpll_config *shared_dpll;
4257 enum intel_dpll_id i;
4259 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4261 if (HAS_PCH_IBX(dev_priv->dev)) {
4262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4263 i = (enum intel_dpll_id) crtc->pipe;
4264 pll = &dev_priv->shared_dplls[i];
4266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267 crtc->base.base.id, pll->name);
4269 WARN_ON(shared_dpll[i].crtc_mask);
4274 if (IS_BROXTON(dev_priv->dev)) {
4275 /* PLL is attached to port in bxt */
4276 struct intel_encoder *encoder;
4277 struct intel_digital_port *intel_dig_port;
4279 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280 if (WARN_ON(!encoder))
4283 intel_dig_port = enc_to_dig_port(&encoder->base);
4284 /* 1:1 mapping between ports and PLLs */
4285 i = (enum intel_dpll_id)intel_dig_port->port;
4286 pll = &dev_priv->shared_dplls[i];
4287 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288 crtc->base.base.id, pll->name);
4289 WARN_ON(shared_dpll[i].crtc_mask);
4294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295 pll = &dev_priv->shared_dplls[i];
4297 /* Only want to check enabled timings first */
4298 if (shared_dpll[i].crtc_mask == 0)
4301 if (memcmp(&crtc_state->dpll_hw_state,
4302 &shared_dpll[i].hw_state,
4303 sizeof(crtc_state->dpll_hw_state)) == 0) {
4304 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4305 crtc->base.base.id, pll->name,
4306 shared_dpll[i].crtc_mask,
4312 /* Ok no matching timings, maybe there's a free one? */
4313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314 pll = &dev_priv->shared_dplls[i];
4315 if (shared_dpll[i].crtc_mask == 0) {
4316 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317 crtc->base.base.id, pll->name);
4325 if (shared_dpll[i].crtc_mask == 0)
4326 shared_dpll[i].hw_state =
4327 crtc_state->dpll_hw_state;
4329 crtc_state->shared_dpll = i;
4330 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331 pipe_name(crtc->pipe));
4333 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4338 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4340 struct drm_i915_private *dev_priv = to_i915(state->dev);
4341 struct intel_shared_dpll_config *shared_dpll;
4342 struct intel_shared_dpll *pll;
4343 enum intel_dpll_id i;
4345 if (!to_intel_atomic_state(state)->dpll_set)
4348 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
4351 pll->config = shared_dpll[i];
4355 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 int dslreg = PIPEDSL(pipe);
4361 temp = I915_READ(dslreg);
4363 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4364 if (wait_for(I915_READ(dslreg) != temp, 5))
4365 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4370 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4371 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4372 int src_w, int src_h, int dst_w, int dst_h)
4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc_state->scaler_state;
4376 struct intel_crtc *intel_crtc =
4377 to_intel_crtc(crtc_state->base.crtc);
4380 need_scaling = intel_rotation_90_or_270(rotation) ?
4381 (src_h != dst_w || src_w != dst_h):
4382 (src_w != dst_w || src_h != dst_h);
4385 * if plane is being disabled or scaler is no more required or force detach
4386 * - free scaler binded to this plane/crtc
4387 * - in order to do this, update crtc->scaler_usage
4389 * Here scaler state in crtc_state is set free so that
4390 * scaler can be assigned to other user. Actual register
4391 * update to free the scaler is done in plane/panel-fit programming.
4392 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4394 if (force_detach || !need_scaling) {
4395 if (*scaler_id >= 0) {
4396 scaler_state->scaler_users &= ~(1 << scaler_user);
4397 scaler_state->scalers[*scaler_id].in_use = 0;
4399 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4400 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4401 intel_crtc->pipe, scaler_user, *scaler_id,
4402 scaler_state->scaler_users);
4409 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4410 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4412 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4413 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4414 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4415 "size is out of scaler range\n",
4416 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4420 /* mark this plane as a scaler user in crtc_state */
4421 scaler_state->scaler_users |= (1 << scaler_user);
4422 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4424 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4425 scaler_state->scaler_users);
4431 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4433 * @state: crtc's scaler state
4436 * 0 - scaler_usage updated successfully
4437 * error - requested scaling cannot be supported or other error condition
4439 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4441 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4442 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4444 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4445 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4447 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4448 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4449 state->pipe_src_w, state->pipe_src_h,
4450 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4454 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4456 * @state: crtc's scaler state
4457 * @plane_state: atomic plane state to update
4460 * 0 - scaler_usage updated successfully
4461 * error - requested scaling cannot be supported or other error condition
4463 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4464 struct intel_plane_state *plane_state)
4467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4468 struct intel_plane *intel_plane =
4469 to_intel_plane(plane_state->base.plane);
4470 struct drm_framebuffer *fb = plane_state->base.fb;
4473 bool force_detach = !fb || !plane_state->visible;
4475 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4476 intel_plane->base.base.id, intel_crtc->pipe,
4477 drm_plane_index(&intel_plane->base));
4479 ret = skl_update_scaler(crtc_state, force_detach,
4480 drm_plane_index(&intel_plane->base),
4481 &plane_state->scaler_id,
4482 plane_state->base.rotation,
4483 drm_rect_width(&plane_state->src) >> 16,
4484 drm_rect_height(&plane_state->src) >> 16,
4485 drm_rect_width(&plane_state->dst),
4486 drm_rect_height(&plane_state->dst));
4488 if (ret || plane_state->scaler_id < 0)
4491 /* check colorkey */
4492 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4493 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4494 intel_plane->base.base.id);
4498 /* Check src format */
4499 switch (fb->pixel_format) {
4500 case DRM_FORMAT_RGB565:
4501 case DRM_FORMAT_XBGR8888:
4502 case DRM_FORMAT_XRGB8888:
4503 case DRM_FORMAT_ABGR8888:
4504 case DRM_FORMAT_ARGB8888:
4505 case DRM_FORMAT_XRGB2101010:
4506 case DRM_FORMAT_XBGR2101010:
4507 case DRM_FORMAT_YUYV:
4508 case DRM_FORMAT_YVYU:
4509 case DRM_FORMAT_UYVY:
4510 case DRM_FORMAT_VYUY:
4513 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4514 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4521 static void skylake_scaler_disable(struct intel_crtc *crtc)
4525 for (i = 0; i < crtc->num_scalers; i++)
4526 skl_detach_scaler(crtc, i);
4529 static void skylake_pfit_enable(struct intel_crtc *crtc)
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 int pipe = crtc->pipe;
4534 struct intel_crtc_scaler_state *scaler_state =
4535 &crtc->config->scaler_state;
4537 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539 if (crtc->config->pch_pfit.enabled) {
4542 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4543 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4547 id = scaler_state->scaler_id;
4548 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4549 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4550 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4551 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4553 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4557 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4559 struct drm_device *dev = crtc->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 int pipe = crtc->pipe;
4563 if (crtc->config->pch_pfit.enabled) {
4564 /* Force use of hard-coded filter coefficients
4565 * as some pre-programmed values are broken,
4568 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4569 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4570 PF_PIPE_SEL_IVB(pipe));
4572 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4573 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4574 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4578 void hsw_enable_ips(struct intel_crtc *crtc)
4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4583 if (!crtc->config->ips_enabled)
4586 /* We can only enable IPS after we enable a plane and wait for a vblank */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4589 assert_plane_enabled(dev_priv, crtc->plane);
4590 if (IS_BROADWELL(dev)) {
4591 mutex_lock(&dev_priv->rps.hw_lock);
4592 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4593 mutex_unlock(&dev_priv->rps.hw_lock);
4594 /* Quoting Art Runyan: "its not safe to expect any particular
4595 * value in IPS_CTL bit 31 after enabling IPS through the
4596 * mailbox." Moreover, the mailbox may return a bogus state,
4597 * so we need to just enable it and continue on.
4600 I915_WRITE(IPS_CTL, IPS_ENABLE);
4601 /* The bit only becomes 1 in the next vblank, so this wait here
4602 * is essentially intel_wait_for_vblank. If we don't have this
4603 * and don't wait for vblanks until the end of crtc_enable, then
4604 * the HW state readout code will complain that the expected
4605 * IPS_CTL value is not the one we read. */
4606 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4607 DRM_ERROR("Timed out waiting for IPS enable\n");
4611 void hsw_disable_ips(struct intel_crtc *crtc)
4613 struct drm_device *dev = crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4616 if (!crtc->config->ips_enabled)
4619 assert_plane_enabled(dev_priv, crtc->plane);
4620 if (IS_BROADWELL(dev)) {
4621 mutex_lock(&dev_priv->rps.hw_lock);
4622 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4623 mutex_unlock(&dev_priv->rps.hw_lock);
4624 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4625 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4626 DRM_ERROR("Timed out waiting for IPS disable\n");
4628 I915_WRITE(IPS_CTL, 0);
4629 POSTING_READ(IPS_CTL);
4632 /* We need to wait for a vblank before we can disable the plane. */
4633 intel_wait_for_vblank(dev, crtc->pipe);
4636 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4637 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4639 struct drm_device *dev = crtc->dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642 enum pipe pipe = intel_crtc->pipe;
4644 bool reenable_ips = false;
4646 /* The clocks have to be on to load the palette. */
4647 if (!crtc->state->active)
4650 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4651 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4652 assert_dsi_pll_enabled(dev_priv);
4654 assert_pll_enabled(dev_priv, pipe);
4657 /* Workaround : Do not read or write the pipe palette/gamma data while
4658 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4660 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4661 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4662 GAMMA_MODE_MODE_SPLIT)) {
4663 hsw_disable_ips(intel_crtc);
4664 reenable_ips = true;
4667 for (i = 0; i < 256; i++) {
4670 if (HAS_GMCH_DISPLAY(dev))
4671 palreg = PALETTE(pipe, i);
4673 palreg = LGC_PALETTE(pipe, i);
4676 (intel_crtc->lut_r[i] << 16) |
4677 (intel_crtc->lut_g[i] << 8) |
4678 intel_crtc->lut_b[i]);
4682 hsw_enable_ips(intel_crtc);
4685 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4687 if (intel_crtc->overlay) {
4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4691 mutex_lock(&dev->struct_mutex);
4692 dev_priv->mm.interruptible = false;
4693 (void) intel_overlay_switch_off(intel_crtc->overlay);
4694 dev_priv->mm.interruptible = true;
4695 mutex_unlock(&dev->struct_mutex);
4698 /* Let userspace switch the overlay on again. In most cases userspace
4699 * has to recompute where to put it anyway.
4704 * intel_post_enable_primary - Perform operations after enabling primary plane
4705 * @crtc: the CRTC whose primary plane was just enabled
4707 * Performs potentially sleeping operations that must be done after the primary
4708 * plane is enabled, such as updating FBC and IPS. Note that this may be
4709 * called due to an explicit primary plane update, or due to an implicit
4710 * re-enable that is caused when a sprite plane is updated to no longer
4711 * completely hide the primary plane.
4714 intel_post_enable_primary(struct drm_crtc *crtc)
4716 struct drm_device *dev = crtc->dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 int pipe = intel_crtc->pipe;
4722 * BDW signals flip done immediately if the plane
4723 * is disabled, even if the plane enable is already
4724 * armed to occur at the next vblank :(
4726 if (IS_BROADWELL(dev))
4727 intel_wait_for_vblank(dev, pipe);
4730 * FIXME IPS should be fine as long as one plane is
4731 * enabled, but in practice it seems to have problems
4732 * when going from primary only to sprite only and vice
4735 hsw_enable_ips(intel_crtc);
4738 * Gen2 reports pipe underruns whenever all planes are disabled.
4739 * So don't enable underrun reporting before at least some planes
4741 * FIXME: Need to fix the logic to work when we turn off all planes
4742 * but leave the pipe running.
4745 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4747 /* Underruns don't raise interrupts, so check manually. */
4748 if (HAS_GMCH_DISPLAY(dev))
4749 i9xx_check_fifo_underruns(dev_priv);
4753 * intel_pre_disable_primary - Perform operations before disabling primary plane
4754 * @crtc: the CRTC whose primary plane is to be disabled
4756 * Performs potentially sleeping operations that must be done before the
4757 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4758 * be called due to an explicit primary plane update, or due to an implicit
4759 * disable that is caused when a sprite plane completely hides the primary
4763 intel_pre_disable_primary(struct drm_crtc *crtc)
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
4771 * Gen2 reports pipe underruns whenever all planes are disabled.
4772 * So diasble underrun reporting before all the planes get disabled.
4773 * FIXME: Need to fix the logic to work when we turn off all planes
4774 * but leave the pipe running.
4777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4780 * Vblank time updates from the shadow to live plane control register
4781 * are blocked if the memory self-refresh mode is active at that
4782 * moment. So to make sure the plane gets truly disabled, disable
4783 * first the self-refresh mode. The self-refresh enable bit in turn
4784 * will be checked/applied by the HW only at the next frame start
4785 * event which is after the vblank start event, so we need to have a
4786 * wait-for-vblank between disabling the plane and the pipe.
4788 if (HAS_GMCH_DISPLAY(dev)) {
4789 intel_set_memory_cxsr(dev_priv, false);
4790 dev_priv->wm.vlv.cxsr = false;
4791 intel_wait_for_vblank(dev, pipe);
4795 * FIXME IPS should be fine as long as one plane is
4796 * enabled, but in practice it seems to have problems
4797 * when going from primary only to sprite only and vice
4800 hsw_disable_ips(intel_crtc);
4803 static void intel_post_plane_update(struct intel_crtc *crtc)
4805 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4806 struct drm_device *dev = crtc->base.dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct drm_plane *plane;
4810 if (atomic->wait_vblank)
4811 intel_wait_for_vblank(dev, crtc->pipe);
4813 intel_frontbuffer_flip(dev, atomic->fb_bits);
4815 if (atomic->disable_cxsr)
4816 crtc->wm.cxsr_allowed = true;
4818 if (crtc->atomic.update_wm_post)
4819 intel_update_watermarks(&crtc->base);
4821 if (atomic->update_fbc)
4822 intel_fbc_update(dev_priv);
4824 if (atomic->post_enable_primary)
4825 intel_post_enable_primary(&crtc->base);
4827 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4828 intel_update_sprite_watermarks(plane, &crtc->base,
4829 0, 0, 0, false, false);
4831 memset(atomic, 0, sizeof(*atomic));
4834 static void intel_pre_plane_update(struct intel_crtc *crtc)
4836 struct drm_device *dev = crtc->base.dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4839 struct drm_plane *p;
4841 /* Track fb's for any planes being disabled */
4842 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4843 struct intel_plane *plane = to_intel_plane(p);
4845 mutex_lock(&dev->struct_mutex);
4846 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4847 plane->frontbuffer_bit);
4848 mutex_unlock(&dev->struct_mutex);
4851 if (atomic->wait_for_flips)
4852 intel_crtc_wait_for_pending_flips(&crtc->base);
4854 if (atomic->disable_fbc)
4855 intel_fbc_disable_crtc(crtc);
4857 if (crtc->atomic.disable_ips)
4858 hsw_disable_ips(crtc);
4860 if (atomic->pre_disable_primary)
4861 intel_pre_disable_primary(&crtc->base);
4863 if (atomic->disable_cxsr) {
4864 crtc->wm.cxsr_allowed = false;
4865 intel_set_memory_cxsr(dev_priv, false);
4869 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4871 struct drm_device *dev = crtc->dev;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873 struct drm_plane *p;
4874 int pipe = intel_crtc->pipe;
4876 intel_crtc_dpms_overlay_disable(intel_crtc);
4878 drm_for_each_plane_mask(p, dev, plane_mask)
4879 to_intel_plane(p)->disable_plane(p, crtc);
4882 * FIXME: Once we grow proper nuclear flip support out of this we need
4883 * to compute the mask of flip planes precisely. For the time being
4884 * consider this a flip to a NULL plane.
4886 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4889 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4891 struct drm_device *dev = crtc->dev;
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894 struct intel_encoder *encoder;
4895 int pipe = intel_crtc->pipe;
4897 if (WARN_ON(intel_crtc->active))
4900 if (intel_crtc->config->has_pch_encoder)
4901 intel_prepare_shared_dpll(intel_crtc);
4903 if (intel_crtc->config->has_dp_encoder)
4904 intel_dp_set_m_n(intel_crtc, M1_N1);
4906 intel_set_pipe_timings(intel_crtc);
4908 if (intel_crtc->config->has_pch_encoder) {
4909 intel_cpu_transcoder_set_m_n(intel_crtc,
4910 &intel_crtc->config->fdi_m_n, NULL);
4913 ironlake_set_pipeconf(crtc);
4915 intel_crtc->active = true;
4917 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 if (encoder->pre_enable)
4922 encoder->pre_enable(encoder);
4924 if (intel_crtc->config->has_pch_encoder) {
4925 /* Note: FDI PLL enabling _must_ be done before we enable the
4926 * cpu pipes, hence this is separate from all the other fdi/pch
4928 ironlake_fdi_pll_enable(intel_crtc);
4930 assert_fdi_tx_disabled(dev_priv, pipe);
4931 assert_fdi_rx_disabled(dev_priv, pipe);
4934 ironlake_pfit_enable(intel_crtc);
4937 * On ILK+ LUT must be loaded before the pipe is running but with
4940 intel_crtc_load_lut(crtc);
4942 intel_update_watermarks(crtc);
4943 intel_enable_pipe(intel_crtc);
4945 if (intel_crtc->config->has_pch_encoder)
4946 ironlake_pch_enable(crtc);
4948 assert_vblank_disabled(crtc);
4949 drm_crtc_vblank_on(crtc);
4951 for_each_encoder_on_crtc(dev, crtc, encoder)
4952 encoder->enable(encoder);
4954 if (HAS_PCH_CPT(dev))
4955 cpt_verify_modeset(dev, intel_crtc->pipe);
4958 /* IPS only exists on ULT machines and is tied to pipe A. */
4959 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4961 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4964 static void haswell_crtc_enable(struct drm_crtc *crtc)
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 struct intel_encoder *encoder;
4970 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4971 struct intel_crtc_state *pipe_config =
4972 to_intel_crtc_state(crtc->state);
4974 if (WARN_ON(intel_crtc->active))
4977 if (intel_crtc_to_shared_dpll(intel_crtc))
4978 intel_enable_shared_dpll(intel_crtc);
4980 if (intel_crtc->config->has_dp_encoder)
4981 intel_dp_set_m_n(intel_crtc, M1_N1);
4983 intel_set_pipe_timings(intel_crtc);
4985 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4986 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4987 intel_crtc->config->pixel_multiplier - 1);
4990 if (intel_crtc->config->has_pch_encoder) {
4991 intel_cpu_transcoder_set_m_n(intel_crtc,
4992 &intel_crtc->config->fdi_m_n, NULL);
4995 haswell_set_pipeconf(crtc);
4997 intel_set_pipe_csc(crtc);
4999 intel_crtc->active = true;
5001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5002 for_each_encoder_on_crtc(dev, crtc, encoder)
5003 if (encoder->pre_enable)
5004 encoder->pre_enable(encoder);
5006 if (intel_crtc->config->has_pch_encoder) {
5007 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5009 dev_priv->display.fdi_link_train(crtc);
5012 intel_ddi_enable_pipe_clock(intel_crtc);
5014 if (INTEL_INFO(dev)->gen >= 9)
5015 skylake_pfit_enable(intel_crtc);
5017 ironlake_pfit_enable(intel_crtc);
5020 * On ILK+ LUT must be loaded before the pipe is running but with
5023 intel_crtc_load_lut(crtc);
5025 intel_ddi_set_pipe_settings(crtc);
5026 intel_ddi_enable_transcoder_func(crtc);
5028 intel_update_watermarks(crtc);
5029 intel_enable_pipe(intel_crtc);
5031 if (intel_crtc->config->has_pch_encoder)
5032 lpt_pch_enable(crtc);
5034 if (intel_crtc->config->dp_encoder_is_mst)
5035 intel_ddi_set_vc_payload_alloc(crtc, true);
5037 assert_vblank_disabled(crtc);
5038 drm_crtc_vblank_on(crtc);
5040 for_each_encoder_on_crtc(dev, crtc, encoder) {
5041 encoder->enable(encoder);
5042 intel_opregion_notify_encoder(encoder, true);
5045 /* If we change the relative order between pipe/planes enabling, we need
5046 * to change the workaround. */
5047 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5048 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5049 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5050 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5054 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5056 struct drm_device *dev = crtc->base.dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 int pipe = crtc->pipe;
5060 /* To avoid upsetting the power well on haswell only disable the pfit if
5061 * it's in use. The hw state code will make sure we get this right. */
5062 if (force || crtc->config->pch_pfit.enabled) {
5063 I915_WRITE(PF_CTL(pipe), 0);
5064 I915_WRITE(PF_WIN_POS(pipe), 0);
5065 I915_WRITE(PF_WIN_SZ(pipe), 0);
5069 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5071 struct drm_device *dev = crtc->dev;
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074 struct intel_encoder *encoder;
5075 int pipe = intel_crtc->pipe;
5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 encoder->disable(encoder);
5081 drm_crtc_vblank_off(crtc);
5082 assert_vblank_disabled(crtc);
5084 if (intel_crtc->config->has_pch_encoder)
5085 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5087 intel_disable_pipe(intel_crtc);
5089 ironlake_pfit_disable(intel_crtc, false);
5091 if (intel_crtc->config->has_pch_encoder)
5092 ironlake_fdi_disable(crtc);
5094 for_each_encoder_on_crtc(dev, crtc, encoder)
5095 if (encoder->post_disable)
5096 encoder->post_disable(encoder);
5098 if (intel_crtc->config->has_pch_encoder) {
5099 ironlake_disable_pch_transcoder(dev_priv, pipe);
5101 if (HAS_PCH_CPT(dev)) {
5102 /* disable TRANS_DP_CTL */
5103 reg = TRANS_DP_CTL(pipe);
5104 temp = I915_READ(reg);
5105 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5106 TRANS_DP_PORT_SEL_MASK);
5107 temp |= TRANS_DP_PORT_SEL_NONE;
5108 I915_WRITE(reg, temp);
5110 /* disable DPLL_SEL */
5111 temp = I915_READ(PCH_DPLL_SEL);
5112 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5113 I915_WRITE(PCH_DPLL_SEL, temp);
5116 ironlake_fdi_pll_disable(intel_crtc);
5119 intel_crtc->active = false;
5120 intel_update_watermarks(crtc);
5123 static void haswell_crtc_disable(struct drm_crtc *crtc)
5125 struct drm_device *dev = crtc->dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128 struct intel_encoder *encoder;
5129 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5131 for_each_encoder_on_crtc(dev, crtc, encoder) {
5132 intel_opregion_notify_encoder(encoder, false);
5133 encoder->disable(encoder);
5136 drm_crtc_vblank_off(crtc);
5137 assert_vblank_disabled(crtc);
5139 if (intel_crtc->config->has_pch_encoder)
5140 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5142 intel_disable_pipe(intel_crtc);
5144 if (intel_crtc->config->dp_encoder_is_mst)
5145 intel_ddi_set_vc_payload_alloc(crtc, false);
5147 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5149 if (INTEL_INFO(dev)->gen >= 9)
5150 skylake_scaler_disable(intel_crtc);
5152 ironlake_pfit_disable(intel_crtc, false);
5154 intel_ddi_disable_pipe_clock(intel_crtc);
5156 if (intel_crtc->config->has_pch_encoder) {
5157 lpt_disable_pch_transcoder(dev_priv);
5158 intel_ddi_fdi_disable(crtc);
5161 for_each_encoder_on_crtc(dev, crtc, encoder)
5162 if (encoder->post_disable)
5163 encoder->post_disable(encoder);
5165 intel_crtc->active = false;
5166 intel_update_watermarks(crtc);
5169 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5171 struct drm_device *dev = crtc->base.dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 struct intel_crtc_state *pipe_config = crtc->config;
5175 if (!pipe_config->gmch_pfit.control)
5179 * The panel fitter should only be adjusted whilst the pipe is disabled,
5180 * according to register description and PRM.
5182 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5183 assert_pipe_disabled(dev_priv, crtc->pipe);
5185 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5186 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5188 /* Border color in case we don't scale up to the full screen. Black by
5189 * default, change to something else for debugging. */
5190 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5193 static enum intel_display_power_domain port_to_power_domain(enum port port)
5197 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5199 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5201 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5203 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5205 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5208 return POWER_DOMAIN_PORT_OTHER;
5212 #define for_each_power_domain(domain, mask) \
5213 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5214 if ((1 << (domain)) & (mask))
5216 enum intel_display_power_domain
5217 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5219 struct drm_device *dev = intel_encoder->base.dev;
5220 struct intel_digital_port *intel_dig_port;
5222 switch (intel_encoder->type) {
5223 case INTEL_OUTPUT_UNKNOWN:
5224 /* Only DDI platforms should ever use this output type */
5225 WARN_ON_ONCE(!HAS_DDI(dev));
5226 case INTEL_OUTPUT_DISPLAYPORT:
5227 case INTEL_OUTPUT_HDMI:
5228 case INTEL_OUTPUT_EDP:
5229 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5230 return port_to_power_domain(intel_dig_port->port);
5231 case INTEL_OUTPUT_DP_MST:
5232 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5233 return port_to_power_domain(intel_dig_port->port);
5234 case INTEL_OUTPUT_ANALOG:
5235 return POWER_DOMAIN_PORT_CRT;
5236 case INTEL_OUTPUT_DSI:
5237 return POWER_DOMAIN_PORT_DSI;
5239 return POWER_DOMAIN_PORT_OTHER;
5243 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5245 struct drm_device *dev = crtc->dev;
5246 struct intel_encoder *intel_encoder;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248 enum pipe pipe = intel_crtc->pipe;
5250 enum transcoder transcoder;
5252 if (!crtc->state->active)
5255 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5257 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5258 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5259 if (intel_crtc->config->pch_pfit.enabled ||
5260 intel_crtc->config->pch_pfit.force_thru)
5261 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5263 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5264 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5269 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5271 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273 enum intel_display_power_domain domain;
5274 unsigned long domains, new_domains, old_domains;
5276 old_domains = intel_crtc->enabled_power_domains;
5277 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5279 domains = new_domains & ~old_domains;
5281 for_each_power_domain(domain, domains)
5282 intel_display_power_get(dev_priv, domain);
5284 return old_domains & ~new_domains;
5287 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5288 unsigned long domains)
5290 enum intel_display_power_domain domain;
5292 for_each_power_domain(domain, domains)
5293 intel_display_power_put(dev_priv, domain);
5296 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5298 struct drm_device *dev = state->dev;
5299 struct drm_i915_private *dev_priv = dev->dev_private;
5300 unsigned long put_domains[I915_MAX_PIPES] = {};
5301 struct drm_crtc_state *crtc_state;
5302 struct drm_crtc *crtc;
5305 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5306 if (needs_modeset(crtc->state))
5307 put_domains[to_intel_crtc(crtc)->pipe] =
5308 modeset_get_crtc_power_domains(crtc);
5311 if (dev_priv->display.modeset_commit_cdclk) {
5312 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5314 if (cdclk != dev_priv->cdclk_freq &&
5315 !WARN_ON(!state->allow_modeset))
5316 dev_priv->display.modeset_commit_cdclk(state);
5319 for (i = 0; i < I915_MAX_PIPES; i++)
5321 modeset_put_power_domains(dev_priv, put_domains[i]);
5324 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5326 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5328 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5329 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5330 return max_cdclk_freq;
5331 else if (IS_CHERRYVIEW(dev_priv))
5332 return max_cdclk_freq*95/100;
5333 else if (INTEL_INFO(dev_priv)->gen < 4)
5334 return 2*max_cdclk_freq*90/100;
5336 return max_cdclk_freq*90/100;
5339 static void intel_update_max_cdclk(struct drm_device *dev)
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5343 if (IS_SKYLAKE(dev)) {
5344 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5346 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5347 dev_priv->max_cdclk_freq = 675000;
5348 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5349 dev_priv->max_cdclk_freq = 540000;
5350 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5351 dev_priv->max_cdclk_freq = 450000;
5353 dev_priv->max_cdclk_freq = 337500;
5354 } else if (IS_BROADWELL(dev)) {
5356 * FIXME with extra cooling we can allow
5357 * 540 MHz for ULX and 675 Mhz for ULT.
5358 * How can we know if extra cooling is
5359 * available? PCI ID, VTB, something else?
5361 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5362 dev_priv->max_cdclk_freq = 450000;
5363 else if (IS_BDW_ULX(dev))
5364 dev_priv->max_cdclk_freq = 450000;
5365 else if (IS_BDW_ULT(dev))
5366 dev_priv->max_cdclk_freq = 540000;
5368 dev_priv->max_cdclk_freq = 675000;
5369 } else if (IS_CHERRYVIEW(dev)) {
5370 dev_priv->max_cdclk_freq = 320000;
5371 } else if (IS_VALLEYVIEW(dev)) {
5372 dev_priv->max_cdclk_freq = 400000;
5374 /* otherwise assume cdclk is fixed */
5375 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5378 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5380 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5381 dev_priv->max_cdclk_freq);
5383 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5384 dev_priv->max_dotclk_freq);
5387 static void intel_update_cdclk(struct drm_device *dev)
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5391 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5392 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5393 dev_priv->cdclk_freq);
5396 * Program the gmbus_freq based on the cdclk frequency.
5397 * BSpec erroneously claims we should aim for 4MHz, but
5398 * in fact 1MHz is the correct frequency.
5400 if (IS_VALLEYVIEW(dev)) {
5402 * Program the gmbus_freq based on the cdclk frequency.
5403 * BSpec erroneously claims we should aim for 4MHz, but
5404 * in fact 1MHz is the correct frequency.
5406 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5409 if (dev_priv->max_cdclk_freq == 0)
5410 intel_update_max_cdclk(dev);
5413 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5418 uint32_t current_freq;
5421 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5422 switch (frequency) {
5424 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5425 ratio = BXT_DE_PLL_RATIO(60);
5428 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5429 ratio = BXT_DE_PLL_RATIO(60);
5432 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5433 ratio = BXT_DE_PLL_RATIO(60);
5436 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5437 ratio = BXT_DE_PLL_RATIO(60);
5440 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5441 ratio = BXT_DE_PLL_RATIO(65);
5445 * Bypass frequency with DE PLL disabled. Init ratio, divider
5446 * to suppress GCC warning.
5452 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5457 mutex_lock(&dev_priv->rps.hw_lock);
5458 /* Inform power controller of upcoming frequency change */
5459 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5461 mutex_unlock(&dev_priv->rps.hw_lock);
5464 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5469 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5470 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5471 current_freq = current_freq * 500 + 1000;
5474 * DE PLL has to be disabled when
5475 * - setting to 19.2MHz (bypass, PLL isn't used)
5476 * - before setting to 624MHz (PLL needs toggling)
5477 * - before setting to any frequency from 624MHz (PLL needs toggling)
5479 if (frequency == 19200 || frequency == 624000 ||
5480 current_freq == 624000) {
5481 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5483 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5485 DRM_ERROR("timout waiting for DE PLL unlock\n");
5488 if (frequency != 19200) {
5491 val = I915_READ(BXT_DE_PLL_CTL);
5492 val &= ~BXT_DE_PLL_RATIO_MASK;
5494 I915_WRITE(BXT_DE_PLL_CTL, val);
5496 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5498 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5499 DRM_ERROR("timeout waiting for DE PLL lock\n");
5501 val = I915_READ(CDCLK_CTL);
5502 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5505 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5508 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5509 if (frequency >= 500000)
5510 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5512 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5513 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5514 val |= (frequency - 1000) / 500;
5515 I915_WRITE(CDCLK_CTL, val);
5518 mutex_lock(&dev_priv->rps.hw_lock);
5519 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520 DIV_ROUND_UP(frequency, 25000));
5521 mutex_unlock(&dev_priv->rps.hw_lock);
5524 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5529 intel_update_cdclk(dev);
5532 void broxton_init_cdclk(struct drm_device *dev)
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5538 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5539 * or else the reset will hang because there is no PCH to respond.
5540 * Move the handshake programming to initialization sequence.
5541 * Previously was left up to BIOS.
5543 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5544 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5545 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5547 /* Enable PG1 for cdclk */
5548 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5550 /* check if cd clock is enabled */
5551 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5552 DRM_DEBUG_KMS("Display already initialized\n");
5558 * - The initial CDCLK needs to be read from VBT.
5559 * Need to make this change after VBT has changes for BXT.
5560 * - check if setting the max (or any) cdclk freq is really necessary
5561 * here, it belongs to modeset time
5563 broxton_set_cdclk(dev, 624000);
5565 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5566 POSTING_READ(DBUF_CTL);
5570 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5571 DRM_ERROR("DBuf power enable timeout!\n");
5574 void broxton_uninit_cdclk(struct drm_device *dev)
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5578 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5579 POSTING_READ(DBUF_CTL);
5583 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5584 DRM_ERROR("DBuf power disable timeout!\n");
5586 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5587 broxton_set_cdclk(dev, 19200);
5589 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5592 static const struct skl_cdclk_entry {
5595 } skl_cdclk_frequencies[] = {
5596 { .freq = 308570, .vco = 8640 },
5597 { .freq = 337500, .vco = 8100 },
5598 { .freq = 432000, .vco = 8640 },
5599 { .freq = 450000, .vco = 8100 },
5600 { .freq = 540000, .vco = 8100 },
5601 { .freq = 617140, .vco = 8640 },
5602 { .freq = 675000, .vco = 8100 },
5605 static unsigned int skl_cdclk_decimal(unsigned int freq)
5607 return (freq - 1000) / 500;
5610 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5614 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5615 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5617 if (e->freq == freq)
5625 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5627 unsigned int min_freq;
5630 /* select the minimum CDCLK before enabling DPLL 0 */
5631 val = I915_READ(CDCLK_CTL);
5632 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5633 val |= CDCLK_FREQ_337_308;
5635 if (required_vco == 8640)
5640 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5642 I915_WRITE(CDCLK_CTL, val);
5643 POSTING_READ(CDCLK_CTL);
5646 * We always enable DPLL0 with the lowest link rate possible, but still
5647 * taking into account the VCO required to operate the eDP panel at the
5648 * desired frequency. The usual DP link rates operate with a VCO of
5649 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5650 * The modeset code is responsible for the selection of the exact link
5651 * rate later on, with the constraint of choosing a frequency that
5652 * works with required_vco.
5654 val = I915_READ(DPLL_CTRL1);
5656 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5657 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5658 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5659 if (required_vco == 8640)
5660 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5663 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5666 I915_WRITE(DPLL_CTRL1, val);
5667 POSTING_READ(DPLL_CTRL1);
5669 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5671 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5672 DRM_ERROR("DPLL0 not locked\n");
5675 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5680 /* inform PCU we want to change CDCLK */
5681 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5682 mutex_lock(&dev_priv->rps.hw_lock);
5683 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5684 mutex_unlock(&dev_priv->rps.hw_lock);
5686 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5689 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5693 for (i = 0; i < 15; i++) {
5694 if (skl_cdclk_pcu_ready(dev_priv))
5702 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5704 struct drm_device *dev = dev_priv->dev;
5705 u32 freq_select, pcu_ack;
5707 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5709 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5710 DRM_ERROR("failed to inform PCU about cdclk change\n");
5718 freq_select = CDCLK_FREQ_450_432;
5722 freq_select = CDCLK_FREQ_540;
5728 freq_select = CDCLK_FREQ_337_308;
5733 freq_select = CDCLK_FREQ_675_617;
5738 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5739 POSTING_READ(CDCLK_CTL);
5741 /* inform PCU of the change */
5742 mutex_lock(&dev_priv->rps.hw_lock);
5743 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5744 mutex_unlock(&dev_priv->rps.hw_lock);
5746 intel_update_cdclk(dev);
5749 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5751 /* disable DBUF power */
5752 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5753 POSTING_READ(DBUF_CTL);
5757 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5758 DRM_ERROR("DBuf power disable timeout\n");
5761 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5763 if (dev_priv->csr.dmc_payload) {
5765 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5767 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5768 DRM_ERROR("Couldn't disable DPLL0\n");
5771 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5774 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5777 unsigned int required_vco;
5779 /* enable PCH reset handshake */
5780 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5781 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5783 /* enable PG1 and Misc I/O */
5784 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5786 /* DPLL0 not enabled (happens on early BIOS versions) */
5787 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5789 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5790 skl_dpll0_enable(dev_priv, required_vco);
5793 /* set CDCLK to the frequency the BIOS chose */
5794 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5796 /* enable DBUF power */
5797 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5798 POSTING_READ(DBUF_CTL);
5802 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5803 DRM_ERROR("DBuf power enable timeout\n");
5806 /* Adjust CDclk dividers to allow high res or save power if possible */
5807 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5812 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5813 != dev_priv->cdclk_freq);
5815 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5817 else if (cdclk == 266667)
5822 mutex_lock(&dev_priv->rps.hw_lock);
5823 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824 val &= ~DSPFREQGUAR_MASK;
5825 val |= (cmd << DSPFREQGUAR_SHIFT);
5826 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5830 DRM_ERROR("timed out waiting for CDclk change\n");
5832 mutex_unlock(&dev_priv->rps.hw_lock);
5834 mutex_lock(&dev_priv->sb_lock);
5836 if (cdclk == 400000) {
5839 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5841 /* adjust cdclk divider */
5842 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5843 val &= ~CCK_FREQUENCY_VALUES;
5845 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5847 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5848 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5850 DRM_ERROR("timed out waiting for CDclk change\n");
5853 /* adjust self-refresh exit latency value */
5854 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5858 * For high bandwidth configs, we set a higher latency in the bunit
5859 * so that the core display fetch happens in time to avoid underruns.
5861 if (cdclk == 400000)
5862 val |= 4500 / 250; /* 4.5 usec */
5864 val |= 3000 / 250; /* 3.0 usec */
5865 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5867 mutex_unlock(&dev_priv->sb_lock);
5869 intel_update_cdclk(dev);
5872 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5877 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878 != dev_priv->cdclk_freq);
5887 MISSING_CASE(cdclk);
5892 * Specs are full of misinformation, but testing on actual
5893 * hardware has shown that we just need to write the desired
5894 * CCK divider into the Punit register.
5896 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5898 mutex_lock(&dev_priv->rps.hw_lock);
5899 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5900 val &= ~DSPFREQGUAR_MASK_CHV;
5901 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5902 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5903 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5904 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5906 DRM_ERROR("timed out waiting for CDclk change\n");
5908 mutex_unlock(&dev_priv->rps.hw_lock);
5910 intel_update_cdclk(dev);
5913 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5916 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5917 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5920 * Really only a few cases to deal with, as only 4 CDclks are supported:
5923 * 320/333MHz (depends on HPLL freq)
5925 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5926 * of the lower bin and adjust if needed.
5928 * We seem to get an unstable or solid color picture at 200MHz.
5929 * Not sure what's wrong. For now use 200MHz only when all pipes
5932 if (!IS_CHERRYVIEW(dev_priv) &&
5933 max_pixclk > freq_320*limit/100)
5935 else if (max_pixclk > 266667*limit/100)
5937 else if (max_pixclk > 0)
5943 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5948 * - remove the guardband, it's not needed on BXT
5949 * - set 19.2MHz bypass frequency if there are no active pipes
5951 if (max_pixclk > 576000*9/10)
5953 else if (max_pixclk > 384000*9/10)
5955 else if (max_pixclk > 288000*9/10)
5957 else if (max_pixclk > 144000*9/10)
5963 /* Compute the max pixel clock for new configuration. Uses atomic state if
5964 * that's non-NULL, look at current state otherwise. */
5965 static int intel_mode_max_pixclk(struct drm_device *dev,
5966 struct drm_atomic_state *state)
5968 struct intel_crtc *intel_crtc;
5969 struct intel_crtc_state *crtc_state;
5972 for_each_intel_crtc(dev, intel_crtc) {
5973 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5974 if (IS_ERR(crtc_state))
5975 return PTR_ERR(crtc_state);
5977 if (!crtc_state->base.enable)
5980 max_pixclk = max(max_pixclk,
5981 crtc_state->base.adjusted_mode.crtc_clock);
5987 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5989 struct drm_device *dev = state->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 int max_pixclk = intel_mode_max_pixclk(dev, state);
5996 to_intel_atomic_state(state)->cdclk =
5997 valleyview_calc_cdclk(dev_priv, max_pixclk);
6002 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6004 struct drm_device *dev = state->dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 int max_pixclk = intel_mode_max_pixclk(dev, state);
6011 to_intel_atomic_state(state)->cdclk =
6012 broxton_calc_cdclk(dev_priv, max_pixclk);
6017 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6019 unsigned int credits, default_credits;
6021 if (IS_CHERRYVIEW(dev_priv))
6022 default_credits = PFI_CREDIT(12);
6024 default_credits = PFI_CREDIT(8);
6026 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6027 /* CHV suggested value is 31 or 63 */
6028 if (IS_CHERRYVIEW(dev_priv))
6029 credits = PFI_CREDIT_63;
6031 credits = PFI_CREDIT(15);
6033 credits = default_credits;
6037 * WA - write default credits before re-programming
6038 * FIXME: should we also set the resend bit here?
6040 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6043 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6044 credits | PFI_CREDIT_RESEND);
6047 * FIXME is this guaranteed to clear
6048 * immediately or should we poll for it?
6050 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6053 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6055 struct drm_device *dev = old_state->dev;
6056 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6060 * FIXME: We can end up here with all power domains off, yet
6061 * with a CDCLK frequency other than the minimum. To account
6062 * for this take the PIPE-A power domain, which covers the HW
6063 * blocks needed for the following programming. This can be
6064 * removed once it's guaranteed that we get here either with
6065 * the minimum CDCLK set, or the required power domains
6068 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6070 if (IS_CHERRYVIEW(dev))
6071 cherryview_set_cdclk(dev, req_cdclk);
6073 valleyview_set_cdclk(dev, req_cdclk);
6075 vlv_program_pfi_credits(dev_priv);
6077 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6080 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6082 struct drm_device *dev = crtc->dev;
6083 struct drm_i915_private *dev_priv = to_i915(dev);
6084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6085 struct intel_encoder *encoder;
6086 int pipe = intel_crtc->pipe;
6089 if (WARN_ON(intel_crtc->active))
6092 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6094 if (intel_crtc->config->has_dp_encoder)
6095 intel_dp_set_m_n(intel_crtc, M1_N1);
6097 intel_set_pipe_timings(intel_crtc);
6099 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6102 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6103 I915_WRITE(CHV_CANVAS(pipe), 0);
6106 i9xx_set_pipeconf(intel_crtc);
6108 intel_crtc->active = true;
6110 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6112 for_each_encoder_on_crtc(dev, crtc, encoder)
6113 if (encoder->pre_pll_enable)
6114 encoder->pre_pll_enable(encoder);
6117 if (IS_CHERRYVIEW(dev)) {
6118 chv_prepare_pll(intel_crtc, intel_crtc->config);
6119 chv_enable_pll(intel_crtc, intel_crtc->config);
6121 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6122 vlv_enable_pll(intel_crtc, intel_crtc->config);
6126 for_each_encoder_on_crtc(dev, crtc, encoder)
6127 if (encoder->pre_enable)
6128 encoder->pre_enable(encoder);
6130 i9xx_pfit_enable(intel_crtc);
6132 intel_crtc_load_lut(crtc);
6134 intel_enable_pipe(intel_crtc);
6136 assert_vblank_disabled(crtc);
6137 drm_crtc_vblank_on(crtc);
6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 encoder->enable(encoder);
6143 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6145 struct drm_device *dev = crtc->base.dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6148 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6149 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6152 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6154 struct drm_device *dev = crtc->dev;
6155 struct drm_i915_private *dev_priv = to_i915(dev);
6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 struct intel_encoder *encoder;
6158 int pipe = intel_crtc->pipe;
6160 if (WARN_ON(intel_crtc->active))
6163 i9xx_set_pll_dividers(intel_crtc);
6165 if (intel_crtc->config->has_dp_encoder)
6166 intel_dp_set_m_n(intel_crtc, M1_N1);
6168 intel_set_pipe_timings(intel_crtc);
6170 i9xx_set_pipeconf(intel_crtc);
6172 intel_crtc->active = true;
6175 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6177 for_each_encoder_on_crtc(dev, crtc, encoder)
6178 if (encoder->pre_enable)
6179 encoder->pre_enable(encoder);
6181 i9xx_enable_pll(intel_crtc);
6183 i9xx_pfit_enable(intel_crtc);
6185 intel_crtc_load_lut(crtc);
6187 intel_update_watermarks(crtc);
6188 intel_enable_pipe(intel_crtc);
6190 assert_vblank_disabled(crtc);
6191 drm_crtc_vblank_on(crtc);
6193 for_each_encoder_on_crtc(dev, crtc, encoder)
6194 encoder->enable(encoder);
6197 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6199 struct drm_device *dev = crtc->base.dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6202 if (!crtc->config->gmch_pfit.control)
6205 assert_pipe_disabled(dev_priv, crtc->pipe);
6207 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6208 I915_READ(PFIT_CONTROL));
6209 I915_WRITE(PFIT_CONTROL, 0);
6212 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217 struct intel_encoder *encoder;
6218 int pipe = intel_crtc->pipe;
6221 * On gen2 planes are double buffered but the pipe isn't, so we must
6222 * wait for planes to fully turn off before disabling the pipe.
6223 * We also need to wait on all gmch platforms because of the
6224 * self-refresh mode constraint explained above.
6226 intel_wait_for_vblank(dev, pipe);
6228 for_each_encoder_on_crtc(dev, crtc, encoder)
6229 encoder->disable(encoder);
6231 drm_crtc_vblank_off(crtc);
6232 assert_vblank_disabled(crtc);
6234 intel_disable_pipe(intel_crtc);
6236 i9xx_pfit_disable(intel_crtc);
6238 for_each_encoder_on_crtc(dev, crtc, encoder)
6239 if (encoder->post_disable)
6240 encoder->post_disable(encoder);
6242 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6243 if (IS_CHERRYVIEW(dev))
6244 chv_disable_pll(dev_priv, pipe);
6245 else if (IS_VALLEYVIEW(dev))
6246 vlv_disable_pll(dev_priv, pipe);
6248 i9xx_disable_pll(intel_crtc);
6251 for_each_encoder_on_crtc(dev, crtc, encoder)
6252 if (encoder->post_pll_disable)
6253 encoder->post_pll_disable(encoder);
6256 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6258 intel_crtc->active = false;
6259 intel_update_watermarks(crtc);
6262 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6266 enum intel_display_power_domain domain;
6267 unsigned long domains;
6269 if (!intel_crtc->active)
6272 if (to_intel_plane_state(crtc->primary->state)->visible) {
6273 intel_crtc_wait_for_pending_flips(crtc);
6274 intel_pre_disable_primary(crtc);
6277 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6278 dev_priv->display.crtc_disable(crtc);
6279 intel_disable_shared_dpll(intel_crtc);
6281 domains = intel_crtc->enabled_power_domains;
6282 for_each_power_domain(domain, domains)
6283 intel_display_power_put(dev_priv, domain);
6284 intel_crtc->enabled_power_domains = 0;
6288 * turn all crtc's off, but do not adjust state
6289 * This has to be paired with a call to intel_modeset_setup_hw_state.
6291 int intel_display_suspend(struct drm_device *dev)
6293 struct drm_mode_config *config = &dev->mode_config;
6294 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6295 struct drm_atomic_state *state;
6296 struct drm_crtc *crtc;
6297 unsigned crtc_mask = 0;
6303 lockdep_assert_held(&ctx->ww_ctx);
6304 state = drm_atomic_state_alloc(dev);
6305 if (WARN_ON(!state))
6308 state->acquire_ctx = ctx;
6309 state->allow_modeset = true;
6311 for_each_crtc(dev, crtc) {
6312 struct drm_crtc_state *crtc_state =
6313 drm_atomic_get_crtc_state(state, crtc);
6315 ret = PTR_ERR_OR_ZERO(crtc_state);
6319 if (!crtc_state->active)
6322 crtc_state->active = false;
6323 crtc_mask |= 1 << drm_crtc_index(crtc);
6327 ret = drm_atomic_commit(state);
6330 for_each_crtc(dev, crtc)
6331 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6332 crtc->state->active = true;
6340 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6341 drm_atomic_state_free(state);
6345 void intel_encoder_destroy(struct drm_encoder *encoder)
6347 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6349 drm_encoder_cleanup(encoder);
6350 kfree(intel_encoder);
6353 /* Cross check the actual hw state with our own modeset state tracking (and it's
6354 * internal consistency). */
6355 static void intel_connector_check_state(struct intel_connector *connector)
6357 struct drm_crtc *crtc = connector->base.state->crtc;
6359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360 connector->base.base.id,
6361 connector->base.name);
6363 if (connector->get_hw_state(connector)) {
6364 struct intel_encoder *encoder = connector->encoder;
6365 struct drm_connector_state *conn_state = connector->base.state;
6367 I915_STATE_WARN(!crtc,
6368 "connector enabled without attached crtc\n");
6373 I915_STATE_WARN(!crtc->state->active,
6374 "connector is active, but attached crtc isn't\n");
6376 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6379 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6380 "atomic encoder doesn't match attached encoder\n");
6382 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6383 "attached encoder crtc differs from connector crtc\n");
6385 I915_STATE_WARN(crtc && crtc->state->active,
6386 "attached crtc is active, but connector isn't\n");
6387 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6388 "best encoder set without crtc!\n");
6392 int intel_connector_init(struct intel_connector *connector)
6394 struct drm_connector_state *connector_state;
6396 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6397 if (!connector_state)
6400 connector->base.state = connector_state;
6404 struct intel_connector *intel_connector_alloc(void)
6406 struct intel_connector *connector;
6408 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6412 if (intel_connector_init(connector) < 0) {
6420 /* Simple connector->get_hw_state implementation for encoders that support only
6421 * one connector and no cloning and hence the encoder state determines the state
6422 * of the connector. */
6423 bool intel_connector_get_hw_state(struct intel_connector *connector)
6426 struct intel_encoder *encoder = connector->encoder;
6428 return encoder->get_hw_state(encoder, &pipe);
6431 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6433 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6434 return crtc_state->fdi_lanes;
6439 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6440 struct intel_crtc_state *pipe_config)
6442 struct drm_atomic_state *state = pipe_config->base.state;
6443 struct intel_crtc *other_crtc;
6444 struct intel_crtc_state *other_crtc_state;
6446 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6447 pipe_name(pipe), pipe_config->fdi_lanes);
6448 if (pipe_config->fdi_lanes > 4) {
6449 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6454 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6455 if (pipe_config->fdi_lanes > 2) {
6456 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6457 pipe_config->fdi_lanes);
6464 if (INTEL_INFO(dev)->num_pipes == 2)
6467 /* Ivybridge 3 pipe is really complicated */
6472 if (pipe_config->fdi_lanes <= 2)
6475 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6477 intel_atomic_get_crtc_state(state, other_crtc);
6478 if (IS_ERR(other_crtc_state))
6479 return PTR_ERR(other_crtc_state);
6481 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6482 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6483 pipe_name(pipe), pipe_config->fdi_lanes);
6488 if (pipe_config->fdi_lanes > 2) {
6489 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6490 pipe_name(pipe), pipe_config->fdi_lanes);
6494 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6496 intel_atomic_get_crtc_state(state, other_crtc);
6497 if (IS_ERR(other_crtc_state))
6498 return PTR_ERR(other_crtc_state);
6500 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6501 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6511 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6512 struct intel_crtc_state *pipe_config)
6514 struct drm_device *dev = intel_crtc->base.dev;
6515 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6516 int lane, link_bw, fdi_dotclock, ret;
6517 bool needs_recompute = false;
6520 /* FDI is a binary signal running at ~2.7GHz, encoding
6521 * each output octet as 10 bits. The actual frequency
6522 * is stored as a divider into a 100MHz clock, and the
6523 * mode pixel clock is stored in units of 1KHz.
6524 * Hence the bw of each lane in terms of the mode signal
6527 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6529 fdi_dotclock = adjusted_mode->crtc_clock;
6531 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6532 pipe_config->pipe_bpp);
6534 pipe_config->fdi_lanes = lane;
6536 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6537 link_bw, &pipe_config->fdi_m_n);
6539 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6540 intel_crtc->pipe, pipe_config);
6541 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6542 pipe_config->pipe_bpp -= 2*3;
6543 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6544 pipe_config->pipe_bpp);
6545 needs_recompute = true;
6546 pipe_config->bw_constrained = true;
6551 if (needs_recompute)
6557 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6558 struct intel_crtc_state *pipe_config)
6560 if (pipe_config->pipe_bpp > 24)
6563 /* HSW can handle pixel rate up to cdclk? */
6564 if (IS_HASWELL(dev_priv->dev))
6568 * We compare against max which means we must take
6569 * the increased cdclk requirement into account when
6570 * calculating the new cdclk.
6572 * Should measure whether using a lower cdclk w/o IPS
6574 return ilk_pipe_pixel_rate(pipe_config) <=
6575 dev_priv->max_cdclk_freq * 95 / 100;
6578 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6579 struct intel_crtc_state *pipe_config)
6581 struct drm_device *dev = crtc->base.dev;
6582 struct drm_i915_private *dev_priv = dev->dev_private;
6584 pipe_config->ips_enabled = i915.enable_ips &&
6585 hsw_crtc_supports_ips(crtc) &&
6586 pipe_config_supports_ips(dev_priv, pipe_config);
6589 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6590 struct intel_crtc_state *pipe_config)
6592 struct drm_device *dev = crtc->base.dev;
6593 struct drm_i915_private *dev_priv = dev->dev_private;
6594 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6596 /* FIXME should check pixel clock limits on all platforms */
6597 if (INTEL_INFO(dev)->gen < 4) {
6598 int clock_limit = dev_priv->max_cdclk_freq;
6601 * Enable pixel doubling when the dot clock
6602 * is > 90% of the (display) core speed.
6604 * GDG double wide on either pipe,
6605 * otherwise pipe A only.
6607 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6608 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6610 pipe_config->double_wide = true;
6613 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6618 * Pipe horizontal size must be even in:
6620 * - LVDS dual channel mode
6621 * - Double wide pipe
6623 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6624 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6625 pipe_config->pipe_src_w &= ~1;
6627 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6628 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6630 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6631 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6635 hsw_compute_ips_config(crtc, pipe_config);
6637 if (pipe_config->has_pch_encoder)
6638 return ironlake_fdi_compute_config(crtc, pipe_config);
6643 static int skylake_get_display_clock_speed(struct drm_device *dev)
6645 struct drm_i915_private *dev_priv = to_i915(dev);
6646 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6647 uint32_t cdctl = I915_READ(CDCLK_CTL);
6650 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6651 return 24000; /* 24MHz is the cd freq with NSSC ref */
6653 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6656 linkrate = (I915_READ(DPLL_CTRL1) &
6657 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6659 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6660 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6662 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6663 case CDCLK_FREQ_450_432:
6665 case CDCLK_FREQ_337_308:
6667 case CDCLK_FREQ_675_617:
6670 WARN(1, "Unknown cd freq selection\n");
6674 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6675 case CDCLK_FREQ_450_432:
6677 case CDCLK_FREQ_337_308:
6679 case CDCLK_FREQ_675_617:
6682 WARN(1, "Unknown cd freq selection\n");
6686 /* error case, do as if DPLL0 isn't enabled */
6690 static int broxton_get_display_clock_speed(struct drm_device *dev)
6692 struct drm_i915_private *dev_priv = to_i915(dev);
6693 uint32_t cdctl = I915_READ(CDCLK_CTL);
6694 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6695 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6698 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6701 cdclk = 19200 * pll_ratio / 2;
6703 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6704 case BXT_CDCLK_CD2X_DIV_SEL_1:
6705 return cdclk; /* 576MHz or 624MHz */
6706 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6707 return cdclk * 2 / 3; /* 384MHz */
6708 case BXT_CDCLK_CD2X_DIV_SEL_2:
6709 return cdclk / 2; /* 288MHz */
6710 case BXT_CDCLK_CD2X_DIV_SEL_4:
6711 return cdclk / 4; /* 144MHz */
6714 /* error case, do as if DE PLL isn't enabled */
6718 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 uint32_t lcpll = I915_READ(LCPLL_CTL);
6722 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6724 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6726 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6728 else if (freq == LCPLL_CLK_FREQ_450)
6730 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6732 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6738 static int haswell_get_display_clock_speed(struct drm_device *dev)
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 uint32_t lcpll = I915_READ(LCPLL_CTL);
6742 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6744 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6746 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6748 else if (freq == LCPLL_CLK_FREQ_450)
6750 else if (IS_HSW_ULT(dev))
6756 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6758 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6759 CCK_DISPLAY_CLOCK_CONTROL);
6762 static int ilk_get_display_clock_speed(struct drm_device *dev)
6767 static int i945_get_display_clock_speed(struct drm_device *dev)
6772 static int i915_get_display_clock_speed(struct drm_device *dev)
6777 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6782 static int pnv_get_display_clock_speed(struct drm_device *dev)
6786 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6788 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6789 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6791 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6793 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6795 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6798 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6799 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6801 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6806 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6810 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6812 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6815 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6816 case GC_DISPLAY_CLOCK_333_MHZ:
6819 case GC_DISPLAY_CLOCK_190_200_MHZ:
6825 static int i865_get_display_clock_speed(struct drm_device *dev)
6830 static int i85x_get_display_clock_speed(struct drm_device *dev)
6835 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6836 * encoding is different :(
6837 * FIXME is this the right way to detect 852GM/852GMV?
6839 if (dev->pdev->revision == 0x1)
6842 pci_bus_read_config_word(dev->pdev->bus,
6843 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6845 /* Assume that the hardware is in the high speed state. This
6846 * should be the default.
6848 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6849 case GC_CLOCK_133_200:
6850 case GC_CLOCK_133_200_2:
6851 case GC_CLOCK_100_200:
6853 case GC_CLOCK_166_250:
6855 case GC_CLOCK_100_133:
6857 case GC_CLOCK_133_266:
6858 case GC_CLOCK_133_266_2:
6859 case GC_CLOCK_166_266:
6863 /* Shouldn't happen */
6867 static int i830_get_display_clock_speed(struct drm_device *dev)
6872 static unsigned int intel_hpll_vco(struct drm_device *dev)
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 static const unsigned int blb_vco[8] = {
6882 static const unsigned int pnv_vco[8] = {
6889 static const unsigned int cl_vco[8] = {
6898 static const unsigned int elk_vco[8] = {
6904 static const unsigned int ctg_vco[8] = {
6912 const unsigned int *vco_table;
6916 /* FIXME other chipsets? */
6918 vco_table = ctg_vco;
6919 else if (IS_G4X(dev))
6920 vco_table = elk_vco;
6921 else if (IS_CRESTLINE(dev))
6923 else if (IS_PINEVIEW(dev))
6924 vco_table = pnv_vco;
6925 else if (IS_G33(dev))
6926 vco_table = blb_vco;
6930 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6932 vco = vco_table[tmp & 0x7];
6934 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6936 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6941 static int gm45_get_display_clock_speed(struct drm_device *dev)
6943 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6946 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6948 cdclk_sel = (tmp >> 12) & 0x1;
6954 return cdclk_sel ? 333333 : 222222;
6956 return cdclk_sel ? 320000 : 228571;
6958 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6963 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6965 static const uint8_t div_3200[] = { 16, 10, 8 };
6966 static const uint8_t div_4000[] = { 20, 12, 10 };
6967 static const uint8_t div_5333[] = { 24, 16, 14 };
6968 const uint8_t *div_table;
6969 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6972 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6974 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6976 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6981 div_table = div_3200;
6984 div_table = div_4000;
6987 div_table = div_5333;
6993 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6996 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7000 static int g33_get_display_clock_speed(struct drm_device *dev)
7002 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7003 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7004 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7005 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7006 const uint8_t *div_table;
7007 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7010 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7012 cdclk_sel = (tmp >> 4) & 0x7;
7014 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7019 div_table = div_3200;
7022 div_table = div_4000;
7025 div_table = div_4800;
7028 div_table = div_5333;
7034 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7037 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7042 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7044 while (*num > DATA_LINK_M_N_MASK ||
7045 *den > DATA_LINK_M_N_MASK) {
7051 static void compute_m_n(unsigned int m, unsigned int n,
7052 uint32_t *ret_m, uint32_t *ret_n)
7054 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7055 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7056 intel_reduce_m_n_ratio(ret_m, ret_n);
7060 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7061 int pixel_clock, int link_clock,
7062 struct intel_link_m_n *m_n)
7066 compute_m_n(bits_per_pixel * pixel_clock,
7067 link_clock * nlanes * 8,
7068 &m_n->gmch_m, &m_n->gmch_n);
7070 compute_m_n(pixel_clock, link_clock,
7071 &m_n->link_m, &m_n->link_n);
7074 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7076 if (i915.panel_use_ssc >= 0)
7077 return i915.panel_use_ssc != 0;
7078 return dev_priv->vbt.lvds_use_ssc
7079 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7082 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7085 struct drm_device *dev = crtc_state->base.crtc->dev;
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7089 WARN_ON(!crtc_state->base.state);
7091 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7093 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7094 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7095 refclk = dev_priv->vbt.lvds_ssc_freq;
7096 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7097 } else if (!IS_GEN2(dev)) {
7106 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7108 return (1 << dpll->n) << 16 | dpll->m2;
7111 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7113 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7116 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7117 struct intel_crtc_state *crtc_state,
7118 intel_clock_t *reduced_clock)
7120 struct drm_device *dev = crtc->base.dev;
7123 if (IS_PINEVIEW(dev)) {
7124 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7126 fp2 = pnv_dpll_compute_fp(reduced_clock);
7128 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7130 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7133 crtc_state->dpll_hw_state.fp0 = fp;
7135 crtc->lowfreq_avail = false;
7136 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7138 crtc_state->dpll_hw_state.fp1 = fp2;
7139 crtc->lowfreq_avail = true;
7141 crtc_state->dpll_hw_state.fp1 = fp;
7145 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7151 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7152 * and set it to a reasonable value instead.
7154 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7155 reg_val &= 0xffffff00;
7156 reg_val |= 0x00000030;
7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7159 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7160 reg_val &= 0x8cffffff;
7161 reg_val = 0x8c000000;
7162 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7164 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7165 reg_val &= 0xffffff00;
7166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7168 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7169 reg_val &= 0x00ffffff;
7170 reg_val |= 0xb0000000;
7171 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7174 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7175 struct intel_link_m_n *m_n)
7177 struct drm_device *dev = crtc->base.dev;
7178 struct drm_i915_private *dev_priv = dev->dev_private;
7179 int pipe = crtc->pipe;
7181 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7182 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7183 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7184 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7187 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7188 struct intel_link_m_n *m_n,
7189 struct intel_link_m_n *m2_n2)
7191 struct drm_device *dev = crtc->base.dev;
7192 struct drm_i915_private *dev_priv = dev->dev_private;
7193 int pipe = crtc->pipe;
7194 enum transcoder transcoder = crtc->config->cpu_transcoder;
7196 if (INTEL_INFO(dev)->gen >= 5) {
7197 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7199 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7200 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7201 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7202 * for gen < 8) and if DRRS is supported (to make sure the
7203 * registers are not unnecessarily accessed).
7205 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7206 crtc->config->has_drrs) {
7207 I915_WRITE(PIPE_DATA_M2(transcoder),
7208 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7209 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7210 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7211 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7214 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7215 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7216 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7217 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7221 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7223 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7226 dp_m_n = &crtc->config->dp_m_n;
7227 dp_m2_n2 = &crtc->config->dp_m2_n2;
7228 } else if (m_n == M2_N2) {
7231 * M2_N2 registers are not supported. Hence m2_n2 divider value
7232 * needs to be programmed into M1_N1.
7234 dp_m_n = &crtc->config->dp_m2_n2;
7236 DRM_ERROR("Unsupported divider value\n");
7240 if (crtc->config->has_pch_encoder)
7241 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7243 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7246 static void vlv_compute_dpll(struct intel_crtc *crtc,
7247 struct intel_crtc_state *pipe_config)
7252 * Enable DPIO clock input. We should never disable the reference
7253 * clock for pipe B, since VGA hotplug / manual detection depends
7256 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7257 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7258 /* We should never disable this, set it here for state tracking */
7259 if (crtc->pipe == PIPE_B)
7260 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7261 dpll |= DPLL_VCO_ENABLE;
7262 pipe_config->dpll_hw_state.dpll = dpll;
7264 dpll_md = (pipe_config->pixel_multiplier - 1)
7265 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7266 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7269 static void vlv_prepare_pll(struct intel_crtc *crtc,
7270 const struct intel_crtc_state *pipe_config)
7272 struct drm_device *dev = crtc->base.dev;
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274 int pipe = crtc->pipe;
7276 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7277 u32 coreclk, reg_val;
7279 mutex_lock(&dev_priv->sb_lock);
7281 bestn = pipe_config->dpll.n;
7282 bestm1 = pipe_config->dpll.m1;
7283 bestm2 = pipe_config->dpll.m2;
7284 bestp1 = pipe_config->dpll.p1;
7285 bestp2 = pipe_config->dpll.p2;
7287 /* See eDP HDMI DPIO driver vbios notes doc */
7289 /* PLL B needs special handling */
7291 vlv_pllb_recal_opamp(dev_priv, pipe);
7293 /* Set up Tx target for periodic Rcomp update */
7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7296 /* Disable target IRef on PLL */
7297 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7298 reg_val &= 0x00ffffff;
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7301 /* Disable fast lock */
7302 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7304 /* Set idtafcrecal before PLL is enabled */
7305 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7306 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7307 mdiv |= ((bestn << DPIO_N_SHIFT));
7308 mdiv |= (1 << DPIO_K_SHIFT);
7311 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7312 * but we don't support that).
7313 * Note: don't use the DAC post divider as it seems unstable.
7315 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7318 mdiv |= DPIO_ENABLE_CALIBRATION;
7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7321 /* Set HBR and RBR LPF coefficients */
7322 if (pipe_config->port_clock == 162000 ||
7323 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7324 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7331 if (pipe_config->has_dp_encoder) {
7332 /* Use SSC source */
7334 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7339 } else { /* HDMI or VGA */
7340 /* Use bend source */
7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7349 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7350 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7351 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7352 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7353 coreclk |= 0x01000000;
7354 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7357 mutex_unlock(&dev_priv->sb_lock);
7360 static void chv_compute_dpll(struct intel_crtc *crtc,
7361 struct intel_crtc_state *pipe_config)
7363 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7364 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7366 if (crtc->pipe != PIPE_A)
7367 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7369 pipe_config->dpll_hw_state.dpll_md =
7370 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7373 static void chv_prepare_pll(struct intel_crtc *crtc,
7374 const struct intel_crtc_state *pipe_config)
7376 struct drm_device *dev = crtc->base.dev;
7377 struct drm_i915_private *dev_priv = dev->dev_private;
7378 int pipe = crtc->pipe;
7379 int dpll_reg = DPLL(crtc->pipe);
7380 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7381 u32 loopfilter, tribuf_calcntr;
7382 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7386 bestn = pipe_config->dpll.n;
7387 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7388 bestm1 = pipe_config->dpll.m1;
7389 bestm2 = pipe_config->dpll.m2 >> 22;
7390 bestp1 = pipe_config->dpll.p1;
7391 bestp2 = pipe_config->dpll.p2;
7392 vco = pipe_config->dpll.vco;
7397 * Enable Refclk and SSC
7399 I915_WRITE(dpll_reg,
7400 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7402 mutex_lock(&dev_priv->sb_lock);
7404 /* p1 and p2 divider */
7405 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7406 5 << DPIO_CHV_S1_DIV_SHIFT |
7407 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7408 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7409 1 << DPIO_CHV_K_DIV_SHIFT);
7411 /* Feedback post-divider - m2 */
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7414 /* Feedback refclk divider - n and m1 */
7415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7416 DPIO_CHV_M1_DIV_BY_2 |
7417 1 << DPIO_CHV_N_DIV_SHIFT);
7419 /* M2 fraction division */
7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7422 /* M2 fraction division enable */
7423 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7424 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7425 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7427 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7430 /* Program digital lock detect threshold */
7431 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7432 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7433 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7434 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7436 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7437 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7440 if (vco == 5400000) {
7441 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7442 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7443 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7444 tribuf_calcntr = 0x9;
7445 } else if (vco <= 6200000) {
7446 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7447 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7448 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449 tribuf_calcntr = 0x9;
7450 } else if (vco <= 6480000) {
7451 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7452 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7453 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7454 tribuf_calcntr = 0x8;
7456 /* Not supported. Apply the same limits as in the max case */
7457 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7458 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7459 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7462 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7464 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7465 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7466 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7470 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7471 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7474 mutex_unlock(&dev_priv->sb_lock);
7478 * vlv_force_pll_on - forcibly enable just the PLL
7479 * @dev_priv: i915 private structure
7480 * @pipe: pipe PLL to enable
7481 * @dpll: PLL configuration
7483 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7484 * in cases where we need the PLL enabled even when @pipe is not going to
7487 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7488 const struct dpll *dpll)
7490 struct intel_crtc *crtc =
7491 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7492 struct intel_crtc_state pipe_config = {
7493 .base.crtc = &crtc->base,
7494 .pixel_multiplier = 1,
7498 if (IS_CHERRYVIEW(dev)) {
7499 chv_compute_dpll(crtc, &pipe_config);
7500 chv_prepare_pll(crtc, &pipe_config);
7501 chv_enable_pll(crtc, &pipe_config);
7503 vlv_compute_dpll(crtc, &pipe_config);
7504 vlv_prepare_pll(crtc, &pipe_config);
7505 vlv_enable_pll(crtc, &pipe_config);
7510 * vlv_force_pll_off - forcibly disable just the PLL
7511 * @dev_priv: i915 private structure
7512 * @pipe: pipe PLL to disable
7514 * Disable the PLL for @pipe. To be used in cases where we need
7515 * the PLL enabled even when @pipe is not going to be enabled.
7517 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7519 if (IS_CHERRYVIEW(dev))
7520 chv_disable_pll(to_i915(dev), pipe);
7522 vlv_disable_pll(to_i915(dev), pipe);
7525 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7526 struct intel_crtc_state *crtc_state,
7527 intel_clock_t *reduced_clock,
7530 struct drm_device *dev = crtc->base.dev;
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7534 struct dpll *clock = &crtc_state->dpll;
7536 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7538 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7539 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7541 dpll = DPLL_VGA_MODE_DIS;
7543 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7544 dpll |= DPLLB_MODE_LVDS;
7546 dpll |= DPLLB_MODE_DAC_SERIAL;
7548 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7549 dpll |= (crtc_state->pixel_multiplier - 1)
7550 << SDVO_MULTIPLIER_SHIFT_HIRES;
7554 dpll |= DPLL_SDVO_HIGH_SPEED;
7556 if (crtc_state->has_dp_encoder)
7557 dpll |= DPLL_SDVO_HIGH_SPEED;
7559 /* compute bitmask from p1 value */
7560 if (IS_PINEVIEW(dev))
7561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564 if (IS_G4X(dev) && reduced_clock)
7565 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7567 switch (clock->p2) {
7569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7581 if (INTEL_INFO(dev)->gen >= 4)
7582 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7584 if (crtc_state->sdvo_tv_clock)
7585 dpll |= PLL_REF_INPUT_TVCLKINBC;
7586 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7590 dpll |= PLL_REF_INPUT_DREFCLK;
7592 dpll |= DPLL_VCO_ENABLE;
7593 crtc_state->dpll_hw_state.dpll = dpll;
7595 if (INTEL_INFO(dev)->gen >= 4) {
7596 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7597 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7598 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7602 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7603 struct intel_crtc_state *crtc_state,
7604 intel_clock_t *reduced_clock,
7607 struct drm_device *dev = crtc->base.dev;
7608 struct drm_i915_private *dev_priv = dev->dev_private;
7610 struct dpll *clock = &crtc_state->dpll;
7612 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7614 dpll = DPLL_VGA_MODE_DIS;
7616 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7617 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7620 dpll |= PLL_P1_DIVIDE_BY_TWO;
7622 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7624 dpll |= PLL_P2_DIVIDE_BY_4;
7627 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7628 dpll |= DPLL_DVO_2X_MODE;
7630 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7631 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7632 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7634 dpll |= PLL_REF_INPUT_DREFCLK;
7636 dpll |= DPLL_VCO_ENABLE;
7637 crtc_state->dpll_hw_state.dpll = dpll;
7640 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7642 struct drm_device *dev = intel_crtc->base.dev;
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644 enum pipe pipe = intel_crtc->pipe;
7645 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7646 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7647 uint32_t crtc_vtotal, crtc_vblank_end;
7650 /* We need to be careful not to changed the adjusted mode, for otherwise
7651 * the hw state checker will get angry at the mismatch. */
7652 crtc_vtotal = adjusted_mode->crtc_vtotal;
7653 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7655 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7656 /* the chip adds 2 halflines automatically */
7658 crtc_vblank_end -= 1;
7660 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7661 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7663 vsyncshift = adjusted_mode->crtc_hsync_start -
7664 adjusted_mode->crtc_htotal / 2;
7666 vsyncshift += adjusted_mode->crtc_htotal;
7669 if (INTEL_INFO(dev)->gen > 3)
7670 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7672 I915_WRITE(HTOTAL(cpu_transcoder),
7673 (adjusted_mode->crtc_hdisplay - 1) |
7674 ((adjusted_mode->crtc_htotal - 1) << 16));
7675 I915_WRITE(HBLANK(cpu_transcoder),
7676 (adjusted_mode->crtc_hblank_start - 1) |
7677 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7678 I915_WRITE(HSYNC(cpu_transcoder),
7679 (adjusted_mode->crtc_hsync_start - 1) |
7680 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7682 I915_WRITE(VTOTAL(cpu_transcoder),
7683 (adjusted_mode->crtc_vdisplay - 1) |
7684 ((crtc_vtotal - 1) << 16));
7685 I915_WRITE(VBLANK(cpu_transcoder),
7686 (adjusted_mode->crtc_vblank_start - 1) |
7687 ((crtc_vblank_end - 1) << 16));
7688 I915_WRITE(VSYNC(cpu_transcoder),
7689 (adjusted_mode->crtc_vsync_start - 1) |
7690 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7692 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7693 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7694 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7696 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7697 (pipe == PIPE_B || pipe == PIPE_C))
7698 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7700 /* pipesrc controls the size that is scaled from, which should
7701 * always be the user's requested size.
7703 I915_WRITE(PIPESRC(pipe),
7704 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7705 (intel_crtc->config->pipe_src_h - 1));
7708 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7709 struct intel_crtc_state *pipe_config)
7711 struct drm_device *dev = crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
7713 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7716 tmp = I915_READ(HTOTAL(cpu_transcoder));
7717 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7719 tmp = I915_READ(HBLANK(cpu_transcoder));
7720 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7721 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7722 tmp = I915_READ(HSYNC(cpu_transcoder));
7723 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7724 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7726 tmp = I915_READ(VTOTAL(cpu_transcoder));
7727 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7728 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7729 tmp = I915_READ(VBLANK(cpu_transcoder));
7730 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7731 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7732 tmp = I915_READ(VSYNC(cpu_transcoder));
7733 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7734 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7736 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7737 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7738 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7739 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7742 tmp = I915_READ(PIPESRC(crtc->pipe));
7743 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7744 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7746 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7747 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7750 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7751 struct intel_crtc_state *pipe_config)
7753 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7754 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7755 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7756 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7758 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7759 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7760 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7761 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7763 mode->flags = pipe_config->base.adjusted_mode.flags;
7764 mode->type = DRM_MODE_TYPE_DRIVER;
7766 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7767 mode->flags |= pipe_config->base.adjusted_mode.flags;
7769 mode->hsync = drm_mode_hsync(mode);
7770 mode->vrefresh = drm_mode_vrefresh(mode);
7771 drm_mode_set_name(mode);
7774 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7776 struct drm_device *dev = intel_crtc->base.dev;
7777 struct drm_i915_private *dev_priv = dev->dev_private;
7782 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7783 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7784 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7786 if (intel_crtc->config->double_wide)
7787 pipeconf |= PIPECONF_DOUBLE_WIDE;
7789 /* only g4x and later have fancy bpc/dither controls */
7790 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7791 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7792 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7793 pipeconf |= PIPECONF_DITHER_EN |
7794 PIPECONF_DITHER_TYPE_SP;
7796 switch (intel_crtc->config->pipe_bpp) {
7798 pipeconf |= PIPECONF_6BPC;
7801 pipeconf |= PIPECONF_8BPC;
7804 pipeconf |= PIPECONF_10BPC;
7807 /* Case prevented by intel_choose_pipe_bpp_dither. */
7812 if (HAS_PIPE_CXSR(dev)) {
7813 if (intel_crtc->lowfreq_avail) {
7814 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7815 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7817 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7821 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7822 if (INTEL_INFO(dev)->gen < 4 ||
7823 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7824 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7826 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7828 pipeconf |= PIPECONF_PROGRESSIVE;
7830 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7831 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7833 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7834 POSTING_READ(PIPECONF(intel_crtc->pipe));
7837 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7838 struct intel_crtc_state *crtc_state)
7840 struct drm_device *dev = crtc->base.dev;
7841 struct drm_i915_private *dev_priv = dev->dev_private;
7842 int refclk, num_connectors = 0;
7843 intel_clock_t clock;
7845 bool is_dsi = false;
7846 struct intel_encoder *encoder;
7847 const intel_limit_t *limit;
7848 struct drm_atomic_state *state = crtc_state->base.state;
7849 struct drm_connector *connector;
7850 struct drm_connector_state *connector_state;
7853 memset(&crtc_state->dpll_hw_state, 0,
7854 sizeof(crtc_state->dpll_hw_state));
7856 for_each_connector_in_state(state, connector, connector_state, i) {
7857 if (connector_state->crtc != &crtc->base)
7860 encoder = to_intel_encoder(connector_state->best_encoder);
7862 switch (encoder->type) {
7863 case INTEL_OUTPUT_DSI:
7876 if (!crtc_state->clock_set) {
7877 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7880 * Returns a set of divisors for the desired target clock with
7881 * the given refclk, or FALSE. The returned values represent
7882 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7885 limit = intel_limit(crtc_state, refclk);
7886 ok = dev_priv->display.find_dpll(limit, crtc_state,
7887 crtc_state->port_clock,
7888 refclk, NULL, &clock);
7890 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7894 /* Compat-code for transition, will disappear. */
7895 crtc_state->dpll.n = clock.n;
7896 crtc_state->dpll.m1 = clock.m1;
7897 crtc_state->dpll.m2 = clock.m2;
7898 crtc_state->dpll.p1 = clock.p1;
7899 crtc_state->dpll.p2 = clock.p2;
7903 i8xx_compute_dpll(crtc, crtc_state, NULL,
7905 } else if (IS_CHERRYVIEW(dev)) {
7906 chv_compute_dpll(crtc, crtc_state);
7907 } else if (IS_VALLEYVIEW(dev)) {
7908 vlv_compute_dpll(crtc, crtc_state);
7910 i9xx_compute_dpll(crtc, crtc_state, NULL,
7917 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7918 struct intel_crtc_state *pipe_config)
7920 struct drm_device *dev = crtc->base.dev;
7921 struct drm_i915_private *dev_priv = dev->dev_private;
7924 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7927 tmp = I915_READ(PFIT_CONTROL);
7928 if (!(tmp & PFIT_ENABLE))
7931 /* Check whether the pfit is attached to our pipe. */
7932 if (INTEL_INFO(dev)->gen < 4) {
7933 if (crtc->pipe != PIPE_B)
7936 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7940 pipe_config->gmch_pfit.control = tmp;
7941 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7942 if (INTEL_INFO(dev)->gen < 5)
7943 pipe_config->gmch_pfit.lvds_border_bits =
7944 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7947 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7948 struct intel_crtc_state *pipe_config)
7950 struct drm_device *dev = crtc->base.dev;
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7952 int pipe = pipe_config->cpu_transcoder;
7953 intel_clock_t clock;
7955 int refclk = 100000;
7957 /* In case of MIPI DPLL will not even be used */
7958 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7961 mutex_lock(&dev_priv->sb_lock);
7962 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7963 mutex_unlock(&dev_priv->sb_lock);
7965 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7966 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7967 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7968 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7969 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7971 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7975 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7976 struct intel_initial_plane_config *plane_config)
7978 struct drm_device *dev = crtc->base.dev;
7979 struct drm_i915_private *dev_priv = dev->dev_private;
7980 u32 val, base, offset;
7981 int pipe = crtc->pipe, plane = crtc->plane;
7982 int fourcc, pixel_format;
7983 unsigned int aligned_height;
7984 struct drm_framebuffer *fb;
7985 struct intel_framebuffer *intel_fb;
7987 val = I915_READ(DSPCNTR(plane));
7988 if (!(val & DISPLAY_PLANE_ENABLE))
7991 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7993 DRM_DEBUG_KMS("failed to alloc fb\n");
7997 fb = &intel_fb->base;
7999 if (INTEL_INFO(dev)->gen >= 4) {
8000 if (val & DISPPLANE_TILED) {
8001 plane_config->tiling = I915_TILING_X;
8002 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8006 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8007 fourcc = i9xx_format_to_fourcc(pixel_format);
8008 fb->pixel_format = fourcc;
8009 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8011 if (INTEL_INFO(dev)->gen >= 4) {
8012 if (plane_config->tiling)
8013 offset = I915_READ(DSPTILEOFF(plane));
8015 offset = I915_READ(DSPLINOFF(plane));
8016 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8018 base = I915_READ(DSPADDR(plane));
8020 plane_config->base = base;
8022 val = I915_READ(PIPESRC(pipe));
8023 fb->width = ((val >> 16) & 0xfff) + 1;
8024 fb->height = ((val >> 0) & 0xfff) + 1;
8026 val = I915_READ(DSPSTRIDE(pipe));
8027 fb->pitches[0] = val & 0xffffffc0;
8029 aligned_height = intel_fb_align_height(dev, fb->height,
8033 plane_config->size = fb->pitches[0] * aligned_height;
8035 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8036 pipe_name(pipe), plane, fb->width, fb->height,
8037 fb->bits_per_pixel, base, fb->pitches[0],
8038 plane_config->size);
8040 plane_config->fb = intel_fb;
8043 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8044 struct intel_crtc_state *pipe_config)
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 int pipe = pipe_config->cpu_transcoder;
8049 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8050 intel_clock_t clock;
8051 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8052 int refclk = 100000;
8054 mutex_lock(&dev_priv->sb_lock);
8055 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8056 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8057 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8058 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8059 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8060 mutex_unlock(&dev_priv->sb_lock);
8062 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8063 clock.m2 = (pll_dw0 & 0xff) << 22;
8064 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8065 clock.m2 |= pll_dw2 & 0x3fffff;
8066 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8067 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8068 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8070 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8073 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8074 struct intel_crtc_state *pipe_config)
8076 struct drm_device *dev = crtc->base.dev;
8077 struct drm_i915_private *dev_priv = dev->dev_private;
8080 if (!intel_display_power_is_enabled(dev_priv,
8081 POWER_DOMAIN_PIPE(crtc->pipe)))
8084 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8085 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8087 tmp = I915_READ(PIPECONF(crtc->pipe));
8088 if (!(tmp & PIPECONF_ENABLE))
8091 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8092 switch (tmp & PIPECONF_BPC_MASK) {
8094 pipe_config->pipe_bpp = 18;
8097 pipe_config->pipe_bpp = 24;
8099 case PIPECONF_10BPC:
8100 pipe_config->pipe_bpp = 30;
8107 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8108 pipe_config->limited_color_range = true;
8110 if (INTEL_INFO(dev)->gen < 4)
8111 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8113 intel_get_pipe_timings(crtc, pipe_config);
8115 i9xx_get_pfit_config(crtc, pipe_config);
8117 if (INTEL_INFO(dev)->gen >= 4) {
8118 tmp = I915_READ(DPLL_MD(crtc->pipe));
8119 pipe_config->pixel_multiplier =
8120 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8121 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8122 pipe_config->dpll_hw_state.dpll_md = tmp;
8123 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8124 tmp = I915_READ(DPLL(crtc->pipe));
8125 pipe_config->pixel_multiplier =
8126 ((tmp & SDVO_MULTIPLIER_MASK)
8127 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8129 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8130 * port and will be fixed up in the encoder->get_config
8132 pipe_config->pixel_multiplier = 1;
8134 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8135 if (!IS_VALLEYVIEW(dev)) {
8137 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8138 * on 830. Filter it out here so that we don't
8139 * report errors due to that.
8142 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8144 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8145 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8147 /* Mask out read-only status bits. */
8148 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8149 DPLL_PORTC_READY_MASK |
8150 DPLL_PORTB_READY_MASK);
8153 if (IS_CHERRYVIEW(dev))
8154 chv_crtc_clock_get(crtc, pipe_config);
8155 else if (IS_VALLEYVIEW(dev))
8156 vlv_crtc_clock_get(crtc, pipe_config);
8158 i9xx_crtc_clock_get(crtc, pipe_config);
8161 * Normally the dotclock is filled in by the encoder .get_config()
8162 * but in case the pipe is enabled w/o any ports we need a sane
8165 pipe_config->base.adjusted_mode.crtc_clock =
8166 pipe_config->port_clock / pipe_config->pixel_multiplier;
8171 static void ironlake_init_pch_refclk(struct drm_device *dev)
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 struct intel_encoder *encoder;
8176 bool has_lvds = false;
8177 bool has_cpu_edp = false;
8178 bool has_panel = false;
8179 bool has_ck505 = false;
8180 bool can_ssc = false;
8182 /* We need to take the global config into account */
8183 for_each_intel_encoder(dev, encoder) {
8184 switch (encoder->type) {
8185 case INTEL_OUTPUT_LVDS:
8189 case INTEL_OUTPUT_EDP:
8191 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8199 if (HAS_PCH_IBX(dev)) {
8200 has_ck505 = dev_priv->vbt.display_clock_mode;
8201 can_ssc = has_ck505;
8207 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208 has_panel, has_lvds, has_ck505);
8210 /* Ironlake: try to setup display ref clock before DPLL
8211 * enabling. This is only under driver's control after
8212 * PCH B stepping, previous chipset stepping should be
8213 * ignoring this setting.
8215 val = I915_READ(PCH_DREF_CONTROL);
8217 /* As we must carefully and slowly disable/enable each source in turn,
8218 * compute the final state we want first and check if we need to
8219 * make any changes at all.
8222 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8224 final |= DREF_NONSPREAD_CK505_ENABLE;
8226 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8228 final &= ~DREF_SSC_SOURCE_MASK;
8229 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230 final &= ~DREF_SSC1_ENABLE;
8233 final |= DREF_SSC_SOURCE_ENABLE;
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236 final |= DREF_SSC1_ENABLE;
8239 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8242 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8244 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8246 final |= DREF_SSC_SOURCE_DISABLE;
8247 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8253 /* Always enable nonspread source */
8254 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8257 val |= DREF_NONSPREAD_CK505_ENABLE;
8259 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8262 val &= ~DREF_SSC_SOURCE_MASK;
8263 val |= DREF_SSC_SOURCE_ENABLE;
8265 /* SSC must be turned on before enabling the CPU output */
8266 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8267 DRM_DEBUG_KMS("Using SSC on panel\n");
8268 val |= DREF_SSC1_ENABLE;
8270 val &= ~DREF_SSC1_ENABLE;
8272 /* Get SSC going before enabling the outputs */
8273 I915_WRITE(PCH_DREF_CONTROL, val);
8274 POSTING_READ(PCH_DREF_CONTROL);
8277 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8279 /* Enable CPU source on CPU attached eDP */
8281 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8282 DRM_DEBUG_KMS("Using SSC on eDP\n");
8283 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8285 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8287 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8289 I915_WRITE(PCH_DREF_CONTROL, val);
8290 POSTING_READ(PCH_DREF_CONTROL);
8293 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8295 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297 /* Turn off CPU output */
8298 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8300 I915_WRITE(PCH_DREF_CONTROL, val);
8301 POSTING_READ(PCH_DREF_CONTROL);
8304 /* Turn off the SSC source */
8305 val &= ~DREF_SSC_SOURCE_MASK;
8306 val |= DREF_SSC_SOURCE_DISABLE;
8309 val &= ~DREF_SSC1_ENABLE;
8311 I915_WRITE(PCH_DREF_CONTROL, val);
8312 POSTING_READ(PCH_DREF_CONTROL);
8316 BUG_ON(val != final);
8319 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8323 tmp = I915_READ(SOUTH_CHICKEN2);
8324 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325 I915_WRITE(SOUTH_CHICKEN2, tmp);
8327 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329 DRM_ERROR("FDI mPHY reset assert timeout\n");
8331 tmp = I915_READ(SOUTH_CHICKEN2);
8332 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333 I915_WRITE(SOUTH_CHICKEN2, tmp);
8335 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8340 /* WaMPhyProgramming:hsw */
8341 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8345 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346 tmp &= ~(0xFF << 24);
8347 tmp |= (0x12 << 24);
8348 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8350 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8352 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8354 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8356 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8358 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8362 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8366 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8369 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8371 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8374 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8376 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8379 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8381 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8384 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8386 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387 tmp &= ~(0xFF << 16);
8388 tmp |= (0x1C << 16);
8389 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8391 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392 tmp &= ~(0xFF << 16);
8393 tmp |= (0x1C << 16);
8394 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8396 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8398 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8400 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8402 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8404 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405 tmp &= ~(0xF << 28);
8407 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8409 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410 tmp &= ~(0xF << 28);
8412 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8415 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8416 * Programming" based on the parameters passed:
8417 * - Sequence to enable CLKOUT_DP
8418 * - Sequence to enable CLKOUT_DP without spread
8419 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8421 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8424 struct drm_i915_private *dev_priv = dev->dev_private;
8427 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8429 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8432 mutex_lock(&dev_priv->sb_lock);
8434 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8435 tmp &= ~SBI_SSCCTL_DISABLE;
8436 tmp |= SBI_SSCCTL_PATHALT;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8442 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8443 tmp &= ~SBI_SSCCTL_PATHALT;
8444 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8447 lpt_reset_fdi_mphy(dev_priv);
8448 lpt_program_fdi_mphy(dev_priv);
8452 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8453 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8454 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8455 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8457 mutex_unlock(&dev_priv->sb_lock);
8460 /* Sequence to disable CLKOUT_DP */
8461 static void lpt_disable_clkout_dp(struct drm_device *dev)
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8466 mutex_lock(&dev_priv->sb_lock);
8468 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8469 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8470 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8471 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8473 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8475 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8476 tmp |= SBI_SSCCTL_PATHALT;
8477 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8480 tmp |= SBI_SSCCTL_DISABLE;
8481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8484 mutex_unlock(&dev_priv->sb_lock);
8487 static void lpt_init_pch_refclk(struct drm_device *dev)
8489 struct intel_encoder *encoder;
8490 bool has_vga = false;
8492 for_each_intel_encoder(dev, encoder) {
8493 switch (encoder->type) {
8494 case INTEL_OUTPUT_ANALOG:
8503 lpt_enable_clkout_dp(dev, true, true);
8505 lpt_disable_clkout_dp(dev);
8509 * Initialize reference clocks when the driver loads
8511 void intel_init_pch_refclk(struct drm_device *dev)
8513 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8514 ironlake_init_pch_refclk(dev);
8515 else if (HAS_PCH_LPT(dev))
8516 lpt_init_pch_refclk(dev);
8519 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8521 struct drm_device *dev = crtc_state->base.crtc->dev;
8522 struct drm_i915_private *dev_priv = dev->dev_private;
8523 struct drm_atomic_state *state = crtc_state->base.state;
8524 struct drm_connector *connector;
8525 struct drm_connector_state *connector_state;
8526 struct intel_encoder *encoder;
8527 int num_connectors = 0, i;
8528 bool is_lvds = false;
8530 for_each_connector_in_state(state, connector, connector_state, i) {
8531 if (connector_state->crtc != crtc_state->base.crtc)
8534 encoder = to_intel_encoder(connector_state->best_encoder);
8536 switch (encoder->type) {
8537 case INTEL_OUTPUT_LVDS:
8546 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8547 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8548 dev_priv->vbt.lvds_ssc_freq);
8549 return dev_priv->vbt.lvds_ssc_freq;
8555 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8557 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8559 int pipe = intel_crtc->pipe;
8564 switch (intel_crtc->config->pipe_bpp) {
8566 val |= PIPECONF_6BPC;
8569 val |= PIPECONF_8BPC;
8572 val |= PIPECONF_10BPC;
8575 val |= PIPECONF_12BPC;
8578 /* Case prevented by intel_choose_pipe_bpp_dither. */
8582 if (intel_crtc->config->dither)
8583 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8585 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8586 val |= PIPECONF_INTERLACED_ILK;
8588 val |= PIPECONF_PROGRESSIVE;
8590 if (intel_crtc->config->limited_color_range)
8591 val |= PIPECONF_COLOR_RANGE_SELECT;
8593 I915_WRITE(PIPECONF(pipe), val);
8594 POSTING_READ(PIPECONF(pipe));
8598 * Set up the pipe CSC unit.
8600 * Currently only full range RGB to limited range RGB conversion
8601 * is supported, but eventually this should handle various
8602 * RGB<->YCbCr scenarios as well.
8604 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8606 struct drm_device *dev = crtc->dev;
8607 struct drm_i915_private *dev_priv = dev->dev_private;
8608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609 int pipe = intel_crtc->pipe;
8610 uint16_t coeff = 0x7800; /* 1.0 */
8613 * TODO: Check what kind of values actually come out of the pipe
8614 * with these coeff/postoff values and adjust to get the best
8615 * accuracy. Perhaps we even need to take the bpc value into
8619 if (intel_crtc->config->limited_color_range)
8620 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8623 * GY/GU and RY/RU should be the other way around according
8624 * to BSpec, but reality doesn't agree. Just set them up in
8625 * a way that results in the correct picture.
8627 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8628 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8630 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8631 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8633 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8634 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8636 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8637 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8638 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8640 if (INTEL_INFO(dev)->gen > 6) {
8641 uint16_t postoff = 0;
8643 if (intel_crtc->config->limited_color_range)
8644 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8646 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8647 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8648 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8650 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8652 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8654 if (intel_crtc->config->limited_color_range)
8655 mode |= CSC_BLACK_SCREEN_OFFSET;
8657 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8661 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8663 struct drm_device *dev = crtc->dev;
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8666 enum pipe pipe = intel_crtc->pipe;
8667 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8672 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8673 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8675 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8676 val |= PIPECONF_INTERLACED_ILK;
8678 val |= PIPECONF_PROGRESSIVE;
8680 I915_WRITE(PIPECONF(cpu_transcoder), val);
8681 POSTING_READ(PIPECONF(cpu_transcoder));
8683 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8684 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8686 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8689 switch (intel_crtc->config->pipe_bpp) {
8691 val |= PIPEMISC_DITHER_6_BPC;
8694 val |= PIPEMISC_DITHER_8_BPC;
8697 val |= PIPEMISC_DITHER_10_BPC;
8700 val |= PIPEMISC_DITHER_12_BPC;
8703 /* Case prevented by pipe_config_set_bpp. */
8707 if (intel_crtc->config->dither)
8708 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8710 I915_WRITE(PIPEMISC(pipe), val);
8714 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8715 struct intel_crtc_state *crtc_state,
8716 intel_clock_t *clock,
8717 bool *has_reduced_clock,
8718 intel_clock_t *reduced_clock)
8720 struct drm_device *dev = crtc->dev;
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8723 const intel_limit_t *limit;
8726 refclk = ironlake_get_refclk(crtc_state);
8729 * Returns a set of divisors for the desired target clock with the given
8730 * refclk, or FALSE. The returned values represent the clock equation:
8731 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8733 limit = intel_limit(crtc_state, refclk);
8734 ret = dev_priv->display.find_dpll(limit, crtc_state,
8735 crtc_state->port_clock,
8736 refclk, NULL, clock);
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8746 * Account for spread spectrum to avoid
8747 * oversubscribing the link. Max center spread
8748 * is 2.5%; use 5% for safety's sake.
8750 u32 bps = target_clock * bpp * 21 / 20;
8751 return DIV_ROUND_UP(bps, link_bw * 8);
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8756 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8759 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760 struct intel_crtc_state *crtc_state,
8762 intel_clock_t *reduced_clock, u32 *fp2)
8764 struct drm_crtc *crtc = &intel_crtc->base;
8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
8767 struct drm_atomic_state *state = crtc_state->base.state;
8768 struct drm_connector *connector;
8769 struct drm_connector_state *connector_state;
8770 struct intel_encoder *encoder;
8772 int factor, num_connectors = 0, i;
8773 bool is_lvds = false, is_sdvo = false;
8775 for_each_connector_in_state(state, connector, connector_state, i) {
8776 if (connector_state->crtc != crtc_state->base.crtc)
8779 encoder = to_intel_encoder(connector_state->best_encoder);
8781 switch (encoder->type) {
8782 case INTEL_OUTPUT_LVDS:
8785 case INTEL_OUTPUT_SDVO:
8786 case INTEL_OUTPUT_HDMI:
8796 /* Enable autotuning of the PLL clock (if permissible) */
8799 if ((intel_panel_use_ssc(dev_priv) &&
8800 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8801 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8803 } else if (crtc_state->sdvo_tv_clock)
8806 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8809 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8815 dpll |= DPLLB_MODE_LVDS;
8817 dpll |= DPLLB_MODE_DAC_SERIAL;
8819 dpll |= (crtc_state->pixel_multiplier - 1)
8820 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8823 dpll |= DPLL_SDVO_HIGH_SPEED;
8824 if (crtc_state->has_dp_encoder)
8825 dpll |= DPLL_SDVO_HIGH_SPEED;
8827 /* compute bitmask from p1 value */
8828 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8830 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8832 switch (crtc_state->dpll.p2) {
8834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8847 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8848 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8850 dpll |= PLL_REF_INPUT_DREFCLK;
8852 return dpll | DPLL_VCO_ENABLE;
8855 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8856 struct intel_crtc_state *crtc_state)
8858 struct drm_device *dev = crtc->base.dev;
8859 intel_clock_t clock, reduced_clock;
8860 u32 dpll = 0, fp = 0, fp2 = 0;
8861 bool ok, has_reduced_clock = false;
8862 bool is_lvds = false;
8863 struct intel_shared_dpll *pll;
8865 memset(&crtc_state->dpll_hw_state, 0,
8866 sizeof(crtc_state->dpll_hw_state));
8868 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8870 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8871 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8873 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8874 &has_reduced_clock, &reduced_clock);
8875 if (!ok && !crtc_state->clock_set) {
8876 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8879 /* Compat-code for transition, will disappear. */
8880 if (!crtc_state->clock_set) {
8881 crtc_state->dpll.n = clock.n;
8882 crtc_state->dpll.m1 = clock.m1;
8883 crtc_state->dpll.m2 = clock.m2;
8884 crtc_state->dpll.p1 = clock.p1;
8885 crtc_state->dpll.p2 = clock.p2;
8888 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8889 if (crtc_state->has_pch_encoder) {
8890 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8891 if (has_reduced_clock)
8892 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8894 dpll = ironlake_compute_dpll(crtc, crtc_state,
8895 &fp, &reduced_clock,
8896 has_reduced_clock ? &fp2 : NULL);
8898 crtc_state->dpll_hw_state.dpll = dpll;
8899 crtc_state->dpll_hw_state.fp0 = fp;
8900 if (has_reduced_clock)
8901 crtc_state->dpll_hw_state.fp1 = fp2;
8903 crtc_state->dpll_hw_state.fp1 = fp;
8905 pll = intel_get_shared_dpll(crtc, crtc_state);
8907 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8908 pipe_name(crtc->pipe));
8913 if (is_lvds && has_reduced_clock)
8914 crtc->lowfreq_avail = true;
8916 crtc->lowfreq_avail = false;
8921 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8922 struct intel_link_m_n *m_n)
8924 struct drm_device *dev = crtc->base.dev;
8925 struct drm_i915_private *dev_priv = dev->dev_private;
8926 enum pipe pipe = crtc->pipe;
8928 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8929 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8930 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8932 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8933 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8937 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8938 enum transcoder transcoder,
8939 struct intel_link_m_n *m_n,
8940 struct intel_link_m_n *m2_n2)
8942 struct drm_device *dev = crtc->base.dev;
8943 struct drm_i915_private *dev_priv = dev->dev_private;
8944 enum pipe pipe = crtc->pipe;
8946 if (INTEL_INFO(dev)->gen >= 5) {
8947 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8948 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8949 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8951 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8952 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8953 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8955 * gen < 8) and if DRRS is supported (to make sure the
8956 * registers are not unnecessarily read).
8958 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8959 crtc->config->has_drrs) {
8960 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8961 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8962 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8964 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8965 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8966 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8969 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8970 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8971 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8973 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8974 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8975 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8979 void intel_dp_get_m_n(struct intel_crtc *crtc,
8980 struct intel_crtc_state *pipe_config)
8982 if (pipe_config->has_pch_encoder)
8983 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8985 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8986 &pipe_config->dp_m_n,
8987 &pipe_config->dp_m2_n2);
8990 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8991 struct intel_crtc_state *pipe_config)
8993 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8994 &pipe_config->fdi_m_n, NULL);
8997 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8998 struct intel_crtc_state *pipe_config)
9000 struct drm_device *dev = crtc->base.dev;
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9002 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9003 uint32_t ps_ctrl = 0;
9007 /* find scaler attached to this pipe */
9008 for (i = 0; i < crtc->num_scalers; i++) {
9009 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9010 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9012 pipe_config->pch_pfit.enabled = true;
9013 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9014 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9019 scaler_state->scaler_id = id;
9021 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9023 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9028 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9029 struct intel_initial_plane_config *plane_config)
9031 struct drm_device *dev = crtc->base.dev;
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 u32 val, base, offset, stride_mult, tiling;
9034 int pipe = crtc->pipe;
9035 int fourcc, pixel_format;
9036 unsigned int aligned_height;
9037 struct drm_framebuffer *fb;
9038 struct intel_framebuffer *intel_fb;
9040 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9042 DRM_DEBUG_KMS("failed to alloc fb\n");
9046 fb = &intel_fb->base;
9048 val = I915_READ(PLANE_CTL(pipe, 0));
9049 if (!(val & PLANE_CTL_ENABLE))
9052 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9053 fourcc = skl_format_to_fourcc(pixel_format,
9054 val & PLANE_CTL_ORDER_RGBX,
9055 val & PLANE_CTL_ALPHA_MASK);
9056 fb->pixel_format = fourcc;
9057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9059 tiling = val & PLANE_CTL_TILED_MASK;
9061 case PLANE_CTL_TILED_LINEAR:
9062 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9064 case PLANE_CTL_TILED_X:
9065 plane_config->tiling = I915_TILING_X;
9066 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9068 case PLANE_CTL_TILED_Y:
9069 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9071 case PLANE_CTL_TILED_YF:
9072 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9075 MISSING_CASE(tiling);
9079 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9080 plane_config->base = base;
9082 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9084 val = I915_READ(PLANE_SIZE(pipe, 0));
9085 fb->height = ((val >> 16) & 0xfff) + 1;
9086 fb->width = ((val >> 0) & 0x1fff) + 1;
9088 val = I915_READ(PLANE_STRIDE(pipe, 0));
9089 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9091 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9093 aligned_height = intel_fb_align_height(dev, fb->height,
9097 plane_config->size = fb->pitches[0] * aligned_height;
9099 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9100 pipe_name(pipe), fb->width, fb->height,
9101 fb->bits_per_pixel, base, fb->pitches[0],
9102 plane_config->size);
9104 plane_config->fb = intel_fb;
9111 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9112 struct intel_crtc_state *pipe_config)
9114 struct drm_device *dev = crtc->base.dev;
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9118 tmp = I915_READ(PF_CTL(crtc->pipe));
9120 if (tmp & PF_ENABLE) {
9121 pipe_config->pch_pfit.enabled = true;
9122 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9123 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9125 /* We currently do not free assignements of panel fitters on
9126 * ivb/hsw (since we don't use the higher upscaling modes which
9127 * differentiates them) so just WARN about this case for now. */
9129 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9130 PF_PIPE_SEL_IVB(crtc->pipe));
9136 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9137 struct intel_initial_plane_config *plane_config)
9139 struct drm_device *dev = crtc->base.dev;
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 u32 val, base, offset;
9142 int pipe = crtc->pipe;
9143 int fourcc, pixel_format;
9144 unsigned int aligned_height;
9145 struct drm_framebuffer *fb;
9146 struct intel_framebuffer *intel_fb;
9148 val = I915_READ(DSPCNTR(pipe));
9149 if (!(val & DISPLAY_PLANE_ENABLE))
9152 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9154 DRM_DEBUG_KMS("failed to alloc fb\n");
9158 fb = &intel_fb->base;
9160 if (INTEL_INFO(dev)->gen >= 4) {
9161 if (val & DISPPLANE_TILED) {
9162 plane_config->tiling = I915_TILING_X;
9163 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9167 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9168 fourcc = i9xx_format_to_fourcc(pixel_format);
9169 fb->pixel_format = fourcc;
9170 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9172 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9173 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9174 offset = I915_READ(DSPOFFSET(pipe));
9176 if (plane_config->tiling)
9177 offset = I915_READ(DSPTILEOFF(pipe));
9179 offset = I915_READ(DSPLINOFF(pipe));
9181 plane_config->base = base;
9183 val = I915_READ(PIPESRC(pipe));
9184 fb->width = ((val >> 16) & 0xfff) + 1;
9185 fb->height = ((val >> 0) & 0xfff) + 1;
9187 val = I915_READ(DSPSTRIDE(pipe));
9188 fb->pitches[0] = val & 0xffffffc0;
9190 aligned_height = intel_fb_align_height(dev, fb->height,
9194 plane_config->size = fb->pitches[0] * aligned_height;
9196 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9197 pipe_name(pipe), fb->width, fb->height,
9198 fb->bits_per_pixel, base, fb->pitches[0],
9199 plane_config->size);
9201 plane_config->fb = intel_fb;
9204 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9205 struct intel_crtc_state *pipe_config)
9207 struct drm_device *dev = crtc->base.dev;
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9211 if (!intel_display_power_is_enabled(dev_priv,
9212 POWER_DOMAIN_PIPE(crtc->pipe)))
9215 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9216 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9218 tmp = I915_READ(PIPECONF(crtc->pipe));
9219 if (!(tmp & PIPECONF_ENABLE))
9222 switch (tmp & PIPECONF_BPC_MASK) {
9224 pipe_config->pipe_bpp = 18;
9227 pipe_config->pipe_bpp = 24;
9229 case PIPECONF_10BPC:
9230 pipe_config->pipe_bpp = 30;
9232 case PIPECONF_12BPC:
9233 pipe_config->pipe_bpp = 36;
9239 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9240 pipe_config->limited_color_range = true;
9242 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9243 struct intel_shared_dpll *pll;
9245 pipe_config->has_pch_encoder = true;
9247 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9248 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9249 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9251 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9253 if (HAS_PCH_IBX(dev_priv->dev)) {
9254 pipe_config->shared_dpll =
9255 (enum intel_dpll_id) crtc->pipe;
9257 tmp = I915_READ(PCH_DPLL_SEL);
9258 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9259 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9261 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9264 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9266 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9267 &pipe_config->dpll_hw_state));
9269 tmp = pipe_config->dpll_hw_state.dpll;
9270 pipe_config->pixel_multiplier =
9271 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9272 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9274 ironlake_pch_clock_get(crtc, pipe_config);
9276 pipe_config->pixel_multiplier = 1;
9279 intel_get_pipe_timings(crtc, pipe_config);
9281 ironlake_get_pfit_config(crtc, pipe_config);
9286 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9288 struct drm_device *dev = dev_priv->dev;
9289 struct intel_crtc *crtc;
9291 for_each_intel_crtc(dev, crtc)
9292 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9293 pipe_name(crtc->pipe));
9295 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9296 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9297 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9298 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9299 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9300 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9301 "CPU PWM1 enabled\n");
9302 if (IS_HASWELL(dev))
9303 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9304 "CPU PWM2 enabled\n");
9305 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9306 "PCH PWM1 enabled\n");
9307 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9308 "Utility pin enabled\n");
9309 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9312 * In theory we can still leave IRQs enabled, as long as only the HPD
9313 * interrupts remain enabled. We used to check for that, but since it's
9314 * gen-specific and since we only disable LCPLL after we fully disable
9315 * the interrupts, the check below should be enough.
9317 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9320 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9322 struct drm_device *dev = dev_priv->dev;
9324 if (IS_HASWELL(dev))
9325 return I915_READ(D_COMP_HSW);
9327 return I915_READ(D_COMP_BDW);
9330 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9332 struct drm_device *dev = dev_priv->dev;
9334 if (IS_HASWELL(dev)) {
9335 mutex_lock(&dev_priv->rps.hw_lock);
9336 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9338 DRM_ERROR("Failed to write to D_COMP\n");
9339 mutex_unlock(&dev_priv->rps.hw_lock);
9341 I915_WRITE(D_COMP_BDW, val);
9342 POSTING_READ(D_COMP_BDW);
9347 * This function implements pieces of two sequences from BSpec:
9348 * - Sequence for display software to disable LCPLL
9349 * - Sequence for display software to allow package C8+
9350 * The steps implemented here are just the steps that actually touch the LCPLL
9351 * register. Callers should take care of disabling all the display engine
9352 * functions, doing the mode unset, fixing interrupts, etc.
9354 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9355 bool switch_to_fclk, bool allow_power_down)
9359 assert_can_disable_lcpll(dev_priv);
9361 val = I915_READ(LCPLL_CTL);
9363 if (switch_to_fclk) {
9364 val |= LCPLL_CD_SOURCE_FCLK;
9365 I915_WRITE(LCPLL_CTL, val);
9367 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9368 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9369 DRM_ERROR("Switching to FCLK failed\n");
9371 val = I915_READ(LCPLL_CTL);
9374 val |= LCPLL_PLL_DISABLE;
9375 I915_WRITE(LCPLL_CTL, val);
9376 POSTING_READ(LCPLL_CTL);
9378 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9379 DRM_ERROR("LCPLL still locked\n");
9381 val = hsw_read_dcomp(dev_priv);
9382 val |= D_COMP_COMP_DISABLE;
9383 hsw_write_dcomp(dev_priv, val);
9386 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9388 DRM_ERROR("D_COMP RCOMP still in progress\n");
9390 if (allow_power_down) {
9391 val = I915_READ(LCPLL_CTL);
9392 val |= LCPLL_POWER_DOWN_ALLOW;
9393 I915_WRITE(LCPLL_CTL, val);
9394 POSTING_READ(LCPLL_CTL);
9399 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9402 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9406 val = I915_READ(LCPLL_CTL);
9408 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9409 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9413 * Make sure we're not on PC8 state before disabling PC8, otherwise
9414 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9416 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9418 if (val & LCPLL_POWER_DOWN_ALLOW) {
9419 val &= ~LCPLL_POWER_DOWN_ALLOW;
9420 I915_WRITE(LCPLL_CTL, val);
9421 POSTING_READ(LCPLL_CTL);
9424 val = hsw_read_dcomp(dev_priv);
9425 val |= D_COMP_COMP_FORCE;
9426 val &= ~D_COMP_COMP_DISABLE;
9427 hsw_write_dcomp(dev_priv, val);
9429 val = I915_READ(LCPLL_CTL);
9430 val &= ~LCPLL_PLL_DISABLE;
9431 I915_WRITE(LCPLL_CTL, val);
9433 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9434 DRM_ERROR("LCPLL not locked yet\n");
9436 if (val & LCPLL_CD_SOURCE_FCLK) {
9437 val = I915_READ(LCPLL_CTL);
9438 val &= ~LCPLL_CD_SOURCE_FCLK;
9439 I915_WRITE(LCPLL_CTL, val);
9441 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9442 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9443 DRM_ERROR("Switching back to LCPLL failed\n");
9446 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9447 intel_update_cdclk(dev_priv->dev);
9451 * Package states C8 and deeper are really deep PC states that can only be
9452 * reached when all the devices on the system allow it, so even if the graphics
9453 * device allows PC8+, it doesn't mean the system will actually get to these
9454 * states. Our driver only allows PC8+ when going into runtime PM.
9456 * The requirements for PC8+ are that all the outputs are disabled, the power
9457 * well is disabled and most interrupts are disabled, and these are also
9458 * requirements for runtime PM. When these conditions are met, we manually do
9459 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9460 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9463 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9464 * the state of some registers, so when we come back from PC8+ we need to
9465 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9466 * need to take care of the registers kept by RC6. Notice that this happens even
9467 * if we don't put the device in PCI D3 state (which is what currently happens
9468 * because of the runtime PM support).
9470 * For more, read "Display Sequences for Package C8" on the hardware
9473 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9475 struct drm_device *dev = dev_priv->dev;
9478 DRM_DEBUG_KMS("Enabling package C8+\n");
9480 if (HAS_PCH_LPT_LP(dev)) {
9481 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9482 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9483 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9486 lpt_disable_clkout_dp(dev);
9487 hsw_disable_lcpll(dev_priv, true, true);
9490 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9492 struct drm_device *dev = dev_priv->dev;
9495 DRM_DEBUG_KMS("Disabling package C8+\n");
9497 hsw_restore_lcpll(dev_priv);
9498 lpt_init_pch_refclk(dev);
9500 if (HAS_PCH_LPT_LP(dev)) {
9501 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9502 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9506 intel_prepare_ddi(dev);
9509 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9511 struct drm_device *dev = old_state->dev;
9512 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9514 broxton_set_cdclk(dev, req_cdclk);
9517 /* compute the max rate for new configuration */
9518 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9520 struct intel_crtc *intel_crtc;
9521 struct intel_crtc_state *crtc_state;
9522 int max_pixel_rate = 0;
9524 for_each_intel_crtc(state->dev, intel_crtc) {
9527 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9528 if (IS_ERR(crtc_state))
9529 return PTR_ERR(crtc_state);
9531 if (!crtc_state->base.enable)
9534 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9536 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9537 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9538 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9540 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9543 return max_pixel_rate;
9546 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9548 struct drm_i915_private *dev_priv = dev->dev_private;
9552 if (WARN((I915_READ(LCPLL_CTL) &
9553 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9554 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9555 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9556 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9557 "trying to change cdclk frequency with cdclk not enabled\n"))
9560 mutex_lock(&dev_priv->rps.hw_lock);
9561 ret = sandybridge_pcode_write(dev_priv,
9562 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9563 mutex_unlock(&dev_priv->rps.hw_lock);
9565 DRM_ERROR("failed to inform pcode about cdclk change\n");
9569 val = I915_READ(LCPLL_CTL);
9570 val |= LCPLL_CD_SOURCE_FCLK;
9571 I915_WRITE(LCPLL_CTL, val);
9573 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9574 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9575 DRM_ERROR("Switching to FCLK failed\n");
9577 val = I915_READ(LCPLL_CTL);
9578 val &= ~LCPLL_CLK_FREQ_MASK;
9582 val |= LCPLL_CLK_FREQ_450;
9586 val |= LCPLL_CLK_FREQ_54O_BDW;
9590 val |= LCPLL_CLK_FREQ_337_5_BDW;
9594 val |= LCPLL_CLK_FREQ_675_BDW;
9598 WARN(1, "invalid cdclk frequency\n");
9602 I915_WRITE(LCPLL_CTL, val);
9604 val = I915_READ(LCPLL_CTL);
9605 val &= ~LCPLL_CD_SOURCE_FCLK;
9606 I915_WRITE(LCPLL_CTL, val);
9608 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9609 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9610 DRM_ERROR("Switching back to LCPLL failed\n");
9612 mutex_lock(&dev_priv->rps.hw_lock);
9613 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9614 mutex_unlock(&dev_priv->rps.hw_lock);
9616 intel_update_cdclk(dev);
9618 WARN(cdclk != dev_priv->cdclk_freq,
9619 "cdclk requested %d kHz but got %d kHz\n",
9620 cdclk, dev_priv->cdclk_freq);
9623 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9625 struct drm_i915_private *dev_priv = to_i915(state->dev);
9626 int max_pixclk = ilk_max_pixel_rate(state);
9630 * FIXME should also account for plane ratio
9631 * once 64bpp pixel formats are supported.
9633 if (max_pixclk > 540000)
9635 else if (max_pixclk > 450000)
9637 else if (max_pixclk > 337500)
9643 * FIXME move the cdclk caclulation to
9644 * compute_config() so we can fail gracegully.
9646 if (cdclk > dev_priv->max_cdclk_freq) {
9647 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9648 cdclk, dev_priv->max_cdclk_freq);
9649 cdclk = dev_priv->max_cdclk_freq;
9652 to_intel_atomic_state(state)->cdclk = cdclk;
9657 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9659 struct drm_device *dev = old_state->dev;
9660 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9662 broadwell_set_cdclk(dev, req_cdclk);
9665 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9666 struct intel_crtc_state *crtc_state)
9668 if (!intel_ddi_pll_select(crtc, crtc_state))
9671 crtc->lowfreq_avail = false;
9676 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9678 struct intel_crtc_state *pipe_config)
9682 pipe_config->ddi_pll_sel = SKL_DPLL0;
9683 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9686 pipe_config->ddi_pll_sel = SKL_DPLL1;
9687 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9690 pipe_config->ddi_pll_sel = SKL_DPLL2;
9691 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9694 DRM_ERROR("Incorrect port type\n");
9698 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9700 struct intel_crtc_state *pipe_config)
9702 u32 temp, dpll_ctl1;
9704 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9705 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9707 switch (pipe_config->ddi_pll_sel) {
9710 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9711 * of the shared DPLL framework and thus needs to be read out
9714 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9715 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9718 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9721 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9724 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9729 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9731 struct intel_crtc_state *pipe_config)
9733 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9735 switch (pipe_config->ddi_pll_sel) {
9736 case PORT_CLK_SEL_WRPLL1:
9737 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9739 case PORT_CLK_SEL_WRPLL2:
9740 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9745 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9746 struct intel_crtc_state *pipe_config)
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
9750 struct intel_shared_dpll *pll;
9754 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9756 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9758 if (IS_SKYLAKE(dev))
9759 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9760 else if (IS_BROXTON(dev))
9761 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9763 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9765 if (pipe_config->shared_dpll >= 0) {
9766 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9768 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9769 &pipe_config->dpll_hw_state));
9773 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9774 * DDI E. So just check whether this pipe is wired to DDI E and whether
9775 * the PCH transcoder is on.
9777 if (INTEL_INFO(dev)->gen < 9 &&
9778 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9779 pipe_config->has_pch_encoder = true;
9781 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9782 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9783 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9785 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9789 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9790 struct intel_crtc_state *pipe_config)
9792 struct drm_device *dev = crtc->base.dev;
9793 struct drm_i915_private *dev_priv = dev->dev_private;
9794 enum intel_display_power_domain pfit_domain;
9797 if (!intel_display_power_is_enabled(dev_priv,
9798 POWER_DOMAIN_PIPE(crtc->pipe)))
9801 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9802 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9804 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9805 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9806 enum pipe trans_edp_pipe;
9807 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9809 WARN(1, "unknown pipe linked to edp transcoder\n");
9810 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9811 case TRANS_DDI_EDP_INPUT_A_ON:
9812 trans_edp_pipe = PIPE_A;
9814 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9815 trans_edp_pipe = PIPE_B;
9817 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9818 trans_edp_pipe = PIPE_C;
9822 if (trans_edp_pipe == crtc->pipe)
9823 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9826 if (!intel_display_power_is_enabled(dev_priv,
9827 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9830 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9831 if (!(tmp & PIPECONF_ENABLE))
9834 haswell_get_ddi_port_state(crtc, pipe_config);
9836 intel_get_pipe_timings(crtc, pipe_config);
9838 if (INTEL_INFO(dev)->gen >= 9) {
9839 skl_init_scalers(dev, crtc, pipe_config);
9842 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9844 if (INTEL_INFO(dev)->gen >= 9) {
9845 pipe_config->scaler_state.scaler_id = -1;
9846 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9849 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9850 if (INTEL_INFO(dev)->gen >= 9)
9851 skylake_get_pfit_config(crtc, pipe_config);
9853 ironlake_get_pfit_config(crtc, pipe_config);
9856 if (IS_HASWELL(dev))
9857 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9858 (I915_READ(IPS_CTL) & IPS_ENABLE);
9860 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9861 pipe_config->pixel_multiplier =
9862 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9864 pipe_config->pixel_multiplier = 1;
9870 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9872 struct drm_device *dev = crtc->dev;
9873 struct drm_i915_private *dev_priv = dev->dev_private;
9874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9875 uint32_t cntl = 0, size = 0;
9878 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9879 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9880 unsigned int stride = roundup_pow_of_two(width) * 4;
9884 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9895 cntl |= CURSOR_ENABLE |
9896 CURSOR_GAMMA_ENABLE |
9897 CURSOR_FORMAT_ARGB |
9898 CURSOR_STRIDE(stride);
9900 size = (height << 12) | width;
9903 if (intel_crtc->cursor_cntl != 0 &&
9904 (intel_crtc->cursor_base != base ||
9905 intel_crtc->cursor_size != size ||
9906 intel_crtc->cursor_cntl != cntl)) {
9907 /* On these chipsets we can only modify the base/size/stride
9908 * whilst the cursor is disabled.
9910 I915_WRITE(CURCNTR(PIPE_A), 0);
9911 POSTING_READ(CURCNTR(PIPE_A));
9912 intel_crtc->cursor_cntl = 0;
9915 if (intel_crtc->cursor_base != base) {
9916 I915_WRITE(CURBASE(PIPE_A), base);
9917 intel_crtc->cursor_base = base;
9920 if (intel_crtc->cursor_size != size) {
9921 I915_WRITE(CURSIZE, size);
9922 intel_crtc->cursor_size = size;
9925 if (intel_crtc->cursor_cntl != cntl) {
9926 I915_WRITE(CURCNTR(PIPE_A), cntl);
9927 POSTING_READ(CURCNTR(PIPE_A));
9928 intel_crtc->cursor_cntl = cntl;
9932 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9934 struct drm_device *dev = crtc->dev;
9935 struct drm_i915_private *dev_priv = dev->dev_private;
9936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9937 int pipe = intel_crtc->pipe;
9942 cntl = MCURSOR_GAMMA_ENABLE;
9943 switch (intel_crtc->base.cursor->state->crtc_w) {
9945 cntl |= CURSOR_MODE_64_ARGB_AX;
9948 cntl |= CURSOR_MODE_128_ARGB_AX;
9951 cntl |= CURSOR_MODE_256_ARGB_AX;
9954 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9957 cntl |= pipe << 28; /* Connect to correct pipe */
9959 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9960 cntl |= CURSOR_PIPE_CSC_ENABLE;
9963 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9964 cntl |= CURSOR_ROTATE_180;
9966 if (intel_crtc->cursor_cntl != cntl) {
9967 I915_WRITE(CURCNTR(pipe), cntl);
9968 POSTING_READ(CURCNTR(pipe));
9969 intel_crtc->cursor_cntl = cntl;
9972 /* and commit changes on next vblank */
9973 I915_WRITE(CURBASE(pipe), base);
9974 POSTING_READ(CURBASE(pipe));
9976 intel_crtc->cursor_base = base;
9979 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9980 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9983 struct drm_device *dev = crtc->dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986 int pipe = intel_crtc->pipe;
9987 struct drm_plane_state *cursor_state = crtc->cursor->state;
9988 int x = cursor_state->crtc_x;
9989 int y = cursor_state->crtc_y;
9990 u32 base = 0, pos = 0;
9993 base = intel_crtc->cursor_addr;
9995 if (x >= intel_crtc->config->pipe_src_w)
9998 if (y >= intel_crtc->config->pipe_src_h)
10002 if (x + cursor_state->crtc_w <= 0)
10005 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10008 pos |= x << CURSOR_X_SHIFT;
10011 if (y + cursor_state->crtc_h <= 0)
10014 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10017 pos |= y << CURSOR_Y_SHIFT;
10019 if (base == 0 && intel_crtc->cursor_base == 0)
10022 I915_WRITE(CURPOS(pipe), pos);
10024 /* ILK+ do this automagically */
10025 if (HAS_GMCH_DISPLAY(dev) &&
10026 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10027 base += (cursor_state->crtc_h *
10028 cursor_state->crtc_w - 1) * 4;
10031 if (IS_845G(dev) || IS_I865G(dev))
10032 i845_update_cursor(crtc, base);
10034 i9xx_update_cursor(crtc, base);
10037 static bool cursor_size_ok(struct drm_device *dev,
10038 uint32_t width, uint32_t height)
10040 if (width == 0 || height == 0)
10044 * 845g/865g are special in that they are only limited by
10045 * the width of their cursors, the height is arbitrary up to
10046 * the precision of the register. Everything else requires
10047 * square cursors, limited to a few power-of-two sizes.
10049 if (IS_845G(dev) || IS_I865G(dev)) {
10050 if ((width & 63) != 0)
10053 if (width > (IS_845G(dev) ? 64 : 512))
10059 switch (width | height) {
10074 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10075 u16 *blue, uint32_t start, uint32_t size)
10077 int end = (start + size > 256) ? 256 : start + size, i;
10078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10080 for (i = start; i < end; i++) {
10081 intel_crtc->lut_r[i] = red[i] >> 8;
10082 intel_crtc->lut_g[i] = green[i] >> 8;
10083 intel_crtc->lut_b[i] = blue[i] >> 8;
10086 intel_crtc_load_lut(crtc);
10089 /* VESA 640x480x72Hz mode to set on the pipe */
10090 static struct drm_display_mode load_detect_mode = {
10091 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10092 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10095 struct drm_framebuffer *
10096 __intel_framebuffer_create(struct drm_device *dev,
10097 struct drm_mode_fb_cmd2 *mode_cmd,
10098 struct drm_i915_gem_object *obj)
10100 struct intel_framebuffer *intel_fb;
10103 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10105 drm_gem_object_unreference(&obj->base);
10106 return ERR_PTR(-ENOMEM);
10109 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10113 return &intel_fb->base;
10115 drm_gem_object_unreference(&obj->base);
10118 return ERR_PTR(ret);
10121 static struct drm_framebuffer *
10122 intel_framebuffer_create(struct drm_device *dev,
10123 struct drm_mode_fb_cmd2 *mode_cmd,
10124 struct drm_i915_gem_object *obj)
10126 struct drm_framebuffer *fb;
10129 ret = i915_mutex_lock_interruptible(dev);
10131 return ERR_PTR(ret);
10132 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10133 mutex_unlock(&dev->struct_mutex);
10139 intel_framebuffer_pitch_for_width(int width, int bpp)
10141 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10142 return ALIGN(pitch, 64);
10146 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10148 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10149 return PAGE_ALIGN(pitch * mode->vdisplay);
10152 static struct drm_framebuffer *
10153 intel_framebuffer_create_for_mode(struct drm_device *dev,
10154 struct drm_display_mode *mode,
10155 int depth, int bpp)
10157 struct drm_i915_gem_object *obj;
10158 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10160 obj = i915_gem_alloc_object(dev,
10161 intel_framebuffer_size_for_mode(mode, bpp));
10163 return ERR_PTR(-ENOMEM);
10165 mode_cmd.width = mode->hdisplay;
10166 mode_cmd.height = mode->vdisplay;
10167 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10169 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10171 return intel_framebuffer_create(dev, &mode_cmd, obj);
10174 static struct drm_framebuffer *
10175 mode_fits_in_fbdev(struct drm_device *dev,
10176 struct drm_display_mode *mode)
10178 #ifdef CONFIG_DRM_FBDEV_EMULATION
10179 struct drm_i915_private *dev_priv = dev->dev_private;
10180 struct drm_i915_gem_object *obj;
10181 struct drm_framebuffer *fb;
10183 if (!dev_priv->fbdev)
10186 if (!dev_priv->fbdev->fb)
10189 obj = dev_priv->fbdev->fb->obj;
10192 fb = &dev_priv->fbdev->fb->base;
10193 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10194 fb->bits_per_pixel))
10197 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10206 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10207 struct drm_crtc *crtc,
10208 struct drm_display_mode *mode,
10209 struct drm_framebuffer *fb,
10212 struct drm_plane_state *plane_state;
10213 int hdisplay, vdisplay;
10216 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10217 if (IS_ERR(plane_state))
10218 return PTR_ERR(plane_state);
10221 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10223 hdisplay = vdisplay = 0;
10225 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10228 drm_atomic_set_fb_for_plane(plane_state, fb);
10229 plane_state->crtc_x = 0;
10230 plane_state->crtc_y = 0;
10231 plane_state->crtc_w = hdisplay;
10232 plane_state->crtc_h = vdisplay;
10233 plane_state->src_x = x << 16;
10234 plane_state->src_y = y << 16;
10235 plane_state->src_w = hdisplay << 16;
10236 plane_state->src_h = vdisplay << 16;
10241 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10242 struct drm_display_mode *mode,
10243 struct intel_load_detect_pipe *old,
10244 struct drm_modeset_acquire_ctx *ctx)
10246 struct intel_crtc *intel_crtc;
10247 struct intel_encoder *intel_encoder =
10248 intel_attached_encoder(connector);
10249 struct drm_crtc *possible_crtc;
10250 struct drm_encoder *encoder = &intel_encoder->base;
10251 struct drm_crtc *crtc = NULL;
10252 struct drm_device *dev = encoder->dev;
10253 struct drm_framebuffer *fb;
10254 struct drm_mode_config *config = &dev->mode_config;
10255 struct drm_atomic_state *state = NULL;
10256 struct drm_connector_state *connector_state;
10257 struct intel_crtc_state *crtc_state;
10260 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10261 connector->base.id, connector->name,
10262 encoder->base.id, encoder->name);
10265 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10270 * Algorithm gets a little messy:
10272 * - if the connector already has an assigned crtc, use it (but make
10273 * sure it's on first)
10275 * - try to find the first unused crtc that can drive this connector,
10276 * and use that if we find one
10279 /* See if we already have a CRTC for this connector */
10280 if (encoder->crtc) {
10281 crtc = encoder->crtc;
10283 ret = drm_modeset_lock(&crtc->mutex, ctx);
10286 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10290 old->dpms_mode = connector->dpms;
10291 old->load_detect_temp = false;
10293 /* Make sure the crtc and connector are running */
10294 if (connector->dpms != DRM_MODE_DPMS_ON)
10295 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10300 /* Find an unused one (if possible) */
10301 for_each_crtc(dev, possible_crtc) {
10303 if (!(encoder->possible_crtcs & (1 << i)))
10305 if (possible_crtc->state->enable)
10308 crtc = possible_crtc;
10313 * If we didn't find an unused CRTC, don't use any.
10316 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10320 ret = drm_modeset_lock(&crtc->mutex, ctx);
10323 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10327 intel_crtc = to_intel_crtc(crtc);
10328 old->dpms_mode = connector->dpms;
10329 old->load_detect_temp = true;
10330 old->release_fb = NULL;
10332 state = drm_atomic_state_alloc(dev);
10336 state->acquire_ctx = ctx;
10338 connector_state = drm_atomic_get_connector_state(state, connector);
10339 if (IS_ERR(connector_state)) {
10340 ret = PTR_ERR(connector_state);
10344 connector_state->crtc = crtc;
10345 connector_state->best_encoder = &intel_encoder->base;
10347 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10348 if (IS_ERR(crtc_state)) {
10349 ret = PTR_ERR(crtc_state);
10353 crtc_state->base.active = crtc_state->base.enable = true;
10356 mode = &load_detect_mode;
10358 /* We need a framebuffer large enough to accommodate all accesses
10359 * that the plane may generate whilst we perform load detection.
10360 * We can not rely on the fbcon either being present (we get called
10361 * during its initialisation to detect all boot displays, or it may
10362 * not even exist) or that it is large enough to satisfy the
10365 fb = mode_fits_in_fbdev(dev, mode);
10367 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10368 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10369 old->release_fb = fb;
10371 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10373 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10377 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10381 drm_mode_copy(&crtc_state->base.mode, mode);
10383 if (drm_atomic_commit(state)) {
10384 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10385 if (old->release_fb)
10386 old->release_fb->funcs->destroy(old->release_fb);
10389 crtc->primary->crtc = crtc;
10391 /* let the connector get through one full cycle before testing */
10392 intel_wait_for_vblank(dev, intel_crtc->pipe);
10396 drm_atomic_state_free(state);
10399 if (ret == -EDEADLK) {
10400 drm_modeset_backoff(ctx);
10407 void intel_release_load_detect_pipe(struct drm_connector *connector,
10408 struct intel_load_detect_pipe *old,
10409 struct drm_modeset_acquire_ctx *ctx)
10411 struct drm_device *dev = connector->dev;
10412 struct intel_encoder *intel_encoder =
10413 intel_attached_encoder(connector);
10414 struct drm_encoder *encoder = &intel_encoder->base;
10415 struct drm_crtc *crtc = encoder->crtc;
10416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10417 struct drm_atomic_state *state;
10418 struct drm_connector_state *connector_state;
10419 struct intel_crtc_state *crtc_state;
10422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10423 connector->base.id, connector->name,
10424 encoder->base.id, encoder->name);
10426 if (old->load_detect_temp) {
10427 state = drm_atomic_state_alloc(dev);
10431 state->acquire_ctx = ctx;
10433 connector_state = drm_atomic_get_connector_state(state, connector);
10434 if (IS_ERR(connector_state))
10437 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10438 if (IS_ERR(crtc_state))
10441 connector_state->best_encoder = NULL;
10442 connector_state->crtc = NULL;
10444 crtc_state->base.enable = crtc_state->base.active = false;
10446 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10451 ret = drm_atomic_commit(state);
10455 if (old->release_fb) {
10456 drm_framebuffer_unregister_private(old->release_fb);
10457 drm_framebuffer_unreference(old->release_fb);
10463 /* Switch crtc and encoder back off if necessary */
10464 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10465 connector->funcs->dpms(connector, old->dpms_mode);
10469 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10470 drm_atomic_state_free(state);
10473 static int i9xx_pll_refclk(struct drm_device *dev,
10474 const struct intel_crtc_state *pipe_config)
10476 struct drm_i915_private *dev_priv = dev->dev_private;
10477 u32 dpll = pipe_config->dpll_hw_state.dpll;
10479 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10480 return dev_priv->vbt.lvds_ssc_freq;
10481 else if (HAS_PCH_SPLIT(dev))
10483 else if (!IS_GEN2(dev))
10489 /* Returns the clock of the currently programmed mode of the given pipe. */
10490 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10491 struct intel_crtc_state *pipe_config)
10493 struct drm_device *dev = crtc->base.dev;
10494 struct drm_i915_private *dev_priv = dev->dev_private;
10495 int pipe = pipe_config->cpu_transcoder;
10496 u32 dpll = pipe_config->dpll_hw_state.dpll;
10498 intel_clock_t clock;
10500 int refclk = i9xx_pll_refclk(dev, pipe_config);
10502 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10503 fp = pipe_config->dpll_hw_state.fp0;
10505 fp = pipe_config->dpll_hw_state.fp1;
10507 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10508 if (IS_PINEVIEW(dev)) {
10509 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10510 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10512 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10513 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10516 if (!IS_GEN2(dev)) {
10517 if (IS_PINEVIEW(dev))
10518 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10519 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10521 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10522 DPLL_FPA01_P1_POST_DIV_SHIFT);
10524 switch (dpll & DPLL_MODE_MASK) {
10525 case DPLLB_MODE_DAC_SERIAL:
10526 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10529 case DPLLB_MODE_LVDS:
10530 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10534 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10535 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10539 if (IS_PINEVIEW(dev))
10540 port_clock = pnv_calc_dpll_params(refclk, &clock);
10542 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10544 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10545 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10548 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10549 DPLL_FPA01_P1_POST_DIV_SHIFT);
10551 if (lvds & LVDS_CLKB_POWER_UP)
10556 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10559 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10560 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10562 if (dpll & PLL_P2_DIVIDE_BY_4)
10568 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10572 * This value includes pixel_multiplier. We will use
10573 * port_clock to compute adjusted_mode.crtc_clock in the
10574 * encoder's get_config() function.
10576 pipe_config->port_clock = port_clock;
10579 int intel_dotclock_calculate(int link_freq,
10580 const struct intel_link_m_n *m_n)
10583 * The calculation for the data clock is:
10584 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10585 * But we want to avoid losing precison if possible, so:
10586 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10588 * and the link clock is simpler:
10589 * link_clock = (m * link_clock) / n
10595 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10598 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10599 struct intel_crtc_state *pipe_config)
10601 struct drm_device *dev = crtc->base.dev;
10603 /* read out port_clock from the DPLL */
10604 i9xx_crtc_clock_get(crtc, pipe_config);
10607 * This value does not include pixel_multiplier.
10608 * We will check that port_clock and adjusted_mode.crtc_clock
10609 * agree once we know their relationship in the encoder's
10610 * get_config() function.
10612 pipe_config->base.adjusted_mode.crtc_clock =
10613 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10614 &pipe_config->fdi_m_n);
10617 /** Returns the currently programmed mode of the given pipe. */
10618 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10619 struct drm_crtc *crtc)
10621 struct drm_i915_private *dev_priv = dev->dev_private;
10622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10624 struct drm_display_mode *mode;
10625 struct intel_crtc_state pipe_config;
10626 int htot = I915_READ(HTOTAL(cpu_transcoder));
10627 int hsync = I915_READ(HSYNC(cpu_transcoder));
10628 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10629 int vsync = I915_READ(VSYNC(cpu_transcoder));
10630 enum pipe pipe = intel_crtc->pipe;
10632 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10637 * Construct a pipe_config sufficient for getting the clock info
10638 * back out of crtc_clock_get.
10640 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10641 * to use a real value here instead.
10643 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10644 pipe_config.pixel_multiplier = 1;
10645 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10646 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10647 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10648 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10650 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10651 mode->hdisplay = (htot & 0xffff) + 1;
10652 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10653 mode->hsync_start = (hsync & 0xffff) + 1;
10654 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10655 mode->vdisplay = (vtot & 0xffff) + 1;
10656 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10657 mode->vsync_start = (vsync & 0xffff) + 1;
10658 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10660 drm_mode_set_name(mode);
10665 void intel_mark_busy(struct drm_device *dev)
10667 struct drm_i915_private *dev_priv = dev->dev_private;
10669 if (dev_priv->mm.busy)
10672 intel_runtime_pm_get(dev_priv);
10673 i915_update_gfx_val(dev_priv);
10674 if (INTEL_INFO(dev)->gen >= 6)
10675 gen6_rps_busy(dev_priv);
10676 dev_priv->mm.busy = true;
10679 void intel_mark_idle(struct drm_device *dev)
10681 struct drm_i915_private *dev_priv = dev->dev_private;
10683 if (!dev_priv->mm.busy)
10686 dev_priv->mm.busy = false;
10688 if (INTEL_INFO(dev)->gen >= 6)
10689 gen6_rps_idle(dev->dev_private);
10691 intel_runtime_pm_put(dev_priv);
10694 static void intel_crtc_destroy(struct drm_crtc *crtc)
10696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10697 struct drm_device *dev = crtc->dev;
10698 struct intel_unpin_work *work;
10700 spin_lock_irq(&dev->event_lock);
10701 work = intel_crtc->unpin_work;
10702 intel_crtc->unpin_work = NULL;
10703 spin_unlock_irq(&dev->event_lock);
10706 cancel_work_sync(&work->work);
10710 drm_crtc_cleanup(crtc);
10715 static void intel_unpin_work_fn(struct work_struct *__work)
10717 struct intel_unpin_work *work =
10718 container_of(__work, struct intel_unpin_work, work);
10719 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10720 struct drm_device *dev = crtc->base.dev;
10721 struct drm_plane *primary = crtc->base.primary;
10723 mutex_lock(&dev->struct_mutex);
10724 intel_unpin_fb_obj(work->old_fb, primary->state);
10725 drm_gem_object_unreference(&work->pending_flip_obj->base);
10727 if (work->flip_queued_req)
10728 i915_gem_request_assign(&work->flip_queued_req, NULL);
10729 mutex_unlock(&dev->struct_mutex);
10731 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10732 drm_framebuffer_unreference(work->old_fb);
10734 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10735 atomic_dec(&crtc->unpin_work_count);
10740 static void do_intel_finish_page_flip(struct drm_device *dev,
10741 struct drm_crtc *crtc)
10743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10744 struct intel_unpin_work *work;
10745 unsigned long flags;
10747 /* Ignore early vblank irqs */
10748 if (intel_crtc == NULL)
10752 * This is called both by irq handlers and the reset code (to complete
10753 * lost pageflips) so needs the full irqsave spinlocks.
10755 spin_lock_irqsave(&dev->event_lock, flags);
10756 work = intel_crtc->unpin_work;
10758 /* Ensure we don't miss a work->pending update ... */
10761 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10762 spin_unlock_irqrestore(&dev->event_lock, flags);
10766 page_flip_completed(intel_crtc);
10768 spin_unlock_irqrestore(&dev->event_lock, flags);
10771 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10773 struct drm_i915_private *dev_priv = dev->dev_private;
10774 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10776 do_intel_finish_page_flip(dev, crtc);
10779 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10781 struct drm_i915_private *dev_priv = dev->dev_private;
10782 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10784 do_intel_finish_page_flip(dev, crtc);
10787 /* Is 'a' after or equal to 'b'? */
10788 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10790 return !((a - b) & 0x80000000);
10793 static bool page_flip_finished(struct intel_crtc *crtc)
10795 struct drm_device *dev = crtc->base.dev;
10796 struct drm_i915_private *dev_priv = dev->dev_private;
10798 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10799 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10803 * The relevant registers doen't exist on pre-ctg.
10804 * As the flip done interrupt doesn't trigger for mmio
10805 * flips on gmch platforms, a flip count check isn't
10806 * really needed there. But since ctg has the registers,
10807 * include it in the check anyway.
10809 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10813 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10814 * used the same base address. In that case the mmio flip might
10815 * have completed, but the CS hasn't even executed the flip yet.
10817 * A flip count check isn't enough as the CS might have updated
10818 * the base address just after start of vblank, but before we
10819 * managed to process the interrupt. This means we'd complete the
10820 * CS flip too soon.
10822 * Combining both checks should get us a good enough result. It may
10823 * still happen that the CS flip has been executed, but has not
10824 * yet actually completed. But in case the base address is the same
10825 * anyway, we don't really care.
10827 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10828 crtc->unpin_work->gtt_offset &&
10829 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10830 crtc->unpin_work->flip_count);
10833 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10835 struct drm_i915_private *dev_priv = dev->dev_private;
10836 struct intel_crtc *intel_crtc =
10837 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10838 unsigned long flags;
10842 * This is called both by irq handlers and the reset code (to complete
10843 * lost pageflips) so needs the full irqsave spinlocks.
10845 * NB: An MMIO update of the plane base pointer will also
10846 * generate a page-flip completion irq, i.e. every modeset
10847 * is also accompanied by a spurious intel_prepare_page_flip().
10849 spin_lock_irqsave(&dev->event_lock, flags);
10850 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10851 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10852 spin_unlock_irqrestore(&dev->event_lock, flags);
10855 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10857 /* Ensure that the work item is consistent when activating it ... */
10859 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10860 /* and that it is marked active as soon as the irq could fire. */
10864 static int intel_gen2_queue_flip(struct drm_device *dev,
10865 struct drm_crtc *crtc,
10866 struct drm_framebuffer *fb,
10867 struct drm_i915_gem_object *obj,
10868 struct drm_i915_gem_request *req,
10871 struct intel_engine_cs *ring = req->ring;
10872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10876 ret = intel_ring_begin(req, 6);
10880 /* Can't queue multiple flips, so wait for the previous
10881 * one to finish before executing the next.
10883 if (intel_crtc->plane)
10884 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10886 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10887 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10888 intel_ring_emit(ring, MI_NOOP);
10889 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10890 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10891 intel_ring_emit(ring, fb->pitches[0]);
10892 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10893 intel_ring_emit(ring, 0); /* aux display base address, unused */
10895 intel_mark_page_flip_active(intel_crtc);
10899 static int intel_gen3_queue_flip(struct drm_device *dev,
10900 struct drm_crtc *crtc,
10901 struct drm_framebuffer *fb,
10902 struct drm_i915_gem_object *obj,
10903 struct drm_i915_gem_request *req,
10906 struct intel_engine_cs *ring = req->ring;
10907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10911 ret = intel_ring_begin(req, 6);
10915 if (intel_crtc->plane)
10916 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10918 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10919 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10920 intel_ring_emit(ring, MI_NOOP);
10921 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10922 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10923 intel_ring_emit(ring, fb->pitches[0]);
10924 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10925 intel_ring_emit(ring, MI_NOOP);
10927 intel_mark_page_flip_active(intel_crtc);
10931 static int intel_gen4_queue_flip(struct drm_device *dev,
10932 struct drm_crtc *crtc,
10933 struct drm_framebuffer *fb,
10934 struct drm_i915_gem_object *obj,
10935 struct drm_i915_gem_request *req,
10938 struct intel_engine_cs *ring = req->ring;
10939 struct drm_i915_private *dev_priv = dev->dev_private;
10940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10941 uint32_t pf, pipesrc;
10944 ret = intel_ring_begin(req, 4);
10948 /* i965+ uses the linear or tiled offsets from the
10949 * Display Registers (which do not change across a page-flip)
10950 * so we need only reprogram the base address.
10952 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10953 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10954 intel_ring_emit(ring, fb->pitches[0]);
10955 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10958 /* XXX Enabling the panel-fitter across page-flip is so far
10959 * untested on non-native modes, so ignore it for now.
10960 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10963 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10964 intel_ring_emit(ring, pf | pipesrc);
10966 intel_mark_page_flip_active(intel_crtc);
10970 static int intel_gen6_queue_flip(struct drm_device *dev,
10971 struct drm_crtc *crtc,
10972 struct drm_framebuffer *fb,
10973 struct drm_i915_gem_object *obj,
10974 struct drm_i915_gem_request *req,
10977 struct intel_engine_cs *ring = req->ring;
10978 struct drm_i915_private *dev_priv = dev->dev_private;
10979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10980 uint32_t pf, pipesrc;
10983 ret = intel_ring_begin(req, 4);
10987 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10988 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10989 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10990 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10992 /* Contrary to the suggestions in the documentation,
10993 * "Enable Panel Fitter" does not seem to be required when page
10994 * flipping with a non-native mode, and worse causes a normal
10996 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10999 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11000 intel_ring_emit(ring, pf | pipesrc);
11002 intel_mark_page_flip_active(intel_crtc);
11006 static int intel_gen7_queue_flip(struct drm_device *dev,
11007 struct drm_crtc *crtc,
11008 struct drm_framebuffer *fb,
11009 struct drm_i915_gem_object *obj,
11010 struct drm_i915_gem_request *req,
11013 struct intel_engine_cs *ring = req->ring;
11014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11015 uint32_t plane_bit = 0;
11018 switch (intel_crtc->plane) {
11020 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11023 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11026 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11029 WARN_ONCE(1, "unknown plane in flip command\n");
11034 if (ring->id == RCS) {
11037 * On Gen 8, SRM is now taking an extra dword to accommodate
11038 * 48bits addresses, and we need a NOOP for the batch size to
11046 * BSpec MI_DISPLAY_FLIP for IVB:
11047 * "The full packet must be contained within the same cache line."
11049 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11050 * cacheline, if we ever start emitting more commands before
11051 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11052 * then do the cacheline alignment, and finally emit the
11055 ret = intel_ring_cacheline_align(req);
11059 ret = intel_ring_begin(req, len);
11063 /* Unmask the flip-done completion message. Note that the bspec says that
11064 * we should do this for both the BCS and RCS, and that we must not unmask
11065 * more than one flip event at any time (or ensure that one flip message
11066 * can be sent by waiting for flip-done prior to queueing new flips).
11067 * Experimentation says that BCS works despite DERRMR masking all
11068 * flip-done completion events and that unmasking all planes at once
11069 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11070 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11072 if (ring->id == RCS) {
11073 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11074 intel_ring_emit(ring, DERRMR);
11075 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11076 DERRMR_PIPEB_PRI_FLIP_DONE |
11077 DERRMR_PIPEC_PRI_FLIP_DONE));
11079 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11080 MI_SRM_LRM_GLOBAL_GTT);
11082 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11083 MI_SRM_LRM_GLOBAL_GTT);
11084 intel_ring_emit(ring, DERRMR);
11085 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11086 if (IS_GEN8(dev)) {
11087 intel_ring_emit(ring, 0);
11088 intel_ring_emit(ring, MI_NOOP);
11092 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11093 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11094 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11095 intel_ring_emit(ring, (MI_NOOP));
11097 intel_mark_page_flip_active(intel_crtc);
11101 static bool use_mmio_flip(struct intel_engine_cs *ring,
11102 struct drm_i915_gem_object *obj)
11105 * This is not being used for older platforms, because
11106 * non-availability of flip done interrupt forces us to use
11107 * CS flips. Older platforms derive flip done using some clever
11108 * tricks involving the flip_pending status bits and vblank irqs.
11109 * So using MMIO flips there would disrupt this mechanism.
11115 if (INTEL_INFO(ring->dev)->gen < 5)
11118 if (i915.use_mmio_flip < 0)
11120 else if (i915.use_mmio_flip > 0)
11122 else if (i915.enable_execlists)
11125 return ring != i915_gem_request_get_ring(obj->last_write_req);
11128 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11130 struct drm_device *dev = intel_crtc->base.dev;
11131 struct drm_i915_private *dev_priv = dev->dev_private;
11132 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11133 const enum pipe pipe = intel_crtc->pipe;
11136 ctl = I915_READ(PLANE_CTL(pipe, 0));
11137 ctl &= ~PLANE_CTL_TILED_MASK;
11138 switch (fb->modifier[0]) {
11139 case DRM_FORMAT_MOD_NONE:
11141 case I915_FORMAT_MOD_X_TILED:
11142 ctl |= PLANE_CTL_TILED_X;
11144 case I915_FORMAT_MOD_Y_TILED:
11145 ctl |= PLANE_CTL_TILED_Y;
11147 case I915_FORMAT_MOD_Yf_TILED:
11148 ctl |= PLANE_CTL_TILED_YF;
11151 MISSING_CASE(fb->modifier[0]);
11155 * The stride is either expressed as a multiple of 64 bytes chunks for
11156 * linear buffers or in number of tiles for tiled buffers.
11158 stride = fb->pitches[0] /
11159 intel_fb_stride_alignment(dev, fb->modifier[0],
11163 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11164 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11166 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11167 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11169 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11170 POSTING_READ(PLANE_SURF(pipe, 0));
11173 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11175 struct drm_device *dev = intel_crtc->base.dev;
11176 struct drm_i915_private *dev_priv = dev->dev_private;
11177 struct intel_framebuffer *intel_fb =
11178 to_intel_framebuffer(intel_crtc->base.primary->fb);
11179 struct drm_i915_gem_object *obj = intel_fb->obj;
11183 reg = DSPCNTR(intel_crtc->plane);
11184 dspcntr = I915_READ(reg);
11186 if (obj->tiling_mode != I915_TILING_NONE)
11187 dspcntr |= DISPPLANE_TILED;
11189 dspcntr &= ~DISPPLANE_TILED;
11191 I915_WRITE(reg, dspcntr);
11193 I915_WRITE(DSPSURF(intel_crtc->plane),
11194 intel_crtc->unpin_work->gtt_offset);
11195 POSTING_READ(DSPSURF(intel_crtc->plane));
11200 * XXX: This is the temporary way to update the plane registers until we get
11201 * around to using the usual plane update functions for MMIO flips
11203 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11205 struct drm_device *dev = intel_crtc->base.dev;
11207 intel_mark_page_flip_active(intel_crtc);
11209 intel_pipe_update_start(intel_crtc);
11211 if (INTEL_INFO(dev)->gen >= 9)
11212 skl_do_mmio_flip(intel_crtc);
11214 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11215 ilk_do_mmio_flip(intel_crtc);
11217 intel_pipe_update_end(intel_crtc);
11220 static void intel_mmio_flip_work_func(struct work_struct *work)
11222 struct intel_mmio_flip *mmio_flip =
11223 container_of(work, struct intel_mmio_flip, work);
11225 if (mmio_flip->req)
11226 WARN_ON(__i915_wait_request(mmio_flip->req,
11227 mmio_flip->crtc->reset_counter,
11229 &mmio_flip->i915->rps.mmioflips));
11231 intel_do_mmio_flip(mmio_flip->crtc);
11233 i915_gem_request_unreference__unlocked(mmio_flip->req);
11237 static int intel_queue_mmio_flip(struct drm_device *dev,
11238 struct drm_crtc *crtc,
11239 struct drm_framebuffer *fb,
11240 struct drm_i915_gem_object *obj,
11241 struct intel_engine_cs *ring,
11244 struct intel_mmio_flip *mmio_flip;
11246 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11247 if (mmio_flip == NULL)
11250 mmio_flip->i915 = to_i915(dev);
11251 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11252 mmio_flip->crtc = to_intel_crtc(crtc);
11254 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11255 schedule_work(&mmio_flip->work);
11260 static int intel_default_queue_flip(struct drm_device *dev,
11261 struct drm_crtc *crtc,
11262 struct drm_framebuffer *fb,
11263 struct drm_i915_gem_object *obj,
11264 struct drm_i915_gem_request *req,
11270 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11271 struct drm_crtc *crtc)
11273 struct drm_i915_private *dev_priv = dev->dev_private;
11274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11275 struct intel_unpin_work *work = intel_crtc->unpin_work;
11278 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11281 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11284 if (!work->enable_stall_check)
11287 if (work->flip_ready_vblank == 0) {
11288 if (work->flip_queued_req &&
11289 !i915_gem_request_completed(work->flip_queued_req, true))
11292 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11295 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11298 /* Potential stall - if we see that the flip has happened,
11299 * assume a missed interrupt. */
11300 if (INTEL_INFO(dev)->gen >= 4)
11301 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11303 addr = I915_READ(DSPADDR(intel_crtc->plane));
11305 /* There is a potential issue here with a false positive after a flip
11306 * to the same address. We could address this by checking for a
11307 * non-incrementing frame counter.
11309 return addr == work->gtt_offset;
11312 void intel_check_page_flip(struct drm_device *dev, int pipe)
11314 struct drm_i915_private *dev_priv = dev->dev_private;
11315 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11317 struct intel_unpin_work *work;
11319 WARN_ON(!in_interrupt());
11324 spin_lock(&dev->event_lock);
11325 work = intel_crtc->unpin_work;
11326 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11327 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11328 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11329 page_flip_completed(intel_crtc);
11332 if (work != NULL &&
11333 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11334 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11335 spin_unlock(&dev->event_lock);
11338 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11339 struct drm_framebuffer *fb,
11340 struct drm_pending_vblank_event *event,
11341 uint32_t page_flip_flags)
11343 struct drm_device *dev = crtc->dev;
11344 struct drm_i915_private *dev_priv = dev->dev_private;
11345 struct drm_framebuffer *old_fb = crtc->primary->fb;
11346 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11348 struct drm_plane *primary = crtc->primary;
11349 enum pipe pipe = intel_crtc->pipe;
11350 struct intel_unpin_work *work;
11351 struct intel_engine_cs *ring;
11353 struct drm_i915_gem_request *request = NULL;
11357 * drm_mode_page_flip_ioctl() should already catch this, but double
11358 * check to be safe. In the future we may enable pageflipping from
11359 * a disabled primary plane.
11361 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11364 /* Can't change pixel format via MI display flips. */
11365 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11369 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11370 * Note that pitch changes could also affect these register.
11372 if (INTEL_INFO(dev)->gen > 3 &&
11373 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11374 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11377 if (i915_terminally_wedged(&dev_priv->gpu_error))
11380 work = kzalloc(sizeof(*work), GFP_KERNEL);
11384 work->event = event;
11386 work->old_fb = old_fb;
11387 INIT_WORK(&work->work, intel_unpin_work_fn);
11389 ret = drm_crtc_vblank_get(crtc);
11393 /* We borrow the event spin lock for protecting unpin_work */
11394 spin_lock_irq(&dev->event_lock);
11395 if (intel_crtc->unpin_work) {
11396 /* Before declaring the flip queue wedged, check if
11397 * the hardware completed the operation behind our backs.
11399 if (__intel_pageflip_stall_check(dev, crtc)) {
11400 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11401 page_flip_completed(intel_crtc);
11403 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11404 spin_unlock_irq(&dev->event_lock);
11406 drm_crtc_vblank_put(crtc);
11411 intel_crtc->unpin_work = work;
11412 spin_unlock_irq(&dev->event_lock);
11414 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11415 flush_workqueue(dev_priv->wq);
11417 /* Reference the objects for the scheduled work. */
11418 drm_framebuffer_reference(work->old_fb);
11419 drm_gem_object_reference(&obj->base);
11421 crtc->primary->fb = fb;
11422 update_state_fb(crtc->primary);
11424 work->pending_flip_obj = obj;
11426 ret = i915_mutex_lock_interruptible(dev);
11430 atomic_inc(&intel_crtc->unpin_work_count);
11431 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11433 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11434 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11436 if (IS_VALLEYVIEW(dev)) {
11437 ring = &dev_priv->ring[BCS];
11438 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11439 /* vlv: DISPLAY_FLIP fails to change tiling */
11441 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11442 ring = &dev_priv->ring[BCS];
11443 } else if (INTEL_INFO(dev)->gen >= 7) {
11444 ring = i915_gem_request_get_ring(obj->last_write_req);
11445 if (ring == NULL || ring->id != RCS)
11446 ring = &dev_priv->ring[BCS];
11448 ring = &dev_priv->ring[RCS];
11451 mmio_flip = use_mmio_flip(ring, obj);
11453 /* When using CS flips, we want to emit semaphores between rings.
11454 * However, when using mmio flips we will create a task to do the
11455 * synchronisation, so all we want here is to pin the framebuffer
11456 * into the display plane and skip any waits.
11458 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11459 crtc->primary->state,
11460 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11462 goto cleanup_pending;
11464 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11466 work->gtt_offset += intel_crtc->dspaddr_offset;
11469 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11472 goto cleanup_unpin;
11474 i915_gem_request_assign(&work->flip_queued_req,
11475 obj->last_write_req);
11478 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11480 goto cleanup_unpin;
11483 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11486 goto cleanup_unpin;
11488 i915_gem_request_assign(&work->flip_queued_req, request);
11492 i915_add_request_no_flush(request);
11494 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11495 work->enable_stall_check = true;
11497 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11498 to_intel_plane(primary)->frontbuffer_bit);
11499 mutex_unlock(&dev->struct_mutex);
11501 intel_fbc_disable_crtc(intel_crtc);
11502 intel_frontbuffer_flip_prepare(dev,
11503 to_intel_plane(primary)->frontbuffer_bit);
11505 trace_i915_flip_request(intel_crtc->plane, obj);
11510 intel_unpin_fb_obj(fb, crtc->primary->state);
11513 i915_gem_request_cancel(request);
11514 atomic_dec(&intel_crtc->unpin_work_count);
11515 mutex_unlock(&dev->struct_mutex);
11517 crtc->primary->fb = old_fb;
11518 update_state_fb(crtc->primary);
11520 drm_gem_object_unreference_unlocked(&obj->base);
11521 drm_framebuffer_unreference(work->old_fb);
11523 spin_lock_irq(&dev->event_lock);
11524 intel_crtc->unpin_work = NULL;
11525 spin_unlock_irq(&dev->event_lock);
11527 drm_crtc_vblank_put(crtc);
11532 struct drm_atomic_state *state;
11533 struct drm_plane_state *plane_state;
11536 state = drm_atomic_state_alloc(dev);
11539 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11542 plane_state = drm_atomic_get_plane_state(state, primary);
11543 ret = PTR_ERR_OR_ZERO(plane_state);
11545 drm_atomic_set_fb_for_plane(plane_state, fb);
11547 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11549 ret = drm_atomic_commit(state);
11552 if (ret == -EDEADLK) {
11553 drm_modeset_backoff(state->acquire_ctx);
11554 drm_atomic_state_clear(state);
11559 drm_atomic_state_free(state);
11561 if (ret == 0 && event) {
11562 spin_lock_irq(&dev->event_lock);
11563 drm_send_vblank_event(dev, pipe, event);
11564 spin_unlock_irq(&dev->event_lock);
11572 * intel_wm_need_update - Check whether watermarks need updating
11573 * @plane: drm plane
11574 * @state: new plane state
11576 * Check current plane state versus the new one to determine whether
11577 * watermarks need to be recalculated.
11579 * Returns true or false.
11581 static bool intel_wm_need_update(struct drm_plane *plane,
11582 struct drm_plane_state *state)
11584 /* Update watermarks on tiling changes. */
11585 if (!plane->state->fb || !state->fb ||
11586 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11587 plane->state->rotation != state->rotation)
11590 if (plane->state->crtc_w != state->crtc_w)
11596 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11597 struct drm_plane_state *plane_state)
11599 struct drm_crtc *crtc = crtc_state->crtc;
11600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11601 struct drm_plane *plane = plane_state->plane;
11602 struct drm_device *dev = crtc->dev;
11603 struct drm_i915_private *dev_priv = dev->dev_private;
11604 struct intel_plane_state *old_plane_state =
11605 to_intel_plane_state(plane->state);
11606 int idx = intel_crtc->base.base.id, ret;
11607 int i = drm_plane_index(plane);
11608 bool mode_changed = needs_modeset(crtc_state);
11609 bool was_crtc_enabled = crtc->state->active;
11610 bool is_crtc_enabled = crtc_state->active;
11612 bool turn_off, turn_on, visible, was_visible;
11613 struct drm_framebuffer *fb = plane_state->fb;
11615 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11616 plane->type != DRM_PLANE_TYPE_CURSOR) {
11617 ret = skl_update_scaler_plane(
11618 to_intel_crtc_state(crtc_state),
11619 to_intel_plane_state(plane_state));
11625 * Disabling a plane is always okay; we just need to update
11626 * fb tracking in a special way since cleanup_fb() won't
11627 * get called by the plane helpers.
11629 if (old_plane_state->base.fb && !fb)
11630 intel_crtc->atomic.disabled_planes |= 1 << i;
11632 was_visible = old_plane_state->visible;
11633 visible = to_intel_plane_state(plane_state)->visible;
11635 if (!was_crtc_enabled && WARN_ON(was_visible))
11636 was_visible = false;
11638 if (!is_crtc_enabled && WARN_ON(visible))
11641 if (!was_visible && !visible)
11644 turn_off = was_visible && (!visible || mode_changed);
11645 turn_on = visible && (!was_visible || mode_changed);
11647 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11648 plane->base.id, fb ? fb->base.id : -1);
11650 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11651 plane->base.id, was_visible, visible,
11652 turn_off, turn_on, mode_changed);
11655 intel_crtc->atomic.update_wm_pre = true;
11656 /* must disable cxsr around plane enable/disable */
11657 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11658 intel_crtc->atomic.disable_cxsr = true;
11659 /* to potentially re-enable cxsr */
11660 intel_crtc->atomic.wait_vblank = true;
11661 intel_crtc->atomic.update_wm_post = true;
11663 } else if (turn_off) {
11664 intel_crtc->atomic.update_wm_post = true;
11665 /* must disable cxsr around plane enable/disable */
11666 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11667 if (is_crtc_enabled)
11668 intel_crtc->atomic.wait_vblank = true;
11669 intel_crtc->atomic.disable_cxsr = true;
11671 } else if (intel_wm_need_update(plane, plane_state)) {
11672 intel_crtc->atomic.update_wm_pre = true;
11675 if (visible || was_visible)
11676 intel_crtc->atomic.fb_bits |=
11677 to_intel_plane(plane)->frontbuffer_bit;
11679 switch (plane->type) {
11680 case DRM_PLANE_TYPE_PRIMARY:
11681 intel_crtc->atomic.wait_for_flips = true;
11682 intel_crtc->atomic.pre_disable_primary = turn_off;
11683 intel_crtc->atomic.post_enable_primary = turn_on;
11687 * FIXME: Actually if we will still have any other
11688 * plane enabled on the pipe we could let IPS enabled
11689 * still, but for now lets consider that when we make
11690 * primary invisible by setting DSPCNTR to 0 on
11691 * update_primary_plane function IPS needs to be
11694 intel_crtc->atomic.disable_ips = true;
11696 intel_crtc->atomic.disable_fbc = true;
11700 * FBC does not work on some platforms for rotated
11701 * planes, so disable it when rotation is not 0 and
11702 * update it when rotation is set back to 0.
11704 * FIXME: This is redundant with the fbc update done in
11705 * the primary plane enable function except that that
11706 * one is done too late. We eventually need to unify
11711 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11712 dev_priv->fbc.crtc == intel_crtc &&
11713 plane_state->rotation != BIT(DRM_ROTATE_0))
11714 intel_crtc->atomic.disable_fbc = true;
11717 * BDW signals flip done immediately if the plane
11718 * is disabled, even if the plane enable is already
11719 * armed to occur at the next vblank :(
11721 if (turn_on && IS_BROADWELL(dev))
11722 intel_crtc->atomic.wait_vblank = true;
11724 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11726 case DRM_PLANE_TYPE_CURSOR:
11728 case DRM_PLANE_TYPE_OVERLAY:
11729 if (turn_off && !mode_changed) {
11730 intel_crtc->atomic.wait_vblank = true;
11731 intel_crtc->atomic.update_sprite_watermarks |=
11738 static bool encoders_cloneable(const struct intel_encoder *a,
11739 const struct intel_encoder *b)
11741 /* masks could be asymmetric, so check both ways */
11742 return a == b || (a->cloneable & (1 << b->type) &&
11743 b->cloneable & (1 << a->type));
11746 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11747 struct intel_crtc *crtc,
11748 struct intel_encoder *encoder)
11750 struct intel_encoder *source_encoder;
11751 struct drm_connector *connector;
11752 struct drm_connector_state *connector_state;
11755 for_each_connector_in_state(state, connector, connector_state, i) {
11756 if (connector_state->crtc != &crtc->base)
11760 to_intel_encoder(connector_state->best_encoder);
11761 if (!encoders_cloneable(encoder, source_encoder))
11768 static bool check_encoder_cloning(struct drm_atomic_state *state,
11769 struct intel_crtc *crtc)
11771 struct intel_encoder *encoder;
11772 struct drm_connector *connector;
11773 struct drm_connector_state *connector_state;
11776 for_each_connector_in_state(state, connector, connector_state, i) {
11777 if (connector_state->crtc != &crtc->base)
11780 encoder = to_intel_encoder(connector_state->best_encoder);
11781 if (!check_single_encoder_cloning(state, crtc, encoder))
11788 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11789 struct drm_crtc_state *crtc_state)
11791 struct drm_device *dev = crtc->dev;
11792 struct drm_i915_private *dev_priv = dev->dev_private;
11793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11794 struct intel_crtc_state *pipe_config =
11795 to_intel_crtc_state(crtc_state);
11796 struct drm_atomic_state *state = crtc_state->state;
11798 bool mode_changed = needs_modeset(crtc_state);
11800 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11801 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11805 if (mode_changed && !crtc_state->active)
11806 intel_crtc->atomic.update_wm_post = true;
11808 if (mode_changed && crtc_state->enable &&
11809 dev_priv->display.crtc_compute_clock &&
11810 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11811 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11818 if (INTEL_INFO(dev)->gen >= 9) {
11820 ret = skl_update_scaler_crtc(pipe_config);
11823 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11830 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11831 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11832 .load_lut = intel_crtc_load_lut,
11833 .atomic_begin = intel_begin_crtc_commit,
11834 .atomic_flush = intel_finish_crtc_commit,
11835 .atomic_check = intel_crtc_atomic_check,
11838 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11840 struct intel_connector *connector;
11842 for_each_intel_connector(dev, connector) {
11843 if (connector->base.encoder) {
11844 connector->base.state->best_encoder =
11845 connector->base.encoder;
11846 connector->base.state->crtc =
11847 connector->base.encoder->crtc;
11849 connector->base.state->best_encoder = NULL;
11850 connector->base.state->crtc = NULL;
11856 connected_sink_compute_bpp(struct intel_connector *connector,
11857 struct intel_crtc_state *pipe_config)
11859 int bpp = pipe_config->pipe_bpp;
11861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11862 connector->base.base.id,
11863 connector->base.name);
11865 /* Don't use an invalid EDID bpc value */
11866 if (connector->base.display_info.bpc &&
11867 connector->base.display_info.bpc * 3 < bpp) {
11868 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11869 bpp, connector->base.display_info.bpc*3);
11870 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11873 /* Clamp bpp to 8 on screens without EDID 1.4 */
11874 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11875 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11877 pipe_config->pipe_bpp = 24;
11882 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11883 struct intel_crtc_state *pipe_config)
11885 struct drm_device *dev = crtc->base.dev;
11886 struct drm_atomic_state *state;
11887 struct drm_connector *connector;
11888 struct drm_connector_state *connector_state;
11891 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11893 else if (INTEL_INFO(dev)->gen >= 5)
11899 pipe_config->pipe_bpp = bpp;
11901 state = pipe_config->base.state;
11903 /* Clamp display bpp to EDID value */
11904 for_each_connector_in_state(state, connector, connector_state, i) {
11905 if (connector_state->crtc != &crtc->base)
11908 connected_sink_compute_bpp(to_intel_connector(connector),
11915 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11917 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11918 "type: 0x%x flags: 0x%x\n",
11920 mode->crtc_hdisplay, mode->crtc_hsync_start,
11921 mode->crtc_hsync_end, mode->crtc_htotal,
11922 mode->crtc_vdisplay, mode->crtc_vsync_start,
11923 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11926 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11927 struct intel_crtc_state *pipe_config,
11928 const char *context)
11930 struct drm_device *dev = crtc->base.dev;
11931 struct drm_plane *plane;
11932 struct intel_plane *intel_plane;
11933 struct intel_plane_state *state;
11934 struct drm_framebuffer *fb;
11936 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11937 context, pipe_config, pipe_name(crtc->pipe));
11939 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11940 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11941 pipe_config->pipe_bpp, pipe_config->dither);
11942 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11943 pipe_config->has_pch_encoder,
11944 pipe_config->fdi_lanes,
11945 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11946 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11947 pipe_config->fdi_m_n.tu);
11948 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11949 pipe_config->has_dp_encoder,
11950 pipe_config->lane_count,
11951 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11952 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11953 pipe_config->dp_m_n.tu);
11955 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11956 pipe_config->has_dp_encoder,
11957 pipe_config->lane_count,
11958 pipe_config->dp_m2_n2.gmch_m,
11959 pipe_config->dp_m2_n2.gmch_n,
11960 pipe_config->dp_m2_n2.link_m,
11961 pipe_config->dp_m2_n2.link_n,
11962 pipe_config->dp_m2_n2.tu);
11964 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11965 pipe_config->has_audio,
11966 pipe_config->has_infoframe);
11968 DRM_DEBUG_KMS("requested mode:\n");
11969 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11970 DRM_DEBUG_KMS("adjusted mode:\n");
11971 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11972 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11973 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11974 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11975 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11976 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11978 pipe_config->scaler_state.scaler_users,
11979 pipe_config->scaler_state.scaler_id);
11980 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11981 pipe_config->gmch_pfit.control,
11982 pipe_config->gmch_pfit.pgm_ratios,
11983 pipe_config->gmch_pfit.lvds_border_bits);
11984 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11985 pipe_config->pch_pfit.pos,
11986 pipe_config->pch_pfit.size,
11987 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11988 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11989 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11991 if (IS_BROXTON(dev)) {
11992 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11993 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11994 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11995 pipe_config->ddi_pll_sel,
11996 pipe_config->dpll_hw_state.ebb0,
11997 pipe_config->dpll_hw_state.ebb4,
11998 pipe_config->dpll_hw_state.pll0,
11999 pipe_config->dpll_hw_state.pll1,
12000 pipe_config->dpll_hw_state.pll2,
12001 pipe_config->dpll_hw_state.pll3,
12002 pipe_config->dpll_hw_state.pll6,
12003 pipe_config->dpll_hw_state.pll8,
12004 pipe_config->dpll_hw_state.pll9,
12005 pipe_config->dpll_hw_state.pll10,
12006 pipe_config->dpll_hw_state.pcsdw12);
12007 } else if (IS_SKYLAKE(dev)) {
12008 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12009 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12010 pipe_config->ddi_pll_sel,
12011 pipe_config->dpll_hw_state.ctrl1,
12012 pipe_config->dpll_hw_state.cfgcr1,
12013 pipe_config->dpll_hw_state.cfgcr2);
12014 } else if (HAS_DDI(dev)) {
12015 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12016 pipe_config->ddi_pll_sel,
12017 pipe_config->dpll_hw_state.wrpll);
12019 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12020 "fp0: 0x%x, fp1: 0x%x\n",
12021 pipe_config->dpll_hw_state.dpll,
12022 pipe_config->dpll_hw_state.dpll_md,
12023 pipe_config->dpll_hw_state.fp0,
12024 pipe_config->dpll_hw_state.fp1);
12027 DRM_DEBUG_KMS("planes on this crtc\n");
12028 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12029 intel_plane = to_intel_plane(plane);
12030 if (intel_plane->pipe != crtc->pipe)
12033 state = to_intel_plane_state(plane->state);
12034 fb = state->base.fb;
12036 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12037 "disabled, scaler_id = %d\n",
12038 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12039 plane->base.id, intel_plane->pipe,
12040 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12041 drm_plane_index(plane), state->scaler_id);
12045 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12046 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12047 plane->base.id, intel_plane->pipe,
12048 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12049 drm_plane_index(plane));
12050 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12051 fb->base.id, fb->width, fb->height, fb->pixel_format);
12052 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12054 state->src.x1 >> 16, state->src.y1 >> 16,
12055 drm_rect_width(&state->src) >> 16,
12056 drm_rect_height(&state->src) >> 16,
12057 state->dst.x1, state->dst.y1,
12058 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12062 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12064 struct drm_device *dev = state->dev;
12065 struct intel_encoder *encoder;
12066 struct drm_connector *connector;
12067 struct drm_connector_state *connector_state;
12068 unsigned int used_ports = 0;
12072 * Walk the connector list instead of the encoder
12073 * list to detect the problem on ddi platforms
12074 * where there's just one encoder per digital port.
12076 for_each_connector_in_state(state, connector, connector_state, i) {
12077 if (!connector_state->best_encoder)
12080 encoder = to_intel_encoder(connector_state->best_encoder);
12082 WARN_ON(!connector_state->crtc);
12084 switch (encoder->type) {
12085 unsigned int port_mask;
12086 case INTEL_OUTPUT_UNKNOWN:
12087 if (WARN_ON(!HAS_DDI(dev)))
12089 case INTEL_OUTPUT_DISPLAYPORT:
12090 case INTEL_OUTPUT_HDMI:
12091 case INTEL_OUTPUT_EDP:
12092 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12094 /* the same port mustn't appear more than once */
12095 if (used_ports & port_mask)
12098 used_ports |= port_mask;
12108 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12110 struct drm_crtc_state tmp_state;
12111 struct intel_crtc_scaler_state scaler_state;
12112 struct intel_dpll_hw_state dpll_hw_state;
12113 enum intel_dpll_id shared_dpll;
12114 uint32_t ddi_pll_sel;
12117 /* FIXME: before the switch to atomic started, a new pipe_config was
12118 * kzalloc'd. Code that depends on any field being zero should be
12119 * fixed, so that the crtc_state can be safely duplicated. For now,
12120 * only fields that are know to not cause problems are preserved. */
12122 tmp_state = crtc_state->base;
12123 scaler_state = crtc_state->scaler_state;
12124 shared_dpll = crtc_state->shared_dpll;
12125 dpll_hw_state = crtc_state->dpll_hw_state;
12126 ddi_pll_sel = crtc_state->ddi_pll_sel;
12127 force_thru = crtc_state->pch_pfit.force_thru;
12129 memset(crtc_state, 0, sizeof *crtc_state);
12131 crtc_state->base = tmp_state;
12132 crtc_state->scaler_state = scaler_state;
12133 crtc_state->shared_dpll = shared_dpll;
12134 crtc_state->dpll_hw_state = dpll_hw_state;
12135 crtc_state->ddi_pll_sel = ddi_pll_sel;
12136 crtc_state->pch_pfit.force_thru = force_thru;
12140 intel_modeset_pipe_config(struct drm_crtc *crtc,
12141 struct intel_crtc_state *pipe_config)
12143 struct drm_atomic_state *state = pipe_config->base.state;
12144 struct intel_encoder *encoder;
12145 struct drm_connector *connector;
12146 struct drm_connector_state *connector_state;
12147 int base_bpp, ret = -EINVAL;
12151 clear_intel_crtc_state(pipe_config);
12153 pipe_config->cpu_transcoder =
12154 (enum transcoder) to_intel_crtc(crtc)->pipe;
12157 * Sanitize sync polarity flags based on requested ones. If neither
12158 * positive or negative polarity is requested, treat this as meaning
12159 * negative polarity.
12161 if (!(pipe_config->base.adjusted_mode.flags &
12162 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12163 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12165 if (!(pipe_config->base.adjusted_mode.flags &
12166 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12167 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12169 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12175 * Determine the real pipe dimensions. Note that stereo modes can
12176 * increase the actual pipe size due to the frame doubling and
12177 * insertion of additional space for blanks between the frame. This
12178 * is stored in the crtc timings. We use the requested mode to do this
12179 * computation to clearly distinguish it from the adjusted mode, which
12180 * can be changed by the connectors in the below retry loop.
12182 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12183 &pipe_config->pipe_src_w,
12184 &pipe_config->pipe_src_h);
12187 /* Ensure the port clock defaults are reset when retrying. */
12188 pipe_config->port_clock = 0;
12189 pipe_config->pixel_multiplier = 1;
12191 /* Fill in default crtc timings, allow encoders to overwrite them. */
12192 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12193 CRTC_STEREO_DOUBLE);
12195 /* Pass our mode to the connectors and the CRTC to give them a chance to
12196 * adjust it according to limitations or connector properties, and also
12197 * a chance to reject the mode entirely.
12199 for_each_connector_in_state(state, connector, connector_state, i) {
12200 if (connector_state->crtc != crtc)
12203 encoder = to_intel_encoder(connector_state->best_encoder);
12205 if (!(encoder->compute_config(encoder, pipe_config))) {
12206 DRM_DEBUG_KMS("Encoder config failure\n");
12211 /* Set default port clock if not overwritten by the encoder. Needs to be
12212 * done afterwards in case the encoder adjusts the mode. */
12213 if (!pipe_config->port_clock)
12214 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12215 * pipe_config->pixel_multiplier;
12217 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12219 DRM_DEBUG_KMS("CRTC fixup failed\n");
12223 if (ret == RETRY) {
12224 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12229 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12231 goto encoder_retry;
12234 /* Dithering seems to not pass-through bits correctly when it should, so
12235 * only enable it on 6bpc panels. */
12236 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12237 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12238 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12245 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12247 struct drm_crtc *crtc;
12248 struct drm_crtc_state *crtc_state;
12251 /* Double check state. */
12252 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12253 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12255 /* Update hwmode for vblank functions */
12256 if (crtc->state->active)
12257 crtc->hwmode = crtc->state->adjusted_mode;
12259 crtc->hwmode.crtc_clock = 0;
12263 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12267 if (clock1 == clock2)
12270 if (!clock1 || !clock2)
12273 diff = abs(clock1 - clock2);
12275 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12281 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12282 list_for_each_entry((intel_crtc), \
12283 &(dev)->mode_config.crtc_list, \
12285 if (mask & (1 <<(intel_crtc)->pipe))
12288 intel_compare_m_n(unsigned int m, unsigned int n,
12289 unsigned int m2, unsigned int n2,
12292 if (m == m2 && n == n2)
12295 if (exact || !m || !n || !m2 || !n2)
12298 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12305 } else if (m < m2) {
12312 return m == m2 && n == n2;
12316 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12317 struct intel_link_m_n *m2_n2,
12320 if (m_n->tu == m2_n2->tu &&
12321 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12322 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12323 intel_compare_m_n(m_n->link_m, m_n->link_n,
12324 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12335 intel_pipe_config_compare(struct drm_device *dev,
12336 struct intel_crtc_state *current_config,
12337 struct intel_crtc_state *pipe_config,
12342 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12345 DRM_ERROR(fmt, ##__VA_ARGS__); \
12347 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12350 #define PIPE_CONF_CHECK_X(name) \
12351 if (current_config->name != pipe_config->name) { \
12352 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353 "(expected 0x%08x, found 0x%08x)\n", \
12354 current_config->name, \
12355 pipe_config->name); \
12359 #define PIPE_CONF_CHECK_I(name) \
12360 if (current_config->name != pipe_config->name) { \
12361 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12362 "(expected %i, found %i)\n", \
12363 current_config->name, \
12364 pipe_config->name); \
12368 #define PIPE_CONF_CHECK_M_N(name) \
12369 if (!intel_compare_link_m_n(¤t_config->name, \
12370 &pipe_config->name,\
12372 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12373 "(expected tu %i gmch %i/%i link %i/%i, " \
12374 "found tu %i, gmch %i/%i link %i/%i)\n", \
12375 current_config->name.tu, \
12376 current_config->name.gmch_m, \
12377 current_config->name.gmch_n, \
12378 current_config->name.link_m, \
12379 current_config->name.link_n, \
12380 pipe_config->name.tu, \
12381 pipe_config->name.gmch_m, \
12382 pipe_config->name.gmch_n, \
12383 pipe_config->name.link_m, \
12384 pipe_config->name.link_n); \
12388 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12389 if (!intel_compare_link_m_n(¤t_config->name, \
12390 &pipe_config->name, adjust) && \
12391 !intel_compare_link_m_n(¤t_config->alt_name, \
12392 &pipe_config->name, adjust)) { \
12393 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12394 "(expected tu %i gmch %i/%i link %i/%i, " \
12395 "or tu %i gmch %i/%i link %i/%i, " \
12396 "found tu %i, gmch %i/%i link %i/%i)\n", \
12397 current_config->name.tu, \
12398 current_config->name.gmch_m, \
12399 current_config->name.gmch_n, \
12400 current_config->name.link_m, \
12401 current_config->name.link_n, \
12402 current_config->alt_name.tu, \
12403 current_config->alt_name.gmch_m, \
12404 current_config->alt_name.gmch_n, \
12405 current_config->alt_name.link_m, \
12406 current_config->alt_name.link_n, \
12407 pipe_config->name.tu, \
12408 pipe_config->name.gmch_m, \
12409 pipe_config->name.gmch_n, \
12410 pipe_config->name.link_m, \
12411 pipe_config->name.link_n); \
12415 /* This is required for BDW+ where there is only one set of registers for
12416 * switching between high and low RR.
12417 * This macro can be used whenever a comparison has to be made between one
12418 * hw state and multiple sw state variables.
12420 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12421 if ((current_config->name != pipe_config->name) && \
12422 (current_config->alt_name != pipe_config->name)) { \
12423 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12424 "(expected %i or %i, found %i)\n", \
12425 current_config->name, \
12426 current_config->alt_name, \
12427 pipe_config->name); \
12431 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12432 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12433 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12434 "(expected %i, found %i)\n", \
12435 current_config->name & (mask), \
12436 pipe_config->name & (mask)); \
12440 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12441 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12442 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12443 "(expected %i, found %i)\n", \
12444 current_config->name, \
12445 pipe_config->name); \
12449 #define PIPE_CONF_QUIRK(quirk) \
12450 ((current_config->quirks | pipe_config->quirks) & (quirk))
12452 PIPE_CONF_CHECK_I(cpu_transcoder);
12454 PIPE_CONF_CHECK_I(has_pch_encoder);
12455 PIPE_CONF_CHECK_I(fdi_lanes);
12456 PIPE_CONF_CHECK_M_N(fdi_m_n);
12458 PIPE_CONF_CHECK_I(has_dp_encoder);
12459 PIPE_CONF_CHECK_I(lane_count);
12461 if (INTEL_INFO(dev)->gen < 8) {
12462 PIPE_CONF_CHECK_M_N(dp_m_n);
12464 PIPE_CONF_CHECK_I(has_drrs);
12465 if (current_config->has_drrs)
12466 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12468 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12470 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12471 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12473 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12484 PIPE_CONF_CHECK_I(pixel_multiplier);
12485 PIPE_CONF_CHECK_I(has_hdmi_sink);
12486 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12487 IS_VALLEYVIEW(dev))
12488 PIPE_CONF_CHECK_I(limited_color_range);
12489 PIPE_CONF_CHECK_I(has_infoframe);
12491 PIPE_CONF_CHECK_I(has_audio);
12493 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12494 DRM_MODE_FLAG_INTERLACE);
12496 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12497 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12498 DRM_MODE_FLAG_PHSYNC);
12499 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12500 DRM_MODE_FLAG_NHSYNC);
12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12502 DRM_MODE_FLAG_PVSYNC);
12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12504 DRM_MODE_FLAG_NVSYNC);
12507 PIPE_CONF_CHECK_X(gmch_pfit.control);
12508 /* pfit ratios are autocomputed by the hw on gen4+ */
12509 if (INTEL_INFO(dev)->gen < 4)
12510 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12511 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12514 PIPE_CONF_CHECK_I(pipe_src_w);
12515 PIPE_CONF_CHECK_I(pipe_src_h);
12517 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12518 if (current_config->pch_pfit.enabled) {
12519 PIPE_CONF_CHECK_X(pch_pfit.pos);
12520 PIPE_CONF_CHECK_X(pch_pfit.size);
12523 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12526 /* BDW+ don't expose a synchronous way to read the state */
12527 if (IS_HASWELL(dev))
12528 PIPE_CONF_CHECK_I(ips_enabled);
12530 PIPE_CONF_CHECK_I(double_wide);
12532 PIPE_CONF_CHECK_X(ddi_pll_sel);
12534 PIPE_CONF_CHECK_I(shared_dpll);
12535 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12536 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12537 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12538 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12539 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12540 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12541 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12542 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12544 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12545 PIPE_CONF_CHECK_I(pipe_bpp);
12547 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12548 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12550 #undef PIPE_CONF_CHECK_X
12551 #undef PIPE_CONF_CHECK_I
12552 #undef PIPE_CONF_CHECK_I_ALT
12553 #undef PIPE_CONF_CHECK_FLAGS
12554 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12555 #undef PIPE_CONF_QUIRK
12556 #undef INTEL_ERR_OR_DBG_KMS
12561 static void check_wm_state(struct drm_device *dev)
12563 struct drm_i915_private *dev_priv = dev->dev_private;
12564 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12565 struct intel_crtc *intel_crtc;
12568 if (INTEL_INFO(dev)->gen < 9)
12571 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12572 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12574 for_each_intel_crtc(dev, intel_crtc) {
12575 struct skl_ddb_entry *hw_entry, *sw_entry;
12576 const enum pipe pipe = intel_crtc->pipe;
12578 if (!intel_crtc->active)
12582 for_each_plane(dev_priv, pipe, plane) {
12583 hw_entry = &hw_ddb.plane[pipe][plane];
12584 sw_entry = &sw_ddb->plane[pipe][plane];
12586 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12589 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12590 "(expected (%u,%u), found (%u,%u))\n",
12591 pipe_name(pipe), plane + 1,
12592 sw_entry->start, sw_entry->end,
12593 hw_entry->start, hw_entry->end);
12597 hw_entry = &hw_ddb.cursor[pipe];
12598 sw_entry = &sw_ddb->cursor[pipe];
12600 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12603 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12604 "(expected (%u,%u), found (%u,%u))\n",
12606 sw_entry->start, sw_entry->end,
12607 hw_entry->start, hw_entry->end);
12612 check_connector_state(struct drm_device *dev,
12613 struct drm_atomic_state *old_state)
12615 struct drm_connector_state *old_conn_state;
12616 struct drm_connector *connector;
12619 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12620 struct drm_encoder *encoder = connector->encoder;
12621 struct drm_connector_state *state = connector->state;
12623 /* This also checks the encoder/connector hw state with the
12624 * ->get_hw_state callbacks. */
12625 intel_connector_check_state(to_intel_connector(connector));
12627 I915_STATE_WARN(state->best_encoder != encoder,
12628 "connector's atomic encoder doesn't match legacy encoder\n");
12633 check_encoder_state(struct drm_device *dev)
12635 struct intel_encoder *encoder;
12636 struct intel_connector *connector;
12638 for_each_intel_encoder(dev, encoder) {
12639 bool enabled = false;
12642 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12643 encoder->base.base.id,
12644 encoder->base.name);
12646 for_each_intel_connector(dev, connector) {
12647 if (connector->base.state->best_encoder != &encoder->base)
12651 I915_STATE_WARN(connector->base.state->crtc !=
12652 encoder->base.crtc,
12653 "connector's crtc doesn't match encoder crtc\n");
12656 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12657 "encoder's enabled state mismatch "
12658 "(expected %i, found %i)\n",
12659 !!encoder->base.crtc, enabled);
12661 if (!encoder->base.crtc) {
12664 active = encoder->get_hw_state(encoder, &pipe);
12665 I915_STATE_WARN(active,
12666 "encoder detached but still enabled on pipe %c.\n",
12673 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12675 struct drm_i915_private *dev_priv = dev->dev_private;
12676 struct intel_encoder *encoder;
12677 struct drm_crtc_state *old_crtc_state;
12678 struct drm_crtc *crtc;
12681 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12683 struct intel_crtc_state *pipe_config, *sw_config;
12686 if (!needs_modeset(crtc->state) &&
12687 !to_intel_crtc_state(crtc->state)->update_pipe)
12690 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12691 pipe_config = to_intel_crtc_state(old_crtc_state);
12692 memset(pipe_config, 0, sizeof(*pipe_config));
12693 pipe_config->base.crtc = crtc;
12694 pipe_config->base.state = old_state;
12696 DRM_DEBUG_KMS("[CRTC:%d]\n",
12699 active = dev_priv->display.get_pipe_config(intel_crtc,
12702 /* hw state is inconsistent with the pipe quirk */
12703 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12704 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12705 active = crtc->state->active;
12707 I915_STATE_WARN(crtc->state->active != active,
12708 "crtc active state doesn't match with hw state "
12709 "(expected %i, found %i)\n", crtc->state->active, active);
12711 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12712 "transitional active state does not match atomic hw state "
12713 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12715 for_each_encoder_on_crtc(dev, crtc, encoder) {
12718 active = encoder->get_hw_state(encoder, &pipe);
12719 I915_STATE_WARN(active != crtc->state->active,
12720 "[ENCODER:%i] active %i with crtc active %i\n",
12721 encoder->base.base.id, active, crtc->state->active);
12723 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12724 "Encoder connected to wrong pipe %c\n",
12728 encoder->get_config(encoder, pipe_config);
12731 if (!crtc->state->active)
12734 sw_config = to_intel_crtc_state(crtc->state);
12735 if (!intel_pipe_config_compare(dev, sw_config,
12736 pipe_config, false)) {
12737 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12738 intel_dump_pipe_config(intel_crtc, pipe_config,
12740 intel_dump_pipe_config(intel_crtc, sw_config,
12747 check_shared_dpll_state(struct drm_device *dev)
12749 struct drm_i915_private *dev_priv = dev->dev_private;
12750 struct intel_crtc *crtc;
12751 struct intel_dpll_hw_state dpll_hw_state;
12754 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12755 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12756 int enabled_crtcs = 0, active_crtcs = 0;
12759 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12761 DRM_DEBUG_KMS("%s\n", pll->name);
12763 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12765 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12766 "more active pll users than references: %i vs %i\n",
12767 pll->active, hweight32(pll->config.crtc_mask));
12768 I915_STATE_WARN(pll->active && !pll->on,
12769 "pll in active use but not on in sw tracking\n");
12770 I915_STATE_WARN(pll->on && !pll->active,
12771 "pll in on but not on in use in sw tracking\n");
12772 I915_STATE_WARN(pll->on != active,
12773 "pll on state mismatch (expected %i, found %i)\n",
12776 for_each_intel_crtc(dev, crtc) {
12777 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12779 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12782 I915_STATE_WARN(pll->active != active_crtcs,
12783 "pll active crtcs mismatch (expected %i, found %i)\n",
12784 pll->active, active_crtcs);
12785 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12786 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12787 hweight32(pll->config.crtc_mask), enabled_crtcs);
12789 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12790 sizeof(dpll_hw_state)),
12791 "pll hw state mismatch\n");
12796 intel_modeset_check_state(struct drm_device *dev,
12797 struct drm_atomic_state *old_state)
12799 check_wm_state(dev);
12800 check_connector_state(dev, old_state);
12801 check_encoder_state(dev);
12802 check_crtc_state(dev, old_state);
12803 check_shared_dpll_state(dev);
12806 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12810 * FDI already provided one idea for the dotclock.
12811 * Yell if the encoder disagrees.
12813 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12814 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12815 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12818 static void update_scanline_offset(struct intel_crtc *crtc)
12820 struct drm_device *dev = crtc->base.dev;
12823 * The scanline counter increments at the leading edge of hsync.
12825 * On most platforms it starts counting from vtotal-1 on the
12826 * first active line. That means the scanline counter value is
12827 * always one less than what we would expect. Ie. just after
12828 * start of vblank, which also occurs at start of hsync (on the
12829 * last active line), the scanline counter will read vblank_start-1.
12831 * On gen2 the scanline counter starts counting from 1 instead
12832 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12833 * to keep the value positive), instead of adding one.
12835 * On HSW+ the behaviour of the scanline counter depends on the output
12836 * type. For DP ports it behaves like most other platforms, but on HDMI
12837 * there's an extra 1 line difference. So we need to add two instead of
12838 * one to the value.
12840 if (IS_GEN2(dev)) {
12841 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12844 vtotal = adjusted_mode->crtc_vtotal;
12845 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12848 crtc->scanline_offset = vtotal - 1;
12849 } else if (HAS_DDI(dev) &&
12850 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12851 crtc->scanline_offset = 2;
12853 crtc->scanline_offset = 1;
12856 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12858 struct drm_device *dev = state->dev;
12859 struct drm_i915_private *dev_priv = to_i915(dev);
12860 struct intel_shared_dpll_config *shared_dpll = NULL;
12861 struct intel_crtc *intel_crtc;
12862 struct intel_crtc_state *intel_crtc_state;
12863 struct drm_crtc *crtc;
12864 struct drm_crtc_state *crtc_state;
12867 if (!dev_priv->display.crtc_compute_clock)
12870 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12873 intel_crtc = to_intel_crtc(crtc);
12874 intel_crtc_state = to_intel_crtc_state(crtc_state);
12875 dpll = intel_crtc_state->shared_dpll;
12877 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12880 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12883 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12885 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12890 * This implements the workaround described in the "notes" section of the mode
12891 * set sequence documentation. When going from no pipes or single pipe to
12892 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12893 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12895 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12897 struct drm_crtc_state *crtc_state;
12898 struct intel_crtc *intel_crtc;
12899 struct drm_crtc *crtc;
12900 struct intel_crtc_state *first_crtc_state = NULL;
12901 struct intel_crtc_state *other_crtc_state = NULL;
12902 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12905 /* look at all crtc's that are going to be enabled in during modeset */
12906 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12907 intel_crtc = to_intel_crtc(crtc);
12909 if (!crtc_state->active || !needs_modeset(crtc_state))
12912 if (first_crtc_state) {
12913 other_crtc_state = to_intel_crtc_state(crtc_state);
12916 first_crtc_state = to_intel_crtc_state(crtc_state);
12917 first_pipe = intel_crtc->pipe;
12921 /* No workaround needed? */
12922 if (!first_crtc_state)
12925 /* w/a possibly needed, check how many crtc's are already enabled. */
12926 for_each_intel_crtc(state->dev, intel_crtc) {
12927 struct intel_crtc_state *pipe_config;
12929 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12930 if (IS_ERR(pipe_config))
12931 return PTR_ERR(pipe_config);
12933 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12935 if (!pipe_config->base.active ||
12936 needs_modeset(&pipe_config->base))
12939 /* 2 or more enabled crtcs means no need for w/a */
12940 if (enabled_pipe != INVALID_PIPE)
12943 enabled_pipe = intel_crtc->pipe;
12946 if (enabled_pipe != INVALID_PIPE)
12947 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12948 else if (other_crtc_state)
12949 other_crtc_state->hsw_workaround_pipe = first_pipe;
12954 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12956 struct drm_crtc *crtc;
12957 struct drm_crtc_state *crtc_state;
12960 /* add all active pipes to the state */
12961 for_each_crtc(state->dev, crtc) {
12962 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12963 if (IS_ERR(crtc_state))
12964 return PTR_ERR(crtc_state);
12966 if (!crtc_state->active || needs_modeset(crtc_state))
12969 crtc_state->mode_changed = true;
12971 ret = drm_atomic_add_affected_connectors(state, crtc);
12975 ret = drm_atomic_add_affected_planes(state, crtc);
12983 static int intel_modeset_checks(struct drm_atomic_state *state)
12985 struct drm_device *dev = state->dev;
12986 struct drm_i915_private *dev_priv = dev->dev_private;
12989 if (!check_digital_port_conflicts(state)) {
12990 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12995 * See if the config requires any additional preparation, e.g.
12996 * to adjust global state with pipes off. We need to do this
12997 * here so we can get the modeset_pipe updated config for the new
12998 * mode set on this crtc. For other crtcs we need to use the
12999 * adjusted_mode bits in the crtc directly.
13001 if (dev_priv->display.modeset_calc_cdclk) {
13002 unsigned int cdclk;
13004 ret = dev_priv->display.modeset_calc_cdclk(state);
13006 cdclk = to_intel_atomic_state(state)->cdclk;
13007 if (!ret && cdclk != dev_priv->cdclk_freq)
13008 ret = intel_modeset_all_pipes(state);
13013 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13015 intel_modeset_clear_plls(state);
13017 if (IS_HASWELL(dev))
13018 return haswell_mode_set_planes_workaround(state);
13024 * intel_atomic_check - validate state object
13026 * @state: state to validate
13028 static int intel_atomic_check(struct drm_device *dev,
13029 struct drm_atomic_state *state)
13031 struct drm_crtc *crtc;
13032 struct drm_crtc_state *crtc_state;
13034 bool any_ms = false;
13036 ret = drm_atomic_helper_check_modeset(dev, state);
13040 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13041 struct intel_crtc_state *pipe_config =
13042 to_intel_crtc_state(crtc_state);
13044 /* Catch I915_MODE_FLAG_INHERITED */
13045 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13046 crtc_state->mode_changed = true;
13048 if (!crtc_state->enable) {
13049 if (needs_modeset(crtc_state))
13054 if (!needs_modeset(crtc_state))
13057 /* FIXME: For only active_changed we shouldn't need to do any
13058 * state recomputation at all. */
13060 ret = drm_atomic_add_affected_connectors(state, crtc);
13064 ret = intel_modeset_pipe_config(crtc, pipe_config);
13068 if (intel_pipe_config_compare(state->dev,
13069 to_intel_crtc_state(crtc->state),
13070 pipe_config, true)) {
13071 crtc_state->mode_changed = false;
13072 to_intel_crtc_state(crtc_state)->update_pipe = true;
13075 if (needs_modeset(crtc_state)) {
13078 ret = drm_atomic_add_affected_planes(state, crtc);
13083 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13084 needs_modeset(crtc_state) ?
13085 "[modeset]" : "[fastset]");
13089 ret = intel_modeset_checks(state);
13094 to_intel_atomic_state(state)->cdclk =
13095 to_i915(state->dev)->cdclk_freq;
13097 return drm_atomic_helper_check_planes(state->dev, state);
13101 * intel_atomic_commit - commit validated state object
13103 * @state: the top-level driver state object
13104 * @async: asynchronous commit
13106 * This function commits a top-level state object that has been validated
13107 * with drm_atomic_helper_check().
13109 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13110 * we can only handle plane-related operations and do not yet support
13111 * asynchronous commit.
13114 * Zero for success or -errno.
13116 static int intel_atomic_commit(struct drm_device *dev,
13117 struct drm_atomic_state *state,
13120 struct drm_i915_private *dev_priv = dev->dev_private;
13121 struct drm_crtc *crtc;
13122 struct drm_crtc_state *crtc_state;
13125 bool any_ms = false;
13128 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13132 ret = drm_atomic_helper_prepare_planes(dev, state);
13136 drm_atomic_helper_swap_state(dev, state);
13138 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13141 if (!needs_modeset(crtc->state))
13145 intel_pre_plane_update(intel_crtc);
13147 if (crtc_state->active) {
13148 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13149 dev_priv->display.crtc_disable(crtc);
13150 intel_crtc->active = false;
13151 intel_disable_shared_dpll(intel_crtc);
13155 /* Only after disabling all output pipelines that will be changed can we
13156 * update the the output configuration. */
13157 intel_modeset_update_crtc_state(state);
13160 intel_shared_dpll_commit(state);
13162 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13163 modeset_update_crtc_power_domains(state);
13166 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13167 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13169 bool modeset = needs_modeset(crtc->state);
13170 bool update_pipe = !modeset &&
13171 to_intel_crtc_state(crtc->state)->update_pipe;
13172 unsigned long put_domains = 0;
13174 if (modeset && crtc->state->active) {
13175 update_scanline_offset(to_intel_crtc(crtc));
13176 dev_priv->display.crtc_enable(crtc);
13180 put_domains = modeset_get_crtc_power_domains(crtc);
13182 /* make sure intel_modeset_check_state runs */
13187 intel_pre_plane_update(intel_crtc);
13189 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13192 modeset_put_power_domains(dev_priv, put_domains);
13194 intel_post_plane_update(intel_crtc);
13197 /* FIXME: add subpixel order */
13199 drm_atomic_helper_wait_for_vblanks(dev, state);
13200 drm_atomic_helper_cleanup_planes(dev, state);
13203 intel_modeset_check_state(dev, state);
13205 drm_atomic_state_free(state);
13210 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13212 struct drm_device *dev = crtc->dev;
13213 struct drm_atomic_state *state;
13214 struct drm_crtc_state *crtc_state;
13217 state = drm_atomic_state_alloc(dev);
13219 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13224 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13227 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13228 ret = PTR_ERR_OR_ZERO(crtc_state);
13230 if (!crtc_state->active)
13233 crtc_state->mode_changed = true;
13234 ret = drm_atomic_commit(state);
13237 if (ret == -EDEADLK) {
13238 drm_atomic_state_clear(state);
13239 drm_modeset_backoff(state->acquire_ctx);
13245 drm_atomic_state_free(state);
13248 #undef for_each_intel_crtc_masked
13250 static const struct drm_crtc_funcs intel_crtc_funcs = {
13251 .gamma_set = intel_crtc_gamma_set,
13252 .set_config = drm_atomic_helper_set_config,
13253 .destroy = intel_crtc_destroy,
13254 .page_flip = intel_crtc_page_flip,
13255 .atomic_duplicate_state = intel_crtc_duplicate_state,
13256 .atomic_destroy_state = intel_crtc_destroy_state,
13259 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13260 struct intel_shared_dpll *pll,
13261 struct intel_dpll_hw_state *hw_state)
13265 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13268 val = I915_READ(PCH_DPLL(pll->id));
13269 hw_state->dpll = val;
13270 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13271 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13273 return val & DPLL_VCO_ENABLE;
13276 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13277 struct intel_shared_dpll *pll)
13279 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13280 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13283 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13284 struct intel_shared_dpll *pll)
13286 /* PCH refclock must be enabled first */
13287 ibx_assert_pch_refclk_enabled(dev_priv);
13289 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13291 /* Wait for the clocks to stabilize. */
13292 POSTING_READ(PCH_DPLL(pll->id));
13295 /* The pixel multiplier can only be updated once the
13296 * DPLL is enabled and the clocks are stable.
13298 * So write it again.
13300 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13301 POSTING_READ(PCH_DPLL(pll->id));
13305 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13306 struct intel_shared_dpll *pll)
13308 struct drm_device *dev = dev_priv->dev;
13309 struct intel_crtc *crtc;
13311 /* Make sure no transcoder isn't still depending on us. */
13312 for_each_intel_crtc(dev, crtc) {
13313 if (intel_crtc_to_shared_dpll(crtc) == pll)
13314 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13317 I915_WRITE(PCH_DPLL(pll->id), 0);
13318 POSTING_READ(PCH_DPLL(pll->id));
13322 static char *ibx_pch_dpll_names[] = {
13327 static void ibx_pch_dpll_init(struct drm_device *dev)
13329 struct drm_i915_private *dev_priv = dev->dev_private;
13332 dev_priv->num_shared_dpll = 2;
13334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13335 dev_priv->shared_dplls[i].id = i;
13336 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13337 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13338 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13339 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13340 dev_priv->shared_dplls[i].get_hw_state =
13341 ibx_pch_dpll_get_hw_state;
13345 static void intel_shared_dpll_init(struct drm_device *dev)
13347 struct drm_i915_private *dev_priv = dev->dev_private;
13350 intel_ddi_pll_init(dev);
13351 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13352 ibx_pch_dpll_init(dev);
13354 dev_priv->num_shared_dpll = 0;
13356 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13360 * intel_prepare_plane_fb - Prepare fb for usage on plane
13361 * @plane: drm plane to prepare for
13362 * @fb: framebuffer to prepare for presentation
13364 * Prepares a framebuffer for usage on a display plane. Generally this
13365 * involves pinning the underlying object and updating the frontbuffer tracking
13366 * bits. Some older platforms need special physical address handling for
13369 * Returns 0 on success, negative error code on failure.
13372 intel_prepare_plane_fb(struct drm_plane *plane,
13373 const struct drm_plane_state *new_state)
13375 struct drm_device *dev = plane->dev;
13376 struct drm_framebuffer *fb = new_state->fb;
13377 struct intel_plane *intel_plane = to_intel_plane(plane);
13378 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13379 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13385 mutex_lock(&dev->struct_mutex);
13387 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13388 INTEL_INFO(dev)->cursor_needs_physical) {
13389 int align = IS_I830(dev) ? 16 * 1024 : 256;
13390 ret = i915_gem_object_attach_phys(obj, align);
13392 DRM_DEBUG_KMS("failed to attach phys object\n");
13394 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13398 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13400 mutex_unlock(&dev->struct_mutex);
13406 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13407 * @plane: drm plane to clean up for
13408 * @fb: old framebuffer that was on plane
13410 * Cleans up a framebuffer that has just been removed from a plane.
13413 intel_cleanup_plane_fb(struct drm_plane *plane,
13414 const struct drm_plane_state *old_state)
13416 struct drm_device *dev = plane->dev;
13417 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13422 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13423 !INTEL_INFO(dev)->cursor_needs_physical) {
13424 mutex_lock(&dev->struct_mutex);
13425 intel_unpin_fb_obj(old_state->fb, old_state);
13426 mutex_unlock(&dev->struct_mutex);
13431 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13434 struct drm_device *dev;
13435 struct drm_i915_private *dev_priv;
13436 int crtc_clock, cdclk;
13438 if (!intel_crtc || !crtc_state)
13439 return DRM_PLANE_HELPER_NO_SCALING;
13441 dev = intel_crtc->base.dev;
13442 dev_priv = dev->dev_private;
13443 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13444 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13446 if (!crtc_clock || !cdclk)
13447 return DRM_PLANE_HELPER_NO_SCALING;
13450 * skl max scale is lower of:
13451 * close to 3 but not 3, -1 is for that purpose
13455 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13461 intel_check_primary_plane(struct drm_plane *plane,
13462 struct intel_crtc_state *crtc_state,
13463 struct intel_plane_state *state)
13465 struct drm_crtc *crtc = state->base.crtc;
13466 struct drm_framebuffer *fb = state->base.fb;
13467 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13468 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13469 bool can_position = false;
13471 /* use scaler when colorkey is not required */
13472 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13473 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13475 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13476 can_position = true;
13479 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13480 &state->dst, &state->clip,
13481 min_scale, max_scale,
13482 can_position, true,
13487 intel_commit_primary_plane(struct drm_plane *plane,
13488 struct intel_plane_state *state)
13490 struct drm_crtc *crtc = state->base.crtc;
13491 struct drm_framebuffer *fb = state->base.fb;
13492 struct drm_device *dev = plane->dev;
13493 struct drm_i915_private *dev_priv = dev->dev_private;
13494 struct intel_crtc *intel_crtc;
13495 struct drm_rect *src = &state->src;
13497 crtc = crtc ? crtc : plane->crtc;
13498 intel_crtc = to_intel_crtc(crtc);
13501 crtc->x = src->x1 >> 16;
13502 crtc->y = src->y1 >> 16;
13504 if (!crtc->state->active)
13507 dev_priv->display.update_primary_plane(crtc, fb,
13508 state->src.x1 >> 16,
13509 state->src.y1 >> 16);
13513 intel_disable_primary_plane(struct drm_plane *plane,
13514 struct drm_crtc *crtc)
13516 struct drm_device *dev = plane->dev;
13517 struct drm_i915_private *dev_priv = dev->dev_private;
13519 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13522 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13523 struct drm_crtc_state *old_crtc_state)
13525 struct drm_device *dev = crtc->dev;
13526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13527 struct intel_crtc_state *old_intel_state =
13528 to_intel_crtc_state(old_crtc_state);
13529 bool modeset = needs_modeset(crtc->state);
13531 if (intel_crtc->atomic.update_wm_pre)
13532 intel_update_watermarks(crtc);
13534 /* Perform vblank evasion around commit operation */
13535 if (crtc->state->active)
13536 intel_pipe_update_start(intel_crtc);
13541 if (to_intel_crtc_state(crtc->state)->update_pipe)
13542 intel_update_pipe_config(intel_crtc, old_intel_state);
13543 else if (INTEL_INFO(dev)->gen >= 9)
13544 skl_detach_scalers(intel_crtc);
13547 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13548 struct drm_crtc_state *old_crtc_state)
13550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13552 if (crtc->state->active)
13553 intel_pipe_update_end(intel_crtc);
13557 * intel_plane_destroy - destroy a plane
13558 * @plane: plane to destroy
13560 * Common destruction function for all types of planes (primary, cursor,
13563 void intel_plane_destroy(struct drm_plane *plane)
13565 struct intel_plane *intel_plane = to_intel_plane(plane);
13566 drm_plane_cleanup(plane);
13567 kfree(intel_plane);
13570 const struct drm_plane_funcs intel_plane_funcs = {
13571 .update_plane = drm_atomic_helper_update_plane,
13572 .disable_plane = drm_atomic_helper_disable_plane,
13573 .destroy = intel_plane_destroy,
13574 .set_property = drm_atomic_helper_plane_set_property,
13575 .atomic_get_property = intel_plane_atomic_get_property,
13576 .atomic_set_property = intel_plane_atomic_set_property,
13577 .atomic_duplicate_state = intel_plane_duplicate_state,
13578 .atomic_destroy_state = intel_plane_destroy_state,
13582 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13585 struct intel_plane *primary;
13586 struct intel_plane_state *state;
13587 const uint32_t *intel_primary_formats;
13588 unsigned int num_formats;
13590 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13591 if (primary == NULL)
13594 state = intel_create_plane_state(&primary->base);
13599 primary->base.state = &state->base;
13601 primary->can_scale = false;
13602 primary->max_downscale = 1;
13603 if (INTEL_INFO(dev)->gen >= 9) {
13604 primary->can_scale = true;
13605 state->scaler_id = -1;
13607 primary->pipe = pipe;
13608 primary->plane = pipe;
13609 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13610 primary->check_plane = intel_check_primary_plane;
13611 primary->commit_plane = intel_commit_primary_plane;
13612 primary->disable_plane = intel_disable_primary_plane;
13613 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13614 primary->plane = !pipe;
13616 if (INTEL_INFO(dev)->gen >= 9) {
13617 intel_primary_formats = skl_primary_formats;
13618 num_formats = ARRAY_SIZE(skl_primary_formats);
13619 } else if (INTEL_INFO(dev)->gen >= 4) {
13620 intel_primary_formats = i965_primary_formats;
13621 num_formats = ARRAY_SIZE(i965_primary_formats);
13623 intel_primary_formats = i8xx_primary_formats;
13624 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13627 drm_universal_plane_init(dev, &primary->base, 0,
13628 &intel_plane_funcs,
13629 intel_primary_formats, num_formats,
13630 DRM_PLANE_TYPE_PRIMARY);
13632 if (INTEL_INFO(dev)->gen >= 4)
13633 intel_create_rotation_property(dev, primary);
13635 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13637 return &primary->base;
13640 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13642 if (!dev->mode_config.rotation_property) {
13643 unsigned long flags = BIT(DRM_ROTATE_0) |
13644 BIT(DRM_ROTATE_180);
13646 if (INTEL_INFO(dev)->gen >= 9)
13647 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13649 dev->mode_config.rotation_property =
13650 drm_mode_create_rotation_property(dev, flags);
13652 if (dev->mode_config.rotation_property)
13653 drm_object_attach_property(&plane->base.base,
13654 dev->mode_config.rotation_property,
13655 plane->base.state->rotation);
13659 intel_check_cursor_plane(struct drm_plane *plane,
13660 struct intel_crtc_state *crtc_state,
13661 struct intel_plane_state *state)
13663 struct drm_crtc *crtc = crtc_state->base.crtc;
13664 struct drm_framebuffer *fb = state->base.fb;
13665 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13669 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13670 &state->dst, &state->clip,
13671 DRM_PLANE_HELPER_NO_SCALING,
13672 DRM_PLANE_HELPER_NO_SCALING,
13673 true, true, &state->visible);
13677 /* if we want to turn off the cursor ignore width and height */
13681 /* Check for which cursor types we support */
13682 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13683 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13684 state->base.crtc_w, state->base.crtc_h);
13688 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13689 if (obj->base.size < stride * state->base.crtc_h) {
13690 DRM_DEBUG_KMS("buffer is too small\n");
13694 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13695 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13703 intel_disable_cursor_plane(struct drm_plane *plane,
13704 struct drm_crtc *crtc)
13706 intel_crtc_update_cursor(crtc, false);
13710 intel_commit_cursor_plane(struct drm_plane *plane,
13711 struct intel_plane_state *state)
13713 struct drm_crtc *crtc = state->base.crtc;
13714 struct drm_device *dev = plane->dev;
13715 struct intel_crtc *intel_crtc;
13716 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13719 crtc = crtc ? crtc : plane->crtc;
13720 intel_crtc = to_intel_crtc(crtc);
13722 if (intel_crtc->cursor_bo == obj)
13727 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13728 addr = i915_gem_obj_ggtt_offset(obj);
13730 addr = obj->phys_handle->busaddr;
13732 intel_crtc->cursor_addr = addr;
13733 intel_crtc->cursor_bo = obj;
13736 if (crtc->state->active)
13737 intel_crtc_update_cursor(crtc, state->visible);
13740 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13743 struct intel_plane *cursor;
13744 struct intel_plane_state *state;
13746 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13747 if (cursor == NULL)
13750 state = intel_create_plane_state(&cursor->base);
13755 cursor->base.state = &state->base;
13757 cursor->can_scale = false;
13758 cursor->max_downscale = 1;
13759 cursor->pipe = pipe;
13760 cursor->plane = pipe;
13761 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13762 cursor->check_plane = intel_check_cursor_plane;
13763 cursor->commit_plane = intel_commit_cursor_plane;
13764 cursor->disable_plane = intel_disable_cursor_plane;
13766 drm_universal_plane_init(dev, &cursor->base, 0,
13767 &intel_plane_funcs,
13768 intel_cursor_formats,
13769 ARRAY_SIZE(intel_cursor_formats),
13770 DRM_PLANE_TYPE_CURSOR);
13772 if (INTEL_INFO(dev)->gen >= 4) {
13773 if (!dev->mode_config.rotation_property)
13774 dev->mode_config.rotation_property =
13775 drm_mode_create_rotation_property(dev,
13776 BIT(DRM_ROTATE_0) |
13777 BIT(DRM_ROTATE_180));
13778 if (dev->mode_config.rotation_property)
13779 drm_object_attach_property(&cursor->base.base,
13780 dev->mode_config.rotation_property,
13781 state->base.rotation);
13784 if (INTEL_INFO(dev)->gen >=9)
13785 state->scaler_id = -1;
13787 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13789 return &cursor->base;
13792 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13793 struct intel_crtc_state *crtc_state)
13796 struct intel_scaler *intel_scaler;
13797 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13799 for (i = 0; i < intel_crtc->num_scalers; i++) {
13800 intel_scaler = &scaler_state->scalers[i];
13801 intel_scaler->in_use = 0;
13802 intel_scaler->mode = PS_SCALER_MODE_DYN;
13805 scaler_state->scaler_id = -1;
13808 static void intel_crtc_init(struct drm_device *dev, int pipe)
13810 struct drm_i915_private *dev_priv = dev->dev_private;
13811 struct intel_crtc *intel_crtc;
13812 struct intel_crtc_state *crtc_state = NULL;
13813 struct drm_plane *primary = NULL;
13814 struct drm_plane *cursor = NULL;
13817 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13818 if (intel_crtc == NULL)
13821 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13824 intel_crtc->config = crtc_state;
13825 intel_crtc->base.state = &crtc_state->base;
13826 crtc_state->base.crtc = &intel_crtc->base;
13828 /* initialize shared scalers */
13829 if (INTEL_INFO(dev)->gen >= 9) {
13830 if (pipe == PIPE_C)
13831 intel_crtc->num_scalers = 1;
13833 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13835 skl_init_scalers(dev, intel_crtc, crtc_state);
13838 primary = intel_primary_plane_create(dev, pipe);
13842 cursor = intel_cursor_plane_create(dev, pipe);
13846 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13847 cursor, &intel_crtc_funcs);
13851 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13852 for (i = 0; i < 256; i++) {
13853 intel_crtc->lut_r[i] = i;
13854 intel_crtc->lut_g[i] = i;
13855 intel_crtc->lut_b[i] = i;
13859 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13860 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13862 intel_crtc->pipe = pipe;
13863 intel_crtc->plane = pipe;
13864 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13865 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13866 intel_crtc->plane = !pipe;
13869 intel_crtc->cursor_base = ~0;
13870 intel_crtc->cursor_cntl = ~0;
13871 intel_crtc->cursor_size = ~0;
13873 intel_crtc->wm.cxsr_allowed = true;
13875 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13876 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13877 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13878 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13880 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13882 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13887 drm_plane_cleanup(primary);
13889 drm_plane_cleanup(cursor);
13894 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13896 struct drm_encoder *encoder = connector->base.encoder;
13897 struct drm_device *dev = connector->base.dev;
13899 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13901 if (!encoder || WARN_ON(!encoder->crtc))
13902 return INVALID_PIPE;
13904 return to_intel_crtc(encoder->crtc)->pipe;
13907 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13908 struct drm_file *file)
13910 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13911 struct drm_crtc *drmmode_crtc;
13912 struct intel_crtc *crtc;
13914 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13916 if (!drmmode_crtc) {
13917 DRM_ERROR("no such CRTC id\n");
13921 crtc = to_intel_crtc(drmmode_crtc);
13922 pipe_from_crtc_id->pipe = crtc->pipe;
13927 static int intel_encoder_clones(struct intel_encoder *encoder)
13929 struct drm_device *dev = encoder->base.dev;
13930 struct intel_encoder *source_encoder;
13931 int index_mask = 0;
13934 for_each_intel_encoder(dev, source_encoder) {
13935 if (encoders_cloneable(encoder, source_encoder))
13936 index_mask |= (1 << entry);
13944 static bool has_edp_a(struct drm_device *dev)
13946 struct drm_i915_private *dev_priv = dev->dev_private;
13948 if (!IS_MOBILE(dev))
13951 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13954 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13960 static bool intel_crt_present(struct drm_device *dev)
13962 struct drm_i915_private *dev_priv = dev->dev_private;
13964 if (INTEL_INFO(dev)->gen >= 9)
13967 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13970 if (IS_CHERRYVIEW(dev))
13973 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13979 static void intel_setup_outputs(struct drm_device *dev)
13981 struct drm_i915_private *dev_priv = dev->dev_private;
13982 struct intel_encoder *encoder;
13983 bool dpd_is_edp = false;
13985 intel_lvds_init(dev);
13987 if (intel_crt_present(dev))
13988 intel_crt_init(dev);
13990 if (IS_BROXTON(dev)) {
13992 * FIXME: Broxton doesn't support port detection via the
13993 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13994 * detect the ports.
13996 intel_ddi_init(dev, PORT_A);
13997 intel_ddi_init(dev, PORT_B);
13998 intel_ddi_init(dev, PORT_C);
13999 } else if (HAS_DDI(dev)) {
14003 * Haswell uses DDI functions to detect digital outputs.
14004 * On SKL pre-D0 the strap isn't connected, so we assume
14007 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14008 /* WaIgnoreDDIAStrap: skl */
14009 if (found || IS_SKYLAKE(dev))
14010 intel_ddi_init(dev, PORT_A);
14012 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14014 found = I915_READ(SFUSE_STRAP);
14016 if (found & SFUSE_STRAP_DDIB_DETECTED)
14017 intel_ddi_init(dev, PORT_B);
14018 if (found & SFUSE_STRAP_DDIC_DETECTED)
14019 intel_ddi_init(dev, PORT_C);
14020 if (found & SFUSE_STRAP_DDID_DETECTED)
14021 intel_ddi_init(dev, PORT_D);
14023 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14025 if (IS_SKYLAKE(dev) &&
14026 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14027 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14028 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14029 intel_ddi_init(dev, PORT_E);
14031 } else if (HAS_PCH_SPLIT(dev)) {
14033 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14035 if (has_edp_a(dev))
14036 intel_dp_init(dev, DP_A, PORT_A);
14038 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14039 /* PCH SDVOB multiplex with HDMIB */
14040 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14042 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14043 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14044 intel_dp_init(dev, PCH_DP_B, PORT_B);
14047 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14048 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14050 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14051 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14053 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14054 intel_dp_init(dev, PCH_DP_C, PORT_C);
14056 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14057 intel_dp_init(dev, PCH_DP_D, PORT_D);
14058 } else if (IS_VALLEYVIEW(dev)) {
14060 * The DP_DETECTED bit is the latched state of the DDC
14061 * SDA pin at boot. However since eDP doesn't require DDC
14062 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14063 * eDP ports may have been muxed to an alternate function.
14064 * Thus we can't rely on the DP_DETECTED bit alone to detect
14065 * eDP ports. Consult the VBT as well as DP_DETECTED to
14066 * detect eDP ports.
14068 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14069 !intel_dp_is_edp(dev, PORT_B))
14070 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14071 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14072 intel_dp_is_edp(dev, PORT_B))
14073 intel_dp_init(dev, VLV_DP_B, PORT_B);
14075 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14076 !intel_dp_is_edp(dev, PORT_C))
14077 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14078 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14079 intel_dp_is_edp(dev, PORT_C))
14080 intel_dp_init(dev, VLV_DP_C, PORT_C);
14082 if (IS_CHERRYVIEW(dev)) {
14083 /* eDP not supported on port D, so don't check VBT */
14084 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14085 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14086 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14087 intel_dp_init(dev, CHV_DP_D, PORT_D);
14090 intel_dsi_init(dev);
14091 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14092 bool found = false;
14094 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14095 DRM_DEBUG_KMS("probing SDVOB\n");
14096 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14097 if (!found && IS_G4X(dev)) {
14098 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14099 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14102 if (!found && IS_G4X(dev))
14103 intel_dp_init(dev, DP_B, PORT_B);
14106 /* Before G4X SDVOC doesn't have its own detect register */
14108 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14109 DRM_DEBUG_KMS("probing SDVOC\n");
14110 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14113 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14116 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14117 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14120 intel_dp_init(dev, DP_C, PORT_C);
14124 (I915_READ(DP_D) & DP_DETECTED))
14125 intel_dp_init(dev, DP_D, PORT_D);
14126 } else if (IS_GEN2(dev))
14127 intel_dvo_init(dev);
14129 if (SUPPORTS_TV(dev))
14130 intel_tv_init(dev);
14132 intel_psr_init(dev);
14134 for_each_intel_encoder(dev, encoder) {
14135 encoder->base.possible_crtcs = encoder->crtc_mask;
14136 encoder->base.possible_clones =
14137 intel_encoder_clones(encoder);
14140 intel_init_pch_refclk(dev);
14142 drm_helper_move_panel_connectors_to_head(dev);
14145 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14147 struct drm_device *dev = fb->dev;
14148 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14150 drm_framebuffer_cleanup(fb);
14151 mutex_lock(&dev->struct_mutex);
14152 WARN_ON(!intel_fb->obj->framebuffer_references--);
14153 drm_gem_object_unreference(&intel_fb->obj->base);
14154 mutex_unlock(&dev->struct_mutex);
14158 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14159 struct drm_file *file,
14160 unsigned int *handle)
14162 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14163 struct drm_i915_gem_object *obj = intel_fb->obj;
14165 return drm_gem_handle_create(file, &obj->base, handle);
14168 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14169 struct drm_file *file,
14170 unsigned flags, unsigned color,
14171 struct drm_clip_rect *clips,
14172 unsigned num_clips)
14174 struct drm_device *dev = fb->dev;
14175 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14176 struct drm_i915_gem_object *obj = intel_fb->obj;
14178 mutex_lock(&dev->struct_mutex);
14179 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14180 mutex_unlock(&dev->struct_mutex);
14185 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14186 .destroy = intel_user_framebuffer_destroy,
14187 .create_handle = intel_user_framebuffer_create_handle,
14188 .dirty = intel_user_framebuffer_dirty,
14192 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14193 uint32_t pixel_format)
14195 u32 gen = INTEL_INFO(dev)->gen;
14198 /* "The stride in bytes must not exceed the of the size of 8K
14199 * pixels and 32K bytes."
14201 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14202 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14204 } else if (gen >= 4) {
14205 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14209 } else if (gen >= 3) {
14210 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14215 /* XXX DSPC is limited to 4k tiled */
14220 static int intel_framebuffer_init(struct drm_device *dev,
14221 struct intel_framebuffer *intel_fb,
14222 struct drm_mode_fb_cmd2 *mode_cmd,
14223 struct drm_i915_gem_object *obj)
14225 unsigned int aligned_height;
14227 u32 pitch_limit, stride_alignment;
14229 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14231 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14232 /* Enforce that fb modifier and tiling mode match, but only for
14233 * X-tiled. This is needed for FBC. */
14234 if (!!(obj->tiling_mode == I915_TILING_X) !=
14235 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14236 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14240 if (obj->tiling_mode == I915_TILING_X)
14241 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14242 else if (obj->tiling_mode == I915_TILING_Y) {
14243 DRM_DEBUG("No Y tiling for legacy addfb\n");
14248 /* Passed in modifier sanity checking. */
14249 switch (mode_cmd->modifier[0]) {
14250 case I915_FORMAT_MOD_Y_TILED:
14251 case I915_FORMAT_MOD_Yf_TILED:
14252 if (INTEL_INFO(dev)->gen < 9) {
14253 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14254 mode_cmd->modifier[0]);
14257 case DRM_FORMAT_MOD_NONE:
14258 case I915_FORMAT_MOD_X_TILED:
14261 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14262 mode_cmd->modifier[0]);
14266 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14267 mode_cmd->pixel_format);
14268 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14269 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14270 mode_cmd->pitches[0], stride_alignment);
14274 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14275 mode_cmd->pixel_format);
14276 if (mode_cmd->pitches[0] > pitch_limit) {
14277 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14278 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14279 "tiled" : "linear",
14280 mode_cmd->pitches[0], pitch_limit);
14284 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14285 mode_cmd->pitches[0] != obj->stride) {
14286 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14287 mode_cmd->pitches[0], obj->stride);
14291 /* Reject formats not supported by any plane early. */
14292 switch (mode_cmd->pixel_format) {
14293 case DRM_FORMAT_C8:
14294 case DRM_FORMAT_RGB565:
14295 case DRM_FORMAT_XRGB8888:
14296 case DRM_FORMAT_ARGB8888:
14298 case DRM_FORMAT_XRGB1555:
14299 if (INTEL_INFO(dev)->gen > 3) {
14300 DRM_DEBUG("unsupported pixel format: %s\n",
14301 drm_get_format_name(mode_cmd->pixel_format));
14305 case DRM_FORMAT_ABGR8888:
14306 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14307 DRM_DEBUG("unsupported pixel format: %s\n",
14308 drm_get_format_name(mode_cmd->pixel_format));
14312 case DRM_FORMAT_XBGR8888:
14313 case DRM_FORMAT_XRGB2101010:
14314 case DRM_FORMAT_XBGR2101010:
14315 if (INTEL_INFO(dev)->gen < 4) {
14316 DRM_DEBUG("unsupported pixel format: %s\n",
14317 drm_get_format_name(mode_cmd->pixel_format));
14321 case DRM_FORMAT_ABGR2101010:
14322 if (!IS_VALLEYVIEW(dev)) {
14323 DRM_DEBUG("unsupported pixel format: %s\n",
14324 drm_get_format_name(mode_cmd->pixel_format));
14328 case DRM_FORMAT_YUYV:
14329 case DRM_FORMAT_UYVY:
14330 case DRM_FORMAT_YVYU:
14331 case DRM_FORMAT_VYUY:
14332 if (INTEL_INFO(dev)->gen < 5) {
14333 DRM_DEBUG("unsupported pixel format: %s\n",
14334 drm_get_format_name(mode_cmd->pixel_format));
14339 DRM_DEBUG("unsupported pixel format: %s\n",
14340 drm_get_format_name(mode_cmd->pixel_format));
14344 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14345 if (mode_cmd->offsets[0] != 0)
14348 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14349 mode_cmd->pixel_format,
14350 mode_cmd->modifier[0]);
14351 /* FIXME drm helper for size checks (especially planar formats)? */
14352 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14355 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14356 intel_fb->obj = obj;
14357 intel_fb->obj->framebuffer_references++;
14359 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14361 DRM_ERROR("framebuffer init failed %d\n", ret);
14368 static struct drm_framebuffer *
14369 intel_user_framebuffer_create(struct drm_device *dev,
14370 struct drm_file *filp,
14371 struct drm_mode_fb_cmd2 *mode_cmd)
14373 struct drm_i915_gem_object *obj;
14375 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14376 mode_cmd->handles[0]));
14377 if (&obj->base == NULL)
14378 return ERR_PTR(-ENOENT);
14380 return intel_framebuffer_create(dev, mode_cmd, obj);
14383 #ifndef CONFIG_DRM_FBDEV_EMULATION
14384 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14389 static const struct drm_mode_config_funcs intel_mode_funcs = {
14390 .fb_create = intel_user_framebuffer_create,
14391 .output_poll_changed = intel_fbdev_output_poll_changed,
14392 .atomic_check = intel_atomic_check,
14393 .atomic_commit = intel_atomic_commit,
14394 .atomic_state_alloc = intel_atomic_state_alloc,
14395 .atomic_state_clear = intel_atomic_state_clear,
14398 /* Set up chip specific display functions */
14399 static void intel_init_display(struct drm_device *dev)
14401 struct drm_i915_private *dev_priv = dev->dev_private;
14403 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14404 dev_priv->display.find_dpll = g4x_find_best_dpll;
14405 else if (IS_CHERRYVIEW(dev))
14406 dev_priv->display.find_dpll = chv_find_best_dpll;
14407 else if (IS_VALLEYVIEW(dev))
14408 dev_priv->display.find_dpll = vlv_find_best_dpll;
14409 else if (IS_PINEVIEW(dev))
14410 dev_priv->display.find_dpll = pnv_find_best_dpll;
14412 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14414 if (INTEL_INFO(dev)->gen >= 9) {
14415 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14416 dev_priv->display.get_initial_plane_config =
14417 skylake_get_initial_plane_config;
14418 dev_priv->display.crtc_compute_clock =
14419 haswell_crtc_compute_clock;
14420 dev_priv->display.crtc_enable = haswell_crtc_enable;
14421 dev_priv->display.crtc_disable = haswell_crtc_disable;
14422 dev_priv->display.update_primary_plane =
14423 skylake_update_primary_plane;
14424 } else if (HAS_DDI(dev)) {
14425 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14426 dev_priv->display.get_initial_plane_config =
14427 ironlake_get_initial_plane_config;
14428 dev_priv->display.crtc_compute_clock =
14429 haswell_crtc_compute_clock;
14430 dev_priv->display.crtc_enable = haswell_crtc_enable;
14431 dev_priv->display.crtc_disable = haswell_crtc_disable;
14432 dev_priv->display.update_primary_plane =
14433 ironlake_update_primary_plane;
14434 } else if (HAS_PCH_SPLIT(dev)) {
14435 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14436 dev_priv->display.get_initial_plane_config =
14437 ironlake_get_initial_plane_config;
14438 dev_priv->display.crtc_compute_clock =
14439 ironlake_crtc_compute_clock;
14440 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14441 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14442 dev_priv->display.update_primary_plane =
14443 ironlake_update_primary_plane;
14444 } else if (IS_VALLEYVIEW(dev)) {
14445 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14446 dev_priv->display.get_initial_plane_config =
14447 i9xx_get_initial_plane_config;
14448 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14449 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14450 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14451 dev_priv->display.update_primary_plane =
14452 i9xx_update_primary_plane;
14454 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14455 dev_priv->display.get_initial_plane_config =
14456 i9xx_get_initial_plane_config;
14457 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14458 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14459 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14460 dev_priv->display.update_primary_plane =
14461 i9xx_update_primary_plane;
14464 /* Returns the core display clock speed */
14465 if (IS_SKYLAKE(dev))
14466 dev_priv->display.get_display_clock_speed =
14467 skylake_get_display_clock_speed;
14468 else if (IS_BROXTON(dev))
14469 dev_priv->display.get_display_clock_speed =
14470 broxton_get_display_clock_speed;
14471 else if (IS_BROADWELL(dev))
14472 dev_priv->display.get_display_clock_speed =
14473 broadwell_get_display_clock_speed;
14474 else if (IS_HASWELL(dev))
14475 dev_priv->display.get_display_clock_speed =
14476 haswell_get_display_clock_speed;
14477 else if (IS_VALLEYVIEW(dev))
14478 dev_priv->display.get_display_clock_speed =
14479 valleyview_get_display_clock_speed;
14480 else if (IS_GEN5(dev))
14481 dev_priv->display.get_display_clock_speed =
14482 ilk_get_display_clock_speed;
14483 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14484 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14485 dev_priv->display.get_display_clock_speed =
14486 i945_get_display_clock_speed;
14487 else if (IS_GM45(dev))
14488 dev_priv->display.get_display_clock_speed =
14489 gm45_get_display_clock_speed;
14490 else if (IS_CRESTLINE(dev))
14491 dev_priv->display.get_display_clock_speed =
14492 i965gm_get_display_clock_speed;
14493 else if (IS_PINEVIEW(dev))
14494 dev_priv->display.get_display_clock_speed =
14495 pnv_get_display_clock_speed;
14496 else if (IS_G33(dev) || IS_G4X(dev))
14497 dev_priv->display.get_display_clock_speed =
14498 g33_get_display_clock_speed;
14499 else if (IS_I915G(dev))
14500 dev_priv->display.get_display_clock_speed =
14501 i915_get_display_clock_speed;
14502 else if (IS_I945GM(dev) || IS_845G(dev))
14503 dev_priv->display.get_display_clock_speed =
14504 i9xx_misc_get_display_clock_speed;
14505 else if (IS_PINEVIEW(dev))
14506 dev_priv->display.get_display_clock_speed =
14507 pnv_get_display_clock_speed;
14508 else if (IS_I915GM(dev))
14509 dev_priv->display.get_display_clock_speed =
14510 i915gm_get_display_clock_speed;
14511 else if (IS_I865G(dev))
14512 dev_priv->display.get_display_clock_speed =
14513 i865_get_display_clock_speed;
14514 else if (IS_I85X(dev))
14515 dev_priv->display.get_display_clock_speed =
14516 i85x_get_display_clock_speed;
14518 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14519 dev_priv->display.get_display_clock_speed =
14520 i830_get_display_clock_speed;
14523 if (IS_GEN5(dev)) {
14524 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14525 } else if (IS_GEN6(dev)) {
14526 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14527 } else if (IS_IVYBRIDGE(dev)) {
14528 /* FIXME: detect B0+ stepping and use auto training */
14529 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14530 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14531 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14532 if (IS_BROADWELL(dev)) {
14533 dev_priv->display.modeset_commit_cdclk =
14534 broadwell_modeset_commit_cdclk;
14535 dev_priv->display.modeset_calc_cdclk =
14536 broadwell_modeset_calc_cdclk;
14538 } else if (IS_VALLEYVIEW(dev)) {
14539 dev_priv->display.modeset_commit_cdclk =
14540 valleyview_modeset_commit_cdclk;
14541 dev_priv->display.modeset_calc_cdclk =
14542 valleyview_modeset_calc_cdclk;
14543 } else if (IS_BROXTON(dev)) {
14544 dev_priv->display.modeset_commit_cdclk =
14545 broxton_modeset_commit_cdclk;
14546 dev_priv->display.modeset_calc_cdclk =
14547 broxton_modeset_calc_cdclk;
14550 switch (INTEL_INFO(dev)->gen) {
14552 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14556 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14561 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14565 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14568 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14569 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14572 /* Drop through - unsupported since execlist only. */
14574 /* Default just returns -ENODEV to indicate unsupported */
14575 dev_priv->display.queue_flip = intel_default_queue_flip;
14578 mutex_init(&dev_priv->pps_mutex);
14582 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14583 * resume, or other times. This quirk makes sure that's the case for
14584 * affected systems.
14586 static void quirk_pipea_force(struct drm_device *dev)
14588 struct drm_i915_private *dev_priv = dev->dev_private;
14590 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14591 DRM_INFO("applying pipe a force quirk\n");
14594 static void quirk_pipeb_force(struct drm_device *dev)
14596 struct drm_i915_private *dev_priv = dev->dev_private;
14598 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14599 DRM_INFO("applying pipe b force quirk\n");
14603 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14605 static void quirk_ssc_force_disable(struct drm_device *dev)
14607 struct drm_i915_private *dev_priv = dev->dev_private;
14608 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14609 DRM_INFO("applying lvds SSC disable quirk\n");
14613 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14616 static void quirk_invert_brightness(struct drm_device *dev)
14618 struct drm_i915_private *dev_priv = dev->dev_private;
14619 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14620 DRM_INFO("applying inverted panel brightness quirk\n");
14623 /* Some VBT's incorrectly indicate no backlight is present */
14624 static void quirk_backlight_present(struct drm_device *dev)
14626 struct drm_i915_private *dev_priv = dev->dev_private;
14627 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14628 DRM_INFO("applying backlight present quirk\n");
14631 struct intel_quirk {
14633 int subsystem_vendor;
14634 int subsystem_device;
14635 void (*hook)(struct drm_device *dev);
14638 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14639 struct intel_dmi_quirk {
14640 void (*hook)(struct drm_device *dev);
14641 const struct dmi_system_id (*dmi_id_list)[];
14644 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14646 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14650 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14652 .dmi_id_list = &(const struct dmi_system_id[]) {
14654 .callback = intel_dmi_reverse_brightness,
14655 .ident = "NCR Corporation",
14656 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14657 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14660 { } /* terminating entry */
14662 .hook = quirk_invert_brightness,
14666 static struct intel_quirk intel_quirks[] = {
14667 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14668 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14670 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14671 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14673 /* 830 needs to leave pipe A & dpll A up */
14674 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14676 /* 830 needs to leave pipe B & dpll B up */
14677 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14679 /* Lenovo U160 cannot use SSC on LVDS */
14680 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14682 /* Sony Vaio Y cannot use SSC on LVDS */
14683 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14685 /* Acer Aspire 5734Z must invert backlight brightness */
14686 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14688 /* Acer/eMachines G725 */
14689 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14691 /* Acer/eMachines e725 */
14692 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14694 /* Acer/Packard Bell NCL20 */
14695 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14697 /* Acer Aspire 4736Z */
14698 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14700 /* Acer Aspire 5336 */
14701 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14703 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14704 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14706 /* Acer C720 Chromebook (Core i3 4005U) */
14707 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14709 /* Apple Macbook 2,1 (Core 2 T7400) */
14710 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14712 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14713 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14715 /* HP Chromebook 14 (Celeron 2955U) */
14716 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14718 /* Dell Chromebook 11 */
14719 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14722 static void intel_init_quirks(struct drm_device *dev)
14724 struct pci_dev *d = dev->pdev;
14727 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14728 struct intel_quirk *q = &intel_quirks[i];
14730 if (d->device == q->device &&
14731 (d->subsystem_vendor == q->subsystem_vendor ||
14732 q->subsystem_vendor == PCI_ANY_ID) &&
14733 (d->subsystem_device == q->subsystem_device ||
14734 q->subsystem_device == PCI_ANY_ID))
14737 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14738 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14739 intel_dmi_quirks[i].hook(dev);
14743 /* Disable the VGA plane that we never use */
14744 static void i915_disable_vga(struct drm_device *dev)
14746 struct drm_i915_private *dev_priv = dev->dev_private;
14748 u32 vga_reg = i915_vgacntrl_reg(dev);
14750 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14751 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14752 outb(SR01, VGA_SR_INDEX);
14753 sr1 = inb(VGA_SR_DATA);
14754 outb(sr1 | 1<<5, VGA_SR_DATA);
14755 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14758 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14759 POSTING_READ(vga_reg);
14762 void intel_modeset_init_hw(struct drm_device *dev)
14764 intel_update_cdclk(dev);
14765 intel_prepare_ddi(dev);
14766 intel_init_clock_gating(dev);
14767 intel_enable_gt_powersave(dev);
14770 void intel_modeset_init(struct drm_device *dev)
14772 struct drm_i915_private *dev_priv = dev->dev_private;
14775 struct intel_crtc *crtc;
14777 drm_mode_config_init(dev);
14779 dev->mode_config.min_width = 0;
14780 dev->mode_config.min_height = 0;
14782 dev->mode_config.preferred_depth = 24;
14783 dev->mode_config.prefer_shadow = 1;
14785 dev->mode_config.allow_fb_modifiers = true;
14787 dev->mode_config.funcs = &intel_mode_funcs;
14789 intel_init_quirks(dev);
14791 intel_init_pm(dev);
14793 if (INTEL_INFO(dev)->num_pipes == 0)
14797 * There may be no VBT; and if the BIOS enabled SSC we can
14798 * just keep using it to avoid unnecessary flicker. Whereas if the
14799 * BIOS isn't using it, don't assume it will work even if the VBT
14800 * indicates as much.
14802 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14803 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14806 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14807 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14808 bios_lvds_use_ssc ? "en" : "dis",
14809 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14810 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14814 intel_init_display(dev);
14815 intel_init_audio(dev);
14817 if (IS_GEN2(dev)) {
14818 dev->mode_config.max_width = 2048;
14819 dev->mode_config.max_height = 2048;
14820 } else if (IS_GEN3(dev)) {
14821 dev->mode_config.max_width = 4096;
14822 dev->mode_config.max_height = 4096;
14824 dev->mode_config.max_width = 8192;
14825 dev->mode_config.max_height = 8192;
14828 if (IS_845G(dev) || IS_I865G(dev)) {
14829 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14830 dev->mode_config.cursor_height = 1023;
14831 } else if (IS_GEN2(dev)) {
14832 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14833 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14835 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14836 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14839 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14841 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14842 INTEL_INFO(dev)->num_pipes,
14843 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14845 for_each_pipe(dev_priv, pipe) {
14846 intel_crtc_init(dev, pipe);
14847 for_each_sprite(dev_priv, pipe, sprite) {
14848 ret = intel_plane_init(dev, pipe, sprite);
14850 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14851 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14855 intel_update_czclk(dev_priv);
14856 intel_update_cdclk(dev);
14858 intel_shared_dpll_init(dev);
14860 /* Just disable it once at startup */
14861 i915_disable_vga(dev);
14862 intel_setup_outputs(dev);
14864 /* Just in case the BIOS is doing something questionable. */
14865 intel_fbc_disable(dev_priv);
14867 drm_modeset_lock_all(dev);
14868 intel_modeset_setup_hw_state(dev);
14869 drm_modeset_unlock_all(dev);
14871 for_each_intel_crtc(dev, crtc) {
14872 struct intel_initial_plane_config plane_config = {};
14878 * Note that reserving the BIOS fb up front prevents us
14879 * from stuffing other stolen allocations like the ring
14880 * on top. This prevents some ugliness at boot time, and
14881 * can even allow for smooth boot transitions if the BIOS
14882 * fb is large enough for the active pipe configuration.
14884 dev_priv->display.get_initial_plane_config(crtc,
14888 * If the fb is shared between multiple heads, we'll
14889 * just get the first one.
14891 intel_find_initial_plane_obj(crtc, &plane_config);
14895 static void intel_enable_pipe_a(struct drm_device *dev)
14897 struct intel_connector *connector;
14898 struct drm_connector *crt = NULL;
14899 struct intel_load_detect_pipe load_detect_temp;
14900 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14902 /* We can't just switch on the pipe A, we need to set things up with a
14903 * proper mode and output configuration. As a gross hack, enable pipe A
14904 * by enabling the load detect pipe once. */
14905 for_each_intel_connector(dev, connector) {
14906 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14907 crt = &connector->base;
14915 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14916 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14920 intel_check_plane_mapping(struct intel_crtc *crtc)
14922 struct drm_device *dev = crtc->base.dev;
14923 struct drm_i915_private *dev_priv = dev->dev_private;
14926 if (INTEL_INFO(dev)->num_pipes == 1)
14929 reg = DSPCNTR(!crtc->plane);
14930 val = I915_READ(reg);
14932 if ((val & DISPLAY_PLANE_ENABLE) &&
14933 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14939 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14941 struct drm_device *dev = crtc->base.dev;
14942 struct intel_encoder *encoder;
14944 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14950 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14952 struct drm_device *dev = crtc->base.dev;
14953 struct drm_i915_private *dev_priv = dev->dev_private;
14956 /* Clear any frame start delays used for debugging left by the BIOS */
14957 reg = PIPECONF(crtc->config->cpu_transcoder);
14958 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14960 /* restore vblank interrupts to correct state */
14961 drm_crtc_vblank_reset(&crtc->base);
14962 if (crtc->active) {
14963 struct intel_plane *plane;
14965 drm_crtc_vblank_on(&crtc->base);
14967 /* Disable everything but the primary plane */
14968 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14969 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14972 plane->disable_plane(&plane->base, &crtc->base);
14976 /* We need to sanitize the plane -> pipe mapping first because this will
14977 * disable the crtc (and hence change the state) if it is wrong. Note
14978 * that gen4+ has a fixed plane -> pipe mapping. */
14979 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14982 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14983 crtc->base.base.id);
14985 /* Pipe has the wrong plane attached and the plane is active.
14986 * Temporarily change the plane mapping and disable everything
14988 plane = crtc->plane;
14989 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14990 crtc->plane = !plane;
14991 intel_crtc_disable_noatomic(&crtc->base);
14992 crtc->plane = plane;
14995 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14996 crtc->pipe == PIPE_A && !crtc->active) {
14997 /* BIOS forgot to enable pipe A, this mostly happens after
14998 * resume. Force-enable the pipe to fix this, the update_dpms
14999 * call below we restore the pipe to the right state, but leave
15000 * the required bits on. */
15001 intel_enable_pipe_a(dev);
15004 /* Adjust the state of the output pipe according to whether we
15005 * have active connectors/encoders. */
15006 if (!intel_crtc_has_encoders(crtc))
15007 intel_crtc_disable_noatomic(&crtc->base);
15009 if (crtc->active != crtc->base.state->active) {
15010 struct intel_encoder *encoder;
15012 /* This can happen either due to bugs in the get_hw_state
15013 * functions or because of calls to intel_crtc_disable_noatomic,
15014 * or because the pipe is force-enabled due to the
15016 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15017 crtc->base.base.id,
15018 crtc->base.state->enable ? "enabled" : "disabled",
15019 crtc->active ? "enabled" : "disabled");
15021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15022 crtc->base.state->active = crtc->active;
15023 crtc->base.enabled = crtc->active;
15025 /* Because we only establish the connector -> encoder ->
15026 * crtc links if something is active, this means the
15027 * crtc is now deactivated. Break the links. connector
15028 * -> encoder links are only establish when things are
15029 * actually up, hence no need to break them. */
15030 WARN_ON(crtc->active);
15032 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15033 encoder->base.crtc = NULL;
15036 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15038 * We start out with underrun reporting disabled to avoid races.
15039 * For correct bookkeeping mark this on active crtcs.
15041 * Also on gmch platforms we dont have any hardware bits to
15042 * disable the underrun reporting. Which means we need to start
15043 * out with underrun reporting disabled also on inactive pipes,
15044 * since otherwise we'll complain about the garbage we read when
15045 * e.g. coming up after runtime pm.
15047 * No protection against concurrent access is required - at
15048 * worst a fifo underrun happens which also sets this to false.
15050 crtc->cpu_fifo_underrun_disabled = true;
15051 crtc->pch_fifo_underrun_disabled = true;
15055 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15057 struct intel_connector *connector;
15058 struct drm_device *dev = encoder->base.dev;
15059 bool active = false;
15061 /* We need to check both for a crtc link (meaning that the
15062 * encoder is active and trying to read from a pipe) and the
15063 * pipe itself being active. */
15064 bool has_active_crtc = encoder->base.crtc &&
15065 to_intel_crtc(encoder->base.crtc)->active;
15067 for_each_intel_connector(dev, connector) {
15068 if (connector->base.encoder != &encoder->base)
15075 if (active && !has_active_crtc) {
15076 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15077 encoder->base.base.id,
15078 encoder->base.name);
15080 /* Connector is active, but has no active pipe. This is
15081 * fallout from our resume register restoring. Disable
15082 * the encoder manually again. */
15083 if (encoder->base.crtc) {
15084 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15085 encoder->base.base.id,
15086 encoder->base.name);
15087 encoder->disable(encoder);
15088 if (encoder->post_disable)
15089 encoder->post_disable(encoder);
15091 encoder->base.crtc = NULL;
15093 /* Inconsistent output/port/pipe state happens presumably due to
15094 * a bug in one of the get_hw_state functions. Or someplace else
15095 * in our code, like the register restore mess on resume. Clamp
15096 * things to off as a safer default. */
15097 for_each_intel_connector(dev, connector) {
15098 if (connector->encoder != encoder)
15100 connector->base.dpms = DRM_MODE_DPMS_OFF;
15101 connector->base.encoder = NULL;
15104 /* Enabled encoders without active connectors will be fixed in
15105 * the crtc fixup. */
15108 void i915_redisable_vga_power_on(struct drm_device *dev)
15110 struct drm_i915_private *dev_priv = dev->dev_private;
15111 u32 vga_reg = i915_vgacntrl_reg(dev);
15113 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15114 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15115 i915_disable_vga(dev);
15119 void i915_redisable_vga(struct drm_device *dev)
15121 struct drm_i915_private *dev_priv = dev->dev_private;
15123 /* This function can be called both from intel_modeset_setup_hw_state or
15124 * at a very early point in our resume sequence, where the power well
15125 * structures are not yet restored. Since this function is at a very
15126 * paranoid "someone might have enabled VGA while we were not looking"
15127 * level, just check if the power well is enabled instead of trying to
15128 * follow the "don't touch the power well if we don't need it" policy
15129 * the rest of the driver uses. */
15130 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15133 i915_redisable_vga_power_on(dev);
15136 static bool primary_get_hw_state(struct intel_plane *plane)
15138 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15140 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15143 /* FIXME read out full plane state for all planes */
15144 static void readout_plane_state(struct intel_crtc *crtc)
15146 struct drm_plane *primary = crtc->base.primary;
15147 struct intel_plane_state *plane_state =
15148 to_intel_plane_state(primary->state);
15150 plane_state->visible =
15151 primary_get_hw_state(to_intel_plane(primary));
15153 if (plane_state->visible)
15154 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15157 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15159 struct drm_i915_private *dev_priv = dev->dev_private;
15161 struct intel_crtc *crtc;
15162 struct intel_encoder *encoder;
15163 struct intel_connector *connector;
15166 for_each_intel_crtc(dev, crtc) {
15167 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15168 memset(crtc->config, 0, sizeof(*crtc->config));
15169 crtc->config->base.crtc = &crtc->base;
15171 crtc->active = dev_priv->display.get_pipe_config(crtc,
15174 crtc->base.state->active = crtc->active;
15175 crtc->base.enabled = crtc->active;
15177 readout_plane_state(crtc);
15179 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15180 crtc->base.base.id,
15181 crtc->active ? "enabled" : "disabled");
15184 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15185 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15187 pll->on = pll->get_hw_state(dev_priv, pll,
15188 &pll->config.hw_state);
15190 pll->config.crtc_mask = 0;
15191 for_each_intel_crtc(dev, crtc) {
15192 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15194 pll->config.crtc_mask |= 1 << crtc->pipe;
15198 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15199 pll->name, pll->config.crtc_mask, pll->on);
15201 if (pll->config.crtc_mask)
15202 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15205 for_each_intel_encoder(dev, encoder) {
15208 if (encoder->get_hw_state(encoder, &pipe)) {
15209 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15210 encoder->base.crtc = &crtc->base;
15211 encoder->get_config(encoder, crtc->config);
15213 encoder->base.crtc = NULL;
15216 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15217 encoder->base.base.id,
15218 encoder->base.name,
15219 encoder->base.crtc ? "enabled" : "disabled",
15223 for_each_intel_connector(dev, connector) {
15224 if (connector->get_hw_state(connector)) {
15225 connector->base.dpms = DRM_MODE_DPMS_ON;
15226 connector->base.encoder = &connector->encoder->base;
15228 connector->base.dpms = DRM_MODE_DPMS_OFF;
15229 connector->base.encoder = NULL;
15231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15232 connector->base.base.id,
15233 connector->base.name,
15234 connector->base.encoder ? "enabled" : "disabled");
15237 for_each_intel_crtc(dev, crtc) {
15238 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15240 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15241 if (crtc->base.state->active) {
15242 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15243 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15244 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15247 * The initial mode needs to be set in order to keep
15248 * the atomic core happy. It wants a valid mode if the
15249 * crtc's enabled, so we do the above call.
15251 * At this point some state updated by the connectors
15252 * in their ->detect() callback has not run yet, so
15253 * no recalculation can be done yet.
15255 * Even if we could do a recalculation and modeset
15256 * right now it would cause a double modeset if
15257 * fbdev or userspace chooses a different initial mode.
15259 * If that happens, someone indicated they wanted a
15260 * mode change, which means it's safe to do a full
15263 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15265 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15266 update_scanline_offset(crtc);
15271 /* Scan out the current hw modeset state,
15272 * and sanitizes it to the current state
15275 intel_modeset_setup_hw_state(struct drm_device *dev)
15277 struct drm_i915_private *dev_priv = dev->dev_private;
15279 struct intel_crtc *crtc;
15280 struct intel_encoder *encoder;
15283 intel_modeset_readout_hw_state(dev);
15285 /* HW state is read out, now we need to sanitize this mess. */
15286 for_each_intel_encoder(dev, encoder) {
15287 intel_sanitize_encoder(encoder);
15290 for_each_pipe(dev_priv, pipe) {
15291 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15292 intel_sanitize_crtc(crtc);
15293 intel_dump_pipe_config(crtc, crtc->config,
15294 "[setup_hw_state]");
15297 intel_modeset_update_connector_atomic_state(dev);
15299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15300 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15302 if (!pll->on || pll->active)
15305 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15307 pll->disable(dev_priv, pll);
15311 if (IS_VALLEYVIEW(dev))
15312 vlv_wm_get_hw_state(dev);
15313 else if (IS_GEN9(dev))
15314 skl_wm_get_hw_state(dev);
15315 else if (HAS_PCH_SPLIT(dev))
15316 ilk_wm_get_hw_state(dev);
15318 for_each_intel_crtc(dev, crtc) {
15319 unsigned long put_domains;
15321 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15322 if (WARN_ON(put_domains))
15323 modeset_put_power_domains(dev_priv, put_domains);
15325 intel_display_set_init_power(dev_priv, false);
15328 void intel_display_resume(struct drm_device *dev)
15330 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15331 struct intel_connector *conn;
15332 struct intel_plane *plane;
15333 struct drm_crtc *crtc;
15339 state->acquire_ctx = dev->mode_config.acquire_ctx;
15341 /* preserve complete old state, including dpll */
15342 intel_atomic_get_shared_dpll_state(state);
15344 for_each_crtc(dev, crtc) {
15345 struct drm_crtc_state *crtc_state =
15346 drm_atomic_get_crtc_state(state, crtc);
15348 ret = PTR_ERR_OR_ZERO(crtc_state);
15352 /* force a restore */
15353 crtc_state->mode_changed = true;
15356 for_each_intel_plane(dev, plane) {
15357 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15362 for_each_intel_connector(dev, conn) {
15363 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15368 intel_modeset_setup_hw_state(dev);
15370 i915_redisable_vga(dev);
15371 ret = drm_atomic_commit(state);
15376 DRM_ERROR("Restoring old state failed with %i\n", ret);
15377 drm_atomic_state_free(state);
15380 void intel_modeset_gem_init(struct drm_device *dev)
15382 struct drm_crtc *c;
15383 struct drm_i915_gem_object *obj;
15386 mutex_lock(&dev->struct_mutex);
15387 intel_init_gt_powersave(dev);
15388 mutex_unlock(&dev->struct_mutex);
15390 intel_modeset_init_hw(dev);
15392 intel_setup_overlay(dev);
15395 * Make sure any fbs we allocated at startup are properly
15396 * pinned & fenced. When we do the allocation it's too early
15399 for_each_crtc(dev, c) {
15400 obj = intel_fb_obj(c->primary->fb);
15404 mutex_lock(&dev->struct_mutex);
15405 ret = intel_pin_and_fence_fb_obj(c->primary,
15409 mutex_unlock(&dev->struct_mutex);
15411 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15412 to_intel_crtc(c)->pipe);
15413 drm_framebuffer_unreference(c->primary->fb);
15414 c->primary->fb = NULL;
15415 c->primary->crtc = c->primary->state->crtc = NULL;
15416 update_state_fb(c->primary);
15417 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15421 intel_backlight_register(dev);
15424 void intel_connector_unregister(struct intel_connector *intel_connector)
15426 struct drm_connector *connector = &intel_connector->base;
15428 intel_panel_destroy_backlight(connector);
15429 drm_connector_unregister(connector);
15432 void intel_modeset_cleanup(struct drm_device *dev)
15434 struct drm_i915_private *dev_priv = dev->dev_private;
15435 struct drm_connector *connector;
15437 intel_disable_gt_powersave(dev);
15439 intel_backlight_unregister(dev);
15442 * Interrupts and polling as the first thing to avoid creating havoc.
15443 * Too much stuff here (turning of connectors, ...) would
15444 * experience fancy races otherwise.
15446 intel_irq_uninstall(dev_priv);
15449 * Due to the hpd irq storm handling the hotplug work can re-arm the
15450 * poll handlers. Hence disable polling after hpd handling is shut down.
15452 drm_kms_helper_poll_fini(dev);
15454 intel_unregister_dsm_handler();
15456 intel_fbc_disable(dev_priv);
15458 /* flush any delayed tasks or pending work */
15459 flush_scheduled_work();
15461 /* destroy the backlight and sysfs files before encoders/connectors */
15462 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15463 struct intel_connector *intel_connector;
15465 intel_connector = to_intel_connector(connector);
15466 intel_connector->unregister(intel_connector);
15469 drm_mode_config_cleanup(dev);
15471 intel_cleanup_overlay(dev);
15473 mutex_lock(&dev->struct_mutex);
15474 intel_cleanup_gt_powersave(dev);
15475 mutex_unlock(&dev->struct_mutex);
15479 * Return which encoder is currently attached for connector.
15481 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15483 return &intel_attached_encoder(connector)->base;
15486 void intel_connector_attach_encoder(struct intel_connector *connector,
15487 struct intel_encoder *encoder)
15489 connector->encoder = encoder;
15490 drm_mode_connector_attach_encoder(&connector->base,
15495 * set vga decode state - true == enable VGA decode
15497 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15499 struct drm_i915_private *dev_priv = dev->dev_private;
15500 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15503 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15504 DRM_ERROR("failed to read control word\n");
15508 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15512 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15514 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15516 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15517 DRM_ERROR("failed to write control word\n");
15524 struct intel_display_error_state {
15526 u32 power_well_driver;
15528 int num_transcoders;
15530 struct intel_cursor_error_state {
15535 } cursor[I915_MAX_PIPES];
15537 struct intel_pipe_error_state {
15538 bool power_domain_on;
15541 } pipe[I915_MAX_PIPES];
15543 struct intel_plane_error_state {
15551 } plane[I915_MAX_PIPES];
15553 struct intel_transcoder_error_state {
15554 bool power_domain_on;
15555 enum transcoder cpu_transcoder;
15568 struct intel_display_error_state *
15569 intel_display_capture_error_state(struct drm_device *dev)
15571 struct drm_i915_private *dev_priv = dev->dev_private;
15572 struct intel_display_error_state *error;
15573 int transcoders[] = {
15581 if (INTEL_INFO(dev)->num_pipes == 0)
15584 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15588 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15589 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15591 for_each_pipe(dev_priv, i) {
15592 error->pipe[i].power_domain_on =
15593 __intel_display_power_is_enabled(dev_priv,
15594 POWER_DOMAIN_PIPE(i));
15595 if (!error->pipe[i].power_domain_on)
15598 error->cursor[i].control = I915_READ(CURCNTR(i));
15599 error->cursor[i].position = I915_READ(CURPOS(i));
15600 error->cursor[i].base = I915_READ(CURBASE(i));
15602 error->plane[i].control = I915_READ(DSPCNTR(i));
15603 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15604 if (INTEL_INFO(dev)->gen <= 3) {
15605 error->plane[i].size = I915_READ(DSPSIZE(i));
15606 error->plane[i].pos = I915_READ(DSPPOS(i));
15608 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15609 error->plane[i].addr = I915_READ(DSPADDR(i));
15610 if (INTEL_INFO(dev)->gen >= 4) {
15611 error->plane[i].surface = I915_READ(DSPSURF(i));
15612 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15615 error->pipe[i].source = I915_READ(PIPESRC(i));
15617 if (HAS_GMCH_DISPLAY(dev))
15618 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15621 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15622 if (HAS_DDI(dev_priv->dev))
15623 error->num_transcoders++; /* Account for eDP. */
15625 for (i = 0; i < error->num_transcoders; i++) {
15626 enum transcoder cpu_transcoder = transcoders[i];
15628 error->transcoder[i].power_domain_on =
15629 __intel_display_power_is_enabled(dev_priv,
15630 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15631 if (!error->transcoder[i].power_domain_on)
15634 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15636 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15637 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15638 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15639 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15640 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15641 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15642 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15648 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15651 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15652 struct drm_device *dev,
15653 struct intel_display_error_state *error)
15655 struct drm_i915_private *dev_priv = dev->dev_private;
15661 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15662 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15663 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15664 error->power_well_driver);
15665 for_each_pipe(dev_priv, i) {
15666 err_printf(m, "Pipe [%d]:\n", i);
15667 err_printf(m, " Power: %s\n",
15668 error->pipe[i].power_domain_on ? "on" : "off");
15669 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15670 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15672 err_printf(m, "Plane [%d]:\n", i);
15673 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15674 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15675 if (INTEL_INFO(dev)->gen <= 3) {
15676 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15677 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15679 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15680 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15681 if (INTEL_INFO(dev)->gen >= 4) {
15682 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15683 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15686 err_printf(m, "Cursor [%d]:\n", i);
15687 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15688 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15689 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15692 for (i = 0; i < error->num_transcoders; i++) {
15693 err_printf(m, "CPU transcoder: %c\n",
15694 transcoder_name(error->transcoder[i].cpu_transcoder));
15695 err_printf(m, " Power: %s\n",
15696 error->transcoder[i].power_domain_on ? "on" : "off");
15697 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15698 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15699 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15700 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15701 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15702 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15703 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15707 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15709 struct intel_crtc *crtc;
15711 for_each_intel_crtc(dev, crtc) {
15712 struct intel_unpin_work *work;
15714 spin_lock_irq(&dev->event_lock);
15716 work = crtc->unpin_work;
15718 if (work && work->event &&
15719 work->event->base.file_priv == file) {
15720 kfree(work->event);
15721 work->event = NULL;
15724 spin_unlock_irq(&dev->event_lock);